./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:24:07,298 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:24:07,300 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:24:07,342 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:24:07,343 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:24:07,346 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:24:07,347 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:24:07,350 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:24:07,351 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:24:07,355 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:24:07,356 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:24:07,357 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:24:07,357 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:24:07,360 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:24:07,361 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:24:07,363 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:24:07,364 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:24:07,365 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:24:07,367 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:24:07,372 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:24:07,373 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:24:07,373 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:24:07,375 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:24:07,376 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:24:07,381 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:24:07,382 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:24:07,382 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:24:07,384 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:24:07,384 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:24:07,385 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:24:07,385 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:24:07,386 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:24:07,387 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:24:07,388 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:24:07,389 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:24:07,389 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:24:07,390 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:24:07,390 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:24:07,390 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:24:07,391 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:24:07,391 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:24:07,392 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:24:07,421 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:24:07,421 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:24:07,421 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:24:07,422 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:24:07,423 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:24:07,423 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:24:07,423 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:24:07,423 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:24:07,424 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:24:07,424 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:24:07,425 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:24:07,425 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:24:07,425 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:24:07,425 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:24:07,425 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:24:07,426 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:24:07,426 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:24:07,426 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:24:07,426 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:24:07,426 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:24:07,427 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:24:07,427 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:24:07,427 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:24:07,427 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:24:07,427 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:24:07,428 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:24:07,428 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:24:07,428 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:24:07,428 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:24:07,428 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:24:07,429 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:24:07,429 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:24:07,430 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f [2022-02-21 04:24:07,644 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:24:07,662 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:24:07,664 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:24:07,665 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:24:07,667 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:24:07,668 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.05.cil.c [2022-02-21 04:24:07,729 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5790967e1/a9eeda95326e4f998a1ec4dde7c47d15/FLAG1db3503d4 [2022-02-21 04:24:08,127 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:08,128 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c [2022-02-21 04:24:08,136 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5790967e1/a9eeda95326e4f998a1ec4dde7c47d15/FLAG1db3503d4 [2022-02-21 04:24:08,147 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5790967e1/a9eeda95326e4f998a1ec4dde7c47d15 [2022-02-21 04:24:08,149 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:08,150 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:08,151 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:08,152 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:08,154 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:08,155 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,156 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@a28683a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08, skipping insertion in model container [2022-02-21 04:24:08,156 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,163 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:08,204 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:08,333 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c[706,719] [2022-02-21 04:24:08,393 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:08,401 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:08,410 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c[706,719] [2022-02-21 04:24:08,465 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:08,479 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:08,487 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08 WrapperNode [2022-02-21 04:24:08,487 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:08,488 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:08,489 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:08,489 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:08,494 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,503 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,584 INFO L137 Inliner]: procedures = 38, calls = 45, calls flagged for inlining = 40, calls inlined = 86, statements flattened = 1229 [2022-02-21 04:24:08,585 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:08,585 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:08,586 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:08,586 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:08,593 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,593 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,607 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,608 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,623 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,636 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,640 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,647 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:08,648 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:08,648 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:08,649 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:08,649 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,656 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:08,666 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:08,705 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:08,734 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:08,755 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:08,755 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:08,755 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:08,755 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:08,842 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:08,844 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:09,749 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:09,759 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:09,760 INFO L299 CfgBuilder]: Removed 9 assume(true) statements. [2022-02-21 04:24:09,761 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:09 BoogieIcfgContainer [2022-02-21 04:24:09,761 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:09,762 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:09,762 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:09,765 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:09,766 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:09,766 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:08" (1/3) ... [2022-02-21 04:24:09,767 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6f4bdbbf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:09, skipping insertion in model container [2022-02-21 04:24:09,767 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:09,767 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08" (2/3) ... [2022-02-21 04:24:09,767 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6f4bdbbf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:09, skipping insertion in model container [2022-02-21 04:24:09,768 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:09,768 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:09" (3/3) ... [2022-02-21 04:24:09,769 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2022-02-21 04:24:09,800 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:09,800 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:09,801 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:09,801 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:09,801 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:09,801 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:09,801 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:09,801 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:09,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:09,990 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 424 [2022-02-21 04:24:09,990 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:09,990 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:10,003 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,004 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,004 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:10,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 424 [2022-02-21 04:24:10,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:10,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:10,064 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,065 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,075 INFO L791 eck$LassoCheckResult]: Stem: 490#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 410#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 389#L863true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 385#L394true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 255#L401true assume !(1 == ~m_i~0);~m_st~0 := 2; 343#L401-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 106#L406-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 401#L411-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 384#L416-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 460#L421-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 326#L426-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L586true assume 0 == ~M_E~0;~M_E~0 := 1; 119#L586-2true assume !(0 == ~T1_E~0); 231#L591-1true assume !(0 == ~T2_E~0); 207#L596-1true assume !(0 == ~T3_E~0); 269#L601-1true assume !(0 == ~T4_E~0); 247#L606-1true assume !(0 == ~T5_E~0); 462#L611-1true assume !(0 == ~E_1~0); 341#L616-1true assume !(0 == ~E_2~0); 349#L621-1true assume 0 == ~E_3~0;~E_3~0 := 1; 50#L626-1true assume !(0 == ~E_4~0); 301#L631-1true assume !(0 == ~E_5~0); 140#L636-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48#L279true assume 1 == ~m_pc~0; 215#L280true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 366#L290true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 189#L291true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 268#L720true assume !(0 != activate_threads_~tmp~1#1); 484#L720-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144#L298true assume !(1 == ~t1_pc~0); 26#L298-2true is_transmit1_triggered_~__retres1~1#1 := 0; 451#L309true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 181#L310true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55#L728true assume !(0 != activate_threads_~tmp___0~0#1); 260#L728-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 122#L317true assume 1 == ~t2_pc~0; 238#L318true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 466#L328true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 402#L329true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 150#L736true assume !(0 != activate_threads_~tmp___1~0#1); 421#L736-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 323#L336true assume 1 == ~t3_pc~0; 185#L337true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 485#L347true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 230#L348true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 277#L744true assume !(0 != activate_threads_~tmp___2~0#1); 333#L744-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 405#L355true assume !(1 == ~t4_pc~0); 331#L355-2true is_transmit4_triggered_~__retres1~4#1 := 0; 98#L366true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 258#L367true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 316#L752true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 62#L752-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 369#L374true assume 1 == ~t5_pc~0; 382#L375true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 386#L385true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 188#L386true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 425#L760true assume !(0 != activate_threads_~tmp___4~0#1); 233#L760-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 434#L649true assume 1 == ~M_E~0;~M_E~0 := 2; 493#L649-2true assume !(1 == ~T1_E~0); 41#L654-1true assume !(1 == ~T2_E~0); 265#L659-1true assume !(1 == ~T3_E~0); 149#L664-1true assume !(1 == ~T4_E~0); 37#L669-1true assume !(1 == ~T5_E~0); 318#L674-1true assume !(1 == ~E_1~0); 329#L679-1true assume !(1 == ~E_2~0); 90#L684-1true assume 1 == ~E_3~0;~E_3~0 := 2; 201#L689-1true assume !(1 == ~E_4~0); 480#L694-1true assume !(1 == ~E_5~0); 200#L699-1true assume { :end_inline_reset_delta_events } true; 469#L900-2true [2022-02-21 04:24:10,078 INFO L793 eck$LassoCheckResult]: Loop: 469#L900-2true assume !false; 502#L901true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60#L561true assume !true; 454#L576true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 419#L394-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 422#L586-3true assume 0 == ~M_E~0;~M_E~0 := 1; 317#L586-5true assume !(0 == ~T1_E~0); 217#L591-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 101#L596-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 228#L601-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 372#L606-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 257#L611-3true assume 0 == ~E_1~0;~E_1~0 := 1; 261#L616-3true assume 0 == ~E_2~0;~E_2~0 := 1; 44#L621-3true assume 0 == ~E_3~0;~E_3~0 := 1; 24#L626-3true assume !(0 == ~E_4~0); 503#L631-3true assume 0 == ~E_5~0;~E_5~0 := 1; 28#L636-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 431#L279-18true assume !(1 == ~m_pc~0); 161#L279-20true is_master_triggered_~__retres1~0#1 := 0; 222#L290-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151#L291-6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 391#L720-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 344#L720-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 232#L298-18true assume 1 == ~t1_pc~0; 14#L299-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 105#L309-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 133#L310-6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 117#L728-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 443#L728-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 209#L317-18true assume 1 == ~t2_pc~0; 135#L318-6true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 240#L328-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102#L329-6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 107#L736-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 353#L736-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 348#L336-18true assume !(1 == ~t3_pc~0); 488#L336-20true is_transmit3_triggered_~__retres1~3#1 := 0; 394#L347-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153#L348-6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 174#L744-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74#L744-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 287#L355-18true assume 1 == ~t4_pc~0; 412#L356-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 418#L366-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 123#L367-6true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 213#L752-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126#L752-20true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 332#L374-18true assume 1 == ~t5_pc~0; 458#L375-6true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 171#L385-6true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 288#L386-6true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 445#L760-18true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 271#L760-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 456#L649-3true assume 1 == ~M_E~0;~M_E~0 := 2; 184#L649-5true assume !(1 == ~T1_E~0); 168#L654-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 79#L659-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 450#L664-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 29#L669-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 474#L674-3true assume 1 == ~E_1~0;~E_1~0 := 2; 23#L679-3true assume 1 == ~E_2~0;~E_2~0 := 2; 179#L684-3true assume 1 == ~E_3~0;~E_3~0 := 2; 3#L689-3true assume !(1 == ~E_4~0); 131#L694-3true assume 1 == ~E_5~0;~E_5~0 := 2; 21#L699-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 416#L439-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 473#L471-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 347#L472-1true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 199#L919true assume !(0 == start_simulation_~tmp~3#1); 483#L919-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 299#L439-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 375#L471-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 157#L472-2true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 192#L874true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 352#L881true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 155#L882true start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 328#L932true assume !(0 != start_simulation_~tmp___0~1#1); 469#L900-2true [2022-02-21 04:24:10,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:10,086 INFO L85 PathProgramCache]: Analyzing trace with hash -777385748, now seen corresponding path program 1 times [2022-02-21 04:24:10,097 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:10,097 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744447095] [2022-02-21 04:24:10,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:10,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:10,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:10,241 INFO L290 TraceCheckUtils]: 0: Hoare triple {509#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; {509#true} is VALID [2022-02-21 04:24:10,242 INFO L290 TraceCheckUtils]: 1: Hoare triple {509#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; {511#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:10,242 INFO L290 TraceCheckUtils]: 2: Hoare triple {511#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {511#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:10,243 INFO L290 TraceCheckUtils]: 3: Hoare triple {511#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {511#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:10,243 INFO L290 TraceCheckUtils]: 4: Hoare triple {511#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {510#false} is VALID [2022-02-21 04:24:10,243 INFO L290 TraceCheckUtils]: 5: Hoare triple {510#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {510#false} is VALID [2022-02-21 04:24:10,244 INFO L290 TraceCheckUtils]: 6: Hoare triple {510#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {510#false} is VALID [2022-02-21 04:24:10,244 INFO L290 TraceCheckUtils]: 7: Hoare triple {510#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {510#false} is VALID [2022-02-21 04:24:10,244 INFO L290 TraceCheckUtils]: 8: Hoare triple {510#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {510#false} is VALID [2022-02-21 04:24:10,244 INFO L290 TraceCheckUtils]: 9: Hoare triple {510#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {510#false} is VALID [2022-02-21 04:24:10,245 INFO L290 TraceCheckUtils]: 10: Hoare triple {510#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {510#false} is VALID [2022-02-21 04:24:10,245 INFO L290 TraceCheckUtils]: 11: Hoare triple {510#false} assume 0 == ~M_E~0;~M_E~0 := 1; {510#false} is VALID [2022-02-21 04:24:10,245 INFO L290 TraceCheckUtils]: 12: Hoare triple {510#false} assume !(0 == ~T1_E~0); {510#false} is VALID [2022-02-21 04:24:10,245 INFO L290 TraceCheckUtils]: 13: Hoare triple {510#false} assume !(0 == ~T2_E~0); {510#false} is VALID [2022-02-21 04:24:10,246 INFO L290 TraceCheckUtils]: 14: Hoare triple {510#false} assume !(0 == ~T3_E~0); {510#false} is VALID [2022-02-21 04:24:10,246 INFO L290 TraceCheckUtils]: 15: Hoare triple {510#false} assume !(0 == ~T4_E~0); {510#false} is VALID [2022-02-21 04:24:10,246 INFO L290 TraceCheckUtils]: 16: Hoare triple {510#false} assume !(0 == ~T5_E~0); {510#false} is VALID [2022-02-21 04:24:10,246 INFO L290 TraceCheckUtils]: 17: Hoare triple {510#false} assume !(0 == ~E_1~0); {510#false} is VALID [2022-02-21 04:24:10,246 INFO L290 TraceCheckUtils]: 18: Hoare triple {510#false} assume !(0 == ~E_2~0); {510#false} is VALID [2022-02-21 04:24:10,247 INFO L290 TraceCheckUtils]: 19: Hoare triple {510#false} assume 0 == ~E_3~0;~E_3~0 := 1; {510#false} is VALID [2022-02-21 04:24:10,247 INFO L290 TraceCheckUtils]: 20: Hoare triple {510#false} assume !(0 == ~E_4~0); {510#false} is VALID [2022-02-21 04:24:10,247 INFO L290 TraceCheckUtils]: 21: Hoare triple {510#false} assume !(0 == ~E_5~0); {510#false} is VALID [2022-02-21 04:24:10,247 INFO L290 TraceCheckUtils]: 22: Hoare triple {510#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {510#false} is VALID [2022-02-21 04:24:10,248 INFO L290 TraceCheckUtils]: 23: Hoare triple {510#false} assume 1 == ~m_pc~0; {510#false} is VALID [2022-02-21 04:24:10,248 INFO L290 TraceCheckUtils]: 24: Hoare triple {510#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {510#false} is VALID [2022-02-21 04:24:10,248 INFO L290 TraceCheckUtils]: 25: Hoare triple {510#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {510#false} is VALID [2022-02-21 04:24:10,248 INFO L290 TraceCheckUtils]: 26: Hoare triple {510#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {510#false} is VALID [2022-02-21 04:24:10,249 INFO L290 TraceCheckUtils]: 27: Hoare triple {510#false} assume !(0 != activate_threads_~tmp~1#1); {510#false} is VALID [2022-02-21 04:24:10,249 INFO L290 TraceCheckUtils]: 28: Hoare triple {510#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {510#false} is VALID [2022-02-21 04:24:10,249 INFO L290 TraceCheckUtils]: 29: Hoare triple {510#false} assume !(1 == ~t1_pc~0); {510#false} is VALID [2022-02-21 04:24:10,249 INFO L290 TraceCheckUtils]: 30: Hoare triple {510#false} is_transmit1_triggered_~__retres1~1#1 := 0; {510#false} is VALID [2022-02-21 04:24:10,249 INFO L290 TraceCheckUtils]: 31: Hoare triple {510#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {510#false} is VALID [2022-02-21 04:24:10,250 INFO L290 TraceCheckUtils]: 32: Hoare triple {510#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {510#false} is VALID [2022-02-21 04:24:10,250 INFO L290 TraceCheckUtils]: 33: Hoare triple {510#false} assume !(0 != activate_threads_~tmp___0~0#1); {510#false} is VALID [2022-02-21 04:24:10,250 INFO L290 TraceCheckUtils]: 34: Hoare triple {510#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {510#false} is VALID [2022-02-21 04:24:10,250 INFO L290 TraceCheckUtils]: 35: Hoare triple {510#false} assume 1 == ~t2_pc~0; {510#false} is VALID [2022-02-21 04:24:10,251 INFO L290 TraceCheckUtils]: 36: Hoare triple {510#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {510#false} is VALID [2022-02-21 04:24:10,251 INFO L290 TraceCheckUtils]: 37: Hoare triple {510#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {510#false} is VALID [2022-02-21 04:24:10,251 INFO L290 TraceCheckUtils]: 38: Hoare triple {510#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {510#false} is VALID [2022-02-21 04:24:10,251 INFO L290 TraceCheckUtils]: 39: Hoare triple {510#false} assume !(0 != activate_threads_~tmp___1~0#1); {510#false} is VALID [2022-02-21 04:24:10,252 INFO L290 TraceCheckUtils]: 40: Hoare triple {510#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {510#false} is VALID [2022-02-21 04:24:10,252 INFO L290 TraceCheckUtils]: 41: Hoare triple {510#false} assume 1 == ~t3_pc~0; {510#false} is VALID [2022-02-21 04:24:10,252 INFO L290 TraceCheckUtils]: 42: Hoare triple {510#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {510#false} is VALID [2022-02-21 04:24:10,252 INFO L290 TraceCheckUtils]: 43: Hoare triple {510#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {510#false} is VALID [2022-02-21 04:24:10,252 INFO L290 TraceCheckUtils]: 44: Hoare triple {510#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {510#false} is VALID [2022-02-21 04:24:10,253 INFO L290 TraceCheckUtils]: 45: Hoare triple {510#false} assume !(0 != activate_threads_~tmp___2~0#1); {510#false} is VALID [2022-02-21 04:24:10,253 INFO L290 TraceCheckUtils]: 46: Hoare triple {510#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {510#false} is VALID [2022-02-21 04:24:10,253 INFO L290 TraceCheckUtils]: 47: Hoare triple {510#false} assume !(1 == ~t4_pc~0); {510#false} is VALID [2022-02-21 04:24:10,253 INFO L290 TraceCheckUtils]: 48: Hoare triple {510#false} is_transmit4_triggered_~__retres1~4#1 := 0; {510#false} is VALID [2022-02-21 04:24:10,254 INFO L290 TraceCheckUtils]: 49: Hoare triple {510#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {510#false} is VALID [2022-02-21 04:24:10,254 INFO L290 TraceCheckUtils]: 50: Hoare triple {510#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {510#false} is VALID [2022-02-21 04:24:10,254 INFO L290 TraceCheckUtils]: 51: Hoare triple {510#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {510#false} is VALID [2022-02-21 04:24:10,254 INFO L290 TraceCheckUtils]: 52: Hoare triple {510#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {510#false} is VALID [2022-02-21 04:24:10,255 INFO L290 TraceCheckUtils]: 53: Hoare triple {510#false} assume 1 == ~t5_pc~0; {510#false} is VALID [2022-02-21 04:24:10,255 INFO L290 TraceCheckUtils]: 54: Hoare triple {510#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {510#false} is VALID [2022-02-21 04:24:10,255 INFO L290 TraceCheckUtils]: 55: Hoare triple {510#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {510#false} is VALID [2022-02-21 04:24:10,255 INFO L290 TraceCheckUtils]: 56: Hoare triple {510#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {510#false} is VALID [2022-02-21 04:24:10,255 INFO L290 TraceCheckUtils]: 57: Hoare triple {510#false} assume !(0 != activate_threads_~tmp___4~0#1); {510#false} is VALID [2022-02-21 04:24:10,256 INFO L290 TraceCheckUtils]: 58: Hoare triple {510#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {510#false} is VALID [2022-02-21 04:24:10,256 INFO L290 TraceCheckUtils]: 59: Hoare triple {510#false} assume 1 == ~M_E~0;~M_E~0 := 2; {510#false} is VALID [2022-02-21 04:24:10,256 INFO L290 TraceCheckUtils]: 60: Hoare triple {510#false} assume !(1 == ~T1_E~0); {510#false} is VALID [2022-02-21 04:24:10,256 INFO L290 TraceCheckUtils]: 61: Hoare triple {510#false} assume !(1 == ~T2_E~0); {510#false} is VALID [2022-02-21 04:24:10,257 INFO L290 TraceCheckUtils]: 62: Hoare triple {510#false} assume !(1 == ~T3_E~0); {510#false} is VALID [2022-02-21 04:24:10,257 INFO L290 TraceCheckUtils]: 63: Hoare triple {510#false} assume !(1 == ~T4_E~0); {510#false} is VALID [2022-02-21 04:24:10,257 INFO L290 TraceCheckUtils]: 64: Hoare triple {510#false} assume !(1 == ~T5_E~0); {510#false} is VALID [2022-02-21 04:24:10,257 INFO L290 TraceCheckUtils]: 65: Hoare triple {510#false} assume !(1 == ~E_1~0); {510#false} is VALID [2022-02-21 04:24:10,258 INFO L290 TraceCheckUtils]: 66: Hoare triple {510#false} assume !(1 == ~E_2~0); {510#false} is VALID [2022-02-21 04:24:10,258 INFO L290 TraceCheckUtils]: 67: Hoare triple {510#false} assume 1 == ~E_3~0;~E_3~0 := 2; {510#false} is VALID [2022-02-21 04:24:10,258 INFO L290 TraceCheckUtils]: 68: Hoare triple {510#false} assume !(1 == ~E_4~0); {510#false} is VALID [2022-02-21 04:24:10,258 INFO L290 TraceCheckUtils]: 69: Hoare triple {510#false} assume !(1 == ~E_5~0); {510#false} is VALID [2022-02-21 04:24:10,258 INFO L290 TraceCheckUtils]: 70: Hoare triple {510#false} assume { :end_inline_reset_delta_events } true; {510#false} is VALID [2022-02-21 04:24:10,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:10,260 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:10,260 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744447095] [2022-02-21 04:24:10,261 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744447095] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:10,261 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:10,261 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:10,263 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [847711115] [2022-02-21 04:24:10,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:10,267 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:10,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:10,267 INFO L85 PathProgramCache]: Analyzing trace with hash -129051228, now seen corresponding path program 1 times [2022-02-21 04:24:10,268 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:10,268 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307709237] [2022-02-21 04:24:10,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:10,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:10,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:10,294 INFO L290 TraceCheckUtils]: 0: Hoare triple {512#true} assume !false; {512#true} is VALID [2022-02-21 04:24:10,294 INFO L290 TraceCheckUtils]: 1: Hoare triple {512#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {512#true} is VALID [2022-02-21 04:24:10,295 INFO L290 TraceCheckUtils]: 2: Hoare triple {512#true} assume !true; {513#false} is VALID [2022-02-21 04:24:10,295 INFO L290 TraceCheckUtils]: 3: Hoare triple {513#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {513#false} is VALID [2022-02-21 04:24:10,295 INFO L290 TraceCheckUtils]: 4: Hoare triple {513#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {513#false} is VALID [2022-02-21 04:24:10,296 INFO L290 TraceCheckUtils]: 5: Hoare triple {513#false} assume 0 == ~M_E~0;~M_E~0 := 1; {513#false} is VALID [2022-02-21 04:24:10,296 INFO L290 TraceCheckUtils]: 6: Hoare triple {513#false} assume !(0 == ~T1_E~0); {513#false} is VALID [2022-02-21 04:24:10,296 INFO L290 TraceCheckUtils]: 7: Hoare triple {513#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {513#false} is VALID [2022-02-21 04:24:10,296 INFO L290 TraceCheckUtils]: 8: Hoare triple {513#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {513#false} is VALID [2022-02-21 04:24:10,297 INFO L290 TraceCheckUtils]: 9: Hoare triple {513#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {513#false} is VALID [2022-02-21 04:24:10,297 INFO L290 TraceCheckUtils]: 10: Hoare triple {513#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {513#false} is VALID [2022-02-21 04:24:10,297 INFO L290 TraceCheckUtils]: 11: Hoare triple {513#false} assume 0 == ~E_1~0;~E_1~0 := 1; {513#false} is VALID [2022-02-21 04:24:10,297 INFO L290 TraceCheckUtils]: 12: Hoare triple {513#false} assume 0 == ~E_2~0;~E_2~0 := 1; {513#false} is VALID [2022-02-21 04:24:10,297 INFO L290 TraceCheckUtils]: 13: Hoare triple {513#false} assume 0 == ~E_3~0;~E_3~0 := 1; {513#false} is VALID [2022-02-21 04:24:10,298 INFO L290 TraceCheckUtils]: 14: Hoare triple {513#false} assume !(0 == ~E_4~0); {513#false} is VALID [2022-02-21 04:24:10,298 INFO L290 TraceCheckUtils]: 15: Hoare triple {513#false} assume 0 == ~E_5~0;~E_5~0 := 1; {513#false} is VALID [2022-02-21 04:24:10,298 INFO L290 TraceCheckUtils]: 16: Hoare triple {513#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {513#false} is VALID [2022-02-21 04:24:10,298 INFO L290 TraceCheckUtils]: 17: Hoare triple {513#false} assume !(1 == ~m_pc~0); {513#false} is VALID [2022-02-21 04:24:10,298 INFO L290 TraceCheckUtils]: 18: Hoare triple {513#false} is_master_triggered_~__retres1~0#1 := 0; {513#false} is VALID [2022-02-21 04:24:10,299 INFO L290 TraceCheckUtils]: 19: Hoare triple {513#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {513#false} is VALID [2022-02-21 04:24:10,299 INFO L290 TraceCheckUtils]: 20: Hoare triple {513#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {513#false} is VALID [2022-02-21 04:24:10,299 INFO L290 TraceCheckUtils]: 21: Hoare triple {513#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {513#false} is VALID [2022-02-21 04:24:10,299 INFO L290 TraceCheckUtils]: 22: Hoare triple {513#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {513#false} is VALID [2022-02-21 04:24:10,300 INFO L290 TraceCheckUtils]: 23: Hoare triple {513#false} assume 1 == ~t1_pc~0; {513#false} is VALID [2022-02-21 04:24:10,300 INFO L290 TraceCheckUtils]: 24: Hoare triple {513#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {513#false} is VALID [2022-02-21 04:24:10,300 INFO L290 TraceCheckUtils]: 25: Hoare triple {513#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {513#false} is VALID [2022-02-21 04:24:10,300 INFO L290 TraceCheckUtils]: 26: Hoare triple {513#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {513#false} is VALID [2022-02-21 04:24:10,300 INFO L290 TraceCheckUtils]: 27: Hoare triple {513#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {513#false} is VALID [2022-02-21 04:24:10,301 INFO L290 TraceCheckUtils]: 28: Hoare triple {513#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {513#false} is VALID [2022-02-21 04:24:10,301 INFO L290 TraceCheckUtils]: 29: Hoare triple {513#false} assume 1 == ~t2_pc~0; {513#false} is VALID [2022-02-21 04:24:10,301 INFO L290 TraceCheckUtils]: 30: Hoare triple {513#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {513#false} is VALID [2022-02-21 04:24:10,301 INFO L290 TraceCheckUtils]: 31: Hoare triple {513#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {513#false} is VALID [2022-02-21 04:24:10,302 INFO L290 TraceCheckUtils]: 32: Hoare triple {513#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {513#false} is VALID [2022-02-21 04:24:10,302 INFO L290 TraceCheckUtils]: 33: Hoare triple {513#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {513#false} is VALID [2022-02-21 04:24:10,302 INFO L290 TraceCheckUtils]: 34: Hoare triple {513#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {513#false} is VALID [2022-02-21 04:24:10,302 INFO L290 TraceCheckUtils]: 35: Hoare triple {513#false} assume !(1 == ~t3_pc~0); {513#false} is VALID [2022-02-21 04:24:10,302 INFO L290 TraceCheckUtils]: 36: Hoare triple {513#false} is_transmit3_triggered_~__retres1~3#1 := 0; {513#false} is VALID [2022-02-21 04:24:10,303 INFO L290 TraceCheckUtils]: 37: Hoare triple {513#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {513#false} is VALID [2022-02-21 04:24:10,303 INFO L290 TraceCheckUtils]: 38: Hoare triple {513#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {513#false} is VALID [2022-02-21 04:24:10,303 INFO L290 TraceCheckUtils]: 39: Hoare triple {513#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {513#false} is VALID [2022-02-21 04:24:10,303 INFO L290 TraceCheckUtils]: 40: Hoare triple {513#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {513#false} is VALID [2022-02-21 04:24:10,304 INFO L290 TraceCheckUtils]: 41: Hoare triple {513#false} assume 1 == ~t4_pc~0; {513#false} is VALID [2022-02-21 04:24:10,304 INFO L290 TraceCheckUtils]: 42: Hoare triple {513#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {513#false} is VALID [2022-02-21 04:24:10,304 INFO L290 TraceCheckUtils]: 43: Hoare triple {513#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {513#false} is VALID [2022-02-21 04:24:10,304 INFO L290 TraceCheckUtils]: 44: Hoare triple {513#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {513#false} is VALID [2022-02-21 04:24:10,304 INFO L290 TraceCheckUtils]: 45: Hoare triple {513#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {513#false} is VALID [2022-02-21 04:24:10,305 INFO L290 TraceCheckUtils]: 46: Hoare triple {513#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {513#false} is VALID [2022-02-21 04:24:10,305 INFO L290 TraceCheckUtils]: 47: Hoare triple {513#false} assume 1 == ~t5_pc~0; {513#false} is VALID [2022-02-21 04:24:10,305 INFO L290 TraceCheckUtils]: 48: Hoare triple {513#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {513#false} is VALID [2022-02-21 04:24:10,305 INFO L290 TraceCheckUtils]: 49: Hoare triple {513#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {513#false} is VALID [2022-02-21 04:24:10,306 INFO L290 TraceCheckUtils]: 50: Hoare triple {513#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {513#false} is VALID [2022-02-21 04:24:10,306 INFO L290 TraceCheckUtils]: 51: Hoare triple {513#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {513#false} is VALID [2022-02-21 04:24:10,306 INFO L290 TraceCheckUtils]: 52: Hoare triple {513#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {513#false} is VALID [2022-02-21 04:24:10,306 INFO L290 TraceCheckUtils]: 53: Hoare triple {513#false} assume 1 == ~M_E~0;~M_E~0 := 2; {513#false} is VALID [2022-02-21 04:24:10,306 INFO L290 TraceCheckUtils]: 54: Hoare triple {513#false} assume !(1 == ~T1_E~0); {513#false} is VALID [2022-02-21 04:24:10,307 INFO L290 TraceCheckUtils]: 55: Hoare triple {513#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {513#false} is VALID [2022-02-21 04:24:10,307 INFO L290 TraceCheckUtils]: 56: Hoare triple {513#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {513#false} is VALID [2022-02-21 04:24:10,309 INFO L290 TraceCheckUtils]: 57: Hoare triple {513#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {513#false} is VALID [2022-02-21 04:24:10,309 INFO L290 TraceCheckUtils]: 58: Hoare triple {513#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {513#false} is VALID [2022-02-21 04:24:10,310 INFO L290 TraceCheckUtils]: 59: Hoare triple {513#false} assume 1 == ~E_1~0;~E_1~0 := 2; {513#false} is VALID [2022-02-21 04:24:10,310 INFO L290 TraceCheckUtils]: 60: Hoare triple {513#false} assume 1 == ~E_2~0;~E_2~0 := 2; {513#false} is VALID [2022-02-21 04:24:10,310 INFO L290 TraceCheckUtils]: 61: Hoare triple {513#false} assume 1 == ~E_3~0;~E_3~0 := 2; {513#false} is VALID [2022-02-21 04:24:10,310 INFO L290 TraceCheckUtils]: 62: Hoare triple {513#false} assume !(1 == ~E_4~0); {513#false} is VALID [2022-02-21 04:24:10,310 INFO L290 TraceCheckUtils]: 63: Hoare triple {513#false} assume 1 == ~E_5~0;~E_5~0 := 2; {513#false} is VALID [2022-02-21 04:24:10,311 INFO L290 TraceCheckUtils]: 64: Hoare triple {513#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {513#false} is VALID [2022-02-21 04:24:10,311 INFO L290 TraceCheckUtils]: 65: Hoare triple {513#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {513#false} is VALID [2022-02-21 04:24:10,311 INFO L290 TraceCheckUtils]: 66: Hoare triple {513#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {513#false} is VALID [2022-02-21 04:24:10,311 INFO L290 TraceCheckUtils]: 67: Hoare triple {513#false} start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {513#false} is VALID [2022-02-21 04:24:10,311 INFO L290 TraceCheckUtils]: 68: Hoare triple {513#false} assume !(0 == start_simulation_~tmp~3#1); {513#false} is VALID [2022-02-21 04:24:10,312 INFO L290 TraceCheckUtils]: 69: Hoare triple {513#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {513#false} is VALID [2022-02-21 04:24:10,312 INFO L290 TraceCheckUtils]: 70: Hoare triple {513#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {513#false} is VALID [2022-02-21 04:24:10,312 INFO L290 TraceCheckUtils]: 71: Hoare triple {513#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {513#false} is VALID [2022-02-21 04:24:10,312 INFO L290 TraceCheckUtils]: 72: Hoare triple {513#false} stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; {513#false} is VALID [2022-02-21 04:24:10,313 INFO L290 TraceCheckUtils]: 73: Hoare triple {513#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {513#false} is VALID [2022-02-21 04:24:10,313 INFO L290 TraceCheckUtils]: 74: Hoare triple {513#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {513#false} is VALID [2022-02-21 04:24:10,313 INFO L290 TraceCheckUtils]: 75: Hoare triple {513#false} start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; {513#false} is VALID [2022-02-21 04:24:10,313 INFO L290 TraceCheckUtils]: 76: Hoare triple {513#false} assume !(0 != start_simulation_~tmp___0~1#1); {513#false} is VALID [2022-02-21 04:24:10,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:10,314 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:10,315 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307709237] [2022-02-21 04:24:10,315 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307709237] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:10,315 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:10,315 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:10,315 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734528962] [2022-02-21 04:24:10,316 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:10,317 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:10,318 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:10,340 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:10,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:10,344 INFO L87 Difference]: Start difference. First operand has 505 states, 504 states have (on average 1.5337301587301588) internal successors, (773), 504 states have internal predecessors, (773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:10,953 INFO L93 Difference]: Finished difference Result 504 states and 752 transitions. [2022-02-21 04:24:10,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:10,954 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,015 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:11,019 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 752 transitions. [2022-02-21 04:24:11,037 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-02-21 04:24:11,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 498 states and 746 transitions. [2022-02-21 04:24:11,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-02-21 04:24:11,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-02-21 04:24:11,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 746 transitions. [2022-02-21 04:24:11,062 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:11,062 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 746 transitions. [2022-02-21 04:24:11,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 746 transitions. [2022-02-21 04:24:11,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-02-21 04:24:11,101 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:11,104 INFO L82 GeneralOperation]: Start isEquivalent. First operand 498 states and 746 transitions. Second operand has 498 states, 498 states have (on average 1.497991967871486) internal successors, (746), 497 states have internal predecessors, (746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,108 INFO L74 IsIncluded]: Start isIncluded. First operand 498 states and 746 transitions. Second operand has 498 states, 498 states have (on average 1.497991967871486) internal successors, (746), 497 states have internal predecessors, (746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,116 INFO L87 Difference]: Start difference. First operand 498 states and 746 transitions. Second operand has 498 states, 498 states have (on average 1.497991967871486) internal successors, (746), 497 states have internal predecessors, (746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,141 INFO L93 Difference]: Finished difference Result 498 states and 746 transitions. [2022-02-21 04:24:11,142 INFO L276 IsEmpty]: Start isEmpty. Operand 498 states and 746 transitions. [2022-02-21 04:24:11,148 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:11,148 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:11,150 INFO L74 IsIncluded]: Start isIncluded. First operand has 498 states, 498 states have (on average 1.497991967871486) internal successors, (746), 497 states have internal predecessors, (746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 498 states and 746 transitions. [2022-02-21 04:24:11,155 INFO L87 Difference]: Start difference. First operand has 498 states, 498 states have (on average 1.497991967871486) internal successors, (746), 497 states have internal predecessors, (746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 498 states and 746 transitions. [2022-02-21 04:24:11,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,173 INFO L93 Difference]: Finished difference Result 498 states and 746 transitions. [2022-02-21 04:24:11,173 INFO L276 IsEmpty]: Start isEmpty. Operand 498 states and 746 transitions. [2022-02-21 04:24:11,174 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:11,174 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:11,174 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:11,174 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:11,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.497991967871486) internal successors, (746), 497 states have internal predecessors, (746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 746 transitions. [2022-02-21 04:24:11,193 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 746 transitions. [2022-02-21 04:24:11,193 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 746 transitions. [2022-02-21 04:24:11,193 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:11,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 746 transitions. [2022-02-21 04:24:11,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-02-21 04:24:11,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:11,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:11,198 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:11,198 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:11,198 INFO L791 eck$LassoCheckResult]: Stem: 1515#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1501#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1493#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1491#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1405#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1406#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1211#L406-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1212#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1489#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1490#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1462#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1183#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 1184#L586-2 assume !(0 == ~T1_E~0); 1237#L591-1 assume !(0 == ~T2_E~0); 1357#L596-1 assume !(0 == ~T3_E~0); 1358#L601-1 assume !(0 == ~T4_E~0); 1396#L606-1 assume !(0 == ~T5_E~0); 1397#L611-1 assume !(0 == ~E_1~0); 1468#L616-1 assume !(0 == ~E_2~0); 1469#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1116#L626-1 assume !(0 == ~E_4~0); 1117#L631-1 assume !(0 == ~E_5~0); 1272#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1111#L279 assume 1 == ~m_pc~0; 1112#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1363#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1339#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1340#L720 assume !(0 != activate_threads_~tmp~1#1); 1413#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1276#L298 assume !(1 == ~t1_pc~0); 1068#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1069#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1328#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1125#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1126#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1243#L317 assume 1 == ~t2_pc~0; 1244#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1390#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1497#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1285#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1286#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1460#L336 assume 1 == ~t3_pc~0; 1332#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1333#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1380#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1381#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1421#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1465#L355 assume !(1 == ~t4_pc~0); 1354#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1197#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1198#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1409#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1135#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1136#L374 assume 1 == ~t5_pc~0; 1483#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1264#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1337#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1338#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1383#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1384#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 1506#L649-2 assume !(1 == ~T1_E~0); 1100#L654-1 assume !(1 == ~T2_E~0); 1101#L659-1 assume !(1 == ~T3_E~0); 1284#L664-1 assume !(1 == ~T4_E~0); 1093#L669-1 assume !(1 == ~T5_E~0); 1094#L674-1 assume !(1 == ~E_1~0); 1456#L679-1 assume !(1 == ~E_2~0); 1188#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1189#L689-1 assume !(1 == ~E_4~0); 1351#L694-1 assume !(1 == ~E_5~0); 1349#L699-1 assume { :end_inline_reset_delta_events } true; 1350#L900-2 [2022-02-21 04:24:11,199 INFO L793 eck$LassoCheckResult]: Loop: 1350#L900-2 assume !false; 1513#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1047#L561 assume !false; 1132#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1313#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1070#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1071#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1176#L486 assume !(0 != eval_~tmp~0#1); 1178#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1503#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1504#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1455#L586-5 assume !(0 == ~T1_E~0); 1364#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1202#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1203#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1377#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1407#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1408#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1104#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1065#L626-3 assume !(0 == ~E_4~0); 1066#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1072#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1073#L279-18 assume 1 == ~m_pc~0; 1165#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1166#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1287#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1288#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1471#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1382#L298-18 assume 1 == ~t1_pc~0; 1044#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1038#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1210#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1233#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1234#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1359#L317-18 assume 1 == ~t2_pc~0; 1265#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1267#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1204#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1205#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1213#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1474#L336-18 assume 1 == ~t3_pc~0; 1457#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1458#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1290#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1291#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1157#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1158#L355-18 assume 1 == ~t4_pc~0; 1431#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1420#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1246#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1247#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1253#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1254#L374-18 assume 1 == ~t5_pc~0; 1464#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1318#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1319#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1432#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1414#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1415#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1331#L649-5 assume !(1 == ~T1_E~0); 1312#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1168#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1169#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1074#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1075#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1063#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1064#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1018#L689-3 assume !(1 == ~E_4~0); 1019#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1058#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1059#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1061#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1473#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1348#L919 assume !(0 == start_simulation_~tmp~3#1); 1077#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1444#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1052#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1297#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1298#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1343#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1293#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1294#L932 assume !(0 != start_simulation_~tmp___0~1#1); 1350#L900-2 [2022-02-21 04:24:11,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:11,218 INFO L85 PathProgramCache]: Analyzing trace with hash 438767978, now seen corresponding path program 1 times [2022-02-21 04:24:11,219 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:11,219 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [503028889] [2022-02-21 04:24:11,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:11,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:11,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:11,264 INFO L290 TraceCheckUtils]: 0: Hoare triple {2515#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; {2515#true} is VALID [2022-02-21 04:24:11,265 INFO L290 TraceCheckUtils]: 1: Hoare triple {2515#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; {2517#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:11,265 INFO L290 TraceCheckUtils]: 2: Hoare triple {2517#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {2517#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:11,266 INFO L290 TraceCheckUtils]: 3: Hoare triple {2517#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {2517#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:11,266 INFO L290 TraceCheckUtils]: 4: Hoare triple {2517#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {2517#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:11,266 INFO L290 TraceCheckUtils]: 5: Hoare triple {2517#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {2517#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:11,267 INFO L290 TraceCheckUtils]: 6: Hoare triple {2517#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {2516#false} is VALID [2022-02-21 04:24:11,267 INFO L290 TraceCheckUtils]: 7: Hoare triple {2516#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {2516#false} is VALID [2022-02-21 04:24:11,267 INFO L290 TraceCheckUtils]: 8: Hoare triple {2516#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {2516#false} is VALID [2022-02-21 04:24:11,268 INFO L290 TraceCheckUtils]: 9: Hoare triple {2516#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {2516#false} is VALID [2022-02-21 04:24:11,268 INFO L290 TraceCheckUtils]: 10: Hoare triple {2516#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {2516#false} is VALID [2022-02-21 04:24:11,268 INFO L290 TraceCheckUtils]: 11: Hoare triple {2516#false} assume 0 == ~M_E~0;~M_E~0 := 1; {2516#false} is VALID [2022-02-21 04:24:11,268 INFO L290 TraceCheckUtils]: 12: Hoare triple {2516#false} assume !(0 == ~T1_E~0); {2516#false} is VALID [2022-02-21 04:24:11,268 INFO L290 TraceCheckUtils]: 13: Hoare triple {2516#false} assume !(0 == ~T2_E~0); {2516#false} is VALID [2022-02-21 04:24:11,269 INFO L290 TraceCheckUtils]: 14: Hoare triple {2516#false} assume !(0 == ~T3_E~0); {2516#false} is VALID [2022-02-21 04:24:11,269 INFO L290 TraceCheckUtils]: 15: Hoare triple {2516#false} assume !(0 == ~T4_E~0); {2516#false} is VALID [2022-02-21 04:24:11,269 INFO L290 TraceCheckUtils]: 16: Hoare triple {2516#false} assume !(0 == ~T5_E~0); {2516#false} is VALID [2022-02-21 04:24:11,269 INFO L290 TraceCheckUtils]: 17: Hoare triple {2516#false} assume !(0 == ~E_1~0); {2516#false} is VALID [2022-02-21 04:24:11,270 INFO L290 TraceCheckUtils]: 18: Hoare triple {2516#false} assume !(0 == ~E_2~0); {2516#false} is VALID [2022-02-21 04:24:11,270 INFO L290 TraceCheckUtils]: 19: Hoare triple {2516#false} assume 0 == ~E_3~0;~E_3~0 := 1; {2516#false} is VALID [2022-02-21 04:24:11,270 INFO L290 TraceCheckUtils]: 20: Hoare triple {2516#false} assume !(0 == ~E_4~0); {2516#false} is VALID [2022-02-21 04:24:11,270 INFO L290 TraceCheckUtils]: 21: Hoare triple {2516#false} assume !(0 == ~E_5~0); {2516#false} is VALID [2022-02-21 04:24:11,270 INFO L290 TraceCheckUtils]: 22: Hoare triple {2516#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2516#false} is VALID [2022-02-21 04:24:11,271 INFO L290 TraceCheckUtils]: 23: Hoare triple {2516#false} assume 1 == ~m_pc~0; {2516#false} is VALID [2022-02-21 04:24:11,271 INFO L290 TraceCheckUtils]: 24: Hoare triple {2516#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {2516#false} is VALID [2022-02-21 04:24:11,271 INFO L290 TraceCheckUtils]: 25: Hoare triple {2516#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2516#false} is VALID [2022-02-21 04:24:11,271 INFO L290 TraceCheckUtils]: 26: Hoare triple {2516#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {2516#false} is VALID [2022-02-21 04:24:11,272 INFO L290 TraceCheckUtils]: 27: Hoare triple {2516#false} assume !(0 != activate_threads_~tmp~1#1); {2516#false} is VALID [2022-02-21 04:24:11,272 INFO L290 TraceCheckUtils]: 28: Hoare triple {2516#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2516#false} is VALID [2022-02-21 04:24:11,272 INFO L290 TraceCheckUtils]: 29: Hoare triple {2516#false} assume !(1 == ~t1_pc~0); {2516#false} is VALID [2022-02-21 04:24:11,272 INFO L290 TraceCheckUtils]: 30: Hoare triple {2516#false} is_transmit1_triggered_~__retres1~1#1 := 0; {2516#false} is VALID [2022-02-21 04:24:11,273 INFO L290 TraceCheckUtils]: 31: Hoare triple {2516#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2516#false} is VALID [2022-02-21 04:24:11,273 INFO L290 TraceCheckUtils]: 32: Hoare triple {2516#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {2516#false} is VALID [2022-02-21 04:24:11,273 INFO L290 TraceCheckUtils]: 33: Hoare triple {2516#false} assume !(0 != activate_threads_~tmp___0~0#1); {2516#false} is VALID [2022-02-21 04:24:11,273 INFO L290 TraceCheckUtils]: 34: Hoare triple {2516#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2516#false} is VALID [2022-02-21 04:24:11,274 INFO L290 TraceCheckUtils]: 35: Hoare triple {2516#false} assume 1 == ~t2_pc~0; {2516#false} is VALID [2022-02-21 04:24:11,274 INFO L290 TraceCheckUtils]: 36: Hoare triple {2516#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2516#false} is VALID [2022-02-21 04:24:11,274 INFO L290 TraceCheckUtils]: 37: Hoare triple {2516#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2516#false} is VALID [2022-02-21 04:24:11,274 INFO L290 TraceCheckUtils]: 38: Hoare triple {2516#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {2516#false} is VALID [2022-02-21 04:24:11,274 INFO L290 TraceCheckUtils]: 39: Hoare triple {2516#false} assume !(0 != activate_threads_~tmp___1~0#1); {2516#false} is VALID [2022-02-21 04:24:11,275 INFO L290 TraceCheckUtils]: 40: Hoare triple {2516#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2516#false} is VALID [2022-02-21 04:24:11,275 INFO L290 TraceCheckUtils]: 41: Hoare triple {2516#false} assume 1 == ~t3_pc~0; {2516#false} is VALID [2022-02-21 04:24:11,275 INFO L290 TraceCheckUtils]: 42: Hoare triple {2516#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {2516#false} is VALID [2022-02-21 04:24:11,275 INFO L290 TraceCheckUtils]: 43: Hoare triple {2516#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2516#false} is VALID [2022-02-21 04:24:11,276 INFO L290 TraceCheckUtils]: 44: Hoare triple {2516#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {2516#false} is VALID [2022-02-21 04:24:11,276 INFO L290 TraceCheckUtils]: 45: Hoare triple {2516#false} assume !(0 != activate_threads_~tmp___2~0#1); {2516#false} is VALID [2022-02-21 04:24:11,276 INFO L290 TraceCheckUtils]: 46: Hoare triple {2516#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2516#false} is VALID [2022-02-21 04:24:11,276 INFO L290 TraceCheckUtils]: 47: Hoare triple {2516#false} assume !(1 == ~t4_pc~0); {2516#false} is VALID [2022-02-21 04:24:11,276 INFO L290 TraceCheckUtils]: 48: Hoare triple {2516#false} is_transmit4_triggered_~__retres1~4#1 := 0; {2516#false} is VALID [2022-02-21 04:24:11,277 INFO L290 TraceCheckUtils]: 49: Hoare triple {2516#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2516#false} is VALID [2022-02-21 04:24:11,277 INFO L290 TraceCheckUtils]: 50: Hoare triple {2516#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {2516#false} is VALID [2022-02-21 04:24:11,277 INFO L290 TraceCheckUtils]: 51: Hoare triple {2516#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {2516#false} is VALID [2022-02-21 04:24:11,277 INFO L290 TraceCheckUtils]: 52: Hoare triple {2516#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {2516#false} is VALID [2022-02-21 04:24:11,278 INFO L290 TraceCheckUtils]: 53: Hoare triple {2516#false} assume 1 == ~t5_pc~0; {2516#false} is VALID [2022-02-21 04:24:11,278 INFO L290 TraceCheckUtils]: 54: Hoare triple {2516#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {2516#false} is VALID [2022-02-21 04:24:11,278 INFO L290 TraceCheckUtils]: 55: Hoare triple {2516#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {2516#false} is VALID [2022-02-21 04:24:11,278 INFO L290 TraceCheckUtils]: 56: Hoare triple {2516#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {2516#false} is VALID [2022-02-21 04:24:11,278 INFO L290 TraceCheckUtils]: 57: Hoare triple {2516#false} assume !(0 != activate_threads_~tmp___4~0#1); {2516#false} is VALID [2022-02-21 04:24:11,279 INFO L290 TraceCheckUtils]: 58: Hoare triple {2516#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2516#false} is VALID [2022-02-21 04:24:11,279 INFO L290 TraceCheckUtils]: 59: Hoare triple {2516#false} assume 1 == ~M_E~0;~M_E~0 := 2; {2516#false} is VALID [2022-02-21 04:24:11,279 INFO L290 TraceCheckUtils]: 60: Hoare triple {2516#false} assume !(1 == ~T1_E~0); {2516#false} is VALID [2022-02-21 04:24:11,279 INFO L290 TraceCheckUtils]: 61: Hoare triple {2516#false} assume !(1 == ~T2_E~0); {2516#false} is VALID [2022-02-21 04:24:11,280 INFO L290 TraceCheckUtils]: 62: Hoare triple {2516#false} assume !(1 == ~T3_E~0); {2516#false} is VALID [2022-02-21 04:24:11,280 INFO L290 TraceCheckUtils]: 63: Hoare triple {2516#false} assume !(1 == ~T4_E~0); {2516#false} is VALID [2022-02-21 04:24:11,280 INFO L290 TraceCheckUtils]: 64: Hoare triple {2516#false} assume !(1 == ~T5_E~0); {2516#false} is VALID [2022-02-21 04:24:11,280 INFO L290 TraceCheckUtils]: 65: Hoare triple {2516#false} assume !(1 == ~E_1~0); {2516#false} is VALID [2022-02-21 04:24:11,281 INFO L290 TraceCheckUtils]: 66: Hoare triple {2516#false} assume !(1 == ~E_2~0); {2516#false} is VALID [2022-02-21 04:24:11,281 INFO L290 TraceCheckUtils]: 67: Hoare triple {2516#false} assume 1 == ~E_3~0;~E_3~0 := 2; {2516#false} is VALID [2022-02-21 04:24:11,281 INFO L290 TraceCheckUtils]: 68: Hoare triple {2516#false} assume !(1 == ~E_4~0); {2516#false} is VALID [2022-02-21 04:24:11,281 INFO L290 TraceCheckUtils]: 69: Hoare triple {2516#false} assume !(1 == ~E_5~0); {2516#false} is VALID [2022-02-21 04:24:11,281 INFO L290 TraceCheckUtils]: 70: Hoare triple {2516#false} assume { :end_inline_reset_delta_events } true; {2516#false} is VALID [2022-02-21 04:24:11,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:11,282 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:11,283 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [503028889] [2022-02-21 04:24:11,283 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [503028889] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:11,290 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:11,290 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:11,291 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1290202227] [2022-02-21 04:24:11,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:11,291 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:11,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:11,292 INFO L85 PathProgramCache]: Analyzing trace with hash -1476238801, now seen corresponding path program 1 times [2022-02-21 04:24:11,292 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:11,292 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [245244090] [2022-02-21 04:24:11,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:11,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:11,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:11,370 INFO L290 TraceCheckUtils]: 0: Hoare triple {2518#true} assume !false; {2518#true} is VALID [2022-02-21 04:24:11,371 INFO L290 TraceCheckUtils]: 1: Hoare triple {2518#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {2518#true} is VALID [2022-02-21 04:24:11,371 INFO L290 TraceCheckUtils]: 2: Hoare triple {2518#true} assume !false; {2518#true} is VALID [2022-02-21 04:24:11,371 INFO L290 TraceCheckUtils]: 3: Hoare triple {2518#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {2518#true} is VALID [2022-02-21 04:24:11,372 INFO L290 TraceCheckUtils]: 4: Hoare triple {2518#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {2518#true} is VALID [2022-02-21 04:24:11,372 INFO L290 TraceCheckUtils]: 5: Hoare triple {2518#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {2518#true} is VALID [2022-02-21 04:24:11,372 INFO L290 TraceCheckUtils]: 6: Hoare triple {2518#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {2518#true} is VALID [2022-02-21 04:24:11,372 INFO L290 TraceCheckUtils]: 7: Hoare triple {2518#true} assume !(0 != eval_~tmp~0#1); {2518#true} is VALID [2022-02-21 04:24:11,372 INFO L290 TraceCheckUtils]: 8: Hoare triple {2518#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {2518#true} is VALID [2022-02-21 04:24:11,373 INFO L290 TraceCheckUtils]: 9: Hoare triple {2518#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {2518#true} is VALID [2022-02-21 04:24:11,373 INFO L290 TraceCheckUtils]: 10: Hoare triple {2518#true} assume 0 == ~M_E~0;~M_E~0 := 1; {2518#true} is VALID [2022-02-21 04:24:11,373 INFO L290 TraceCheckUtils]: 11: Hoare triple {2518#true} assume !(0 == ~T1_E~0); {2518#true} is VALID [2022-02-21 04:24:11,373 INFO L290 TraceCheckUtils]: 12: Hoare triple {2518#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {2518#true} is VALID [2022-02-21 04:24:11,374 INFO L290 TraceCheckUtils]: 13: Hoare triple {2518#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {2518#true} is VALID [2022-02-21 04:24:11,374 INFO L290 TraceCheckUtils]: 14: Hoare triple {2518#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {2518#true} is VALID [2022-02-21 04:24:11,374 INFO L290 TraceCheckUtils]: 15: Hoare triple {2518#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {2518#true} is VALID [2022-02-21 04:24:11,374 INFO L290 TraceCheckUtils]: 16: Hoare triple {2518#true} assume 0 == ~E_1~0;~E_1~0 := 1; {2518#true} is VALID [2022-02-21 04:24:11,374 INFO L290 TraceCheckUtils]: 17: Hoare triple {2518#true} assume 0 == ~E_2~0;~E_2~0 := 1; {2518#true} is VALID [2022-02-21 04:24:11,375 INFO L290 TraceCheckUtils]: 18: Hoare triple {2518#true} assume 0 == ~E_3~0;~E_3~0 := 1; {2518#true} is VALID [2022-02-21 04:24:11,375 INFO L290 TraceCheckUtils]: 19: Hoare triple {2518#true} assume !(0 == ~E_4~0); {2518#true} is VALID [2022-02-21 04:24:11,375 INFO L290 TraceCheckUtils]: 20: Hoare triple {2518#true} assume 0 == ~E_5~0;~E_5~0 := 1; {2518#true} is VALID [2022-02-21 04:24:11,375 INFO L290 TraceCheckUtils]: 21: Hoare triple {2518#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2518#true} is VALID [2022-02-21 04:24:11,376 INFO L290 TraceCheckUtils]: 22: Hoare triple {2518#true} assume 1 == ~m_pc~0; {2518#true} is VALID [2022-02-21 04:24:11,376 INFO L290 TraceCheckUtils]: 23: Hoare triple {2518#true} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {2518#true} is VALID [2022-02-21 04:24:11,376 INFO L290 TraceCheckUtils]: 24: Hoare triple {2518#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2518#true} is VALID [2022-02-21 04:24:11,376 INFO L290 TraceCheckUtils]: 25: Hoare triple {2518#true} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {2518#true} is VALID [2022-02-21 04:24:11,376 INFO L290 TraceCheckUtils]: 26: Hoare triple {2518#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {2518#true} is VALID [2022-02-21 04:24:11,377 INFO L290 TraceCheckUtils]: 27: Hoare triple {2518#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2518#true} is VALID [2022-02-21 04:24:11,377 INFO L290 TraceCheckUtils]: 28: Hoare triple {2518#true} assume 1 == ~t1_pc~0; {2518#true} is VALID [2022-02-21 04:24:11,377 INFO L290 TraceCheckUtils]: 29: Hoare triple {2518#true} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {2518#true} is VALID [2022-02-21 04:24:11,377 INFO L290 TraceCheckUtils]: 30: Hoare triple {2518#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2518#true} is VALID [2022-02-21 04:24:11,377 INFO L290 TraceCheckUtils]: 31: Hoare triple {2518#true} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {2518#true} is VALID [2022-02-21 04:24:11,378 INFO L290 TraceCheckUtils]: 32: Hoare triple {2518#true} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {2518#true} is VALID [2022-02-21 04:24:11,378 INFO L290 TraceCheckUtils]: 33: Hoare triple {2518#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2518#true} is VALID [2022-02-21 04:24:11,378 INFO L290 TraceCheckUtils]: 34: Hoare triple {2518#true} assume 1 == ~t2_pc~0; {2518#true} is VALID [2022-02-21 04:24:11,378 INFO L290 TraceCheckUtils]: 35: Hoare triple {2518#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2518#true} is VALID [2022-02-21 04:24:11,379 INFO L290 TraceCheckUtils]: 36: Hoare triple {2518#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2518#true} is VALID [2022-02-21 04:24:11,379 INFO L290 TraceCheckUtils]: 37: Hoare triple {2518#true} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {2518#true} is VALID [2022-02-21 04:24:11,379 INFO L290 TraceCheckUtils]: 38: Hoare triple {2518#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {2518#true} is VALID [2022-02-21 04:24:11,379 INFO L290 TraceCheckUtils]: 39: Hoare triple {2518#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2518#true} is VALID [2022-02-21 04:24:11,379 INFO L290 TraceCheckUtils]: 40: Hoare triple {2518#true} assume 1 == ~t3_pc~0; {2518#true} is VALID [2022-02-21 04:24:11,380 INFO L290 TraceCheckUtils]: 41: Hoare triple {2518#true} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {2518#true} is VALID [2022-02-21 04:24:11,380 INFO L290 TraceCheckUtils]: 42: Hoare triple {2518#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2518#true} is VALID [2022-02-21 04:24:11,380 INFO L290 TraceCheckUtils]: 43: Hoare triple {2518#true} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {2518#true} is VALID [2022-02-21 04:24:11,380 INFO L290 TraceCheckUtils]: 44: Hoare triple {2518#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {2518#true} is VALID [2022-02-21 04:24:11,380 INFO L290 TraceCheckUtils]: 45: Hoare triple {2518#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2518#true} is VALID [2022-02-21 04:24:11,381 INFO L290 TraceCheckUtils]: 46: Hoare triple {2518#true} assume 1 == ~t4_pc~0; {2518#true} is VALID [2022-02-21 04:24:11,381 INFO L290 TraceCheckUtils]: 47: Hoare triple {2518#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,382 INFO L290 TraceCheckUtils]: 48: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,382 INFO L290 TraceCheckUtils]: 49: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,383 INFO L290 TraceCheckUtils]: 50: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,383 INFO L290 TraceCheckUtils]: 51: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,384 INFO L290 TraceCheckUtils]: 52: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~t5_pc~0; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,384 INFO L290 TraceCheckUtils]: 53: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,384 INFO L290 TraceCheckUtils]: 54: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,385 INFO L290 TraceCheckUtils]: 55: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,385 INFO L290 TraceCheckUtils]: 56: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,386 INFO L290 TraceCheckUtils]: 57: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,386 INFO L290 TraceCheckUtils]: 58: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,386 INFO L290 TraceCheckUtils]: 59: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~T1_E~0); {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,387 INFO L290 TraceCheckUtils]: 60: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,388 INFO L290 TraceCheckUtils]: 61: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,388 INFO L290 TraceCheckUtils]: 62: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,389 INFO L290 TraceCheckUtils]: 63: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,389 INFO L290 TraceCheckUtils]: 64: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,389 INFO L290 TraceCheckUtils]: 65: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,390 INFO L290 TraceCheckUtils]: 66: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {2520#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:11,390 INFO L290 TraceCheckUtils]: 67: Hoare triple {2520#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~E_4~0); {2519#false} is VALID [2022-02-21 04:24:11,391 INFO L290 TraceCheckUtils]: 68: Hoare triple {2519#false} assume 1 == ~E_5~0;~E_5~0 := 2; {2519#false} is VALID [2022-02-21 04:24:11,391 INFO L290 TraceCheckUtils]: 69: Hoare triple {2519#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {2519#false} is VALID [2022-02-21 04:24:11,391 INFO L290 TraceCheckUtils]: 70: Hoare triple {2519#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {2519#false} is VALID [2022-02-21 04:24:11,391 INFO L290 TraceCheckUtils]: 71: Hoare triple {2519#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {2519#false} is VALID [2022-02-21 04:24:11,391 INFO L290 TraceCheckUtils]: 72: Hoare triple {2519#false} start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {2519#false} is VALID [2022-02-21 04:24:11,392 INFO L290 TraceCheckUtils]: 73: Hoare triple {2519#false} assume !(0 == start_simulation_~tmp~3#1); {2519#false} is VALID [2022-02-21 04:24:11,392 INFO L290 TraceCheckUtils]: 74: Hoare triple {2519#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {2519#false} is VALID [2022-02-21 04:24:11,392 INFO L290 TraceCheckUtils]: 75: Hoare triple {2519#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {2519#false} is VALID [2022-02-21 04:24:11,392 INFO L290 TraceCheckUtils]: 76: Hoare triple {2519#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {2519#false} is VALID [2022-02-21 04:24:11,392 INFO L290 TraceCheckUtils]: 77: Hoare triple {2519#false} stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; {2519#false} is VALID [2022-02-21 04:24:11,393 INFO L290 TraceCheckUtils]: 78: Hoare triple {2519#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {2519#false} is VALID [2022-02-21 04:24:11,393 INFO L290 TraceCheckUtils]: 79: Hoare triple {2519#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {2519#false} is VALID [2022-02-21 04:24:11,393 INFO L290 TraceCheckUtils]: 80: Hoare triple {2519#false} start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; {2519#false} is VALID [2022-02-21 04:24:11,393 INFO L290 TraceCheckUtils]: 81: Hoare triple {2519#false} assume !(0 != start_simulation_~tmp___0~1#1); {2519#false} is VALID [2022-02-21 04:24:11,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:11,394 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:11,394 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [245244090] [2022-02-21 04:24:11,395 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [245244090] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:11,395 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:11,395 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:11,395 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1994238201] [2022-02-21 04:24:11,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:11,396 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:11,396 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:11,397 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:11,397 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:11,397 INFO L87 Difference]: Start difference. First operand 498 states and 746 transitions. cyclomatic complexity: 249 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,857 INFO L93 Difference]: Finished difference Result 498 states and 745 transitions. [2022-02-21 04:24:11,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:11,858 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,919 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:11,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 745 transitions. [2022-02-21 04:24:11,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-02-21 04:24:11,964 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 745 transitions. [2022-02-21 04:24:11,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-02-21 04:24:11,965 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-02-21 04:24:11,965 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 745 transitions. [2022-02-21 04:24:11,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:11,966 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 745 transitions. [2022-02-21 04:24:11,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 745 transitions. [2022-02-21 04:24:11,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-02-21 04:24:11,976 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:11,978 INFO L82 GeneralOperation]: Start isEquivalent. First operand 498 states and 745 transitions. Second operand has 498 states, 498 states have (on average 1.4959839357429718) internal successors, (745), 497 states have internal predecessors, (745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,979 INFO L74 IsIncluded]: Start isIncluded. First operand 498 states and 745 transitions. Second operand has 498 states, 498 states have (on average 1.4959839357429718) internal successors, (745), 497 states have internal predecessors, (745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,980 INFO L87 Difference]: Start difference. First operand 498 states and 745 transitions. Second operand has 498 states, 498 states have (on average 1.4959839357429718) internal successors, (745), 497 states have internal predecessors, (745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,992 INFO L93 Difference]: Finished difference Result 498 states and 745 transitions. [2022-02-21 04:24:11,992 INFO L276 IsEmpty]: Start isEmpty. Operand 498 states and 745 transitions. [2022-02-21 04:24:11,993 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:11,993 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:11,994 INFO L74 IsIncluded]: Start isIncluded. First operand has 498 states, 498 states have (on average 1.4959839357429718) internal successors, (745), 497 states have internal predecessors, (745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 498 states and 745 transitions. [2022-02-21 04:24:11,995 INFO L87 Difference]: Start difference. First operand has 498 states, 498 states have (on average 1.4959839357429718) internal successors, (745), 497 states have internal predecessors, (745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 498 states and 745 transitions. [2022-02-21 04:24:12,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:12,008 INFO L93 Difference]: Finished difference Result 498 states and 745 transitions. [2022-02-21 04:24:12,008 INFO L276 IsEmpty]: Start isEmpty. Operand 498 states and 745 transitions. [2022-02-21 04:24:12,009 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:12,009 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:12,009 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:12,010 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:12,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4959839357429718) internal successors, (745), 497 states have internal predecessors, (745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 745 transitions. [2022-02-21 04:24:12,023 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 745 transitions. [2022-02-21 04:24:12,023 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 745 transitions. [2022-02-21 04:24:12,023 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:12,023 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 745 transitions. [2022-02-21 04:24:12,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-02-21 04:24:12,026 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:12,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:12,027 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:12,027 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:12,028 INFO L791 eck$LassoCheckResult]: Stem: 3516#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3502#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3494#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3492#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3406#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 3407#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3212#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3213#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3490#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3491#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3463#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3184#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 3185#L586-2 assume !(0 == ~T1_E~0); 3238#L591-1 assume !(0 == ~T2_E~0); 3358#L596-1 assume !(0 == ~T3_E~0); 3359#L601-1 assume !(0 == ~T4_E~0); 3397#L606-1 assume !(0 == ~T5_E~0); 3398#L611-1 assume !(0 == ~E_1~0); 3469#L616-1 assume !(0 == ~E_2~0); 3470#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3117#L626-1 assume !(0 == ~E_4~0); 3118#L631-1 assume !(0 == ~E_5~0); 3273#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3112#L279 assume 1 == ~m_pc~0; 3113#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3364#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3340#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3341#L720 assume !(0 != activate_threads_~tmp~1#1); 3414#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3277#L298 assume !(1 == ~t1_pc~0); 3069#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3070#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3329#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3126#L728 assume !(0 != activate_threads_~tmp___0~0#1); 3127#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3244#L317 assume 1 == ~t2_pc~0; 3245#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3391#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3498#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3286#L736 assume !(0 != activate_threads_~tmp___1~0#1); 3287#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3461#L336 assume 1 == ~t3_pc~0; 3333#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3334#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3381#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3382#L744 assume !(0 != activate_threads_~tmp___2~0#1); 3422#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3466#L355 assume !(1 == ~t4_pc~0); 3355#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3198#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3199#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3410#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3136#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3137#L374 assume 1 == ~t5_pc~0; 3484#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3265#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3338#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3339#L760 assume !(0 != activate_threads_~tmp___4~0#1); 3384#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3385#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 3507#L649-2 assume !(1 == ~T1_E~0); 3101#L654-1 assume !(1 == ~T2_E~0); 3102#L659-1 assume !(1 == ~T3_E~0); 3285#L664-1 assume !(1 == ~T4_E~0); 3094#L669-1 assume !(1 == ~T5_E~0); 3095#L674-1 assume !(1 == ~E_1~0); 3457#L679-1 assume !(1 == ~E_2~0); 3189#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3190#L689-1 assume !(1 == ~E_4~0); 3352#L694-1 assume !(1 == ~E_5~0); 3350#L699-1 assume { :end_inline_reset_delta_events } true; 3351#L900-2 [2022-02-21 04:24:12,028 INFO L793 eck$LassoCheckResult]: Loop: 3351#L900-2 assume !false; 3514#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3048#L561 assume !false; 3133#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3314#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3071#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3072#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3177#L486 assume !(0 != eval_~tmp~0#1); 3179#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3504#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3505#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3456#L586-5 assume !(0 == ~T1_E~0); 3365#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3203#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3204#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3378#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3408#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3409#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3105#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3066#L626-3 assume !(0 == ~E_4~0); 3067#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3073#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3074#L279-18 assume !(1 == ~m_pc~0); 3168#L279-20 is_master_triggered_~__retres1~0#1 := 0; 3167#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3288#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3289#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3472#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3383#L298-18 assume 1 == ~t1_pc~0; 3045#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3039#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3211#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3234#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3235#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3360#L317-18 assume 1 == ~t2_pc~0; 3266#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3268#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3205#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3206#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3214#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3475#L336-18 assume 1 == ~t3_pc~0; 3458#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3459#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3291#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3292#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3158#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3159#L355-18 assume 1 == ~t4_pc~0; 3432#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3421#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3247#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3248#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3254#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3255#L374-18 assume 1 == ~t5_pc~0; 3465#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3319#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3320#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3433#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3415#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3416#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3332#L649-5 assume !(1 == ~T1_E~0); 3313#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3169#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3170#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3075#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3076#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3064#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3065#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3019#L689-3 assume !(1 == ~E_4~0); 3020#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3059#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3060#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3062#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3474#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3349#L919 assume !(0 == start_simulation_~tmp~3#1); 3078#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3445#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3053#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3298#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3299#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3344#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3294#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3295#L932 assume !(0 != start_simulation_~tmp___0~1#1); 3351#L900-2 [2022-02-21 04:24:12,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:12,029 INFO L85 PathProgramCache]: Analyzing trace with hash 2124947816, now seen corresponding path program 1 times [2022-02-21 04:24:12,029 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:12,029 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552618060] [2022-02-21 04:24:12,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:12,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:12,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:12,064 INFO L290 TraceCheckUtils]: 0: Hoare triple {4516#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; {4516#true} is VALID [2022-02-21 04:24:12,065 INFO L290 TraceCheckUtils]: 1: Hoare triple {4516#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; {4518#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,065 INFO L290 TraceCheckUtils]: 2: Hoare triple {4518#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {4518#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,066 INFO L290 TraceCheckUtils]: 3: Hoare triple {4518#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {4518#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,066 INFO L290 TraceCheckUtils]: 4: Hoare triple {4518#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {4518#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,066 INFO L290 TraceCheckUtils]: 5: Hoare triple {4518#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {4518#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,067 INFO L290 TraceCheckUtils]: 6: Hoare triple {4518#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {4518#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,067 INFO L290 TraceCheckUtils]: 7: Hoare triple {4518#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {4517#false} is VALID [2022-02-21 04:24:12,067 INFO L290 TraceCheckUtils]: 8: Hoare triple {4517#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {4517#false} is VALID [2022-02-21 04:24:12,068 INFO L290 TraceCheckUtils]: 9: Hoare triple {4517#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {4517#false} is VALID [2022-02-21 04:24:12,068 INFO L290 TraceCheckUtils]: 10: Hoare triple {4517#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {4517#false} is VALID [2022-02-21 04:24:12,068 INFO L290 TraceCheckUtils]: 11: Hoare triple {4517#false} assume 0 == ~M_E~0;~M_E~0 := 1; {4517#false} is VALID [2022-02-21 04:24:12,068 INFO L290 TraceCheckUtils]: 12: Hoare triple {4517#false} assume !(0 == ~T1_E~0); {4517#false} is VALID [2022-02-21 04:24:12,068 INFO L290 TraceCheckUtils]: 13: Hoare triple {4517#false} assume !(0 == ~T2_E~0); {4517#false} is VALID [2022-02-21 04:24:12,068 INFO L290 TraceCheckUtils]: 14: Hoare triple {4517#false} assume !(0 == ~T3_E~0); {4517#false} is VALID [2022-02-21 04:24:12,069 INFO L290 TraceCheckUtils]: 15: Hoare triple {4517#false} assume !(0 == ~T4_E~0); {4517#false} is VALID [2022-02-21 04:24:12,069 INFO L290 TraceCheckUtils]: 16: Hoare triple {4517#false} assume !(0 == ~T5_E~0); {4517#false} is VALID [2022-02-21 04:24:12,069 INFO L290 TraceCheckUtils]: 17: Hoare triple {4517#false} assume !(0 == ~E_1~0); {4517#false} is VALID [2022-02-21 04:24:12,069 INFO L290 TraceCheckUtils]: 18: Hoare triple {4517#false} assume !(0 == ~E_2~0); {4517#false} is VALID [2022-02-21 04:24:12,069 INFO L290 TraceCheckUtils]: 19: Hoare triple {4517#false} assume 0 == ~E_3~0;~E_3~0 := 1; {4517#false} is VALID [2022-02-21 04:24:12,069 INFO L290 TraceCheckUtils]: 20: Hoare triple {4517#false} assume !(0 == ~E_4~0); {4517#false} is VALID [2022-02-21 04:24:12,070 INFO L290 TraceCheckUtils]: 21: Hoare triple {4517#false} assume !(0 == ~E_5~0); {4517#false} is VALID [2022-02-21 04:24:12,070 INFO L290 TraceCheckUtils]: 22: Hoare triple {4517#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4517#false} is VALID [2022-02-21 04:24:12,070 INFO L290 TraceCheckUtils]: 23: Hoare triple {4517#false} assume 1 == ~m_pc~0; {4517#false} is VALID [2022-02-21 04:24:12,070 INFO L290 TraceCheckUtils]: 24: Hoare triple {4517#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {4517#false} is VALID [2022-02-21 04:24:12,070 INFO L290 TraceCheckUtils]: 25: Hoare triple {4517#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4517#false} is VALID [2022-02-21 04:24:12,071 INFO L290 TraceCheckUtils]: 26: Hoare triple {4517#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {4517#false} is VALID [2022-02-21 04:24:12,071 INFO L290 TraceCheckUtils]: 27: Hoare triple {4517#false} assume !(0 != activate_threads_~tmp~1#1); {4517#false} is VALID [2022-02-21 04:24:12,071 INFO L290 TraceCheckUtils]: 28: Hoare triple {4517#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4517#false} is VALID [2022-02-21 04:24:12,071 INFO L290 TraceCheckUtils]: 29: Hoare triple {4517#false} assume !(1 == ~t1_pc~0); {4517#false} is VALID [2022-02-21 04:24:12,071 INFO L290 TraceCheckUtils]: 30: Hoare triple {4517#false} is_transmit1_triggered_~__retres1~1#1 := 0; {4517#false} is VALID [2022-02-21 04:24:12,071 INFO L290 TraceCheckUtils]: 31: Hoare triple {4517#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4517#false} is VALID [2022-02-21 04:24:12,072 INFO L290 TraceCheckUtils]: 32: Hoare triple {4517#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {4517#false} is VALID [2022-02-21 04:24:12,072 INFO L290 TraceCheckUtils]: 33: Hoare triple {4517#false} assume !(0 != activate_threads_~tmp___0~0#1); {4517#false} is VALID [2022-02-21 04:24:12,072 INFO L290 TraceCheckUtils]: 34: Hoare triple {4517#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4517#false} is VALID [2022-02-21 04:24:12,072 INFO L290 TraceCheckUtils]: 35: Hoare triple {4517#false} assume 1 == ~t2_pc~0; {4517#false} is VALID [2022-02-21 04:24:12,072 INFO L290 TraceCheckUtils]: 36: Hoare triple {4517#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {4517#false} is VALID [2022-02-21 04:24:12,072 INFO L290 TraceCheckUtils]: 37: Hoare triple {4517#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4517#false} is VALID [2022-02-21 04:24:12,073 INFO L290 TraceCheckUtils]: 38: Hoare triple {4517#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {4517#false} is VALID [2022-02-21 04:24:12,073 INFO L290 TraceCheckUtils]: 39: Hoare triple {4517#false} assume !(0 != activate_threads_~tmp___1~0#1); {4517#false} is VALID [2022-02-21 04:24:12,073 INFO L290 TraceCheckUtils]: 40: Hoare triple {4517#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4517#false} is VALID [2022-02-21 04:24:12,073 INFO L290 TraceCheckUtils]: 41: Hoare triple {4517#false} assume 1 == ~t3_pc~0; {4517#false} is VALID [2022-02-21 04:24:12,073 INFO L290 TraceCheckUtils]: 42: Hoare triple {4517#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {4517#false} is VALID [2022-02-21 04:24:12,074 INFO L290 TraceCheckUtils]: 43: Hoare triple {4517#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4517#false} is VALID [2022-02-21 04:24:12,074 INFO L290 TraceCheckUtils]: 44: Hoare triple {4517#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {4517#false} is VALID [2022-02-21 04:24:12,074 INFO L290 TraceCheckUtils]: 45: Hoare triple {4517#false} assume !(0 != activate_threads_~tmp___2~0#1); {4517#false} is VALID [2022-02-21 04:24:12,074 INFO L290 TraceCheckUtils]: 46: Hoare triple {4517#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {4517#false} is VALID [2022-02-21 04:24:12,074 INFO L290 TraceCheckUtils]: 47: Hoare triple {4517#false} assume !(1 == ~t4_pc~0); {4517#false} is VALID [2022-02-21 04:24:12,074 INFO L290 TraceCheckUtils]: 48: Hoare triple {4517#false} is_transmit4_triggered_~__retres1~4#1 := 0; {4517#false} is VALID [2022-02-21 04:24:12,075 INFO L290 TraceCheckUtils]: 49: Hoare triple {4517#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {4517#false} is VALID [2022-02-21 04:24:12,075 INFO L290 TraceCheckUtils]: 50: Hoare triple {4517#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {4517#false} is VALID [2022-02-21 04:24:12,075 INFO L290 TraceCheckUtils]: 51: Hoare triple {4517#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {4517#false} is VALID [2022-02-21 04:24:12,075 INFO L290 TraceCheckUtils]: 52: Hoare triple {4517#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {4517#false} is VALID [2022-02-21 04:24:12,075 INFO L290 TraceCheckUtils]: 53: Hoare triple {4517#false} assume 1 == ~t5_pc~0; {4517#false} is VALID [2022-02-21 04:24:12,075 INFO L290 TraceCheckUtils]: 54: Hoare triple {4517#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {4517#false} is VALID [2022-02-21 04:24:12,076 INFO L290 TraceCheckUtils]: 55: Hoare triple {4517#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {4517#false} is VALID [2022-02-21 04:24:12,076 INFO L290 TraceCheckUtils]: 56: Hoare triple {4517#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {4517#false} is VALID [2022-02-21 04:24:12,076 INFO L290 TraceCheckUtils]: 57: Hoare triple {4517#false} assume !(0 != activate_threads_~tmp___4~0#1); {4517#false} is VALID [2022-02-21 04:24:12,076 INFO L290 TraceCheckUtils]: 58: Hoare triple {4517#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4517#false} is VALID [2022-02-21 04:24:12,076 INFO L290 TraceCheckUtils]: 59: Hoare triple {4517#false} assume 1 == ~M_E~0;~M_E~0 := 2; {4517#false} is VALID [2022-02-21 04:24:12,076 INFO L290 TraceCheckUtils]: 60: Hoare triple {4517#false} assume !(1 == ~T1_E~0); {4517#false} is VALID [2022-02-21 04:24:12,077 INFO L290 TraceCheckUtils]: 61: Hoare triple {4517#false} assume !(1 == ~T2_E~0); {4517#false} is VALID [2022-02-21 04:24:12,077 INFO L290 TraceCheckUtils]: 62: Hoare triple {4517#false} assume !(1 == ~T3_E~0); {4517#false} is VALID [2022-02-21 04:24:12,077 INFO L290 TraceCheckUtils]: 63: Hoare triple {4517#false} assume !(1 == ~T4_E~0); {4517#false} is VALID [2022-02-21 04:24:12,077 INFO L290 TraceCheckUtils]: 64: Hoare triple {4517#false} assume !(1 == ~T5_E~0); {4517#false} is VALID [2022-02-21 04:24:12,077 INFO L290 TraceCheckUtils]: 65: Hoare triple {4517#false} assume !(1 == ~E_1~0); {4517#false} is VALID [2022-02-21 04:24:12,077 INFO L290 TraceCheckUtils]: 66: Hoare triple {4517#false} assume !(1 == ~E_2~0); {4517#false} is VALID [2022-02-21 04:24:12,077 INFO L290 TraceCheckUtils]: 67: Hoare triple {4517#false} assume 1 == ~E_3~0;~E_3~0 := 2; {4517#false} is VALID [2022-02-21 04:24:12,077 INFO L290 TraceCheckUtils]: 68: Hoare triple {4517#false} assume !(1 == ~E_4~0); {4517#false} is VALID [2022-02-21 04:24:12,077 INFO L290 TraceCheckUtils]: 69: Hoare triple {4517#false} assume !(1 == ~E_5~0); {4517#false} is VALID [2022-02-21 04:24:12,077 INFO L290 TraceCheckUtils]: 70: Hoare triple {4517#false} assume { :end_inline_reset_delta_events } true; {4517#false} is VALID [2022-02-21 04:24:12,078 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:12,078 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:12,078 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552618060] [2022-02-21 04:24:12,078 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552618060] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:12,078 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:12,078 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:12,078 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503270469] [2022-02-21 04:24:12,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:12,079 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:12,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:12,079 INFO L85 PathProgramCache]: Analyzing trace with hash 912244302, now seen corresponding path program 1 times [2022-02-21 04:24:12,079 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:12,079 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316054791] [2022-02-21 04:24:12,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:12,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:12,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:12,163 INFO L290 TraceCheckUtils]: 0: Hoare triple {4519#true} assume !false; {4519#true} is VALID [2022-02-21 04:24:12,163 INFO L290 TraceCheckUtils]: 1: Hoare triple {4519#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {4519#true} is VALID [2022-02-21 04:24:12,163 INFO L290 TraceCheckUtils]: 2: Hoare triple {4519#true} assume !false; {4519#true} is VALID [2022-02-21 04:24:12,163 INFO L290 TraceCheckUtils]: 3: Hoare triple {4519#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {4519#true} is VALID [2022-02-21 04:24:12,163 INFO L290 TraceCheckUtils]: 4: Hoare triple {4519#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {4519#true} is VALID [2022-02-21 04:24:12,164 INFO L290 TraceCheckUtils]: 5: Hoare triple {4519#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {4519#true} is VALID [2022-02-21 04:24:12,164 INFO L290 TraceCheckUtils]: 6: Hoare triple {4519#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {4519#true} is VALID [2022-02-21 04:24:12,164 INFO L290 TraceCheckUtils]: 7: Hoare triple {4519#true} assume !(0 != eval_~tmp~0#1); {4519#true} is VALID [2022-02-21 04:24:12,164 INFO L290 TraceCheckUtils]: 8: Hoare triple {4519#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {4519#true} is VALID [2022-02-21 04:24:12,164 INFO L290 TraceCheckUtils]: 9: Hoare triple {4519#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {4519#true} is VALID [2022-02-21 04:24:12,164 INFO L290 TraceCheckUtils]: 10: Hoare triple {4519#true} assume 0 == ~M_E~0;~M_E~0 := 1; {4519#true} is VALID [2022-02-21 04:24:12,164 INFO L290 TraceCheckUtils]: 11: Hoare triple {4519#true} assume !(0 == ~T1_E~0); {4519#true} is VALID [2022-02-21 04:24:12,164 INFO L290 TraceCheckUtils]: 12: Hoare triple {4519#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {4519#true} is VALID [2022-02-21 04:24:12,165 INFO L290 TraceCheckUtils]: 13: Hoare triple {4519#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {4519#true} is VALID [2022-02-21 04:24:12,165 INFO L290 TraceCheckUtils]: 14: Hoare triple {4519#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {4519#true} is VALID [2022-02-21 04:24:12,165 INFO L290 TraceCheckUtils]: 15: Hoare triple {4519#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {4519#true} is VALID [2022-02-21 04:24:12,165 INFO L290 TraceCheckUtils]: 16: Hoare triple {4519#true} assume 0 == ~E_1~0;~E_1~0 := 1; {4519#true} is VALID [2022-02-21 04:24:12,165 INFO L290 TraceCheckUtils]: 17: Hoare triple {4519#true} assume 0 == ~E_2~0;~E_2~0 := 1; {4519#true} is VALID [2022-02-21 04:24:12,165 INFO L290 TraceCheckUtils]: 18: Hoare triple {4519#true} assume 0 == ~E_3~0;~E_3~0 := 1; {4519#true} is VALID [2022-02-21 04:24:12,165 INFO L290 TraceCheckUtils]: 19: Hoare triple {4519#true} assume !(0 == ~E_4~0); {4519#true} is VALID [2022-02-21 04:24:12,165 INFO L290 TraceCheckUtils]: 20: Hoare triple {4519#true} assume 0 == ~E_5~0;~E_5~0 := 1; {4519#true} is VALID [2022-02-21 04:24:12,166 INFO L290 TraceCheckUtils]: 21: Hoare triple {4519#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4519#true} is VALID [2022-02-21 04:24:12,166 INFO L290 TraceCheckUtils]: 22: Hoare triple {4519#true} assume !(1 == ~m_pc~0); {4519#true} is VALID [2022-02-21 04:24:12,166 INFO L290 TraceCheckUtils]: 23: Hoare triple {4519#true} is_master_triggered_~__retres1~0#1 := 0; {4519#true} is VALID [2022-02-21 04:24:12,166 INFO L290 TraceCheckUtils]: 24: Hoare triple {4519#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4519#true} is VALID [2022-02-21 04:24:12,166 INFO L290 TraceCheckUtils]: 25: Hoare triple {4519#true} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {4519#true} is VALID [2022-02-21 04:24:12,166 INFO L290 TraceCheckUtils]: 26: Hoare triple {4519#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {4519#true} is VALID [2022-02-21 04:24:12,166 INFO L290 TraceCheckUtils]: 27: Hoare triple {4519#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4519#true} is VALID [2022-02-21 04:24:12,166 INFO L290 TraceCheckUtils]: 28: Hoare triple {4519#true} assume 1 == ~t1_pc~0; {4519#true} is VALID [2022-02-21 04:24:12,167 INFO L290 TraceCheckUtils]: 29: Hoare triple {4519#true} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {4519#true} is VALID [2022-02-21 04:24:12,167 INFO L290 TraceCheckUtils]: 30: Hoare triple {4519#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4519#true} is VALID [2022-02-21 04:24:12,167 INFO L290 TraceCheckUtils]: 31: Hoare triple {4519#true} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {4519#true} is VALID [2022-02-21 04:24:12,167 INFO L290 TraceCheckUtils]: 32: Hoare triple {4519#true} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {4519#true} is VALID [2022-02-21 04:24:12,167 INFO L290 TraceCheckUtils]: 33: Hoare triple {4519#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4519#true} is VALID [2022-02-21 04:24:12,167 INFO L290 TraceCheckUtils]: 34: Hoare triple {4519#true} assume 1 == ~t2_pc~0; {4519#true} is VALID [2022-02-21 04:24:12,167 INFO L290 TraceCheckUtils]: 35: Hoare triple {4519#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {4519#true} is VALID [2022-02-21 04:24:12,168 INFO L290 TraceCheckUtils]: 36: Hoare triple {4519#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4519#true} is VALID [2022-02-21 04:24:12,168 INFO L290 TraceCheckUtils]: 37: Hoare triple {4519#true} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {4519#true} is VALID [2022-02-21 04:24:12,168 INFO L290 TraceCheckUtils]: 38: Hoare triple {4519#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {4519#true} is VALID [2022-02-21 04:24:12,168 INFO L290 TraceCheckUtils]: 39: Hoare triple {4519#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4519#true} is VALID [2022-02-21 04:24:12,168 INFO L290 TraceCheckUtils]: 40: Hoare triple {4519#true} assume 1 == ~t3_pc~0; {4519#true} is VALID [2022-02-21 04:24:12,168 INFO L290 TraceCheckUtils]: 41: Hoare triple {4519#true} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {4519#true} is VALID [2022-02-21 04:24:12,168 INFO L290 TraceCheckUtils]: 42: Hoare triple {4519#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4519#true} is VALID [2022-02-21 04:24:12,168 INFO L290 TraceCheckUtils]: 43: Hoare triple {4519#true} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {4519#true} is VALID [2022-02-21 04:24:12,169 INFO L290 TraceCheckUtils]: 44: Hoare triple {4519#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {4519#true} is VALID [2022-02-21 04:24:12,169 INFO L290 TraceCheckUtils]: 45: Hoare triple {4519#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {4519#true} is VALID [2022-02-21 04:24:12,169 INFO L290 TraceCheckUtils]: 46: Hoare triple {4519#true} assume 1 == ~t4_pc~0; {4519#true} is VALID [2022-02-21 04:24:12,175 INFO L290 TraceCheckUtils]: 47: Hoare triple {4519#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,176 INFO L290 TraceCheckUtils]: 48: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,176 INFO L290 TraceCheckUtils]: 49: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,176 INFO L290 TraceCheckUtils]: 50: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,177 INFO L290 TraceCheckUtils]: 51: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,177 INFO L290 TraceCheckUtils]: 52: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~t5_pc~0; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,178 INFO L290 TraceCheckUtils]: 53: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,178 INFO L290 TraceCheckUtils]: 54: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,178 INFO L290 TraceCheckUtils]: 55: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,179 INFO L290 TraceCheckUtils]: 56: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,179 INFO L290 TraceCheckUtils]: 57: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,180 INFO L290 TraceCheckUtils]: 58: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,180 INFO L290 TraceCheckUtils]: 59: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~T1_E~0); {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,180 INFO L290 TraceCheckUtils]: 60: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,181 INFO L290 TraceCheckUtils]: 61: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,181 INFO L290 TraceCheckUtils]: 62: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,182 INFO L290 TraceCheckUtils]: 63: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,183 INFO L290 TraceCheckUtils]: 64: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,183 INFO L290 TraceCheckUtils]: 65: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,184 INFO L290 TraceCheckUtils]: 66: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {4521#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,184 INFO L290 TraceCheckUtils]: 67: Hoare triple {4521#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~E_4~0); {4520#false} is VALID [2022-02-21 04:24:12,184 INFO L290 TraceCheckUtils]: 68: Hoare triple {4520#false} assume 1 == ~E_5~0;~E_5~0 := 2; {4520#false} is VALID [2022-02-21 04:24:12,184 INFO L290 TraceCheckUtils]: 69: Hoare triple {4520#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {4520#false} is VALID [2022-02-21 04:24:12,184 INFO L290 TraceCheckUtils]: 70: Hoare triple {4520#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {4520#false} is VALID [2022-02-21 04:24:12,185 INFO L290 TraceCheckUtils]: 71: Hoare triple {4520#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {4520#false} is VALID [2022-02-21 04:24:12,185 INFO L290 TraceCheckUtils]: 72: Hoare triple {4520#false} start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {4520#false} is VALID [2022-02-21 04:24:12,185 INFO L290 TraceCheckUtils]: 73: Hoare triple {4520#false} assume !(0 == start_simulation_~tmp~3#1); {4520#false} is VALID [2022-02-21 04:24:12,185 INFO L290 TraceCheckUtils]: 74: Hoare triple {4520#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {4520#false} is VALID [2022-02-21 04:24:12,185 INFO L290 TraceCheckUtils]: 75: Hoare triple {4520#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {4520#false} is VALID [2022-02-21 04:24:12,186 INFO L290 TraceCheckUtils]: 76: Hoare triple {4520#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {4520#false} is VALID [2022-02-21 04:24:12,186 INFO L290 TraceCheckUtils]: 77: Hoare triple {4520#false} stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; {4520#false} is VALID [2022-02-21 04:24:12,186 INFO L290 TraceCheckUtils]: 78: Hoare triple {4520#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {4520#false} is VALID [2022-02-21 04:24:12,186 INFO L290 TraceCheckUtils]: 79: Hoare triple {4520#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {4520#false} is VALID [2022-02-21 04:24:12,186 INFO L290 TraceCheckUtils]: 80: Hoare triple {4520#false} start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; {4520#false} is VALID [2022-02-21 04:24:12,186 INFO L290 TraceCheckUtils]: 81: Hoare triple {4520#false} assume !(0 != start_simulation_~tmp___0~1#1); {4520#false} is VALID [2022-02-21 04:24:12,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:12,188 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:12,188 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316054791] [2022-02-21 04:24:12,189 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1316054791] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:12,189 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:12,189 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:12,189 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734909239] [2022-02-21 04:24:12,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:12,190 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:12,190 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:12,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:12,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:12,192 INFO L87 Difference]: Start difference. First operand 498 states and 745 transitions. cyclomatic complexity: 248 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:12,621 INFO L93 Difference]: Finished difference Result 498 states and 744 transitions. [2022-02-21 04:24:12,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:12,621 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,677 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:12,679 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 744 transitions. [2022-02-21 04:24:12,692 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-02-21 04:24:12,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 744 transitions. [2022-02-21 04:24:12,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-02-21 04:24:12,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-02-21 04:24:12,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 744 transitions. [2022-02-21 04:24:12,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:12,707 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 744 transitions. [2022-02-21 04:24:12,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 744 transitions. [2022-02-21 04:24:12,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-02-21 04:24:12,712 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:12,713 INFO L82 GeneralOperation]: Start isEquivalent. First operand 498 states and 744 transitions. Second operand has 498 states, 498 states have (on average 1.4939759036144578) internal successors, (744), 497 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,715 INFO L74 IsIncluded]: Start isIncluded. First operand 498 states and 744 transitions. Second operand has 498 states, 498 states have (on average 1.4939759036144578) internal successors, (744), 497 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,716 INFO L87 Difference]: Start difference. First operand 498 states and 744 transitions. Second operand has 498 states, 498 states have (on average 1.4939759036144578) internal successors, (744), 497 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:12,728 INFO L93 Difference]: Finished difference Result 498 states and 744 transitions. [2022-02-21 04:24:12,728 INFO L276 IsEmpty]: Start isEmpty. Operand 498 states and 744 transitions. [2022-02-21 04:24:12,729 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:12,729 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:12,730 INFO L74 IsIncluded]: Start isIncluded. First operand has 498 states, 498 states have (on average 1.4939759036144578) internal successors, (744), 497 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 498 states and 744 transitions. [2022-02-21 04:24:12,731 INFO L87 Difference]: Start difference. First operand has 498 states, 498 states have (on average 1.4939759036144578) internal successors, (744), 497 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 498 states and 744 transitions. [2022-02-21 04:24:12,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:12,744 INFO L93 Difference]: Finished difference Result 498 states and 744 transitions. [2022-02-21 04:24:12,744 INFO L276 IsEmpty]: Start isEmpty. Operand 498 states and 744 transitions. [2022-02-21 04:24:12,745 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:12,745 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:12,745 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:12,745 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:12,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4939759036144578) internal successors, (744), 497 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 744 transitions. [2022-02-21 04:24:12,757 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 744 transitions. [2022-02-21 04:24:12,757 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 744 transitions. [2022-02-21 04:24:12,757 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:12,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 744 transitions. [2022-02-21 04:24:12,759 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-02-21 04:24:12,759 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:12,759 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:12,761 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:12,761 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:12,761 INFO L791 eck$LassoCheckResult]: Stem: 5517#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5503#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5495#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5493#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5407#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 5408#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5213#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5214#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5491#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5492#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5464#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5185#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 5186#L586-2 assume !(0 == ~T1_E~0); 5239#L591-1 assume !(0 == ~T2_E~0); 5359#L596-1 assume !(0 == ~T3_E~0); 5360#L601-1 assume !(0 == ~T4_E~0); 5398#L606-1 assume !(0 == ~T5_E~0); 5399#L611-1 assume !(0 == ~E_1~0); 5470#L616-1 assume !(0 == ~E_2~0); 5471#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5118#L626-1 assume !(0 == ~E_4~0); 5119#L631-1 assume !(0 == ~E_5~0); 5274#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5113#L279 assume 1 == ~m_pc~0; 5114#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5365#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5341#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5342#L720 assume !(0 != activate_threads_~tmp~1#1); 5415#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5278#L298 assume !(1 == ~t1_pc~0); 5070#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5071#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5330#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5127#L728 assume !(0 != activate_threads_~tmp___0~0#1); 5128#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5245#L317 assume 1 == ~t2_pc~0; 5246#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5392#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5499#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5287#L736 assume !(0 != activate_threads_~tmp___1~0#1); 5288#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5462#L336 assume 1 == ~t3_pc~0; 5334#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5335#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5382#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5383#L744 assume !(0 != activate_threads_~tmp___2~0#1); 5423#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5467#L355 assume !(1 == ~t4_pc~0); 5356#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5199#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5200#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5411#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5137#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5138#L374 assume 1 == ~t5_pc~0; 5485#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5266#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5339#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5340#L760 assume !(0 != activate_threads_~tmp___4~0#1); 5385#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5386#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 5508#L649-2 assume !(1 == ~T1_E~0); 5102#L654-1 assume !(1 == ~T2_E~0); 5103#L659-1 assume !(1 == ~T3_E~0); 5286#L664-1 assume !(1 == ~T4_E~0); 5095#L669-1 assume !(1 == ~T5_E~0); 5096#L674-1 assume !(1 == ~E_1~0); 5458#L679-1 assume !(1 == ~E_2~0); 5190#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5191#L689-1 assume !(1 == ~E_4~0); 5353#L694-1 assume !(1 == ~E_5~0); 5351#L699-1 assume { :end_inline_reset_delta_events } true; 5352#L900-2 [2022-02-21 04:24:12,761 INFO L793 eck$LassoCheckResult]: Loop: 5352#L900-2 assume !false; 5515#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5049#L561 assume !false; 5134#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5315#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5072#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5073#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5178#L486 assume !(0 != eval_~tmp~0#1); 5180#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5505#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5506#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5457#L586-5 assume !(0 == ~T1_E~0); 5366#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5204#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5205#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5379#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5409#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5410#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5106#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5067#L626-3 assume !(0 == ~E_4~0); 5068#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5074#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5075#L279-18 assume !(1 == ~m_pc~0); 5169#L279-20 is_master_triggered_~__retres1~0#1 := 0; 5168#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5289#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5290#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5473#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5384#L298-18 assume 1 == ~t1_pc~0; 5046#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5040#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5212#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5235#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5236#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5361#L317-18 assume 1 == ~t2_pc~0; 5267#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5269#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5206#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5207#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5215#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5476#L336-18 assume 1 == ~t3_pc~0; 5459#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5460#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5292#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5293#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5159#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5160#L355-18 assume 1 == ~t4_pc~0; 5433#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5422#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5248#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5249#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5255#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5256#L374-18 assume !(1 == ~t5_pc~0); 5440#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 5320#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5321#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5434#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5416#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5417#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5333#L649-5 assume !(1 == ~T1_E~0); 5314#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5170#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5171#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5076#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5077#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5065#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5066#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5020#L689-3 assume !(1 == ~E_4~0); 5021#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5060#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5061#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5063#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5475#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5350#L919 assume !(0 == start_simulation_~tmp~3#1); 5079#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5446#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5054#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5299#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5300#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5345#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5295#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5296#L932 assume !(0 != start_simulation_~tmp___0~1#1); 5352#L900-2 [2022-02-21 04:24:12,762 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:12,762 INFO L85 PathProgramCache]: Analyzing trace with hash -2115626582, now seen corresponding path program 1 times [2022-02-21 04:24:12,762 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:12,762 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [40403832] [2022-02-21 04:24:12,763 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:12,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:12,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:12,791 INFO L290 TraceCheckUtils]: 0: Hoare triple {6517#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; {6517#true} is VALID [2022-02-21 04:24:12,791 INFO L290 TraceCheckUtils]: 1: Hoare triple {6517#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; {6519#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:12,792 INFO L290 TraceCheckUtils]: 2: Hoare triple {6519#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {6519#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:12,792 INFO L290 TraceCheckUtils]: 3: Hoare triple {6519#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {6519#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:12,793 INFO L290 TraceCheckUtils]: 4: Hoare triple {6519#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {6519#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:12,793 INFO L290 TraceCheckUtils]: 5: Hoare triple {6519#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {6519#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:12,793 INFO L290 TraceCheckUtils]: 6: Hoare triple {6519#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {6519#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:12,794 INFO L290 TraceCheckUtils]: 7: Hoare triple {6519#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {6519#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:12,794 INFO L290 TraceCheckUtils]: 8: Hoare triple {6519#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {6518#false} is VALID [2022-02-21 04:24:12,794 INFO L290 TraceCheckUtils]: 9: Hoare triple {6518#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {6518#false} is VALID [2022-02-21 04:24:12,794 INFO L290 TraceCheckUtils]: 10: Hoare triple {6518#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {6518#false} is VALID [2022-02-21 04:24:12,795 INFO L290 TraceCheckUtils]: 11: Hoare triple {6518#false} assume 0 == ~M_E~0;~M_E~0 := 1; {6518#false} is VALID [2022-02-21 04:24:12,795 INFO L290 TraceCheckUtils]: 12: Hoare triple {6518#false} assume !(0 == ~T1_E~0); {6518#false} is VALID [2022-02-21 04:24:12,795 INFO L290 TraceCheckUtils]: 13: Hoare triple {6518#false} assume !(0 == ~T2_E~0); {6518#false} is VALID [2022-02-21 04:24:12,795 INFO L290 TraceCheckUtils]: 14: Hoare triple {6518#false} assume !(0 == ~T3_E~0); {6518#false} is VALID [2022-02-21 04:24:12,795 INFO L290 TraceCheckUtils]: 15: Hoare triple {6518#false} assume !(0 == ~T4_E~0); {6518#false} is VALID [2022-02-21 04:24:12,795 INFO L290 TraceCheckUtils]: 16: Hoare triple {6518#false} assume !(0 == ~T5_E~0); {6518#false} is VALID [2022-02-21 04:24:12,796 INFO L290 TraceCheckUtils]: 17: Hoare triple {6518#false} assume !(0 == ~E_1~0); {6518#false} is VALID [2022-02-21 04:24:12,796 INFO L290 TraceCheckUtils]: 18: Hoare triple {6518#false} assume !(0 == ~E_2~0); {6518#false} is VALID [2022-02-21 04:24:12,796 INFO L290 TraceCheckUtils]: 19: Hoare triple {6518#false} assume 0 == ~E_3~0;~E_3~0 := 1; {6518#false} is VALID [2022-02-21 04:24:12,796 INFO L290 TraceCheckUtils]: 20: Hoare triple {6518#false} assume !(0 == ~E_4~0); {6518#false} is VALID [2022-02-21 04:24:12,796 INFO L290 TraceCheckUtils]: 21: Hoare triple {6518#false} assume !(0 == ~E_5~0); {6518#false} is VALID [2022-02-21 04:24:12,796 INFO L290 TraceCheckUtils]: 22: Hoare triple {6518#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6518#false} is VALID [2022-02-21 04:24:12,797 INFO L290 TraceCheckUtils]: 23: Hoare triple {6518#false} assume 1 == ~m_pc~0; {6518#false} is VALID [2022-02-21 04:24:12,797 INFO L290 TraceCheckUtils]: 24: Hoare triple {6518#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {6518#false} is VALID [2022-02-21 04:24:12,797 INFO L290 TraceCheckUtils]: 25: Hoare triple {6518#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6518#false} is VALID [2022-02-21 04:24:12,797 INFO L290 TraceCheckUtils]: 26: Hoare triple {6518#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {6518#false} is VALID [2022-02-21 04:24:12,797 INFO L290 TraceCheckUtils]: 27: Hoare triple {6518#false} assume !(0 != activate_threads_~tmp~1#1); {6518#false} is VALID [2022-02-21 04:24:12,797 INFO L290 TraceCheckUtils]: 28: Hoare triple {6518#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6518#false} is VALID [2022-02-21 04:24:12,797 INFO L290 TraceCheckUtils]: 29: Hoare triple {6518#false} assume !(1 == ~t1_pc~0); {6518#false} is VALID [2022-02-21 04:24:12,798 INFO L290 TraceCheckUtils]: 30: Hoare triple {6518#false} is_transmit1_triggered_~__retres1~1#1 := 0; {6518#false} is VALID [2022-02-21 04:24:12,798 INFO L290 TraceCheckUtils]: 31: Hoare triple {6518#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6518#false} is VALID [2022-02-21 04:24:12,798 INFO L290 TraceCheckUtils]: 32: Hoare triple {6518#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {6518#false} is VALID [2022-02-21 04:24:12,798 INFO L290 TraceCheckUtils]: 33: Hoare triple {6518#false} assume !(0 != activate_threads_~tmp___0~0#1); {6518#false} is VALID [2022-02-21 04:24:12,798 INFO L290 TraceCheckUtils]: 34: Hoare triple {6518#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6518#false} is VALID [2022-02-21 04:24:12,799 INFO L290 TraceCheckUtils]: 35: Hoare triple {6518#false} assume 1 == ~t2_pc~0; {6518#false} is VALID [2022-02-21 04:24:12,799 INFO L290 TraceCheckUtils]: 36: Hoare triple {6518#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6518#false} is VALID [2022-02-21 04:24:12,802 INFO L290 TraceCheckUtils]: 37: Hoare triple {6518#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6518#false} is VALID [2022-02-21 04:24:12,802 INFO L290 TraceCheckUtils]: 38: Hoare triple {6518#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {6518#false} is VALID [2022-02-21 04:24:12,803 INFO L290 TraceCheckUtils]: 39: Hoare triple {6518#false} assume !(0 != activate_threads_~tmp___1~0#1); {6518#false} is VALID [2022-02-21 04:24:12,803 INFO L290 TraceCheckUtils]: 40: Hoare triple {6518#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6518#false} is VALID [2022-02-21 04:24:12,803 INFO L290 TraceCheckUtils]: 41: Hoare triple {6518#false} assume 1 == ~t3_pc~0; {6518#false} is VALID [2022-02-21 04:24:12,803 INFO L290 TraceCheckUtils]: 42: Hoare triple {6518#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6518#false} is VALID [2022-02-21 04:24:12,803 INFO L290 TraceCheckUtils]: 43: Hoare triple {6518#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6518#false} is VALID [2022-02-21 04:24:12,803 INFO L290 TraceCheckUtils]: 44: Hoare triple {6518#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {6518#false} is VALID [2022-02-21 04:24:12,804 INFO L290 TraceCheckUtils]: 45: Hoare triple {6518#false} assume !(0 != activate_threads_~tmp___2~0#1); {6518#false} is VALID [2022-02-21 04:24:12,804 INFO L290 TraceCheckUtils]: 46: Hoare triple {6518#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6518#false} is VALID [2022-02-21 04:24:12,804 INFO L290 TraceCheckUtils]: 47: Hoare triple {6518#false} assume !(1 == ~t4_pc~0); {6518#false} is VALID [2022-02-21 04:24:12,804 INFO L290 TraceCheckUtils]: 48: Hoare triple {6518#false} is_transmit4_triggered_~__retres1~4#1 := 0; {6518#false} is VALID [2022-02-21 04:24:12,804 INFO L290 TraceCheckUtils]: 49: Hoare triple {6518#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6518#false} is VALID [2022-02-21 04:24:12,804 INFO L290 TraceCheckUtils]: 50: Hoare triple {6518#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {6518#false} is VALID [2022-02-21 04:24:12,805 INFO L290 TraceCheckUtils]: 51: Hoare triple {6518#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {6518#false} is VALID [2022-02-21 04:24:12,805 INFO L290 TraceCheckUtils]: 52: Hoare triple {6518#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6518#false} is VALID [2022-02-21 04:24:12,805 INFO L290 TraceCheckUtils]: 53: Hoare triple {6518#false} assume 1 == ~t5_pc~0; {6518#false} is VALID [2022-02-21 04:24:12,805 INFO L290 TraceCheckUtils]: 54: Hoare triple {6518#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {6518#false} is VALID [2022-02-21 04:24:12,805 INFO L290 TraceCheckUtils]: 55: Hoare triple {6518#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6518#false} is VALID [2022-02-21 04:24:12,806 INFO L290 TraceCheckUtils]: 56: Hoare triple {6518#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {6518#false} is VALID [2022-02-21 04:24:12,806 INFO L290 TraceCheckUtils]: 57: Hoare triple {6518#false} assume !(0 != activate_threads_~tmp___4~0#1); {6518#false} is VALID [2022-02-21 04:24:12,806 INFO L290 TraceCheckUtils]: 58: Hoare triple {6518#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6518#false} is VALID [2022-02-21 04:24:12,806 INFO L290 TraceCheckUtils]: 59: Hoare triple {6518#false} assume 1 == ~M_E~0;~M_E~0 := 2; {6518#false} is VALID [2022-02-21 04:24:12,806 INFO L290 TraceCheckUtils]: 60: Hoare triple {6518#false} assume !(1 == ~T1_E~0); {6518#false} is VALID [2022-02-21 04:24:12,806 INFO L290 TraceCheckUtils]: 61: Hoare triple {6518#false} assume !(1 == ~T2_E~0); {6518#false} is VALID [2022-02-21 04:24:12,811 INFO L290 TraceCheckUtils]: 62: Hoare triple {6518#false} assume !(1 == ~T3_E~0); {6518#false} is VALID [2022-02-21 04:24:12,811 INFO L290 TraceCheckUtils]: 63: Hoare triple {6518#false} assume !(1 == ~T4_E~0); {6518#false} is VALID [2022-02-21 04:24:12,811 INFO L290 TraceCheckUtils]: 64: Hoare triple {6518#false} assume !(1 == ~T5_E~0); {6518#false} is VALID [2022-02-21 04:24:12,812 INFO L290 TraceCheckUtils]: 65: Hoare triple {6518#false} assume !(1 == ~E_1~0); {6518#false} is VALID [2022-02-21 04:24:12,812 INFO L290 TraceCheckUtils]: 66: Hoare triple {6518#false} assume !(1 == ~E_2~0); {6518#false} is VALID [2022-02-21 04:24:12,812 INFO L290 TraceCheckUtils]: 67: Hoare triple {6518#false} assume 1 == ~E_3~0;~E_3~0 := 2; {6518#false} is VALID [2022-02-21 04:24:12,812 INFO L290 TraceCheckUtils]: 68: Hoare triple {6518#false} assume !(1 == ~E_4~0); {6518#false} is VALID [2022-02-21 04:24:12,812 INFO L290 TraceCheckUtils]: 69: Hoare triple {6518#false} assume !(1 == ~E_5~0); {6518#false} is VALID [2022-02-21 04:24:12,812 INFO L290 TraceCheckUtils]: 70: Hoare triple {6518#false} assume { :end_inline_reset_delta_events } true; {6518#false} is VALID [2022-02-21 04:24:12,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:12,813 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:12,813 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [40403832] [2022-02-21 04:24:12,813 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [40403832] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:12,813 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:12,814 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:12,814 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235169855] [2022-02-21 04:24:12,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:12,814 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:12,815 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:12,817 INFO L85 PathProgramCache]: Analyzing trace with hash 855100077, now seen corresponding path program 1 times [2022-02-21 04:24:12,817 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:12,818 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2116131198] [2022-02-21 04:24:12,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:12,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:12,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:12,865 INFO L290 TraceCheckUtils]: 0: Hoare triple {6520#true} assume !false; {6520#true} is VALID [2022-02-21 04:24:12,865 INFO L290 TraceCheckUtils]: 1: Hoare triple {6520#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {6520#true} is VALID [2022-02-21 04:24:12,866 INFO L290 TraceCheckUtils]: 2: Hoare triple {6520#true} assume !false; {6520#true} is VALID [2022-02-21 04:24:12,866 INFO L290 TraceCheckUtils]: 3: Hoare triple {6520#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {6520#true} is VALID [2022-02-21 04:24:12,866 INFO L290 TraceCheckUtils]: 4: Hoare triple {6520#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {6520#true} is VALID [2022-02-21 04:24:12,866 INFO L290 TraceCheckUtils]: 5: Hoare triple {6520#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {6520#true} is VALID [2022-02-21 04:24:12,866 INFO L290 TraceCheckUtils]: 6: Hoare triple {6520#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {6520#true} is VALID [2022-02-21 04:24:12,866 INFO L290 TraceCheckUtils]: 7: Hoare triple {6520#true} assume !(0 != eval_~tmp~0#1); {6520#true} is VALID [2022-02-21 04:24:12,867 INFO L290 TraceCheckUtils]: 8: Hoare triple {6520#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {6520#true} is VALID [2022-02-21 04:24:12,867 INFO L290 TraceCheckUtils]: 9: Hoare triple {6520#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {6520#true} is VALID [2022-02-21 04:24:12,867 INFO L290 TraceCheckUtils]: 10: Hoare triple {6520#true} assume 0 == ~M_E~0;~M_E~0 := 1; {6520#true} is VALID [2022-02-21 04:24:12,867 INFO L290 TraceCheckUtils]: 11: Hoare triple {6520#true} assume !(0 == ~T1_E~0); {6520#true} is VALID [2022-02-21 04:24:12,867 INFO L290 TraceCheckUtils]: 12: Hoare triple {6520#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {6520#true} is VALID [2022-02-21 04:24:12,867 INFO L290 TraceCheckUtils]: 13: Hoare triple {6520#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {6520#true} is VALID [2022-02-21 04:24:12,868 INFO L290 TraceCheckUtils]: 14: Hoare triple {6520#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {6520#true} is VALID [2022-02-21 04:24:12,868 INFO L290 TraceCheckUtils]: 15: Hoare triple {6520#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {6520#true} is VALID [2022-02-21 04:24:12,868 INFO L290 TraceCheckUtils]: 16: Hoare triple {6520#true} assume 0 == ~E_1~0;~E_1~0 := 1; {6520#true} is VALID [2022-02-21 04:24:12,868 INFO L290 TraceCheckUtils]: 17: Hoare triple {6520#true} assume 0 == ~E_2~0;~E_2~0 := 1; {6520#true} is VALID [2022-02-21 04:24:12,868 INFO L290 TraceCheckUtils]: 18: Hoare triple {6520#true} assume 0 == ~E_3~0;~E_3~0 := 1; {6520#true} is VALID [2022-02-21 04:24:12,868 INFO L290 TraceCheckUtils]: 19: Hoare triple {6520#true} assume !(0 == ~E_4~0); {6520#true} is VALID [2022-02-21 04:24:12,869 INFO L290 TraceCheckUtils]: 20: Hoare triple {6520#true} assume 0 == ~E_5~0;~E_5~0 := 1; {6520#true} is VALID [2022-02-21 04:24:12,869 INFO L290 TraceCheckUtils]: 21: Hoare triple {6520#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6520#true} is VALID [2022-02-21 04:24:12,869 INFO L290 TraceCheckUtils]: 22: Hoare triple {6520#true} assume !(1 == ~m_pc~0); {6520#true} is VALID [2022-02-21 04:24:12,869 INFO L290 TraceCheckUtils]: 23: Hoare triple {6520#true} is_master_triggered_~__retres1~0#1 := 0; {6520#true} is VALID [2022-02-21 04:24:12,869 INFO L290 TraceCheckUtils]: 24: Hoare triple {6520#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6520#true} is VALID [2022-02-21 04:24:12,869 INFO L290 TraceCheckUtils]: 25: Hoare triple {6520#true} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {6520#true} is VALID [2022-02-21 04:24:12,870 INFO L290 TraceCheckUtils]: 26: Hoare triple {6520#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {6520#true} is VALID [2022-02-21 04:24:12,870 INFO L290 TraceCheckUtils]: 27: Hoare triple {6520#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6520#true} is VALID [2022-02-21 04:24:12,870 INFO L290 TraceCheckUtils]: 28: Hoare triple {6520#true} assume 1 == ~t1_pc~0; {6520#true} is VALID [2022-02-21 04:24:12,870 INFO L290 TraceCheckUtils]: 29: Hoare triple {6520#true} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {6520#true} is VALID [2022-02-21 04:24:12,870 INFO L290 TraceCheckUtils]: 30: Hoare triple {6520#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6520#true} is VALID [2022-02-21 04:24:12,870 INFO L290 TraceCheckUtils]: 31: Hoare triple {6520#true} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {6520#true} is VALID [2022-02-21 04:24:12,871 INFO L290 TraceCheckUtils]: 32: Hoare triple {6520#true} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {6520#true} is VALID [2022-02-21 04:24:12,871 INFO L290 TraceCheckUtils]: 33: Hoare triple {6520#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6520#true} is VALID [2022-02-21 04:24:12,871 INFO L290 TraceCheckUtils]: 34: Hoare triple {6520#true} assume 1 == ~t2_pc~0; {6520#true} is VALID [2022-02-21 04:24:12,871 INFO L290 TraceCheckUtils]: 35: Hoare triple {6520#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6520#true} is VALID [2022-02-21 04:24:12,871 INFO L290 TraceCheckUtils]: 36: Hoare triple {6520#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6520#true} is VALID [2022-02-21 04:24:12,871 INFO L290 TraceCheckUtils]: 37: Hoare triple {6520#true} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {6520#true} is VALID [2022-02-21 04:24:12,872 INFO L290 TraceCheckUtils]: 38: Hoare triple {6520#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {6520#true} is VALID [2022-02-21 04:24:12,872 INFO L290 TraceCheckUtils]: 39: Hoare triple {6520#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6520#true} is VALID [2022-02-21 04:24:12,872 INFO L290 TraceCheckUtils]: 40: Hoare triple {6520#true} assume 1 == ~t3_pc~0; {6520#true} is VALID [2022-02-21 04:24:12,872 INFO L290 TraceCheckUtils]: 41: Hoare triple {6520#true} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6520#true} is VALID [2022-02-21 04:24:12,872 INFO L290 TraceCheckUtils]: 42: Hoare triple {6520#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6520#true} is VALID [2022-02-21 04:24:12,872 INFO L290 TraceCheckUtils]: 43: Hoare triple {6520#true} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {6520#true} is VALID [2022-02-21 04:24:12,872 INFO L290 TraceCheckUtils]: 44: Hoare triple {6520#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {6520#true} is VALID [2022-02-21 04:24:12,873 INFO L290 TraceCheckUtils]: 45: Hoare triple {6520#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6520#true} is VALID [2022-02-21 04:24:12,873 INFO L290 TraceCheckUtils]: 46: Hoare triple {6520#true} assume 1 == ~t4_pc~0; {6520#true} is VALID [2022-02-21 04:24:12,873 INFO L290 TraceCheckUtils]: 47: Hoare triple {6520#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,874 INFO L290 TraceCheckUtils]: 48: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,874 INFO L290 TraceCheckUtils]: 49: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,875 INFO L290 TraceCheckUtils]: 50: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,875 INFO L290 TraceCheckUtils]: 51: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,875 INFO L290 TraceCheckUtils]: 52: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~t5_pc~0); {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,876 INFO L290 TraceCheckUtils]: 53: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,876 INFO L290 TraceCheckUtils]: 54: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,876 INFO L290 TraceCheckUtils]: 55: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,877 INFO L290 TraceCheckUtils]: 56: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,877 INFO L290 TraceCheckUtils]: 57: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,878 INFO L290 TraceCheckUtils]: 58: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,878 INFO L290 TraceCheckUtils]: 59: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~T1_E~0); {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,878 INFO L290 TraceCheckUtils]: 60: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,879 INFO L290 TraceCheckUtils]: 61: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,879 INFO L290 TraceCheckUtils]: 62: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,879 INFO L290 TraceCheckUtils]: 63: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,880 INFO L290 TraceCheckUtils]: 64: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,880 INFO L290 TraceCheckUtils]: 65: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,881 INFO L290 TraceCheckUtils]: 66: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {6522#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:12,881 INFO L290 TraceCheckUtils]: 67: Hoare triple {6522#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~E_4~0); {6521#false} is VALID [2022-02-21 04:24:12,881 INFO L290 TraceCheckUtils]: 68: Hoare triple {6521#false} assume 1 == ~E_5~0;~E_5~0 := 2; {6521#false} is VALID [2022-02-21 04:24:12,881 INFO L290 TraceCheckUtils]: 69: Hoare triple {6521#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {6521#false} is VALID [2022-02-21 04:24:12,881 INFO L290 TraceCheckUtils]: 70: Hoare triple {6521#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {6521#false} is VALID [2022-02-21 04:24:12,882 INFO L290 TraceCheckUtils]: 71: Hoare triple {6521#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {6521#false} is VALID [2022-02-21 04:24:12,882 INFO L290 TraceCheckUtils]: 72: Hoare triple {6521#false} start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {6521#false} is VALID [2022-02-21 04:24:12,882 INFO L290 TraceCheckUtils]: 73: Hoare triple {6521#false} assume !(0 == start_simulation_~tmp~3#1); {6521#false} is VALID [2022-02-21 04:24:12,882 INFO L290 TraceCheckUtils]: 74: Hoare triple {6521#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {6521#false} is VALID [2022-02-21 04:24:12,882 INFO L290 TraceCheckUtils]: 75: Hoare triple {6521#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {6521#false} is VALID [2022-02-21 04:24:12,883 INFO L290 TraceCheckUtils]: 76: Hoare triple {6521#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {6521#false} is VALID [2022-02-21 04:24:12,883 INFO L290 TraceCheckUtils]: 77: Hoare triple {6521#false} stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; {6521#false} is VALID [2022-02-21 04:24:12,883 INFO L290 TraceCheckUtils]: 78: Hoare triple {6521#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {6521#false} is VALID [2022-02-21 04:24:12,883 INFO L290 TraceCheckUtils]: 79: Hoare triple {6521#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {6521#false} is VALID [2022-02-21 04:24:12,883 INFO L290 TraceCheckUtils]: 80: Hoare triple {6521#false} start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; {6521#false} is VALID [2022-02-21 04:24:12,883 INFO L290 TraceCheckUtils]: 81: Hoare triple {6521#false} assume !(0 != start_simulation_~tmp___0~1#1); {6521#false} is VALID [2022-02-21 04:24:12,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:12,884 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:12,884 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2116131198] [2022-02-21 04:24:12,884 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2116131198] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:12,885 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:12,885 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:12,885 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96546992] [2022-02-21 04:24:12,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:12,885 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:12,886 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:12,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:12,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:12,886 INFO L87 Difference]: Start difference. First operand 498 states and 744 transitions. cyclomatic complexity: 247 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,398 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:13,398 INFO L93 Difference]: Finished difference Result 498 states and 743 transitions. [2022-02-21 04:24:13,398 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:13,399 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,456 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:13,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 743 transitions. [2022-02-21 04:24:13,470 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-02-21 04:24:13,481 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 743 transitions. [2022-02-21 04:24:13,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-02-21 04:24:13,482 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-02-21 04:24:13,482 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 743 transitions. [2022-02-21 04:24:13,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:13,483 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 743 transitions. [2022-02-21 04:24:13,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 743 transitions. [2022-02-21 04:24:13,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-02-21 04:24:13,488 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:13,489 INFO L82 GeneralOperation]: Start isEquivalent. First operand 498 states and 743 transitions. Second operand has 498 states, 498 states have (on average 1.4919678714859437) internal successors, (743), 497 states have internal predecessors, (743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,490 INFO L74 IsIncluded]: Start isIncluded. First operand 498 states and 743 transitions. Second operand has 498 states, 498 states have (on average 1.4919678714859437) internal successors, (743), 497 states have internal predecessors, (743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,491 INFO L87 Difference]: Start difference. First operand 498 states and 743 transitions. Second operand has 498 states, 498 states have (on average 1.4919678714859437) internal successors, (743), 497 states have internal predecessors, (743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:13,502 INFO L93 Difference]: Finished difference Result 498 states and 743 transitions. [2022-02-21 04:24:13,502 INFO L276 IsEmpty]: Start isEmpty. Operand 498 states and 743 transitions. [2022-02-21 04:24:13,503 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:13,503 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:13,504 INFO L74 IsIncluded]: Start isIncluded. First operand has 498 states, 498 states have (on average 1.4919678714859437) internal successors, (743), 497 states have internal predecessors, (743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 498 states and 743 transitions. [2022-02-21 04:24:13,505 INFO L87 Difference]: Start difference. First operand has 498 states, 498 states have (on average 1.4919678714859437) internal successors, (743), 497 states have internal predecessors, (743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 498 states and 743 transitions. [2022-02-21 04:24:13,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:13,517 INFO L93 Difference]: Finished difference Result 498 states and 743 transitions. [2022-02-21 04:24:13,517 INFO L276 IsEmpty]: Start isEmpty. Operand 498 states and 743 transitions. [2022-02-21 04:24:13,518 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:13,518 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:13,518 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:13,518 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:13,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4919678714859437) internal successors, (743), 497 states have internal predecessors, (743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 743 transitions. [2022-02-21 04:24:13,530 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 743 transitions. [2022-02-21 04:24:13,530 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 743 transitions. [2022-02-21 04:24:13,530 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:13,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 743 transitions. [2022-02-21 04:24:13,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-02-21 04:24:13,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:13,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:13,534 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:13,534 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:13,534 INFO L791 eck$LassoCheckResult]: Stem: 7518#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 7504#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7496#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7494#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7408#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 7409#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7214#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7215#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7492#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7493#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7465#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7186#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 7187#L586-2 assume !(0 == ~T1_E~0); 7240#L591-1 assume !(0 == ~T2_E~0); 7360#L596-1 assume !(0 == ~T3_E~0); 7361#L601-1 assume !(0 == ~T4_E~0); 7399#L606-1 assume !(0 == ~T5_E~0); 7400#L611-1 assume !(0 == ~E_1~0); 7471#L616-1 assume !(0 == ~E_2~0); 7472#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 7119#L626-1 assume !(0 == ~E_4~0); 7120#L631-1 assume !(0 == ~E_5~0); 7275#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7114#L279 assume 1 == ~m_pc~0; 7115#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7366#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7342#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7343#L720 assume !(0 != activate_threads_~tmp~1#1); 7416#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7279#L298 assume !(1 == ~t1_pc~0); 7071#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7072#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7331#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7128#L728 assume !(0 != activate_threads_~tmp___0~0#1); 7129#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7246#L317 assume 1 == ~t2_pc~0; 7247#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7393#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7500#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7288#L736 assume !(0 != activate_threads_~tmp___1~0#1); 7289#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7463#L336 assume 1 == ~t3_pc~0; 7335#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7336#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7383#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7384#L744 assume !(0 != activate_threads_~tmp___2~0#1); 7424#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7468#L355 assume !(1 == ~t4_pc~0); 7357#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7200#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7201#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7412#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7138#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7139#L374 assume 1 == ~t5_pc~0; 7486#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7267#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7340#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7341#L760 assume !(0 != activate_threads_~tmp___4~0#1); 7386#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7387#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 7509#L649-2 assume !(1 == ~T1_E~0); 7103#L654-1 assume !(1 == ~T2_E~0); 7104#L659-1 assume !(1 == ~T3_E~0); 7287#L664-1 assume !(1 == ~T4_E~0); 7096#L669-1 assume !(1 == ~T5_E~0); 7097#L674-1 assume !(1 == ~E_1~0); 7459#L679-1 assume !(1 == ~E_2~0); 7191#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 7192#L689-1 assume !(1 == ~E_4~0); 7354#L694-1 assume !(1 == ~E_5~0); 7352#L699-1 assume { :end_inline_reset_delta_events } true; 7353#L900-2 [2022-02-21 04:24:13,534 INFO L793 eck$LassoCheckResult]: Loop: 7353#L900-2 assume !false; 7516#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7050#L561 assume !false; 7135#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7316#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7073#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7074#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7179#L486 assume !(0 != eval_~tmp~0#1); 7181#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7506#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7507#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7458#L586-5 assume !(0 == ~T1_E~0); 7367#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7205#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7206#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7380#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7410#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7411#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7107#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7068#L626-3 assume !(0 == ~E_4~0); 7069#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7075#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7076#L279-18 assume 1 == ~m_pc~0; 7168#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7169#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7290#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7291#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7474#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7385#L298-18 assume !(1 == ~t1_pc~0); 7040#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 7041#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7213#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7236#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7237#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7362#L317-18 assume 1 == ~t2_pc~0; 7268#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7270#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7207#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7208#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7216#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7477#L336-18 assume 1 == ~t3_pc~0; 7460#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7461#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7293#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7294#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7160#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7161#L355-18 assume 1 == ~t4_pc~0; 7434#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7423#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7249#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7250#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7256#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7257#L374-18 assume !(1 == ~t5_pc~0); 7441#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 7321#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7322#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7435#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7417#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7418#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7334#L649-5 assume !(1 == ~T1_E~0); 7315#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7171#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7172#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7077#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7078#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7066#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7067#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7021#L689-3 assume !(1 == ~E_4~0); 7022#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7061#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7062#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7064#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7476#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 7351#L919 assume !(0 == start_simulation_~tmp~3#1); 7080#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7447#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7055#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7300#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 7301#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7346#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7296#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7297#L932 assume !(0 != start_simulation_~tmp___0~1#1); 7353#L900-2 [2022-02-21 04:24:13,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:13,535 INFO L85 PathProgramCache]: Analyzing trace with hash -1698229976, now seen corresponding path program 1 times [2022-02-21 04:24:13,535 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:13,535 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215980682] [2022-02-21 04:24:13,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:13,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:13,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:13,580 INFO L290 TraceCheckUtils]: 0: Hoare triple {8518#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; {8518#true} is VALID [2022-02-21 04:24:13,581 INFO L290 TraceCheckUtils]: 1: Hoare triple {8518#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; {8520#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,581 INFO L290 TraceCheckUtils]: 2: Hoare triple {8520#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {8520#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,581 INFO L290 TraceCheckUtils]: 3: Hoare triple {8520#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {8520#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,582 INFO L290 TraceCheckUtils]: 4: Hoare triple {8520#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {8520#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,582 INFO L290 TraceCheckUtils]: 5: Hoare triple {8520#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {8520#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,582 INFO L290 TraceCheckUtils]: 6: Hoare triple {8520#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {8520#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,583 INFO L290 TraceCheckUtils]: 7: Hoare triple {8520#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {8520#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,583 INFO L290 TraceCheckUtils]: 8: Hoare triple {8520#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {8520#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,583 INFO L290 TraceCheckUtils]: 9: Hoare triple {8520#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {8519#false} is VALID [2022-02-21 04:24:13,584 INFO L290 TraceCheckUtils]: 10: Hoare triple {8519#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {8519#false} is VALID [2022-02-21 04:24:13,584 INFO L290 TraceCheckUtils]: 11: Hoare triple {8519#false} assume 0 == ~M_E~0;~M_E~0 := 1; {8519#false} is VALID [2022-02-21 04:24:13,584 INFO L290 TraceCheckUtils]: 12: Hoare triple {8519#false} assume !(0 == ~T1_E~0); {8519#false} is VALID [2022-02-21 04:24:13,584 INFO L290 TraceCheckUtils]: 13: Hoare triple {8519#false} assume !(0 == ~T2_E~0); {8519#false} is VALID [2022-02-21 04:24:13,584 INFO L290 TraceCheckUtils]: 14: Hoare triple {8519#false} assume !(0 == ~T3_E~0); {8519#false} is VALID [2022-02-21 04:24:13,584 INFO L290 TraceCheckUtils]: 15: Hoare triple {8519#false} assume !(0 == ~T4_E~0); {8519#false} is VALID [2022-02-21 04:24:13,585 INFO L290 TraceCheckUtils]: 16: Hoare triple {8519#false} assume !(0 == ~T5_E~0); {8519#false} is VALID [2022-02-21 04:24:13,585 INFO L290 TraceCheckUtils]: 17: Hoare triple {8519#false} assume !(0 == ~E_1~0); {8519#false} is VALID [2022-02-21 04:24:13,585 INFO L290 TraceCheckUtils]: 18: Hoare triple {8519#false} assume !(0 == ~E_2~0); {8519#false} is VALID [2022-02-21 04:24:13,585 INFO L290 TraceCheckUtils]: 19: Hoare triple {8519#false} assume 0 == ~E_3~0;~E_3~0 := 1; {8519#false} is VALID [2022-02-21 04:24:13,585 INFO L290 TraceCheckUtils]: 20: Hoare triple {8519#false} assume !(0 == ~E_4~0); {8519#false} is VALID [2022-02-21 04:24:13,585 INFO L290 TraceCheckUtils]: 21: Hoare triple {8519#false} assume !(0 == ~E_5~0); {8519#false} is VALID [2022-02-21 04:24:13,585 INFO L290 TraceCheckUtils]: 22: Hoare triple {8519#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8519#false} is VALID [2022-02-21 04:24:13,586 INFO L290 TraceCheckUtils]: 23: Hoare triple {8519#false} assume 1 == ~m_pc~0; {8519#false} is VALID [2022-02-21 04:24:13,586 INFO L290 TraceCheckUtils]: 24: Hoare triple {8519#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {8519#false} is VALID [2022-02-21 04:24:13,586 INFO L290 TraceCheckUtils]: 25: Hoare triple {8519#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8519#false} is VALID [2022-02-21 04:24:13,586 INFO L290 TraceCheckUtils]: 26: Hoare triple {8519#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {8519#false} is VALID [2022-02-21 04:24:13,586 INFO L290 TraceCheckUtils]: 27: Hoare triple {8519#false} assume !(0 != activate_threads_~tmp~1#1); {8519#false} is VALID [2022-02-21 04:24:13,586 INFO L290 TraceCheckUtils]: 28: Hoare triple {8519#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8519#false} is VALID [2022-02-21 04:24:13,586 INFO L290 TraceCheckUtils]: 29: Hoare triple {8519#false} assume !(1 == ~t1_pc~0); {8519#false} is VALID [2022-02-21 04:24:13,587 INFO L290 TraceCheckUtils]: 30: Hoare triple {8519#false} is_transmit1_triggered_~__retres1~1#1 := 0; {8519#false} is VALID [2022-02-21 04:24:13,587 INFO L290 TraceCheckUtils]: 31: Hoare triple {8519#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8519#false} is VALID [2022-02-21 04:24:13,587 INFO L290 TraceCheckUtils]: 32: Hoare triple {8519#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {8519#false} is VALID [2022-02-21 04:24:13,587 INFO L290 TraceCheckUtils]: 33: Hoare triple {8519#false} assume !(0 != activate_threads_~tmp___0~0#1); {8519#false} is VALID [2022-02-21 04:24:13,587 INFO L290 TraceCheckUtils]: 34: Hoare triple {8519#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8519#false} is VALID [2022-02-21 04:24:13,587 INFO L290 TraceCheckUtils]: 35: Hoare triple {8519#false} assume 1 == ~t2_pc~0; {8519#false} is VALID [2022-02-21 04:24:13,588 INFO L290 TraceCheckUtils]: 36: Hoare triple {8519#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8519#false} is VALID [2022-02-21 04:24:13,588 INFO L290 TraceCheckUtils]: 37: Hoare triple {8519#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8519#false} is VALID [2022-02-21 04:24:13,588 INFO L290 TraceCheckUtils]: 38: Hoare triple {8519#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {8519#false} is VALID [2022-02-21 04:24:13,588 INFO L290 TraceCheckUtils]: 39: Hoare triple {8519#false} assume !(0 != activate_threads_~tmp___1~0#1); {8519#false} is VALID [2022-02-21 04:24:13,588 INFO L290 TraceCheckUtils]: 40: Hoare triple {8519#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8519#false} is VALID [2022-02-21 04:24:13,588 INFO L290 TraceCheckUtils]: 41: Hoare triple {8519#false} assume 1 == ~t3_pc~0; {8519#false} is VALID [2022-02-21 04:24:13,588 INFO L290 TraceCheckUtils]: 42: Hoare triple {8519#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {8519#false} is VALID [2022-02-21 04:24:13,589 INFO L290 TraceCheckUtils]: 43: Hoare triple {8519#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8519#false} is VALID [2022-02-21 04:24:13,596 INFO L290 TraceCheckUtils]: 44: Hoare triple {8519#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8519#false} is VALID [2022-02-21 04:24:13,596 INFO L290 TraceCheckUtils]: 45: Hoare triple {8519#false} assume !(0 != activate_threads_~tmp___2~0#1); {8519#false} is VALID [2022-02-21 04:24:13,596 INFO L290 TraceCheckUtils]: 46: Hoare triple {8519#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8519#false} is VALID [2022-02-21 04:24:13,596 INFO L290 TraceCheckUtils]: 47: Hoare triple {8519#false} assume !(1 == ~t4_pc~0); {8519#false} is VALID [2022-02-21 04:24:13,596 INFO L290 TraceCheckUtils]: 48: Hoare triple {8519#false} is_transmit4_triggered_~__retres1~4#1 := 0; {8519#false} is VALID [2022-02-21 04:24:13,596 INFO L290 TraceCheckUtils]: 49: Hoare triple {8519#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8519#false} is VALID [2022-02-21 04:24:13,597 INFO L290 TraceCheckUtils]: 50: Hoare triple {8519#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8519#false} is VALID [2022-02-21 04:24:13,597 INFO L290 TraceCheckUtils]: 51: Hoare triple {8519#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {8519#false} is VALID [2022-02-21 04:24:13,597 INFO L290 TraceCheckUtils]: 52: Hoare triple {8519#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8519#false} is VALID [2022-02-21 04:24:13,597 INFO L290 TraceCheckUtils]: 53: Hoare triple {8519#false} assume 1 == ~t5_pc~0; {8519#false} is VALID [2022-02-21 04:24:13,597 INFO L290 TraceCheckUtils]: 54: Hoare triple {8519#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {8519#false} is VALID [2022-02-21 04:24:13,597 INFO L290 TraceCheckUtils]: 55: Hoare triple {8519#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8519#false} is VALID [2022-02-21 04:24:13,598 INFO L290 TraceCheckUtils]: 56: Hoare triple {8519#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {8519#false} is VALID [2022-02-21 04:24:13,598 INFO L290 TraceCheckUtils]: 57: Hoare triple {8519#false} assume !(0 != activate_threads_~tmp___4~0#1); {8519#false} is VALID [2022-02-21 04:24:13,598 INFO L290 TraceCheckUtils]: 58: Hoare triple {8519#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8519#false} is VALID [2022-02-21 04:24:13,598 INFO L290 TraceCheckUtils]: 59: Hoare triple {8519#false} assume 1 == ~M_E~0;~M_E~0 := 2; {8519#false} is VALID [2022-02-21 04:24:13,598 INFO L290 TraceCheckUtils]: 60: Hoare triple {8519#false} assume !(1 == ~T1_E~0); {8519#false} is VALID [2022-02-21 04:24:13,598 INFO L290 TraceCheckUtils]: 61: Hoare triple {8519#false} assume !(1 == ~T2_E~0); {8519#false} is VALID [2022-02-21 04:24:13,598 INFO L290 TraceCheckUtils]: 62: Hoare triple {8519#false} assume !(1 == ~T3_E~0); {8519#false} is VALID [2022-02-21 04:24:13,599 INFO L290 TraceCheckUtils]: 63: Hoare triple {8519#false} assume !(1 == ~T4_E~0); {8519#false} is VALID [2022-02-21 04:24:13,599 INFO L290 TraceCheckUtils]: 64: Hoare triple {8519#false} assume !(1 == ~T5_E~0); {8519#false} is VALID [2022-02-21 04:24:13,599 INFO L290 TraceCheckUtils]: 65: Hoare triple {8519#false} assume !(1 == ~E_1~0); {8519#false} is VALID [2022-02-21 04:24:13,599 INFO L290 TraceCheckUtils]: 66: Hoare triple {8519#false} assume !(1 == ~E_2~0); {8519#false} is VALID [2022-02-21 04:24:13,599 INFO L290 TraceCheckUtils]: 67: Hoare triple {8519#false} assume 1 == ~E_3~0;~E_3~0 := 2; {8519#false} is VALID [2022-02-21 04:24:13,599 INFO L290 TraceCheckUtils]: 68: Hoare triple {8519#false} assume !(1 == ~E_4~0); {8519#false} is VALID [2022-02-21 04:24:13,599 INFO L290 TraceCheckUtils]: 69: Hoare triple {8519#false} assume !(1 == ~E_5~0); {8519#false} is VALID [2022-02-21 04:24:13,600 INFO L290 TraceCheckUtils]: 70: Hoare triple {8519#false} assume { :end_inline_reset_delta_events } true; {8519#false} is VALID [2022-02-21 04:24:13,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:13,600 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:13,600 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215980682] [2022-02-21 04:24:13,600 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1215980682] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:13,601 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:13,601 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:13,601 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619274437] [2022-02-21 04:24:13,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:13,601 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:13,602 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:13,602 INFO L85 PathProgramCache]: Analyzing trace with hash -1430581779, now seen corresponding path program 1 times [2022-02-21 04:24:13,602 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:13,602 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677858235] [2022-02-21 04:24:13,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:13,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:13,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:13,639 INFO L290 TraceCheckUtils]: 0: Hoare triple {8521#true} assume !false; {8521#true} is VALID [2022-02-21 04:24:13,639 INFO L290 TraceCheckUtils]: 1: Hoare triple {8521#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {8521#true} is VALID [2022-02-21 04:24:13,639 INFO L290 TraceCheckUtils]: 2: Hoare triple {8521#true} assume !false; {8521#true} is VALID [2022-02-21 04:24:13,642 INFO L290 TraceCheckUtils]: 3: Hoare triple {8521#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {8521#true} is VALID [2022-02-21 04:24:13,642 INFO L290 TraceCheckUtils]: 4: Hoare triple {8521#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {8521#true} is VALID [2022-02-21 04:24:13,642 INFO L290 TraceCheckUtils]: 5: Hoare triple {8521#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {8521#true} is VALID [2022-02-21 04:24:13,642 INFO L290 TraceCheckUtils]: 6: Hoare triple {8521#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {8521#true} is VALID [2022-02-21 04:24:13,643 INFO L290 TraceCheckUtils]: 7: Hoare triple {8521#true} assume !(0 != eval_~tmp~0#1); {8521#true} is VALID [2022-02-21 04:24:13,643 INFO L290 TraceCheckUtils]: 8: Hoare triple {8521#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {8521#true} is VALID [2022-02-21 04:24:13,643 INFO L290 TraceCheckUtils]: 9: Hoare triple {8521#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {8521#true} is VALID [2022-02-21 04:24:13,643 INFO L290 TraceCheckUtils]: 10: Hoare triple {8521#true} assume 0 == ~M_E~0;~M_E~0 := 1; {8521#true} is VALID [2022-02-21 04:24:13,643 INFO L290 TraceCheckUtils]: 11: Hoare triple {8521#true} assume !(0 == ~T1_E~0); {8521#true} is VALID [2022-02-21 04:24:13,643 INFO L290 TraceCheckUtils]: 12: Hoare triple {8521#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {8521#true} is VALID [2022-02-21 04:24:13,643 INFO L290 TraceCheckUtils]: 13: Hoare triple {8521#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {8521#true} is VALID [2022-02-21 04:24:13,644 INFO L290 TraceCheckUtils]: 14: Hoare triple {8521#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {8521#true} is VALID [2022-02-21 04:24:13,644 INFO L290 TraceCheckUtils]: 15: Hoare triple {8521#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {8521#true} is VALID [2022-02-21 04:24:13,644 INFO L290 TraceCheckUtils]: 16: Hoare triple {8521#true} assume 0 == ~E_1~0;~E_1~0 := 1; {8521#true} is VALID [2022-02-21 04:24:13,644 INFO L290 TraceCheckUtils]: 17: Hoare triple {8521#true} assume 0 == ~E_2~0;~E_2~0 := 1; {8521#true} is VALID [2022-02-21 04:24:13,644 INFO L290 TraceCheckUtils]: 18: Hoare triple {8521#true} assume 0 == ~E_3~0;~E_3~0 := 1; {8521#true} is VALID [2022-02-21 04:24:13,644 INFO L290 TraceCheckUtils]: 19: Hoare triple {8521#true} assume !(0 == ~E_4~0); {8521#true} is VALID [2022-02-21 04:24:13,644 INFO L290 TraceCheckUtils]: 20: Hoare triple {8521#true} assume 0 == ~E_5~0;~E_5~0 := 1; {8521#true} is VALID [2022-02-21 04:24:13,645 INFO L290 TraceCheckUtils]: 21: Hoare triple {8521#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8521#true} is VALID [2022-02-21 04:24:13,645 INFO L290 TraceCheckUtils]: 22: Hoare triple {8521#true} assume 1 == ~m_pc~0; {8521#true} is VALID [2022-02-21 04:24:13,659 INFO L290 TraceCheckUtils]: 23: Hoare triple {8521#true} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {8521#true} is VALID [2022-02-21 04:24:13,659 INFO L290 TraceCheckUtils]: 24: Hoare triple {8521#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8521#true} is VALID [2022-02-21 04:24:13,659 INFO L290 TraceCheckUtils]: 25: Hoare triple {8521#true} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {8521#true} is VALID [2022-02-21 04:24:13,660 INFO L290 TraceCheckUtils]: 26: Hoare triple {8521#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {8521#true} is VALID [2022-02-21 04:24:13,660 INFO L290 TraceCheckUtils]: 27: Hoare triple {8521#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8521#true} is VALID [2022-02-21 04:24:13,660 INFO L290 TraceCheckUtils]: 28: Hoare triple {8521#true} assume !(1 == ~t1_pc~0); {8521#true} is VALID [2022-02-21 04:24:13,660 INFO L290 TraceCheckUtils]: 29: Hoare triple {8521#true} is_transmit1_triggered_~__retres1~1#1 := 0; {8521#true} is VALID [2022-02-21 04:24:13,660 INFO L290 TraceCheckUtils]: 30: Hoare triple {8521#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8521#true} is VALID [2022-02-21 04:24:13,660 INFO L290 TraceCheckUtils]: 31: Hoare triple {8521#true} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {8521#true} is VALID [2022-02-21 04:24:13,660 INFO L290 TraceCheckUtils]: 32: Hoare triple {8521#true} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8521#true} is VALID [2022-02-21 04:24:13,661 INFO L290 TraceCheckUtils]: 33: Hoare triple {8521#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8521#true} is VALID [2022-02-21 04:24:13,661 INFO L290 TraceCheckUtils]: 34: Hoare triple {8521#true} assume 1 == ~t2_pc~0; {8521#true} is VALID [2022-02-21 04:24:13,661 INFO L290 TraceCheckUtils]: 35: Hoare triple {8521#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8521#true} is VALID [2022-02-21 04:24:13,661 INFO L290 TraceCheckUtils]: 36: Hoare triple {8521#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8521#true} is VALID [2022-02-21 04:24:13,661 INFO L290 TraceCheckUtils]: 37: Hoare triple {8521#true} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {8521#true} is VALID [2022-02-21 04:24:13,661 INFO L290 TraceCheckUtils]: 38: Hoare triple {8521#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {8521#true} is VALID [2022-02-21 04:24:13,662 INFO L290 TraceCheckUtils]: 39: Hoare triple {8521#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8521#true} is VALID [2022-02-21 04:24:13,662 INFO L290 TraceCheckUtils]: 40: Hoare triple {8521#true} assume 1 == ~t3_pc~0; {8521#true} is VALID [2022-02-21 04:24:13,662 INFO L290 TraceCheckUtils]: 41: Hoare triple {8521#true} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {8521#true} is VALID [2022-02-21 04:24:13,662 INFO L290 TraceCheckUtils]: 42: Hoare triple {8521#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8521#true} is VALID [2022-02-21 04:24:13,662 INFO L290 TraceCheckUtils]: 43: Hoare triple {8521#true} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8521#true} is VALID [2022-02-21 04:24:13,662 INFO L290 TraceCheckUtils]: 44: Hoare triple {8521#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {8521#true} is VALID [2022-02-21 04:24:13,662 INFO L290 TraceCheckUtils]: 45: Hoare triple {8521#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8521#true} is VALID [2022-02-21 04:24:13,663 INFO L290 TraceCheckUtils]: 46: Hoare triple {8521#true} assume 1 == ~t4_pc~0; {8521#true} is VALID [2022-02-21 04:24:13,663 INFO L290 TraceCheckUtils]: 47: Hoare triple {8521#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,664 INFO L290 TraceCheckUtils]: 48: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,664 INFO L290 TraceCheckUtils]: 49: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,664 INFO L290 TraceCheckUtils]: 50: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,665 INFO L290 TraceCheckUtils]: 51: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,665 INFO L290 TraceCheckUtils]: 52: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~t5_pc~0); {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,666 INFO L290 TraceCheckUtils]: 53: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,666 INFO L290 TraceCheckUtils]: 54: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,667 INFO L290 TraceCheckUtils]: 55: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,667 INFO L290 TraceCheckUtils]: 56: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,667 INFO L290 TraceCheckUtils]: 57: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,668 INFO L290 TraceCheckUtils]: 58: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,668 INFO L290 TraceCheckUtils]: 59: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~T1_E~0); {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,668 INFO L290 TraceCheckUtils]: 60: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,669 INFO L290 TraceCheckUtils]: 61: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,669 INFO L290 TraceCheckUtils]: 62: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,669 INFO L290 TraceCheckUtils]: 63: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,670 INFO L290 TraceCheckUtils]: 64: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,670 INFO L290 TraceCheckUtils]: 65: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,670 INFO L290 TraceCheckUtils]: 66: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {8523#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:13,671 INFO L290 TraceCheckUtils]: 67: Hoare triple {8523#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~E_4~0); {8522#false} is VALID [2022-02-21 04:24:13,671 INFO L290 TraceCheckUtils]: 68: Hoare triple {8522#false} assume 1 == ~E_5~0;~E_5~0 := 2; {8522#false} is VALID [2022-02-21 04:24:13,671 INFO L290 TraceCheckUtils]: 69: Hoare triple {8522#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {8522#false} is VALID [2022-02-21 04:24:13,671 INFO L290 TraceCheckUtils]: 70: Hoare triple {8522#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {8522#false} is VALID [2022-02-21 04:24:13,671 INFO L290 TraceCheckUtils]: 71: Hoare triple {8522#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {8522#false} is VALID [2022-02-21 04:24:13,671 INFO L290 TraceCheckUtils]: 72: Hoare triple {8522#false} start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {8522#false} is VALID [2022-02-21 04:24:13,672 INFO L290 TraceCheckUtils]: 73: Hoare triple {8522#false} assume !(0 == start_simulation_~tmp~3#1); {8522#false} is VALID [2022-02-21 04:24:13,672 INFO L290 TraceCheckUtils]: 74: Hoare triple {8522#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {8522#false} is VALID [2022-02-21 04:24:13,672 INFO L290 TraceCheckUtils]: 75: Hoare triple {8522#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {8522#false} is VALID [2022-02-21 04:24:13,672 INFO L290 TraceCheckUtils]: 76: Hoare triple {8522#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {8522#false} is VALID [2022-02-21 04:24:13,672 INFO L290 TraceCheckUtils]: 77: Hoare triple {8522#false} stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; {8522#false} is VALID [2022-02-21 04:24:13,672 INFO L290 TraceCheckUtils]: 78: Hoare triple {8522#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {8522#false} is VALID [2022-02-21 04:24:13,672 INFO L290 TraceCheckUtils]: 79: Hoare triple {8522#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {8522#false} is VALID [2022-02-21 04:24:13,673 INFO L290 TraceCheckUtils]: 80: Hoare triple {8522#false} start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; {8522#false} is VALID [2022-02-21 04:24:13,673 INFO L290 TraceCheckUtils]: 81: Hoare triple {8522#false} assume !(0 != start_simulation_~tmp___0~1#1); {8522#false} is VALID [2022-02-21 04:24:13,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:13,674 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:13,674 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [677858235] [2022-02-21 04:24:13,674 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [677858235] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:13,674 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:13,674 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:13,674 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [616138290] [2022-02-21 04:24:13,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:13,675 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:13,675 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:13,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:13,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:13,676 INFO L87 Difference]: Start difference. First operand 498 states and 743 transitions. cyclomatic complexity: 246 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:14,122 INFO L93 Difference]: Finished difference Result 498 states and 742 transitions. [2022-02-21 04:24:14,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:14,123 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,178 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:14,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 498 states and 742 transitions. [2022-02-21 04:24:14,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-02-21 04:24:14,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 498 states to 498 states and 742 transitions. [2022-02-21 04:24:14,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 498 [2022-02-21 04:24:14,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 498 [2022-02-21 04:24:14,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 498 states and 742 transitions. [2022-02-21 04:24:14,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:14,209 INFO L681 BuchiCegarLoop]: Abstraction has 498 states and 742 transitions. [2022-02-21 04:24:14,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states and 742 transitions. [2022-02-21 04:24:14,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 498. [2022-02-21 04:24:14,215 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:14,216 INFO L82 GeneralOperation]: Start isEquivalent. First operand 498 states and 742 transitions. Second operand has 498 states, 498 states have (on average 1.4899598393574298) internal successors, (742), 497 states have internal predecessors, (742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,217 INFO L74 IsIncluded]: Start isIncluded. First operand 498 states and 742 transitions. Second operand has 498 states, 498 states have (on average 1.4899598393574298) internal successors, (742), 497 states have internal predecessors, (742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,218 INFO L87 Difference]: Start difference. First operand 498 states and 742 transitions. Second operand has 498 states, 498 states have (on average 1.4899598393574298) internal successors, (742), 497 states have internal predecessors, (742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:14,231 INFO L93 Difference]: Finished difference Result 498 states and 742 transitions. [2022-02-21 04:24:14,231 INFO L276 IsEmpty]: Start isEmpty. Operand 498 states and 742 transitions. [2022-02-21 04:24:14,232 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:14,232 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:14,233 INFO L74 IsIncluded]: Start isIncluded. First operand has 498 states, 498 states have (on average 1.4899598393574298) internal successors, (742), 497 states have internal predecessors, (742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 498 states and 742 transitions. [2022-02-21 04:24:14,234 INFO L87 Difference]: Start difference. First operand has 498 states, 498 states have (on average 1.4899598393574298) internal successors, (742), 497 states have internal predecessors, (742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 498 states and 742 transitions. [2022-02-21 04:24:14,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:14,247 INFO L93 Difference]: Finished difference Result 498 states and 742 transitions. [2022-02-21 04:24:14,247 INFO L276 IsEmpty]: Start isEmpty. Operand 498 states and 742 transitions. [2022-02-21 04:24:14,248 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:14,248 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:14,248 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:14,248 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:14,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 498 states, 498 states have (on average 1.4899598393574298) internal successors, (742), 497 states have internal predecessors, (742), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 742 transitions. [2022-02-21 04:24:14,262 INFO L704 BuchiCegarLoop]: Abstraction has 498 states and 742 transitions. [2022-02-21 04:24:14,262 INFO L587 BuchiCegarLoop]: Abstraction has 498 states and 742 transitions. [2022-02-21 04:24:14,262 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:14,262 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 742 transitions. [2022-02-21 04:24:14,265 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 421 [2022-02-21 04:24:14,265 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:14,265 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:14,269 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:14,269 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:14,269 INFO L791 eck$LassoCheckResult]: Stem: 9519#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 9505#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9497#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9495#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9409#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 9410#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9215#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9216#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9493#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9494#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9466#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9187#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 9188#L586-2 assume !(0 == ~T1_E~0); 9241#L591-1 assume !(0 == ~T2_E~0); 9361#L596-1 assume !(0 == ~T3_E~0); 9362#L601-1 assume !(0 == ~T4_E~0); 9400#L606-1 assume !(0 == ~T5_E~0); 9401#L611-1 assume !(0 == ~E_1~0); 9472#L616-1 assume !(0 == ~E_2~0); 9473#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9120#L626-1 assume !(0 == ~E_4~0); 9121#L631-1 assume !(0 == ~E_5~0); 9276#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9115#L279 assume 1 == ~m_pc~0; 9116#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9367#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9343#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9344#L720 assume !(0 != activate_threads_~tmp~1#1); 9417#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9280#L298 assume !(1 == ~t1_pc~0); 9072#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9073#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9332#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9129#L728 assume !(0 != activate_threads_~tmp___0~0#1); 9130#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9247#L317 assume 1 == ~t2_pc~0; 9248#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9394#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9501#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9289#L736 assume !(0 != activate_threads_~tmp___1~0#1); 9290#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9464#L336 assume 1 == ~t3_pc~0; 9336#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9337#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9384#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9385#L744 assume !(0 != activate_threads_~tmp___2~0#1); 9425#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9469#L355 assume !(1 == ~t4_pc~0); 9358#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9201#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9202#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9413#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9139#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9140#L374 assume 1 == ~t5_pc~0; 9487#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9268#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9341#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9342#L760 assume !(0 != activate_threads_~tmp___4~0#1); 9387#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9388#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 9510#L649-2 assume !(1 == ~T1_E~0); 9104#L654-1 assume !(1 == ~T2_E~0); 9105#L659-1 assume !(1 == ~T3_E~0); 9288#L664-1 assume !(1 == ~T4_E~0); 9097#L669-1 assume !(1 == ~T5_E~0); 9098#L674-1 assume !(1 == ~E_1~0); 9460#L679-1 assume !(1 == ~E_2~0); 9192#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9193#L689-1 assume !(1 == ~E_4~0); 9355#L694-1 assume !(1 == ~E_5~0); 9353#L699-1 assume { :end_inline_reset_delta_events } true; 9354#L900-2 [2022-02-21 04:24:14,269 INFO L793 eck$LassoCheckResult]: Loop: 9354#L900-2 assume !false; 9517#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9051#L561 assume !false; 9136#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9317#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9074#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9075#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9180#L486 assume !(0 != eval_~tmp~0#1); 9182#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9507#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9508#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9459#L586-5 assume !(0 == ~T1_E~0); 9368#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9206#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9207#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9381#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9411#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9412#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9108#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9069#L626-3 assume !(0 == ~E_4~0); 9070#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9076#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9077#L279-18 assume 1 == ~m_pc~0; 9169#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9170#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9291#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9292#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9475#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9386#L298-18 assume !(1 == ~t1_pc~0); 9041#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 9042#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9214#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9237#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9238#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9363#L317-18 assume 1 == ~t2_pc~0; 9269#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9271#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9208#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9209#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9217#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9478#L336-18 assume 1 == ~t3_pc~0; 9461#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9462#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9294#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9295#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9161#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9162#L355-18 assume 1 == ~t4_pc~0; 9435#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9424#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9250#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9251#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9257#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9258#L374-18 assume !(1 == ~t5_pc~0); 9442#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 9322#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9323#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9436#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9418#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9419#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9335#L649-5 assume !(1 == ~T1_E~0); 9316#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9172#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9173#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9078#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9079#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9067#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9068#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9022#L689-3 assume !(1 == ~E_4~0); 9023#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9062#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9063#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9065#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9477#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 9352#L919 assume !(0 == start_simulation_~tmp~3#1); 9081#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9448#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9056#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9301#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 9302#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9347#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9297#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9298#L932 assume !(0 != start_simulation_~tmp___0~1#1); 9354#L900-2 [2022-02-21 04:24:14,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:14,270 INFO L85 PathProgramCache]: Analyzing trace with hash 1917465066, now seen corresponding path program 1 times [2022-02-21 04:24:14,271 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:14,272 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286073749] [2022-02-21 04:24:14,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:14,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:14,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:14,324 INFO L290 TraceCheckUtils]: 0: Hoare triple {10519#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; {10521#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:14,325 INFO L290 TraceCheckUtils]: 1: Hoare triple {10521#(<= 2 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; {10521#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:14,325 INFO L290 TraceCheckUtils]: 2: Hoare triple {10521#(<= 2 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10521#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:14,326 INFO L290 TraceCheckUtils]: 3: Hoare triple {10521#(<= 2 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10521#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:14,326 INFO L290 TraceCheckUtils]: 4: Hoare triple {10521#(<= 2 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {10521#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:14,326 INFO L290 TraceCheckUtils]: 5: Hoare triple {10521#(<= 2 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10521#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:14,327 INFO L290 TraceCheckUtils]: 6: Hoare triple {10521#(<= 2 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {10521#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:14,328 INFO L290 TraceCheckUtils]: 7: Hoare triple {10521#(<= 2 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {10521#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:14,328 INFO L290 TraceCheckUtils]: 8: Hoare triple {10521#(<= 2 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {10521#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:14,329 INFO L290 TraceCheckUtils]: 9: Hoare triple {10521#(<= 2 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {10521#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:14,329 INFO L290 TraceCheckUtils]: 10: Hoare triple {10521#(<= 2 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10521#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:14,330 INFO L290 TraceCheckUtils]: 11: Hoare triple {10521#(<= 2 ~M_E~0)} assume 0 == ~M_E~0;~M_E~0 := 1; {10520#false} is VALID [2022-02-21 04:24:14,330 INFO L290 TraceCheckUtils]: 12: Hoare triple {10520#false} assume !(0 == ~T1_E~0); {10520#false} is VALID [2022-02-21 04:24:14,330 INFO L290 TraceCheckUtils]: 13: Hoare triple {10520#false} assume !(0 == ~T2_E~0); {10520#false} is VALID [2022-02-21 04:24:14,330 INFO L290 TraceCheckUtils]: 14: Hoare triple {10520#false} assume !(0 == ~T3_E~0); {10520#false} is VALID [2022-02-21 04:24:14,330 INFO L290 TraceCheckUtils]: 15: Hoare triple {10520#false} assume !(0 == ~T4_E~0); {10520#false} is VALID [2022-02-21 04:24:14,330 INFO L290 TraceCheckUtils]: 16: Hoare triple {10520#false} assume !(0 == ~T5_E~0); {10520#false} is VALID [2022-02-21 04:24:14,331 INFO L290 TraceCheckUtils]: 17: Hoare triple {10520#false} assume !(0 == ~E_1~0); {10520#false} is VALID [2022-02-21 04:24:14,331 INFO L290 TraceCheckUtils]: 18: Hoare triple {10520#false} assume !(0 == ~E_2~0); {10520#false} is VALID [2022-02-21 04:24:14,331 INFO L290 TraceCheckUtils]: 19: Hoare triple {10520#false} assume 0 == ~E_3~0;~E_3~0 := 1; {10520#false} is VALID [2022-02-21 04:24:14,331 INFO L290 TraceCheckUtils]: 20: Hoare triple {10520#false} assume !(0 == ~E_4~0); {10520#false} is VALID [2022-02-21 04:24:14,331 INFO L290 TraceCheckUtils]: 21: Hoare triple {10520#false} assume !(0 == ~E_5~0); {10520#false} is VALID [2022-02-21 04:24:14,331 INFO L290 TraceCheckUtils]: 22: Hoare triple {10520#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10520#false} is VALID [2022-02-21 04:24:14,332 INFO L290 TraceCheckUtils]: 23: Hoare triple {10520#false} assume 1 == ~m_pc~0; {10520#false} is VALID [2022-02-21 04:24:14,332 INFO L290 TraceCheckUtils]: 24: Hoare triple {10520#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {10520#false} is VALID [2022-02-21 04:24:14,332 INFO L290 TraceCheckUtils]: 25: Hoare triple {10520#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10520#false} is VALID [2022-02-21 04:24:14,332 INFO L290 TraceCheckUtils]: 26: Hoare triple {10520#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {10520#false} is VALID [2022-02-21 04:24:14,332 INFO L290 TraceCheckUtils]: 27: Hoare triple {10520#false} assume !(0 != activate_threads_~tmp~1#1); {10520#false} is VALID [2022-02-21 04:24:14,332 INFO L290 TraceCheckUtils]: 28: Hoare triple {10520#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10520#false} is VALID [2022-02-21 04:24:14,332 INFO L290 TraceCheckUtils]: 29: Hoare triple {10520#false} assume !(1 == ~t1_pc~0); {10520#false} is VALID [2022-02-21 04:24:14,333 INFO L290 TraceCheckUtils]: 30: Hoare triple {10520#false} is_transmit1_triggered_~__retres1~1#1 := 0; {10520#false} is VALID [2022-02-21 04:24:14,333 INFO L290 TraceCheckUtils]: 31: Hoare triple {10520#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10520#false} is VALID [2022-02-21 04:24:14,333 INFO L290 TraceCheckUtils]: 32: Hoare triple {10520#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {10520#false} is VALID [2022-02-21 04:24:14,333 INFO L290 TraceCheckUtils]: 33: Hoare triple {10520#false} assume !(0 != activate_threads_~tmp___0~0#1); {10520#false} is VALID [2022-02-21 04:24:14,333 INFO L290 TraceCheckUtils]: 34: Hoare triple {10520#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10520#false} is VALID [2022-02-21 04:24:14,334 INFO L290 TraceCheckUtils]: 35: Hoare triple {10520#false} assume 1 == ~t2_pc~0; {10520#false} is VALID [2022-02-21 04:24:14,334 INFO L290 TraceCheckUtils]: 36: Hoare triple {10520#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10520#false} is VALID [2022-02-21 04:24:14,334 INFO L290 TraceCheckUtils]: 37: Hoare triple {10520#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10520#false} is VALID [2022-02-21 04:24:14,334 INFO L290 TraceCheckUtils]: 38: Hoare triple {10520#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {10520#false} is VALID [2022-02-21 04:24:14,334 INFO L290 TraceCheckUtils]: 39: Hoare triple {10520#false} assume !(0 != activate_threads_~tmp___1~0#1); {10520#false} is VALID [2022-02-21 04:24:14,334 INFO L290 TraceCheckUtils]: 40: Hoare triple {10520#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10520#false} is VALID [2022-02-21 04:24:14,334 INFO L290 TraceCheckUtils]: 41: Hoare triple {10520#false} assume 1 == ~t3_pc~0; {10520#false} is VALID [2022-02-21 04:24:14,335 INFO L290 TraceCheckUtils]: 42: Hoare triple {10520#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {10520#false} is VALID [2022-02-21 04:24:14,335 INFO L290 TraceCheckUtils]: 43: Hoare triple {10520#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10520#false} is VALID [2022-02-21 04:24:14,335 INFO L290 TraceCheckUtils]: 44: Hoare triple {10520#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {10520#false} is VALID [2022-02-21 04:24:14,335 INFO L290 TraceCheckUtils]: 45: Hoare triple {10520#false} assume !(0 != activate_threads_~tmp___2~0#1); {10520#false} is VALID [2022-02-21 04:24:14,335 INFO L290 TraceCheckUtils]: 46: Hoare triple {10520#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10520#false} is VALID [2022-02-21 04:24:14,335 INFO L290 TraceCheckUtils]: 47: Hoare triple {10520#false} assume !(1 == ~t4_pc~0); {10520#false} is VALID [2022-02-21 04:24:14,336 INFO L290 TraceCheckUtils]: 48: Hoare triple {10520#false} is_transmit4_triggered_~__retres1~4#1 := 0; {10520#false} is VALID [2022-02-21 04:24:14,336 INFO L290 TraceCheckUtils]: 49: Hoare triple {10520#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10520#false} is VALID [2022-02-21 04:24:14,336 INFO L290 TraceCheckUtils]: 50: Hoare triple {10520#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {10520#false} is VALID [2022-02-21 04:24:14,336 INFO L290 TraceCheckUtils]: 51: Hoare triple {10520#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {10520#false} is VALID [2022-02-21 04:24:14,336 INFO L290 TraceCheckUtils]: 52: Hoare triple {10520#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10520#false} is VALID [2022-02-21 04:24:14,336 INFO L290 TraceCheckUtils]: 53: Hoare triple {10520#false} assume 1 == ~t5_pc~0; {10520#false} is VALID [2022-02-21 04:24:14,337 INFO L290 TraceCheckUtils]: 54: Hoare triple {10520#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {10520#false} is VALID [2022-02-21 04:24:14,337 INFO L290 TraceCheckUtils]: 55: Hoare triple {10520#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10520#false} is VALID [2022-02-21 04:24:14,337 INFO L290 TraceCheckUtils]: 56: Hoare triple {10520#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10520#false} is VALID [2022-02-21 04:24:14,337 INFO L290 TraceCheckUtils]: 57: Hoare triple {10520#false} assume !(0 != activate_threads_~tmp___4~0#1); {10520#false} is VALID [2022-02-21 04:24:14,337 INFO L290 TraceCheckUtils]: 58: Hoare triple {10520#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10520#false} is VALID [2022-02-21 04:24:14,337 INFO L290 TraceCheckUtils]: 59: Hoare triple {10520#false} assume 1 == ~M_E~0;~M_E~0 := 2; {10520#false} is VALID [2022-02-21 04:24:14,338 INFO L290 TraceCheckUtils]: 60: Hoare triple {10520#false} assume !(1 == ~T1_E~0); {10520#false} is VALID [2022-02-21 04:24:14,338 INFO L290 TraceCheckUtils]: 61: Hoare triple {10520#false} assume !(1 == ~T2_E~0); {10520#false} is VALID [2022-02-21 04:24:14,338 INFO L290 TraceCheckUtils]: 62: Hoare triple {10520#false} assume !(1 == ~T3_E~0); {10520#false} is VALID [2022-02-21 04:24:14,338 INFO L290 TraceCheckUtils]: 63: Hoare triple {10520#false} assume !(1 == ~T4_E~0); {10520#false} is VALID [2022-02-21 04:24:14,338 INFO L290 TraceCheckUtils]: 64: Hoare triple {10520#false} assume !(1 == ~T5_E~0); {10520#false} is VALID [2022-02-21 04:24:14,338 INFO L290 TraceCheckUtils]: 65: Hoare triple {10520#false} assume !(1 == ~E_1~0); {10520#false} is VALID [2022-02-21 04:24:14,339 INFO L290 TraceCheckUtils]: 66: Hoare triple {10520#false} assume !(1 == ~E_2~0); {10520#false} is VALID [2022-02-21 04:24:14,339 INFO L290 TraceCheckUtils]: 67: Hoare triple {10520#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10520#false} is VALID [2022-02-21 04:24:14,339 INFO L290 TraceCheckUtils]: 68: Hoare triple {10520#false} assume !(1 == ~E_4~0); {10520#false} is VALID [2022-02-21 04:24:14,339 INFO L290 TraceCheckUtils]: 69: Hoare triple {10520#false} assume !(1 == ~E_5~0); {10520#false} is VALID [2022-02-21 04:24:14,339 INFO L290 TraceCheckUtils]: 70: Hoare triple {10520#false} assume { :end_inline_reset_delta_events } true; {10520#false} is VALID [2022-02-21 04:24:14,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:14,340 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:14,341 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1286073749] [2022-02-21 04:24:14,341 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1286073749] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:14,341 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:14,341 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:14,342 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [947846911] [2022-02-21 04:24:14,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:14,342 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:14,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:14,343 INFO L85 PathProgramCache]: Analyzing trace with hash -1430581779, now seen corresponding path program 2 times [2022-02-21 04:24:14,343 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:14,346 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328979921] [2022-02-21 04:24:14,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:14,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:14,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:14,391 INFO L290 TraceCheckUtils]: 0: Hoare triple {10522#true} assume !false; {10522#true} is VALID [2022-02-21 04:24:14,391 INFO L290 TraceCheckUtils]: 1: Hoare triple {10522#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10522#true} is VALID [2022-02-21 04:24:14,391 INFO L290 TraceCheckUtils]: 2: Hoare triple {10522#true} assume !false; {10522#true} is VALID [2022-02-21 04:24:14,391 INFO L290 TraceCheckUtils]: 3: Hoare triple {10522#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {10522#true} is VALID [2022-02-21 04:24:14,391 INFO L290 TraceCheckUtils]: 4: Hoare triple {10522#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {10522#true} is VALID [2022-02-21 04:24:14,392 INFO L290 TraceCheckUtils]: 5: Hoare triple {10522#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {10522#true} is VALID [2022-02-21 04:24:14,392 INFO L290 TraceCheckUtils]: 6: Hoare triple {10522#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {10522#true} is VALID [2022-02-21 04:24:14,392 INFO L290 TraceCheckUtils]: 7: Hoare triple {10522#true} assume !(0 != eval_~tmp~0#1); {10522#true} is VALID [2022-02-21 04:24:14,392 INFO L290 TraceCheckUtils]: 8: Hoare triple {10522#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10522#true} is VALID [2022-02-21 04:24:14,392 INFO L290 TraceCheckUtils]: 9: Hoare triple {10522#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10522#true} is VALID [2022-02-21 04:24:14,392 INFO L290 TraceCheckUtils]: 10: Hoare triple {10522#true} assume 0 == ~M_E~0;~M_E~0 := 1; {10522#true} is VALID [2022-02-21 04:24:14,392 INFO L290 TraceCheckUtils]: 11: Hoare triple {10522#true} assume !(0 == ~T1_E~0); {10522#true} is VALID [2022-02-21 04:24:14,393 INFO L290 TraceCheckUtils]: 12: Hoare triple {10522#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {10522#true} is VALID [2022-02-21 04:24:14,393 INFO L290 TraceCheckUtils]: 13: Hoare triple {10522#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10522#true} is VALID [2022-02-21 04:24:14,393 INFO L290 TraceCheckUtils]: 14: Hoare triple {10522#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {10522#true} is VALID [2022-02-21 04:24:14,393 INFO L290 TraceCheckUtils]: 15: Hoare triple {10522#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {10522#true} is VALID [2022-02-21 04:24:14,393 INFO L290 TraceCheckUtils]: 16: Hoare triple {10522#true} assume 0 == ~E_1~0;~E_1~0 := 1; {10522#true} is VALID [2022-02-21 04:24:14,393 INFO L290 TraceCheckUtils]: 17: Hoare triple {10522#true} assume 0 == ~E_2~0;~E_2~0 := 1; {10522#true} is VALID [2022-02-21 04:24:14,393 INFO L290 TraceCheckUtils]: 18: Hoare triple {10522#true} assume 0 == ~E_3~0;~E_3~0 := 1; {10522#true} is VALID [2022-02-21 04:24:14,394 INFO L290 TraceCheckUtils]: 19: Hoare triple {10522#true} assume !(0 == ~E_4~0); {10522#true} is VALID [2022-02-21 04:24:14,394 INFO L290 TraceCheckUtils]: 20: Hoare triple {10522#true} assume 0 == ~E_5~0;~E_5~0 := 1; {10522#true} is VALID [2022-02-21 04:24:14,394 INFO L290 TraceCheckUtils]: 21: Hoare triple {10522#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10522#true} is VALID [2022-02-21 04:24:14,394 INFO L290 TraceCheckUtils]: 22: Hoare triple {10522#true} assume 1 == ~m_pc~0; {10522#true} is VALID [2022-02-21 04:24:14,394 INFO L290 TraceCheckUtils]: 23: Hoare triple {10522#true} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {10522#true} is VALID [2022-02-21 04:24:14,394 INFO L290 TraceCheckUtils]: 24: Hoare triple {10522#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10522#true} is VALID [2022-02-21 04:24:14,394 INFO L290 TraceCheckUtils]: 25: Hoare triple {10522#true} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {10522#true} is VALID [2022-02-21 04:24:14,395 INFO L290 TraceCheckUtils]: 26: Hoare triple {10522#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10522#true} is VALID [2022-02-21 04:24:14,395 INFO L290 TraceCheckUtils]: 27: Hoare triple {10522#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10522#true} is VALID [2022-02-21 04:24:14,395 INFO L290 TraceCheckUtils]: 28: Hoare triple {10522#true} assume !(1 == ~t1_pc~0); {10522#true} is VALID [2022-02-21 04:24:14,395 INFO L290 TraceCheckUtils]: 29: Hoare triple {10522#true} is_transmit1_triggered_~__retres1~1#1 := 0; {10522#true} is VALID [2022-02-21 04:24:14,395 INFO L290 TraceCheckUtils]: 30: Hoare triple {10522#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10522#true} is VALID [2022-02-21 04:24:14,395 INFO L290 TraceCheckUtils]: 31: Hoare triple {10522#true} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {10522#true} is VALID [2022-02-21 04:24:14,395 INFO L290 TraceCheckUtils]: 32: Hoare triple {10522#true} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10522#true} is VALID [2022-02-21 04:24:14,396 INFO L290 TraceCheckUtils]: 33: Hoare triple {10522#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10522#true} is VALID [2022-02-21 04:24:14,396 INFO L290 TraceCheckUtils]: 34: Hoare triple {10522#true} assume 1 == ~t2_pc~0; {10522#true} is VALID [2022-02-21 04:24:14,396 INFO L290 TraceCheckUtils]: 35: Hoare triple {10522#true} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10522#true} is VALID [2022-02-21 04:24:14,396 INFO L290 TraceCheckUtils]: 36: Hoare triple {10522#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10522#true} is VALID [2022-02-21 04:24:14,396 INFO L290 TraceCheckUtils]: 37: Hoare triple {10522#true} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {10522#true} is VALID [2022-02-21 04:24:14,396 INFO L290 TraceCheckUtils]: 38: Hoare triple {10522#true} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10522#true} is VALID [2022-02-21 04:24:14,396 INFO L290 TraceCheckUtils]: 39: Hoare triple {10522#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10522#true} is VALID [2022-02-21 04:24:14,397 INFO L290 TraceCheckUtils]: 40: Hoare triple {10522#true} assume 1 == ~t3_pc~0; {10522#true} is VALID [2022-02-21 04:24:14,397 INFO L290 TraceCheckUtils]: 41: Hoare triple {10522#true} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {10522#true} is VALID [2022-02-21 04:24:14,397 INFO L290 TraceCheckUtils]: 42: Hoare triple {10522#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10522#true} is VALID [2022-02-21 04:24:14,397 INFO L290 TraceCheckUtils]: 43: Hoare triple {10522#true} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {10522#true} is VALID [2022-02-21 04:24:14,397 INFO L290 TraceCheckUtils]: 44: Hoare triple {10522#true} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10522#true} is VALID [2022-02-21 04:24:14,397 INFO L290 TraceCheckUtils]: 45: Hoare triple {10522#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10522#true} is VALID [2022-02-21 04:24:14,397 INFO L290 TraceCheckUtils]: 46: Hoare triple {10522#true} assume 1 == ~t4_pc~0; {10522#true} is VALID [2022-02-21 04:24:14,398 INFO L290 TraceCheckUtils]: 47: Hoare triple {10522#true} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,398 INFO L290 TraceCheckUtils]: 48: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,399 INFO L290 TraceCheckUtils]: 49: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,399 INFO L290 TraceCheckUtils]: 50: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,399 INFO L290 TraceCheckUtils]: 51: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,400 INFO L290 TraceCheckUtils]: 52: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~t5_pc~0); {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,400 INFO L290 TraceCheckUtils]: 53: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,401 INFO L290 TraceCheckUtils]: 54: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,401 INFO L290 TraceCheckUtils]: 55: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,401 INFO L290 TraceCheckUtils]: 56: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,402 INFO L290 TraceCheckUtils]: 57: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,402 INFO L290 TraceCheckUtils]: 58: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,402 INFO L290 TraceCheckUtils]: 59: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~T1_E~0); {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,403 INFO L290 TraceCheckUtils]: 60: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,403 INFO L290 TraceCheckUtils]: 61: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,403 INFO L290 TraceCheckUtils]: 62: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,404 INFO L290 TraceCheckUtils]: 63: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,404 INFO L290 TraceCheckUtils]: 64: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_1~0;~E_1~0 := 2; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,404 INFO L290 TraceCheckUtils]: 65: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_2~0;~E_2~0 := 2; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,405 INFO L290 TraceCheckUtils]: 66: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume 1 == ~E_3~0;~E_3~0 := 2; {10524#(= (+ (- 1) ~E_4~0) 0)} is VALID [2022-02-21 04:24:14,405 INFO L290 TraceCheckUtils]: 67: Hoare triple {10524#(= (+ (- 1) ~E_4~0) 0)} assume !(1 == ~E_4~0); {10523#false} is VALID [2022-02-21 04:24:14,405 INFO L290 TraceCheckUtils]: 68: Hoare triple {10523#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10523#false} is VALID [2022-02-21 04:24:14,405 INFO L290 TraceCheckUtils]: 69: Hoare triple {10523#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {10523#false} is VALID [2022-02-21 04:24:14,405 INFO L290 TraceCheckUtils]: 70: Hoare triple {10523#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {10523#false} is VALID [2022-02-21 04:24:14,406 INFO L290 TraceCheckUtils]: 71: Hoare triple {10523#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {10523#false} is VALID [2022-02-21 04:24:14,406 INFO L290 TraceCheckUtils]: 72: Hoare triple {10523#false} start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {10523#false} is VALID [2022-02-21 04:24:14,406 INFO L290 TraceCheckUtils]: 73: Hoare triple {10523#false} assume !(0 == start_simulation_~tmp~3#1); {10523#false} is VALID [2022-02-21 04:24:14,406 INFO L290 TraceCheckUtils]: 74: Hoare triple {10523#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {10523#false} is VALID [2022-02-21 04:24:14,406 INFO L290 TraceCheckUtils]: 75: Hoare triple {10523#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {10523#false} is VALID [2022-02-21 04:24:14,406 INFO L290 TraceCheckUtils]: 76: Hoare triple {10523#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {10523#false} is VALID [2022-02-21 04:24:14,406 INFO L290 TraceCheckUtils]: 77: Hoare triple {10523#false} stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; {10523#false} is VALID [2022-02-21 04:24:14,406 INFO L290 TraceCheckUtils]: 78: Hoare triple {10523#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {10523#false} is VALID [2022-02-21 04:24:14,407 INFO L290 TraceCheckUtils]: 79: Hoare triple {10523#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10523#false} is VALID [2022-02-21 04:24:14,407 INFO L290 TraceCheckUtils]: 80: Hoare triple {10523#false} start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; {10523#false} is VALID [2022-02-21 04:24:14,407 INFO L290 TraceCheckUtils]: 81: Hoare triple {10523#false} assume !(0 != start_simulation_~tmp___0~1#1); {10523#false} is VALID [2022-02-21 04:24:14,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:14,408 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:14,408 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [328979921] [2022-02-21 04:24:14,408 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [328979921] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:14,408 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:14,409 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:14,409 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2054174147] [2022-02-21 04:24:14,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:14,409 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:14,410 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:14,410 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:14,410 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:14,410 INFO L87 Difference]: Start difference. First operand 498 states and 742 transitions. cyclomatic complexity: 245 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:15,129 INFO L93 Difference]: Finished difference Result 875 states and 1292 transitions. [2022-02-21 04:24:15,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:15,130 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,203 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:15,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 875 states and 1292 transitions. [2022-02-21 04:24:15,238 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 798 [2022-02-21 04:24:15,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 875 states to 875 states and 1292 transitions. [2022-02-21 04:24:15,270 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 875 [2022-02-21 04:24:15,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 875 [2022-02-21 04:24:15,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 875 states and 1292 transitions. [2022-02-21 04:24:15,271 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:15,271 INFO L681 BuchiCegarLoop]: Abstraction has 875 states and 1292 transitions. [2022-02-21 04:24:15,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 875 states and 1292 transitions. [2022-02-21 04:24:15,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 875 to 875. [2022-02-21 04:24:15,283 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:15,284 INFO L82 GeneralOperation]: Start isEquivalent. First operand 875 states and 1292 transitions. Second operand has 875 states, 875 states have (on average 1.4765714285714286) internal successors, (1292), 874 states have internal predecessors, (1292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,286 INFO L74 IsIncluded]: Start isIncluded. First operand 875 states and 1292 transitions. Second operand has 875 states, 875 states have (on average 1.4765714285714286) internal successors, (1292), 874 states have internal predecessors, (1292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,287 INFO L87 Difference]: Start difference. First operand 875 states and 1292 transitions. Second operand has 875 states, 875 states have (on average 1.4765714285714286) internal successors, (1292), 874 states have internal predecessors, (1292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:15,318 INFO L93 Difference]: Finished difference Result 875 states and 1292 transitions. [2022-02-21 04:24:15,319 INFO L276 IsEmpty]: Start isEmpty. Operand 875 states and 1292 transitions. [2022-02-21 04:24:15,320 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:15,320 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:15,322 INFO L74 IsIncluded]: Start isIncluded. First operand has 875 states, 875 states have (on average 1.4765714285714286) internal successors, (1292), 874 states have internal predecessors, (1292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 875 states and 1292 transitions. [2022-02-21 04:24:15,323 INFO L87 Difference]: Start difference. First operand has 875 states, 875 states have (on average 1.4765714285714286) internal successors, (1292), 874 states have internal predecessors, (1292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 875 states and 1292 transitions. [2022-02-21 04:24:15,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:15,356 INFO L93 Difference]: Finished difference Result 875 states and 1292 transitions. [2022-02-21 04:24:15,356 INFO L276 IsEmpty]: Start isEmpty. Operand 875 states and 1292 transitions. [2022-02-21 04:24:15,357 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:15,357 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:15,357 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:15,357 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:15,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 875 states, 875 states have (on average 1.4765714285714286) internal successors, (1292), 874 states have internal predecessors, (1292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 875 states to 875 states and 1292 transitions. [2022-02-21 04:24:15,390 INFO L704 BuchiCegarLoop]: Abstraction has 875 states and 1292 transitions. [2022-02-21 04:24:15,390 INFO L587 BuchiCegarLoop]: Abstraction has 875 states and 1292 transitions. [2022-02-21 04:24:15,391 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:15,391 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 875 states and 1292 transitions. [2022-02-21 04:24:15,394 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 798 [2022-02-21 04:24:15,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:15,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:15,395 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:15,395 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:15,396 INFO L791 eck$LassoCheckResult]: Stem: 11915#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 11895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 11887#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11885#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11790#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 11791#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11595#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11596#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11883#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11884#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11849#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11566#L586 assume !(0 == ~M_E~0); 11567#L586-2 assume !(0 == ~T1_E~0); 11621#L591-1 assume !(0 == ~T2_E~0); 11741#L596-1 assume !(0 == ~T3_E~0); 11742#L601-1 assume !(0 == ~T4_E~0); 11781#L606-1 assume !(0 == ~T5_E~0); 11782#L611-1 assume !(0 == ~E_1~0); 11857#L616-1 assume !(0 == ~E_2~0); 11858#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 11497#L626-1 assume !(0 == ~E_4~0); 11498#L631-1 assume !(0 == ~E_5~0); 11656#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11492#L279 assume !(1 == ~m_pc~0); 11494#L279-2 is_master_triggered_~__retres1~0#1 := 0; 11799#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11723#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11724#L720 assume !(0 != activate_threads_~tmp~1#1); 11798#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11660#L298 assume !(1 == ~t1_pc~0); 11450#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11451#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11712#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11506#L728 assume !(0 != activate_threads_~tmp___0~0#1); 11507#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11627#L317 assume 1 == ~t2_pc~0; 11628#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11775#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11891#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11669#L736 assume !(0 != activate_threads_~tmp___1~0#1); 11670#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11847#L336 assume 1 == ~t3_pc~0; 11716#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11717#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11764#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11765#L744 assume !(0 != activate_threads_~tmp___2~0#1); 11807#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11854#L355 assume !(1 == ~t4_pc~0); 11738#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11581#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11582#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11794#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11516#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11517#L374 assume 1 == ~t5_pc~0; 11874#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11648#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11721#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11722#L760 assume !(0 != activate_threads_~tmp___4~0#1); 11767#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11768#L649 assume !(1 == ~M_E~0); 11902#L649-2 assume !(1 == ~T1_E~0); 11481#L654-1 assume !(1 == ~T2_E~0); 11482#L659-1 assume !(1 == ~T3_E~0); 11668#L664-1 assume !(1 == ~T4_E~0); 11474#L669-1 assume !(1 == ~T5_E~0); 11475#L674-1 assume !(1 == ~E_1~0); 11843#L679-1 assume !(1 == ~E_2~0); 11571#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 11572#L689-1 assume !(1 == ~E_4~0); 11735#L694-1 assume !(1 == ~E_5~0); 11733#L699-1 assume { :end_inline_reset_delta_events } true; 11734#L900-2 [2022-02-21 04:24:15,396 INFO L793 eck$LassoCheckResult]: Loop: 11734#L900-2 assume !false; 11957#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11955#L561 assume !false; 11954#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 11952#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 11946#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 11943#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11940#L486 assume !(0 != eval_~tmp~0#1); 11941#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12274#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12273#L586-3 assume !(0 == ~M_E~0); 12272#L586-5 assume !(0 == ~T1_E~0); 11747#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11586#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11587#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11761#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11792#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11793#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11485#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11447#L626-3 assume !(0 == ~E_4~0); 11448#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11454#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11455#L279-18 assume !(1 == ~m_pc~0); 12036#L279-20 is_master_triggered_~__retres1~0#1 := 0; 12034#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12032#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12030#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12027#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12025#L298-18 assume 1 == ~t1_pc~0; 12022#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12020#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12018#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12016#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12013#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12011#L317-18 assume !(1 == ~t2_pc~0); 12008#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 12006#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12004#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12003#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12000#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11998#L336-18 assume 1 == ~t3_pc~0; 11995#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11994#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11993#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11992#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11991#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11990#L355-18 assume !(1 == ~t4_pc~0); 11987#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 11986#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11985#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11984#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11982#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11980#L374-18 assume 1 == ~t5_pc~0; 11977#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11975#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11974#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11905#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11800#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11801#L649-3 assume !(1 == ~M_E~0); 11715#L649-5 assume !(1 == ~T1_E~0); 11697#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11549#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11550#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11456#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11457#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11445#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11446#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11400#L689-3 assume !(1 == ~E_4~0); 11401#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11440#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 11441#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 11443#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 11862#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 11732#L919 assume !(0 == start_simulation_~tmp~3#1); 11459#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 11830#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 11434#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 11682#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 11683#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11727#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11678#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 11679#L932 assume !(0 != start_simulation_~tmp___0~1#1); 11734#L900-2 [2022-02-21 04:24:15,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:15,396 INFO L85 PathProgramCache]: Analyzing trace with hash -484678139, now seen corresponding path program 1 times [2022-02-21 04:24:15,396 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:15,397 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604994378] [2022-02-21 04:24:15,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:15,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:15,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:15,437 INFO L290 TraceCheckUtils]: 0: Hoare triple {14028#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,437 INFO L290 TraceCheckUtils]: 1: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,437 INFO L290 TraceCheckUtils]: 2: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,438 INFO L290 TraceCheckUtils]: 3: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,438 INFO L290 TraceCheckUtils]: 4: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,439 INFO L290 TraceCheckUtils]: 5: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,439 INFO L290 TraceCheckUtils]: 6: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,439 INFO L290 TraceCheckUtils]: 7: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,440 INFO L290 TraceCheckUtils]: 8: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,440 INFO L290 TraceCheckUtils]: 9: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,440 INFO L290 TraceCheckUtils]: 10: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,441 INFO L290 TraceCheckUtils]: 11: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~M_E~0); {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,441 INFO L290 TraceCheckUtils]: 12: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T1_E~0); {14030#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:15,441 INFO L290 TraceCheckUtils]: 13: Hoare triple {14030#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T2_E~0); {14031#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:15,442 INFO L290 TraceCheckUtils]: 14: Hoare triple {14031#(not (= ~E_3~0 0))} assume !(0 == ~T3_E~0); {14031#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:15,442 INFO L290 TraceCheckUtils]: 15: Hoare triple {14031#(not (= ~E_3~0 0))} assume !(0 == ~T4_E~0); {14031#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:15,442 INFO L290 TraceCheckUtils]: 16: Hoare triple {14031#(not (= ~E_3~0 0))} assume !(0 == ~T5_E~0); {14031#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:15,443 INFO L290 TraceCheckUtils]: 17: Hoare triple {14031#(not (= ~E_3~0 0))} assume !(0 == ~E_1~0); {14031#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:15,443 INFO L290 TraceCheckUtils]: 18: Hoare triple {14031#(not (= ~E_3~0 0))} assume !(0 == ~E_2~0); {14031#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:15,443 INFO L290 TraceCheckUtils]: 19: Hoare triple {14031#(not (= ~E_3~0 0))} assume 0 == ~E_3~0;~E_3~0 := 1; {14029#false} is VALID [2022-02-21 04:24:15,444 INFO L290 TraceCheckUtils]: 20: Hoare triple {14029#false} assume !(0 == ~E_4~0); {14029#false} is VALID [2022-02-21 04:24:15,444 INFO L290 TraceCheckUtils]: 21: Hoare triple {14029#false} assume !(0 == ~E_5~0); {14029#false} is VALID [2022-02-21 04:24:15,444 INFO L290 TraceCheckUtils]: 22: Hoare triple {14029#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14029#false} is VALID [2022-02-21 04:24:15,444 INFO L290 TraceCheckUtils]: 23: Hoare triple {14029#false} assume !(1 == ~m_pc~0); {14029#false} is VALID [2022-02-21 04:24:15,444 INFO L290 TraceCheckUtils]: 24: Hoare triple {14029#false} is_master_triggered_~__retres1~0#1 := 0; {14029#false} is VALID [2022-02-21 04:24:15,444 INFO L290 TraceCheckUtils]: 25: Hoare triple {14029#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14029#false} is VALID [2022-02-21 04:24:15,444 INFO L290 TraceCheckUtils]: 26: Hoare triple {14029#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {14029#false} is VALID [2022-02-21 04:24:15,444 INFO L290 TraceCheckUtils]: 27: Hoare triple {14029#false} assume !(0 != activate_threads_~tmp~1#1); {14029#false} is VALID [2022-02-21 04:24:15,444 INFO L290 TraceCheckUtils]: 28: Hoare triple {14029#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14029#false} is VALID [2022-02-21 04:24:15,444 INFO L290 TraceCheckUtils]: 29: Hoare triple {14029#false} assume !(1 == ~t1_pc~0); {14029#false} is VALID [2022-02-21 04:24:15,445 INFO L290 TraceCheckUtils]: 30: Hoare triple {14029#false} is_transmit1_triggered_~__retres1~1#1 := 0; {14029#false} is VALID [2022-02-21 04:24:15,445 INFO L290 TraceCheckUtils]: 31: Hoare triple {14029#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14029#false} is VALID [2022-02-21 04:24:15,445 INFO L290 TraceCheckUtils]: 32: Hoare triple {14029#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {14029#false} is VALID [2022-02-21 04:24:15,445 INFO L290 TraceCheckUtils]: 33: Hoare triple {14029#false} assume !(0 != activate_threads_~tmp___0~0#1); {14029#false} is VALID [2022-02-21 04:24:15,445 INFO L290 TraceCheckUtils]: 34: Hoare triple {14029#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14029#false} is VALID [2022-02-21 04:24:15,445 INFO L290 TraceCheckUtils]: 35: Hoare triple {14029#false} assume 1 == ~t2_pc~0; {14029#false} is VALID [2022-02-21 04:24:15,445 INFO L290 TraceCheckUtils]: 36: Hoare triple {14029#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {14029#false} is VALID [2022-02-21 04:24:15,445 INFO L290 TraceCheckUtils]: 37: Hoare triple {14029#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14029#false} is VALID [2022-02-21 04:24:15,445 INFO L290 TraceCheckUtils]: 38: Hoare triple {14029#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {14029#false} is VALID [2022-02-21 04:24:15,445 INFO L290 TraceCheckUtils]: 39: Hoare triple {14029#false} assume !(0 != activate_threads_~tmp___1~0#1); {14029#false} is VALID [2022-02-21 04:24:15,446 INFO L290 TraceCheckUtils]: 40: Hoare triple {14029#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14029#false} is VALID [2022-02-21 04:24:15,446 INFO L290 TraceCheckUtils]: 41: Hoare triple {14029#false} assume 1 == ~t3_pc~0; {14029#false} is VALID [2022-02-21 04:24:15,446 INFO L290 TraceCheckUtils]: 42: Hoare triple {14029#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {14029#false} is VALID [2022-02-21 04:24:15,446 INFO L290 TraceCheckUtils]: 43: Hoare triple {14029#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14029#false} is VALID [2022-02-21 04:24:15,446 INFO L290 TraceCheckUtils]: 44: Hoare triple {14029#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {14029#false} is VALID [2022-02-21 04:24:15,446 INFO L290 TraceCheckUtils]: 45: Hoare triple {14029#false} assume !(0 != activate_threads_~tmp___2~0#1); {14029#false} is VALID [2022-02-21 04:24:15,446 INFO L290 TraceCheckUtils]: 46: Hoare triple {14029#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14029#false} is VALID [2022-02-21 04:24:15,446 INFO L290 TraceCheckUtils]: 47: Hoare triple {14029#false} assume !(1 == ~t4_pc~0); {14029#false} is VALID [2022-02-21 04:24:15,446 INFO L290 TraceCheckUtils]: 48: Hoare triple {14029#false} is_transmit4_triggered_~__retres1~4#1 := 0; {14029#false} is VALID [2022-02-21 04:24:15,446 INFO L290 TraceCheckUtils]: 49: Hoare triple {14029#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14029#false} is VALID [2022-02-21 04:24:15,447 INFO L290 TraceCheckUtils]: 50: Hoare triple {14029#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {14029#false} is VALID [2022-02-21 04:24:15,447 INFO L290 TraceCheckUtils]: 51: Hoare triple {14029#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {14029#false} is VALID [2022-02-21 04:24:15,447 INFO L290 TraceCheckUtils]: 52: Hoare triple {14029#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14029#false} is VALID [2022-02-21 04:24:15,447 INFO L290 TraceCheckUtils]: 53: Hoare triple {14029#false} assume 1 == ~t5_pc~0; {14029#false} is VALID [2022-02-21 04:24:15,447 INFO L290 TraceCheckUtils]: 54: Hoare triple {14029#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {14029#false} is VALID [2022-02-21 04:24:15,447 INFO L290 TraceCheckUtils]: 55: Hoare triple {14029#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14029#false} is VALID [2022-02-21 04:24:15,447 INFO L290 TraceCheckUtils]: 56: Hoare triple {14029#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {14029#false} is VALID [2022-02-21 04:24:15,447 INFO L290 TraceCheckUtils]: 57: Hoare triple {14029#false} assume !(0 != activate_threads_~tmp___4~0#1); {14029#false} is VALID [2022-02-21 04:24:15,447 INFO L290 TraceCheckUtils]: 58: Hoare triple {14029#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14029#false} is VALID [2022-02-21 04:24:15,447 INFO L290 TraceCheckUtils]: 59: Hoare triple {14029#false} assume !(1 == ~M_E~0); {14029#false} is VALID [2022-02-21 04:24:15,448 INFO L290 TraceCheckUtils]: 60: Hoare triple {14029#false} assume !(1 == ~T1_E~0); {14029#false} is VALID [2022-02-21 04:24:15,448 INFO L290 TraceCheckUtils]: 61: Hoare triple {14029#false} assume !(1 == ~T2_E~0); {14029#false} is VALID [2022-02-21 04:24:15,448 INFO L290 TraceCheckUtils]: 62: Hoare triple {14029#false} assume !(1 == ~T3_E~0); {14029#false} is VALID [2022-02-21 04:24:15,448 INFO L290 TraceCheckUtils]: 63: Hoare triple {14029#false} assume !(1 == ~T4_E~0); {14029#false} is VALID [2022-02-21 04:24:15,448 INFO L290 TraceCheckUtils]: 64: Hoare triple {14029#false} assume !(1 == ~T5_E~0); {14029#false} is VALID [2022-02-21 04:24:15,448 INFO L290 TraceCheckUtils]: 65: Hoare triple {14029#false} assume !(1 == ~E_1~0); {14029#false} is VALID [2022-02-21 04:24:15,448 INFO L290 TraceCheckUtils]: 66: Hoare triple {14029#false} assume !(1 == ~E_2~0); {14029#false} is VALID [2022-02-21 04:24:15,448 INFO L290 TraceCheckUtils]: 67: Hoare triple {14029#false} assume 1 == ~E_3~0;~E_3~0 := 2; {14029#false} is VALID [2022-02-21 04:24:15,448 INFO L290 TraceCheckUtils]: 68: Hoare triple {14029#false} assume !(1 == ~E_4~0); {14029#false} is VALID [2022-02-21 04:24:15,448 INFO L290 TraceCheckUtils]: 69: Hoare triple {14029#false} assume !(1 == ~E_5~0); {14029#false} is VALID [2022-02-21 04:24:15,448 INFO L290 TraceCheckUtils]: 70: Hoare triple {14029#false} assume { :end_inline_reset_delta_events } true; {14029#false} is VALID [2022-02-21 04:24:15,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:15,449 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:15,449 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604994378] [2022-02-21 04:24:15,449 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604994378] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:15,450 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:15,450 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:15,450 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211341146] [2022-02-21 04:24:15,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:15,450 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:15,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:15,451 INFO L85 PathProgramCache]: Analyzing trace with hash 523149704, now seen corresponding path program 1 times [2022-02-21 04:24:15,451 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:15,451 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323754919] [2022-02-21 04:24:15,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:15,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:15,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:15,496 INFO L290 TraceCheckUtils]: 0: Hoare triple {14032#true} assume !false; {14032#true} is VALID [2022-02-21 04:24:15,496 INFO L290 TraceCheckUtils]: 1: Hoare triple {14032#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {14032#true} is VALID [2022-02-21 04:24:15,496 INFO L290 TraceCheckUtils]: 2: Hoare triple {14032#true} assume !false; {14032#true} is VALID [2022-02-21 04:24:15,496 INFO L290 TraceCheckUtils]: 3: Hoare triple {14032#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {14032#true} is VALID [2022-02-21 04:24:15,497 INFO L290 TraceCheckUtils]: 4: Hoare triple {14032#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {14034#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~6#1|)} is VALID [2022-02-21 04:24:15,497 INFO L290 TraceCheckUtils]: 5: Hoare triple {14034#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~6#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {14035#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:15,497 INFO L290 TraceCheckUtils]: 6: Hoare triple {14035#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {14036#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:15,498 INFO L290 TraceCheckUtils]: 7: Hoare triple {14036#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {14033#false} is VALID [2022-02-21 04:24:15,498 INFO L290 TraceCheckUtils]: 8: Hoare triple {14033#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {14033#false} is VALID [2022-02-21 04:24:15,498 INFO L290 TraceCheckUtils]: 9: Hoare triple {14033#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {14033#false} is VALID [2022-02-21 04:24:15,498 INFO L290 TraceCheckUtils]: 10: Hoare triple {14033#false} assume !(0 == ~M_E~0); {14033#false} is VALID [2022-02-21 04:24:15,498 INFO L290 TraceCheckUtils]: 11: Hoare triple {14033#false} assume !(0 == ~T1_E~0); {14033#false} is VALID [2022-02-21 04:24:15,499 INFO L290 TraceCheckUtils]: 12: Hoare triple {14033#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {14033#false} is VALID [2022-02-21 04:24:15,499 INFO L290 TraceCheckUtils]: 13: Hoare triple {14033#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {14033#false} is VALID [2022-02-21 04:24:15,499 INFO L290 TraceCheckUtils]: 14: Hoare triple {14033#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {14033#false} is VALID [2022-02-21 04:24:15,499 INFO L290 TraceCheckUtils]: 15: Hoare triple {14033#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {14033#false} is VALID [2022-02-21 04:24:15,499 INFO L290 TraceCheckUtils]: 16: Hoare triple {14033#false} assume 0 == ~E_1~0;~E_1~0 := 1; {14033#false} is VALID [2022-02-21 04:24:15,499 INFO L290 TraceCheckUtils]: 17: Hoare triple {14033#false} assume 0 == ~E_2~0;~E_2~0 := 1; {14033#false} is VALID [2022-02-21 04:24:15,499 INFO L290 TraceCheckUtils]: 18: Hoare triple {14033#false} assume 0 == ~E_3~0;~E_3~0 := 1; {14033#false} is VALID [2022-02-21 04:24:15,500 INFO L290 TraceCheckUtils]: 19: Hoare triple {14033#false} assume !(0 == ~E_4~0); {14033#false} is VALID [2022-02-21 04:24:15,500 INFO L290 TraceCheckUtils]: 20: Hoare triple {14033#false} assume 0 == ~E_5~0;~E_5~0 := 1; {14033#false} is VALID [2022-02-21 04:24:15,500 INFO L290 TraceCheckUtils]: 21: Hoare triple {14033#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14033#false} is VALID [2022-02-21 04:24:15,500 INFO L290 TraceCheckUtils]: 22: Hoare triple {14033#false} assume !(1 == ~m_pc~0); {14033#false} is VALID [2022-02-21 04:24:15,500 INFO L290 TraceCheckUtils]: 23: Hoare triple {14033#false} is_master_triggered_~__retres1~0#1 := 0; {14033#false} is VALID [2022-02-21 04:24:15,500 INFO L290 TraceCheckUtils]: 24: Hoare triple {14033#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14033#false} is VALID [2022-02-21 04:24:15,500 INFO L290 TraceCheckUtils]: 25: Hoare triple {14033#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {14033#false} is VALID [2022-02-21 04:24:15,501 INFO L290 TraceCheckUtils]: 26: Hoare triple {14033#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {14033#false} is VALID [2022-02-21 04:24:15,501 INFO L290 TraceCheckUtils]: 27: Hoare triple {14033#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14033#false} is VALID [2022-02-21 04:24:15,501 INFO L290 TraceCheckUtils]: 28: Hoare triple {14033#false} assume 1 == ~t1_pc~0; {14033#false} is VALID [2022-02-21 04:24:15,501 INFO L290 TraceCheckUtils]: 29: Hoare triple {14033#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {14033#false} is VALID [2022-02-21 04:24:15,501 INFO L290 TraceCheckUtils]: 30: Hoare triple {14033#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14033#false} is VALID [2022-02-21 04:24:15,501 INFO L290 TraceCheckUtils]: 31: Hoare triple {14033#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {14033#false} is VALID [2022-02-21 04:24:15,501 INFO L290 TraceCheckUtils]: 32: Hoare triple {14033#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {14033#false} is VALID [2022-02-21 04:24:15,502 INFO L290 TraceCheckUtils]: 33: Hoare triple {14033#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14033#false} is VALID [2022-02-21 04:24:15,502 INFO L290 TraceCheckUtils]: 34: Hoare triple {14033#false} assume !(1 == ~t2_pc~0); {14033#false} is VALID [2022-02-21 04:24:15,502 INFO L290 TraceCheckUtils]: 35: Hoare triple {14033#false} is_transmit2_triggered_~__retres1~2#1 := 0; {14033#false} is VALID [2022-02-21 04:24:15,502 INFO L290 TraceCheckUtils]: 36: Hoare triple {14033#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14033#false} is VALID [2022-02-21 04:24:15,502 INFO L290 TraceCheckUtils]: 37: Hoare triple {14033#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {14033#false} is VALID [2022-02-21 04:24:15,502 INFO L290 TraceCheckUtils]: 38: Hoare triple {14033#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {14033#false} is VALID [2022-02-21 04:24:15,502 INFO L290 TraceCheckUtils]: 39: Hoare triple {14033#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14033#false} is VALID [2022-02-21 04:24:15,503 INFO L290 TraceCheckUtils]: 40: Hoare triple {14033#false} assume 1 == ~t3_pc~0; {14033#false} is VALID [2022-02-21 04:24:15,503 INFO L290 TraceCheckUtils]: 41: Hoare triple {14033#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {14033#false} is VALID [2022-02-21 04:24:15,503 INFO L290 TraceCheckUtils]: 42: Hoare triple {14033#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14033#false} is VALID [2022-02-21 04:24:15,503 INFO L290 TraceCheckUtils]: 43: Hoare triple {14033#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {14033#false} is VALID [2022-02-21 04:24:15,503 INFO L290 TraceCheckUtils]: 44: Hoare triple {14033#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {14033#false} is VALID [2022-02-21 04:24:15,503 INFO L290 TraceCheckUtils]: 45: Hoare triple {14033#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14033#false} is VALID [2022-02-21 04:24:15,504 INFO L290 TraceCheckUtils]: 46: Hoare triple {14033#false} assume !(1 == ~t4_pc~0); {14033#false} is VALID [2022-02-21 04:24:15,504 INFO L290 TraceCheckUtils]: 47: Hoare triple {14033#false} is_transmit4_triggered_~__retres1~4#1 := 0; {14033#false} is VALID [2022-02-21 04:24:15,504 INFO L290 TraceCheckUtils]: 48: Hoare triple {14033#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14033#false} is VALID [2022-02-21 04:24:15,504 INFO L290 TraceCheckUtils]: 49: Hoare triple {14033#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {14033#false} is VALID [2022-02-21 04:24:15,504 INFO L290 TraceCheckUtils]: 50: Hoare triple {14033#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {14033#false} is VALID [2022-02-21 04:24:15,504 INFO L290 TraceCheckUtils]: 51: Hoare triple {14033#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14033#false} is VALID [2022-02-21 04:24:15,504 INFO L290 TraceCheckUtils]: 52: Hoare triple {14033#false} assume 1 == ~t5_pc~0; {14033#false} is VALID [2022-02-21 04:24:15,504 INFO L290 TraceCheckUtils]: 53: Hoare triple {14033#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {14033#false} is VALID [2022-02-21 04:24:15,505 INFO L290 TraceCheckUtils]: 54: Hoare triple {14033#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14033#false} is VALID [2022-02-21 04:24:15,505 INFO L290 TraceCheckUtils]: 55: Hoare triple {14033#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {14033#false} is VALID [2022-02-21 04:24:15,505 INFO L290 TraceCheckUtils]: 56: Hoare triple {14033#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {14033#false} is VALID [2022-02-21 04:24:15,505 INFO L290 TraceCheckUtils]: 57: Hoare triple {14033#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14033#false} is VALID [2022-02-21 04:24:15,505 INFO L290 TraceCheckUtils]: 58: Hoare triple {14033#false} assume !(1 == ~M_E~0); {14033#false} is VALID [2022-02-21 04:24:15,505 INFO L290 TraceCheckUtils]: 59: Hoare triple {14033#false} assume !(1 == ~T1_E~0); {14033#false} is VALID [2022-02-21 04:24:15,506 INFO L290 TraceCheckUtils]: 60: Hoare triple {14033#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {14033#false} is VALID [2022-02-21 04:24:15,506 INFO L290 TraceCheckUtils]: 61: Hoare triple {14033#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {14033#false} is VALID [2022-02-21 04:24:15,506 INFO L290 TraceCheckUtils]: 62: Hoare triple {14033#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {14033#false} is VALID [2022-02-21 04:24:15,506 INFO L290 TraceCheckUtils]: 63: Hoare triple {14033#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {14033#false} is VALID [2022-02-21 04:24:15,506 INFO L290 TraceCheckUtils]: 64: Hoare triple {14033#false} assume 1 == ~E_1~0;~E_1~0 := 2; {14033#false} is VALID [2022-02-21 04:24:15,506 INFO L290 TraceCheckUtils]: 65: Hoare triple {14033#false} assume 1 == ~E_2~0;~E_2~0 := 2; {14033#false} is VALID [2022-02-21 04:24:15,506 INFO L290 TraceCheckUtils]: 66: Hoare triple {14033#false} assume 1 == ~E_3~0;~E_3~0 := 2; {14033#false} is VALID [2022-02-21 04:24:15,507 INFO L290 TraceCheckUtils]: 67: Hoare triple {14033#false} assume !(1 == ~E_4~0); {14033#false} is VALID [2022-02-21 04:24:15,507 INFO L290 TraceCheckUtils]: 68: Hoare triple {14033#false} assume 1 == ~E_5~0;~E_5~0 := 2; {14033#false} is VALID [2022-02-21 04:24:15,507 INFO L290 TraceCheckUtils]: 69: Hoare triple {14033#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {14033#false} is VALID [2022-02-21 04:24:15,507 INFO L290 TraceCheckUtils]: 70: Hoare triple {14033#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {14033#false} is VALID [2022-02-21 04:24:15,507 INFO L290 TraceCheckUtils]: 71: Hoare triple {14033#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {14033#false} is VALID [2022-02-21 04:24:15,507 INFO L290 TraceCheckUtils]: 72: Hoare triple {14033#false} start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {14033#false} is VALID [2022-02-21 04:24:15,507 INFO L290 TraceCheckUtils]: 73: Hoare triple {14033#false} assume !(0 == start_simulation_~tmp~3#1); {14033#false} is VALID [2022-02-21 04:24:15,508 INFO L290 TraceCheckUtils]: 74: Hoare triple {14033#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {14033#false} is VALID [2022-02-21 04:24:15,508 INFO L290 TraceCheckUtils]: 75: Hoare triple {14033#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {14033#false} is VALID [2022-02-21 04:24:15,508 INFO L290 TraceCheckUtils]: 76: Hoare triple {14033#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {14033#false} is VALID [2022-02-21 04:24:15,508 INFO L290 TraceCheckUtils]: 77: Hoare triple {14033#false} stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; {14033#false} is VALID [2022-02-21 04:24:15,508 INFO L290 TraceCheckUtils]: 78: Hoare triple {14033#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {14033#false} is VALID [2022-02-21 04:24:15,508 INFO L290 TraceCheckUtils]: 79: Hoare triple {14033#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {14033#false} is VALID [2022-02-21 04:24:15,508 INFO L290 TraceCheckUtils]: 80: Hoare triple {14033#false} start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; {14033#false} is VALID [2022-02-21 04:24:15,509 INFO L290 TraceCheckUtils]: 81: Hoare triple {14033#false} assume !(0 != start_simulation_~tmp___0~1#1); {14033#false} is VALID [2022-02-21 04:24:15,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:15,509 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:15,509 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323754919] [2022-02-21 04:24:15,509 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323754919] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:15,510 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:15,510 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:15,510 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633360685] [2022-02-21 04:24:15,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:15,510 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:15,510 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:15,511 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:15,511 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:15,511 INFO L87 Difference]: Start difference. First operand 875 states and 1292 transitions. cyclomatic complexity: 418 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:16,731 INFO L93 Difference]: Finished difference Result 1596 states and 2357 transitions. [2022-02-21 04:24:16,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:16,731 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,776 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:16,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1596 states and 2357 transitions. [2022-02-21 04:24:16,875 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1508 [2022-02-21 04:24:16,970 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1596 states to 1596 states and 2357 transitions. [2022-02-21 04:24:16,971 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1596 [2022-02-21 04:24:16,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1596 [2022-02-21 04:24:16,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1596 states and 2357 transitions. [2022-02-21 04:24:16,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:16,974 INFO L681 BuchiCegarLoop]: Abstraction has 1596 states and 2357 transitions. [2022-02-21 04:24:16,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1596 states and 2357 transitions. [2022-02-21 04:24:16,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1596 to 1594. [2022-02-21 04:24:16,995 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:16,998 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1596 states and 2357 transitions. Second operand has 1594 states, 1594 states have (on average 1.4774153074027603) internal successors, (2355), 1593 states have internal predecessors, (2355), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,014 INFO L74 IsIncluded]: Start isIncluded. First operand 1596 states and 2357 transitions. Second operand has 1594 states, 1594 states have (on average 1.4774153074027603) internal successors, (2355), 1593 states have internal predecessors, (2355), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,018 INFO L87 Difference]: Start difference. First operand 1596 states and 2357 transitions. Second operand has 1594 states, 1594 states have (on average 1.4774153074027603) internal successors, (2355), 1593 states have internal predecessors, (2355), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,113 INFO L93 Difference]: Finished difference Result 1596 states and 2357 transitions. [2022-02-21 04:24:17,113 INFO L276 IsEmpty]: Start isEmpty. Operand 1596 states and 2357 transitions. [2022-02-21 04:24:17,116 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:17,116 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:17,119 INFO L74 IsIncluded]: Start isIncluded. First operand has 1594 states, 1594 states have (on average 1.4774153074027603) internal successors, (2355), 1593 states have internal predecessors, (2355), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1596 states and 2357 transitions. [2022-02-21 04:24:17,121 INFO L87 Difference]: Start difference. First operand has 1594 states, 1594 states have (on average 1.4774153074027603) internal successors, (2355), 1593 states have internal predecessors, (2355), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1596 states and 2357 transitions. [2022-02-21 04:24:17,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,213 INFO L93 Difference]: Finished difference Result 1596 states and 2357 transitions. [2022-02-21 04:24:17,213 INFO L276 IsEmpty]: Start isEmpty. Operand 1596 states and 2357 transitions. [2022-02-21 04:24:17,216 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:17,216 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:17,216 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:17,216 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:17,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1594 states, 1594 states have (on average 1.4774153074027603) internal successors, (2355), 1593 states have internal predecessors, (2355), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1594 states to 1594 states and 2355 transitions. [2022-02-21 04:24:17,313 INFO L704 BuchiCegarLoop]: Abstraction has 1594 states and 2355 transitions. [2022-02-21 04:24:17,313 INFO L587 BuchiCegarLoop]: Abstraction has 1594 states and 2355 transitions. [2022-02-21 04:24:17,313 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:17,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1594 states and 2355 transitions. [2022-02-21 04:24:17,319 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1508 [2022-02-21 04:24:17,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:17,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:17,329 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,330 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,330 INFO L791 eck$LassoCheckResult]: Stem: 16236#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 16204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 16188#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16184#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16055#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 16056#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15833#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15834#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16182#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16183#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16137#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15803#L586 assume !(0 == ~M_E~0); 15804#L586-2 assume !(0 == ~T1_E~0); 15861#L591-1 assume !(0 == ~T2_E~0); 16001#L596-1 assume !(0 == ~T3_E~0); 16002#L601-1 assume !(0 == ~T4_E~0); 16046#L606-1 assume !(0 == ~T5_E~0); 16047#L611-1 assume !(0 == ~E_1~0); 16147#L616-1 assume !(0 == ~E_2~0); 16148#L621-1 assume !(0 == ~E_3~0); 15735#L626-1 assume !(0 == ~E_4~0); 15736#L631-1 assume !(0 == ~E_5~0); 15897#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15730#L279 assume !(1 == ~m_pc~0); 15732#L279-2 is_master_triggered_~__retres1~0#1 := 0; 16068#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15973#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15974#L720 assume !(0 != activate_threads_~tmp~1#1); 16067#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15903#L298 assume !(1 == ~t1_pc~0); 15685#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15686#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15961#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15744#L728 assume !(0 != activate_threads_~tmp___0~0#1); 15745#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15867#L317 assume 1 == ~t2_pc~0; 15868#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16038#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16197#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15913#L736 assume !(0 != activate_threads_~tmp___1~0#1); 15914#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16133#L336 assume 1 == ~t3_pc~0; 15965#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15966#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16025#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16026#L744 assume !(0 != activate_threads_~tmp___2~0#1); 16077#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16141#L355 assume !(1 == ~t4_pc~0); 15998#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15819#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15820#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16062#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15755#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15756#L374 assume 1 == ~t5_pc~0; 16171#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15889#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15971#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15972#L760 assume !(0 != activate_threads_~tmp___4~0#1); 16028#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16029#L649 assume !(1 == ~M_E~0); 16213#L649-2 assume !(1 == ~T1_E~0); 15718#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15719#L659-1 assume !(1 == ~T3_E~0); 15912#L664-1 assume !(1 == ~T4_E~0); 15711#L669-1 assume !(1 == ~T5_E~0); 15712#L674-1 assume !(1 == ~E_1~0); 16123#L679-1 assume !(1 == ~E_2~0); 15809#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 15810#L689-1 assume !(1 == ~E_4~0); 15994#L694-1 assume !(1 == ~E_5~0); 15992#L699-1 assume { :end_inline_reset_delta_events } true; 15993#L900-2 [2022-02-21 04:24:17,330 INFO L793 eck$LassoCheckResult]: Loop: 15993#L900-2 assume !false; 16987#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16985#L561 assume !false; 16984#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 16982#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16977#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16976#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16974#L486 assume !(0 != eval_~tmp~0#1); 16973#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16972#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16971#L586-3 assume !(0 == ~M_E~0); 16970#L586-5 assume !(0 == ~T1_E~0); 16969#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16968#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16967#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16966#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16965#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16964#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16963#L621-3 assume !(0 == ~E_3~0); 16962#L626-3 assume !(0 == ~E_4~0); 16961#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16960#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16959#L279-18 assume !(1 == ~m_pc~0); 16957#L279-20 is_master_triggered_~__retres1~0#1 := 0; 16956#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16955#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16954#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16953#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16952#L298-18 assume 1 == ~t1_pc~0; 16950#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16949#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16948#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16947#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16946#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16945#L317-18 assume 1 == ~t2_pc~0; 16944#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16942#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16941#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16940#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16939#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16938#L336-18 assume 1 == ~t3_pc~0; 16936#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16935#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16934#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16933#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16932#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16931#L355-18 assume !(1 == ~t4_pc~0); 16929#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 16928#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16927#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16926#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16925#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16924#L374-18 assume 1 == ~t5_pc~0; 16922#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16921#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16920#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16919#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16918#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16917#L649-3 assume !(1 == ~M_E~0); 16830#L649-5 assume !(1 == ~T1_E~0); 16916#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16425#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16915#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16914#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16913#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16912#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16911#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16416#L689-3 assume !(1 == ~E_4~0); 16910#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16909#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 16908#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16902#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16901#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 16900#L919 assume !(0 == start_simulation_~tmp~3#1); 16393#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 16323#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16315#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16310#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 16302#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16301#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16300#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 16298#L932 assume !(0 != start_simulation_~tmp___0~1#1); 15993#L900-2 [2022-02-21 04:24:17,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,331 INFO L85 PathProgramCache]: Analyzing trace with hash 1446688901, now seen corresponding path program 1 times [2022-02-21 04:24:17,331 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,331 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982677138] [2022-02-21 04:24:17,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,373 INFO L290 TraceCheckUtils]: 0: Hoare triple {20424#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,373 INFO L290 TraceCheckUtils]: 1: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,374 INFO L290 TraceCheckUtils]: 2: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,374 INFO L290 TraceCheckUtils]: 3: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,374 INFO L290 TraceCheckUtils]: 4: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,375 INFO L290 TraceCheckUtils]: 5: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,375 INFO L290 TraceCheckUtils]: 6: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,375 INFO L290 TraceCheckUtils]: 7: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,375 INFO L290 TraceCheckUtils]: 8: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,376 INFO L290 TraceCheckUtils]: 9: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,376 INFO L290 TraceCheckUtils]: 10: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,376 INFO L290 TraceCheckUtils]: 11: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~M_E~0); {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,377 INFO L290 TraceCheckUtils]: 12: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T1_E~0); {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,377 INFO L290 TraceCheckUtils]: 13: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T2_E~0); {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,377 INFO L290 TraceCheckUtils]: 14: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T3_E~0); {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,377 INFO L290 TraceCheckUtils]: 15: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T4_E~0); {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,378 INFO L290 TraceCheckUtils]: 16: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T5_E~0); {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,378 INFO L290 TraceCheckUtils]: 17: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_1~0); {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,378 INFO L290 TraceCheckUtils]: 18: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_2~0); {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 19: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_3~0); {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 20: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_4~0); {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 21: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_5~0); {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 22: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20426#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 23: Hoare triple {20426#(= ~m_pc~0 ~t2_pc~0)} assume !(1 == ~m_pc~0); {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 24: Hoare triple {20427#(not (= ~t2_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 25: Hoare triple {20427#(not (= ~t2_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 26: Hoare triple {20427#(not (= ~t2_pc~0 1))} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 27: Hoare triple {20427#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 28: Hoare triple {20427#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 29: Hoare triple {20427#(not (= ~t2_pc~0 1))} assume !(1 == ~t1_pc~0); {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 30: Hoare triple {20427#(not (= ~t2_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 31: Hoare triple {20427#(not (= ~t2_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 32: Hoare triple {20427#(not (= ~t2_pc~0 1))} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 33: Hoare triple {20427#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 34: Hoare triple {20427#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20427#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 35: Hoare triple {20427#(not (= ~t2_pc~0 1))} assume 1 == ~t2_pc~0; {20425#false} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 36: Hoare triple {20425#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {20425#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 37: Hoare triple {20425#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20425#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 38: Hoare triple {20425#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {20425#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 39: Hoare triple {20425#false} assume !(0 != activate_threads_~tmp___1~0#1); {20425#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 40: Hoare triple {20425#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20425#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 41: Hoare triple {20425#false} assume 1 == ~t3_pc~0; {20425#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 42: Hoare triple {20425#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {20425#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 43: Hoare triple {20425#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20425#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 44: Hoare triple {20425#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {20425#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 45: Hoare triple {20425#false} assume !(0 != activate_threads_~tmp___2~0#1); {20425#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 46: Hoare triple {20425#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20425#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 47: Hoare triple {20425#false} assume !(1 == ~t4_pc~0); {20425#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 48: Hoare triple {20425#false} is_transmit4_triggered_~__retres1~4#1 := 0; {20425#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 49: Hoare triple {20425#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20425#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 50: Hoare triple {20425#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {20425#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 51: Hoare triple {20425#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {20425#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 52: Hoare triple {20425#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20425#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 53: Hoare triple {20425#false} assume 1 == ~t5_pc~0; {20425#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 54: Hoare triple {20425#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {20425#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 55: Hoare triple {20425#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20425#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 56: Hoare triple {20425#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {20425#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 57: Hoare triple {20425#false} assume !(0 != activate_threads_~tmp___4~0#1); {20425#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 58: Hoare triple {20425#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20425#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 59: Hoare triple {20425#false} assume !(1 == ~M_E~0); {20425#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 60: Hoare triple {20425#false} assume !(1 == ~T1_E~0); {20425#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 61: Hoare triple {20425#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {20425#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 62: Hoare triple {20425#false} assume !(1 == ~T3_E~0); {20425#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 63: Hoare triple {20425#false} assume !(1 == ~T4_E~0); {20425#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 64: Hoare triple {20425#false} assume !(1 == ~T5_E~0); {20425#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 65: Hoare triple {20425#false} assume !(1 == ~E_1~0); {20425#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 66: Hoare triple {20425#false} assume !(1 == ~E_2~0); {20425#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 67: Hoare triple {20425#false} assume 1 == ~E_3~0;~E_3~0 := 2; {20425#false} is VALID [2022-02-21 04:24:17,387 INFO L290 TraceCheckUtils]: 68: Hoare triple {20425#false} assume !(1 == ~E_4~0); {20425#false} is VALID [2022-02-21 04:24:17,387 INFO L290 TraceCheckUtils]: 69: Hoare triple {20425#false} assume !(1 == ~E_5~0); {20425#false} is VALID [2022-02-21 04:24:17,387 INFO L290 TraceCheckUtils]: 70: Hoare triple {20425#false} assume { :end_inline_reset_delta_events } true; {20425#false} is VALID [2022-02-21 04:24:17,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,388 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,388 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982677138] [2022-02-21 04:24:17,388 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982677138] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,389 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,389 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:17,389 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566438440] [2022-02-21 04:24:17,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,389 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:17,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,390 INFO L85 PathProgramCache]: Analyzing trace with hash -964077913, now seen corresponding path program 1 times [2022-02-21 04:24:17,390 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,394 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1695624315] [2022-02-21 04:24:17,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 0: Hoare triple {20428#true} assume !false; {20428#true} is VALID [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 1: Hoare triple {20428#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {20428#true} is VALID [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 2: Hoare triple {20428#true} assume !false; {20428#true} is VALID [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 3: Hoare triple {20428#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {20428#true} is VALID [2022-02-21 04:24:17,439 INFO L290 TraceCheckUtils]: 4: Hoare triple {20428#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {20430#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~6#1|)} is VALID [2022-02-21 04:24:17,439 INFO L290 TraceCheckUtils]: 5: Hoare triple {20430#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~6#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {20431#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 6: Hoare triple {20431#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {20432#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 7: Hoare triple {20432#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {20429#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 8: Hoare triple {20429#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {20429#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 9: Hoare triple {20429#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {20429#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 10: Hoare triple {20429#false} assume !(0 == ~M_E~0); {20429#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 11: Hoare triple {20429#false} assume !(0 == ~T1_E~0); {20429#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 12: Hoare triple {20429#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {20429#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 13: Hoare triple {20429#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {20429#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 14: Hoare triple {20429#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {20429#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 15: Hoare triple {20429#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {20429#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 16: Hoare triple {20429#false} assume 0 == ~E_1~0;~E_1~0 := 1; {20429#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 17: Hoare triple {20429#false} assume 0 == ~E_2~0;~E_2~0 := 1; {20429#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 18: Hoare triple {20429#false} assume !(0 == ~E_3~0); {20429#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 19: Hoare triple {20429#false} assume !(0 == ~E_4~0); {20429#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 20: Hoare triple {20429#false} assume 0 == ~E_5~0;~E_5~0 := 1; {20429#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 21: Hoare triple {20429#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20429#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 22: Hoare triple {20429#false} assume !(1 == ~m_pc~0); {20429#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 23: Hoare triple {20429#false} is_master_triggered_~__retres1~0#1 := 0; {20429#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 24: Hoare triple {20429#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20429#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 25: Hoare triple {20429#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {20429#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 26: Hoare triple {20429#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {20429#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 27: Hoare triple {20429#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20429#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 28: Hoare triple {20429#false} assume 1 == ~t1_pc~0; {20429#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 29: Hoare triple {20429#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {20429#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 30: Hoare triple {20429#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20429#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 31: Hoare triple {20429#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {20429#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 32: Hoare triple {20429#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {20429#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 33: Hoare triple {20429#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20429#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 34: Hoare triple {20429#false} assume 1 == ~t2_pc~0; {20429#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 35: Hoare triple {20429#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {20429#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 36: Hoare triple {20429#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20429#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 37: Hoare triple {20429#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {20429#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 38: Hoare triple {20429#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {20429#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 39: Hoare triple {20429#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20429#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 40: Hoare triple {20429#false} assume 1 == ~t3_pc~0; {20429#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 41: Hoare triple {20429#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {20429#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 42: Hoare triple {20429#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20429#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 43: Hoare triple {20429#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {20429#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 44: Hoare triple {20429#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {20429#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 45: Hoare triple {20429#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20429#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 46: Hoare triple {20429#false} assume !(1 == ~t4_pc~0); {20429#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 47: Hoare triple {20429#false} is_transmit4_triggered_~__retres1~4#1 := 0; {20429#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 48: Hoare triple {20429#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20429#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 49: Hoare triple {20429#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {20429#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 50: Hoare triple {20429#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {20429#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 51: Hoare triple {20429#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20429#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 52: Hoare triple {20429#false} assume 1 == ~t5_pc~0; {20429#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 53: Hoare triple {20429#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {20429#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 54: Hoare triple {20429#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20429#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 55: Hoare triple {20429#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {20429#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 56: Hoare triple {20429#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {20429#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 57: Hoare triple {20429#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20429#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 58: Hoare triple {20429#false} assume !(1 == ~M_E~0); {20429#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 59: Hoare triple {20429#false} assume !(1 == ~T1_E~0); {20429#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 60: Hoare triple {20429#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {20429#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 61: Hoare triple {20429#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {20429#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 62: Hoare triple {20429#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {20429#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 63: Hoare triple {20429#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {20429#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 64: Hoare triple {20429#false} assume 1 == ~E_1~0;~E_1~0 := 2; {20429#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 65: Hoare triple {20429#false} assume 1 == ~E_2~0;~E_2~0 := 2; {20429#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 66: Hoare triple {20429#false} assume 1 == ~E_3~0;~E_3~0 := 2; {20429#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 67: Hoare triple {20429#false} assume !(1 == ~E_4~0); {20429#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 68: Hoare triple {20429#false} assume 1 == ~E_5~0;~E_5~0 := 2; {20429#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 69: Hoare triple {20429#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {20429#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 70: Hoare triple {20429#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {20429#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 71: Hoare triple {20429#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {20429#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 72: Hoare triple {20429#false} start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {20429#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 73: Hoare triple {20429#false} assume !(0 == start_simulation_~tmp~3#1); {20429#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 74: Hoare triple {20429#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {20429#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 75: Hoare triple {20429#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {20429#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 76: Hoare triple {20429#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {20429#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 77: Hoare triple {20429#false} stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; {20429#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 78: Hoare triple {20429#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {20429#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 79: Hoare triple {20429#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {20429#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 80: Hoare triple {20429#false} start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; {20429#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 81: Hoare triple {20429#false} assume !(0 != start_simulation_~tmp___0~1#1); {20429#false} is VALID [2022-02-21 04:24:17,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,448 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,450 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1695624315] [2022-02-21 04:24:17,451 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1695624315] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,451 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,451 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:17,451 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440812865] [2022-02-21 04:24:17,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,452 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:17,452 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:17,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:17,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:17,453 INFO L87 Difference]: Start difference. First operand 1594 states and 2355 transitions. cyclomatic complexity: 763 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:19,295 INFO L93 Difference]: Finished difference Result 4404 states and 6412 transitions. [2022-02-21 04:24:19,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:19,295 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,346 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:19,347 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4404 states and 6412 transitions. [2022-02-21 04:24:19,796 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4116 [2022-02-21 04:24:20,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4404 states to 4404 states and 6412 transitions. [2022-02-21 04:24:20,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4404 [2022-02-21 04:24:20,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4404 [2022-02-21 04:24:20,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4404 states and 6412 transitions. [2022-02-21 04:24:20,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:20,272 INFO L681 BuchiCegarLoop]: Abstraction has 4404 states and 6412 transitions. [2022-02-21 04:24:20,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4404 states and 6412 transitions. [2022-02-21 04:24:20,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4404 to 4162. [2022-02-21 04:24:20,319 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:20,326 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4404 states and 6412 transitions. Second operand has 4162 states, 4162 states have (on average 1.4632388274867851) internal successors, (6090), 4161 states have internal predecessors, (6090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,332 INFO L74 IsIncluded]: Start isIncluded. First operand 4404 states and 6412 transitions. Second operand has 4162 states, 4162 states have (on average 1.4632388274867851) internal successors, (6090), 4161 states have internal predecessors, (6090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,338 INFO L87 Difference]: Start difference. First operand 4404 states and 6412 transitions. Second operand has 4162 states, 4162 states have (on average 1.4632388274867851) internal successors, (6090), 4161 states have internal predecessors, (6090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,765 INFO L93 Difference]: Finished difference Result 4404 states and 6412 transitions. [2022-02-21 04:24:20,765 INFO L276 IsEmpty]: Start isEmpty. Operand 4404 states and 6412 transitions. [2022-02-21 04:24:20,772 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:20,772 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:20,778 INFO L74 IsIncluded]: Start isIncluded. First operand has 4162 states, 4162 states have (on average 1.4632388274867851) internal successors, (6090), 4161 states have internal predecessors, (6090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4404 states and 6412 transitions. [2022-02-21 04:24:20,784 INFO L87 Difference]: Start difference. First operand has 4162 states, 4162 states have (on average 1.4632388274867851) internal successors, (6090), 4161 states have internal predecessors, (6090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4404 states and 6412 transitions. [2022-02-21 04:24:21,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:21,271 INFO L93 Difference]: Finished difference Result 4404 states and 6412 transitions. [2022-02-21 04:24:21,271 INFO L276 IsEmpty]: Start isEmpty. Operand 4404 states and 6412 transitions. [2022-02-21 04:24:21,277 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:21,277 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:21,277 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:21,278 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:21,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4162 states, 4162 states have (on average 1.4632388274867851) internal successors, (6090), 4161 states have internal predecessors, (6090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4162 states to 4162 states and 6090 transitions. [2022-02-21 04:24:21,767 INFO L704 BuchiCegarLoop]: Abstraction has 4162 states and 6090 transitions. [2022-02-21 04:24:21,768 INFO L587 BuchiCegarLoop]: Abstraction has 4162 states and 6090 transitions. [2022-02-21 04:24:21,768 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:21,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4162 states and 6090 transitions. [2022-02-21 04:24:21,782 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4058 [2022-02-21 04:24:21,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:21,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:21,784 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:21,784 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:21,784 INFO L791 eck$LassoCheckResult]: Stem: 25390#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 25362#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 25353#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25350#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25239#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 25240#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25033#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25034#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25348#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25349#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25310#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25004#L586 assume !(0 == ~M_E~0); 25005#L586-2 assume !(0 == ~T1_E~0); 25059#L591-1 assume !(0 == ~T2_E~0); 25187#L596-1 assume !(0 == ~T3_E~0); 25188#L601-1 assume !(0 == ~T4_E~0); 25229#L606-1 assume !(0 == ~T5_E~0); 25230#L611-1 assume !(0 == ~E_1~0); 25319#L616-1 assume !(0 == ~E_2~0); 25320#L621-1 assume !(0 == ~E_3~0); 24936#L626-1 assume !(0 == ~E_4~0); 24937#L631-1 assume !(0 == ~E_5~0); 25093#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24932#L279 assume !(1 == ~m_pc~0); 24933#L279-2 is_master_triggered_~__retres1~0#1 := 0; 25249#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25163#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 25164#L720 assume !(0 != activate_threads_~tmp~1#1); 25248#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25097#L298 assume !(1 == ~t1_pc~0); 24888#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24889#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25152#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24945#L728 assume !(0 != activate_threads_~tmp___0~0#1); 24946#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25065#L317 assume !(1 == ~t2_pc~0); 25066#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25268#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25358#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25107#L736 assume !(0 != activate_threads_~tmp___1~0#1); 25108#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25308#L336 assume 1 == ~t3_pc~0; 25156#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25157#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25212#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25213#L744 assume !(0 != activate_threads_~tmp___2~0#1); 25258#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25316#L355 assume !(1 == ~t4_pc~0); 25184#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25019#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25020#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25243#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24955#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24956#L374 assume 1 == ~t5_pc~0; 25339#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25085#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25161#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25162#L760 assume !(0 != activate_threads_~tmp___4~0#1); 25215#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25216#L649 assume !(1 == ~M_E~0); 25368#L649-2 assume !(1 == ~T1_E~0); 24920#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24921#L659-1 assume !(1 == ~T3_E~0); 27798#L664-1 assume !(1 == ~T4_E~0); 24913#L669-1 assume !(1 == ~T5_E~0); 24914#L674-1 assume !(1 == ~E_1~0); 25313#L679-1 assume !(1 == ~E_2~0); 25314#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 25011#L689-1 assume !(1 == ~E_4~0); 27775#L694-1 assume !(1 == ~E_5~0); 25176#L699-1 assume { :end_inline_reset_delta_events } true; 25177#L900-2 [2022-02-21 04:24:21,784 INFO L793 eck$LassoCheckResult]: Loop: 25177#L900-2 assume !false; 28262#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28259#L561 assume !false; 28256#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 28244#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 28238#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 28220#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28214#L486 assume !(0 != eval_~tmp~0#1); 28215#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28587#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28585#L586-3 assume !(0 == ~M_E~0); 28582#L586-5 assume !(0 == ~T1_E~0); 28580#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28578#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28576#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28574#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28572#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28569#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28567#L621-3 assume !(0 == ~E_3~0); 28565#L626-3 assume !(0 == ~E_4~0); 28563#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28561#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28559#L279-18 assume !(1 == ~m_pc~0); 28556#L279-20 is_master_triggered_~__retres1~0#1 := 0; 28555#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28554#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 28553#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28552#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28551#L298-18 assume 1 == ~t1_pc~0; 28544#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28542#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28540#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28538#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28536#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28534#L317-18 assume !(1 == ~t2_pc~0); 28532#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 28530#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28528#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 28526#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28524#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28521#L336-18 assume 1 == ~t3_pc~0; 28518#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28516#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28514#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28512#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28510#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28507#L355-18 assume !(1 == ~t4_pc~0); 28504#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 28502#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28500#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28498#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28496#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28495#L374-18 assume 1 == ~t5_pc~0; 28491#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28489#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28487#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28485#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28483#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28482#L649-3 assume !(1 == ~M_E~0); 28479#L649-5 assume !(1 == ~T1_E~0); 28477#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27673#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28474#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28471#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28469#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28467#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28466#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27653#L689-3 assume !(1 == ~E_4~0); 28463#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28461#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 28459#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 28452#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 28451#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 28448#L919 assume !(0 == start_simulation_~tmp~3#1); 28447#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 28442#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 28436#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 28434#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 28432#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28430#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28428#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 28425#L932 assume !(0 != start_simulation_~tmp___0~1#1); 25177#L900-2 [2022-02-21 04:24:21,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:21,785 INFO L85 PathProgramCache]: Analyzing trace with hash -318127708, now seen corresponding path program 1 times [2022-02-21 04:24:21,785 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:21,785 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870094447] [2022-02-21 04:24:21,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:21,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:21,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:21,826 INFO L290 TraceCheckUtils]: 0: Hoare triple {37812#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,826 INFO L290 TraceCheckUtils]: 1: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,827 INFO L290 TraceCheckUtils]: 2: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,827 INFO L290 TraceCheckUtils]: 3: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,828 INFO L290 TraceCheckUtils]: 4: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,828 INFO L290 TraceCheckUtils]: 5: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,828 INFO L290 TraceCheckUtils]: 6: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,829 INFO L290 TraceCheckUtils]: 7: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,829 INFO L290 TraceCheckUtils]: 8: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,829 INFO L290 TraceCheckUtils]: 9: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,830 INFO L290 TraceCheckUtils]: 10: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,830 INFO L290 TraceCheckUtils]: 11: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~M_E~0); {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,831 INFO L290 TraceCheckUtils]: 12: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T1_E~0); {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,831 INFO L290 TraceCheckUtils]: 13: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T2_E~0); {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,831 INFO L290 TraceCheckUtils]: 14: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T3_E~0); {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,832 INFO L290 TraceCheckUtils]: 15: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T4_E~0); {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,832 INFO L290 TraceCheckUtils]: 16: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T5_E~0); {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,832 INFO L290 TraceCheckUtils]: 17: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_1~0); {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,833 INFO L290 TraceCheckUtils]: 18: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_2~0); {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,833 INFO L290 TraceCheckUtils]: 19: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_3~0); {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,833 INFO L290 TraceCheckUtils]: 20: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_4~0); {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,834 INFO L290 TraceCheckUtils]: 21: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_5~0); {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,834 INFO L290 TraceCheckUtils]: 22: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37814#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:21,835 INFO L290 TraceCheckUtils]: 23: Hoare triple {37814#(= ~m_pc~0 ~t3_pc~0)} assume !(1 == ~m_pc~0); {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,835 INFO L290 TraceCheckUtils]: 24: Hoare triple {37815#(not (= ~t3_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,835 INFO L290 TraceCheckUtils]: 25: Hoare triple {37815#(not (= ~t3_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,836 INFO L290 TraceCheckUtils]: 26: Hoare triple {37815#(not (= ~t3_pc~0 1))} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,836 INFO L290 TraceCheckUtils]: 27: Hoare triple {37815#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,836 INFO L290 TraceCheckUtils]: 28: Hoare triple {37815#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,836 INFO L290 TraceCheckUtils]: 29: Hoare triple {37815#(not (= ~t3_pc~0 1))} assume !(1 == ~t1_pc~0); {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,837 INFO L290 TraceCheckUtils]: 30: Hoare triple {37815#(not (= ~t3_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,837 INFO L290 TraceCheckUtils]: 31: Hoare triple {37815#(not (= ~t3_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,837 INFO L290 TraceCheckUtils]: 32: Hoare triple {37815#(not (= ~t3_pc~0 1))} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,838 INFO L290 TraceCheckUtils]: 33: Hoare triple {37815#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,838 INFO L290 TraceCheckUtils]: 34: Hoare triple {37815#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,838 INFO L290 TraceCheckUtils]: 35: Hoare triple {37815#(not (= ~t3_pc~0 1))} assume !(1 == ~t2_pc~0); {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,839 INFO L290 TraceCheckUtils]: 36: Hoare triple {37815#(not (= ~t3_pc~0 1))} is_transmit2_triggered_~__retres1~2#1 := 0; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,839 INFO L290 TraceCheckUtils]: 37: Hoare triple {37815#(not (= ~t3_pc~0 1))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,839 INFO L290 TraceCheckUtils]: 38: Hoare triple {37815#(not (= ~t3_pc~0 1))} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,840 INFO L290 TraceCheckUtils]: 39: Hoare triple {37815#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___1~0#1); {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,840 INFO L290 TraceCheckUtils]: 40: Hoare triple {37815#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {37815#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:21,840 INFO L290 TraceCheckUtils]: 41: Hoare triple {37815#(not (= ~t3_pc~0 1))} assume 1 == ~t3_pc~0; {37813#false} is VALID [2022-02-21 04:24:21,840 INFO L290 TraceCheckUtils]: 42: Hoare triple {37813#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {37813#false} is VALID [2022-02-21 04:24:21,841 INFO L290 TraceCheckUtils]: 43: Hoare triple {37813#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {37813#false} is VALID [2022-02-21 04:24:21,841 INFO L290 TraceCheckUtils]: 44: Hoare triple {37813#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {37813#false} is VALID [2022-02-21 04:24:21,841 INFO L290 TraceCheckUtils]: 45: Hoare triple {37813#false} assume !(0 != activate_threads_~tmp___2~0#1); {37813#false} is VALID [2022-02-21 04:24:21,841 INFO L290 TraceCheckUtils]: 46: Hoare triple {37813#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {37813#false} is VALID [2022-02-21 04:24:21,841 INFO L290 TraceCheckUtils]: 47: Hoare triple {37813#false} assume !(1 == ~t4_pc~0); {37813#false} is VALID [2022-02-21 04:24:21,841 INFO L290 TraceCheckUtils]: 48: Hoare triple {37813#false} is_transmit4_triggered_~__retres1~4#1 := 0; {37813#false} is VALID [2022-02-21 04:24:21,842 INFO L290 TraceCheckUtils]: 49: Hoare triple {37813#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {37813#false} is VALID [2022-02-21 04:24:21,842 INFO L290 TraceCheckUtils]: 50: Hoare triple {37813#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {37813#false} is VALID [2022-02-21 04:24:21,842 INFO L290 TraceCheckUtils]: 51: Hoare triple {37813#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {37813#false} is VALID [2022-02-21 04:24:21,842 INFO L290 TraceCheckUtils]: 52: Hoare triple {37813#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {37813#false} is VALID [2022-02-21 04:24:21,842 INFO L290 TraceCheckUtils]: 53: Hoare triple {37813#false} assume 1 == ~t5_pc~0; {37813#false} is VALID [2022-02-21 04:24:21,842 INFO L290 TraceCheckUtils]: 54: Hoare triple {37813#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {37813#false} is VALID [2022-02-21 04:24:21,842 INFO L290 TraceCheckUtils]: 55: Hoare triple {37813#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {37813#false} is VALID [2022-02-21 04:24:21,842 INFO L290 TraceCheckUtils]: 56: Hoare triple {37813#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {37813#false} is VALID [2022-02-21 04:24:21,843 INFO L290 TraceCheckUtils]: 57: Hoare triple {37813#false} assume !(0 != activate_threads_~tmp___4~0#1); {37813#false} is VALID [2022-02-21 04:24:21,843 INFO L290 TraceCheckUtils]: 58: Hoare triple {37813#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37813#false} is VALID [2022-02-21 04:24:21,843 INFO L290 TraceCheckUtils]: 59: Hoare triple {37813#false} assume !(1 == ~M_E~0); {37813#false} is VALID [2022-02-21 04:24:21,843 INFO L290 TraceCheckUtils]: 60: Hoare triple {37813#false} assume !(1 == ~T1_E~0); {37813#false} is VALID [2022-02-21 04:24:21,843 INFO L290 TraceCheckUtils]: 61: Hoare triple {37813#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {37813#false} is VALID [2022-02-21 04:24:21,843 INFO L290 TraceCheckUtils]: 62: Hoare triple {37813#false} assume !(1 == ~T3_E~0); {37813#false} is VALID [2022-02-21 04:24:21,843 INFO L290 TraceCheckUtils]: 63: Hoare triple {37813#false} assume !(1 == ~T4_E~0); {37813#false} is VALID [2022-02-21 04:24:21,844 INFO L290 TraceCheckUtils]: 64: Hoare triple {37813#false} assume !(1 == ~T5_E~0); {37813#false} is VALID [2022-02-21 04:24:21,844 INFO L290 TraceCheckUtils]: 65: Hoare triple {37813#false} assume !(1 == ~E_1~0); {37813#false} is VALID [2022-02-21 04:24:21,844 INFO L290 TraceCheckUtils]: 66: Hoare triple {37813#false} assume !(1 == ~E_2~0); {37813#false} is VALID [2022-02-21 04:24:21,844 INFO L290 TraceCheckUtils]: 67: Hoare triple {37813#false} assume 1 == ~E_3~0;~E_3~0 := 2; {37813#false} is VALID [2022-02-21 04:24:21,844 INFO L290 TraceCheckUtils]: 68: Hoare triple {37813#false} assume !(1 == ~E_4~0); {37813#false} is VALID [2022-02-21 04:24:21,844 INFO L290 TraceCheckUtils]: 69: Hoare triple {37813#false} assume !(1 == ~E_5~0); {37813#false} is VALID [2022-02-21 04:24:21,844 INFO L290 TraceCheckUtils]: 70: Hoare triple {37813#false} assume { :end_inline_reset_delta_events } true; {37813#false} is VALID [2022-02-21 04:24:21,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:21,845 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:21,845 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870094447] [2022-02-21 04:24:21,845 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1870094447] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:21,845 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:21,845 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:21,846 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43146031] [2022-02-21 04:24:21,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:21,846 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:21,847 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:21,847 INFO L85 PathProgramCache]: Analyzing trace with hash 468756806, now seen corresponding path program 1 times [2022-02-21 04:24:21,847 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:21,847 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [860276859] [2022-02-21 04:24:21,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:21,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:21,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:21,891 INFO L290 TraceCheckUtils]: 0: Hoare triple {37816#true} assume !false; {37816#true} is VALID [2022-02-21 04:24:21,891 INFO L290 TraceCheckUtils]: 1: Hoare triple {37816#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {37816#true} is VALID [2022-02-21 04:24:21,892 INFO L290 TraceCheckUtils]: 2: Hoare triple {37816#true} assume !false; {37816#true} is VALID [2022-02-21 04:24:21,892 INFO L290 TraceCheckUtils]: 3: Hoare triple {37816#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {37816#true} is VALID [2022-02-21 04:24:21,892 INFO L290 TraceCheckUtils]: 4: Hoare triple {37816#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {37818#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~6#1|)} is VALID [2022-02-21 04:24:21,893 INFO L290 TraceCheckUtils]: 5: Hoare triple {37818#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~6#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {37819#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:21,893 INFO L290 TraceCheckUtils]: 6: Hoare triple {37819#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {37820#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:21,893 INFO L290 TraceCheckUtils]: 7: Hoare triple {37820#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {37817#false} is VALID [2022-02-21 04:24:21,893 INFO L290 TraceCheckUtils]: 8: Hoare triple {37817#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {37817#false} is VALID [2022-02-21 04:24:21,894 INFO L290 TraceCheckUtils]: 9: Hoare triple {37817#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {37817#false} is VALID [2022-02-21 04:24:21,894 INFO L290 TraceCheckUtils]: 10: Hoare triple {37817#false} assume !(0 == ~M_E~0); {37817#false} is VALID [2022-02-21 04:24:21,894 INFO L290 TraceCheckUtils]: 11: Hoare triple {37817#false} assume !(0 == ~T1_E~0); {37817#false} is VALID [2022-02-21 04:24:21,894 INFO L290 TraceCheckUtils]: 12: Hoare triple {37817#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {37817#false} is VALID [2022-02-21 04:24:21,894 INFO L290 TraceCheckUtils]: 13: Hoare triple {37817#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {37817#false} is VALID [2022-02-21 04:24:21,894 INFO L290 TraceCheckUtils]: 14: Hoare triple {37817#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {37817#false} is VALID [2022-02-21 04:24:21,894 INFO L290 TraceCheckUtils]: 15: Hoare triple {37817#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {37817#false} is VALID [2022-02-21 04:24:21,894 INFO L290 TraceCheckUtils]: 16: Hoare triple {37817#false} assume 0 == ~E_1~0;~E_1~0 := 1; {37817#false} is VALID [2022-02-21 04:24:21,895 INFO L290 TraceCheckUtils]: 17: Hoare triple {37817#false} assume 0 == ~E_2~0;~E_2~0 := 1; {37817#false} is VALID [2022-02-21 04:24:21,895 INFO L290 TraceCheckUtils]: 18: Hoare triple {37817#false} assume !(0 == ~E_3~0); {37817#false} is VALID [2022-02-21 04:24:21,895 INFO L290 TraceCheckUtils]: 19: Hoare triple {37817#false} assume !(0 == ~E_4~0); {37817#false} is VALID [2022-02-21 04:24:21,895 INFO L290 TraceCheckUtils]: 20: Hoare triple {37817#false} assume 0 == ~E_5~0;~E_5~0 := 1; {37817#false} is VALID [2022-02-21 04:24:21,895 INFO L290 TraceCheckUtils]: 21: Hoare triple {37817#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37817#false} is VALID [2022-02-21 04:24:21,895 INFO L290 TraceCheckUtils]: 22: Hoare triple {37817#false} assume !(1 == ~m_pc~0); {37817#false} is VALID [2022-02-21 04:24:21,895 INFO L290 TraceCheckUtils]: 23: Hoare triple {37817#false} is_master_triggered_~__retres1~0#1 := 0; {37817#false} is VALID [2022-02-21 04:24:21,896 INFO L290 TraceCheckUtils]: 24: Hoare triple {37817#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37817#false} is VALID [2022-02-21 04:24:21,896 INFO L290 TraceCheckUtils]: 25: Hoare triple {37817#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {37817#false} is VALID [2022-02-21 04:24:21,896 INFO L290 TraceCheckUtils]: 26: Hoare triple {37817#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {37817#false} is VALID [2022-02-21 04:24:21,896 INFO L290 TraceCheckUtils]: 27: Hoare triple {37817#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37817#false} is VALID [2022-02-21 04:24:21,896 INFO L290 TraceCheckUtils]: 28: Hoare triple {37817#false} assume 1 == ~t1_pc~0; {37817#false} is VALID [2022-02-21 04:24:21,896 INFO L290 TraceCheckUtils]: 29: Hoare triple {37817#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {37817#false} is VALID [2022-02-21 04:24:21,896 INFO L290 TraceCheckUtils]: 30: Hoare triple {37817#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37817#false} is VALID [2022-02-21 04:24:21,897 INFO L290 TraceCheckUtils]: 31: Hoare triple {37817#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {37817#false} is VALID [2022-02-21 04:24:21,897 INFO L290 TraceCheckUtils]: 32: Hoare triple {37817#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {37817#false} is VALID [2022-02-21 04:24:21,897 INFO L290 TraceCheckUtils]: 33: Hoare triple {37817#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37817#false} is VALID [2022-02-21 04:24:21,897 INFO L290 TraceCheckUtils]: 34: Hoare triple {37817#false} assume !(1 == ~t2_pc~0); {37817#false} is VALID [2022-02-21 04:24:21,897 INFO L290 TraceCheckUtils]: 35: Hoare triple {37817#false} is_transmit2_triggered_~__retres1~2#1 := 0; {37817#false} is VALID [2022-02-21 04:24:21,897 INFO L290 TraceCheckUtils]: 36: Hoare triple {37817#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37817#false} is VALID [2022-02-21 04:24:21,897 INFO L290 TraceCheckUtils]: 37: Hoare triple {37817#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {37817#false} is VALID [2022-02-21 04:24:21,897 INFO L290 TraceCheckUtils]: 38: Hoare triple {37817#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {37817#false} is VALID [2022-02-21 04:24:21,898 INFO L290 TraceCheckUtils]: 39: Hoare triple {37817#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {37817#false} is VALID [2022-02-21 04:24:21,898 INFO L290 TraceCheckUtils]: 40: Hoare triple {37817#false} assume 1 == ~t3_pc~0; {37817#false} is VALID [2022-02-21 04:24:21,898 INFO L290 TraceCheckUtils]: 41: Hoare triple {37817#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {37817#false} is VALID [2022-02-21 04:24:21,898 INFO L290 TraceCheckUtils]: 42: Hoare triple {37817#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {37817#false} is VALID [2022-02-21 04:24:21,898 INFO L290 TraceCheckUtils]: 43: Hoare triple {37817#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {37817#false} is VALID [2022-02-21 04:24:21,898 INFO L290 TraceCheckUtils]: 44: Hoare triple {37817#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {37817#false} is VALID [2022-02-21 04:24:21,898 INFO L290 TraceCheckUtils]: 45: Hoare triple {37817#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {37817#false} is VALID [2022-02-21 04:24:21,899 INFO L290 TraceCheckUtils]: 46: Hoare triple {37817#false} assume !(1 == ~t4_pc~0); {37817#false} is VALID [2022-02-21 04:24:21,899 INFO L290 TraceCheckUtils]: 47: Hoare triple {37817#false} is_transmit4_triggered_~__retres1~4#1 := 0; {37817#false} is VALID [2022-02-21 04:24:21,899 INFO L290 TraceCheckUtils]: 48: Hoare triple {37817#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {37817#false} is VALID [2022-02-21 04:24:21,899 INFO L290 TraceCheckUtils]: 49: Hoare triple {37817#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {37817#false} is VALID [2022-02-21 04:24:21,899 INFO L290 TraceCheckUtils]: 50: Hoare triple {37817#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {37817#false} is VALID [2022-02-21 04:24:21,899 INFO L290 TraceCheckUtils]: 51: Hoare triple {37817#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {37817#false} is VALID [2022-02-21 04:24:21,899 INFO L290 TraceCheckUtils]: 52: Hoare triple {37817#false} assume 1 == ~t5_pc~0; {37817#false} is VALID [2022-02-21 04:24:21,899 INFO L290 TraceCheckUtils]: 53: Hoare triple {37817#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {37817#false} is VALID [2022-02-21 04:24:21,900 INFO L290 TraceCheckUtils]: 54: Hoare triple {37817#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {37817#false} is VALID [2022-02-21 04:24:21,900 INFO L290 TraceCheckUtils]: 55: Hoare triple {37817#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {37817#false} is VALID [2022-02-21 04:24:21,900 INFO L290 TraceCheckUtils]: 56: Hoare triple {37817#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {37817#false} is VALID [2022-02-21 04:24:21,900 INFO L290 TraceCheckUtils]: 57: Hoare triple {37817#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37817#false} is VALID [2022-02-21 04:24:21,900 INFO L290 TraceCheckUtils]: 58: Hoare triple {37817#false} assume !(1 == ~M_E~0); {37817#false} is VALID [2022-02-21 04:24:21,900 INFO L290 TraceCheckUtils]: 59: Hoare triple {37817#false} assume !(1 == ~T1_E~0); {37817#false} is VALID [2022-02-21 04:24:21,900 INFO L290 TraceCheckUtils]: 60: Hoare triple {37817#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {37817#false} is VALID [2022-02-21 04:24:21,901 INFO L290 TraceCheckUtils]: 61: Hoare triple {37817#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {37817#false} is VALID [2022-02-21 04:24:21,901 INFO L290 TraceCheckUtils]: 62: Hoare triple {37817#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {37817#false} is VALID [2022-02-21 04:24:21,901 INFO L290 TraceCheckUtils]: 63: Hoare triple {37817#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {37817#false} is VALID [2022-02-21 04:24:21,901 INFO L290 TraceCheckUtils]: 64: Hoare triple {37817#false} assume 1 == ~E_1~0;~E_1~0 := 2; {37817#false} is VALID [2022-02-21 04:24:21,901 INFO L290 TraceCheckUtils]: 65: Hoare triple {37817#false} assume 1 == ~E_2~0;~E_2~0 := 2; {37817#false} is VALID [2022-02-21 04:24:21,901 INFO L290 TraceCheckUtils]: 66: Hoare triple {37817#false} assume 1 == ~E_3~0;~E_3~0 := 2; {37817#false} is VALID [2022-02-21 04:24:21,901 INFO L290 TraceCheckUtils]: 67: Hoare triple {37817#false} assume !(1 == ~E_4~0); {37817#false} is VALID [2022-02-21 04:24:21,901 INFO L290 TraceCheckUtils]: 68: Hoare triple {37817#false} assume 1 == ~E_5~0;~E_5~0 := 2; {37817#false} is VALID [2022-02-21 04:24:21,902 INFO L290 TraceCheckUtils]: 69: Hoare triple {37817#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {37817#false} is VALID [2022-02-21 04:24:21,902 INFO L290 TraceCheckUtils]: 70: Hoare triple {37817#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {37817#false} is VALID [2022-02-21 04:24:21,902 INFO L290 TraceCheckUtils]: 71: Hoare triple {37817#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {37817#false} is VALID [2022-02-21 04:24:21,902 INFO L290 TraceCheckUtils]: 72: Hoare triple {37817#false} start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {37817#false} is VALID [2022-02-21 04:24:21,902 INFO L290 TraceCheckUtils]: 73: Hoare triple {37817#false} assume !(0 == start_simulation_~tmp~3#1); {37817#false} is VALID [2022-02-21 04:24:21,902 INFO L290 TraceCheckUtils]: 74: Hoare triple {37817#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {37817#false} is VALID [2022-02-21 04:24:21,902 INFO L290 TraceCheckUtils]: 75: Hoare triple {37817#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {37817#false} is VALID [2022-02-21 04:24:21,903 INFO L290 TraceCheckUtils]: 76: Hoare triple {37817#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {37817#false} is VALID [2022-02-21 04:24:21,903 INFO L290 TraceCheckUtils]: 77: Hoare triple {37817#false} stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; {37817#false} is VALID [2022-02-21 04:24:21,903 INFO L290 TraceCheckUtils]: 78: Hoare triple {37817#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {37817#false} is VALID [2022-02-21 04:24:21,903 INFO L290 TraceCheckUtils]: 79: Hoare triple {37817#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {37817#false} is VALID [2022-02-21 04:24:21,903 INFO L290 TraceCheckUtils]: 80: Hoare triple {37817#false} start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; {37817#false} is VALID [2022-02-21 04:24:21,903 INFO L290 TraceCheckUtils]: 81: Hoare triple {37817#false} assume !(0 != start_simulation_~tmp___0~1#1); {37817#false} is VALID [2022-02-21 04:24:21,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:21,904 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:21,904 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [860276859] [2022-02-21 04:24:21,904 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [860276859] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:21,904 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:21,904 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:21,904 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655080205] [2022-02-21 04:24:21,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:21,905 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:21,905 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:21,906 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:21,906 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:21,907 INFO L87 Difference]: Start difference. First operand 4162 states and 6090 transitions. cyclomatic complexity: 1932 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,121 INFO L93 Difference]: Finished difference Result 11351 states and 16460 transitions. [2022-02-21 04:24:26,121 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:26,121 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,172 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:26,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11351 states and 16460 transitions. [2022-02-21 04:24:28,745 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10788 [2022-02-21 04:24:31,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11351 states to 11351 states and 16460 transitions. [2022-02-21 04:24:31,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11351 [2022-02-21 04:24:31,442 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11351 [2022-02-21 04:24:31,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11351 states and 16460 transitions. [2022-02-21 04:24:31,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:31,457 INFO L681 BuchiCegarLoop]: Abstraction has 11351 states and 16460 transitions. [2022-02-21 04:24:31,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11351 states and 16460 transitions. [2022-02-21 04:24:31,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11351 to 10667. [2022-02-21 04:24:31,642 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:31,656 INFO L82 GeneralOperation]: Start isEquivalent. First operand 11351 states and 16460 transitions. Second operand has 10667 states, 10667 states have (on average 1.4594543920502485) internal successors, (15568), 10666 states have internal predecessors, (15568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,669 INFO L74 IsIncluded]: Start isIncluded. First operand 11351 states and 16460 transitions. Second operand has 10667 states, 10667 states have (on average 1.4594543920502485) internal successors, (15568), 10666 states have internal predecessors, (15568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,683 INFO L87 Difference]: Start difference. First operand 11351 states and 16460 transitions. Second operand has 10667 states, 10667 states have (on average 1.4594543920502485) internal successors, (15568), 10666 states have internal predecessors, (15568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:34,351 INFO L93 Difference]: Finished difference Result 11351 states and 16460 transitions. [2022-02-21 04:24:34,351 INFO L276 IsEmpty]: Start isEmpty. Operand 11351 states and 16460 transitions. [2022-02-21 04:24:34,364 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:34,364 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:34,376 INFO L74 IsIncluded]: Start isIncluded. First operand has 10667 states, 10667 states have (on average 1.4594543920502485) internal successors, (15568), 10666 states have internal predecessors, (15568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 11351 states and 16460 transitions. [2022-02-21 04:24:34,386 INFO L87 Difference]: Start difference. First operand has 10667 states, 10667 states have (on average 1.4594543920502485) internal successors, (15568), 10666 states have internal predecessors, (15568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 11351 states and 16460 transitions. [2022-02-21 04:24:37,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:37,320 INFO L93 Difference]: Finished difference Result 11351 states and 16460 transitions. [2022-02-21 04:24:37,320 INFO L276 IsEmpty]: Start isEmpty. Operand 11351 states and 16460 transitions. [2022-02-21 04:24:37,361 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:37,361 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:37,361 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:37,361 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:37,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10667 states, 10667 states have (on average 1.4594543920502485) internal successors, (15568), 10666 states have internal predecessors, (15568), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10667 states to 10667 states and 15568 transitions. [2022-02-21 04:24:39,899 INFO L704 BuchiCegarLoop]: Abstraction has 10667 states and 15568 transitions. [2022-02-21 04:24:39,899 INFO L587 BuchiCegarLoop]: Abstraction has 10667 states and 15568 transitions. [2022-02-21 04:24:39,899 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:24:39,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10667 states and 15568 transitions. [2022-02-21 04:24:39,924 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10524 [2022-02-21 04:24:39,924 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:39,925 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:39,925 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:39,926 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:39,926 INFO L791 eck$LassoCheckResult]: Stem: 49776#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 49730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 49716#L863 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 49713#L394 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49592#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 49593#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49376#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49377#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49711#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49712#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49667#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49343#L586 assume !(0 == ~M_E~0); 49344#L586-2 assume !(0 == ~T1_E~0); 49404#L591-1 assume !(0 == ~T2_E~0); 49539#L596-1 assume !(0 == ~T3_E~0); 49540#L601-1 assume !(0 == ~T4_E~0); 49582#L606-1 assume !(0 == ~T5_E~0); 49583#L611-1 assume !(0 == ~E_1~0); 49678#L616-1 assume !(0 == ~E_2~0); 49679#L621-1 assume !(0 == ~E_3~0); 49272#L626-1 assume !(0 == ~E_4~0); 49273#L631-1 assume !(0 == ~E_5~0); 49438#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49268#L279 assume !(1 == ~m_pc~0); 49269#L279-2 is_master_triggered_~__retres1~0#1 := 0; 49604#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49516#L291 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 49517#L720 assume !(0 != activate_threads_~tmp~1#1); 49603#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49444#L298 assume !(1 == ~t1_pc~0); 49224#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49225#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49507#L310 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 49281#L728 assume !(0 != activate_threads_~tmp___0~0#1); 49282#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49410#L317 assume !(1 == ~t2_pc~0); 49411#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49624#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49724#L329 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 49454#L736 assume !(0 != activate_threads_~tmp___1~0#1); 49455#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49664#L336 assume !(1 == ~t3_pc~0); 49665#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 49753#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49565#L348 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 49566#L744 assume !(0 != activate_threads_~tmp___2~0#1); 49612#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49674#L355 assume !(1 == ~t4_pc~0); 49536#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49362#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49363#L367 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49597#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49294#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49295#L374 assume 1 == ~t5_pc~0; 49701#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49429#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49514#L386 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49515#L760 assume !(0 != activate_threads_~tmp___4~0#1); 49568#L760-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49569#L649 assume !(1 == ~M_E~0); 49742#L649-2 assume !(1 == ~T1_E~0); 49256#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49257#L659-1 assume !(1 == ~T3_E~0); 49452#L664-1 assume !(1 == ~T4_E~0); 49453#L669-1 assume !(1 == ~T5_E~0); 49659#L674-1 assume !(1 == ~E_1~0); 49660#L679-1 assume !(1 == ~E_2~0); 49349#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 49350#L689-1 assume !(1 == ~E_4~0); 49772#L694-1 assume !(1 == ~E_5~0); 49773#L699-1 assume { :end_inline_reset_delta_events } true; 55594#L900-2 [2022-02-21 04:24:39,926 INFO L793 eck$LassoCheckResult]: Loop: 55594#L900-2 assume !false; 55595#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55578#L561 assume !false; 55579#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 55563#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 55559#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 55545#L472 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55546#L486 assume !(0 != eval_~tmp~0#1); 58212#L576 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58565#L394-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58564#L586-3 assume !(0 == ~M_E~0); 58563#L586-5 assume !(0 == ~T1_E~0); 58562#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58561#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58560#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58559#L606-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 58558#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 58557#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58556#L621-3 assume !(0 == ~E_3~0); 58555#L626-3 assume !(0 == ~E_4~0); 58554#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58553#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58552#L279-18 assume !(1 == ~m_pc~0); 58551#L279-20 is_master_triggered_~__retres1~0#1 := 0; 58550#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58549#L291-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 58548#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58547#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58546#L298-18 assume 1 == ~t1_pc~0; 58544#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58543#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58542#L310-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 58541#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58540#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58539#L317-18 assume !(1 == ~t2_pc~0); 58538#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 58537#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58536#L329-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 58535#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58534#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58533#L336-18 assume !(1 == ~t3_pc~0); 58532#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 58531#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58530#L348-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 58529#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58528#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58527#L355-18 assume !(1 == ~t4_pc~0); 58525#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 58524#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58523#L367-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 58522#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58521#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58520#L374-18 assume 1 == ~t5_pc~0; 58518#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58517#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58516#L386-6 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 58515#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58514#L760-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58513#L649-3 assume !(1 == ~M_E~0); 58510#L649-5 assume !(1 == ~T1_E~0); 58509#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58393#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58508#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58507#L669-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58506#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55805#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55806#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58384#L689-3 assume !(1 == ~E_4~0); 58383#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58382#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 55716#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 55711#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 55696#L472-1 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 55697#L919 assume !(0 == start_simulation_~tmp~3#1); 55684#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 55685#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 58260#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 58259#L472-2 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 58258#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 58257#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 58256#L882 start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 58255#L932 assume !(0 != start_simulation_~tmp___0~1#1); 55594#L900-2 [2022-02-21 04:24:39,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:39,927 INFO L85 PathProgramCache]: Analyzing trace with hash -375271933, now seen corresponding path program 1 times [2022-02-21 04:24:39,927 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:39,927 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713283070] [2022-02-21 04:24:39,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:39,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:39,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:39,973 INFO L290 TraceCheckUtils]: 0: Hoare triple {82546#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; {82546#true} is VALID [2022-02-21 04:24:39,974 INFO L290 TraceCheckUtils]: 1: Hoare triple {82546#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; {82546#true} is VALID [2022-02-21 04:24:39,974 INFO L290 TraceCheckUtils]: 2: Hoare triple {82546#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {82546#true} is VALID [2022-02-21 04:24:39,974 INFO L290 TraceCheckUtils]: 3: Hoare triple {82546#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {82546#true} is VALID [2022-02-21 04:24:39,974 INFO L290 TraceCheckUtils]: 4: Hoare triple {82546#true} assume 1 == ~m_i~0;~m_st~0 := 0; {82546#true} is VALID [2022-02-21 04:24:39,974 INFO L290 TraceCheckUtils]: 5: Hoare triple {82546#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {82546#true} is VALID [2022-02-21 04:24:39,974 INFO L290 TraceCheckUtils]: 6: Hoare triple {82546#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {82546#true} is VALID [2022-02-21 04:24:39,975 INFO L290 TraceCheckUtils]: 7: Hoare triple {82546#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {82546#true} is VALID [2022-02-21 04:24:39,975 INFO L290 TraceCheckUtils]: 8: Hoare triple {82546#true} assume 1 == ~t4_i~0;~t4_st~0 := 0; {82546#true} is VALID [2022-02-21 04:24:39,975 INFO L290 TraceCheckUtils]: 9: Hoare triple {82546#true} assume 1 == ~t5_i~0;~t5_st~0 := 0; {82546#true} is VALID [2022-02-21 04:24:39,975 INFO L290 TraceCheckUtils]: 10: Hoare triple {82546#true} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {82546#true} is VALID [2022-02-21 04:24:39,975 INFO L290 TraceCheckUtils]: 11: Hoare triple {82546#true} assume !(0 == ~M_E~0); {82546#true} is VALID [2022-02-21 04:24:39,975 INFO L290 TraceCheckUtils]: 12: Hoare triple {82546#true} assume !(0 == ~T1_E~0); {82546#true} is VALID [2022-02-21 04:24:39,975 INFO L290 TraceCheckUtils]: 13: Hoare triple {82546#true} assume !(0 == ~T2_E~0); {82546#true} is VALID [2022-02-21 04:24:39,976 INFO L290 TraceCheckUtils]: 14: Hoare triple {82546#true} assume !(0 == ~T3_E~0); {82546#true} is VALID [2022-02-21 04:24:39,976 INFO L290 TraceCheckUtils]: 15: Hoare triple {82546#true} assume !(0 == ~T4_E~0); {82546#true} is VALID [2022-02-21 04:24:39,976 INFO L290 TraceCheckUtils]: 16: Hoare triple {82546#true} assume !(0 == ~T5_E~0); {82546#true} is VALID [2022-02-21 04:24:39,976 INFO L290 TraceCheckUtils]: 17: Hoare triple {82546#true} assume !(0 == ~E_1~0); {82546#true} is VALID [2022-02-21 04:24:39,976 INFO L290 TraceCheckUtils]: 18: Hoare triple {82546#true} assume !(0 == ~E_2~0); {82546#true} is VALID [2022-02-21 04:24:39,976 INFO L290 TraceCheckUtils]: 19: Hoare triple {82546#true} assume !(0 == ~E_3~0); {82546#true} is VALID [2022-02-21 04:24:39,976 INFO L290 TraceCheckUtils]: 20: Hoare triple {82546#true} assume !(0 == ~E_4~0); {82546#true} is VALID [2022-02-21 04:24:39,977 INFO L290 TraceCheckUtils]: 21: Hoare triple {82546#true} assume !(0 == ~E_5~0); {82546#true} is VALID [2022-02-21 04:24:39,977 INFO L290 TraceCheckUtils]: 22: Hoare triple {82546#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {82546#true} is VALID [2022-02-21 04:24:39,977 INFO L290 TraceCheckUtils]: 23: Hoare triple {82546#true} assume !(1 == ~m_pc~0); {82546#true} is VALID [2022-02-21 04:24:39,977 INFO L290 TraceCheckUtils]: 24: Hoare triple {82546#true} is_master_triggered_~__retres1~0#1 := 0; {82546#true} is VALID [2022-02-21 04:24:39,977 INFO L290 TraceCheckUtils]: 25: Hoare triple {82546#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {82546#true} is VALID [2022-02-21 04:24:39,977 INFO L290 TraceCheckUtils]: 26: Hoare triple {82546#true} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {82546#true} is VALID [2022-02-21 04:24:39,977 INFO L290 TraceCheckUtils]: 27: Hoare triple {82546#true} assume !(0 != activate_threads_~tmp~1#1); {82546#true} is VALID [2022-02-21 04:24:39,978 INFO L290 TraceCheckUtils]: 28: Hoare triple {82546#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {82546#true} is VALID [2022-02-21 04:24:39,978 INFO L290 TraceCheckUtils]: 29: Hoare triple {82546#true} assume !(1 == ~t1_pc~0); {82546#true} is VALID [2022-02-21 04:24:39,978 INFO L290 TraceCheckUtils]: 30: Hoare triple {82546#true} is_transmit1_triggered_~__retres1~1#1 := 0; {82546#true} is VALID [2022-02-21 04:24:39,978 INFO L290 TraceCheckUtils]: 31: Hoare triple {82546#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {82546#true} is VALID [2022-02-21 04:24:39,978 INFO L290 TraceCheckUtils]: 32: Hoare triple {82546#true} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {82546#true} is VALID [2022-02-21 04:24:39,978 INFO L290 TraceCheckUtils]: 33: Hoare triple {82546#true} assume !(0 != activate_threads_~tmp___0~0#1); {82546#true} is VALID [2022-02-21 04:24:39,978 INFO L290 TraceCheckUtils]: 34: Hoare triple {82546#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {82546#true} is VALID [2022-02-21 04:24:39,979 INFO L290 TraceCheckUtils]: 35: Hoare triple {82546#true} assume !(1 == ~t2_pc~0); {82546#true} is VALID [2022-02-21 04:24:39,979 INFO L290 TraceCheckUtils]: 36: Hoare triple {82546#true} is_transmit2_triggered_~__retres1~2#1 := 0; {82546#true} is VALID [2022-02-21 04:24:39,979 INFO L290 TraceCheckUtils]: 37: Hoare triple {82546#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {82546#true} is VALID [2022-02-21 04:24:39,979 INFO L290 TraceCheckUtils]: 38: Hoare triple {82546#true} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {82546#true} is VALID [2022-02-21 04:24:39,979 INFO L290 TraceCheckUtils]: 39: Hoare triple {82546#true} assume !(0 != activate_threads_~tmp___1~0#1); {82546#true} is VALID [2022-02-21 04:24:39,979 INFO L290 TraceCheckUtils]: 40: Hoare triple {82546#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {82546#true} is VALID [2022-02-21 04:24:39,992 INFO L290 TraceCheckUtils]: 41: Hoare triple {82546#true} assume !(1 == ~t3_pc~0); {82546#true} is VALID [2022-02-21 04:24:39,992 INFO L290 TraceCheckUtils]: 42: Hoare triple {82546#true} is_transmit3_triggered_~__retres1~3#1 := 0; {82546#true} is VALID [2022-02-21 04:24:39,992 INFO L290 TraceCheckUtils]: 43: Hoare triple {82546#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {82546#true} is VALID [2022-02-21 04:24:39,992 INFO L290 TraceCheckUtils]: 44: Hoare triple {82546#true} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {82546#true} is VALID [2022-02-21 04:24:39,993 INFO L290 TraceCheckUtils]: 45: Hoare triple {82546#true} assume !(0 != activate_threads_~tmp___2~0#1); {82546#true} is VALID [2022-02-21 04:24:39,993 INFO L290 TraceCheckUtils]: 46: Hoare triple {82546#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {82546#true} is VALID [2022-02-21 04:24:39,993 INFO L290 TraceCheckUtils]: 47: Hoare triple {82546#true} assume !(1 == ~t4_pc~0); {82546#true} is VALID [2022-02-21 04:24:39,993 INFO L290 TraceCheckUtils]: 48: Hoare triple {82546#true} is_transmit4_triggered_~__retres1~4#1 := 0; {82548#(= |ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1| 0)} is VALID [2022-02-21 04:24:39,994 INFO L290 TraceCheckUtils]: 49: Hoare triple {82548#(= |ULTIMATE.start_is_transmit4_triggered_~__retres1~4#1| 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {82549#(= |ULTIMATE.start_is_transmit4_triggered_#res#1| 0)} is VALID [2022-02-21 04:24:39,994 INFO L290 TraceCheckUtils]: 50: Hoare triple {82549#(= |ULTIMATE.start_is_transmit4_triggered_#res#1| 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {82550#(= |ULTIMATE.start_activate_threads_~tmp___3~0#1| 0)} is VALID [2022-02-21 04:24:39,995 INFO L290 TraceCheckUtils]: 51: Hoare triple {82550#(= |ULTIMATE.start_activate_threads_~tmp___3~0#1| 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {82547#false} is VALID [2022-02-21 04:24:39,995 INFO L290 TraceCheckUtils]: 52: Hoare triple {82547#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {82547#false} is VALID [2022-02-21 04:24:39,995 INFO L290 TraceCheckUtils]: 53: Hoare triple {82547#false} assume 1 == ~t5_pc~0; {82547#false} is VALID [2022-02-21 04:24:39,995 INFO L290 TraceCheckUtils]: 54: Hoare triple {82547#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {82547#false} is VALID [2022-02-21 04:24:39,995 INFO L290 TraceCheckUtils]: 55: Hoare triple {82547#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {82547#false} is VALID [2022-02-21 04:24:39,995 INFO L290 TraceCheckUtils]: 56: Hoare triple {82547#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {82547#false} is VALID [2022-02-21 04:24:39,995 INFO L290 TraceCheckUtils]: 57: Hoare triple {82547#false} assume !(0 != activate_threads_~tmp___4~0#1); {82547#false} is VALID [2022-02-21 04:24:39,996 INFO L290 TraceCheckUtils]: 58: Hoare triple {82547#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {82547#false} is VALID [2022-02-21 04:24:39,996 INFO L290 TraceCheckUtils]: 59: Hoare triple {82547#false} assume !(1 == ~M_E~0); {82547#false} is VALID [2022-02-21 04:24:39,996 INFO L290 TraceCheckUtils]: 60: Hoare triple {82547#false} assume !(1 == ~T1_E~0); {82547#false} is VALID [2022-02-21 04:24:39,996 INFO L290 TraceCheckUtils]: 61: Hoare triple {82547#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {82547#false} is VALID [2022-02-21 04:24:39,996 INFO L290 TraceCheckUtils]: 62: Hoare triple {82547#false} assume !(1 == ~T3_E~0); {82547#false} is VALID [2022-02-21 04:24:39,996 INFO L290 TraceCheckUtils]: 63: Hoare triple {82547#false} assume !(1 == ~T4_E~0); {82547#false} is VALID [2022-02-21 04:24:39,996 INFO L290 TraceCheckUtils]: 64: Hoare triple {82547#false} assume !(1 == ~T5_E~0); {82547#false} is VALID [2022-02-21 04:24:39,997 INFO L290 TraceCheckUtils]: 65: Hoare triple {82547#false} assume !(1 == ~E_1~0); {82547#false} is VALID [2022-02-21 04:24:39,997 INFO L290 TraceCheckUtils]: 66: Hoare triple {82547#false} assume !(1 == ~E_2~0); {82547#false} is VALID [2022-02-21 04:24:39,997 INFO L290 TraceCheckUtils]: 67: Hoare triple {82547#false} assume 1 == ~E_3~0;~E_3~0 := 2; {82547#false} is VALID [2022-02-21 04:24:39,997 INFO L290 TraceCheckUtils]: 68: Hoare triple {82547#false} assume !(1 == ~E_4~0); {82547#false} is VALID [2022-02-21 04:24:39,997 INFO L290 TraceCheckUtils]: 69: Hoare triple {82547#false} assume !(1 == ~E_5~0); {82547#false} is VALID [2022-02-21 04:24:39,997 INFO L290 TraceCheckUtils]: 70: Hoare triple {82547#false} assume { :end_inline_reset_delta_events } true; {82547#false} is VALID [2022-02-21 04:24:39,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:39,998 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:39,998 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713283070] [2022-02-21 04:24:39,998 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713283070] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:39,998 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:39,998 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:39,999 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [973240133] [2022-02-21 04:24:39,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:40,000 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:40,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:40,000 INFO L85 PathProgramCache]: Analyzing trace with hash -1686757595, now seen corresponding path program 1 times [2022-02-21 04:24:40,001 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:40,001 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271793750] [2022-02-21 04:24:40,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:40,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:40,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:40,040 INFO L290 TraceCheckUtils]: 0: Hoare triple {82551#true} assume !false; {82551#true} is VALID [2022-02-21 04:24:40,040 INFO L290 TraceCheckUtils]: 1: Hoare triple {82551#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {82551#true} is VALID [2022-02-21 04:24:40,040 INFO L290 TraceCheckUtils]: 2: Hoare triple {82551#true} assume !false; {82551#true} is VALID [2022-02-21 04:24:40,040 INFO L290 TraceCheckUtils]: 3: Hoare triple {82551#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {82551#true} is VALID [2022-02-21 04:24:40,041 INFO L290 TraceCheckUtils]: 4: Hoare triple {82551#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {82553#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~6#1|)} is VALID [2022-02-21 04:24:40,041 INFO L290 TraceCheckUtils]: 5: Hoare triple {82553#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~6#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {82554#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:40,042 INFO L290 TraceCheckUtils]: 6: Hoare triple {82554#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {82555#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:40,042 INFO L290 TraceCheckUtils]: 7: Hoare triple {82555#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {82552#false} is VALID [2022-02-21 04:24:40,042 INFO L290 TraceCheckUtils]: 8: Hoare triple {82552#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {82552#false} is VALID [2022-02-21 04:24:40,042 INFO L290 TraceCheckUtils]: 9: Hoare triple {82552#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {82552#false} is VALID [2022-02-21 04:24:40,042 INFO L290 TraceCheckUtils]: 10: Hoare triple {82552#false} assume !(0 == ~M_E~0); {82552#false} is VALID [2022-02-21 04:24:40,043 INFO L290 TraceCheckUtils]: 11: Hoare triple {82552#false} assume !(0 == ~T1_E~0); {82552#false} is VALID [2022-02-21 04:24:40,043 INFO L290 TraceCheckUtils]: 12: Hoare triple {82552#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {82552#false} is VALID [2022-02-21 04:24:40,043 INFO L290 TraceCheckUtils]: 13: Hoare triple {82552#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {82552#false} is VALID [2022-02-21 04:24:40,043 INFO L290 TraceCheckUtils]: 14: Hoare triple {82552#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {82552#false} is VALID [2022-02-21 04:24:40,043 INFO L290 TraceCheckUtils]: 15: Hoare triple {82552#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {82552#false} is VALID [2022-02-21 04:24:40,043 INFO L290 TraceCheckUtils]: 16: Hoare triple {82552#false} assume 0 == ~E_1~0;~E_1~0 := 1; {82552#false} is VALID [2022-02-21 04:24:40,043 INFO L290 TraceCheckUtils]: 17: Hoare triple {82552#false} assume 0 == ~E_2~0;~E_2~0 := 1; {82552#false} is VALID [2022-02-21 04:24:40,044 INFO L290 TraceCheckUtils]: 18: Hoare triple {82552#false} assume !(0 == ~E_3~0); {82552#false} is VALID [2022-02-21 04:24:40,044 INFO L290 TraceCheckUtils]: 19: Hoare triple {82552#false} assume !(0 == ~E_4~0); {82552#false} is VALID [2022-02-21 04:24:40,044 INFO L290 TraceCheckUtils]: 20: Hoare triple {82552#false} assume 0 == ~E_5~0;~E_5~0 := 1; {82552#false} is VALID [2022-02-21 04:24:40,044 INFO L290 TraceCheckUtils]: 21: Hoare triple {82552#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {82552#false} is VALID [2022-02-21 04:24:40,044 INFO L290 TraceCheckUtils]: 22: Hoare triple {82552#false} assume !(1 == ~m_pc~0); {82552#false} is VALID [2022-02-21 04:24:40,044 INFO L290 TraceCheckUtils]: 23: Hoare triple {82552#false} is_master_triggered_~__retres1~0#1 := 0; {82552#false} is VALID [2022-02-21 04:24:40,044 INFO L290 TraceCheckUtils]: 24: Hoare triple {82552#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {82552#false} is VALID [2022-02-21 04:24:40,045 INFO L290 TraceCheckUtils]: 25: Hoare triple {82552#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {82552#false} is VALID [2022-02-21 04:24:40,045 INFO L290 TraceCheckUtils]: 26: Hoare triple {82552#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {82552#false} is VALID [2022-02-21 04:24:40,045 INFO L290 TraceCheckUtils]: 27: Hoare triple {82552#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {82552#false} is VALID [2022-02-21 04:24:40,045 INFO L290 TraceCheckUtils]: 28: Hoare triple {82552#false} assume 1 == ~t1_pc~0; {82552#false} is VALID [2022-02-21 04:24:40,045 INFO L290 TraceCheckUtils]: 29: Hoare triple {82552#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {82552#false} is VALID [2022-02-21 04:24:40,045 INFO L290 TraceCheckUtils]: 30: Hoare triple {82552#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {82552#false} is VALID [2022-02-21 04:24:40,046 INFO L290 TraceCheckUtils]: 31: Hoare triple {82552#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {82552#false} is VALID [2022-02-21 04:24:40,046 INFO L290 TraceCheckUtils]: 32: Hoare triple {82552#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {82552#false} is VALID [2022-02-21 04:24:40,046 INFO L290 TraceCheckUtils]: 33: Hoare triple {82552#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {82552#false} is VALID [2022-02-21 04:24:40,046 INFO L290 TraceCheckUtils]: 34: Hoare triple {82552#false} assume !(1 == ~t2_pc~0); {82552#false} is VALID [2022-02-21 04:24:40,046 INFO L290 TraceCheckUtils]: 35: Hoare triple {82552#false} is_transmit2_triggered_~__retres1~2#1 := 0; {82552#false} is VALID [2022-02-21 04:24:40,046 INFO L290 TraceCheckUtils]: 36: Hoare triple {82552#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {82552#false} is VALID [2022-02-21 04:24:40,046 INFO L290 TraceCheckUtils]: 37: Hoare triple {82552#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {82552#false} is VALID [2022-02-21 04:24:40,046 INFO L290 TraceCheckUtils]: 38: Hoare triple {82552#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {82552#false} is VALID [2022-02-21 04:24:40,047 INFO L290 TraceCheckUtils]: 39: Hoare triple {82552#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {82552#false} is VALID [2022-02-21 04:24:40,047 INFO L290 TraceCheckUtils]: 40: Hoare triple {82552#false} assume !(1 == ~t3_pc~0); {82552#false} is VALID [2022-02-21 04:24:40,047 INFO L290 TraceCheckUtils]: 41: Hoare triple {82552#false} is_transmit3_triggered_~__retres1~3#1 := 0; {82552#false} is VALID [2022-02-21 04:24:40,047 INFO L290 TraceCheckUtils]: 42: Hoare triple {82552#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {82552#false} is VALID [2022-02-21 04:24:40,047 INFO L290 TraceCheckUtils]: 43: Hoare triple {82552#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {82552#false} is VALID [2022-02-21 04:24:40,047 INFO L290 TraceCheckUtils]: 44: Hoare triple {82552#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {82552#false} is VALID [2022-02-21 04:24:40,047 INFO L290 TraceCheckUtils]: 45: Hoare triple {82552#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {82552#false} is VALID [2022-02-21 04:24:40,048 INFO L290 TraceCheckUtils]: 46: Hoare triple {82552#false} assume !(1 == ~t4_pc~0); {82552#false} is VALID [2022-02-21 04:24:40,048 INFO L290 TraceCheckUtils]: 47: Hoare triple {82552#false} is_transmit4_triggered_~__retres1~4#1 := 0; {82552#false} is VALID [2022-02-21 04:24:40,048 INFO L290 TraceCheckUtils]: 48: Hoare triple {82552#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {82552#false} is VALID [2022-02-21 04:24:40,048 INFO L290 TraceCheckUtils]: 49: Hoare triple {82552#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {82552#false} is VALID [2022-02-21 04:24:40,048 INFO L290 TraceCheckUtils]: 50: Hoare triple {82552#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {82552#false} is VALID [2022-02-21 04:24:40,048 INFO L290 TraceCheckUtils]: 51: Hoare triple {82552#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {82552#false} is VALID [2022-02-21 04:24:40,048 INFO L290 TraceCheckUtils]: 52: Hoare triple {82552#false} assume 1 == ~t5_pc~0; {82552#false} is VALID [2022-02-21 04:24:40,049 INFO L290 TraceCheckUtils]: 53: Hoare triple {82552#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {82552#false} is VALID [2022-02-21 04:24:40,049 INFO L290 TraceCheckUtils]: 54: Hoare triple {82552#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {82552#false} is VALID [2022-02-21 04:24:40,049 INFO L290 TraceCheckUtils]: 55: Hoare triple {82552#false} activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {82552#false} is VALID [2022-02-21 04:24:40,049 INFO L290 TraceCheckUtils]: 56: Hoare triple {82552#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {82552#false} is VALID [2022-02-21 04:24:40,049 INFO L290 TraceCheckUtils]: 57: Hoare triple {82552#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {82552#false} is VALID [2022-02-21 04:24:40,049 INFO L290 TraceCheckUtils]: 58: Hoare triple {82552#false} assume !(1 == ~M_E~0); {82552#false} is VALID [2022-02-21 04:24:40,049 INFO L290 TraceCheckUtils]: 59: Hoare triple {82552#false} assume !(1 == ~T1_E~0); {82552#false} is VALID [2022-02-21 04:24:40,050 INFO L290 TraceCheckUtils]: 60: Hoare triple {82552#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {82552#false} is VALID [2022-02-21 04:24:40,050 INFO L290 TraceCheckUtils]: 61: Hoare triple {82552#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {82552#false} is VALID [2022-02-21 04:24:40,050 INFO L290 TraceCheckUtils]: 62: Hoare triple {82552#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {82552#false} is VALID [2022-02-21 04:24:40,050 INFO L290 TraceCheckUtils]: 63: Hoare triple {82552#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {82552#false} is VALID [2022-02-21 04:24:40,050 INFO L290 TraceCheckUtils]: 64: Hoare triple {82552#false} assume 1 == ~E_1~0;~E_1~0 := 2; {82552#false} is VALID [2022-02-21 04:24:40,050 INFO L290 TraceCheckUtils]: 65: Hoare triple {82552#false} assume 1 == ~E_2~0;~E_2~0 := 2; {82552#false} is VALID [2022-02-21 04:24:40,050 INFO L290 TraceCheckUtils]: 66: Hoare triple {82552#false} assume 1 == ~E_3~0;~E_3~0 := 2; {82552#false} is VALID [2022-02-21 04:24:40,051 INFO L290 TraceCheckUtils]: 67: Hoare triple {82552#false} assume !(1 == ~E_4~0); {82552#false} is VALID [2022-02-21 04:24:40,051 INFO L290 TraceCheckUtils]: 68: Hoare triple {82552#false} assume 1 == ~E_5~0;~E_5~0 := 2; {82552#false} is VALID [2022-02-21 04:24:40,051 INFO L290 TraceCheckUtils]: 69: Hoare triple {82552#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {82552#false} is VALID [2022-02-21 04:24:40,051 INFO L290 TraceCheckUtils]: 70: Hoare triple {82552#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {82552#false} is VALID [2022-02-21 04:24:40,051 INFO L290 TraceCheckUtils]: 71: Hoare triple {82552#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {82552#false} is VALID [2022-02-21 04:24:40,051 INFO L290 TraceCheckUtils]: 72: Hoare triple {82552#false} start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {82552#false} is VALID [2022-02-21 04:24:40,051 INFO L290 TraceCheckUtils]: 73: Hoare triple {82552#false} assume !(0 == start_simulation_~tmp~3#1); {82552#false} is VALID [2022-02-21 04:24:40,052 INFO L290 TraceCheckUtils]: 74: Hoare triple {82552#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; {82552#false} is VALID [2022-02-21 04:24:40,052 INFO L290 TraceCheckUtils]: 75: Hoare triple {82552#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; {82552#false} is VALID [2022-02-21 04:24:40,052 INFO L290 TraceCheckUtils]: 76: Hoare triple {82552#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; {82552#false} is VALID [2022-02-21 04:24:40,052 INFO L290 TraceCheckUtils]: 77: Hoare triple {82552#false} stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; {82552#false} is VALID [2022-02-21 04:24:40,052 INFO L290 TraceCheckUtils]: 78: Hoare triple {82552#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {82552#false} is VALID [2022-02-21 04:24:40,052 INFO L290 TraceCheckUtils]: 79: Hoare triple {82552#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {82552#false} is VALID [2022-02-21 04:24:40,052 INFO L290 TraceCheckUtils]: 80: Hoare triple {82552#false} start_simulation_#t~ret19#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; {82552#false} is VALID [2022-02-21 04:24:40,053 INFO L290 TraceCheckUtils]: 81: Hoare triple {82552#false} assume !(0 != start_simulation_~tmp___0~1#1); {82552#false} is VALID [2022-02-21 04:24:40,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:40,053 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:40,053 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271793750] [2022-02-21 04:24:40,054 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271793750] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:40,054 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:40,054 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:40,054 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127575041] [2022-02-21 04:24:40,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:40,054 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:40,055 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:40,055 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:24:40,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:24:40,055 INFO L87 Difference]: Start difference. First operand 10667 states and 15568 transitions. cyclomatic complexity: 4909 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:56,055 INFO L93 Difference]: Finished difference Result 26236 states and 38605 transitions. [2022-02-21 04:24:56,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:24:56,056 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,103 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:56,104 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26236 states and 38605 transitions. [2022-02-21 04:25:09,748 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 25924