./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.06.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.06.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:24:07,769 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:24:07,772 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:24:07,808 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:24:07,809 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:24:07,812 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:24:07,813 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:24:07,816 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:24:07,817 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:24:07,820 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:24:07,821 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:24:07,822 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:24:07,823 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:24:07,825 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:24:07,826 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:24:07,828 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:24:07,829 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:24:07,830 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:24:07,832 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:24:07,836 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:24:07,837 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:24:07,838 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:24:07,840 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:24:07,840 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:24:07,845 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:24:07,846 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:24:07,846 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:24:07,847 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:24:07,848 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:24:07,848 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:24:07,849 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:24:07,850 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:24:07,851 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:24:07,852 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:24:07,853 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:24:07,853 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:24:07,853 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:24:07,854 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:24:07,854 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:24:07,854 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:24:07,855 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:24:07,856 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:24:07,882 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:24:07,882 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:24:07,883 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:24:07,883 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:24:07,884 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:24:07,884 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:24:07,884 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:24:07,884 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:24:07,885 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:24:07,885 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:24:07,885 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:24:07,886 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:24:07,886 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:24:07,886 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:24:07,886 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:24:07,886 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:24:07,886 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:24:07,886 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:24:07,887 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:24:07,887 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:24:07,887 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:24:07,887 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:24:07,887 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:24:07,887 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:24:07,888 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:24:07,888 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:24:07,888 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:24:07,888 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:24:07,888 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:24:07,888 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:24:07,888 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:24:07,889 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:24:07,890 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df [2022-02-21 04:24:08,106 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:24:08,129 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:24:08,133 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:24:08,134 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:24:08,135 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:24:08,136 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.06.cil.c [2022-02-21 04:24:08,194 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3d82d23fb/7059d50a1c8940649ae8d0e344eb4498/FLAG2aec2202e [2022-02-21 04:24:08,620 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:08,621 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.06.cil.c [2022-02-21 04:24:08,631 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3d82d23fb/7059d50a1c8940649ae8d0e344eb4498/FLAG2aec2202e [2022-02-21 04:24:08,647 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3d82d23fb/7059d50a1c8940649ae8d0e344eb4498 [2022-02-21 04:24:08,649 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:08,651 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:08,653 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:08,653 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:08,656 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:08,657 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,658 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@33529f72 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:08, skipping insertion in model container [2022-02-21 04:24:08,658 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:08" (1/1) ... [2022-02-21 04:24:08,663 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:08,697 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:08,839 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.06.cil.c[706,719] [2022-02-21 04:24:08,933 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:08,946 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:08,960 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.06.cil.c[706,719] [2022-02-21 04:24:08,992 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:09,009 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:09,009 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09 WrapperNode [2022-02-21 04:24:09,010 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:09,010 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:09,011 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:09,011 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:09,016 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09" (1/1) ... [2022-02-21 04:24:09,033 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09" (1/1) ... [2022-02-21 04:24:09,097 INFO L137 Inliner]: procedures = 40, calls = 48, calls flagged for inlining = 43, calls inlined = 104, statements flattened = 1522 [2022-02-21 04:24:09,097 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:09,098 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:09,098 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:09,098 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:09,106 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09" (1/1) ... [2022-02-21 04:24:09,106 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09" (1/1) ... [2022-02-21 04:24:09,113 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09" (1/1) ... [2022-02-21 04:24:09,121 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09" (1/1) ... [2022-02-21 04:24:09,134 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09" (1/1) ... [2022-02-21 04:24:09,181 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09" (1/1) ... [2022-02-21 04:24:09,183 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09" (1/1) ... [2022-02-21 04:24:09,188 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:09,189 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:09,189 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:09,189 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:09,190 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09" (1/1) ... [2022-02-21 04:24:09,200 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:09,215 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:09,244 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:09,273 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:09,277 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:09,277 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:09,277 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:09,277 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:09,371 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:09,372 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:10,307 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:10,323 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:10,323 INFO L299 CfgBuilder]: Removed 10 assume(true) statements. [2022-02-21 04:24:10,326 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:10 BoogieIcfgContainer [2022-02-21 04:24:10,326 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:10,326 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:10,327 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:10,329 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:10,330 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:10,330 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:08" (1/3) ... [2022-02-21 04:24:10,331 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2cdd42e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:10, skipping insertion in model container [2022-02-21 04:24:10,331 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:10,331 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:09" (2/3) ... [2022-02-21 04:24:10,332 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2cdd42e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:10, skipping insertion in model container [2022-02-21 04:24:10,332 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:10,332 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:10" (3/3) ... [2022-02-21 04:24:10,333 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.06.cil.c [2022-02-21 04:24:10,374 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:10,375 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:10,375 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:10,375 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:10,375 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:10,375 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:10,375 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:10,375 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:10,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,504 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 540 [2022-02-21 04:24:10,504 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:10,505 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:10,529 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,529 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,529 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:10,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:10,605 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 540 [2022-02-21 04:24:10,605 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:10,605 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:10,607 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,607 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:10,612 INFO L791 eck$LassoCheckResult]: Stem: 625#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 513#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 414#L987true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5#L454true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3#L461true assume !(1 == ~m_i~0);~m_st~0 := 2; 340#L461-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 555#L466-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 610#L471-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 45#L476-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 272#L481-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 130#L486-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 54#L491-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 525#L670true assume !(0 == ~M_E~0); 301#L670-2true assume !(0 == ~T1_E~0); 251#L675-1true assume !(0 == ~T2_E~0); 338#L680-1true assume !(0 == ~T3_E~0); 432#L685-1true assume !(0 == ~T4_E~0); 306#L690-1true assume !(0 == ~T5_E~0); 609#L695-1true assume !(0 == ~T6_E~0); 384#L700-1true assume 0 == ~E_1~0;~E_1~0 := 1; 373#L705-1true assume !(0 == ~E_2~0); 547#L710-1true assume !(0 == ~E_3~0); 249#L715-1true assume !(0 == ~E_4~0); 192#L720-1true assume !(0 == ~E_5~0); 234#L725-1true assume !(0 == ~E_6~0); 275#L730-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 405#L320true assume 1 == ~m_pc~0; 222#L321true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 153#L331true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 498#L332true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 131#L825true assume !(0 != activate_threads_~tmp~1#1); 447#L825-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134#L339true assume !(1 == ~t1_pc~0); 420#L339-2true is_transmit1_triggered_~__retres1~1#1 := 0; 121#L350true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 388#L351true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57#L833true assume !(0 != activate_threads_~tmp___0~0#1); 537#L833-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14#L358true assume 1 == ~t2_pc~0; 588#L359true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 511#L369true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 303#L370true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 238#L841true assume !(0 != activate_threads_~tmp___1~0#1); 128#L841-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 452#L377true assume !(1 == ~t3_pc~0); 320#L377-2true is_transmit3_triggered_~__retres1~3#1 := 0; 330#L388true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 317#L389true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 133#L849true assume !(0 != activate_threads_~tmp___2~0#1); 335#L849-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101#L396true assume 1 == ~t4_pc~0; 443#L397true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15#L407true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 607#L408true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 263#L857true assume !(0 != activate_threads_~tmp___3~0#1); 85#L857-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 122#L415true assume 1 == ~t5_pc~0; 324#L416true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 276#L426true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 583#L427true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 423#L865true assume !(0 != activate_threads_~tmp___4~0#1); 35#L865-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 321#L434true assume !(1 == ~t6_pc~0); 214#L434-2true is_transmit6_triggered_~__retres1~6#1 := 0; 351#L445true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 604#L446true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 352#L873true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 139#L873-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 535#L743true assume !(1 == ~M_E~0); 80#L743-2true assume !(1 == ~T1_E~0); 484#L748-1true assume !(1 == ~T2_E~0); 268#L753-1true assume !(1 == ~T3_E~0); 389#L758-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 458#L763-1true assume !(1 == ~T5_E~0); 552#L768-1true assume !(1 == ~T6_E~0); 136#L773-1true assume !(1 == ~E_1~0); 623#L778-1true assume !(1 == ~E_2~0); 126#L783-1true assume !(1 == ~E_3~0); 597#L788-1true assume !(1 == ~E_4~0); 336#L793-1true assume !(1 == ~E_5~0); 293#L798-1true assume 1 == ~E_6~0;~E_6~0 := 2; 65#L803-1true assume { :end_inline_reset_delta_events } true; 243#L1024-2true [2022-02-21 04:24:10,628 INFO L793 eck$LassoCheckResult]: Loop: 243#L1024-2true assume !false; 471#L1025true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 459#L645true assume false; 589#L660true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 367#L454-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61#L670-3true assume 0 == ~M_E~0;~M_E~0 := 1; 228#L670-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 150#L675-3true assume !(0 == ~T2_E~0); 426#L680-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 333#L685-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 603#L690-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 558#L695-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 346#L700-3true assume 0 == ~E_1~0;~E_1~0 := 1; 632#L705-3true assume 0 == ~E_2~0;~E_2~0 := 1; 93#L710-3true assume 0 == ~E_3~0;~E_3~0 := 1; 379#L715-3true assume !(0 == ~E_4~0); 240#L720-3true assume 0 == ~E_5~0;~E_5~0 := 1; 307#L725-3true assume 0 == ~E_6~0;~E_6~0 := 1; 495#L730-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137#L320-21true assume 1 == ~m_pc~0; 456#L321-7true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 530#L331-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185#L332-7true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 473#L825-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 441#L825-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99#L339-21true assume !(1 == ~t1_pc~0); 265#L339-23true is_transmit1_triggered_~__retres1~1#1 := 0; 620#L350-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86#L351-7true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26#L833-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 74#L833-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 580#L358-21true assume !(1 == ~t2_pc~0); 104#L358-23true is_transmit2_triggered_~__retres1~2#1 := 0; 66#L369-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 242#L370-7true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 395#L841-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87#L841-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 464#L377-21true assume 1 == ~t3_pc~0; 561#L378-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 262#L388-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 357#L389-7true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 281#L849-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 167#L849-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 294#L396-21true assume !(1 == ~t4_pc~0); 184#L396-23true is_transmit4_triggered_~__retres1~4#1 := 0; 223#L407-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 165#L408-7true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18#L857-21true assume !(0 != activate_threads_~tmp___3~0#1); 297#L857-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 151#L415-21true assume 1 == ~t5_pc~0; 507#L416-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 425#L426-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77#L427-7true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 219#L865-21true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 195#L865-23true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 374#L434-21true assume !(1 == ~t6_pc~0); 30#L434-23true is_transmit6_triggered_~__retres1~6#1 := 0; 419#L445-7true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 431#L446-7true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 147#L873-21true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 256#L873-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144#L743-3true assume 1 == ~M_E~0;~M_E~0 := 2; 491#L743-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 554#L748-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 257#L753-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 209#L758-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 161#L763-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 522#L768-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 465#L773-3true assume !(1 == ~E_1~0); 112#L778-3true assume 1 == ~E_2~0;~E_2~0 := 2; 260#L783-3true assume 1 == ~E_3~0;~E_3~0 := 2; 571#L788-3true assume 1 == ~E_4~0;~E_4~0 := 2; 516#L793-3true assume 1 == ~E_5~0;~E_5~0 := 2; 529#L798-3true assume 1 == ~E_6~0;~E_6~0 := 2; 299#L803-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 107#L504-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 391#L541-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 203#L542-1true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 434#L1043true assume !(0 == start_simulation_~tmp~3#1); 429#L1043-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 258#L504-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 323#L541-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 236#L542-2true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 226#L998true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59#L1005true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 140#L1006true start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 218#L1056true assume !(0 != start_simulation_~tmp___0~1#1); 243#L1024-2true [2022-02-21 04:24:10,634 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:10,635 INFO L85 PathProgramCache]: Analyzing trace with hash -1010496615, now seen corresponding path program 1 times [2022-02-21 04:24:10,641 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:10,642 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1377564996] [2022-02-21 04:24:10,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:10,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:10,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:10,804 INFO L290 TraceCheckUtils]: 0: Hoare triple {637#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {637#true} is VALID [2022-02-21 04:24:10,806 INFO L290 TraceCheckUtils]: 1: Hoare triple {637#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {639#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:10,806 INFO L290 TraceCheckUtils]: 2: Hoare triple {639#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {639#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:10,807 INFO L290 TraceCheckUtils]: 3: Hoare triple {639#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {639#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:10,807 INFO L290 TraceCheckUtils]: 4: Hoare triple {639#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {638#false} is VALID [2022-02-21 04:24:10,808 INFO L290 TraceCheckUtils]: 5: Hoare triple {638#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {638#false} is VALID [2022-02-21 04:24:10,808 INFO L290 TraceCheckUtils]: 6: Hoare triple {638#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {638#false} is VALID [2022-02-21 04:24:10,808 INFO L290 TraceCheckUtils]: 7: Hoare triple {638#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {638#false} is VALID [2022-02-21 04:24:10,809 INFO L290 TraceCheckUtils]: 8: Hoare triple {638#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {638#false} is VALID [2022-02-21 04:24:10,809 INFO L290 TraceCheckUtils]: 9: Hoare triple {638#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {638#false} is VALID [2022-02-21 04:24:10,809 INFO L290 TraceCheckUtils]: 10: Hoare triple {638#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {638#false} is VALID [2022-02-21 04:24:10,809 INFO L290 TraceCheckUtils]: 11: Hoare triple {638#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {638#false} is VALID [2022-02-21 04:24:10,809 INFO L290 TraceCheckUtils]: 12: Hoare triple {638#false} assume !(0 == ~M_E~0); {638#false} is VALID [2022-02-21 04:24:10,809 INFO L290 TraceCheckUtils]: 13: Hoare triple {638#false} assume !(0 == ~T1_E~0); {638#false} is VALID [2022-02-21 04:24:10,810 INFO L290 TraceCheckUtils]: 14: Hoare triple {638#false} assume !(0 == ~T2_E~0); {638#false} is VALID [2022-02-21 04:24:10,810 INFO L290 TraceCheckUtils]: 15: Hoare triple {638#false} assume !(0 == ~T3_E~0); {638#false} is VALID [2022-02-21 04:24:10,810 INFO L290 TraceCheckUtils]: 16: Hoare triple {638#false} assume !(0 == ~T4_E~0); {638#false} is VALID [2022-02-21 04:24:10,810 INFO L290 TraceCheckUtils]: 17: Hoare triple {638#false} assume !(0 == ~T5_E~0); {638#false} is VALID [2022-02-21 04:24:10,810 INFO L290 TraceCheckUtils]: 18: Hoare triple {638#false} assume !(0 == ~T6_E~0); {638#false} is VALID [2022-02-21 04:24:10,810 INFO L290 TraceCheckUtils]: 19: Hoare triple {638#false} assume 0 == ~E_1~0;~E_1~0 := 1; {638#false} is VALID [2022-02-21 04:24:10,811 INFO L290 TraceCheckUtils]: 20: Hoare triple {638#false} assume !(0 == ~E_2~0); {638#false} is VALID [2022-02-21 04:24:10,811 INFO L290 TraceCheckUtils]: 21: Hoare triple {638#false} assume !(0 == ~E_3~0); {638#false} is VALID [2022-02-21 04:24:10,811 INFO L290 TraceCheckUtils]: 22: Hoare triple {638#false} assume !(0 == ~E_4~0); {638#false} is VALID [2022-02-21 04:24:10,811 INFO L290 TraceCheckUtils]: 23: Hoare triple {638#false} assume !(0 == ~E_5~0); {638#false} is VALID [2022-02-21 04:24:10,812 INFO L290 TraceCheckUtils]: 24: Hoare triple {638#false} assume !(0 == ~E_6~0); {638#false} is VALID [2022-02-21 04:24:10,812 INFO L290 TraceCheckUtils]: 25: Hoare triple {638#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {638#false} is VALID [2022-02-21 04:24:10,813 INFO L290 TraceCheckUtils]: 26: Hoare triple {638#false} assume 1 == ~m_pc~0; {638#false} is VALID [2022-02-21 04:24:10,813 INFO L290 TraceCheckUtils]: 27: Hoare triple {638#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {638#false} is VALID [2022-02-21 04:24:10,813 INFO L290 TraceCheckUtils]: 28: Hoare triple {638#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {638#false} is VALID [2022-02-21 04:24:10,813 INFO L290 TraceCheckUtils]: 29: Hoare triple {638#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {638#false} is VALID [2022-02-21 04:24:10,814 INFO L290 TraceCheckUtils]: 30: Hoare triple {638#false} assume !(0 != activate_threads_~tmp~1#1); {638#false} is VALID [2022-02-21 04:24:10,814 INFO L290 TraceCheckUtils]: 31: Hoare triple {638#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {638#false} is VALID [2022-02-21 04:24:10,814 INFO L290 TraceCheckUtils]: 32: Hoare triple {638#false} assume !(1 == ~t1_pc~0); {638#false} is VALID [2022-02-21 04:24:10,814 INFO L290 TraceCheckUtils]: 33: Hoare triple {638#false} is_transmit1_triggered_~__retres1~1#1 := 0; {638#false} is VALID [2022-02-21 04:24:10,814 INFO L290 TraceCheckUtils]: 34: Hoare triple {638#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {638#false} is VALID [2022-02-21 04:24:10,814 INFO L290 TraceCheckUtils]: 35: Hoare triple {638#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {638#false} is VALID [2022-02-21 04:24:10,815 INFO L290 TraceCheckUtils]: 36: Hoare triple {638#false} assume !(0 != activate_threads_~tmp___0~0#1); {638#false} is VALID [2022-02-21 04:24:10,815 INFO L290 TraceCheckUtils]: 37: Hoare triple {638#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {638#false} is VALID [2022-02-21 04:24:10,815 INFO L290 TraceCheckUtils]: 38: Hoare triple {638#false} assume 1 == ~t2_pc~0; {638#false} is VALID [2022-02-21 04:24:10,815 INFO L290 TraceCheckUtils]: 39: Hoare triple {638#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {638#false} is VALID [2022-02-21 04:24:10,816 INFO L290 TraceCheckUtils]: 40: Hoare triple {638#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {638#false} is VALID [2022-02-21 04:24:10,816 INFO L290 TraceCheckUtils]: 41: Hoare triple {638#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {638#false} is VALID [2022-02-21 04:24:10,816 INFO L290 TraceCheckUtils]: 42: Hoare triple {638#false} assume !(0 != activate_threads_~tmp___1~0#1); {638#false} is VALID [2022-02-21 04:24:10,816 INFO L290 TraceCheckUtils]: 43: Hoare triple {638#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {638#false} is VALID [2022-02-21 04:24:10,817 INFO L290 TraceCheckUtils]: 44: Hoare triple {638#false} assume !(1 == ~t3_pc~0); {638#false} is VALID [2022-02-21 04:24:10,817 INFO L290 TraceCheckUtils]: 45: Hoare triple {638#false} is_transmit3_triggered_~__retres1~3#1 := 0; {638#false} is VALID [2022-02-21 04:24:10,817 INFO L290 TraceCheckUtils]: 46: Hoare triple {638#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {638#false} is VALID [2022-02-21 04:24:10,817 INFO L290 TraceCheckUtils]: 47: Hoare triple {638#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {638#false} is VALID [2022-02-21 04:24:10,817 INFO L290 TraceCheckUtils]: 48: Hoare triple {638#false} assume !(0 != activate_threads_~tmp___2~0#1); {638#false} is VALID [2022-02-21 04:24:10,818 INFO L290 TraceCheckUtils]: 49: Hoare triple {638#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {638#false} is VALID [2022-02-21 04:24:10,823 INFO L290 TraceCheckUtils]: 50: Hoare triple {638#false} assume 1 == ~t4_pc~0; {638#false} is VALID [2022-02-21 04:24:10,823 INFO L290 TraceCheckUtils]: 51: Hoare triple {638#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {638#false} is VALID [2022-02-21 04:24:10,823 INFO L290 TraceCheckUtils]: 52: Hoare triple {638#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {638#false} is VALID [2022-02-21 04:24:10,823 INFO L290 TraceCheckUtils]: 53: Hoare triple {638#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {638#false} is VALID [2022-02-21 04:24:10,823 INFO L290 TraceCheckUtils]: 54: Hoare triple {638#false} assume !(0 != activate_threads_~tmp___3~0#1); {638#false} is VALID [2022-02-21 04:24:10,824 INFO L290 TraceCheckUtils]: 55: Hoare triple {638#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {638#false} is VALID [2022-02-21 04:24:10,824 INFO L290 TraceCheckUtils]: 56: Hoare triple {638#false} assume 1 == ~t5_pc~0; {638#false} is VALID [2022-02-21 04:24:10,824 INFO L290 TraceCheckUtils]: 57: Hoare triple {638#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {638#false} is VALID [2022-02-21 04:24:10,824 INFO L290 TraceCheckUtils]: 58: Hoare triple {638#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {638#false} is VALID [2022-02-21 04:24:10,824 INFO L290 TraceCheckUtils]: 59: Hoare triple {638#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {638#false} is VALID [2022-02-21 04:24:10,825 INFO L290 TraceCheckUtils]: 60: Hoare triple {638#false} assume !(0 != activate_threads_~tmp___4~0#1); {638#false} is VALID [2022-02-21 04:24:10,825 INFO L290 TraceCheckUtils]: 61: Hoare triple {638#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {638#false} is VALID [2022-02-21 04:24:10,826 INFO L290 TraceCheckUtils]: 62: Hoare triple {638#false} assume !(1 == ~t6_pc~0); {638#false} is VALID [2022-02-21 04:24:10,826 INFO L290 TraceCheckUtils]: 63: Hoare triple {638#false} is_transmit6_triggered_~__retres1~6#1 := 0; {638#false} is VALID [2022-02-21 04:24:10,826 INFO L290 TraceCheckUtils]: 64: Hoare triple {638#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {638#false} is VALID [2022-02-21 04:24:10,828 INFO L290 TraceCheckUtils]: 65: Hoare triple {638#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {638#false} is VALID [2022-02-21 04:24:10,829 INFO L290 TraceCheckUtils]: 66: Hoare triple {638#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {638#false} is VALID [2022-02-21 04:24:10,829 INFO L290 TraceCheckUtils]: 67: Hoare triple {638#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {638#false} is VALID [2022-02-21 04:24:10,829 INFO L290 TraceCheckUtils]: 68: Hoare triple {638#false} assume !(1 == ~M_E~0); {638#false} is VALID [2022-02-21 04:24:10,830 INFO L290 TraceCheckUtils]: 69: Hoare triple {638#false} assume !(1 == ~T1_E~0); {638#false} is VALID [2022-02-21 04:24:10,830 INFO L290 TraceCheckUtils]: 70: Hoare triple {638#false} assume !(1 == ~T2_E~0); {638#false} is VALID [2022-02-21 04:24:10,830 INFO L290 TraceCheckUtils]: 71: Hoare triple {638#false} assume !(1 == ~T3_E~0); {638#false} is VALID [2022-02-21 04:24:10,830 INFO L290 TraceCheckUtils]: 72: Hoare triple {638#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {638#false} is VALID [2022-02-21 04:24:10,831 INFO L290 TraceCheckUtils]: 73: Hoare triple {638#false} assume !(1 == ~T5_E~0); {638#false} is VALID [2022-02-21 04:24:10,831 INFO L290 TraceCheckUtils]: 74: Hoare triple {638#false} assume !(1 == ~T6_E~0); {638#false} is VALID [2022-02-21 04:24:10,832 INFO L290 TraceCheckUtils]: 75: Hoare triple {638#false} assume !(1 == ~E_1~0); {638#false} is VALID [2022-02-21 04:24:10,832 INFO L290 TraceCheckUtils]: 76: Hoare triple {638#false} assume !(1 == ~E_2~0); {638#false} is VALID [2022-02-21 04:24:10,832 INFO L290 TraceCheckUtils]: 77: Hoare triple {638#false} assume !(1 == ~E_3~0); {638#false} is VALID [2022-02-21 04:24:10,833 INFO L290 TraceCheckUtils]: 78: Hoare triple {638#false} assume !(1 == ~E_4~0); {638#false} is VALID [2022-02-21 04:24:10,833 INFO L290 TraceCheckUtils]: 79: Hoare triple {638#false} assume !(1 == ~E_5~0); {638#false} is VALID [2022-02-21 04:24:10,833 INFO L290 TraceCheckUtils]: 80: Hoare triple {638#false} assume 1 == ~E_6~0;~E_6~0 := 2; {638#false} is VALID [2022-02-21 04:24:10,833 INFO L290 TraceCheckUtils]: 81: Hoare triple {638#false} assume { :end_inline_reset_delta_events } true; {638#false} is VALID [2022-02-21 04:24:10,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:10,835 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:10,835 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1377564996] [2022-02-21 04:24:10,836 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1377564996] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:10,836 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:10,837 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:10,839 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256205331] [2022-02-21 04:24:10,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:10,843 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:10,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:10,846 INFO L85 PathProgramCache]: Analyzing trace with hash -243567112, now seen corresponding path program 1 times [2022-02-21 04:24:10,847 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:10,847 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932596777] [2022-02-21 04:24:10,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:10,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:10,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:10,895 INFO L290 TraceCheckUtils]: 0: Hoare triple {640#true} assume !false; {640#true} is VALID [2022-02-21 04:24:10,896 INFO L290 TraceCheckUtils]: 1: Hoare triple {640#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {640#true} is VALID [2022-02-21 04:24:10,896 INFO L290 TraceCheckUtils]: 2: Hoare triple {640#true} assume false; {641#false} is VALID [2022-02-21 04:24:10,896 INFO L290 TraceCheckUtils]: 3: Hoare triple {641#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {641#false} is VALID [2022-02-21 04:24:10,896 INFO L290 TraceCheckUtils]: 4: Hoare triple {641#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {641#false} is VALID [2022-02-21 04:24:10,897 INFO L290 TraceCheckUtils]: 5: Hoare triple {641#false} assume 0 == ~M_E~0;~M_E~0 := 1; {641#false} is VALID [2022-02-21 04:24:10,899 INFO L290 TraceCheckUtils]: 6: Hoare triple {641#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {641#false} is VALID [2022-02-21 04:24:10,899 INFO L290 TraceCheckUtils]: 7: Hoare triple {641#false} assume !(0 == ~T2_E~0); {641#false} is VALID [2022-02-21 04:24:10,899 INFO L290 TraceCheckUtils]: 8: Hoare triple {641#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {641#false} is VALID [2022-02-21 04:24:10,899 INFO L290 TraceCheckUtils]: 9: Hoare triple {641#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {641#false} is VALID [2022-02-21 04:24:10,899 INFO L290 TraceCheckUtils]: 10: Hoare triple {641#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {641#false} is VALID [2022-02-21 04:24:10,900 INFO L290 TraceCheckUtils]: 11: Hoare triple {641#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {641#false} is VALID [2022-02-21 04:24:10,900 INFO L290 TraceCheckUtils]: 12: Hoare triple {641#false} assume 0 == ~E_1~0;~E_1~0 := 1; {641#false} is VALID [2022-02-21 04:24:10,900 INFO L290 TraceCheckUtils]: 13: Hoare triple {641#false} assume 0 == ~E_2~0;~E_2~0 := 1; {641#false} is VALID [2022-02-21 04:24:10,900 INFO L290 TraceCheckUtils]: 14: Hoare triple {641#false} assume 0 == ~E_3~0;~E_3~0 := 1; {641#false} is VALID [2022-02-21 04:24:10,900 INFO L290 TraceCheckUtils]: 15: Hoare triple {641#false} assume !(0 == ~E_4~0); {641#false} is VALID [2022-02-21 04:24:10,900 INFO L290 TraceCheckUtils]: 16: Hoare triple {641#false} assume 0 == ~E_5~0;~E_5~0 := 1; {641#false} is VALID [2022-02-21 04:24:10,914 INFO L290 TraceCheckUtils]: 17: Hoare triple {641#false} assume 0 == ~E_6~0;~E_6~0 := 1; {641#false} is VALID [2022-02-21 04:24:10,919 INFO L290 TraceCheckUtils]: 18: Hoare triple {641#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {641#false} is VALID [2022-02-21 04:24:10,920 INFO L290 TraceCheckUtils]: 19: Hoare triple {641#false} assume 1 == ~m_pc~0; {641#false} is VALID [2022-02-21 04:24:10,920 INFO L290 TraceCheckUtils]: 20: Hoare triple {641#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {641#false} is VALID [2022-02-21 04:24:10,920 INFO L290 TraceCheckUtils]: 21: Hoare triple {641#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {641#false} is VALID [2022-02-21 04:24:10,920 INFO L290 TraceCheckUtils]: 22: Hoare triple {641#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {641#false} is VALID [2022-02-21 04:24:10,920 INFO L290 TraceCheckUtils]: 23: Hoare triple {641#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {641#false} is VALID [2022-02-21 04:24:10,922 INFO L290 TraceCheckUtils]: 24: Hoare triple {641#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {641#false} is VALID [2022-02-21 04:24:10,923 INFO L290 TraceCheckUtils]: 25: Hoare triple {641#false} assume !(1 == ~t1_pc~0); {641#false} is VALID [2022-02-21 04:24:10,923 INFO L290 TraceCheckUtils]: 26: Hoare triple {641#false} is_transmit1_triggered_~__retres1~1#1 := 0; {641#false} is VALID [2022-02-21 04:24:10,923 INFO L290 TraceCheckUtils]: 27: Hoare triple {641#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {641#false} is VALID [2022-02-21 04:24:10,923 INFO L290 TraceCheckUtils]: 28: Hoare triple {641#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {641#false} is VALID [2022-02-21 04:24:10,923 INFO L290 TraceCheckUtils]: 29: Hoare triple {641#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {641#false} is VALID [2022-02-21 04:24:10,924 INFO L290 TraceCheckUtils]: 30: Hoare triple {641#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {641#false} is VALID [2022-02-21 04:24:10,924 INFO L290 TraceCheckUtils]: 31: Hoare triple {641#false} assume !(1 == ~t2_pc~0); {641#false} is VALID [2022-02-21 04:24:10,925 INFO L290 TraceCheckUtils]: 32: Hoare triple {641#false} is_transmit2_triggered_~__retres1~2#1 := 0; {641#false} is VALID [2022-02-21 04:24:10,925 INFO L290 TraceCheckUtils]: 33: Hoare triple {641#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {641#false} is VALID [2022-02-21 04:24:10,926 INFO L290 TraceCheckUtils]: 34: Hoare triple {641#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {641#false} is VALID [2022-02-21 04:24:10,926 INFO L290 TraceCheckUtils]: 35: Hoare triple {641#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {641#false} is VALID [2022-02-21 04:24:10,927 INFO L290 TraceCheckUtils]: 36: Hoare triple {641#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {641#false} is VALID [2022-02-21 04:24:10,927 INFO L290 TraceCheckUtils]: 37: Hoare triple {641#false} assume 1 == ~t3_pc~0; {641#false} is VALID [2022-02-21 04:24:10,934 INFO L290 TraceCheckUtils]: 38: Hoare triple {641#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {641#false} is VALID [2022-02-21 04:24:10,934 INFO L290 TraceCheckUtils]: 39: Hoare triple {641#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {641#false} is VALID [2022-02-21 04:24:10,935 INFO L290 TraceCheckUtils]: 40: Hoare triple {641#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {641#false} is VALID [2022-02-21 04:24:10,935 INFO L290 TraceCheckUtils]: 41: Hoare triple {641#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {641#false} is VALID [2022-02-21 04:24:10,935 INFO L290 TraceCheckUtils]: 42: Hoare triple {641#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {641#false} is VALID [2022-02-21 04:24:10,935 INFO L290 TraceCheckUtils]: 43: Hoare triple {641#false} assume !(1 == ~t4_pc~0); {641#false} is VALID [2022-02-21 04:24:10,935 INFO L290 TraceCheckUtils]: 44: Hoare triple {641#false} is_transmit4_triggered_~__retres1~4#1 := 0; {641#false} is VALID [2022-02-21 04:24:10,936 INFO L290 TraceCheckUtils]: 45: Hoare triple {641#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {641#false} is VALID [2022-02-21 04:24:10,936 INFO L290 TraceCheckUtils]: 46: Hoare triple {641#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {641#false} is VALID [2022-02-21 04:24:10,936 INFO L290 TraceCheckUtils]: 47: Hoare triple {641#false} assume !(0 != activate_threads_~tmp___3~0#1); {641#false} is VALID [2022-02-21 04:24:10,936 INFO L290 TraceCheckUtils]: 48: Hoare triple {641#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {641#false} is VALID [2022-02-21 04:24:10,936 INFO L290 TraceCheckUtils]: 49: Hoare triple {641#false} assume 1 == ~t5_pc~0; {641#false} is VALID [2022-02-21 04:24:10,936 INFO L290 TraceCheckUtils]: 50: Hoare triple {641#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {641#false} is VALID [2022-02-21 04:24:10,937 INFO L290 TraceCheckUtils]: 51: Hoare triple {641#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {641#false} is VALID [2022-02-21 04:24:10,937 INFO L290 TraceCheckUtils]: 52: Hoare triple {641#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {641#false} is VALID [2022-02-21 04:24:10,937 INFO L290 TraceCheckUtils]: 53: Hoare triple {641#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {641#false} is VALID [2022-02-21 04:24:10,937 INFO L290 TraceCheckUtils]: 54: Hoare triple {641#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {641#false} is VALID [2022-02-21 04:24:10,937 INFO L290 TraceCheckUtils]: 55: Hoare triple {641#false} assume !(1 == ~t6_pc~0); {641#false} is VALID [2022-02-21 04:24:10,937 INFO L290 TraceCheckUtils]: 56: Hoare triple {641#false} is_transmit6_triggered_~__retres1~6#1 := 0; {641#false} is VALID [2022-02-21 04:24:10,938 INFO L290 TraceCheckUtils]: 57: Hoare triple {641#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {641#false} is VALID [2022-02-21 04:24:10,938 INFO L290 TraceCheckUtils]: 58: Hoare triple {641#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {641#false} is VALID [2022-02-21 04:24:10,938 INFO L290 TraceCheckUtils]: 59: Hoare triple {641#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {641#false} is VALID [2022-02-21 04:24:10,938 INFO L290 TraceCheckUtils]: 60: Hoare triple {641#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {641#false} is VALID [2022-02-21 04:24:10,938 INFO L290 TraceCheckUtils]: 61: Hoare triple {641#false} assume 1 == ~M_E~0;~M_E~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,938 INFO L290 TraceCheckUtils]: 62: Hoare triple {641#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,939 INFO L290 TraceCheckUtils]: 63: Hoare triple {641#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,939 INFO L290 TraceCheckUtils]: 64: Hoare triple {641#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,939 INFO L290 TraceCheckUtils]: 65: Hoare triple {641#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,939 INFO L290 TraceCheckUtils]: 66: Hoare triple {641#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,939 INFO L290 TraceCheckUtils]: 67: Hoare triple {641#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,940 INFO L290 TraceCheckUtils]: 68: Hoare triple {641#false} assume !(1 == ~E_1~0); {641#false} is VALID [2022-02-21 04:24:10,940 INFO L290 TraceCheckUtils]: 69: Hoare triple {641#false} assume 1 == ~E_2~0;~E_2~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,940 INFO L290 TraceCheckUtils]: 70: Hoare triple {641#false} assume 1 == ~E_3~0;~E_3~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,940 INFO L290 TraceCheckUtils]: 71: Hoare triple {641#false} assume 1 == ~E_4~0;~E_4~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,940 INFO L290 TraceCheckUtils]: 72: Hoare triple {641#false} assume 1 == ~E_5~0;~E_5~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,940 INFO L290 TraceCheckUtils]: 73: Hoare triple {641#false} assume 1 == ~E_6~0;~E_6~0 := 2; {641#false} is VALID [2022-02-21 04:24:10,941 INFO L290 TraceCheckUtils]: 74: Hoare triple {641#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {641#false} is VALID [2022-02-21 04:24:10,941 INFO L290 TraceCheckUtils]: 75: Hoare triple {641#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {641#false} is VALID [2022-02-21 04:24:10,941 INFO L290 TraceCheckUtils]: 76: Hoare triple {641#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {641#false} is VALID [2022-02-21 04:24:10,941 INFO L290 TraceCheckUtils]: 77: Hoare triple {641#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {641#false} is VALID [2022-02-21 04:24:10,941 INFO L290 TraceCheckUtils]: 78: Hoare triple {641#false} assume !(0 == start_simulation_~tmp~3#1); {641#false} is VALID [2022-02-21 04:24:10,941 INFO L290 TraceCheckUtils]: 79: Hoare triple {641#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {641#false} is VALID [2022-02-21 04:24:10,942 INFO L290 TraceCheckUtils]: 80: Hoare triple {641#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {641#false} is VALID [2022-02-21 04:24:10,942 INFO L290 TraceCheckUtils]: 81: Hoare triple {641#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {641#false} is VALID [2022-02-21 04:24:10,942 INFO L290 TraceCheckUtils]: 82: Hoare triple {641#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {641#false} is VALID [2022-02-21 04:24:10,942 INFO L290 TraceCheckUtils]: 83: Hoare triple {641#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {641#false} is VALID [2022-02-21 04:24:10,942 INFO L290 TraceCheckUtils]: 84: Hoare triple {641#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {641#false} is VALID [2022-02-21 04:24:10,942 INFO L290 TraceCheckUtils]: 85: Hoare triple {641#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {641#false} is VALID [2022-02-21 04:24:10,943 INFO L290 TraceCheckUtils]: 86: Hoare triple {641#false} assume !(0 != start_simulation_~tmp___0~1#1); {641#false} is VALID [2022-02-21 04:24:10,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:10,943 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:10,944 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932596777] [2022-02-21 04:24:10,944 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932596777] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:10,944 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:10,944 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:10,944 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [472220528] [2022-02-21 04:24:10,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:10,945 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:10,946 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:10,968 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:10,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:10,971 INFO L87 Difference]: Start difference. First operand has 633 states, 632 states have (on average 1.5284810126582278) internal successors, (966), 632 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,552 INFO L93 Difference]: Finished difference Result 632 states and 943 transitions. [2022-02-21 04:24:11,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:11,553 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,611 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:11,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 632 states and 943 transitions. [2022-02-21 04:24:11,649 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:11,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 632 states to 626 states and 937 transitions. [2022-02-21 04:24:11,672 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-02-21 04:24:11,673 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-02-21 04:24:11,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 937 transitions. [2022-02-21 04:24:11,675 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:11,675 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 937 transitions. [2022-02-21 04:24:11,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 937 transitions. [2022-02-21 04:24:11,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-02-21 04:24:11,712 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:11,716 INFO L82 GeneralOperation]: Start isEquivalent. First operand 626 states and 937 transitions. Second operand has 626 states, 626 states have (on average 1.4968051118210863) internal successors, (937), 625 states have internal predecessors, (937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,718 INFO L74 IsIncluded]: Start isIncluded. First operand 626 states and 937 transitions. Second operand has 626 states, 626 states have (on average 1.4968051118210863) internal successors, (937), 625 states have internal predecessors, (937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,720 INFO L87 Difference]: Start difference. First operand 626 states and 937 transitions. Second operand has 626 states, 626 states have (on average 1.4968051118210863) internal successors, (937), 625 states have internal predecessors, (937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,740 INFO L93 Difference]: Finished difference Result 626 states and 937 transitions. [2022-02-21 04:24:11,741 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 937 transitions. [2022-02-21 04:24:11,749 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:11,750 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:11,751 INFO L74 IsIncluded]: Start isIncluded. First operand has 626 states, 626 states have (on average 1.4968051118210863) internal successors, (937), 625 states have internal predecessors, (937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 937 transitions. [2022-02-21 04:24:11,752 INFO L87 Difference]: Start difference. First operand has 626 states, 626 states have (on average 1.4968051118210863) internal successors, (937), 625 states have internal predecessors, (937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 937 transitions. [2022-02-21 04:24:11,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:11,778 INFO L93 Difference]: Finished difference Result 626 states and 937 transitions. [2022-02-21 04:24:11,779 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 937 transitions. [2022-02-21 04:24:11,779 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:11,780 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:11,780 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:11,780 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:11,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4968051118210863) internal successors, (937), 625 states have internal predecessors, (937), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:11,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 937 transitions. [2022-02-21 04:24:11,795 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 937 transitions. [2022-02-21 04:24:11,795 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 937 transitions. [2022-02-21 04:24:11,795 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:11,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 937 transitions. [2022-02-21 04:24:11,798 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:11,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:11,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:11,800 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:11,800 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:11,801 INFO L791 eck$LassoCheckResult]: Stem: 1899#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1882#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1834#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1278#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1274#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1275#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1790#L466-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1893#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1370#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1371#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1523#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1387#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1388#L670 assume !(0 == ~M_E~0); 1758#L670-2 assume !(0 == ~T1_E~0); 1706#L675-1 assume !(0 == ~T2_E~0); 1707#L680-1 assume !(0 == ~T3_E~0); 1788#L685-1 assume !(0 == ~T4_E~0); 1761#L690-1 assume !(0 == ~T5_E~0); 1762#L695-1 assume !(0 == ~T6_E~0); 1820#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1812#L705-1 assume !(0 == ~E_2~0); 1813#L710-1 assume !(0 == ~E_3~0); 1705#L715-1 assume !(0 == ~E_4~0); 1629#L720-1 assume !(0 == ~E_5~0); 1630#L725-1 assume !(0 == ~E_6~0); 1683#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1730#L320 assume 1 == ~m_pc~0; 1671#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1565#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1566#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1524#L825 assume !(0 != activate_threads_~tmp~1#1); 1525#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1530#L339 assume !(1 == ~t1_pc~0); 1531#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1508#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1509#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1390#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1391#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1299#L358 assume 1 == ~t2_pc~0; 1300#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1808#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1759#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1687#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1521#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1522#L377 assume !(1 == ~t3_pc~0); 1774#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1775#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1770#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1528#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1529#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1474#L396 assume 1 == ~t4_pc~0; 1475#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1302#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1303#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1721#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1443#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1444#L415 assume 1 == ~t5_pc~0; 1510#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1555#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1731#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1838#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1345#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1346#L434 assume !(1 == ~t6_pc~0); 1660#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1661#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1800#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1801#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1541#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1542#L743 assume !(1 == ~M_E~0); 1435#L743-2 assume !(1 == ~T1_E~0); 1436#L748-1 assume !(1 == ~T2_E~0); 1724#L753-1 assume !(1 == ~T3_E~0); 1725#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1824#L763-1 assume !(1 == ~T5_E~0); 1856#L768-1 assume !(1 == ~T6_E~0); 1536#L773-1 assume !(1 == ~E_1~0); 1537#L778-1 assume !(1 == ~E_2~0); 1516#L783-1 assume !(1 == ~E_3~0); 1517#L788-1 assume !(1 == ~E_4~0); 1786#L793-1 assume !(1 == ~E_5~0); 1751#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1407#L803-1 assume { :end_inline_reset_delta_events } true; 1408#L1024-2 [2022-02-21 04:24:11,801 INFO L793 eck$LassoCheckResult]: Loop: 1408#L1024-2 assume !false; 1693#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1748#L645 assume !false; 1625#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1626#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1353#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1830#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1863#L556 assume !(0 != eval_~tmp~0#1); 1897#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1807#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1401#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1402#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1562#L675-3 assume !(0 == ~T2_E~0); 1563#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1783#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1784#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1894#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1794#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1795#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1456#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1457#L715-3 assume !(0 == ~E_4~0); 1688#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1689#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1763#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1538#L320-21 assume 1 == ~m_pc~0; 1539#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1686#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1612#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1613#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1848#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1469#L339-21 assume !(1 == ~t1_pc~0); 1470#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 1573#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1445#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1327#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1328#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1427#L358-21 assume !(1 == ~t2_pc~0); 1481#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 1409#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1410#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1692#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1446#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1447#L377-21 assume 1 == ~t3_pc~0; 1859#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1718#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1719#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1739#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1584#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1585#L396-21 assume 1 == ~t4_pc~0; 1752#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1611#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1582#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1309#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 1310#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1560#L415-21 assume 1 == ~t5_pc~0; 1561#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1535#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1431#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1432#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1632#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1633#L434-21 assume !(1 == ~t6_pc~0); 1332#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 1333#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1835#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1556#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1557#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1551#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1552#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1872#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1714#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1652#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1575#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1576#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1860#L773-3 assume !(1 == ~E_1~0); 1494#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1495#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1717#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1884#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1885#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1756#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1485#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1381#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1645#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1646#L1043 assume !(0 == start_simulation_~tmp~3#1); 1839#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1715#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1502#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1684#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1673#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1395#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1396#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1543#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 1408#L1024-2 [2022-02-21 04:24:11,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:11,802 INFO L85 PathProgramCache]: Analyzing trace with hash -1849530277, now seen corresponding path program 1 times [2022-02-21 04:24:11,802 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:11,803 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593270078] [2022-02-21 04:24:11,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:11,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:11,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:11,836 INFO L290 TraceCheckUtils]: 0: Hoare triple {3155#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {3155#true} is VALID [2022-02-21 04:24:11,837 INFO L290 TraceCheckUtils]: 1: Hoare triple {3155#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {3157#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:11,837 INFO L290 TraceCheckUtils]: 2: Hoare triple {3157#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {3157#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:11,838 INFO L290 TraceCheckUtils]: 3: Hoare triple {3157#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {3157#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:11,838 INFO L290 TraceCheckUtils]: 4: Hoare triple {3157#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {3157#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:11,838 INFO L290 TraceCheckUtils]: 5: Hoare triple {3157#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {3157#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:11,839 INFO L290 TraceCheckUtils]: 6: Hoare triple {3157#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {3156#false} is VALID [2022-02-21 04:24:11,839 INFO L290 TraceCheckUtils]: 7: Hoare triple {3156#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {3156#false} is VALID [2022-02-21 04:24:11,839 INFO L290 TraceCheckUtils]: 8: Hoare triple {3156#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {3156#false} is VALID [2022-02-21 04:24:11,839 INFO L290 TraceCheckUtils]: 9: Hoare triple {3156#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {3156#false} is VALID [2022-02-21 04:24:11,839 INFO L290 TraceCheckUtils]: 10: Hoare triple {3156#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {3156#false} is VALID [2022-02-21 04:24:11,839 INFO L290 TraceCheckUtils]: 11: Hoare triple {3156#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {3156#false} is VALID [2022-02-21 04:24:11,839 INFO L290 TraceCheckUtils]: 12: Hoare triple {3156#false} assume !(0 == ~M_E~0); {3156#false} is VALID [2022-02-21 04:24:11,840 INFO L290 TraceCheckUtils]: 13: Hoare triple {3156#false} assume !(0 == ~T1_E~0); {3156#false} is VALID [2022-02-21 04:24:11,840 INFO L290 TraceCheckUtils]: 14: Hoare triple {3156#false} assume !(0 == ~T2_E~0); {3156#false} is VALID [2022-02-21 04:24:11,840 INFO L290 TraceCheckUtils]: 15: Hoare triple {3156#false} assume !(0 == ~T3_E~0); {3156#false} is VALID [2022-02-21 04:24:11,840 INFO L290 TraceCheckUtils]: 16: Hoare triple {3156#false} assume !(0 == ~T4_E~0); {3156#false} is VALID [2022-02-21 04:24:11,840 INFO L290 TraceCheckUtils]: 17: Hoare triple {3156#false} assume !(0 == ~T5_E~0); {3156#false} is VALID [2022-02-21 04:24:11,840 INFO L290 TraceCheckUtils]: 18: Hoare triple {3156#false} assume !(0 == ~T6_E~0); {3156#false} is VALID [2022-02-21 04:24:11,840 INFO L290 TraceCheckUtils]: 19: Hoare triple {3156#false} assume 0 == ~E_1~0;~E_1~0 := 1; {3156#false} is VALID [2022-02-21 04:24:11,841 INFO L290 TraceCheckUtils]: 20: Hoare triple {3156#false} assume !(0 == ~E_2~0); {3156#false} is VALID [2022-02-21 04:24:11,841 INFO L290 TraceCheckUtils]: 21: Hoare triple {3156#false} assume !(0 == ~E_3~0); {3156#false} is VALID [2022-02-21 04:24:11,841 INFO L290 TraceCheckUtils]: 22: Hoare triple {3156#false} assume !(0 == ~E_4~0); {3156#false} is VALID [2022-02-21 04:24:11,841 INFO L290 TraceCheckUtils]: 23: Hoare triple {3156#false} assume !(0 == ~E_5~0); {3156#false} is VALID [2022-02-21 04:24:11,841 INFO L290 TraceCheckUtils]: 24: Hoare triple {3156#false} assume !(0 == ~E_6~0); {3156#false} is VALID [2022-02-21 04:24:11,841 INFO L290 TraceCheckUtils]: 25: Hoare triple {3156#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3156#false} is VALID [2022-02-21 04:24:11,841 INFO L290 TraceCheckUtils]: 26: Hoare triple {3156#false} assume 1 == ~m_pc~0; {3156#false} is VALID [2022-02-21 04:24:11,842 INFO L290 TraceCheckUtils]: 27: Hoare triple {3156#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {3156#false} is VALID [2022-02-21 04:24:11,842 INFO L290 TraceCheckUtils]: 28: Hoare triple {3156#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3156#false} is VALID [2022-02-21 04:24:11,842 INFO L290 TraceCheckUtils]: 29: Hoare triple {3156#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {3156#false} is VALID [2022-02-21 04:24:11,842 INFO L290 TraceCheckUtils]: 30: Hoare triple {3156#false} assume !(0 != activate_threads_~tmp~1#1); {3156#false} is VALID [2022-02-21 04:24:11,842 INFO L290 TraceCheckUtils]: 31: Hoare triple {3156#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3156#false} is VALID [2022-02-21 04:24:11,842 INFO L290 TraceCheckUtils]: 32: Hoare triple {3156#false} assume !(1 == ~t1_pc~0); {3156#false} is VALID [2022-02-21 04:24:11,842 INFO L290 TraceCheckUtils]: 33: Hoare triple {3156#false} is_transmit1_triggered_~__retres1~1#1 := 0; {3156#false} is VALID [2022-02-21 04:24:11,843 INFO L290 TraceCheckUtils]: 34: Hoare triple {3156#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3156#false} is VALID [2022-02-21 04:24:11,843 INFO L290 TraceCheckUtils]: 35: Hoare triple {3156#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {3156#false} is VALID [2022-02-21 04:24:11,843 INFO L290 TraceCheckUtils]: 36: Hoare triple {3156#false} assume !(0 != activate_threads_~tmp___0~0#1); {3156#false} is VALID [2022-02-21 04:24:11,847 INFO L290 TraceCheckUtils]: 37: Hoare triple {3156#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3156#false} is VALID [2022-02-21 04:24:11,847 INFO L290 TraceCheckUtils]: 38: Hoare triple {3156#false} assume 1 == ~t2_pc~0; {3156#false} is VALID [2022-02-21 04:24:11,847 INFO L290 TraceCheckUtils]: 39: Hoare triple {3156#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {3156#false} is VALID [2022-02-21 04:24:11,847 INFO L290 TraceCheckUtils]: 40: Hoare triple {3156#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3156#false} is VALID [2022-02-21 04:24:11,848 INFO L290 TraceCheckUtils]: 41: Hoare triple {3156#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {3156#false} is VALID [2022-02-21 04:24:11,848 INFO L290 TraceCheckUtils]: 42: Hoare triple {3156#false} assume !(0 != activate_threads_~tmp___1~0#1); {3156#false} is VALID [2022-02-21 04:24:11,848 INFO L290 TraceCheckUtils]: 43: Hoare triple {3156#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {3156#false} is VALID [2022-02-21 04:24:11,848 INFO L290 TraceCheckUtils]: 44: Hoare triple {3156#false} assume !(1 == ~t3_pc~0); {3156#false} is VALID [2022-02-21 04:24:11,848 INFO L290 TraceCheckUtils]: 45: Hoare triple {3156#false} is_transmit3_triggered_~__retres1~3#1 := 0; {3156#false} is VALID [2022-02-21 04:24:11,848 INFO L290 TraceCheckUtils]: 46: Hoare triple {3156#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {3156#false} is VALID [2022-02-21 04:24:11,848 INFO L290 TraceCheckUtils]: 47: Hoare triple {3156#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {3156#false} is VALID [2022-02-21 04:24:11,849 INFO L290 TraceCheckUtils]: 48: Hoare triple {3156#false} assume !(0 != activate_threads_~tmp___2~0#1); {3156#false} is VALID [2022-02-21 04:24:11,849 INFO L290 TraceCheckUtils]: 49: Hoare triple {3156#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {3156#false} is VALID [2022-02-21 04:24:11,849 INFO L290 TraceCheckUtils]: 50: Hoare triple {3156#false} assume 1 == ~t4_pc~0; {3156#false} is VALID [2022-02-21 04:24:11,849 INFO L290 TraceCheckUtils]: 51: Hoare triple {3156#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {3156#false} is VALID [2022-02-21 04:24:11,849 INFO L290 TraceCheckUtils]: 52: Hoare triple {3156#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {3156#false} is VALID [2022-02-21 04:24:11,849 INFO L290 TraceCheckUtils]: 53: Hoare triple {3156#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {3156#false} is VALID [2022-02-21 04:24:11,849 INFO L290 TraceCheckUtils]: 54: Hoare triple {3156#false} assume !(0 != activate_threads_~tmp___3~0#1); {3156#false} is VALID [2022-02-21 04:24:11,850 INFO L290 TraceCheckUtils]: 55: Hoare triple {3156#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {3156#false} is VALID [2022-02-21 04:24:11,850 INFO L290 TraceCheckUtils]: 56: Hoare triple {3156#false} assume 1 == ~t5_pc~0; {3156#false} is VALID [2022-02-21 04:24:11,850 INFO L290 TraceCheckUtils]: 57: Hoare triple {3156#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {3156#false} is VALID [2022-02-21 04:24:11,850 INFO L290 TraceCheckUtils]: 58: Hoare triple {3156#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {3156#false} is VALID [2022-02-21 04:24:11,850 INFO L290 TraceCheckUtils]: 59: Hoare triple {3156#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {3156#false} is VALID [2022-02-21 04:24:11,850 INFO L290 TraceCheckUtils]: 60: Hoare triple {3156#false} assume !(0 != activate_threads_~tmp___4~0#1); {3156#false} is VALID [2022-02-21 04:24:11,851 INFO L290 TraceCheckUtils]: 61: Hoare triple {3156#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {3156#false} is VALID [2022-02-21 04:24:11,851 INFO L290 TraceCheckUtils]: 62: Hoare triple {3156#false} assume !(1 == ~t6_pc~0); {3156#false} is VALID [2022-02-21 04:24:11,851 INFO L290 TraceCheckUtils]: 63: Hoare triple {3156#false} is_transmit6_triggered_~__retres1~6#1 := 0; {3156#false} is VALID [2022-02-21 04:24:11,851 INFO L290 TraceCheckUtils]: 64: Hoare triple {3156#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {3156#false} is VALID [2022-02-21 04:24:11,851 INFO L290 TraceCheckUtils]: 65: Hoare triple {3156#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {3156#false} is VALID [2022-02-21 04:24:11,851 INFO L290 TraceCheckUtils]: 66: Hoare triple {3156#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {3156#false} is VALID [2022-02-21 04:24:11,851 INFO L290 TraceCheckUtils]: 67: Hoare triple {3156#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3156#false} is VALID [2022-02-21 04:24:11,852 INFO L290 TraceCheckUtils]: 68: Hoare triple {3156#false} assume !(1 == ~M_E~0); {3156#false} is VALID [2022-02-21 04:24:11,853 INFO L290 TraceCheckUtils]: 69: Hoare triple {3156#false} assume !(1 == ~T1_E~0); {3156#false} is VALID [2022-02-21 04:24:11,854 INFO L290 TraceCheckUtils]: 70: Hoare triple {3156#false} assume !(1 == ~T2_E~0); {3156#false} is VALID [2022-02-21 04:24:11,854 INFO L290 TraceCheckUtils]: 71: Hoare triple {3156#false} assume !(1 == ~T3_E~0); {3156#false} is VALID [2022-02-21 04:24:11,854 INFO L290 TraceCheckUtils]: 72: Hoare triple {3156#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {3156#false} is VALID [2022-02-21 04:24:11,858 INFO L290 TraceCheckUtils]: 73: Hoare triple {3156#false} assume !(1 == ~T5_E~0); {3156#false} is VALID [2022-02-21 04:24:11,858 INFO L290 TraceCheckUtils]: 74: Hoare triple {3156#false} assume !(1 == ~T6_E~0); {3156#false} is VALID [2022-02-21 04:24:11,859 INFO L290 TraceCheckUtils]: 75: Hoare triple {3156#false} assume !(1 == ~E_1~0); {3156#false} is VALID [2022-02-21 04:24:11,860 INFO L290 TraceCheckUtils]: 76: Hoare triple {3156#false} assume !(1 == ~E_2~0); {3156#false} is VALID [2022-02-21 04:24:11,862 INFO L290 TraceCheckUtils]: 77: Hoare triple {3156#false} assume !(1 == ~E_3~0); {3156#false} is VALID [2022-02-21 04:24:11,862 INFO L290 TraceCheckUtils]: 78: Hoare triple {3156#false} assume !(1 == ~E_4~0); {3156#false} is VALID [2022-02-21 04:24:11,865 INFO L290 TraceCheckUtils]: 79: Hoare triple {3156#false} assume !(1 == ~E_5~0); {3156#false} is VALID [2022-02-21 04:24:11,866 INFO L290 TraceCheckUtils]: 80: Hoare triple {3156#false} assume 1 == ~E_6~0;~E_6~0 := 2; {3156#false} is VALID [2022-02-21 04:24:11,866 INFO L290 TraceCheckUtils]: 81: Hoare triple {3156#false} assume { :end_inline_reset_delta_events } true; {3156#false} is VALID [2022-02-21 04:24:11,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:11,867 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:11,867 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593270078] [2022-02-21 04:24:11,867 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [593270078] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:11,867 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:11,867 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:11,867 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901185390] [2022-02-21 04:24:11,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:11,868 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:11,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:11,869 INFO L85 PathProgramCache]: Analyzing trace with hash 2030983010, now seen corresponding path program 1 times [2022-02-21 04:24:11,869 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:11,869 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010141471] [2022-02-21 04:24:11,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:11,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:11,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:11,935 INFO L290 TraceCheckUtils]: 0: Hoare triple {3158#true} assume !false; {3158#true} is VALID [2022-02-21 04:24:11,936 INFO L290 TraceCheckUtils]: 1: Hoare triple {3158#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {3158#true} is VALID [2022-02-21 04:24:11,936 INFO L290 TraceCheckUtils]: 2: Hoare triple {3158#true} assume !false; {3158#true} is VALID [2022-02-21 04:24:11,936 INFO L290 TraceCheckUtils]: 3: Hoare triple {3158#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {3158#true} is VALID [2022-02-21 04:24:11,936 INFO L290 TraceCheckUtils]: 4: Hoare triple {3158#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {3158#true} is VALID [2022-02-21 04:24:11,936 INFO L290 TraceCheckUtils]: 5: Hoare triple {3158#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {3158#true} is VALID [2022-02-21 04:24:11,936 INFO L290 TraceCheckUtils]: 6: Hoare triple {3158#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {3158#true} is VALID [2022-02-21 04:24:11,936 INFO L290 TraceCheckUtils]: 7: Hoare triple {3158#true} assume !(0 != eval_~tmp~0#1); {3158#true} is VALID [2022-02-21 04:24:11,937 INFO L290 TraceCheckUtils]: 8: Hoare triple {3158#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {3158#true} is VALID [2022-02-21 04:24:11,937 INFO L290 TraceCheckUtils]: 9: Hoare triple {3158#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {3158#true} is VALID [2022-02-21 04:24:11,937 INFO L290 TraceCheckUtils]: 10: Hoare triple {3158#true} assume 0 == ~M_E~0;~M_E~0 := 1; {3158#true} is VALID [2022-02-21 04:24:11,937 INFO L290 TraceCheckUtils]: 11: Hoare triple {3158#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {3158#true} is VALID [2022-02-21 04:24:11,937 INFO L290 TraceCheckUtils]: 12: Hoare triple {3158#true} assume !(0 == ~T2_E~0); {3158#true} is VALID [2022-02-21 04:24:11,937 INFO L290 TraceCheckUtils]: 13: Hoare triple {3158#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {3158#true} is VALID [2022-02-21 04:24:11,937 INFO L290 TraceCheckUtils]: 14: Hoare triple {3158#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {3158#true} is VALID [2022-02-21 04:24:11,937 INFO L290 TraceCheckUtils]: 15: Hoare triple {3158#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {3158#true} is VALID [2022-02-21 04:24:11,938 INFO L290 TraceCheckUtils]: 16: Hoare triple {3158#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {3158#true} is VALID [2022-02-21 04:24:11,938 INFO L290 TraceCheckUtils]: 17: Hoare triple {3158#true} assume 0 == ~E_1~0;~E_1~0 := 1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,938 INFO L290 TraceCheckUtils]: 18: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,939 INFO L290 TraceCheckUtils]: 19: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,939 INFO L290 TraceCheckUtils]: 20: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,939 INFO L290 TraceCheckUtils]: 21: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,940 INFO L290 TraceCheckUtils]: 22: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,940 INFO L290 TraceCheckUtils]: 23: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,940 INFO L290 TraceCheckUtils]: 24: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,941 INFO L290 TraceCheckUtils]: 25: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,941 INFO L290 TraceCheckUtils]: 26: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,941 INFO L290 TraceCheckUtils]: 27: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,942 INFO L290 TraceCheckUtils]: 28: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,942 INFO L290 TraceCheckUtils]: 29: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,943 INFO L290 TraceCheckUtils]: 30: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,943 INFO L290 TraceCheckUtils]: 31: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,943 INFO L290 TraceCheckUtils]: 32: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,944 INFO L290 TraceCheckUtils]: 33: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,944 INFO L290 TraceCheckUtils]: 34: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,944 INFO L290 TraceCheckUtils]: 35: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,945 INFO L290 TraceCheckUtils]: 36: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t2_pc~0); {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,945 INFO L290 TraceCheckUtils]: 37: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,945 INFO L290 TraceCheckUtils]: 38: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,946 INFO L290 TraceCheckUtils]: 39: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,946 INFO L290 TraceCheckUtils]: 40: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,946 INFO L290 TraceCheckUtils]: 41: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,947 INFO L290 TraceCheckUtils]: 42: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t3_pc~0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,947 INFO L290 TraceCheckUtils]: 43: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,947 INFO L290 TraceCheckUtils]: 44: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,948 INFO L290 TraceCheckUtils]: 45: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,948 INFO L290 TraceCheckUtils]: 46: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,948 INFO L290 TraceCheckUtils]: 47: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,949 INFO L290 TraceCheckUtils]: 48: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,949 INFO L290 TraceCheckUtils]: 49: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,949 INFO L290 TraceCheckUtils]: 50: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,950 INFO L290 TraceCheckUtils]: 51: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,950 INFO L290 TraceCheckUtils]: 52: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,950 INFO L290 TraceCheckUtils]: 53: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,950 INFO L290 TraceCheckUtils]: 54: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t5_pc~0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,952 INFO L290 TraceCheckUtils]: 55: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,952 INFO L290 TraceCheckUtils]: 56: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,952 INFO L290 TraceCheckUtils]: 57: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,953 INFO L290 TraceCheckUtils]: 58: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,953 INFO L290 TraceCheckUtils]: 59: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,953 INFO L290 TraceCheckUtils]: 60: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t6_pc~0); {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,953 INFO L290 TraceCheckUtils]: 61: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,954 INFO L290 TraceCheckUtils]: 62: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,954 INFO L290 TraceCheckUtils]: 63: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,954 INFO L290 TraceCheckUtils]: 64: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,955 INFO L290 TraceCheckUtils]: 65: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,955 INFO L290 TraceCheckUtils]: 66: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,955 INFO L290 TraceCheckUtils]: 67: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,956 INFO L290 TraceCheckUtils]: 68: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,956 INFO L290 TraceCheckUtils]: 69: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,956 INFO L290 TraceCheckUtils]: 70: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,957 INFO L290 TraceCheckUtils]: 71: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,957 INFO L290 TraceCheckUtils]: 72: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {3160#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:11,957 INFO L290 TraceCheckUtils]: 73: Hoare triple {3160#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {3159#false} is VALID [2022-02-21 04:24:11,957 INFO L290 TraceCheckUtils]: 74: Hoare triple {3159#false} assume 1 == ~E_2~0;~E_2~0 := 2; {3159#false} is VALID [2022-02-21 04:24:11,958 INFO L290 TraceCheckUtils]: 75: Hoare triple {3159#false} assume 1 == ~E_3~0;~E_3~0 := 2; {3159#false} is VALID [2022-02-21 04:24:11,958 INFO L290 TraceCheckUtils]: 76: Hoare triple {3159#false} assume 1 == ~E_4~0;~E_4~0 := 2; {3159#false} is VALID [2022-02-21 04:24:11,958 INFO L290 TraceCheckUtils]: 77: Hoare triple {3159#false} assume 1 == ~E_5~0;~E_5~0 := 2; {3159#false} is VALID [2022-02-21 04:24:11,958 INFO L290 TraceCheckUtils]: 78: Hoare triple {3159#false} assume 1 == ~E_6~0;~E_6~0 := 2; {3159#false} is VALID [2022-02-21 04:24:11,958 INFO L290 TraceCheckUtils]: 79: Hoare triple {3159#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {3159#false} is VALID [2022-02-21 04:24:11,958 INFO L290 TraceCheckUtils]: 80: Hoare triple {3159#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {3159#false} is VALID [2022-02-21 04:24:11,958 INFO L290 TraceCheckUtils]: 81: Hoare triple {3159#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {3159#false} is VALID [2022-02-21 04:24:11,958 INFO L290 TraceCheckUtils]: 82: Hoare triple {3159#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {3159#false} is VALID [2022-02-21 04:24:11,958 INFO L290 TraceCheckUtils]: 83: Hoare triple {3159#false} assume !(0 == start_simulation_~tmp~3#1); {3159#false} is VALID [2022-02-21 04:24:11,959 INFO L290 TraceCheckUtils]: 84: Hoare triple {3159#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {3159#false} is VALID [2022-02-21 04:24:11,959 INFO L290 TraceCheckUtils]: 85: Hoare triple {3159#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {3159#false} is VALID [2022-02-21 04:24:11,959 INFO L290 TraceCheckUtils]: 86: Hoare triple {3159#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {3159#false} is VALID [2022-02-21 04:24:11,959 INFO L290 TraceCheckUtils]: 87: Hoare triple {3159#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {3159#false} is VALID [2022-02-21 04:24:11,959 INFO L290 TraceCheckUtils]: 88: Hoare triple {3159#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {3159#false} is VALID [2022-02-21 04:24:11,959 INFO L290 TraceCheckUtils]: 89: Hoare triple {3159#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {3159#false} is VALID [2022-02-21 04:24:11,959 INFO L290 TraceCheckUtils]: 90: Hoare triple {3159#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {3159#false} is VALID [2022-02-21 04:24:11,959 INFO L290 TraceCheckUtils]: 91: Hoare triple {3159#false} assume !(0 != start_simulation_~tmp___0~1#1); {3159#false} is VALID [2022-02-21 04:24:11,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:11,960 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:11,960 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1010141471] [2022-02-21 04:24:11,960 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1010141471] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:11,961 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:11,961 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:11,961 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775407873] [2022-02-21 04:24:11,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:11,961 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:11,961 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:11,962 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:11,962 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:11,962 INFO L87 Difference]: Start difference. First operand 626 states and 937 transitions. cyclomatic complexity: 312 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:12,407 INFO L93 Difference]: Finished difference Result 626 states and 936 transitions. [2022-02-21 04:24:12,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:12,407 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,456 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:12,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 936 transitions. [2022-02-21 04:24:12,470 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:12,483 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 936 transitions. [2022-02-21 04:24:12,483 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-02-21 04:24:12,483 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-02-21 04:24:12,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 936 transitions. [2022-02-21 04:24:12,484 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:12,484 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 936 transitions. [2022-02-21 04:24:12,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 936 transitions. [2022-02-21 04:24:12,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-02-21 04:24:12,494 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:12,495 INFO L82 GeneralOperation]: Start isEquivalent. First operand 626 states and 936 transitions. Second operand has 626 states, 626 states have (on average 1.4952076677316295) internal successors, (936), 625 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,496 INFO L74 IsIncluded]: Start isIncluded. First operand 626 states and 936 transitions. Second operand has 626 states, 626 states have (on average 1.4952076677316295) internal successors, (936), 625 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,497 INFO L87 Difference]: Start difference. First operand 626 states and 936 transitions. Second operand has 626 states, 626 states have (on average 1.4952076677316295) internal successors, (936), 625 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:12,509 INFO L93 Difference]: Finished difference Result 626 states and 936 transitions. [2022-02-21 04:24:12,510 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 936 transitions. [2022-02-21 04:24:12,510 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:12,510 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:12,512 INFO L74 IsIncluded]: Start isIncluded. First operand has 626 states, 626 states have (on average 1.4952076677316295) internal successors, (936), 625 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 936 transitions. [2022-02-21 04:24:12,513 INFO L87 Difference]: Start difference. First operand has 626 states, 626 states have (on average 1.4952076677316295) internal successors, (936), 625 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 936 transitions. [2022-02-21 04:24:12,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:12,525 INFO L93 Difference]: Finished difference Result 626 states and 936 transitions. [2022-02-21 04:24:12,525 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 936 transitions. [2022-02-21 04:24:12,526 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:12,526 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:12,526 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:12,526 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:12,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4952076677316295) internal successors, (936), 625 states have internal predecessors, (936), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:12,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 936 transitions. [2022-02-21 04:24:12,539 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 936 transitions. [2022-02-21 04:24:12,539 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 936 transitions. [2022-02-21 04:24:12,539 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:12,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 936 transitions. [2022-02-21 04:24:12,541 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:12,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:12,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:12,542 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:12,542 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:12,543 INFO L791 eck$LassoCheckResult]: Stem: 4412#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 4395#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4347#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3791#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3787#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 3788#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4302#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4406#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3881#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3882#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4036#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3900#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3901#L670 assume !(0 == ~M_E~0); 4271#L670-2 assume !(0 == ~T1_E~0); 4219#L675-1 assume !(0 == ~T2_E~0); 4220#L680-1 assume !(0 == ~T3_E~0); 4301#L685-1 assume !(0 == ~T4_E~0); 4274#L690-1 assume !(0 == ~T5_E~0); 4275#L695-1 assume !(0 == ~T6_E~0); 4333#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 4325#L705-1 assume !(0 == ~E_2~0); 4326#L710-1 assume !(0 == ~E_3~0); 4217#L715-1 assume !(0 == ~E_4~0); 4140#L720-1 assume !(0 == ~E_5~0); 4141#L725-1 assume !(0 == ~E_6~0); 4196#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4243#L320 assume 1 == ~m_pc~0; 4184#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4078#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4079#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4037#L825 assume !(0 != activate_threads_~tmp~1#1); 4038#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4043#L339 assume !(1 == ~t1_pc~0); 4044#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4021#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4022#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3903#L833 assume !(0 != activate_threads_~tmp___0~0#1); 3904#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3812#L358 assume 1 == ~t2_pc~0; 3813#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4321#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4272#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4200#L841 assume !(0 != activate_threads_~tmp___1~0#1); 4032#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4033#L377 assume !(1 == ~t3_pc~0); 4287#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4288#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4283#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4041#L849 assume !(0 != activate_threads_~tmp___2~0#1); 4042#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3987#L396 assume 1 == ~t4_pc~0; 3988#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3815#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3816#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4234#L857 assume !(0 != activate_threads_~tmp___3~0#1); 3956#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3957#L415 assume 1 == ~t5_pc~0; 4023#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4066#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4244#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4351#L865 assume !(0 != activate_threads_~tmp___4~0#1); 3858#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3859#L434 assume !(1 == ~t6_pc~0); 4173#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4174#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4313#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4314#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4054#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4055#L743 assume !(1 == ~M_E~0); 3948#L743-2 assume !(1 == ~T1_E~0); 3949#L748-1 assume !(1 == ~T2_E~0); 4237#L753-1 assume !(1 == ~T3_E~0); 4238#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4337#L763-1 assume !(1 == ~T5_E~0); 4369#L768-1 assume !(1 == ~T6_E~0); 4047#L773-1 assume !(1 == ~E_1~0); 4048#L778-1 assume !(1 == ~E_2~0); 4029#L783-1 assume !(1 == ~E_3~0); 4030#L788-1 assume !(1 == ~E_4~0); 4299#L793-1 assume !(1 == ~E_5~0); 4264#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3920#L803-1 assume { :end_inline_reset_delta_events } true; 3921#L1024-2 [2022-02-21 04:24:12,543 INFO L793 eck$LassoCheckResult]: Loop: 3921#L1024-2 assume !false; 4206#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4261#L645 assume !false; 4138#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4139#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3866#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4343#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4376#L556 assume !(0 != eval_~tmp~0#1); 4410#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4320#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3912#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3913#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4073#L675-3 assume !(0 == ~T2_E~0); 4074#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4296#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4297#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4407#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4305#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4306#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3969#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3970#L715-3 assume !(0 == ~E_4~0); 4201#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4202#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4276#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4049#L320-21 assume 1 == ~m_pc~0; 4050#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4199#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4125#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4126#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4360#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3982#L339-21 assume 1 == ~t1_pc~0; 3984#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4086#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3958#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3840#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3841#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3940#L358-21 assume !(1 == ~t2_pc~0); 3994#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 3922#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3923#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4205#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3959#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3960#L377-21 assume 1 == ~t3_pc~0; 4372#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4232#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4233#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4252#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4097#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4098#L396-21 assume 1 == ~t4_pc~0; 4265#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4124#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4095#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3822#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 3823#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4075#L415-21 assume !(1 == ~t5_pc~0); 4052#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4053#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3944#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3945#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4145#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4146#L434-21 assume !(1 == ~t6_pc~0); 3847#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 3848#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4349#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4069#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4070#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4064#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4065#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4385#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4227#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4165#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4088#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4089#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4373#L773-3 assume !(1 == ~E_1~0); 4007#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4008#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4230#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4397#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4398#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4270#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3998#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3894#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4158#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4159#L1043 assume !(0 == start_simulation_~tmp~3#1); 4352#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4228#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4016#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4198#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4186#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3908#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3909#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4056#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 3921#L1024-2 [2022-02-21 04:24:12,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:12,543 INFO L85 PathProgramCache]: Analyzing trace with hash 227806621, now seen corresponding path program 1 times [2022-02-21 04:24:12,544 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:12,544 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1131551520] [2022-02-21 04:24:12,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:12,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:12,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:12,570 INFO L290 TraceCheckUtils]: 0: Hoare triple {5668#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {5668#true} is VALID [2022-02-21 04:24:12,571 INFO L290 TraceCheckUtils]: 1: Hoare triple {5668#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {5670#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,571 INFO L290 TraceCheckUtils]: 2: Hoare triple {5670#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {5670#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,571 INFO L290 TraceCheckUtils]: 3: Hoare triple {5670#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {5670#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,572 INFO L290 TraceCheckUtils]: 4: Hoare triple {5670#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {5670#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,572 INFO L290 TraceCheckUtils]: 5: Hoare triple {5670#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {5670#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,572 INFO L290 TraceCheckUtils]: 6: Hoare triple {5670#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {5670#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:12,572 INFO L290 TraceCheckUtils]: 7: Hoare triple {5670#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {5669#false} is VALID [2022-02-21 04:24:12,573 INFO L290 TraceCheckUtils]: 8: Hoare triple {5669#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {5669#false} is VALID [2022-02-21 04:24:12,573 INFO L290 TraceCheckUtils]: 9: Hoare triple {5669#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {5669#false} is VALID [2022-02-21 04:24:12,573 INFO L290 TraceCheckUtils]: 10: Hoare triple {5669#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {5669#false} is VALID [2022-02-21 04:24:12,573 INFO L290 TraceCheckUtils]: 11: Hoare triple {5669#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {5669#false} is VALID [2022-02-21 04:24:12,573 INFO L290 TraceCheckUtils]: 12: Hoare triple {5669#false} assume !(0 == ~M_E~0); {5669#false} is VALID [2022-02-21 04:24:12,573 INFO L290 TraceCheckUtils]: 13: Hoare triple {5669#false} assume !(0 == ~T1_E~0); {5669#false} is VALID [2022-02-21 04:24:12,573 INFO L290 TraceCheckUtils]: 14: Hoare triple {5669#false} assume !(0 == ~T2_E~0); {5669#false} is VALID [2022-02-21 04:24:12,573 INFO L290 TraceCheckUtils]: 15: Hoare triple {5669#false} assume !(0 == ~T3_E~0); {5669#false} is VALID [2022-02-21 04:24:12,574 INFO L290 TraceCheckUtils]: 16: Hoare triple {5669#false} assume !(0 == ~T4_E~0); {5669#false} is VALID [2022-02-21 04:24:12,574 INFO L290 TraceCheckUtils]: 17: Hoare triple {5669#false} assume !(0 == ~T5_E~0); {5669#false} is VALID [2022-02-21 04:24:12,574 INFO L290 TraceCheckUtils]: 18: Hoare triple {5669#false} assume !(0 == ~T6_E~0); {5669#false} is VALID [2022-02-21 04:24:12,574 INFO L290 TraceCheckUtils]: 19: Hoare triple {5669#false} assume 0 == ~E_1~0;~E_1~0 := 1; {5669#false} is VALID [2022-02-21 04:24:12,574 INFO L290 TraceCheckUtils]: 20: Hoare triple {5669#false} assume !(0 == ~E_2~0); {5669#false} is VALID [2022-02-21 04:24:12,574 INFO L290 TraceCheckUtils]: 21: Hoare triple {5669#false} assume !(0 == ~E_3~0); {5669#false} is VALID [2022-02-21 04:24:12,574 INFO L290 TraceCheckUtils]: 22: Hoare triple {5669#false} assume !(0 == ~E_4~0); {5669#false} is VALID [2022-02-21 04:24:12,574 INFO L290 TraceCheckUtils]: 23: Hoare triple {5669#false} assume !(0 == ~E_5~0); {5669#false} is VALID [2022-02-21 04:24:12,574 INFO L290 TraceCheckUtils]: 24: Hoare triple {5669#false} assume !(0 == ~E_6~0); {5669#false} is VALID [2022-02-21 04:24:12,575 INFO L290 TraceCheckUtils]: 25: Hoare triple {5669#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5669#false} is VALID [2022-02-21 04:24:12,575 INFO L290 TraceCheckUtils]: 26: Hoare triple {5669#false} assume 1 == ~m_pc~0; {5669#false} is VALID [2022-02-21 04:24:12,575 INFO L290 TraceCheckUtils]: 27: Hoare triple {5669#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {5669#false} is VALID [2022-02-21 04:24:12,575 INFO L290 TraceCheckUtils]: 28: Hoare triple {5669#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5669#false} is VALID [2022-02-21 04:24:12,575 INFO L290 TraceCheckUtils]: 29: Hoare triple {5669#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {5669#false} is VALID [2022-02-21 04:24:12,575 INFO L290 TraceCheckUtils]: 30: Hoare triple {5669#false} assume !(0 != activate_threads_~tmp~1#1); {5669#false} is VALID [2022-02-21 04:24:12,575 INFO L290 TraceCheckUtils]: 31: Hoare triple {5669#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5669#false} is VALID [2022-02-21 04:24:12,575 INFO L290 TraceCheckUtils]: 32: Hoare triple {5669#false} assume !(1 == ~t1_pc~0); {5669#false} is VALID [2022-02-21 04:24:12,576 INFO L290 TraceCheckUtils]: 33: Hoare triple {5669#false} is_transmit1_triggered_~__retres1~1#1 := 0; {5669#false} is VALID [2022-02-21 04:24:12,576 INFO L290 TraceCheckUtils]: 34: Hoare triple {5669#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5669#false} is VALID [2022-02-21 04:24:12,576 INFO L290 TraceCheckUtils]: 35: Hoare triple {5669#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {5669#false} is VALID [2022-02-21 04:24:12,576 INFO L290 TraceCheckUtils]: 36: Hoare triple {5669#false} assume !(0 != activate_threads_~tmp___0~0#1); {5669#false} is VALID [2022-02-21 04:24:12,576 INFO L290 TraceCheckUtils]: 37: Hoare triple {5669#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5669#false} is VALID [2022-02-21 04:24:12,576 INFO L290 TraceCheckUtils]: 38: Hoare triple {5669#false} assume 1 == ~t2_pc~0; {5669#false} is VALID [2022-02-21 04:24:12,576 INFO L290 TraceCheckUtils]: 39: Hoare triple {5669#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {5669#false} is VALID [2022-02-21 04:24:12,576 INFO L290 TraceCheckUtils]: 40: Hoare triple {5669#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5669#false} is VALID [2022-02-21 04:24:12,577 INFO L290 TraceCheckUtils]: 41: Hoare triple {5669#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {5669#false} is VALID [2022-02-21 04:24:12,577 INFO L290 TraceCheckUtils]: 42: Hoare triple {5669#false} assume !(0 != activate_threads_~tmp___1~0#1); {5669#false} is VALID [2022-02-21 04:24:12,577 INFO L290 TraceCheckUtils]: 43: Hoare triple {5669#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5669#false} is VALID [2022-02-21 04:24:12,577 INFO L290 TraceCheckUtils]: 44: Hoare triple {5669#false} assume !(1 == ~t3_pc~0); {5669#false} is VALID [2022-02-21 04:24:12,577 INFO L290 TraceCheckUtils]: 45: Hoare triple {5669#false} is_transmit3_triggered_~__retres1~3#1 := 0; {5669#false} is VALID [2022-02-21 04:24:12,577 INFO L290 TraceCheckUtils]: 46: Hoare triple {5669#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5669#false} is VALID [2022-02-21 04:24:12,577 INFO L290 TraceCheckUtils]: 47: Hoare triple {5669#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {5669#false} is VALID [2022-02-21 04:24:12,577 INFO L290 TraceCheckUtils]: 48: Hoare triple {5669#false} assume !(0 != activate_threads_~tmp___2~0#1); {5669#false} is VALID [2022-02-21 04:24:12,577 INFO L290 TraceCheckUtils]: 49: Hoare triple {5669#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5669#false} is VALID [2022-02-21 04:24:12,578 INFO L290 TraceCheckUtils]: 50: Hoare triple {5669#false} assume 1 == ~t4_pc~0; {5669#false} is VALID [2022-02-21 04:24:12,578 INFO L290 TraceCheckUtils]: 51: Hoare triple {5669#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {5669#false} is VALID [2022-02-21 04:24:12,578 INFO L290 TraceCheckUtils]: 52: Hoare triple {5669#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5669#false} is VALID [2022-02-21 04:24:12,578 INFO L290 TraceCheckUtils]: 53: Hoare triple {5669#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {5669#false} is VALID [2022-02-21 04:24:12,578 INFO L290 TraceCheckUtils]: 54: Hoare triple {5669#false} assume !(0 != activate_threads_~tmp___3~0#1); {5669#false} is VALID [2022-02-21 04:24:12,578 INFO L290 TraceCheckUtils]: 55: Hoare triple {5669#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {5669#false} is VALID [2022-02-21 04:24:12,578 INFO L290 TraceCheckUtils]: 56: Hoare triple {5669#false} assume 1 == ~t5_pc~0; {5669#false} is VALID [2022-02-21 04:24:12,578 INFO L290 TraceCheckUtils]: 57: Hoare triple {5669#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {5669#false} is VALID [2022-02-21 04:24:12,579 INFO L290 TraceCheckUtils]: 58: Hoare triple {5669#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {5669#false} is VALID [2022-02-21 04:24:12,579 INFO L290 TraceCheckUtils]: 59: Hoare triple {5669#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {5669#false} is VALID [2022-02-21 04:24:12,579 INFO L290 TraceCheckUtils]: 60: Hoare triple {5669#false} assume !(0 != activate_threads_~tmp___4~0#1); {5669#false} is VALID [2022-02-21 04:24:12,579 INFO L290 TraceCheckUtils]: 61: Hoare triple {5669#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {5669#false} is VALID [2022-02-21 04:24:12,579 INFO L290 TraceCheckUtils]: 62: Hoare triple {5669#false} assume !(1 == ~t6_pc~0); {5669#false} is VALID [2022-02-21 04:24:12,579 INFO L290 TraceCheckUtils]: 63: Hoare triple {5669#false} is_transmit6_triggered_~__retres1~6#1 := 0; {5669#false} is VALID [2022-02-21 04:24:12,579 INFO L290 TraceCheckUtils]: 64: Hoare triple {5669#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {5669#false} is VALID [2022-02-21 04:24:12,579 INFO L290 TraceCheckUtils]: 65: Hoare triple {5669#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {5669#false} is VALID [2022-02-21 04:24:12,580 INFO L290 TraceCheckUtils]: 66: Hoare triple {5669#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {5669#false} is VALID [2022-02-21 04:24:12,580 INFO L290 TraceCheckUtils]: 67: Hoare triple {5669#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5669#false} is VALID [2022-02-21 04:24:12,580 INFO L290 TraceCheckUtils]: 68: Hoare triple {5669#false} assume !(1 == ~M_E~0); {5669#false} is VALID [2022-02-21 04:24:12,580 INFO L290 TraceCheckUtils]: 69: Hoare triple {5669#false} assume !(1 == ~T1_E~0); {5669#false} is VALID [2022-02-21 04:24:12,580 INFO L290 TraceCheckUtils]: 70: Hoare triple {5669#false} assume !(1 == ~T2_E~0); {5669#false} is VALID [2022-02-21 04:24:12,580 INFO L290 TraceCheckUtils]: 71: Hoare triple {5669#false} assume !(1 == ~T3_E~0); {5669#false} is VALID [2022-02-21 04:24:12,580 INFO L290 TraceCheckUtils]: 72: Hoare triple {5669#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {5669#false} is VALID [2022-02-21 04:24:12,580 INFO L290 TraceCheckUtils]: 73: Hoare triple {5669#false} assume !(1 == ~T5_E~0); {5669#false} is VALID [2022-02-21 04:24:12,581 INFO L290 TraceCheckUtils]: 74: Hoare triple {5669#false} assume !(1 == ~T6_E~0); {5669#false} is VALID [2022-02-21 04:24:12,581 INFO L290 TraceCheckUtils]: 75: Hoare triple {5669#false} assume !(1 == ~E_1~0); {5669#false} is VALID [2022-02-21 04:24:12,581 INFO L290 TraceCheckUtils]: 76: Hoare triple {5669#false} assume !(1 == ~E_2~0); {5669#false} is VALID [2022-02-21 04:24:12,581 INFO L290 TraceCheckUtils]: 77: Hoare triple {5669#false} assume !(1 == ~E_3~0); {5669#false} is VALID [2022-02-21 04:24:12,581 INFO L290 TraceCheckUtils]: 78: Hoare triple {5669#false} assume !(1 == ~E_4~0); {5669#false} is VALID [2022-02-21 04:24:12,581 INFO L290 TraceCheckUtils]: 79: Hoare triple {5669#false} assume !(1 == ~E_5~0); {5669#false} is VALID [2022-02-21 04:24:12,581 INFO L290 TraceCheckUtils]: 80: Hoare triple {5669#false} assume 1 == ~E_6~0;~E_6~0 := 2; {5669#false} is VALID [2022-02-21 04:24:12,581 INFO L290 TraceCheckUtils]: 81: Hoare triple {5669#false} assume { :end_inline_reset_delta_events } true; {5669#false} is VALID [2022-02-21 04:24:12,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:12,582 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:12,582 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1131551520] [2022-02-21 04:24:12,582 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1131551520] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:12,582 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:12,582 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:12,583 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [472779285] [2022-02-21 04:24:12,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:12,583 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:12,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:12,583 INFO L85 PathProgramCache]: Analyzing trace with hash 734577762, now seen corresponding path program 1 times [2022-02-21 04:24:12,584 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:12,584 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157815208] [2022-02-21 04:24:12,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:12,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:12,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:12,622 INFO L290 TraceCheckUtils]: 0: Hoare triple {5671#true} assume !false; {5671#true} is VALID [2022-02-21 04:24:12,622 INFO L290 TraceCheckUtils]: 1: Hoare triple {5671#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {5671#true} is VALID [2022-02-21 04:24:12,622 INFO L290 TraceCheckUtils]: 2: Hoare triple {5671#true} assume !false; {5671#true} is VALID [2022-02-21 04:24:12,622 INFO L290 TraceCheckUtils]: 3: Hoare triple {5671#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {5671#true} is VALID [2022-02-21 04:24:12,622 INFO L290 TraceCheckUtils]: 4: Hoare triple {5671#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {5671#true} is VALID [2022-02-21 04:24:12,623 INFO L290 TraceCheckUtils]: 5: Hoare triple {5671#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {5671#true} is VALID [2022-02-21 04:24:12,623 INFO L290 TraceCheckUtils]: 6: Hoare triple {5671#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {5671#true} is VALID [2022-02-21 04:24:12,623 INFO L290 TraceCheckUtils]: 7: Hoare triple {5671#true} assume !(0 != eval_~tmp~0#1); {5671#true} is VALID [2022-02-21 04:24:12,623 INFO L290 TraceCheckUtils]: 8: Hoare triple {5671#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {5671#true} is VALID [2022-02-21 04:24:12,623 INFO L290 TraceCheckUtils]: 9: Hoare triple {5671#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {5671#true} is VALID [2022-02-21 04:24:12,623 INFO L290 TraceCheckUtils]: 10: Hoare triple {5671#true} assume 0 == ~M_E~0;~M_E~0 := 1; {5671#true} is VALID [2022-02-21 04:24:12,623 INFO L290 TraceCheckUtils]: 11: Hoare triple {5671#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {5671#true} is VALID [2022-02-21 04:24:12,623 INFO L290 TraceCheckUtils]: 12: Hoare triple {5671#true} assume !(0 == ~T2_E~0); {5671#true} is VALID [2022-02-21 04:24:12,624 INFO L290 TraceCheckUtils]: 13: Hoare triple {5671#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {5671#true} is VALID [2022-02-21 04:24:12,624 INFO L290 TraceCheckUtils]: 14: Hoare triple {5671#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {5671#true} is VALID [2022-02-21 04:24:12,624 INFO L290 TraceCheckUtils]: 15: Hoare triple {5671#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {5671#true} is VALID [2022-02-21 04:24:12,624 INFO L290 TraceCheckUtils]: 16: Hoare triple {5671#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {5671#true} is VALID [2022-02-21 04:24:12,624 INFO L290 TraceCheckUtils]: 17: Hoare triple {5671#true} assume 0 == ~E_1~0;~E_1~0 := 1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,625 INFO L290 TraceCheckUtils]: 18: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,625 INFO L290 TraceCheckUtils]: 19: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,625 INFO L290 TraceCheckUtils]: 20: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,626 INFO L290 TraceCheckUtils]: 21: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,626 INFO L290 TraceCheckUtils]: 22: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,626 INFO L290 TraceCheckUtils]: 23: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,626 INFO L290 TraceCheckUtils]: 24: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,627 INFO L290 TraceCheckUtils]: 25: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,627 INFO L290 TraceCheckUtils]: 26: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,627 INFO L290 TraceCheckUtils]: 27: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,628 INFO L290 TraceCheckUtils]: 28: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,628 INFO L290 TraceCheckUtils]: 29: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,628 INFO L290 TraceCheckUtils]: 30: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t1_pc~0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,629 INFO L290 TraceCheckUtils]: 31: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,629 INFO L290 TraceCheckUtils]: 32: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,629 INFO L290 TraceCheckUtils]: 33: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,630 INFO L290 TraceCheckUtils]: 34: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,630 INFO L290 TraceCheckUtils]: 35: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,630 INFO L290 TraceCheckUtils]: 36: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t2_pc~0); {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,631 INFO L290 TraceCheckUtils]: 37: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,631 INFO L290 TraceCheckUtils]: 38: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,631 INFO L290 TraceCheckUtils]: 39: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,632 INFO L290 TraceCheckUtils]: 40: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,632 INFO L290 TraceCheckUtils]: 41: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,632 INFO L290 TraceCheckUtils]: 42: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t3_pc~0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,632 INFO L290 TraceCheckUtils]: 43: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,633 INFO L290 TraceCheckUtils]: 44: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,633 INFO L290 TraceCheckUtils]: 45: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,633 INFO L290 TraceCheckUtils]: 46: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,634 INFO L290 TraceCheckUtils]: 47: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,634 INFO L290 TraceCheckUtils]: 48: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,634 INFO L290 TraceCheckUtils]: 49: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,635 INFO L290 TraceCheckUtils]: 50: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,635 INFO L290 TraceCheckUtils]: 51: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,635 INFO L290 TraceCheckUtils]: 52: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,636 INFO L290 TraceCheckUtils]: 53: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,636 INFO L290 TraceCheckUtils]: 54: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t5_pc~0); {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,636 INFO L290 TraceCheckUtils]: 55: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,636 INFO L290 TraceCheckUtils]: 56: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,637 INFO L290 TraceCheckUtils]: 57: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,637 INFO L290 TraceCheckUtils]: 58: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,637 INFO L290 TraceCheckUtils]: 59: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,638 INFO L290 TraceCheckUtils]: 60: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t6_pc~0); {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,638 INFO L290 TraceCheckUtils]: 61: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,638 INFO L290 TraceCheckUtils]: 62: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,639 INFO L290 TraceCheckUtils]: 63: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,639 INFO L290 TraceCheckUtils]: 64: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,639 INFO L290 TraceCheckUtils]: 65: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,640 INFO L290 TraceCheckUtils]: 66: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,640 INFO L290 TraceCheckUtils]: 67: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,640 INFO L290 TraceCheckUtils]: 68: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,641 INFO L290 TraceCheckUtils]: 69: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,641 INFO L290 TraceCheckUtils]: 70: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,641 INFO L290 TraceCheckUtils]: 71: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,642 INFO L290 TraceCheckUtils]: 72: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {5673#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:12,642 INFO L290 TraceCheckUtils]: 73: Hoare triple {5673#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {5672#false} is VALID [2022-02-21 04:24:12,642 INFO L290 TraceCheckUtils]: 74: Hoare triple {5672#false} assume 1 == ~E_2~0;~E_2~0 := 2; {5672#false} is VALID [2022-02-21 04:24:12,642 INFO L290 TraceCheckUtils]: 75: Hoare triple {5672#false} assume 1 == ~E_3~0;~E_3~0 := 2; {5672#false} is VALID [2022-02-21 04:24:12,642 INFO L290 TraceCheckUtils]: 76: Hoare triple {5672#false} assume 1 == ~E_4~0;~E_4~0 := 2; {5672#false} is VALID [2022-02-21 04:24:12,642 INFO L290 TraceCheckUtils]: 77: Hoare triple {5672#false} assume 1 == ~E_5~0;~E_5~0 := 2; {5672#false} is VALID [2022-02-21 04:24:12,643 INFO L290 TraceCheckUtils]: 78: Hoare triple {5672#false} assume 1 == ~E_6~0;~E_6~0 := 2; {5672#false} is VALID [2022-02-21 04:24:12,643 INFO L290 TraceCheckUtils]: 79: Hoare triple {5672#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {5672#false} is VALID [2022-02-21 04:24:12,643 INFO L290 TraceCheckUtils]: 80: Hoare triple {5672#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {5672#false} is VALID [2022-02-21 04:24:12,643 INFO L290 TraceCheckUtils]: 81: Hoare triple {5672#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {5672#false} is VALID [2022-02-21 04:24:12,643 INFO L290 TraceCheckUtils]: 82: Hoare triple {5672#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {5672#false} is VALID [2022-02-21 04:24:12,643 INFO L290 TraceCheckUtils]: 83: Hoare triple {5672#false} assume !(0 == start_simulation_~tmp~3#1); {5672#false} is VALID [2022-02-21 04:24:12,643 INFO L290 TraceCheckUtils]: 84: Hoare triple {5672#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {5672#false} is VALID [2022-02-21 04:24:12,643 INFO L290 TraceCheckUtils]: 85: Hoare triple {5672#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {5672#false} is VALID [2022-02-21 04:24:12,643 INFO L290 TraceCheckUtils]: 86: Hoare triple {5672#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {5672#false} is VALID [2022-02-21 04:24:12,644 INFO L290 TraceCheckUtils]: 87: Hoare triple {5672#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {5672#false} is VALID [2022-02-21 04:24:12,644 INFO L290 TraceCheckUtils]: 88: Hoare triple {5672#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {5672#false} is VALID [2022-02-21 04:24:12,644 INFO L290 TraceCheckUtils]: 89: Hoare triple {5672#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {5672#false} is VALID [2022-02-21 04:24:12,644 INFO L290 TraceCheckUtils]: 90: Hoare triple {5672#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {5672#false} is VALID [2022-02-21 04:24:12,655 INFO L290 TraceCheckUtils]: 91: Hoare triple {5672#false} assume !(0 != start_simulation_~tmp___0~1#1); {5672#false} is VALID [2022-02-21 04:24:12,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:12,659 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:12,659 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [157815208] [2022-02-21 04:24:12,660 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [157815208] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:12,660 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:12,660 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:12,660 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1203750465] [2022-02-21 04:24:12,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:12,660 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:12,660 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:12,660 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:12,661 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:12,661 INFO L87 Difference]: Start difference. First operand 626 states and 936 transitions. cyclomatic complexity: 311 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:13,086 INFO L93 Difference]: Finished difference Result 626 states and 935 transitions. [2022-02-21 04:24:13,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:13,087 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,132 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:13,132 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 935 transitions. [2022-02-21 04:24:13,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:13,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 935 transitions. [2022-02-21 04:24:13,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-02-21 04:24:13,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-02-21 04:24:13,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 935 transitions. [2022-02-21 04:24:13,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:13,158 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 935 transitions. [2022-02-21 04:24:13,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 935 transitions. [2022-02-21 04:24:13,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-02-21 04:24:13,164 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:13,165 INFO L82 GeneralOperation]: Start isEquivalent. First operand 626 states and 935 transitions. Second operand has 626 states, 626 states have (on average 1.4936102236421724) internal successors, (935), 625 states have internal predecessors, (935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,166 INFO L74 IsIncluded]: Start isIncluded. First operand 626 states and 935 transitions. Second operand has 626 states, 626 states have (on average 1.4936102236421724) internal successors, (935), 625 states have internal predecessors, (935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,167 INFO L87 Difference]: Start difference. First operand 626 states and 935 transitions. Second operand has 626 states, 626 states have (on average 1.4936102236421724) internal successors, (935), 625 states have internal predecessors, (935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:13,178 INFO L93 Difference]: Finished difference Result 626 states and 935 transitions. [2022-02-21 04:24:13,178 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 935 transitions. [2022-02-21 04:24:13,179 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:13,179 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:13,180 INFO L74 IsIncluded]: Start isIncluded. First operand has 626 states, 626 states have (on average 1.4936102236421724) internal successors, (935), 625 states have internal predecessors, (935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 935 transitions. [2022-02-21 04:24:13,181 INFO L87 Difference]: Start difference. First operand has 626 states, 626 states have (on average 1.4936102236421724) internal successors, (935), 625 states have internal predecessors, (935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 935 transitions. [2022-02-21 04:24:13,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:13,193 INFO L93 Difference]: Finished difference Result 626 states and 935 transitions. [2022-02-21 04:24:13,193 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 935 transitions. [2022-02-21 04:24:13,193 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:13,194 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:13,194 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:13,194 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:13,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4936102236421724) internal successors, (935), 625 states have internal predecessors, (935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 935 transitions. [2022-02-21 04:24:13,206 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 935 transitions. [2022-02-21 04:24:13,206 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 935 transitions. [2022-02-21 04:24:13,206 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:13,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 935 transitions. [2022-02-21 04:24:13,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:13,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:13,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:13,209 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:13,209 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:13,210 INFO L791 eck$LassoCheckResult]: Stem: 6925#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 6908#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6860#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6304#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6300#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 6301#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6816#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6919#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6394#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6395#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6549#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6413#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6414#L670 assume !(0 == ~M_E~0); 6784#L670-2 assume !(0 == ~T1_E~0); 6732#L675-1 assume !(0 == ~T2_E~0); 6733#L680-1 assume !(0 == ~T3_E~0); 6814#L685-1 assume !(0 == ~T4_E~0); 6787#L690-1 assume !(0 == ~T5_E~0); 6788#L695-1 assume !(0 == ~T6_E~0); 6846#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6838#L705-1 assume !(0 == ~E_2~0); 6839#L710-1 assume !(0 == ~E_3~0); 6730#L715-1 assume !(0 == ~E_4~0); 6653#L720-1 assume !(0 == ~E_5~0); 6654#L725-1 assume !(0 == ~E_6~0); 6709#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6756#L320 assume 1 == ~m_pc~0; 6697#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6591#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6592#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6550#L825 assume !(0 != activate_threads_~tmp~1#1); 6551#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6556#L339 assume !(1 == ~t1_pc~0); 6557#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6534#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6535#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6416#L833 assume !(0 != activate_threads_~tmp___0~0#1); 6417#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6325#L358 assume 1 == ~t2_pc~0; 6326#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6834#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6785#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6713#L841 assume !(0 != activate_threads_~tmp___1~0#1); 6547#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6548#L377 assume !(1 == ~t3_pc~0); 6800#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6801#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6796#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6554#L849 assume !(0 != activate_threads_~tmp___2~0#1); 6555#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6500#L396 assume 1 == ~t4_pc~0; 6501#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6328#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6329#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6747#L857 assume !(0 != activate_threads_~tmp___3~0#1); 6469#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6470#L415 assume 1 == ~t5_pc~0; 6536#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6581#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6757#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6864#L865 assume !(0 != activate_threads_~tmp___4~0#1); 6371#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6372#L434 assume !(1 == ~t6_pc~0); 6686#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6687#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6826#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6827#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6567#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6568#L743 assume !(1 == ~M_E~0); 6461#L743-2 assume !(1 == ~T1_E~0); 6462#L748-1 assume !(1 == ~T2_E~0); 6750#L753-1 assume !(1 == ~T3_E~0); 6751#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6850#L763-1 assume !(1 == ~T5_E~0); 6882#L768-1 assume !(1 == ~T6_E~0); 6562#L773-1 assume !(1 == ~E_1~0); 6563#L778-1 assume !(1 == ~E_2~0); 6542#L783-1 assume !(1 == ~E_3~0); 6543#L788-1 assume !(1 == ~E_4~0); 6812#L793-1 assume !(1 == ~E_5~0); 6777#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6433#L803-1 assume { :end_inline_reset_delta_events } true; 6434#L1024-2 [2022-02-21 04:24:13,210 INFO L793 eck$LassoCheckResult]: Loop: 6434#L1024-2 assume !false; 6719#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6774#L645 assume !false; 6651#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6652#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6379#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6856#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6889#L556 assume !(0 != eval_~tmp~0#1); 6923#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6833#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6427#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6428#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6588#L675-3 assume !(0 == ~T2_E~0); 6589#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6809#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6810#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6920#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6818#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6819#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6482#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6483#L715-3 assume !(0 == ~E_4~0); 6714#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6715#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6789#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6564#L320-21 assume 1 == ~m_pc~0; 6565#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6712#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6638#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6639#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6874#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6495#L339-21 assume !(1 == ~t1_pc~0); 6496#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 6599#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6471#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6353#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6354#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6453#L358-21 assume !(1 == ~t2_pc~0); 6507#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 6435#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6436#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6718#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6472#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6473#L377-21 assume 1 == ~t3_pc~0; 6886#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6745#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6746#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6765#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6610#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6611#L396-21 assume 1 == ~t4_pc~0; 6778#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6637#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6608#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6333#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 6334#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6586#L415-21 assume !(1 == ~t5_pc~0); 6560#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 6561#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6457#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6458#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6658#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6659#L434-21 assume !(1 == ~t6_pc~0); 6358#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 6359#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6861#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6582#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6583#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6577#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6578#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6898#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6740#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6677#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6601#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6602#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6885#L773-3 assume !(1 == ~E_1~0); 6520#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6521#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6743#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6910#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6911#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6782#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6511#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6407#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6671#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6672#L1043 assume !(0 == start_simulation_~tmp~3#1); 6865#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6741#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6528#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6710#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 6699#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6421#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6422#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6569#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 6434#L1024-2 [2022-02-21 04:24:13,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:13,210 INFO L85 PathProgramCache]: Analyzing trace with hash -1506297829, now seen corresponding path program 1 times [2022-02-21 04:24:13,211 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:13,211 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987372971] [2022-02-21 04:24:13,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:13,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:13,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:13,231 INFO L290 TraceCheckUtils]: 0: Hoare triple {8181#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {8181#true} is VALID [2022-02-21 04:24:13,231 INFO L290 TraceCheckUtils]: 1: Hoare triple {8181#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {8183#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:13,231 INFO L290 TraceCheckUtils]: 2: Hoare triple {8183#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {8183#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:13,232 INFO L290 TraceCheckUtils]: 3: Hoare triple {8183#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {8183#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:13,232 INFO L290 TraceCheckUtils]: 4: Hoare triple {8183#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {8183#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:13,232 INFO L290 TraceCheckUtils]: 5: Hoare triple {8183#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {8183#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:13,232 INFO L290 TraceCheckUtils]: 6: Hoare triple {8183#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {8183#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:13,233 INFO L290 TraceCheckUtils]: 7: Hoare triple {8183#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {8183#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:13,233 INFO L290 TraceCheckUtils]: 8: Hoare triple {8183#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {8182#false} is VALID [2022-02-21 04:24:13,233 INFO L290 TraceCheckUtils]: 9: Hoare triple {8182#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {8182#false} is VALID [2022-02-21 04:24:13,233 INFO L290 TraceCheckUtils]: 10: Hoare triple {8182#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {8182#false} is VALID [2022-02-21 04:24:13,233 INFO L290 TraceCheckUtils]: 11: Hoare triple {8182#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {8182#false} is VALID [2022-02-21 04:24:13,233 INFO L290 TraceCheckUtils]: 12: Hoare triple {8182#false} assume !(0 == ~M_E~0); {8182#false} is VALID [2022-02-21 04:24:13,233 INFO L290 TraceCheckUtils]: 13: Hoare triple {8182#false} assume !(0 == ~T1_E~0); {8182#false} is VALID [2022-02-21 04:24:13,233 INFO L290 TraceCheckUtils]: 14: Hoare triple {8182#false} assume !(0 == ~T2_E~0); {8182#false} is VALID [2022-02-21 04:24:13,234 INFO L290 TraceCheckUtils]: 15: Hoare triple {8182#false} assume !(0 == ~T3_E~0); {8182#false} is VALID [2022-02-21 04:24:13,234 INFO L290 TraceCheckUtils]: 16: Hoare triple {8182#false} assume !(0 == ~T4_E~0); {8182#false} is VALID [2022-02-21 04:24:13,234 INFO L290 TraceCheckUtils]: 17: Hoare triple {8182#false} assume !(0 == ~T5_E~0); {8182#false} is VALID [2022-02-21 04:24:13,244 INFO L290 TraceCheckUtils]: 18: Hoare triple {8182#false} assume !(0 == ~T6_E~0); {8182#false} is VALID [2022-02-21 04:24:13,244 INFO L290 TraceCheckUtils]: 19: Hoare triple {8182#false} assume 0 == ~E_1~0;~E_1~0 := 1; {8182#false} is VALID [2022-02-21 04:24:13,244 INFO L290 TraceCheckUtils]: 20: Hoare triple {8182#false} assume !(0 == ~E_2~0); {8182#false} is VALID [2022-02-21 04:24:13,245 INFO L290 TraceCheckUtils]: 21: Hoare triple {8182#false} assume !(0 == ~E_3~0); {8182#false} is VALID [2022-02-21 04:24:13,245 INFO L290 TraceCheckUtils]: 22: Hoare triple {8182#false} assume !(0 == ~E_4~0); {8182#false} is VALID [2022-02-21 04:24:13,245 INFO L290 TraceCheckUtils]: 23: Hoare triple {8182#false} assume !(0 == ~E_5~0); {8182#false} is VALID [2022-02-21 04:24:13,245 INFO L290 TraceCheckUtils]: 24: Hoare triple {8182#false} assume !(0 == ~E_6~0); {8182#false} is VALID [2022-02-21 04:24:13,245 INFO L290 TraceCheckUtils]: 25: Hoare triple {8182#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8182#false} is VALID [2022-02-21 04:24:13,245 INFO L290 TraceCheckUtils]: 26: Hoare triple {8182#false} assume 1 == ~m_pc~0; {8182#false} is VALID [2022-02-21 04:24:13,245 INFO L290 TraceCheckUtils]: 27: Hoare triple {8182#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {8182#false} is VALID [2022-02-21 04:24:13,245 INFO L290 TraceCheckUtils]: 28: Hoare triple {8182#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8182#false} is VALID [2022-02-21 04:24:13,246 INFO L290 TraceCheckUtils]: 29: Hoare triple {8182#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {8182#false} is VALID [2022-02-21 04:24:13,246 INFO L290 TraceCheckUtils]: 30: Hoare triple {8182#false} assume !(0 != activate_threads_~tmp~1#1); {8182#false} is VALID [2022-02-21 04:24:13,246 INFO L290 TraceCheckUtils]: 31: Hoare triple {8182#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8182#false} is VALID [2022-02-21 04:24:13,246 INFO L290 TraceCheckUtils]: 32: Hoare triple {8182#false} assume !(1 == ~t1_pc~0); {8182#false} is VALID [2022-02-21 04:24:13,246 INFO L290 TraceCheckUtils]: 33: Hoare triple {8182#false} is_transmit1_triggered_~__retres1~1#1 := 0; {8182#false} is VALID [2022-02-21 04:24:13,246 INFO L290 TraceCheckUtils]: 34: Hoare triple {8182#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8182#false} is VALID [2022-02-21 04:24:13,246 INFO L290 TraceCheckUtils]: 35: Hoare triple {8182#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {8182#false} is VALID [2022-02-21 04:24:13,247 INFO L290 TraceCheckUtils]: 36: Hoare triple {8182#false} assume !(0 != activate_threads_~tmp___0~0#1); {8182#false} is VALID [2022-02-21 04:24:13,247 INFO L290 TraceCheckUtils]: 37: Hoare triple {8182#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8182#false} is VALID [2022-02-21 04:24:13,247 INFO L290 TraceCheckUtils]: 38: Hoare triple {8182#false} assume 1 == ~t2_pc~0; {8182#false} is VALID [2022-02-21 04:24:13,247 INFO L290 TraceCheckUtils]: 39: Hoare triple {8182#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8182#false} is VALID [2022-02-21 04:24:13,247 INFO L290 TraceCheckUtils]: 40: Hoare triple {8182#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8182#false} is VALID [2022-02-21 04:24:13,247 INFO L290 TraceCheckUtils]: 41: Hoare triple {8182#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8182#false} is VALID [2022-02-21 04:24:13,247 INFO L290 TraceCheckUtils]: 42: Hoare triple {8182#false} assume !(0 != activate_threads_~tmp___1~0#1); {8182#false} is VALID [2022-02-21 04:24:13,247 INFO L290 TraceCheckUtils]: 43: Hoare triple {8182#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8182#false} is VALID [2022-02-21 04:24:13,248 INFO L290 TraceCheckUtils]: 44: Hoare triple {8182#false} assume !(1 == ~t3_pc~0); {8182#false} is VALID [2022-02-21 04:24:13,248 INFO L290 TraceCheckUtils]: 45: Hoare triple {8182#false} is_transmit3_triggered_~__retres1~3#1 := 0; {8182#false} is VALID [2022-02-21 04:24:13,248 INFO L290 TraceCheckUtils]: 46: Hoare triple {8182#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8182#false} is VALID [2022-02-21 04:24:13,248 INFO L290 TraceCheckUtils]: 47: Hoare triple {8182#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8182#false} is VALID [2022-02-21 04:24:13,248 INFO L290 TraceCheckUtils]: 48: Hoare triple {8182#false} assume !(0 != activate_threads_~tmp___2~0#1); {8182#false} is VALID [2022-02-21 04:24:13,248 INFO L290 TraceCheckUtils]: 49: Hoare triple {8182#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8182#false} is VALID [2022-02-21 04:24:13,248 INFO L290 TraceCheckUtils]: 50: Hoare triple {8182#false} assume 1 == ~t4_pc~0; {8182#false} is VALID [2022-02-21 04:24:13,248 INFO L290 TraceCheckUtils]: 51: Hoare triple {8182#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8182#false} is VALID [2022-02-21 04:24:13,249 INFO L290 TraceCheckUtils]: 52: Hoare triple {8182#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8182#false} is VALID [2022-02-21 04:24:13,249 INFO L290 TraceCheckUtils]: 53: Hoare triple {8182#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {8182#false} is VALID [2022-02-21 04:24:13,249 INFO L290 TraceCheckUtils]: 54: Hoare triple {8182#false} assume !(0 != activate_threads_~tmp___3~0#1); {8182#false} is VALID [2022-02-21 04:24:13,249 INFO L290 TraceCheckUtils]: 55: Hoare triple {8182#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8182#false} is VALID [2022-02-21 04:24:13,249 INFO L290 TraceCheckUtils]: 56: Hoare triple {8182#false} assume 1 == ~t5_pc~0; {8182#false} is VALID [2022-02-21 04:24:13,249 INFO L290 TraceCheckUtils]: 57: Hoare triple {8182#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {8182#false} is VALID [2022-02-21 04:24:13,249 INFO L290 TraceCheckUtils]: 58: Hoare triple {8182#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8182#false} is VALID [2022-02-21 04:24:13,250 INFO L290 TraceCheckUtils]: 59: Hoare triple {8182#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {8182#false} is VALID [2022-02-21 04:24:13,250 INFO L290 TraceCheckUtils]: 60: Hoare triple {8182#false} assume !(0 != activate_threads_~tmp___4~0#1); {8182#false} is VALID [2022-02-21 04:24:13,250 INFO L290 TraceCheckUtils]: 61: Hoare triple {8182#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8182#false} is VALID [2022-02-21 04:24:13,250 INFO L290 TraceCheckUtils]: 62: Hoare triple {8182#false} assume !(1 == ~t6_pc~0); {8182#false} is VALID [2022-02-21 04:24:13,250 INFO L290 TraceCheckUtils]: 63: Hoare triple {8182#false} is_transmit6_triggered_~__retres1~6#1 := 0; {8182#false} is VALID [2022-02-21 04:24:13,250 INFO L290 TraceCheckUtils]: 64: Hoare triple {8182#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8182#false} is VALID [2022-02-21 04:24:13,250 INFO L290 TraceCheckUtils]: 65: Hoare triple {8182#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {8182#false} is VALID [2022-02-21 04:24:13,250 INFO L290 TraceCheckUtils]: 66: Hoare triple {8182#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {8182#false} is VALID [2022-02-21 04:24:13,251 INFO L290 TraceCheckUtils]: 67: Hoare triple {8182#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8182#false} is VALID [2022-02-21 04:24:13,251 INFO L290 TraceCheckUtils]: 68: Hoare triple {8182#false} assume !(1 == ~M_E~0); {8182#false} is VALID [2022-02-21 04:24:13,251 INFO L290 TraceCheckUtils]: 69: Hoare triple {8182#false} assume !(1 == ~T1_E~0); {8182#false} is VALID [2022-02-21 04:24:13,251 INFO L290 TraceCheckUtils]: 70: Hoare triple {8182#false} assume !(1 == ~T2_E~0); {8182#false} is VALID [2022-02-21 04:24:13,251 INFO L290 TraceCheckUtils]: 71: Hoare triple {8182#false} assume !(1 == ~T3_E~0); {8182#false} is VALID [2022-02-21 04:24:13,251 INFO L290 TraceCheckUtils]: 72: Hoare triple {8182#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {8182#false} is VALID [2022-02-21 04:24:13,251 INFO L290 TraceCheckUtils]: 73: Hoare triple {8182#false} assume !(1 == ~T5_E~0); {8182#false} is VALID [2022-02-21 04:24:13,251 INFO L290 TraceCheckUtils]: 74: Hoare triple {8182#false} assume !(1 == ~T6_E~0); {8182#false} is VALID [2022-02-21 04:24:13,252 INFO L290 TraceCheckUtils]: 75: Hoare triple {8182#false} assume !(1 == ~E_1~0); {8182#false} is VALID [2022-02-21 04:24:13,252 INFO L290 TraceCheckUtils]: 76: Hoare triple {8182#false} assume !(1 == ~E_2~0); {8182#false} is VALID [2022-02-21 04:24:13,252 INFO L290 TraceCheckUtils]: 77: Hoare triple {8182#false} assume !(1 == ~E_3~0); {8182#false} is VALID [2022-02-21 04:24:13,252 INFO L290 TraceCheckUtils]: 78: Hoare triple {8182#false} assume !(1 == ~E_4~0); {8182#false} is VALID [2022-02-21 04:24:13,252 INFO L290 TraceCheckUtils]: 79: Hoare triple {8182#false} assume !(1 == ~E_5~0); {8182#false} is VALID [2022-02-21 04:24:13,252 INFO L290 TraceCheckUtils]: 80: Hoare triple {8182#false} assume 1 == ~E_6~0;~E_6~0 := 2; {8182#false} is VALID [2022-02-21 04:24:13,252 INFO L290 TraceCheckUtils]: 81: Hoare triple {8182#false} assume { :end_inline_reset_delta_events } true; {8182#false} is VALID [2022-02-21 04:24:13,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:13,253 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:13,253 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987372971] [2022-02-21 04:24:13,253 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1987372971] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:13,253 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:13,253 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:13,254 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231036830] [2022-02-21 04:24:13,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:13,254 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:13,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:13,255 INFO L85 PathProgramCache]: Analyzing trace with hash -1740663615, now seen corresponding path program 1 times [2022-02-21 04:24:13,255 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:13,255 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1224616215] [2022-02-21 04:24:13,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:13,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:13,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:13,285 INFO L290 TraceCheckUtils]: 0: Hoare triple {8184#true} assume !false; {8184#true} is VALID [2022-02-21 04:24:13,285 INFO L290 TraceCheckUtils]: 1: Hoare triple {8184#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {8184#true} is VALID [2022-02-21 04:24:13,285 INFO L290 TraceCheckUtils]: 2: Hoare triple {8184#true} assume !false; {8184#true} is VALID [2022-02-21 04:24:13,286 INFO L290 TraceCheckUtils]: 3: Hoare triple {8184#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {8184#true} is VALID [2022-02-21 04:24:13,286 INFO L290 TraceCheckUtils]: 4: Hoare triple {8184#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {8184#true} is VALID [2022-02-21 04:24:13,286 INFO L290 TraceCheckUtils]: 5: Hoare triple {8184#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {8184#true} is VALID [2022-02-21 04:24:13,286 INFO L290 TraceCheckUtils]: 6: Hoare triple {8184#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {8184#true} is VALID [2022-02-21 04:24:13,286 INFO L290 TraceCheckUtils]: 7: Hoare triple {8184#true} assume !(0 != eval_~tmp~0#1); {8184#true} is VALID [2022-02-21 04:24:13,286 INFO L290 TraceCheckUtils]: 8: Hoare triple {8184#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {8184#true} is VALID [2022-02-21 04:24:13,286 INFO L290 TraceCheckUtils]: 9: Hoare triple {8184#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {8184#true} is VALID [2022-02-21 04:24:13,286 INFO L290 TraceCheckUtils]: 10: Hoare triple {8184#true} assume 0 == ~M_E~0;~M_E~0 := 1; {8184#true} is VALID [2022-02-21 04:24:13,287 INFO L290 TraceCheckUtils]: 11: Hoare triple {8184#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {8184#true} is VALID [2022-02-21 04:24:13,287 INFO L290 TraceCheckUtils]: 12: Hoare triple {8184#true} assume !(0 == ~T2_E~0); {8184#true} is VALID [2022-02-21 04:24:13,287 INFO L290 TraceCheckUtils]: 13: Hoare triple {8184#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {8184#true} is VALID [2022-02-21 04:24:13,299 INFO L290 TraceCheckUtils]: 14: Hoare triple {8184#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {8184#true} is VALID [2022-02-21 04:24:13,299 INFO L290 TraceCheckUtils]: 15: Hoare triple {8184#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {8184#true} is VALID [2022-02-21 04:24:13,299 INFO L290 TraceCheckUtils]: 16: Hoare triple {8184#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {8184#true} is VALID [2022-02-21 04:24:13,300 INFO L290 TraceCheckUtils]: 17: Hoare triple {8184#true} assume 0 == ~E_1~0;~E_1~0 := 1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,300 INFO L290 TraceCheckUtils]: 18: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,300 INFO L290 TraceCheckUtils]: 19: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,301 INFO L290 TraceCheckUtils]: 20: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,301 INFO L290 TraceCheckUtils]: 21: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,301 INFO L290 TraceCheckUtils]: 22: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,302 INFO L290 TraceCheckUtils]: 23: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,302 INFO L290 TraceCheckUtils]: 24: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,302 INFO L290 TraceCheckUtils]: 25: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,303 INFO L290 TraceCheckUtils]: 26: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,303 INFO L290 TraceCheckUtils]: 27: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,303 INFO L290 TraceCheckUtils]: 28: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,304 INFO L290 TraceCheckUtils]: 29: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,304 INFO L290 TraceCheckUtils]: 30: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,304 INFO L290 TraceCheckUtils]: 31: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,305 INFO L290 TraceCheckUtils]: 32: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,305 INFO L290 TraceCheckUtils]: 33: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,305 INFO L290 TraceCheckUtils]: 34: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,306 INFO L290 TraceCheckUtils]: 35: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,306 INFO L290 TraceCheckUtils]: 36: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t2_pc~0); {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,306 INFO L290 TraceCheckUtils]: 37: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,306 INFO L290 TraceCheckUtils]: 38: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,307 INFO L290 TraceCheckUtils]: 39: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,308 INFO L290 TraceCheckUtils]: 40: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,308 INFO L290 TraceCheckUtils]: 41: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,308 INFO L290 TraceCheckUtils]: 42: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t3_pc~0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,309 INFO L290 TraceCheckUtils]: 43: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,309 INFO L290 TraceCheckUtils]: 44: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,309 INFO L290 TraceCheckUtils]: 45: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,310 INFO L290 TraceCheckUtils]: 46: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,310 INFO L290 TraceCheckUtils]: 47: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,310 INFO L290 TraceCheckUtils]: 48: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,311 INFO L290 TraceCheckUtils]: 49: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,311 INFO L290 TraceCheckUtils]: 50: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,311 INFO L290 TraceCheckUtils]: 51: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,312 INFO L290 TraceCheckUtils]: 52: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,312 INFO L290 TraceCheckUtils]: 53: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,312 INFO L290 TraceCheckUtils]: 54: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t5_pc~0); {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,312 INFO L290 TraceCheckUtils]: 55: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,313 INFO L290 TraceCheckUtils]: 56: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,313 INFO L290 TraceCheckUtils]: 57: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,313 INFO L290 TraceCheckUtils]: 58: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,314 INFO L290 TraceCheckUtils]: 59: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,314 INFO L290 TraceCheckUtils]: 60: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t6_pc~0); {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,314 INFO L290 TraceCheckUtils]: 61: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,315 INFO L290 TraceCheckUtils]: 62: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,315 INFO L290 TraceCheckUtils]: 63: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,315 INFO L290 TraceCheckUtils]: 64: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,316 INFO L290 TraceCheckUtils]: 65: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,316 INFO L290 TraceCheckUtils]: 66: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,316 INFO L290 TraceCheckUtils]: 67: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,317 INFO L290 TraceCheckUtils]: 68: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,317 INFO L290 TraceCheckUtils]: 69: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,317 INFO L290 TraceCheckUtils]: 70: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,317 INFO L290 TraceCheckUtils]: 71: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,318 INFO L290 TraceCheckUtils]: 72: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {8186#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,318 INFO L290 TraceCheckUtils]: 73: Hoare triple {8186#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {8185#false} is VALID [2022-02-21 04:24:13,318 INFO L290 TraceCheckUtils]: 74: Hoare triple {8185#false} assume 1 == ~E_2~0;~E_2~0 := 2; {8185#false} is VALID [2022-02-21 04:24:13,318 INFO L290 TraceCheckUtils]: 75: Hoare triple {8185#false} assume 1 == ~E_3~0;~E_3~0 := 2; {8185#false} is VALID [2022-02-21 04:24:13,318 INFO L290 TraceCheckUtils]: 76: Hoare triple {8185#false} assume 1 == ~E_4~0;~E_4~0 := 2; {8185#false} is VALID [2022-02-21 04:24:13,318 INFO L290 TraceCheckUtils]: 77: Hoare triple {8185#false} assume 1 == ~E_5~0;~E_5~0 := 2; {8185#false} is VALID [2022-02-21 04:24:13,318 INFO L290 TraceCheckUtils]: 78: Hoare triple {8185#false} assume 1 == ~E_6~0;~E_6~0 := 2; {8185#false} is VALID [2022-02-21 04:24:13,319 INFO L290 TraceCheckUtils]: 79: Hoare triple {8185#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {8185#false} is VALID [2022-02-21 04:24:13,319 INFO L290 TraceCheckUtils]: 80: Hoare triple {8185#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {8185#false} is VALID [2022-02-21 04:24:13,319 INFO L290 TraceCheckUtils]: 81: Hoare triple {8185#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {8185#false} is VALID [2022-02-21 04:24:13,319 INFO L290 TraceCheckUtils]: 82: Hoare triple {8185#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {8185#false} is VALID [2022-02-21 04:24:13,321 INFO L290 TraceCheckUtils]: 83: Hoare triple {8185#false} assume !(0 == start_simulation_~tmp~3#1); {8185#false} is VALID [2022-02-21 04:24:13,321 INFO L290 TraceCheckUtils]: 84: Hoare triple {8185#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {8185#false} is VALID [2022-02-21 04:24:13,321 INFO L290 TraceCheckUtils]: 85: Hoare triple {8185#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {8185#false} is VALID [2022-02-21 04:24:13,321 INFO L290 TraceCheckUtils]: 86: Hoare triple {8185#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {8185#false} is VALID [2022-02-21 04:24:13,321 INFO L290 TraceCheckUtils]: 87: Hoare triple {8185#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {8185#false} is VALID [2022-02-21 04:24:13,322 INFO L290 TraceCheckUtils]: 88: Hoare triple {8185#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {8185#false} is VALID [2022-02-21 04:24:13,322 INFO L290 TraceCheckUtils]: 89: Hoare triple {8185#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {8185#false} is VALID [2022-02-21 04:24:13,322 INFO L290 TraceCheckUtils]: 90: Hoare triple {8185#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {8185#false} is VALID [2022-02-21 04:24:13,322 INFO L290 TraceCheckUtils]: 91: Hoare triple {8185#false} assume !(0 != start_simulation_~tmp___0~1#1); {8185#false} is VALID [2022-02-21 04:24:13,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:13,323 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:13,323 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1224616215] [2022-02-21 04:24:13,323 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1224616215] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:13,323 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:13,323 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:13,323 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [860787695] [2022-02-21 04:24:13,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:13,324 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:13,324 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:13,324 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:13,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:13,325 INFO L87 Difference]: Start difference. First operand 626 states and 935 transitions. cyclomatic complexity: 310 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:13,711 INFO L93 Difference]: Finished difference Result 626 states and 934 transitions. [2022-02-21 04:24:13,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:13,712 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,764 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:13,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 934 transitions. [2022-02-21 04:24:13,777 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:13,788 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 934 transitions. [2022-02-21 04:24:13,789 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-02-21 04:24:13,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-02-21 04:24:13,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 934 transitions. [2022-02-21 04:24:13,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:13,790 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 934 transitions. [2022-02-21 04:24:13,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 934 transitions. [2022-02-21 04:24:13,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-02-21 04:24:13,795 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:13,796 INFO L82 GeneralOperation]: Start isEquivalent. First operand 626 states and 934 transitions. Second operand has 626 states, 626 states have (on average 1.4920127795527156) internal successors, (934), 625 states have internal predecessors, (934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,797 INFO L74 IsIncluded]: Start isIncluded. First operand 626 states and 934 transitions. Second operand has 626 states, 626 states have (on average 1.4920127795527156) internal successors, (934), 625 states have internal predecessors, (934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,798 INFO L87 Difference]: Start difference. First operand 626 states and 934 transitions. Second operand has 626 states, 626 states have (on average 1.4920127795527156) internal successors, (934), 625 states have internal predecessors, (934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:13,809 INFO L93 Difference]: Finished difference Result 626 states and 934 transitions. [2022-02-21 04:24:13,809 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 934 transitions. [2022-02-21 04:24:13,810 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:13,810 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:13,812 INFO L74 IsIncluded]: Start isIncluded. First operand has 626 states, 626 states have (on average 1.4920127795527156) internal successors, (934), 625 states have internal predecessors, (934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 934 transitions. [2022-02-21 04:24:13,812 INFO L87 Difference]: Start difference. First operand has 626 states, 626 states have (on average 1.4920127795527156) internal successors, (934), 625 states have internal predecessors, (934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 934 transitions. [2022-02-21 04:24:13,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:13,824 INFO L93 Difference]: Finished difference Result 626 states and 934 transitions. [2022-02-21 04:24:13,824 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 934 transitions. [2022-02-21 04:24:13,825 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:13,825 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:13,826 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:13,826 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:13,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4920127795527156) internal successors, (934), 625 states have internal predecessors, (934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:13,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 934 transitions. [2022-02-21 04:24:13,839 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 934 transitions. [2022-02-21 04:24:13,839 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 934 transitions. [2022-02-21 04:24:13,839 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:13,839 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 934 transitions. [2022-02-21 04:24:13,841 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:13,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:13,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:13,844 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:13,845 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:13,845 INFO L791 eck$LassoCheckResult]: Stem: 9438#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 9421#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9373#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8817#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8813#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 8814#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9328#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9432#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8907#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8908#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9062#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8926#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8927#L670 assume !(0 == ~M_E~0); 9297#L670-2 assume !(0 == ~T1_E~0); 9245#L675-1 assume !(0 == ~T2_E~0); 9246#L680-1 assume !(0 == ~T3_E~0); 9327#L685-1 assume !(0 == ~T4_E~0); 9300#L690-1 assume !(0 == ~T5_E~0); 9301#L695-1 assume !(0 == ~T6_E~0); 9359#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 9351#L705-1 assume !(0 == ~E_2~0); 9352#L710-1 assume !(0 == ~E_3~0); 9243#L715-1 assume !(0 == ~E_4~0); 9166#L720-1 assume !(0 == ~E_5~0); 9167#L725-1 assume !(0 == ~E_6~0); 9222#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9269#L320 assume 1 == ~m_pc~0; 9210#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9104#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9105#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9063#L825 assume !(0 != activate_threads_~tmp~1#1); 9064#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9069#L339 assume !(1 == ~t1_pc~0); 9070#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9047#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9048#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8929#L833 assume !(0 != activate_threads_~tmp___0~0#1); 8930#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8838#L358 assume 1 == ~t2_pc~0; 8839#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9347#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9298#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9226#L841 assume !(0 != activate_threads_~tmp___1~0#1); 9058#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9059#L377 assume !(1 == ~t3_pc~0); 9313#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9314#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9309#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9067#L849 assume !(0 != activate_threads_~tmp___2~0#1); 9068#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9013#L396 assume 1 == ~t4_pc~0; 9014#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8841#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8842#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9260#L857 assume !(0 != activate_threads_~tmp___3~0#1); 8982#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8983#L415 assume 1 == ~t5_pc~0; 9049#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9092#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9270#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9377#L865 assume !(0 != activate_threads_~tmp___4~0#1); 8884#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8885#L434 assume !(1 == ~t6_pc~0); 9199#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9200#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9339#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9340#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9080#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9081#L743 assume !(1 == ~M_E~0); 8974#L743-2 assume !(1 == ~T1_E~0); 8975#L748-1 assume !(1 == ~T2_E~0); 9263#L753-1 assume !(1 == ~T3_E~0); 9264#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9363#L763-1 assume !(1 == ~T5_E~0); 9395#L768-1 assume !(1 == ~T6_E~0); 9073#L773-1 assume !(1 == ~E_1~0); 9074#L778-1 assume !(1 == ~E_2~0); 9055#L783-1 assume !(1 == ~E_3~0); 9056#L788-1 assume !(1 == ~E_4~0); 9325#L793-1 assume !(1 == ~E_5~0); 9290#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8946#L803-1 assume { :end_inline_reset_delta_events } true; 8947#L1024-2 [2022-02-21 04:24:13,845 INFO L793 eck$LassoCheckResult]: Loop: 8947#L1024-2 assume !false; 9232#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9287#L645 assume !false; 9164#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9165#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8892#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9369#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9402#L556 assume !(0 != eval_~tmp~0#1); 9436#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9346#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8938#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8939#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9099#L675-3 assume !(0 == ~T2_E~0); 9100#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9322#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9323#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9433#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9331#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9332#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8995#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8996#L715-3 assume !(0 == ~E_4~0); 9227#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9228#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9302#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9075#L320-21 assume 1 == ~m_pc~0; 9076#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9225#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9151#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9152#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9386#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9008#L339-21 assume !(1 == ~t1_pc~0); 9009#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 9112#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8984#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8866#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8867#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8966#L358-21 assume 1 == ~t2_pc~0; 9072#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8948#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8949#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9231#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8985#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8986#L377-21 assume 1 == ~t3_pc~0; 9398#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9258#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9259#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9278#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9123#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9124#L396-21 assume 1 == ~t4_pc~0; 9291#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9150#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9121#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8848#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 8849#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9101#L415-21 assume !(1 == ~t5_pc~0); 9078#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 9079#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8970#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8971#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9171#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9172#L434-21 assume !(1 == ~t6_pc~0); 8873#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 8874#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9375#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9095#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9096#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9090#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9091#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9411#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9253#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9191#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9114#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9115#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9399#L773-3 assume !(1 == ~E_1~0); 9033#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9034#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9256#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9423#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9424#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9296#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9024#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8920#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9184#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9185#L1043 assume !(0 == start_simulation_~tmp~3#1); 9378#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9254#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9042#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9224#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9212#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8934#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8935#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9082#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 8947#L1024-2 [2022-02-21 04:24:13,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:13,846 INFO L85 PathProgramCache]: Analyzing trace with hash 1901446621, now seen corresponding path program 1 times [2022-02-21 04:24:13,846 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:13,846 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563168595] [2022-02-21 04:24:13,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:13,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:13,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:13,889 INFO L290 TraceCheckUtils]: 0: Hoare triple {10694#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {10694#true} is VALID [2022-02-21 04:24:13,890 INFO L290 TraceCheckUtils]: 1: Hoare triple {10694#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {10696#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,890 INFO L290 TraceCheckUtils]: 2: Hoare triple {10696#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10696#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,890 INFO L290 TraceCheckUtils]: 3: Hoare triple {10696#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10696#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,890 INFO L290 TraceCheckUtils]: 4: Hoare triple {10696#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {10696#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,891 INFO L290 TraceCheckUtils]: 5: Hoare triple {10696#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10696#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,891 INFO L290 TraceCheckUtils]: 6: Hoare triple {10696#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {10696#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,891 INFO L290 TraceCheckUtils]: 7: Hoare triple {10696#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {10696#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,891 INFO L290 TraceCheckUtils]: 8: Hoare triple {10696#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {10696#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:13,891 INFO L290 TraceCheckUtils]: 9: Hoare triple {10696#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 10: Hoare triple {10695#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 11: Hoare triple {10695#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 12: Hoare triple {10695#false} assume !(0 == ~M_E~0); {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 13: Hoare triple {10695#false} assume !(0 == ~T1_E~0); {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 14: Hoare triple {10695#false} assume !(0 == ~T2_E~0); {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 15: Hoare triple {10695#false} assume !(0 == ~T3_E~0); {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 16: Hoare triple {10695#false} assume !(0 == ~T4_E~0); {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 17: Hoare triple {10695#false} assume !(0 == ~T5_E~0); {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 18: Hoare triple {10695#false} assume !(0 == ~T6_E~0); {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 19: Hoare triple {10695#false} assume 0 == ~E_1~0;~E_1~0 := 1; {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 20: Hoare triple {10695#false} assume !(0 == ~E_2~0); {10695#false} is VALID [2022-02-21 04:24:13,892 INFO L290 TraceCheckUtils]: 21: Hoare triple {10695#false} assume !(0 == ~E_3~0); {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 22: Hoare triple {10695#false} assume !(0 == ~E_4~0); {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 23: Hoare triple {10695#false} assume !(0 == ~E_5~0); {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 24: Hoare triple {10695#false} assume !(0 == ~E_6~0); {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 25: Hoare triple {10695#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 26: Hoare triple {10695#false} assume 1 == ~m_pc~0; {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 27: Hoare triple {10695#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 28: Hoare triple {10695#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 29: Hoare triple {10695#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 30: Hoare triple {10695#false} assume !(0 != activate_threads_~tmp~1#1); {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 31: Hoare triple {10695#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 32: Hoare triple {10695#false} assume !(1 == ~t1_pc~0); {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 33: Hoare triple {10695#false} is_transmit1_triggered_~__retres1~1#1 := 0; {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 34: Hoare triple {10695#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 35: Hoare triple {10695#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {10695#false} is VALID [2022-02-21 04:24:13,916 INFO L290 TraceCheckUtils]: 36: Hoare triple {10695#false} assume !(0 != activate_threads_~tmp___0~0#1); {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 37: Hoare triple {10695#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 38: Hoare triple {10695#false} assume 1 == ~t2_pc~0; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 39: Hoare triple {10695#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 40: Hoare triple {10695#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 41: Hoare triple {10695#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 42: Hoare triple {10695#false} assume !(0 != activate_threads_~tmp___1~0#1); {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 43: Hoare triple {10695#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 44: Hoare triple {10695#false} assume !(1 == ~t3_pc~0); {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 45: Hoare triple {10695#false} is_transmit3_triggered_~__retres1~3#1 := 0; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 46: Hoare triple {10695#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 47: Hoare triple {10695#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 48: Hoare triple {10695#false} assume !(0 != activate_threads_~tmp___2~0#1); {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 49: Hoare triple {10695#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 50: Hoare triple {10695#false} assume 1 == ~t4_pc~0; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 51: Hoare triple {10695#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 52: Hoare triple {10695#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 53: Hoare triple {10695#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10695#false} is VALID [2022-02-21 04:24:13,917 INFO L290 TraceCheckUtils]: 54: Hoare triple {10695#false} assume !(0 != activate_threads_~tmp___3~0#1); {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 55: Hoare triple {10695#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 56: Hoare triple {10695#false} assume 1 == ~t5_pc~0; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 57: Hoare triple {10695#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 58: Hoare triple {10695#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 59: Hoare triple {10695#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 60: Hoare triple {10695#false} assume !(0 != activate_threads_~tmp___4~0#1); {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 61: Hoare triple {10695#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 62: Hoare triple {10695#false} assume !(1 == ~t6_pc~0); {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 63: Hoare triple {10695#false} is_transmit6_triggered_~__retres1~6#1 := 0; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 64: Hoare triple {10695#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 65: Hoare triple {10695#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 66: Hoare triple {10695#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 67: Hoare triple {10695#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 68: Hoare triple {10695#false} assume !(1 == ~M_E~0); {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 69: Hoare triple {10695#false} assume !(1 == ~T1_E~0); {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 70: Hoare triple {10695#false} assume !(1 == ~T2_E~0); {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 71: Hoare triple {10695#false} assume !(1 == ~T3_E~0); {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 72: Hoare triple {10695#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10695#false} is VALID [2022-02-21 04:24:13,918 INFO L290 TraceCheckUtils]: 73: Hoare triple {10695#false} assume !(1 == ~T5_E~0); {10695#false} is VALID [2022-02-21 04:24:13,919 INFO L290 TraceCheckUtils]: 74: Hoare triple {10695#false} assume !(1 == ~T6_E~0); {10695#false} is VALID [2022-02-21 04:24:13,919 INFO L290 TraceCheckUtils]: 75: Hoare triple {10695#false} assume !(1 == ~E_1~0); {10695#false} is VALID [2022-02-21 04:24:13,919 INFO L290 TraceCheckUtils]: 76: Hoare triple {10695#false} assume !(1 == ~E_2~0); {10695#false} is VALID [2022-02-21 04:24:13,919 INFO L290 TraceCheckUtils]: 77: Hoare triple {10695#false} assume !(1 == ~E_3~0); {10695#false} is VALID [2022-02-21 04:24:13,919 INFO L290 TraceCheckUtils]: 78: Hoare triple {10695#false} assume !(1 == ~E_4~0); {10695#false} is VALID [2022-02-21 04:24:13,919 INFO L290 TraceCheckUtils]: 79: Hoare triple {10695#false} assume !(1 == ~E_5~0); {10695#false} is VALID [2022-02-21 04:24:13,919 INFO L290 TraceCheckUtils]: 80: Hoare triple {10695#false} assume 1 == ~E_6~0;~E_6~0 := 2; {10695#false} is VALID [2022-02-21 04:24:13,919 INFO L290 TraceCheckUtils]: 81: Hoare triple {10695#false} assume { :end_inline_reset_delta_events } true; {10695#false} is VALID [2022-02-21 04:24:13,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:13,919 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:13,919 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563168595] [2022-02-21 04:24:13,919 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1563168595] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:13,920 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:13,920 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:13,920 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491725244] [2022-02-21 04:24:13,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:13,920 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:13,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:13,920 INFO L85 PathProgramCache]: Analyzing trace with hash -1748414174, now seen corresponding path program 1 times [2022-02-21 04:24:13,920 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:13,921 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446915129] [2022-02-21 04:24:13,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:13,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:13,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:13,954 INFO L290 TraceCheckUtils]: 0: Hoare triple {10697#true} assume !false; {10697#true} is VALID [2022-02-21 04:24:13,954 INFO L290 TraceCheckUtils]: 1: Hoare triple {10697#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10697#true} is VALID [2022-02-21 04:24:13,954 INFO L290 TraceCheckUtils]: 2: Hoare triple {10697#true} assume !false; {10697#true} is VALID [2022-02-21 04:24:13,954 INFO L290 TraceCheckUtils]: 3: Hoare triple {10697#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {10697#true} is VALID [2022-02-21 04:24:13,954 INFO L290 TraceCheckUtils]: 4: Hoare triple {10697#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {10697#true} is VALID [2022-02-21 04:24:13,954 INFO L290 TraceCheckUtils]: 5: Hoare triple {10697#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 6: Hoare triple {10697#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 7: Hoare triple {10697#true} assume !(0 != eval_~tmp~0#1); {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 8: Hoare triple {10697#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 9: Hoare triple {10697#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 10: Hoare triple {10697#true} assume 0 == ~M_E~0;~M_E~0 := 1; {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 11: Hoare triple {10697#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 12: Hoare triple {10697#true} assume !(0 == ~T2_E~0); {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 13: Hoare triple {10697#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 14: Hoare triple {10697#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 15: Hoare triple {10697#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 16: Hoare triple {10697#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10697#true} is VALID [2022-02-21 04:24:13,955 INFO L290 TraceCheckUtils]: 17: Hoare triple {10697#true} assume 0 == ~E_1~0;~E_1~0 := 1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,956 INFO L290 TraceCheckUtils]: 18: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,956 INFO L290 TraceCheckUtils]: 19: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,956 INFO L290 TraceCheckUtils]: 20: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,956 INFO L290 TraceCheckUtils]: 21: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,957 INFO L290 TraceCheckUtils]: 22: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,957 INFO L290 TraceCheckUtils]: 23: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,957 INFO L290 TraceCheckUtils]: 24: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,957 INFO L290 TraceCheckUtils]: 25: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,958 INFO L290 TraceCheckUtils]: 26: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,958 INFO L290 TraceCheckUtils]: 27: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,958 INFO L290 TraceCheckUtils]: 28: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,959 INFO L290 TraceCheckUtils]: 29: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,959 INFO L290 TraceCheckUtils]: 30: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,959 INFO L290 TraceCheckUtils]: 31: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,959 INFO L290 TraceCheckUtils]: 32: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,960 INFO L290 TraceCheckUtils]: 33: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,960 INFO L290 TraceCheckUtils]: 34: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,960 INFO L290 TraceCheckUtils]: 35: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,960 INFO L290 TraceCheckUtils]: 36: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t2_pc~0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,961 INFO L290 TraceCheckUtils]: 37: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,961 INFO L290 TraceCheckUtils]: 38: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,961 INFO L290 TraceCheckUtils]: 39: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,962 INFO L290 TraceCheckUtils]: 40: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,962 INFO L290 TraceCheckUtils]: 41: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,962 INFO L290 TraceCheckUtils]: 42: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t3_pc~0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,962 INFO L290 TraceCheckUtils]: 43: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,963 INFO L290 TraceCheckUtils]: 44: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,963 INFO L290 TraceCheckUtils]: 45: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,963 INFO L290 TraceCheckUtils]: 46: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,963 INFO L290 TraceCheckUtils]: 47: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,964 INFO L290 TraceCheckUtils]: 48: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,964 INFO L290 TraceCheckUtils]: 49: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,964 INFO L290 TraceCheckUtils]: 50: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,965 INFO L290 TraceCheckUtils]: 51: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,965 INFO L290 TraceCheckUtils]: 52: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,965 INFO L290 TraceCheckUtils]: 53: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,965 INFO L290 TraceCheckUtils]: 54: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t5_pc~0); {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,966 INFO L290 TraceCheckUtils]: 55: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,966 INFO L290 TraceCheckUtils]: 56: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,966 INFO L290 TraceCheckUtils]: 57: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,966 INFO L290 TraceCheckUtils]: 58: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,967 INFO L290 TraceCheckUtils]: 59: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,967 INFO L290 TraceCheckUtils]: 60: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t6_pc~0); {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,967 INFO L290 TraceCheckUtils]: 61: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,968 INFO L290 TraceCheckUtils]: 62: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,968 INFO L290 TraceCheckUtils]: 63: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,968 INFO L290 TraceCheckUtils]: 64: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,968 INFO L290 TraceCheckUtils]: 65: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,969 INFO L290 TraceCheckUtils]: 66: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,969 INFO L290 TraceCheckUtils]: 67: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,969 INFO L290 TraceCheckUtils]: 68: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,969 INFO L290 TraceCheckUtils]: 69: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,970 INFO L290 TraceCheckUtils]: 70: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,970 INFO L290 TraceCheckUtils]: 71: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,970 INFO L290 TraceCheckUtils]: 72: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {10699#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 73: Hoare triple {10699#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 74: Hoare triple {10698#false} assume 1 == ~E_2~0;~E_2~0 := 2; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 75: Hoare triple {10698#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 76: Hoare triple {10698#false} assume 1 == ~E_4~0;~E_4~0 := 2; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 77: Hoare triple {10698#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 78: Hoare triple {10698#false} assume 1 == ~E_6~0;~E_6~0 := 2; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 79: Hoare triple {10698#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 80: Hoare triple {10698#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 81: Hoare triple {10698#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 82: Hoare triple {10698#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 83: Hoare triple {10698#false} assume !(0 == start_simulation_~tmp~3#1); {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 84: Hoare triple {10698#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 85: Hoare triple {10698#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 86: Hoare triple {10698#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 87: Hoare triple {10698#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 88: Hoare triple {10698#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {10698#false} is VALID [2022-02-21 04:24:13,971 INFO L290 TraceCheckUtils]: 89: Hoare triple {10698#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10698#false} is VALID [2022-02-21 04:24:13,972 INFO L290 TraceCheckUtils]: 90: Hoare triple {10698#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {10698#false} is VALID [2022-02-21 04:24:13,972 INFO L290 TraceCheckUtils]: 91: Hoare triple {10698#false} assume !(0 != start_simulation_~tmp___0~1#1); {10698#false} is VALID [2022-02-21 04:24:13,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:13,972 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:13,972 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446915129] [2022-02-21 04:24:13,972 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1446915129] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:13,973 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:13,973 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:13,973 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963625465] [2022-02-21 04:24:13,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:13,973 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:13,973 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:13,974 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:13,974 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:13,974 INFO L87 Difference]: Start difference. First operand 626 states and 934 transitions. cyclomatic complexity: 309 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:14,362 INFO L93 Difference]: Finished difference Result 626 states and 933 transitions. [2022-02-21 04:24:14,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:14,362 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,415 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:14,415 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 933 transitions. [2022-02-21 04:24:14,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:14,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 933 transitions. [2022-02-21 04:24:14,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-02-21 04:24:14,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-02-21 04:24:14,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 933 transitions. [2022-02-21 04:24:14,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:14,439 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 933 transitions. [2022-02-21 04:24:14,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 933 transitions. [2022-02-21 04:24:14,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-02-21 04:24:14,444 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:14,445 INFO L82 GeneralOperation]: Start isEquivalent. First operand 626 states and 933 transitions. Second operand has 626 states, 626 states have (on average 1.4904153354632588) internal successors, (933), 625 states have internal predecessors, (933), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,446 INFO L74 IsIncluded]: Start isIncluded. First operand 626 states and 933 transitions. Second operand has 626 states, 626 states have (on average 1.4904153354632588) internal successors, (933), 625 states have internal predecessors, (933), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,446 INFO L87 Difference]: Start difference. First operand 626 states and 933 transitions. Second operand has 626 states, 626 states have (on average 1.4904153354632588) internal successors, (933), 625 states have internal predecessors, (933), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:14,459 INFO L93 Difference]: Finished difference Result 626 states and 933 transitions. [2022-02-21 04:24:14,459 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 933 transitions. [2022-02-21 04:24:14,459 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:14,459 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:14,460 INFO L74 IsIncluded]: Start isIncluded. First operand has 626 states, 626 states have (on average 1.4904153354632588) internal successors, (933), 625 states have internal predecessors, (933), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 933 transitions. [2022-02-21 04:24:14,461 INFO L87 Difference]: Start difference. First operand has 626 states, 626 states have (on average 1.4904153354632588) internal successors, (933), 625 states have internal predecessors, (933), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 933 transitions. [2022-02-21 04:24:14,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:14,472 INFO L93 Difference]: Finished difference Result 626 states and 933 transitions. [2022-02-21 04:24:14,472 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 933 transitions. [2022-02-21 04:24:14,473 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:14,473 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:14,473 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:14,473 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:14,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.4904153354632588) internal successors, (933), 625 states have internal predecessors, (933), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 933 transitions. [2022-02-21 04:24:14,485 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 933 transitions. [2022-02-21 04:24:14,485 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 933 transitions. [2022-02-21 04:24:14,485 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:14,486 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 933 transitions. [2022-02-21 04:24:14,487 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:14,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:14,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:14,488 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:14,488 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:14,488 INFO L791 eck$LassoCheckResult]: Stem: 11951#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 11934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 11886#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11330#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11326#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 11327#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11841#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11945#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11420#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11421#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11575#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11439#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11440#L670 assume !(0 == ~M_E~0); 11810#L670-2 assume !(0 == ~T1_E~0); 11758#L675-1 assume !(0 == ~T2_E~0); 11759#L680-1 assume !(0 == ~T3_E~0); 11840#L685-1 assume !(0 == ~T4_E~0); 11813#L690-1 assume !(0 == ~T5_E~0); 11814#L695-1 assume !(0 == ~T6_E~0); 11872#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 11864#L705-1 assume !(0 == ~E_2~0); 11865#L710-1 assume !(0 == ~E_3~0); 11756#L715-1 assume !(0 == ~E_4~0); 11679#L720-1 assume !(0 == ~E_5~0); 11680#L725-1 assume !(0 == ~E_6~0); 11735#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11782#L320 assume 1 == ~m_pc~0; 11723#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11617#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11618#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11576#L825 assume !(0 != activate_threads_~tmp~1#1); 11577#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11582#L339 assume !(1 == ~t1_pc~0); 11583#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11560#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11561#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11442#L833 assume !(0 != activate_threads_~tmp___0~0#1); 11443#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11351#L358 assume 1 == ~t2_pc~0; 11352#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11860#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11811#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11739#L841 assume !(0 != activate_threads_~tmp___1~0#1); 11573#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11574#L377 assume !(1 == ~t3_pc~0); 11826#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11827#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11822#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11580#L849 assume !(0 != activate_threads_~tmp___2~0#1); 11581#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11526#L396 assume 1 == ~t4_pc~0; 11527#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11354#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11355#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11773#L857 assume !(0 != activate_threads_~tmp___3~0#1); 11495#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11496#L415 assume 1 == ~t5_pc~0; 11562#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11607#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11783#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11890#L865 assume !(0 != activate_threads_~tmp___4~0#1); 11397#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11398#L434 assume !(1 == ~t6_pc~0); 11712#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11713#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11852#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11853#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11593#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11594#L743 assume !(1 == ~M_E~0); 11487#L743-2 assume !(1 == ~T1_E~0); 11488#L748-1 assume !(1 == ~T2_E~0); 11776#L753-1 assume !(1 == ~T3_E~0); 11777#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11876#L763-1 assume !(1 == ~T5_E~0); 11908#L768-1 assume !(1 == ~T6_E~0); 11586#L773-1 assume !(1 == ~E_1~0); 11587#L778-1 assume !(1 == ~E_2~0); 11568#L783-1 assume !(1 == ~E_3~0); 11569#L788-1 assume !(1 == ~E_4~0); 11838#L793-1 assume !(1 == ~E_5~0); 11803#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11459#L803-1 assume { :end_inline_reset_delta_events } true; 11460#L1024-2 [2022-02-21 04:24:14,489 INFO L793 eck$LassoCheckResult]: Loop: 11460#L1024-2 assume !false; 11745#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11800#L645 assume !false; 11677#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11678#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 11405#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11882#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11915#L556 assume !(0 != eval_~tmp~0#1); 11949#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11859#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11451#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11452#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11612#L675-3 assume !(0 == ~T2_E~0); 11613#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11835#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11836#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11946#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11844#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11845#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11508#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11509#L715-3 assume !(0 == ~E_4~0); 11740#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11741#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11815#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11588#L320-21 assume 1 == ~m_pc~0; 11589#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11738#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11664#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11665#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11900#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11521#L339-21 assume !(1 == ~t1_pc~0); 11522#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 11625#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11497#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11379#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11380#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11479#L358-21 assume 1 == ~t2_pc~0; 11585#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11461#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11462#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11744#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11498#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11499#L377-21 assume 1 == ~t3_pc~0; 11911#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11771#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11772#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11791#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11636#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11637#L396-21 assume 1 == ~t4_pc~0; 11804#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11663#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11634#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11363#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 11364#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11614#L415-21 assume !(1 == ~t5_pc~0); 11591#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 11592#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11483#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11484#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11684#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11685#L434-21 assume 1 == ~t6_pc~0; 11696#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11387#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11888#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11608#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11609#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11603#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11604#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11924#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11766#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11704#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11627#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11628#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11912#L773-3 assume !(1 == ~E_1~0); 11546#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11547#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11769#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11936#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11937#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11809#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11537#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 11433#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11697#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 11698#L1043 assume !(0 == start_simulation_~tmp~3#1); 11892#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11767#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 11554#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11737#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 11725#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11447#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11448#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 11595#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 11460#L1024-2 [2022-02-21 04:24:14,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:14,489 INFO L85 PathProgramCache]: Analyzing trace with hash -482478117, now seen corresponding path program 1 times [2022-02-21 04:24:14,489 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:14,489 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983013582] [2022-02-21 04:24:14,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:14,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:14,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:14,505 INFO L290 TraceCheckUtils]: 0: Hoare triple {13207#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {13207#true} is VALID [2022-02-21 04:24:14,505 INFO L290 TraceCheckUtils]: 1: Hoare triple {13207#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {13209#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:14,505 INFO L290 TraceCheckUtils]: 2: Hoare triple {13209#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {13209#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:14,505 INFO L290 TraceCheckUtils]: 3: Hoare triple {13209#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {13209#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:14,506 INFO L290 TraceCheckUtils]: 4: Hoare triple {13209#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {13209#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:14,506 INFO L290 TraceCheckUtils]: 5: Hoare triple {13209#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {13209#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:14,506 INFO L290 TraceCheckUtils]: 6: Hoare triple {13209#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {13209#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:14,506 INFO L290 TraceCheckUtils]: 7: Hoare triple {13209#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {13209#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:14,506 INFO L290 TraceCheckUtils]: 8: Hoare triple {13209#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {13209#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 9: Hoare triple {13209#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {13209#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 10: Hoare triple {13209#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {13208#false} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 11: Hoare triple {13208#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {13208#false} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 12: Hoare triple {13208#false} assume !(0 == ~M_E~0); {13208#false} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 13: Hoare triple {13208#false} assume !(0 == ~T1_E~0); {13208#false} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 14: Hoare triple {13208#false} assume !(0 == ~T2_E~0); {13208#false} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 15: Hoare triple {13208#false} assume !(0 == ~T3_E~0); {13208#false} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 16: Hoare triple {13208#false} assume !(0 == ~T4_E~0); {13208#false} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 17: Hoare triple {13208#false} assume !(0 == ~T5_E~0); {13208#false} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 18: Hoare triple {13208#false} assume !(0 == ~T6_E~0); {13208#false} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 19: Hoare triple {13208#false} assume 0 == ~E_1~0;~E_1~0 := 1; {13208#false} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 20: Hoare triple {13208#false} assume !(0 == ~E_2~0); {13208#false} is VALID [2022-02-21 04:24:14,507 INFO L290 TraceCheckUtils]: 21: Hoare triple {13208#false} assume !(0 == ~E_3~0); {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 22: Hoare triple {13208#false} assume !(0 == ~E_4~0); {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 23: Hoare triple {13208#false} assume !(0 == ~E_5~0); {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 24: Hoare triple {13208#false} assume !(0 == ~E_6~0); {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 25: Hoare triple {13208#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 26: Hoare triple {13208#false} assume 1 == ~m_pc~0; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 27: Hoare triple {13208#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 28: Hoare triple {13208#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 29: Hoare triple {13208#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 30: Hoare triple {13208#false} assume !(0 != activate_threads_~tmp~1#1); {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 31: Hoare triple {13208#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 32: Hoare triple {13208#false} assume !(1 == ~t1_pc~0); {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 33: Hoare triple {13208#false} is_transmit1_triggered_~__retres1~1#1 := 0; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 34: Hoare triple {13208#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 35: Hoare triple {13208#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 36: Hoare triple {13208#false} assume !(0 != activate_threads_~tmp___0~0#1); {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 37: Hoare triple {13208#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 38: Hoare triple {13208#false} assume 1 == ~t2_pc~0; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 39: Hoare triple {13208#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {13208#false} is VALID [2022-02-21 04:24:14,508 INFO L290 TraceCheckUtils]: 40: Hoare triple {13208#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 41: Hoare triple {13208#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 42: Hoare triple {13208#false} assume !(0 != activate_threads_~tmp___1~0#1); {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 43: Hoare triple {13208#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 44: Hoare triple {13208#false} assume !(1 == ~t3_pc~0); {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 45: Hoare triple {13208#false} is_transmit3_triggered_~__retres1~3#1 := 0; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 46: Hoare triple {13208#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 47: Hoare triple {13208#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 48: Hoare triple {13208#false} assume !(0 != activate_threads_~tmp___2~0#1); {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 49: Hoare triple {13208#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 50: Hoare triple {13208#false} assume 1 == ~t4_pc~0; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 51: Hoare triple {13208#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 52: Hoare triple {13208#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 53: Hoare triple {13208#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 54: Hoare triple {13208#false} assume !(0 != activate_threads_~tmp___3~0#1); {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 55: Hoare triple {13208#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 56: Hoare triple {13208#false} assume 1 == ~t5_pc~0; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 57: Hoare triple {13208#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 58: Hoare triple {13208#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {13208#false} is VALID [2022-02-21 04:24:14,509 INFO L290 TraceCheckUtils]: 59: Hoare triple {13208#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 60: Hoare triple {13208#false} assume !(0 != activate_threads_~tmp___4~0#1); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 61: Hoare triple {13208#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 62: Hoare triple {13208#false} assume !(1 == ~t6_pc~0); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 63: Hoare triple {13208#false} is_transmit6_triggered_~__retres1~6#1 := 0; {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 64: Hoare triple {13208#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 65: Hoare triple {13208#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 66: Hoare triple {13208#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 67: Hoare triple {13208#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 68: Hoare triple {13208#false} assume !(1 == ~M_E~0); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 69: Hoare triple {13208#false} assume !(1 == ~T1_E~0); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 70: Hoare triple {13208#false} assume !(1 == ~T2_E~0); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 71: Hoare triple {13208#false} assume !(1 == ~T3_E~0); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 72: Hoare triple {13208#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 73: Hoare triple {13208#false} assume !(1 == ~T5_E~0); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 74: Hoare triple {13208#false} assume !(1 == ~T6_E~0); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 75: Hoare triple {13208#false} assume !(1 == ~E_1~0); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 76: Hoare triple {13208#false} assume !(1 == ~E_2~0); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 77: Hoare triple {13208#false} assume !(1 == ~E_3~0); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 78: Hoare triple {13208#false} assume !(1 == ~E_4~0); {13208#false} is VALID [2022-02-21 04:24:14,510 INFO L290 TraceCheckUtils]: 79: Hoare triple {13208#false} assume !(1 == ~E_5~0); {13208#false} is VALID [2022-02-21 04:24:14,511 INFO L290 TraceCheckUtils]: 80: Hoare triple {13208#false} assume 1 == ~E_6~0;~E_6~0 := 2; {13208#false} is VALID [2022-02-21 04:24:14,511 INFO L290 TraceCheckUtils]: 81: Hoare triple {13208#false} assume { :end_inline_reset_delta_events } true; {13208#false} is VALID [2022-02-21 04:24:14,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:14,511 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:14,511 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983013582] [2022-02-21 04:24:14,511 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1983013582] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:14,511 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:14,511 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:14,511 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567522610] [2022-02-21 04:24:14,511 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:14,512 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:14,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:14,512 INFO L85 PathProgramCache]: Analyzing trace with hash 1627578499, now seen corresponding path program 1 times [2022-02-21 04:24:14,512 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:14,512 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3187483] [2022-02-21 04:24:14,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:14,512 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:14,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:14,539 INFO L290 TraceCheckUtils]: 0: Hoare triple {13210#true} assume !false; {13210#true} is VALID [2022-02-21 04:24:14,540 INFO L290 TraceCheckUtils]: 1: Hoare triple {13210#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {13210#true} is VALID [2022-02-21 04:24:14,540 INFO L290 TraceCheckUtils]: 2: Hoare triple {13210#true} assume !false; {13210#true} is VALID [2022-02-21 04:24:14,540 INFO L290 TraceCheckUtils]: 3: Hoare triple {13210#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {13210#true} is VALID [2022-02-21 04:24:14,540 INFO L290 TraceCheckUtils]: 4: Hoare triple {13210#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {13210#true} is VALID [2022-02-21 04:24:14,540 INFO L290 TraceCheckUtils]: 5: Hoare triple {13210#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {13210#true} is VALID [2022-02-21 04:24:14,540 INFO L290 TraceCheckUtils]: 6: Hoare triple {13210#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {13210#true} is VALID [2022-02-21 04:24:14,540 INFO L290 TraceCheckUtils]: 7: Hoare triple {13210#true} assume !(0 != eval_~tmp~0#1); {13210#true} is VALID [2022-02-21 04:24:14,540 INFO L290 TraceCheckUtils]: 8: Hoare triple {13210#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {13210#true} is VALID [2022-02-21 04:24:14,541 INFO L290 TraceCheckUtils]: 9: Hoare triple {13210#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {13210#true} is VALID [2022-02-21 04:24:14,541 INFO L290 TraceCheckUtils]: 10: Hoare triple {13210#true} assume 0 == ~M_E~0;~M_E~0 := 1; {13210#true} is VALID [2022-02-21 04:24:14,541 INFO L290 TraceCheckUtils]: 11: Hoare triple {13210#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {13210#true} is VALID [2022-02-21 04:24:14,541 INFO L290 TraceCheckUtils]: 12: Hoare triple {13210#true} assume !(0 == ~T2_E~0); {13210#true} is VALID [2022-02-21 04:24:14,541 INFO L290 TraceCheckUtils]: 13: Hoare triple {13210#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {13210#true} is VALID [2022-02-21 04:24:14,541 INFO L290 TraceCheckUtils]: 14: Hoare triple {13210#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {13210#true} is VALID [2022-02-21 04:24:14,541 INFO L290 TraceCheckUtils]: 15: Hoare triple {13210#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {13210#true} is VALID [2022-02-21 04:24:14,541 INFO L290 TraceCheckUtils]: 16: Hoare triple {13210#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {13210#true} is VALID [2022-02-21 04:24:14,542 INFO L290 TraceCheckUtils]: 17: Hoare triple {13210#true} assume 0 == ~E_1~0;~E_1~0 := 1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,542 INFO L290 TraceCheckUtils]: 18: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,542 INFO L290 TraceCheckUtils]: 19: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,543 INFO L290 TraceCheckUtils]: 20: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,543 INFO L290 TraceCheckUtils]: 21: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,543 INFO L290 TraceCheckUtils]: 22: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,563 INFO L290 TraceCheckUtils]: 23: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,563 INFO L290 TraceCheckUtils]: 24: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,563 INFO L290 TraceCheckUtils]: 25: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,564 INFO L290 TraceCheckUtils]: 26: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,564 INFO L290 TraceCheckUtils]: 27: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,564 INFO L290 TraceCheckUtils]: 28: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,564 INFO L290 TraceCheckUtils]: 29: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,565 INFO L290 TraceCheckUtils]: 30: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,565 INFO L290 TraceCheckUtils]: 31: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,565 INFO L290 TraceCheckUtils]: 32: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,566 INFO L290 TraceCheckUtils]: 33: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,566 INFO L290 TraceCheckUtils]: 34: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,566 INFO L290 TraceCheckUtils]: 35: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,566 INFO L290 TraceCheckUtils]: 36: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t2_pc~0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,567 INFO L290 TraceCheckUtils]: 37: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,567 INFO L290 TraceCheckUtils]: 38: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,567 INFO L290 TraceCheckUtils]: 39: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,568 INFO L290 TraceCheckUtils]: 40: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,568 INFO L290 TraceCheckUtils]: 41: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,568 INFO L290 TraceCheckUtils]: 42: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t3_pc~0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,568 INFO L290 TraceCheckUtils]: 43: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,569 INFO L290 TraceCheckUtils]: 44: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,569 INFO L290 TraceCheckUtils]: 45: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,569 INFO L290 TraceCheckUtils]: 46: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,570 INFO L290 TraceCheckUtils]: 47: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,570 INFO L290 TraceCheckUtils]: 48: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,570 INFO L290 TraceCheckUtils]: 49: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,570 INFO L290 TraceCheckUtils]: 50: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,571 INFO L290 TraceCheckUtils]: 51: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,571 INFO L290 TraceCheckUtils]: 52: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,571 INFO L290 TraceCheckUtils]: 53: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,571 INFO L290 TraceCheckUtils]: 54: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t5_pc~0); {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,572 INFO L290 TraceCheckUtils]: 55: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,572 INFO L290 TraceCheckUtils]: 56: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,572 INFO L290 TraceCheckUtils]: 57: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,573 INFO L290 TraceCheckUtils]: 58: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,573 INFO L290 TraceCheckUtils]: 59: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,573 INFO L290 TraceCheckUtils]: 60: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t6_pc~0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,573 INFO L290 TraceCheckUtils]: 61: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,574 INFO L290 TraceCheckUtils]: 62: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,574 INFO L290 TraceCheckUtils]: 63: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,574 INFO L290 TraceCheckUtils]: 64: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,575 INFO L290 TraceCheckUtils]: 65: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,575 INFO L290 TraceCheckUtils]: 66: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,575 INFO L290 TraceCheckUtils]: 67: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,575 INFO L290 TraceCheckUtils]: 68: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,576 INFO L290 TraceCheckUtils]: 69: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,576 INFO L290 TraceCheckUtils]: 70: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,576 INFO L290 TraceCheckUtils]: 71: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 72: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {13212#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 73: Hoare triple {13212#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 74: Hoare triple {13211#false} assume 1 == ~E_2~0;~E_2~0 := 2; {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 75: Hoare triple {13211#false} assume 1 == ~E_3~0;~E_3~0 := 2; {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 76: Hoare triple {13211#false} assume 1 == ~E_4~0;~E_4~0 := 2; {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 77: Hoare triple {13211#false} assume 1 == ~E_5~0;~E_5~0 := 2; {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 78: Hoare triple {13211#false} assume 1 == ~E_6~0;~E_6~0 := 2; {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 79: Hoare triple {13211#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 80: Hoare triple {13211#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 81: Hoare triple {13211#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 82: Hoare triple {13211#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 83: Hoare triple {13211#false} assume !(0 == start_simulation_~tmp~3#1); {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 84: Hoare triple {13211#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {13211#false} is VALID [2022-02-21 04:24:14,577 INFO L290 TraceCheckUtils]: 85: Hoare triple {13211#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {13211#false} is VALID [2022-02-21 04:24:14,578 INFO L290 TraceCheckUtils]: 86: Hoare triple {13211#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {13211#false} is VALID [2022-02-21 04:24:14,578 INFO L290 TraceCheckUtils]: 87: Hoare triple {13211#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {13211#false} is VALID [2022-02-21 04:24:14,578 INFO L290 TraceCheckUtils]: 88: Hoare triple {13211#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {13211#false} is VALID [2022-02-21 04:24:14,578 INFO L290 TraceCheckUtils]: 89: Hoare triple {13211#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {13211#false} is VALID [2022-02-21 04:24:14,578 INFO L290 TraceCheckUtils]: 90: Hoare triple {13211#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {13211#false} is VALID [2022-02-21 04:24:14,578 INFO L290 TraceCheckUtils]: 91: Hoare triple {13211#false} assume !(0 != start_simulation_~tmp___0~1#1); {13211#false} is VALID [2022-02-21 04:24:14,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:14,578 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:14,578 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3187483] [2022-02-21 04:24:14,578 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [3187483] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:14,578 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:14,578 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:14,579 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1167459928] [2022-02-21 04:24:14,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:14,579 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:14,579 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:14,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:14,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:14,579 INFO L87 Difference]: Start difference. First operand 626 states and 933 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:14,992 INFO L93 Difference]: Finished difference Result 626 states and 932 transitions. [2022-02-21 04:24:14,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:14,993 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,045 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:15,047 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 626 states and 932 transitions. [2022-02-21 04:24:15,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:15,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 626 states to 626 states and 932 transitions. [2022-02-21 04:24:15,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 626 [2022-02-21 04:24:15,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 626 [2022-02-21 04:24:15,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 626 states and 932 transitions. [2022-02-21 04:24:15,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:15,071 INFO L681 BuchiCegarLoop]: Abstraction has 626 states and 932 transitions. [2022-02-21 04:24:15,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 626 states and 932 transitions. [2022-02-21 04:24:15,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 626 to 626. [2022-02-21 04:24:15,076 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:15,077 INFO L82 GeneralOperation]: Start isEquivalent. First operand 626 states and 932 transitions. Second operand has 626 states, 626 states have (on average 1.488817891373802) internal successors, (932), 625 states have internal predecessors, (932), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,077 INFO L74 IsIncluded]: Start isIncluded. First operand 626 states and 932 transitions. Second operand has 626 states, 626 states have (on average 1.488817891373802) internal successors, (932), 625 states have internal predecessors, (932), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,078 INFO L87 Difference]: Start difference. First operand 626 states and 932 transitions. Second operand has 626 states, 626 states have (on average 1.488817891373802) internal successors, (932), 625 states have internal predecessors, (932), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:15,100 INFO L93 Difference]: Finished difference Result 626 states and 932 transitions. [2022-02-21 04:24:15,100 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 932 transitions. [2022-02-21 04:24:15,100 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:15,100 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:15,102 INFO L74 IsIncluded]: Start isIncluded. First operand has 626 states, 626 states have (on average 1.488817891373802) internal successors, (932), 625 states have internal predecessors, (932), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 932 transitions. [2022-02-21 04:24:15,103 INFO L87 Difference]: Start difference. First operand has 626 states, 626 states have (on average 1.488817891373802) internal successors, (932), 625 states have internal predecessors, (932), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 626 states and 932 transitions. [2022-02-21 04:24:15,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:15,115 INFO L93 Difference]: Finished difference Result 626 states and 932 transitions. [2022-02-21 04:24:15,115 INFO L276 IsEmpty]: Start isEmpty. Operand 626 states and 932 transitions. [2022-02-21 04:24:15,115 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:15,115 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:15,116 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:15,116 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:15,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 626 states, 626 states have (on average 1.488817891373802) internal successors, (932), 625 states have internal predecessors, (932), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 626 states to 626 states and 932 transitions. [2022-02-21 04:24:15,143 INFO L704 BuchiCegarLoop]: Abstraction has 626 states and 932 transitions. [2022-02-21 04:24:15,143 INFO L587 BuchiCegarLoop]: Abstraction has 626 states and 932 transitions. [2022-02-21 04:24:15,143 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:15,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 626 states and 932 transitions. [2022-02-21 04:24:15,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 537 [2022-02-21 04:24:15,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:15,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:15,146 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:15,146 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:15,146 INFO L791 eck$LassoCheckResult]: Stem: 14464#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 14447#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14399#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13843#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13839#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 13840#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14355#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14458#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13935#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13936#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14088#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13953#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13954#L670 assume !(0 == ~M_E~0); 14323#L670-2 assume !(0 == ~T1_E~0); 14271#L675-1 assume !(0 == ~T2_E~0); 14272#L680-1 assume !(0 == ~T3_E~0); 14353#L685-1 assume !(0 == ~T4_E~0); 14327#L690-1 assume !(0 == ~T5_E~0); 14328#L695-1 assume !(0 == ~T6_E~0); 14385#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 14377#L705-1 assume !(0 == ~E_2~0); 14378#L710-1 assume !(0 == ~E_3~0); 14270#L715-1 assume !(0 == ~E_4~0); 14194#L720-1 assume !(0 == ~E_5~0); 14195#L725-1 assume !(0 == ~E_6~0); 14248#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14295#L320 assume 1 == ~m_pc~0; 14236#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14130#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14131#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14089#L825 assume !(0 != activate_threads_~tmp~1#1); 14090#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14096#L339 assume !(1 == ~t1_pc~0); 14097#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14073#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14074#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13955#L833 assume !(0 != activate_threads_~tmp___0~0#1); 13956#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13864#L358 assume 1 == ~t2_pc~0; 13865#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14373#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14324#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14252#L841 assume !(0 != activate_threads_~tmp___1~0#1); 14086#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14087#L377 assume !(1 == ~t3_pc~0); 14339#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 14340#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14338#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14093#L849 assume !(0 != activate_threads_~tmp___2~0#1); 14094#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14041#L396 assume 1 == ~t4_pc~0; 14042#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13867#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13868#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14286#L857 assume !(0 != activate_threads_~tmp___3~0#1); 14008#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14009#L415 assume 1 == ~t5_pc~0; 14076#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14120#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14296#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14403#L865 assume !(0 != activate_threads_~tmp___4~0#1); 13910#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13911#L434 assume !(1 == ~t6_pc~0); 14226#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 14227#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14365#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14366#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14106#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14107#L743 assume !(1 == ~M_E~0); 14000#L743-2 assume !(1 == ~T1_E~0); 14001#L748-1 assume !(1 == ~T2_E~0); 14290#L753-1 assume !(1 == ~T3_E~0); 14291#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14389#L763-1 assume !(1 == ~T5_E~0); 14421#L768-1 assume !(1 == ~T6_E~0); 14104#L773-1 assume !(1 == ~E_1~0); 14105#L778-1 assume !(1 == ~E_2~0); 14081#L783-1 assume !(1 == ~E_3~0); 14082#L788-1 assume !(1 == ~E_4~0); 14351#L793-1 assume !(1 == ~E_5~0); 14316#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 13974#L803-1 assume { :end_inline_reset_delta_events } true; 13975#L1024-2 [2022-02-21 04:24:15,146 INFO L793 eck$LassoCheckResult]: Loop: 13975#L1024-2 assume !false; 14258#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14313#L645 assume !false; 14190#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14191#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13918#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14395#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14430#L556 assume !(0 != eval_~tmp~0#1); 14462#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14372#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13964#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13965#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14125#L675-3 assume !(0 == ~T2_E~0); 14126#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14348#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14349#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14459#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14357#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14358#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14021#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14022#L715-3 assume !(0 == ~E_4~0); 14253#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14254#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14326#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14099#L320-21 assume 1 == ~m_pc~0; 14100#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14251#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14177#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14178#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14412#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14034#L339-21 assume !(1 == ~t1_pc~0); 14035#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 14138#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14010#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13892#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13893#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13992#L358-21 assume !(1 == ~t2_pc~0); 14046#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 13972#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13973#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14257#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14011#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14012#L377-21 assume !(1 == ~t3_pc~0); 14368#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 14284#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14285#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14304#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14149#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14150#L396-21 assume 1 == ~t4_pc~0; 14317#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14176#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14147#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13874#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 13875#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14127#L415-21 assume 1 == ~t5_pc~0; 14128#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14103#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13996#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13997#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14197#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14198#L434-21 assume 1 == ~t6_pc~0; 14209#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13900#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14401#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14121#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14122#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14116#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14117#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14437#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14279#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14217#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14140#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14141#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14425#L773-3 assume !(1 == ~E_1~0); 14059#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14060#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14282#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14449#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14450#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14322#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14050#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13946#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14210#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 14211#L1043 assume !(0 == start_simulation_~tmp~3#1); 14404#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14280#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14068#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14250#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 14238#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13960#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13961#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 14108#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 13975#L1024-2 [2022-02-21 04:24:15,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:15,147 INFO L85 PathProgramCache]: Analyzing trace with hash -559378915, now seen corresponding path program 1 times [2022-02-21 04:24:15,147 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:15,147 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179244529] [2022-02-21 04:24:15,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:15,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:15,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:15,170 INFO L290 TraceCheckUtils]: 0: Hoare triple {15720#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,170 INFO L290 TraceCheckUtils]: 1: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,171 INFO L290 TraceCheckUtils]: 2: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,171 INFO L290 TraceCheckUtils]: 3: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,171 INFO L290 TraceCheckUtils]: 4: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,171 INFO L290 TraceCheckUtils]: 5: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,172 INFO L290 TraceCheckUtils]: 6: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,172 INFO L290 TraceCheckUtils]: 7: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,172 INFO L290 TraceCheckUtils]: 8: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,172 INFO L290 TraceCheckUtils]: 9: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,173 INFO L290 TraceCheckUtils]: 10: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,173 INFO L290 TraceCheckUtils]: 11: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,173 INFO L290 TraceCheckUtils]: 12: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~M_E~0); {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,173 INFO L290 TraceCheckUtils]: 13: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~T1_E~0); {15722#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:15,174 INFO L290 TraceCheckUtils]: 14: Hoare triple {15722#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~T2_E~0); {15723#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:15,174 INFO L290 TraceCheckUtils]: 15: Hoare triple {15723#(not (= ~E_1~0 0))} assume !(0 == ~T3_E~0); {15723#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:15,174 INFO L290 TraceCheckUtils]: 16: Hoare triple {15723#(not (= ~E_1~0 0))} assume !(0 == ~T4_E~0); {15723#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:15,174 INFO L290 TraceCheckUtils]: 17: Hoare triple {15723#(not (= ~E_1~0 0))} assume !(0 == ~T5_E~0); {15723#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 18: Hoare triple {15723#(not (= ~E_1~0 0))} assume !(0 == ~T6_E~0); {15723#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 19: Hoare triple {15723#(not (= ~E_1~0 0))} assume 0 == ~E_1~0;~E_1~0 := 1; {15721#false} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 20: Hoare triple {15721#false} assume !(0 == ~E_2~0); {15721#false} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 21: Hoare triple {15721#false} assume !(0 == ~E_3~0); {15721#false} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 22: Hoare triple {15721#false} assume !(0 == ~E_4~0); {15721#false} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 23: Hoare triple {15721#false} assume !(0 == ~E_5~0); {15721#false} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 24: Hoare triple {15721#false} assume !(0 == ~E_6~0); {15721#false} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 25: Hoare triple {15721#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {15721#false} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 26: Hoare triple {15721#false} assume 1 == ~m_pc~0; {15721#false} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 27: Hoare triple {15721#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {15721#false} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 28: Hoare triple {15721#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {15721#false} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 29: Hoare triple {15721#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {15721#false} is VALID [2022-02-21 04:24:15,175 INFO L290 TraceCheckUtils]: 30: Hoare triple {15721#false} assume !(0 != activate_threads_~tmp~1#1); {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 31: Hoare triple {15721#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 32: Hoare triple {15721#false} assume !(1 == ~t1_pc~0); {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 33: Hoare triple {15721#false} is_transmit1_triggered_~__retres1~1#1 := 0; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 34: Hoare triple {15721#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 35: Hoare triple {15721#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 36: Hoare triple {15721#false} assume !(0 != activate_threads_~tmp___0~0#1); {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 37: Hoare triple {15721#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 38: Hoare triple {15721#false} assume 1 == ~t2_pc~0; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 39: Hoare triple {15721#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 40: Hoare triple {15721#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 41: Hoare triple {15721#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 42: Hoare triple {15721#false} assume !(0 != activate_threads_~tmp___1~0#1); {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 43: Hoare triple {15721#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 44: Hoare triple {15721#false} assume !(1 == ~t3_pc~0); {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 45: Hoare triple {15721#false} is_transmit3_triggered_~__retres1~3#1 := 0; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 46: Hoare triple {15721#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 47: Hoare triple {15721#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 48: Hoare triple {15721#false} assume !(0 != activate_threads_~tmp___2~0#1); {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 49: Hoare triple {15721#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 50: Hoare triple {15721#false} assume 1 == ~t4_pc~0; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 51: Hoare triple {15721#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {15721#false} is VALID [2022-02-21 04:24:15,176 INFO L290 TraceCheckUtils]: 52: Hoare triple {15721#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 53: Hoare triple {15721#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 54: Hoare triple {15721#false} assume !(0 != activate_threads_~tmp___3~0#1); {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 55: Hoare triple {15721#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 56: Hoare triple {15721#false} assume 1 == ~t5_pc~0; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 57: Hoare triple {15721#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 58: Hoare triple {15721#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 59: Hoare triple {15721#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 60: Hoare triple {15721#false} assume !(0 != activate_threads_~tmp___4~0#1); {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 61: Hoare triple {15721#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 62: Hoare triple {15721#false} assume !(1 == ~t6_pc~0); {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 63: Hoare triple {15721#false} is_transmit6_triggered_~__retres1~6#1 := 0; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 64: Hoare triple {15721#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 65: Hoare triple {15721#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 66: Hoare triple {15721#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 67: Hoare triple {15721#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 68: Hoare triple {15721#false} assume !(1 == ~M_E~0); {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 69: Hoare triple {15721#false} assume !(1 == ~T1_E~0); {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 70: Hoare triple {15721#false} assume !(1 == ~T2_E~0); {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 71: Hoare triple {15721#false} assume !(1 == ~T3_E~0); {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 72: Hoare triple {15721#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {15721#false} is VALID [2022-02-21 04:24:15,177 INFO L290 TraceCheckUtils]: 73: Hoare triple {15721#false} assume !(1 == ~T5_E~0); {15721#false} is VALID [2022-02-21 04:24:15,178 INFO L290 TraceCheckUtils]: 74: Hoare triple {15721#false} assume !(1 == ~T6_E~0); {15721#false} is VALID [2022-02-21 04:24:15,178 INFO L290 TraceCheckUtils]: 75: Hoare triple {15721#false} assume !(1 == ~E_1~0); {15721#false} is VALID [2022-02-21 04:24:15,178 INFO L290 TraceCheckUtils]: 76: Hoare triple {15721#false} assume !(1 == ~E_2~0); {15721#false} is VALID [2022-02-21 04:24:15,178 INFO L290 TraceCheckUtils]: 77: Hoare triple {15721#false} assume !(1 == ~E_3~0); {15721#false} is VALID [2022-02-21 04:24:15,178 INFO L290 TraceCheckUtils]: 78: Hoare triple {15721#false} assume !(1 == ~E_4~0); {15721#false} is VALID [2022-02-21 04:24:15,178 INFO L290 TraceCheckUtils]: 79: Hoare triple {15721#false} assume !(1 == ~E_5~0); {15721#false} is VALID [2022-02-21 04:24:15,178 INFO L290 TraceCheckUtils]: 80: Hoare triple {15721#false} assume 1 == ~E_6~0;~E_6~0 := 2; {15721#false} is VALID [2022-02-21 04:24:15,178 INFO L290 TraceCheckUtils]: 81: Hoare triple {15721#false} assume { :end_inline_reset_delta_events } true; {15721#false} is VALID [2022-02-21 04:24:15,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:15,178 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:15,178 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1179244529] [2022-02-21 04:24:15,178 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1179244529] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:15,178 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:15,178 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:15,178 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019607166] [2022-02-21 04:24:15,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:15,179 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:15,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:15,179 INFO L85 PathProgramCache]: Analyzing trace with hash -618328670, now seen corresponding path program 1 times [2022-02-21 04:24:15,179 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:15,179 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1931472754] [2022-02-21 04:24:15,179 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:15,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:15,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:15,200 INFO L290 TraceCheckUtils]: 0: Hoare triple {15724#true} assume !false; {15724#true} is VALID [2022-02-21 04:24:15,200 INFO L290 TraceCheckUtils]: 1: Hoare triple {15724#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {15724#true} is VALID [2022-02-21 04:24:15,200 INFO L290 TraceCheckUtils]: 2: Hoare triple {15724#true} assume !false; {15724#true} is VALID [2022-02-21 04:24:15,200 INFO L290 TraceCheckUtils]: 3: Hoare triple {15724#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {15724#true} is VALID [2022-02-21 04:24:15,200 INFO L290 TraceCheckUtils]: 4: Hoare triple {15724#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {15724#true} is VALID [2022-02-21 04:24:15,200 INFO L290 TraceCheckUtils]: 5: Hoare triple {15724#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {15724#true} is VALID [2022-02-21 04:24:15,200 INFO L290 TraceCheckUtils]: 6: Hoare triple {15724#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {15724#true} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 7: Hoare triple {15724#true} assume !(0 != eval_~tmp~0#1); {15724#true} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 8: Hoare triple {15724#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {15724#true} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 9: Hoare triple {15724#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {15724#true} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 10: Hoare triple {15724#true} assume 0 == ~M_E~0;~M_E~0 := 1; {15724#true} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 11: Hoare triple {15724#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {15724#true} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 12: Hoare triple {15724#true} assume !(0 == ~T2_E~0); {15724#true} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 13: Hoare triple {15724#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {15724#true} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 14: Hoare triple {15724#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {15724#true} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 15: Hoare triple {15724#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {15724#true} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 16: Hoare triple {15724#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {15724#true} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 17: Hoare triple {15724#true} assume 0 == ~E_1~0;~E_1~0 := 1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,201 INFO L290 TraceCheckUtils]: 18: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,202 INFO L290 TraceCheckUtils]: 19: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,202 INFO L290 TraceCheckUtils]: 20: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,202 INFO L290 TraceCheckUtils]: 21: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,203 INFO L290 TraceCheckUtils]: 22: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,203 INFO L290 TraceCheckUtils]: 23: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,203 INFO L290 TraceCheckUtils]: 24: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,203 INFO L290 TraceCheckUtils]: 25: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,204 INFO L290 TraceCheckUtils]: 26: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,204 INFO L290 TraceCheckUtils]: 27: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,204 INFO L290 TraceCheckUtils]: 28: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,205 INFO L290 TraceCheckUtils]: 29: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,205 INFO L290 TraceCheckUtils]: 30: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,205 INFO L290 TraceCheckUtils]: 31: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,205 INFO L290 TraceCheckUtils]: 32: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,206 INFO L290 TraceCheckUtils]: 33: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,206 INFO L290 TraceCheckUtils]: 34: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,206 INFO L290 TraceCheckUtils]: 35: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,206 INFO L290 TraceCheckUtils]: 36: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t2_pc~0); {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,207 INFO L290 TraceCheckUtils]: 37: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,207 INFO L290 TraceCheckUtils]: 38: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,207 INFO L290 TraceCheckUtils]: 39: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,208 INFO L290 TraceCheckUtils]: 40: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,208 INFO L290 TraceCheckUtils]: 41: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,208 INFO L290 TraceCheckUtils]: 42: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t3_pc~0); {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,208 INFO L290 TraceCheckUtils]: 43: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,209 INFO L290 TraceCheckUtils]: 44: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,209 INFO L290 TraceCheckUtils]: 45: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,209 INFO L290 TraceCheckUtils]: 46: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,209 INFO L290 TraceCheckUtils]: 47: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,210 INFO L290 TraceCheckUtils]: 48: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,210 INFO L290 TraceCheckUtils]: 49: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,210 INFO L290 TraceCheckUtils]: 50: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,211 INFO L290 TraceCheckUtils]: 51: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,211 INFO L290 TraceCheckUtils]: 52: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,211 INFO L290 TraceCheckUtils]: 53: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,211 INFO L290 TraceCheckUtils]: 54: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t5_pc~0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,212 INFO L290 TraceCheckUtils]: 55: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,212 INFO L290 TraceCheckUtils]: 56: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,212 INFO L290 TraceCheckUtils]: 57: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,212 INFO L290 TraceCheckUtils]: 58: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,213 INFO L290 TraceCheckUtils]: 59: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,213 INFO L290 TraceCheckUtils]: 60: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t6_pc~0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,213 INFO L290 TraceCheckUtils]: 61: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,214 INFO L290 TraceCheckUtils]: 62: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,214 INFO L290 TraceCheckUtils]: 63: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,214 INFO L290 TraceCheckUtils]: 64: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,214 INFO L290 TraceCheckUtils]: 65: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,215 INFO L290 TraceCheckUtils]: 66: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,215 INFO L290 TraceCheckUtils]: 67: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,215 INFO L290 TraceCheckUtils]: 68: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,215 INFO L290 TraceCheckUtils]: 69: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,216 INFO L290 TraceCheckUtils]: 70: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,216 INFO L290 TraceCheckUtils]: 71: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,216 INFO L290 TraceCheckUtils]: 72: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {15726#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 73: Hoare triple {15726#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 74: Hoare triple {15725#false} assume 1 == ~E_2~0;~E_2~0 := 2; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 75: Hoare triple {15725#false} assume 1 == ~E_3~0;~E_3~0 := 2; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 76: Hoare triple {15725#false} assume 1 == ~E_4~0;~E_4~0 := 2; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 77: Hoare triple {15725#false} assume 1 == ~E_5~0;~E_5~0 := 2; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 78: Hoare triple {15725#false} assume 1 == ~E_6~0;~E_6~0 := 2; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 79: Hoare triple {15725#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 80: Hoare triple {15725#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 81: Hoare triple {15725#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 82: Hoare triple {15725#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 83: Hoare triple {15725#false} assume !(0 == start_simulation_~tmp~3#1); {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 84: Hoare triple {15725#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 85: Hoare triple {15725#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 86: Hoare triple {15725#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 87: Hoare triple {15725#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 88: Hoare triple {15725#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 89: Hoare triple {15725#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 90: Hoare triple {15725#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {15725#false} is VALID [2022-02-21 04:24:15,217 INFO L290 TraceCheckUtils]: 91: Hoare triple {15725#false} assume !(0 != start_simulation_~tmp___0~1#1); {15725#false} is VALID [2022-02-21 04:24:15,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:15,218 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:15,218 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1931472754] [2022-02-21 04:24:15,218 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1931472754] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:15,218 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:15,218 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:15,218 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1718786835] [2022-02-21 04:24:15,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:15,218 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:15,218 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:15,219 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:15,219 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:15,219 INFO L87 Difference]: Start difference. First operand 626 states and 932 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:16,352 INFO L93 Difference]: Finished difference Result 1124 states and 1672 transitions. [2022-02-21 04:24:16,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:16,353 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,398 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:16,399 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1124 states and 1672 transitions. [2022-02-21 04:24:16,431 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1022 [2022-02-21 04:24:16,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1124 states to 1124 states and 1672 transitions. [2022-02-21 04:24:16,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1124 [2022-02-21 04:24:16,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1124 [2022-02-21 04:24:16,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1124 states and 1672 transitions. [2022-02-21 04:24:16,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:16,497 INFO L681 BuchiCegarLoop]: Abstraction has 1124 states and 1672 transitions. [2022-02-21 04:24:16,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1124 states and 1672 transitions. [2022-02-21 04:24:16,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1124 to 1122. [2022-02-21 04:24:16,509 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:16,511 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1124 states and 1672 transitions. Second operand has 1122 states, 1122 states have (on average 1.4884135472370768) internal successors, (1670), 1121 states have internal predecessors, (1670), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,512 INFO L74 IsIncluded]: Start isIncluded. First operand 1124 states and 1672 transitions. Second operand has 1122 states, 1122 states have (on average 1.4884135472370768) internal successors, (1670), 1121 states have internal predecessors, (1670), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,513 INFO L87 Difference]: Start difference. First operand 1124 states and 1672 transitions. Second operand has 1122 states, 1122 states have (on average 1.4884135472370768) internal successors, (1670), 1121 states have internal predecessors, (1670), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:16,546 INFO L93 Difference]: Finished difference Result 1124 states and 1672 transitions. [2022-02-21 04:24:16,546 INFO L276 IsEmpty]: Start isEmpty. Operand 1124 states and 1672 transitions. [2022-02-21 04:24:16,547 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:16,547 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:16,549 INFO L74 IsIncluded]: Start isIncluded. First operand has 1122 states, 1122 states have (on average 1.4884135472370768) internal successors, (1670), 1121 states have internal predecessors, (1670), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1124 states and 1672 transitions. [2022-02-21 04:24:16,550 INFO L87 Difference]: Start difference. First operand has 1122 states, 1122 states have (on average 1.4884135472370768) internal successors, (1670), 1121 states have internal predecessors, (1670), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1124 states and 1672 transitions. [2022-02-21 04:24:16,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:16,581 INFO L93 Difference]: Finished difference Result 1124 states and 1672 transitions. [2022-02-21 04:24:16,581 INFO L276 IsEmpty]: Start isEmpty. Operand 1124 states and 1672 transitions. [2022-02-21 04:24:16,583 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:16,583 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:16,583 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:16,583 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:16,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1122 states, 1122 states have (on average 1.4884135472370768) internal successors, (1670), 1121 states have internal predecessors, (1670), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1122 states to 1122 states and 1670 transitions. [2022-02-21 04:24:16,615 INFO L704 BuchiCegarLoop]: Abstraction has 1122 states and 1670 transitions. [2022-02-21 04:24:16,615 INFO L587 BuchiCegarLoop]: Abstraction has 1122 states and 1670 transitions. [2022-02-21 04:24:16,615 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:16,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1122 states and 1670 transitions. [2022-02-21 04:24:16,619 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1022 [2022-02-21 04:24:16,619 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:16,619 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:16,620 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:16,620 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:16,620 INFO L791 eck$LassoCheckResult]: Stem: 17505#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 17481#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 17419#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16857#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16853#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 16854#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17373#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17496#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16949#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16950#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17102#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16966#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16967#L670 assume !(0 == ~M_E~0); 17340#L670-2 assume !(0 == ~T1_E~0); 17287#L675-1 assume !(0 == ~T2_E~0); 17288#L680-1 assume !(0 == ~T3_E~0); 17371#L685-1 assume !(0 == ~T4_E~0); 17343#L690-1 assume !(0 == ~T5_E~0); 17344#L695-1 assume !(0 == ~T6_E~0); 17403#L700-1 assume !(0 == ~E_1~0); 17395#L705-1 assume !(0 == ~E_2~0); 17396#L710-1 assume !(0 == ~E_3~0); 17286#L715-1 assume !(0 == ~E_4~0); 17210#L720-1 assume !(0 == ~E_5~0); 17211#L725-1 assume !(0 == ~E_6~0); 17264#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17312#L320 assume 1 == ~m_pc~0; 17252#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17144#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17145#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17103#L825 assume !(0 != activate_threads_~tmp~1#1); 17104#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17109#L339 assume !(1 == ~t1_pc~0); 17110#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17087#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17088#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16969#L833 assume !(0 != activate_threads_~tmp___0~0#1); 16970#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16878#L358 assume 1 == ~t2_pc~0; 16879#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17391#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17341#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17268#L841 assume !(0 != activate_threads_~tmp___1~0#1); 17100#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17101#L377 assume !(1 == ~t3_pc~0); 17356#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17357#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17352#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17107#L849 assume !(0 != activate_threads_~tmp___2~0#1); 17108#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17053#L396 assume 1 == ~t4_pc~0; 17054#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16881#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16882#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17303#L857 assume !(0 != activate_threads_~tmp___3~0#1); 17022#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17023#L415 assume 1 == ~t5_pc~0; 17089#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17134#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17313#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17423#L865 assume !(0 != activate_threads_~tmp___4~0#1); 16924#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16925#L434 assume !(1 == ~t6_pc~0); 17241#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17242#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17383#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17384#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17120#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17121#L743 assume !(1 == ~M_E~0); 17014#L743-2 assume !(1 == ~T1_E~0); 17015#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17306#L753-1 assume !(1 == ~T3_E~0); 17307#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17407#L763-1 assume !(1 == ~T5_E~0); 17446#L768-1 assume !(1 == ~T6_E~0); 17115#L773-1 assume !(1 == ~E_1~0); 17116#L778-1 assume !(1 == ~E_2~0); 17095#L783-1 assume !(1 == ~E_3~0); 17096#L788-1 assume !(1 == ~E_4~0); 17369#L793-1 assume !(1 == ~E_5~0); 17333#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 16986#L803-1 assume { :end_inline_reset_delta_events } true; 16987#L1024-2 [2022-02-21 04:24:16,620 INFO L793 eck$LassoCheckResult]: Loop: 16987#L1024-2 assume !false; 17274#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17447#L645 assume !false; 17206#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 17207#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 16932#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17415#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17513#L556 assume !(0 != eval_~tmp~0#1); 17512#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17511#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17510#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17509#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17507#L675-3 assume !(0 == ~T2_E~0); 17508#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17889#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17888#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17887#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17886#L700-3 assume !(0 == ~E_1~0); 17885#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17884#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17883#L715-3 assume !(0 == ~E_4~0); 17882#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17881#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17880#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17879#L320-21 assume 1 == ~m_pc~0; 17877#L321-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17876#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17875#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17874#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17873#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17872#L339-21 assume !(1 == ~t1_pc~0); 17870#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 17869#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17836#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17835#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17834#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17833#L358-21 assume 1 == ~t2_pc~0; 17831#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17830#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17829#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17828#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17827#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17826#L377-21 assume !(1 == ~t3_pc~0); 17824#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 17823#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17822#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17820#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17818#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17816#L396-21 assume 1 == ~t4_pc~0; 17813#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17812#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17811#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17809#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 17808#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17807#L415-21 assume 1 == ~t5_pc~0; 17805#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17804#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17803#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17802#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17801#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17800#L434-21 assume !(1 == ~t6_pc~0); 17798#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 17797#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17795#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17792#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17790#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17788#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17786#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17784#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17495#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17780#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17778#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17763#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17762#L773-3 assume !(1 == ~E_1~0); 17452#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17760#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17759#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17758#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17757#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17756#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 17752#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 17748#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17747#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 17746#L1043 assume !(0 == start_simulation_~tmp~3#1); 17424#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 17296#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 17081#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17265#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 17254#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16974#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16975#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 17122#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 16987#L1024-2 [2022-02-21 04:24:16,621 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:16,621 INFO L85 PathProgramCache]: Analyzing trace with hash -1234940959, now seen corresponding path program 1 times [2022-02-21 04:24:16,621 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:16,621 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355470684] [2022-02-21 04:24:16,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:16,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:16,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:16,648 INFO L290 TraceCheckUtils]: 0: Hoare triple {20226#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,649 INFO L290 TraceCheckUtils]: 1: Hoare triple {20228#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,649 INFO L290 TraceCheckUtils]: 2: Hoare triple {20228#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,649 INFO L290 TraceCheckUtils]: 3: Hoare triple {20228#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,650 INFO L290 TraceCheckUtils]: 4: Hoare triple {20228#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,650 INFO L290 TraceCheckUtils]: 5: Hoare triple {20228#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,650 INFO L290 TraceCheckUtils]: 6: Hoare triple {20228#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,650 INFO L290 TraceCheckUtils]: 7: Hoare triple {20228#(= ~m_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,651 INFO L290 TraceCheckUtils]: 8: Hoare triple {20228#(= ~m_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,651 INFO L290 TraceCheckUtils]: 9: Hoare triple {20228#(= ~m_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,651 INFO L290 TraceCheckUtils]: 10: Hoare triple {20228#(= ~m_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,651 INFO L290 TraceCheckUtils]: 11: Hoare triple {20228#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,652 INFO L290 TraceCheckUtils]: 12: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,652 INFO L290 TraceCheckUtils]: 13: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,652 INFO L290 TraceCheckUtils]: 14: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,652 INFO L290 TraceCheckUtils]: 15: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~T3_E~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,653 INFO L290 TraceCheckUtils]: 16: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~T4_E~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,653 INFO L290 TraceCheckUtils]: 17: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~T5_E~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,653 INFO L290 TraceCheckUtils]: 18: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~T6_E~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,653 INFO L290 TraceCheckUtils]: 19: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,654 INFO L290 TraceCheckUtils]: 20: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,654 INFO L290 TraceCheckUtils]: 21: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~E_3~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,654 INFO L290 TraceCheckUtils]: 22: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~E_4~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,654 INFO L290 TraceCheckUtils]: 23: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~E_5~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,655 INFO L290 TraceCheckUtils]: 24: Hoare triple {20228#(= ~m_pc~0 0)} assume !(0 == ~E_6~0); {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,655 INFO L290 TraceCheckUtils]: 25: Hoare triple {20228#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20228#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:16,655 INFO L290 TraceCheckUtils]: 26: Hoare triple {20228#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {20227#false} is VALID [2022-02-21 04:24:16,655 INFO L290 TraceCheckUtils]: 27: Hoare triple {20227#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {20227#false} is VALID [2022-02-21 04:24:16,655 INFO L290 TraceCheckUtils]: 28: Hoare triple {20227#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20227#false} is VALID [2022-02-21 04:24:16,655 INFO L290 TraceCheckUtils]: 29: Hoare triple {20227#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {20227#false} is VALID [2022-02-21 04:24:16,656 INFO L290 TraceCheckUtils]: 30: Hoare triple {20227#false} assume !(0 != activate_threads_~tmp~1#1); {20227#false} is VALID [2022-02-21 04:24:16,656 INFO L290 TraceCheckUtils]: 31: Hoare triple {20227#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20227#false} is VALID [2022-02-21 04:24:16,656 INFO L290 TraceCheckUtils]: 32: Hoare triple {20227#false} assume !(1 == ~t1_pc~0); {20227#false} is VALID [2022-02-21 04:24:16,656 INFO L290 TraceCheckUtils]: 33: Hoare triple {20227#false} is_transmit1_triggered_~__retres1~1#1 := 0; {20227#false} is VALID [2022-02-21 04:24:16,656 INFO L290 TraceCheckUtils]: 34: Hoare triple {20227#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20227#false} is VALID [2022-02-21 04:24:16,656 INFO L290 TraceCheckUtils]: 35: Hoare triple {20227#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {20227#false} is VALID [2022-02-21 04:24:16,656 INFO L290 TraceCheckUtils]: 36: Hoare triple {20227#false} assume !(0 != activate_threads_~tmp___0~0#1); {20227#false} is VALID [2022-02-21 04:24:16,656 INFO L290 TraceCheckUtils]: 37: Hoare triple {20227#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20227#false} is VALID [2022-02-21 04:24:16,656 INFO L290 TraceCheckUtils]: 38: Hoare triple {20227#false} assume 1 == ~t2_pc~0; {20227#false} is VALID [2022-02-21 04:24:16,656 INFO L290 TraceCheckUtils]: 39: Hoare triple {20227#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {20227#false} is VALID [2022-02-21 04:24:16,657 INFO L290 TraceCheckUtils]: 40: Hoare triple {20227#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20227#false} is VALID [2022-02-21 04:24:16,657 INFO L290 TraceCheckUtils]: 41: Hoare triple {20227#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {20227#false} is VALID [2022-02-21 04:24:16,657 INFO L290 TraceCheckUtils]: 42: Hoare triple {20227#false} assume !(0 != activate_threads_~tmp___1~0#1); {20227#false} is VALID [2022-02-21 04:24:16,657 INFO L290 TraceCheckUtils]: 43: Hoare triple {20227#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20227#false} is VALID [2022-02-21 04:24:16,657 INFO L290 TraceCheckUtils]: 44: Hoare triple {20227#false} assume !(1 == ~t3_pc~0); {20227#false} is VALID [2022-02-21 04:24:16,657 INFO L290 TraceCheckUtils]: 45: Hoare triple {20227#false} is_transmit3_triggered_~__retres1~3#1 := 0; {20227#false} is VALID [2022-02-21 04:24:16,657 INFO L290 TraceCheckUtils]: 46: Hoare triple {20227#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20227#false} is VALID [2022-02-21 04:24:16,657 INFO L290 TraceCheckUtils]: 47: Hoare triple {20227#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {20227#false} is VALID [2022-02-21 04:24:16,658 INFO L290 TraceCheckUtils]: 48: Hoare triple {20227#false} assume !(0 != activate_threads_~tmp___2~0#1); {20227#false} is VALID [2022-02-21 04:24:16,658 INFO L290 TraceCheckUtils]: 49: Hoare triple {20227#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20227#false} is VALID [2022-02-21 04:24:16,658 INFO L290 TraceCheckUtils]: 50: Hoare triple {20227#false} assume 1 == ~t4_pc~0; {20227#false} is VALID [2022-02-21 04:24:16,658 INFO L290 TraceCheckUtils]: 51: Hoare triple {20227#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {20227#false} is VALID [2022-02-21 04:24:16,658 INFO L290 TraceCheckUtils]: 52: Hoare triple {20227#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20227#false} is VALID [2022-02-21 04:24:16,658 INFO L290 TraceCheckUtils]: 53: Hoare triple {20227#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {20227#false} is VALID [2022-02-21 04:24:16,658 INFO L290 TraceCheckUtils]: 54: Hoare triple {20227#false} assume !(0 != activate_threads_~tmp___3~0#1); {20227#false} is VALID [2022-02-21 04:24:16,658 INFO L290 TraceCheckUtils]: 55: Hoare triple {20227#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20227#false} is VALID [2022-02-21 04:24:16,659 INFO L290 TraceCheckUtils]: 56: Hoare triple {20227#false} assume 1 == ~t5_pc~0; {20227#false} is VALID [2022-02-21 04:24:16,659 INFO L290 TraceCheckUtils]: 57: Hoare triple {20227#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {20227#false} is VALID [2022-02-21 04:24:16,659 INFO L290 TraceCheckUtils]: 58: Hoare triple {20227#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20227#false} is VALID [2022-02-21 04:24:16,659 INFO L290 TraceCheckUtils]: 59: Hoare triple {20227#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {20227#false} is VALID [2022-02-21 04:24:16,659 INFO L290 TraceCheckUtils]: 60: Hoare triple {20227#false} assume !(0 != activate_threads_~tmp___4~0#1); {20227#false} is VALID [2022-02-21 04:24:16,659 INFO L290 TraceCheckUtils]: 61: Hoare triple {20227#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {20227#false} is VALID [2022-02-21 04:24:16,659 INFO L290 TraceCheckUtils]: 62: Hoare triple {20227#false} assume !(1 == ~t6_pc~0); {20227#false} is VALID [2022-02-21 04:24:16,659 INFO L290 TraceCheckUtils]: 63: Hoare triple {20227#false} is_transmit6_triggered_~__retres1~6#1 := 0; {20227#false} is VALID [2022-02-21 04:24:16,660 INFO L290 TraceCheckUtils]: 64: Hoare triple {20227#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {20227#false} is VALID [2022-02-21 04:24:16,660 INFO L290 TraceCheckUtils]: 65: Hoare triple {20227#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {20227#false} is VALID [2022-02-21 04:24:16,660 INFO L290 TraceCheckUtils]: 66: Hoare triple {20227#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {20227#false} is VALID [2022-02-21 04:24:16,660 INFO L290 TraceCheckUtils]: 67: Hoare triple {20227#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20227#false} is VALID [2022-02-21 04:24:16,660 INFO L290 TraceCheckUtils]: 68: Hoare triple {20227#false} assume !(1 == ~M_E~0); {20227#false} is VALID [2022-02-21 04:24:16,660 INFO L290 TraceCheckUtils]: 69: Hoare triple {20227#false} assume !(1 == ~T1_E~0); {20227#false} is VALID [2022-02-21 04:24:16,660 INFO L290 TraceCheckUtils]: 70: Hoare triple {20227#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {20227#false} is VALID [2022-02-21 04:24:16,660 INFO L290 TraceCheckUtils]: 71: Hoare triple {20227#false} assume !(1 == ~T3_E~0); {20227#false} is VALID [2022-02-21 04:24:16,661 INFO L290 TraceCheckUtils]: 72: Hoare triple {20227#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {20227#false} is VALID [2022-02-21 04:24:16,661 INFO L290 TraceCheckUtils]: 73: Hoare triple {20227#false} assume !(1 == ~T5_E~0); {20227#false} is VALID [2022-02-21 04:24:16,661 INFO L290 TraceCheckUtils]: 74: Hoare triple {20227#false} assume !(1 == ~T6_E~0); {20227#false} is VALID [2022-02-21 04:24:16,661 INFO L290 TraceCheckUtils]: 75: Hoare triple {20227#false} assume !(1 == ~E_1~0); {20227#false} is VALID [2022-02-21 04:24:16,661 INFO L290 TraceCheckUtils]: 76: Hoare triple {20227#false} assume !(1 == ~E_2~0); {20227#false} is VALID [2022-02-21 04:24:16,661 INFO L290 TraceCheckUtils]: 77: Hoare triple {20227#false} assume !(1 == ~E_3~0); {20227#false} is VALID [2022-02-21 04:24:16,661 INFO L290 TraceCheckUtils]: 78: Hoare triple {20227#false} assume !(1 == ~E_4~0); {20227#false} is VALID [2022-02-21 04:24:16,661 INFO L290 TraceCheckUtils]: 79: Hoare triple {20227#false} assume !(1 == ~E_5~0); {20227#false} is VALID [2022-02-21 04:24:16,662 INFO L290 TraceCheckUtils]: 80: Hoare triple {20227#false} assume 1 == ~E_6~0;~E_6~0 := 2; {20227#false} is VALID [2022-02-21 04:24:16,662 INFO L290 TraceCheckUtils]: 81: Hoare triple {20227#false} assume { :end_inline_reset_delta_events } true; {20227#false} is VALID [2022-02-21 04:24:16,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:16,662 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:16,662 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355470684] [2022-02-21 04:24:16,663 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355470684] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:16,664 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:16,664 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:16,664 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374975378] [2022-02-21 04:24:16,664 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:16,665 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:16,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:16,665 INFO L85 PathProgramCache]: Analyzing trace with hash 2026999844, now seen corresponding path program 1 times [2022-02-21 04:24:16,665 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:16,669 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63986738] [2022-02-21 04:24:16,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:16,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:16,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:16,698 INFO L290 TraceCheckUtils]: 0: Hoare triple {20229#true} assume !false; {20229#true} is VALID [2022-02-21 04:24:16,699 INFO L290 TraceCheckUtils]: 1: Hoare triple {20229#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {20229#true} is VALID [2022-02-21 04:24:16,699 INFO L290 TraceCheckUtils]: 2: Hoare triple {20229#true} assume !false; {20229#true} is VALID [2022-02-21 04:24:16,699 INFO L290 TraceCheckUtils]: 3: Hoare triple {20229#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {20229#true} is VALID [2022-02-21 04:24:16,699 INFO L290 TraceCheckUtils]: 4: Hoare triple {20229#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {20231#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~7#1|)} is VALID [2022-02-21 04:24:16,700 INFO L290 TraceCheckUtils]: 5: Hoare triple {20231#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~7#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {20232#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:16,700 INFO L290 TraceCheckUtils]: 6: Hoare triple {20232#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {20233#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:16,700 INFO L290 TraceCheckUtils]: 7: Hoare triple {20233#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {20230#false} is VALID [2022-02-21 04:24:16,700 INFO L290 TraceCheckUtils]: 8: Hoare triple {20230#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {20230#false} is VALID [2022-02-21 04:24:16,700 INFO L290 TraceCheckUtils]: 9: Hoare triple {20230#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {20230#false} is VALID [2022-02-21 04:24:16,701 INFO L290 TraceCheckUtils]: 10: Hoare triple {20230#false} assume 0 == ~M_E~0;~M_E~0 := 1; {20230#false} is VALID [2022-02-21 04:24:16,701 INFO L290 TraceCheckUtils]: 11: Hoare triple {20230#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {20230#false} is VALID [2022-02-21 04:24:16,701 INFO L290 TraceCheckUtils]: 12: Hoare triple {20230#false} assume !(0 == ~T2_E~0); {20230#false} is VALID [2022-02-21 04:24:16,701 INFO L290 TraceCheckUtils]: 13: Hoare triple {20230#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {20230#false} is VALID [2022-02-21 04:24:16,701 INFO L290 TraceCheckUtils]: 14: Hoare triple {20230#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {20230#false} is VALID [2022-02-21 04:24:16,701 INFO L290 TraceCheckUtils]: 15: Hoare triple {20230#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {20230#false} is VALID [2022-02-21 04:24:16,701 INFO L290 TraceCheckUtils]: 16: Hoare triple {20230#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {20230#false} is VALID [2022-02-21 04:24:16,701 INFO L290 TraceCheckUtils]: 17: Hoare triple {20230#false} assume !(0 == ~E_1~0); {20230#false} is VALID [2022-02-21 04:24:16,701 INFO L290 TraceCheckUtils]: 18: Hoare triple {20230#false} assume 0 == ~E_2~0;~E_2~0 := 1; {20230#false} is VALID [2022-02-21 04:24:16,701 INFO L290 TraceCheckUtils]: 19: Hoare triple {20230#false} assume 0 == ~E_3~0;~E_3~0 := 1; {20230#false} is VALID [2022-02-21 04:24:16,702 INFO L290 TraceCheckUtils]: 20: Hoare triple {20230#false} assume !(0 == ~E_4~0); {20230#false} is VALID [2022-02-21 04:24:16,702 INFO L290 TraceCheckUtils]: 21: Hoare triple {20230#false} assume 0 == ~E_5~0;~E_5~0 := 1; {20230#false} is VALID [2022-02-21 04:24:16,702 INFO L290 TraceCheckUtils]: 22: Hoare triple {20230#false} assume 0 == ~E_6~0;~E_6~0 := 1; {20230#false} is VALID [2022-02-21 04:24:16,702 INFO L290 TraceCheckUtils]: 23: Hoare triple {20230#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20230#false} is VALID [2022-02-21 04:24:16,702 INFO L290 TraceCheckUtils]: 24: Hoare triple {20230#false} assume 1 == ~m_pc~0; {20230#false} is VALID [2022-02-21 04:24:16,702 INFO L290 TraceCheckUtils]: 25: Hoare triple {20230#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {20230#false} is VALID [2022-02-21 04:24:16,702 INFO L290 TraceCheckUtils]: 26: Hoare triple {20230#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20230#false} is VALID [2022-02-21 04:24:16,702 INFO L290 TraceCheckUtils]: 27: Hoare triple {20230#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {20230#false} is VALID [2022-02-21 04:24:16,702 INFO L290 TraceCheckUtils]: 28: Hoare triple {20230#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {20230#false} is VALID [2022-02-21 04:24:16,703 INFO L290 TraceCheckUtils]: 29: Hoare triple {20230#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20230#false} is VALID [2022-02-21 04:24:16,703 INFO L290 TraceCheckUtils]: 30: Hoare triple {20230#false} assume !(1 == ~t1_pc~0); {20230#false} is VALID [2022-02-21 04:24:16,703 INFO L290 TraceCheckUtils]: 31: Hoare triple {20230#false} is_transmit1_triggered_~__retres1~1#1 := 0; {20230#false} is VALID [2022-02-21 04:24:16,703 INFO L290 TraceCheckUtils]: 32: Hoare triple {20230#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20230#false} is VALID [2022-02-21 04:24:16,703 INFO L290 TraceCheckUtils]: 33: Hoare triple {20230#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {20230#false} is VALID [2022-02-21 04:24:16,703 INFO L290 TraceCheckUtils]: 34: Hoare triple {20230#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {20230#false} is VALID [2022-02-21 04:24:16,703 INFO L290 TraceCheckUtils]: 35: Hoare triple {20230#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20230#false} is VALID [2022-02-21 04:24:16,703 INFO L290 TraceCheckUtils]: 36: Hoare triple {20230#false} assume 1 == ~t2_pc~0; {20230#false} is VALID [2022-02-21 04:24:16,703 INFO L290 TraceCheckUtils]: 37: Hoare triple {20230#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {20230#false} is VALID [2022-02-21 04:24:16,703 INFO L290 TraceCheckUtils]: 38: Hoare triple {20230#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20230#false} is VALID [2022-02-21 04:24:16,704 INFO L290 TraceCheckUtils]: 39: Hoare triple {20230#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {20230#false} is VALID [2022-02-21 04:24:16,704 INFO L290 TraceCheckUtils]: 40: Hoare triple {20230#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {20230#false} is VALID [2022-02-21 04:24:16,704 INFO L290 TraceCheckUtils]: 41: Hoare triple {20230#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20230#false} is VALID [2022-02-21 04:24:16,704 INFO L290 TraceCheckUtils]: 42: Hoare triple {20230#false} assume !(1 == ~t3_pc~0); {20230#false} is VALID [2022-02-21 04:24:16,704 INFO L290 TraceCheckUtils]: 43: Hoare triple {20230#false} is_transmit3_triggered_~__retres1~3#1 := 0; {20230#false} is VALID [2022-02-21 04:24:16,704 INFO L290 TraceCheckUtils]: 44: Hoare triple {20230#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20230#false} is VALID [2022-02-21 04:24:16,704 INFO L290 TraceCheckUtils]: 45: Hoare triple {20230#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {20230#false} is VALID [2022-02-21 04:24:16,704 INFO L290 TraceCheckUtils]: 46: Hoare triple {20230#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {20230#false} is VALID [2022-02-21 04:24:16,704 INFO L290 TraceCheckUtils]: 47: Hoare triple {20230#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20230#false} is VALID [2022-02-21 04:24:16,704 INFO L290 TraceCheckUtils]: 48: Hoare triple {20230#false} assume 1 == ~t4_pc~0; {20230#false} is VALID [2022-02-21 04:24:16,705 INFO L290 TraceCheckUtils]: 49: Hoare triple {20230#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {20230#false} is VALID [2022-02-21 04:24:16,705 INFO L290 TraceCheckUtils]: 50: Hoare triple {20230#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20230#false} is VALID [2022-02-21 04:24:16,705 INFO L290 TraceCheckUtils]: 51: Hoare triple {20230#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {20230#false} is VALID [2022-02-21 04:24:16,705 INFO L290 TraceCheckUtils]: 52: Hoare triple {20230#false} assume !(0 != activate_threads_~tmp___3~0#1); {20230#false} is VALID [2022-02-21 04:24:16,705 INFO L290 TraceCheckUtils]: 53: Hoare triple {20230#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20230#false} is VALID [2022-02-21 04:24:16,705 INFO L290 TraceCheckUtils]: 54: Hoare triple {20230#false} assume 1 == ~t5_pc~0; {20230#false} is VALID [2022-02-21 04:24:16,705 INFO L290 TraceCheckUtils]: 55: Hoare triple {20230#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {20230#false} is VALID [2022-02-21 04:24:16,705 INFO L290 TraceCheckUtils]: 56: Hoare triple {20230#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20230#false} is VALID [2022-02-21 04:24:16,705 INFO L290 TraceCheckUtils]: 57: Hoare triple {20230#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {20230#false} is VALID [2022-02-21 04:24:16,706 INFO L290 TraceCheckUtils]: 58: Hoare triple {20230#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {20230#false} is VALID [2022-02-21 04:24:16,706 INFO L290 TraceCheckUtils]: 59: Hoare triple {20230#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {20230#false} is VALID [2022-02-21 04:24:16,706 INFO L290 TraceCheckUtils]: 60: Hoare triple {20230#false} assume !(1 == ~t6_pc~0); {20230#false} is VALID [2022-02-21 04:24:16,706 INFO L290 TraceCheckUtils]: 61: Hoare triple {20230#false} is_transmit6_triggered_~__retres1~6#1 := 0; {20230#false} is VALID [2022-02-21 04:24:16,706 INFO L290 TraceCheckUtils]: 62: Hoare triple {20230#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {20230#false} is VALID [2022-02-21 04:24:16,706 INFO L290 TraceCheckUtils]: 63: Hoare triple {20230#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {20230#false} is VALID [2022-02-21 04:24:16,706 INFO L290 TraceCheckUtils]: 64: Hoare triple {20230#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {20230#false} is VALID [2022-02-21 04:24:16,706 INFO L290 TraceCheckUtils]: 65: Hoare triple {20230#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20230#false} is VALID [2022-02-21 04:24:16,706 INFO L290 TraceCheckUtils]: 66: Hoare triple {20230#false} assume 1 == ~M_E~0;~M_E~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,706 INFO L290 TraceCheckUtils]: 67: Hoare triple {20230#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,707 INFO L290 TraceCheckUtils]: 68: Hoare triple {20230#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,707 INFO L290 TraceCheckUtils]: 69: Hoare triple {20230#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,707 INFO L290 TraceCheckUtils]: 70: Hoare triple {20230#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,707 INFO L290 TraceCheckUtils]: 71: Hoare triple {20230#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,707 INFO L290 TraceCheckUtils]: 72: Hoare triple {20230#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,707 INFO L290 TraceCheckUtils]: 73: Hoare triple {20230#false} assume !(1 == ~E_1~0); {20230#false} is VALID [2022-02-21 04:24:16,707 INFO L290 TraceCheckUtils]: 74: Hoare triple {20230#false} assume 1 == ~E_2~0;~E_2~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,707 INFO L290 TraceCheckUtils]: 75: Hoare triple {20230#false} assume 1 == ~E_3~0;~E_3~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,707 INFO L290 TraceCheckUtils]: 76: Hoare triple {20230#false} assume 1 == ~E_4~0;~E_4~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,707 INFO L290 TraceCheckUtils]: 77: Hoare triple {20230#false} assume 1 == ~E_5~0;~E_5~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,708 INFO L290 TraceCheckUtils]: 78: Hoare triple {20230#false} assume 1 == ~E_6~0;~E_6~0 := 2; {20230#false} is VALID [2022-02-21 04:24:16,708 INFO L290 TraceCheckUtils]: 79: Hoare triple {20230#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {20230#false} is VALID [2022-02-21 04:24:16,708 INFO L290 TraceCheckUtils]: 80: Hoare triple {20230#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {20230#false} is VALID [2022-02-21 04:24:16,708 INFO L290 TraceCheckUtils]: 81: Hoare triple {20230#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {20230#false} is VALID [2022-02-21 04:24:16,708 INFO L290 TraceCheckUtils]: 82: Hoare triple {20230#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {20230#false} is VALID [2022-02-21 04:24:16,708 INFO L290 TraceCheckUtils]: 83: Hoare triple {20230#false} assume !(0 == start_simulation_~tmp~3#1); {20230#false} is VALID [2022-02-21 04:24:16,708 INFO L290 TraceCheckUtils]: 84: Hoare triple {20230#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {20230#false} is VALID [2022-02-21 04:24:16,708 INFO L290 TraceCheckUtils]: 85: Hoare triple {20230#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {20230#false} is VALID [2022-02-21 04:24:16,708 INFO L290 TraceCheckUtils]: 86: Hoare triple {20230#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {20230#false} is VALID [2022-02-21 04:24:16,708 INFO L290 TraceCheckUtils]: 87: Hoare triple {20230#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {20230#false} is VALID [2022-02-21 04:24:16,709 INFO L290 TraceCheckUtils]: 88: Hoare triple {20230#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {20230#false} is VALID [2022-02-21 04:24:16,709 INFO L290 TraceCheckUtils]: 89: Hoare triple {20230#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {20230#false} is VALID [2022-02-21 04:24:16,709 INFO L290 TraceCheckUtils]: 90: Hoare triple {20230#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {20230#false} is VALID [2022-02-21 04:24:16,709 INFO L290 TraceCheckUtils]: 91: Hoare triple {20230#false} assume !(0 != start_simulation_~tmp___0~1#1); {20230#false} is VALID [2022-02-21 04:24:16,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:16,709 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:16,711 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63986738] [2022-02-21 04:24:16,712 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63986738] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:16,712 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:16,712 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:16,712 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853853172] [2022-02-21 04:24:16,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:16,713 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:16,713 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:16,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:16,714 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:16,714 INFO L87 Difference]: Start difference. First operand 1122 states and 1670 transitions. cyclomatic complexity: 550 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,385 INFO L93 Difference]: Finished difference Result 1637 states and 2406 transitions. [2022-02-21 04:24:17,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:17,385 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,425 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:17,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1637 states and 2406 transitions. [2022-02-21 04:24:17,490 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1536 [2022-02-21 04:24:17,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1637 states to 1637 states and 2406 transitions. [2022-02-21 04:24:17,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1637 [2022-02-21 04:24:17,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1637 [2022-02-21 04:24:17,557 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1637 states and 2406 transitions. [2022-02-21 04:24:17,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:17,559 INFO L681 BuchiCegarLoop]: Abstraction has 1637 states and 2406 transitions. [2022-02-21 04:24:17,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1637 states and 2406 transitions. [2022-02-21 04:24:17,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1637 to 1586. [2022-02-21 04:24:17,588 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:17,590 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1637 states and 2406 transitions. Second operand has 1586 states, 1586 states have (on average 1.4728877679697352) internal successors, (2336), 1585 states have internal predecessors, (2336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,591 INFO L74 IsIncluded]: Start isIncluded. First operand 1637 states and 2406 transitions. Second operand has 1586 states, 1586 states have (on average 1.4728877679697352) internal successors, (2336), 1585 states have internal predecessors, (2336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,593 INFO L87 Difference]: Start difference. First operand 1637 states and 2406 transitions. Second operand has 1586 states, 1586 states have (on average 1.4728877679697352) internal successors, (2336), 1585 states have internal predecessors, (2336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,652 INFO L93 Difference]: Finished difference Result 1637 states and 2406 transitions. [2022-02-21 04:24:17,652 INFO L276 IsEmpty]: Start isEmpty. Operand 1637 states and 2406 transitions. [2022-02-21 04:24:17,654 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:17,654 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:17,656 INFO L74 IsIncluded]: Start isIncluded. First operand has 1586 states, 1586 states have (on average 1.4728877679697352) internal successors, (2336), 1585 states have internal predecessors, (2336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1637 states and 2406 transitions. [2022-02-21 04:24:17,657 INFO L87 Difference]: Start difference. First operand has 1586 states, 1586 states have (on average 1.4728877679697352) internal successors, (2336), 1585 states have internal predecessors, (2336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1637 states and 2406 transitions. [2022-02-21 04:24:17,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,714 INFO L93 Difference]: Finished difference Result 1637 states and 2406 transitions. [2022-02-21 04:24:17,714 INFO L276 IsEmpty]: Start isEmpty. Operand 1637 states and 2406 transitions. [2022-02-21 04:24:17,716 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:17,716 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:17,717 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:17,717 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:17,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1586 states, 1586 states have (on average 1.4728877679697352) internal successors, (2336), 1585 states have internal predecessors, (2336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1586 states to 1586 states and 2336 transitions. [2022-02-21 04:24:17,773 INFO L704 BuchiCegarLoop]: Abstraction has 1586 states and 2336 transitions. [2022-02-21 04:24:17,773 INFO L587 BuchiCegarLoop]: Abstraction has 1586 states and 2336 transitions. [2022-02-21 04:24:17,773 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:17,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1586 states and 2336 transitions. [2022-02-21 04:24:17,778 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1486 [2022-02-21 04:24:17,778 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:17,778 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:17,779 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,779 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,779 INFO L791 eck$LassoCheckResult]: Stem: 22537#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 22502#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 22439#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21875#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21871#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 21872#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22389#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22522#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21966#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21967#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22115#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21984#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21985#L670 assume !(0 == ~M_E~0); 22351#L670-2 assume !(0 == ~T1_E~0); 22297#L675-1 assume !(0 == ~T2_E~0); 22298#L680-1 assume !(0 == ~T3_E~0); 22387#L685-1 assume !(0 == ~T4_E~0); 22356#L690-1 assume !(0 == ~T5_E~0); 22357#L695-1 assume !(0 == ~T6_E~0); 22418#L700-1 assume !(0 == ~E_1~0); 22410#L705-1 assume !(0 == ~E_2~0); 22411#L710-1 assume !(0 == ~E_3~0); 22296#L715-1 assume !(0 == ~E_4~0); 22221#L720-1 assume !(0 == ~E_5~0); 22222#L725-1 assume !(0 == ~E_6~0); 22274#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22323#L320 assume !(1 == ~m_pc~0); 22436#L320-2 is_master_triggered_~__retres1~0#1 := 0; 22157#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22158#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22116#L825 assume !(0 != activate_threads_~tmp~1#1); 22117#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22123#L339 assume !(1 == ~t1_pc~0); 22124#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22100#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22101#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21986#L833 assume !(0 != activate_threads_~tmp___0~0#1); 21987#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21896#L358 assume 1 == ~t2_pc~0; 21897#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22406#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22352#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22278#L841 assume !(0 != activate_threads_~tmp___1~0#1); 22113#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22114#L377 assume !(1 == ~t3_pc~0); 22371#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22372#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22370#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22120#L849 assume !(0 != activate_threads_~tmp___2~0#1); 22121#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22070#L396 assume 1 == ~t4_pc~0; 22071#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21899#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21900#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22312#L857 assume !(0 != activate_threads_~tmp___3~0#1); 22038#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22039#L415 assume 1 == ~t5_pc~0; 22103#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22147#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22324#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22444#L865 assume !(0 != activate_threads_~tmp___4~0#1); 21942#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21943#L434 assume !(1 == ~t6_pc~0); 22253#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22254#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22399#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22400#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22133#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22134#L743 assume !(1 == ~M_E~0); 22031#L743-2 assume !(1 == ~T1_E~0); 22032#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22489#L753-1 assume !(1 == ~T3_E~0); 23288#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23287#L763-1 assume !(1 == ~T5_E~0); 23286#L768-1 assume !(1 == ~T6_E~0); 23284#L773-1 assume !(1 == ~E_1~0); 22131#L778-1 assume !(1 == ~E_2~0); 23281#L783-1 assume !(1 == ~E_3~0); 23279#L788-1 assume !(1 == ~E_4~0); 23277#L793-1 assume !(1 == ~E_5~0); 23050#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 23030#L803-1 assume { :end_inline_reset_delta_events } true; 23024#L1024-2 [2022-02-21 04:24:17,779 INFO L793 eck$LassoCheckResult]: Loop: 23024#L1024-2 assume !false; 22483#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22341#L645 assume !false; 23015#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 23014#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 23007#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 22480#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22481#L556 assume !(0 != eval_~tmp~0#1); 22530#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22405#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21999#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22000#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23002#L675-3 assume !(0 == ~T2_E~0); 22445#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22382#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22383#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22523#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22391#L700-3 assume !(0 == ~E_1~0); 22392#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22051#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22052#L715-3 assume !(0 == ~E_4~0); 22279#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22280#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22355#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22126#L320-21 assume !(1 == ~m_pc~0); 22127#L320-23 is_master_triggered_~__retres1~0#1 := 0; 22277#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22204#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22205#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22455#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22063#L339-21 assume !(1 == ~t1_pc~0); 22064#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 22165#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22040#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21924#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21925#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22023#L358-21 assume 1 == ~t2_pc~0; 22122#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22003#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22004#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22283#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22041#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22042#L377-21 assume !(1 == ~t3_pc~0); 22402#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 22309#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22310#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22332#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22176#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22177#L396-21 assume 1 == ~t4_pc~0; 22345#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22203#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22174#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21906#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 21907#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22152#L415-21 assume !(1 == ~t5_pc~0); 22128#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 22129#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22027#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22028#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22224#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22225#L434-21 assume !(1 == ~t6_pc~0); 21931#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 21932#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22442#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22148#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22149#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22143#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22144#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22491#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22304#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22244#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22167#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22168#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22474#L773-3 assume !(1 == ~E_1~0); 22088#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22089#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23322#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23320#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23318#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23316#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 23113#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 23108#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 23106#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 23103#L1043 assume !(0 == start_simulation_~tmp~3#1); 23101#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 23091#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 23085#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 23083#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 23081#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23038#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23036#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 23031#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 23024#L1024-2 [2022-02-21 04:24:17,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,780 INFO L85 PathProgramCache]: Analyzing trace with hash -1227190400, now seen corresponding path program 1 times [2022-02-21 04:24:17,780 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,780 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537935923] [2022-02-21 04:24:17,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,799 INFO L290 TraceCheckUtils]: 0: Hoare triple {26734#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,800 INFO L290 TraceCheckUtils]: 1: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,800 INFO L290 TraceCheckUtils]: 2: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,800 INFO L290 TraceCheckUtils]: 3: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,801 INFO L290 TraceCheckUtils]: 4: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,801 INFO L290 TraceCheckUtils]: 5: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,801 INFO L290 TraceCheckUtils]: 6: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,801 INFO L290 TraceCheckUtils]: 7: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,802 INFO L290 TraceCheckUtils]: 8: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,802 INFO L290 TraceCheckUtils]: 9: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,802 INFO L290 TraceCheckUtils]: 10: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,802 INFO L290 TraceCheckUtils]: 11: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,803 INFO L290 TraceCheckUtils]: 12: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~M_E~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,803 INFO L290 TraceCheckUtils]: 13: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T1_E~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,803 INFO L290 TraceCheckUtils]: 14: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T2_E~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,803 INFO L290 TraceCheckUtils]: 15: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T3_E~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,804 INFO L290 TraceCheckUtils]: 16: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T4_E~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,804 INFO L290 TraceCheckUtils]: 17: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T5_E~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,804 INFO L290 TraceCheckUtils]: 18: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T6_E~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,804 INFO L290 TraceCheckUtils]: 19: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_1~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,804 INFO L290 TraceCheckUtils]: 20: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_2~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,805 INFO L290 TraceCheckUtils]: 21: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_3~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,805 INFO L290 TraceCheckUtils]: 22: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_4~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,805 INFO L290 TraceCheckUtils]: 23: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_5~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,805 INFO L290 TraceCheckUtils]: 24: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_6~0); {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,806 INFO L290 TraceCheckUtils]: 25: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26736#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:17,806 INFO L290 TraceCheckUtils]: 26: Hoare triple {26736#(= ~m_pc~0 ~t2_pc~0)} assume !(1 == ~m_pc~0); {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,806 INFO L290 TraceCheckUtils]: 27: Hoare triple {26737#(not (= ~t2_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,806 INFO L290 TraceCheckUtils]: 28: Hoare triple {26737#(not (= ~t2_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,808 INFO L290 TraceCheckUtils]: 29: Hoare triple {26737#(not (= ~t2_pc~0 1))} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,817 INFO L290 TraceCheckUtils]: 30: Hoare triple {26737#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,817 INFO L290 TraceCheckUtils]: 31: Hoare triple {26737#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,817 INFO L290 TraceCheckUtils]: 32: Hoare triple {26737#(not (= ~t2_pc~0 1))} assume !(1 == ~t1_pc~0); {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,818 INFO L290 TraceCheckUtils]: 33: Hoare triple {26737#(not (= ~t2_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,818 INFO L290 TraceCheckUtils]: 34: Hoare triple {26737#(not (= ~t2_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,818 INFO L290 TraceCheckUtils]: 35: Hoare triple {26737#(not (= ~t2_pc~0 1))} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,818 INFO L290 TraceCheckUtils]: 36: Hoare triple {26737#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,819 INFO L290 TraceCheckUtils]: 37: Hoare triple {26737#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26737#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:17,819 INFO L290 TraceCheckUtils]: 38: Hoare triple {26737#(not (= ~t2_pc~0 1))} assume 1 == ~t2_pc~0; {26735#false} is VALID [2022-02-21 04:24:17,819 INFO L290 TraceCheckUtils]: 39: Hoare triple {26735#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26735#false} is VALID [2022-02-21 04:24:17,819 INFO L290 TraceCheckUtils]: 40: Hoare triple {26735#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26735#false} is VALID [2022-02-21 04:24:17,819 INFO L290 TraceCheckUtils]: 41: Hoare triple {26735#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {26735#false} is VALID [2022-02-21 04:24:17,819 INFO L290 TraceCheckUtils]: 42: Hoare triple {26735#false} assume !(0 != activate_threads_~tmp___1~0#1); {26735#false} is VALID [2022-02-21 04:24:17,820 INFO L290 TraceCheckUtils]: 43: Hoare triple {26735#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26735#false} is VALID [2022-02-21 04:24:17,820 INFO L290 TraceCheckUtils]: 44: Hoare triple {26735#false} assume !(1 == ~t3_pc~0); {26735#false} is VALID [2022-02-21 04:24:17,820 INFO L290 TraceCheckUtils]: 45: Hoare triple {26735#false} is_transmit3_triggered_~__retres1~3#1 := 0; {26735#false} is VALID [2022-02-21 04:24:17,820 INFO L290 TraceCheckUtils]: 46: Hoare triple {26735#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26735#false} is VALID [2022-02-21 04:24:17,820 INFO L290 TraceCheckUtils]: 47: Hoare triple {26735#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {26735#false} is VALID [2022-02-21 04:24:17,820 INFO L290 TraceCheckUtils]: 48: Hoare triple {26735#false} assume !(0 != activate_threads_~tmp___2~0#1); {26735#false} is VALID [2022-02-21 04:24:17,820 INFO L290 TraceCheckUtils]: 49: Hoare triple {26735#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26735#false} is VALID [2022-02-21 04:24:17,820 INFO L290 TraceCheckUtils]: 50: Hoare triple {26735#false} assume 1 == ~t4_pc~0; {26735#false} is VALID [2022-02-21 04:24:17,820 INFO L290 TraceCheckUtils]: 51: Hoare triple {26735#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26735#false} is VALID [2022-02-21 04:24:17,821 INFO L290 TraceCheckUtils]: 52: Hoare triple {26735#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26735#false} is VALID [2022-02-21 04:24:17,821 INFO L290 TraceCheckUtils]: 53: Hoare triple {26735#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {26735#false} is VALID [2022-02-21 04:24:17,821 INFO L290 TraceCheckUtils]: 54: Hoare triple {26735#false} assume !(0 != activate_threads_~tmp___3~0#1); {26735#false} is VALID [2022-02-21 04:24:17,821 INFO L290 TraceCheckUtils]: 55: Hoare triple {26735#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26735#false} is VALID [2022-02-21 04:24:17,821 INFO L290 TraceCheckUtils]: 56: Hoare triple {26735#false} assume 1 == ~t5_pc~0; {26735#false} is VALID [2022-02-21 04:24:17,821 INFO L290 TraceCheckUtils]: 57: Hoare triple {26735#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {26735#false} is VALID [2022-02-21 04:24:17,821 INFO L290 TraceCheckUtils]: 58: Hoare triple {26735#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26735#false} is VALID [2022-02-21 04:24:17,821 INFO L290 TraceCheckUtils]: 59: Hoare triple {26735#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {26735#false} is VALID [2022-02-21 04:24:17,821 INFO L290 TraceCheckUtils]: 60: Hoare triple {26735#false} assume !(0 != activate_threads_~tmp___4~0#1); {26735#false} is VALID [2022-02-21 04:24:17,821 INFO L290 TraceCheckUtils]: 61: Hoare triple {26735#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26735#false} is VALID [2022-02-21 04:24:17,822 INFO L290 TraceCheckUtils]: 62: Hoare triple {26735#false} assume !(1 == ~t6_pc~0); {26735#false} is VALID [2022-02-21 04:24:17,822 INFO L290 TraceCheckUtils]: 63: Hoare triple {26735#false} is_transmit6_triggered_~__retres1~6#1 := 0; {26735#false} is VALID [2022-02-21 04:24:17,822 INFO L290 TraceCheckUtils]: 64: Hoare triple {26735#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26735#false} is VALID [2022-02-21 04:24:17,822 INFO L290 TraceCheckUtils]: 65: Hoare triple {26735#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {26735#false} is VALID [2022-02-21 04:24:17,822 INFO L290 TraceCheckUtils]: 66: Hoare triple {26735#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {26735#false} is VALID [2022-02-21 04:24:17,822 INFO L290 TraceCheckUtils]: 67: Hoare triple {26735#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26735#false} is VALID [2022-02-21 04:24:17,822 INFO L290 TraceCheckUtils]: 68: Hoare triple {26735#false} assume !(1 == ~M_E~0); {26735#false} is VALID [2022-02-21 04:24:17,822 INFO L290 TraceCheckUtils]: 69: Hoare triple {26735#false} assume !(1 == ~T1_E~0); {26735#false} is VALID [2022-02-21 04:24:17,822 INFO L290 TraceCheckUtils]: 70: Hoare triple {26735#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {26735#false} is VALID [2022-02-21 04:24:17,823 INFO L290 TraceCheckUtils]: 71: Hoare triple {26735#false} assume !(1 == ~T3_E~0); {26735#false} is VALID [2022-02-21 04:24:17,823 INFO L290 TraceCheckUtils]: 72: Hoare triple {26735#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {26735#false} is VALID [2022-02-21 04:24:17,823 INFO L290 TraceCheckUtils]: 73: Hoare triple {26735#false} assume !(1 == ~T5_E~0); {26735#false} is VALID [2022-02-21 04:24:17,823 INFO L290 TraceCheckUtils]: 74: Hoare triple {26735#false} assume !(1 == ~T6_E~0); {26735#false} is VALID [2022-02-21 04:24:17,823 INFO L290 TraceCheckUtils]: 75: Hoare triple {26735#false} assume !(1 == ~E_1~0); {26735#false} is VALID [2022-02-21 04:24:17,823 INFO L290 TraceCheckUtils]: 76: Hoare triple {26735#false} assume !(1 == ~E_2~0); {26735#false} is VALID [2022-02-21 04:24:17,823 INFO L290 TraceCheckUtils]: 77: Hoare triple {26735#false} assume !(1 == ~E_3~0); {26735#false} is VALID [2022-02-21 04:24:17,823 INFO L290 TraceCheckUtils]: 78: Hoare triple {26735#false} assume !(1 == ~E_4~0); {26735#false} is VALID [2022-02-21 04:24:17,823 INFO L290 TraceCheckUtils]: 79: Hoare triple {26735#false} assume !(1 == ~E_5~0); {26735#false} is VALID [2022-02-21 04:24:17,824 INFO L290 TraceCheckUtils]: 80: Hoare triple {26735#false} assume 1 == ~E_6~0;~E_6~0 := 2; {26735#false} is VALID [2022-02-21 04:24:17,824 INFO L290 TraceCheckUtils]: 81: Hoare triple {26735#false} assume { :end_inline_reset_delta_events } true; {26735#false} is VALID [2022-02-21 04:24:17,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,824 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,824 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1537935923] [2022-02-21 04:24:17,824 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1537935923] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,824 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,824 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:17,825 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151108113] [2022-02-21 04:24:17,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,825 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:17,825 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,826 INFO L85 PathProgramCache]: Analyzing trace with hash 93166242, now seen corresponding path program 1 times [2022-02-21 04:24:17,826 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,826 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640298539] [2022-02-21 04:24:17,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,851 INFO L290 TraceCheckUtils]: 0: Hoare triple {26738#true} assume !false; {26738#true} is VALID [2022-02-21 04:24:17,851 INFO L290 TraceCheckUtils]: 1: Hoare triple {26738#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {26738#true} is VALID [2022-02-21 04:24:17,852 INFO L290 TraceCheckUtils]: 2: Hoare triple {26738#true} assume !false; {26738#true} is VALID [2022-02-21 04:24:17,852 INFO L290 TraceCheckUtils]: 3: Hoare triple {26738#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {26738#true} is VALID [2022-02-21 04:24:17,852 INFO L290 TraceCheckUtils]: 4: Hoare triple {26738#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {26740#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~7#1|)} is VALID [2022-02-21 04:24:17,852 INFO L290 TraceCheckUtils]: 5: Hoare triple {26740#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~7#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {26741#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:17,853 INFO L290 TraceCheckUtils]: 6: Hoare triple {26741#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {26742#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:17,853 INFO L290 TraceCheckUtils]: 7: Hoare triple {26742#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {26739#false} is VALID [2022-02-21 04:24:17,853 INFO L290 TraceCheckUtils]: 8: Hoare triple {26739#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {26739#false} is VALID [2022-02-21 04:24:17,853 INFO L290 TraceCheckUtils]: 9: Hoare triple {26739#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {26739#false} is VALID [2022-02-21 04:24:17,853 INFO L290 TraceCheckUtils]: 10: Hoare triple {26739#false} assume 0 == ~M_E~0;~M_E~0 := 1; {26739#false} is VALID [2022-02-21 04:24:17,853 INFO L290 TraceCheckUtils]: 11: Hoare triple {26739#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {26739#false} is VALID [2022-02-21 04:24:17,854 INFO L290 TraceCheckUtils]: 12: Hoare triple {26739#false} assume !(0 == ~T2_E~0); {26739#false} is VALID [2022-02-21 04:24:17,854 INFO L290 TraceCheckUtils]: 13: Hoare triple {26739#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {26739#false} is VALID [2022-02-21 04:24:17,854 INFO L290 TraceCheckUtils]: 14: Hoare triple {26739#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {26739#false} is VALID [2022-02-21 04:24:17,854 INFO L290 TraceCheckUtils]: 15: Hoare triple {26739#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {26739#false} is VALID [2022-02-21 04:24:17,854 INFO L290 TraceCheckUtils]: 16: Hoare triple {26739#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {26739#false} is VALID [2022-02-21 04:24:17,854 INFO L290 TraceCheckUtils]: 17: Hoare triple {26739#false} assume !(0 == ~E_1~0); {26739#false} is VALID [2022-02-21 04:24:17,854 INFO L290 TraceCheckUtils]: 18: Hoare triple {26739#false} assume 0 == ~E_2~0;~E_2~0 := 1; {26739#false} is VALID [2022-02-21 04:24:17,854 INFO L290 TraceCheckUtils]: 19: Hoare triple {26739#false} assume 0 == ~E_3~0;~E_3~0 := 1; {26739#false} is VALID [2022-02-21 04:24:17,854 INFO L290 TraceCheckUtils]: 20: Hoare triple {26739#false} assume !(0 == ~E_4~0); {26739#false} is VALID [2022-02-21 04:24:17,854 INFO L290 TraceCheckUtils]: 21: Hoare triple {26739#false} assume 0 == ~E_5~0;~E_5~0 := 1; {26739#false} is VALID [2022-02-21 04:24:17,855 INFO L290 TraceCheckUtils]: 22: Hoare triple {26739#false} assume 0 == ~E_6~0;~E_6~0 := 1; {26739#false} is VALID [2022-02-21 04:24:17,855 INFO L290 TraceCheckUtils]: 23: Hoare triple {26739#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26739#false} is VALID [2022-02-21 04:24:17,855 INFO L290 TraceCheckUtils]: 24: Hoare triple {26739#false} assume !(1 == ~m_pc~0); {26739#false} is VALID [2022-02-21 04:24:17,855 INFO L290 TraceCheckUtils]: 25: Hoare triple {26739#false} is_master_triggered_~__retres1~0#1 := 0; {26739#false} is VALID [2022-02-21 04:24:17,855 INFO L290 TraceCheckUtils]: 26: Hoare triple {26739#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26739#false} is VALID [2022-02-21 04:24:17,855 INFO L290 TraceCheckUtils]: 27: Hoare triple {26739#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {26739#false} is VALID [2022-02-21 04:24:17,855 INFO L290 TraceCheckUtils]: 28: Hoare triple {26739#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {26739#false} is VALID [2022-02-21 04:24:17,855 INFO L290 TraceCheckUtils]: 29: Hoare triple {26739#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26739#false} is VALID [2022-02-21 04:24:17,855 INFO L290 TraceCheckUtils]: 30: Hoare triple {26739#false} assume !(1 == ~t1_pc~0); {26739#false} is VALID [2022-02-21 04:24:17,856 INFO L290 TraceCheckUtils]: 31: Hoare triple {26739#false} is_transmit1_triggered_~__retres1~1#1 := 0; {26739#false} is VALID [2022-02-21 04:24:17,856 INFO L290 TraceCheckUtils]: 32: Hoare triple {26739#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26739#false} is VALID [2022-02-21 04:24:17,856 INFO L290 TraceCheckUtils]: 33: Hoare triple {26739#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {26739#false} is VALID [2022-02-21 04:24:17,856 INFO L290 TraceCheckUtils]: 34: Hoare triple {26739#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {26739#false} is VALID [2022-02-21 04:24:17,856 INFO L290 TraceCheckUtils]: 35: Hoare triple {26739#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26739#false} is VALID [2022-02-21 04:24:17,856 INFO L290 TraceCheckUtils]: 36: Hoare triple {26739#false} assume 1 == ~t2_pc~0; {26739#false} is VALID [2022-02-21 04:24:17,856 INFO L290 TraceCheckUtils]: 37: Hoare triple {26739#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26739#false} is VALID [2022-02-21 04:24:17,856 INFO L290 TraceCheckUtils]: 38: Hoare triple {26739#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26739#false} is VALID [2022-02-21 04:24:17,856 INFO L290 TraceCheckUtils]: 39: Hoare triple {26739#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {26739#false} is VALID [2022-02-21 04:24:17,856 INFO L290 TraceCheckUtils]: 40: Hoare triple {26739#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {26739#false} is VALID [2022-02-21 04:24:17,857 INFO L290 TraceCheckUtils]: 41: Hoare triple {26739#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26739#false} is VALID [2022-02-21 04:24:17,857 INFO L290 TraceCheckUtils]: 42: Hoare triple {26739#false} assume !(1 == ~t3_pc~0); {26739#false} is VALID [2022-02-21 04:24:17,857 INFO L290 TraceCheckUtils]: 43: Hoare triple {26739#false} is_transmit3_triggered_~__retres1~3#1 := 0; {26739#false} is VALID [2022-02-21 04:24:17,857 INFO L290 TraceCheckUtils]: 44: Hoare triple {26739#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26739#false} is VALID [2022-02-21 04:24:17,857 INFO L290 TraceCheckUtils]: 45: Hoare triple {26739#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {26739#false} is VALID [2022-02-21 04:24:17,857 INFO L290 TraceCheckUtils]: 46: Hoare triple {26739#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26739#false} is VALID [2022-02-21 04:24:17,857 INFO L290 TraceCheckUtils]: 47: Hoare triple {26739#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26739#false} is VALID [2022-02-21 04:24:17,857 INFO L290 TraceCheckUtils]: 48: Hoare triple {26739#false} assume 1 == ~t4_pc~0; {26739#false} is VALID [2022-02-21 04:24:17,857 INFO L290 TraceCheckUtils]: 49: Hoare triple {26739#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26739#false} is VALID [2022-02-21 04:24:17,858 INFO L290 TraceCheckUtils]: 50: Hoare triple {26739#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26739#false} is VALID [2022-02-21 04:24:17,858 INFO L290 TraceCheckUtils]: 51: Hoare triple {26739#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {26739#false} is VALID [2022-02-21 04:24:17,858 INFO L290 TraceCheckUtils]: 52: Hoare triple {26739#false} assume !(0 != activate_threads_~tmp___3~0#1); {26739#false} is VALID [2022-02-21 04:24:17,858 INFO L290 TraceCheckUtils]: 53: Hoare triple {26739#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26739#false} is VALID [2022-02-21 04:24:17,858 INFO L290 TraceCheckUtils]: 54: Hoare triple {26739#false} assume !(1 == ~t5_pc~0); {26739#false} is VALID [2022-02-21 04:24:17,858 INFO L290 TraceCheckUtils]: 55: Hoare triple {26739#false} is_transmit5_triggered_~__retres1~5#1 := 0; {26739#false} is VALID [2022-02-21 04:24:17,858 INFO L290 TraceCheckUtils]: 56: Hoare triple {26739#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26739#false} is VALID [2022-02-21 04:24:17,858 INFO L290 TraceCheckUtils]: 57: Hoare triple {26739#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {26739#false} is VALID [2022-02-21 04:24:17,858 INFO L290 TraceCheckUtils]: 58: Hoare triple {26739#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {26739#false} is VALID [2022-02-21 04:24:17,858 INFO L290 TraceCheckUtils]: 59: Hoare triple {26739#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26739#false} is VALID [2022-02-21 04:24:17,859 INFO L290 TraceCheckUtils]: 60: Hoare triple {26739#false} assume !(1 == ~t6_pc~0); {26739#false} is VALID [2022-02-21 04:24:17,859 INFO L290 TraceCheckUtils]: 61: Hoare triple {26739#false} is_transmit6_triggered_~__retres1~6#1 := 0; {26739#false} is VALID [2022-02-21 04:24:17,859 INFO L290 TraceCheckUtils]: 62: Hoare triple {26739#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26739#false} is VALID [2022-02-21 04:24:17,859 INFO L290 TraceCheckUtils]: 63: Hoare triple {26739#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {26739#false} is VALID [2022-02-21 04:24:17,859 INFO L290 TraceCheckUtils]: 64: Hoare triple {26739#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {26739#false} is VALID [2022-02-21 04:24:17,859 INFO L290 TraceCheckUtils]: 65: Hoare triple {26739#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26739#false} is VALID [2022-02-21 04:24:17,859 INFO L290 TraceCheckUtils]: 66: Hoare triple {26739#false} assume 1 == ~M_E~0;~M_E~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,859 INFO L290 TraceCheckUtils]: 67: Hoare triple {26739#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,859 INFO L290 TraceCheckUtils]: 68: Hoare triple {26739#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,860 INFO L290 TraceCheckUtils]: 69: Hoare triple {26739#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,860 INFO L290 TraceCheckUtils]: 70: Hoare triple {26739#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,860 INFO L290 TraceCheckUtils]: 71: Hoare triple {26739#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,860 INFO L290 TraceCheckUtils]: 72: Hoare triple {26739#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,860 INFO L290 TraceCheckUtils]: 73: Hoare triple {26739#false} assume !(1 == ~E_1~0); {26739#false} is VALID [2022-02-21 04:24:17,860 INFO L290 TraceCheckUtils]: 74: Hoare triple {26739#false} assume 1 == ~E_2~0;~E_2~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,860 INFO L290 TraceCheckUtils]: 75: Hoare triple {26739#false} assume 1 == ~E_3~0;~E_3~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,860 INFO L290 TraceCheckUtils]: 76: Hoare triple {26739#false} assume 1 == ~E_4~0;~E_4~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,860 INFO L290 TraceCheckUtils]: 77: Hoare triple {26739#false} assume 1 == ~E_5~0;~E_5~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,861 INFO L290 TraceCheckUtils]: 78: Hoare triple {26739#false} assume 1 == ~E_6~0;~E_6~0 := 2; {26739#false} is VALID [2022-02-21 04:24:17,861 INFO L290 TraceCheckUtils]: 79: Hoare triple {26739#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {26739#false} is VALID [2022-02-21 04:24:17,861 INFO L290 TraceCheckUtils]: 80: Hoare triple {26739#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {26739#false} is VALID [2022-02-21 04:24:17,861 INFO L290 TraceCheckUtils]: 81: Hoare triple {26739#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {26739#false} is VALID [2022-02-21 04:24:17,861 INFO L290 TraceCheckUtils]: 82: Hoare triple {26739#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {26739#false} is VALID [2022-02-21 04:24:17,861 INFO L290 TraceCheckUtils]: 83: Hoare triple {26739#false} assume !(0 == start_simulation_~tmp~3#1); {26739#false} is VALID [2022-02-21 04:24:17,861 INFO L290 TraceCheckUtils]: 84: Hoare triple {26739#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {26739#false} is VALID [2022-02-21 04:24:17,861 INFO L290 TraceCheckUtils]: 85: Hoare triple {26739#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {26739#false} is VALID [2022-02-21 04:24:17,861 INFO L290 TraceCheckUtils]: 86: Hoare triple {26739#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {26739#false} is VALID [2022-02-21 04:24:17,861 INFO L290 TraceCheckUtils]: 87: Hoare triple {26739#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {26739#false} is VALID [2022-02-21 04:24:17,862 INFO L290 TraceCheckUtils]: 88: Hoare triple {26739#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {26739#false} is VALID [2022-02-21 04:24:17,862 INFO L290 TraceCheckUtils]: 89: Hoare triple {26739#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {26739#false} is VALID [2022-02-21 04:24:17,862 INFO L290 TraceCheckUtils]: 90: Hoare triple {26739#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {26739#false} is VALID [2022-02-21 04:24:17,862 INFO L290 TraceCheckUtils]: 91: Hoare triple {26739#false} assume !(0 != start_simulation_~tmp___0~1#1); {26739#false} is VALID [2022-02-21 04:24:17,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,862 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,862 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640298539] [2022-02-21 04:24:17,862 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [640298539] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,863 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,863 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:17,863 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224010423] [2022-02-21 04:24:17,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,863 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:17,863 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:17,864 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:17,864 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:17,864 INFO L87 Difference]: Start difference. First operand 1586 states and 2336 transitions. cyclomatic complexity: 753 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:19,438 INFO L93 Difference]: Finished difference Result 3886 states and 5661 transitions. [2022-02-21 04:24:19,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:19,438 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,487 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:19,487 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3886 states and 5661 transitions. [2022-02-21 04:24:19,813 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 3725 [2022-02-21 04:24:20,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3886 states to 3886 states and 5661 transitions. [2022-02-21 04:24:20,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3886 [2022-02-21 04:24:20,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3886 [2022-02-21 04:24:20,167 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3886 states and 5661 transitions. [2022-02-21 04:24:20,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:20,170 INFO L681 BuchiCegarLoop]: Abstraction has 3886 states and 5661 transitions. [2022-02-21 04:24:20,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3886 states and 5661 transitions. [2022-02-21 04:24:20,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3886 to 2893. [2022-02-21 04:24:20,195 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:20,198 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3886 states and 5661 transitions. Second operand has 2893 states, 2893 states have (on average 1.4645696508814379) internal successors, (4237), 2892 states have internal predecessors, (4237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,200 INFO L74 IsIncluded]: Start isIncluded. First operand 3886 states and 5661 transitions. Second operand has 2893 states, 2893 states have (on average 1.4645696508814379) internal successors, (4237), 2892 states have internal predecessors, (4237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,202 INFO L87 Difference]: Start difference. First operand 3886 states and 5661 transitions. Second operand has 2893 states, 2893 states have (on average 1.4645696508814379) internal successors, (4237), 2892 states have internal predecessors, (4237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,509 INFO L93 Difference]: Finished difference Result 3886 states and 5661 transitions. [2022-02-21 04:24:20,510 INFO L276 IsEmpty]: Start isEmpty. Operand 3886 states and 5661 transitions. [2022-02-21 04:24:20,513 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:20,513 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:20,517 INFO L74 IsIncluded]: Start isIncluded. First operand has 2893 states, 2893 states have (on average 1.4645696508814379) internal successors, (4237), 2892 states have internal predecessors, (4237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3886 states and 5661 transitions. [2022-02-21 04:24:20,518 INFO L87 Difference]: Start difference. First operand has 2893 states, 2893 states have (on average 1.4645696508814379) internal successors, (4237), 2892 states have internal predecessors, (4237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3886 states and 5661 transitions. [2022-02-21 04:24:20,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,846 INFO L93 Difference]: Finished difference Result 3886 states and 5661 transitions. [2022-02-21 04:24:20,846 INFO L276 IsEmpty]: Start isEmpty. Operand 3886 states and 5661 transitions. [2022-02-21 04:24:20,849 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:20,849 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:20,849 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:20,849 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:20,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2893 states, 2893 states have (on average 1.4645696508814379) internal successors, (4237), 2892 states have internal predecessors, (4237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2893 states to 2893 states and 4237 transitions. [2022-02-21 04:24:21,028 INFO L704 BuchiCegarLoop]: Abstraction has 2893 states and 4237 transitions. [2022-02-21 04:24:21,028 INFO L587 BuchiCegarLoop]: Abstraction has 2893 states and 4237 transitions. [2022-02-21 04:24:21,028 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:24:21,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2893 states and 4237 transitions. [2022-02-21 04:24:21,034 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2793 [2022-02-21 04:24:21,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:21,034 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:21,035 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:21,035 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:21,035 INFO L791 eck$LassoCheckResult]: Stem: 31318#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 31273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 31213#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30635#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30631#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 30632#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31154#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31293#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30722#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30723#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30876#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30741#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30742#L670 assume !(0 == ~M_E~0); 31115#L670-2 assume !(0 == ~T1_E~0); 31062#L675-1 assume !(0 == ~T2_E~0); 31063#L680-1 assume !(0 == ~T3_E~0); 31153#L685-1 assume !(0 == ~T4_E~0); 31118#L690-1 assume !(0 == ~T5_E~0); 31119#L695-1 assume !(0 == ~T6_E~0); 31188#L700-1 assume !(0 == ~E_1~0); 31179#L705-1 assume !(0 == ~E_2~0); 31180#L710-1 assume !(0 == ~E_3~0); 31060#L715-1 assume !(0 == ~E_4~0); 30984#L720-1 assume !(0 == ~E_5~0); 30985#L725-1 assume !(0 == ~E_6~0); 31038#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31086#L320 assume !(1 == ~m_pc~0); 31210#L320-2 is_master_triggered_~__retres1~0#1 := 0; 30919#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30920#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30877#L825 assume !(0 != activate_threads_~tmp~1#1); 30878#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30883#L339 assume !(1 == ~t1_pc~0); 30884#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30861#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30862#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30744#L833 assume !(0 != activate_threads_~tmp___0~0#1); 30745#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30656#L358 assume !(1 == ~t2_pc~0); 30657#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31175#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31116#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31043#L841 assume !(0 != activate_threads_~tmp___1~0#1); 30872#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30873#L377 assume !(1 == ~t3_pc~0); 31135#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31136#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31131#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30881#L849 assume !(0 != activate_threads_~tmp___2~0#1); 30882#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30828#L396 assume 1 == ~t4_pc~0; 30829#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30658#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30659#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31076#L857 assume !(0 != activate_threads_~tmp___3~0#1); 30798#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30799#L415 assume 1 == ~t5_pc~0; 30863#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30907#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31087#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31217#L865 assume !(0 != activate_threads_~tmp___4~0#1); 30700#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30701#L434 assume !(1 == ~t6_pc~0); 31017#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31018#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31165#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31166#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30895#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30896#L743 assume !(1 == ~M_E~0); 30791#L743-2 assume !(1 == ~T1_E~0); 30792#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31079#L753-1 assume !(1 == ~T3_E~0); 31080#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31241#L763-1 assume !(1 == ~T5_E~0); 31242#L768-1 assume !(1 == ~T6_E~0); 30889#L773-1 assume !(1 == ~E_1~0); 30890#L778-1 assume !(1 == ~E_2~0); 30869#L783-1 assume !(1 == ~E_3~0); 30870#L788-1 assume !(1 == ~E_4~0); 31150#L793-1 assume !(1 == ~E_5~0); 31151#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 30761#L803-1 assume { :end_inline_reset_delta_events } true; 30762#L1024-2 [2022-02-21 04:24:21,035 INFO L793 eck$LassoCheckResult]: Loop: 30762#L1024-2 assume !false; 31049#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31104#L645 assume !false; 30982#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 30983#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 30707#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31205#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31250#L556 assume !(0 != eval_~tmp~0#1); 31320#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33501#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33500#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33499#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33498#L675-3 assume !(0 == ~T2_E~0); 33497#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33496#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33495#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33494#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33493#L700-3 assume !(0 == ~E_1~0); 33492#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33491#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33490#L715-3 assume !(0 == ~E_4~0); 33489#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33487#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33485#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33483#L320-21 assume !(1 == ~m_pc~0); 31041#L320-23 is_master_triggered_~__retres1~0#1 := 0; 31042#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30969#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30970#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31228#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30823#L339-21 assume !(1 == ~t1_pc~0); 30824#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 30927#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30800#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30682#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30683#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30781#L358-21 assume !(1 == ~t2_pc~0); 30835#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 30763#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30764#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31048#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30801#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30802#L377-21 assume !(1 == ~t3_pc~0); 31168#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 31074#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31075#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31095#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30939#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30940#L396-21 assume 1 == ~t4_pc~0; 31109#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30968#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30936#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30665#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 30666#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30916#L415-21 assume 1 == ~t5_pc~0; 30917#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30894#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30785#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30786#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30989#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30990#L434-21 assume !(1 == ~t6_pc~0); 30689#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 30690#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31215#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30910#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30911#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30905#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30906#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31261#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31069#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31009#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30929#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30930#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 31246#L773-3 assume !(1 == ~E_1~0); 30847#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30848#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31072#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31275#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31276#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31114#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 30839#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 30735#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31002#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 31003#L1043 assume !(0 == start_simulation_~tmp~3#1); 31218#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 31070#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 30854#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 31040#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 31028#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30749#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30750#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 30897#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 30762#L1024-2 [2022-02-21 04:24:21,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:21,036 INFO L85 PathProgramCache]: Analyzing trace with hash 1792674207, now seen corresponding path program 1 times [2022-02-21 04:24:21,036 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:21,036 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809400838] [2022-02-21 04:24:21,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:21,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:21,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:21,060 INFO L290 TraceCheckUtils]: 0: Hoare triple {41299#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,060 INFO L290 TraceCheckUtils]: 1: Hoare triple {41301#(<= ~t4_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,060 INFO L290 TraceCheckUtils]: 2: Hoare triple {41301#(<= ~t4_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,061 INFO L290 TraceCheckUtils]: 3: Hoare triple {41301#(<= ~t4_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,061 INFO L290 TraceCheckUtils]: 4: Hoare triple {41301#(<= ~t4_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,061 INFO L290 TraceCheckUtils]: 5: Hoare triple {41301#(<= ~t4_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,061 INFO L290 TraceCheckUtils]: 6: Hoare triple {41301#(<= ~t4_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,062 INFO L290 TraceCheckUtils]: 7: Hoare triple {41301#(<= ~t4_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,062 INFO L290 TraceCheckUtils]: 8: Hoare triple {41301#(<= ~t4_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,062 INFO L290 TraceCheckUtils]: 9: Hoare triple {41301#(<= ~t4_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,062 INFO L290 TraceCheckUtils]: 10: Hoare triple {41301#(<= ~t4_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,063 INFO L290 TraceCheckUtils]: 11: Hoare triple {41301#(<= ~t4_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,063 INFO L290 TraceCheckUtils]: 12: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~M_E~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,063 INFO L290 TraceCheckUtils]: 13: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~T1_E~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,063 INFO L290 TraceCheckUtils]: 14: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~T2_E~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,064 INFO L290 TraceCheckUtils]: 15: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~T3_E~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,064 INFO L290 TraceCheckUtils]: 16: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~T4_E~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,064 INFO L290 TraceCheckUtils]: 17: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~T5_E~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,064 INFO L290 TraceCheckUtils]: 18: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~T6_E~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,064 INFO L290 TraceCheckUtils]: 19: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~E_1~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,065 INFO L290 TraceCheckUtils]: 20: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~E_2~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,065 INFO L290 TraceCheckUtils]: 21: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~E_3~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,065 INFO L290 TraceCheckUtils]: 22: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~E_4~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,065 INFO L290 TraceCheckUtils]: 23: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~E_5~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,066 INFO L290 TraceCheckUtils]: 24: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 == ~E_6~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,066 INFO L290 TraceCheckUtils]: 25: Hoare triple {41301#(<= ~t4_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,066 INFO L290 TraceCheckUtils]: 26: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(1 == ~m_pc~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,066 INFO L290 TraceCheckUtils]: 27: Hoare triple {41301#(<= ~t4_pc~0 0)} is_master_triggered_~__retres1~0#1 := 0; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,067 INFO L290 TraceCheckUtils]: 28: Hoare triple {41301#(<= ~t4_pc~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,067 INFO L290 TraceCheckUtils]: 29: Hoare triple {41301#(<= ~t4_pc~0 0)} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,067 INFO L290 TraceCheckUtils]: 30: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp~1#1); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,067 INFO L290 TraceCheckUtils]: 31: Hoare triple {41301#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,068 INFO L290 TraceCheckUtils]: 32: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(1 == ~t1_pc~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,068 INFO L290 TraceCheckUtils]: 33: Hoare triple {41301#(<= ~t4_pc~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,068 INFO L290 TraceCheckUtils]: 34: Hoare triple {41301#(<= ~t4_pc~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,068 INFO L290 TraceCheckUtils]: 35: Hoare triple {41301#(<= ~t4_pc~0 0)} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,069 INFO L290 TraceCheckUtils]: 36: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,069 INFO L290 TraceCheckUtils]: 37: Hoare triple {41301#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,069 INFO L290 TraceCheckUtils]: 38: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(1 == ~t2_pc~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,069 INFO L290 TraceCheckUtils]: 39: Hoare triple {41301#(<= ~t4_pc~0 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,070 INFO L290 TraceCheckUtils]: 40: Hoare triple {41301#(<= ~t4_pc~0 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,070 INFO L290 TraceCheckUtils]: 41: Hoare triple {41301#(<= ~t4_pc~0 0)} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,070 INFO L290 TraceCheckUtils]: 42: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___1~0#1); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,070 INFO L290 TraceCheckUtils]: 43: Hoare triple {41301#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,070 INFO L290 TraceCheckUtils]: 44: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(1 == ~t3_pc~0); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,071 INFO L290 TraceCheckUtils]: 45: Hoare triple {41301#(<= ~t4_pc~0 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,071 INFO L290 TraceCheckUtils]: 46: Hoare triple {41301#(<= ~t4_pc~0 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,071 INFO L290 TraceCheckUtils]: 47: Hoare triple {41301#(<= ~t4_pc~0 0)} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,071 INFO L290 TraceCheckUtils]: 48: Hoare triple {41301#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___2~0#1); {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,072 INFO L290 TraceCheckUtils]: 49: Hoare triple {41301#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {41301#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:21,072 INFO L290 TraceCheckUtils]: 50: Hoare triple {41301#(<= ~t4_pc~0 0)} assume 1 == ~t4_pc~0; {41300#false} is VALID [2022-02-21 04:24:21,072 INFO L290 TraceCheckUtils]: 51: Hoare triple {41300#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {41300#false} is VALID [2022-02-21 04:24:21,072 INFO L290 TraceCheckUtils]: 52: Hoare triple {41300#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {41300#false} is VALID [2022-02-21 04:24:21,072 INFO L290 TraceCheckUtils]: 53: Hoare triple {41300#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {41300#false} is VALID [2022-02-21 04:24:21,072 INFO L290 TraceCheckUtils]: 54: Hoare triple {41300#false} assume !(0 != activate_threads_~tmp___3~0#1); {41300#false} is VALID [2022-02-21 04:24:21,073 INFO L290 TraceCheckUtils]: 55: Hoare triple {41300#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {41300#false} is VALID [2022-02-21 04:24:21,073 INFO L290 TraceCheckUtils]: 56: Hoare triple {41300#false} assume 1 == ~t5_pc~0; {41300#false} is VALID [2022-02-21 04:24:21,073 INFO L290 TraceCheckUtils]: 57: Hoare triple {41300#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {41300#false} is VALID [2022-02-21 04:24:21,073 INFO L290 TraceCheckUtils]: 58: Hoare triple {41300#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {41300#false} is VALID [2022-02-21 04:24:21,073 INFO L290 TraceCheckUtils]: 59: Hoare triple {41300#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {41300#false} is VALID [2022-02-21 04:24:21,073 INFO L290 TraceCheckUtils]: 60: Hoare triple {41300#false} assume !(0 != activate_threads_~tmp___4~0#1); {41300#false} is VALID [2022-02-21 04:24:21,073 INFO L290 TraceCheckUtils]: 61: Hoare triple {41300#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {41300#false} is VALID [2022-02-21 04:24:21,073 INFO L290 TraceCheckUtils]: 62: Hoare triple {41300#false} assume !(1 == ~t6_pc~0); {41300#false} is VALID [2022-02-21 04:24:21,073 INFO L290 TraceCheckUtils]: 63: Hoare triple {41300#false} is_transmit6_triggered_~__retres1~6#1 := 0; {41300#false} is VALID [2022-02-21 04:24:21,074 INFO L290 TraceCheckUtils]: 64: Hoare triple {41300#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {41300#false} is VALID [2022-02-21 04:24:21,074 INFO L290 TraceCheckUtils]: 65: Hoare triple {41300#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {41300#false} is VALID [2022-02-21 04:24:21,074 INFO L290 TraceCheckUtils]: 66: Hoare triple {41300#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {41300#false} is VALID [2022-02-21 04:24:21,074 INFO L290 TraceCheckUtils]: 67: Hoare triple {41300#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {41300#false} is VALID [2022-02-21 04:24:21,074 INFO L290 TraceCheckUtils]: 68: Hoare triple {41300#false} assume !(1 == ~M_E~0); {41300#false} is VALID [2022-02-21 04:24:21,074 INFO L290 TraceCheckUtils]: 69: Hoare triple {41300#false} assume !(1 == ~T1_E~0); {41300#false} is VALID [2022-02-21 04:24:21,074 INFO L290 TraceCheckUtils]: 70: Hoare triple {41300#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {41300#false} is VALID [2022-02-21 04:24:21,074 INFO L290 TraceCheckUtils]: 71: Hoare triple {41300#false} assume !(1 == ~T3_E~0); {41300#false} is VALID [2022-02-21 04:24:21,074 INFO L290 TraceCheckUtils]: 72: Hoare triple {41300#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {41300#false} is VALID [2022-02-21 04:24:21,074 INFO L290 TraceCheckUtils]: 73: Hoare triple {41300#false} assume !(1 == ~T5_E~0); {41300#false} is VALID [2022-02-21 04:24:21,075 INFO L290 TraceCheckUtils]: 74: Hoare triple {41300#false} assume !(1 == ~T6_E~0); {41300#false} is VALID [2022-02-21 04:24:21,075 INFO L290 TraceCheckUtils]: 75: Hoare triple {41300#false} assume !(1 == ~E_1~0); {41300#false} is VALID [2022-02-21 04:24:21,075 INFO L290 TraceCheckUtils]: 76: Hoare triple {41300#false} assume !(1 == ~E_2~0); {41300#false} is VALID [2022-02-21 04:24:21,075 INFO L290 TraceCheckUtils]: 77: Hoare triple {41300#false} assume !(1 == ~E_3~0); {41300#false} is VALID [2022-02-21 04:24:21,075 INFO L290 TraceCheckUtils]: 78: Hoare triple {41300#false} assume !(1 == ~E_4~0); {41300#false} is VALID [2022-02-21 04:24:21,075 INFO L290 TraceCheckUtils]: 79: Hoare triple {41300#false} assume !(1 == ~E_5~0); {41300#false} is VALID [2022-02-21 04:24:21,075 INFO L290 TraceCheckUtils]: 80: Hoare triple {41300#false} assume 1 == ~E_6~0;~E_6~0 := 2; {41300#false} is VALID [2022-02-21 04:24:21,075 INFO L290 TraceCheckUtils]: 81: Hoare triple {41300#false} assume { :end_inline_reset_delta_events } true; {41300#false} is VALID [2022-02-21 04:24:21,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:21,076 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:21,076 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809400838] [2022-02-21 04:24:21,076 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [809400838] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:21,076 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:21,076 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:21,076 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [456659192] [2022-02-21 04:24:21,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:21,077 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:21,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:21,077 INFO L85 PathProgramCache]: Analyzing trace with hash -422403870, now seen corresponding path program 1 times [2022-02-21 04:24:21,077 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:21,077 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343394409] [2022-02-21 04:24:21,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:21,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:21,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:21,102 INFO L290 TraceCheckUtils]: 0: Hoare triple {41302#true} assume !false; {41302#true} is VALID [2022-02-21 04:24:21,102 INFO L290 TraceCheckUtils]: 1: Hoare triple {41302#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {41302#true} is VALID [2022-02-21 04:24:21,102 INFO L290 TraceCheckUtils]: 2: Hoare triple {41302#true} assume !false; {41302#true} is VALID [2022-02-21 04:24:21,102 INFO L290 TraceCheckUtils]: 3: Hoare triple {41302#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {41302#true} is VALID [2022-02-21 04:24:21,103 INFO L290 TraceCheckUtils]: 4: Hoare triple {41302#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {41304#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~7#1|)} is VALID [2022-02-21 04:24:21,103 INFO L290 TraceCheckUtils]: 5: Hoare triple {41304#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~7#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {41305#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:21,103 INFO L290 TraceCheckUtils]: 6: Hoare triple {41305#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {41306#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:21,104 INFO L290 TraceCheckUtils]: 7: Hoare triple {41306#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {41303#false} is VALID [2022-02-21 04:24:21,104 INFO L290 TraceCheckUtils]: 8: Hoare triple {41303#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {41303#false} is VALID [2022-02-21 04:24:21,104 INFO L290 TraceCheckUtils]: 9: Hoare triple {41303#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {41303#false} is VALID [2022-02-21 04:24:21,104 INFO L290 TraceCheckUtils]: 10: Hoare triple {41303#false} assume 0 == ~M_E~0;~M_E~0 := 1; {41303#false} is VALID [2022-02-21 04:24:21,104 INFO L290 TraceCheckUtils]: 11: Hoare triple {41303#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {41303#false} is VALID [2022-02-21 04:24:21,104 INFO L290 TraceCheckUtils]: 12: Hoare triple {41303#false} assume !(0 == ~T2_E~0); {41303#false} is VALID [2022-02-21 04:24:21,104 INFO L290 TraceCheckUtils]: 13: Hoare triple {41303#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {41303#false} is VALID [2022-02-21 04:24:21,104 INFO L290 TraceCheckUtils]: 14: Hoare triple {41303#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {41303#false} is VALID [2022-02-21 04:24:21,104 INFO L290 TraceCheckUtils]: 15: Hoare triple {41303#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {41303#false} is VALID [2022-02-21 04:24:21,104 INFO L290 TraceCheckUtils]: 16: Hoare triple {41303#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {41303#false} is VALID [2022-02-21 04:24:21,105 INFO L290 TraceCheckUtils]: 17: Hoare triple {41303#false} assume !(0 == ~E_1~0); {41303#false} is VALID [2022-02-21 04:24:21,105 INFO L290 TraceCheckUtils]: 18: Hoare triple {41303#false} assume 0 == ~E_2~0;~E_2~0 := 1; {41303#false} is VALID [2022-02-21 04:24:21,105 INFO L290 TraceCheckUtils]: 19: Hoare triple {41303#false} assume 0 == ~E_3~0;~E_3~0 := 1; {41303#false} is VALID [2022-02-21 04:24:21,105 INFO L290 TraceCheckUtils]: 20: Hoare triple {41303#false} assume !(0 == ~E_4~0); {41303#false} is VALID [2022-02-21 04:24:21,105 INFO L290 TraceCheckUtils]: 21: Hoare triple {41303#false} assume 0 == ~E_5~0;~E_5~0 := 1; {41303#false} is VALID [2022-02-21 04:24:21,105 INFO L290 TraceCheckUtils]: 22: Hoare triple {41303#false} assume 0 == ~E_6~0;~E_6~0 := 1; {41303#false} is VALID [2022-02-21 04:24:21,105 INFO L290 TraceCheckUtils]: 23: Hoare triple {41303#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {41303#false} is VALID [2022-02-21 04:24:21,105 INFO L290 TraceCheckUtils]: 24: Hoare triple {41303#false} assume !(1 == ~m_pc~0); {41303#false} is VALID [2022-02-21 04:24:21,105 INFO L290 TraceCheckUtils]: 25: Hoare triple {41303#false} is_master_triggered_~__retres1~0#1 := 0; {41303#false} is VALID [2022-02-21 04:24:21,106 INFO L290 TraceCheckUtils]: 26: Hoare triple {41303#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {41303#false} is VALID [2022-02-21 04:24:21,106 INFO L290 TraceCheckUtils]: 27: Hoare triple {41303#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {41303#false} is VALID [2022-02-21 04:24:21,106 INFO L290 TraceCheckUtils]: 28: Hoare triple {41303#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {41303#false} is VALID [2022-02-21 04:24:21,106 INFO L290 TraceCheckUtils]: 29: Hoare triple {41303#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {41303#false} is VALID [2022-02-21 04:24:21,106 INFO L290 TraceCheckUtils]: 30: Hoare triple {41303#false} assume !(1 == ~t1_pc~0); {41303#false} is VALID [2022-02-21 04:24:21,106 INFO L290 TraceCheckUtils]: 31: Hoare triple {41303#false} is_transmit1_triggered_~__retres1~1#1 := 0; {41303#false} is VALID [2022-02-21 04:24:21,106 INFO L290 TraceCheckUtils]: 32: Hoare triple {41303#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {41303#false} is VALID [2022-02-21 04:24:21,106 INFO L290 TraceCheckUtils]: 33: Hoare triple {41303#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {41303#false} is VALID [2022-02-21 04:24:21,106 INFO L290 TraceCheckUtils]: 34: Hoare triple {41303#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {41303#false} is VALID [2022-02-21 04:24:21,107 INFO L290 TraceCheckUtils]: 35: Hoare triple {41303#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {41303#false} is VALID [2022-02-21 04:24:21,107 INFO L290 TraceCheckUtils]: 36: Hoare triple {41303#false} assume !(1 == ~t2_pc~0); {41303#false} is VALID [2022-02-21 04:24:21,107 INFO L290 TraceCheckUtils]: 37: Hoare triple {41303#false} is_transmit2_triggered_~__retres1~2#1 := 0; {41303#false} is VALID [2022-02-21 04:24:21,107 INFO L290 TraceCheckUtils]: 38: Hoare triple {41303#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {41303#false} is VALID [2022-02-21 04:24:21,107 INFO L290 TraceCheckUtils]: 39: Hoare triple {41303#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {41303#false} is VALID [2022-02-21 04:24:21,107 INFO L290 TraceCheckUtils]: 40: Hoare triple {41303#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {41303#false} is VALID [2022-02-21 04:24:21,107 INFO L290 TraceCheckUtils]: 41: Hoare triple {41303#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {41303#false} is VALID [2022-02-21 04:24:21,107 INFO L290 TraceCheckUtils]: 42: Hoare triple {41303#false} assume !(1 == ~t3_pc~0); {41303#false} is VALID [2022-02-21 04:24:21,107 INFO L290 TraceCheckUtils]: 43: Hoare triple {41303#false} is_transmit3_triggered_~__retres1~3#1 := 0; {41303#false} is VALID [2022-02-21 04:24:21,108 INFO L290 TraceCheckUtils]: 44: Hoare triple {41303#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {41303#false} is VALID [2022-02-21 04:24:21,108 INFO L290 TraceCheckUtils]: 45: Hoare triple {41303#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {41303#false} is VALID [2022-02-21 04:24:21,108 INFO L290 TraceCheckUtils]: 46: Hoare triple {41303#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {41303#false} is VALID [2022-02-21 04:24:21,108 INFO L290 TraceCheckUtils]: 47: Hoare triple {41303#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {41303#false} is VALID [2022-02-21 04:24:21,108 INFO L290 TraceCheckUtils]: 48: Hoare triple {41303#false} assume 1 == ~t4_pc~0; {41303#false} is VALID [2022-02-21 04:24:21,108 INFO L290 TraceCheckUtils]: 49: Hoare triple {41303#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {41303#false} is VALID [2022-02-21 04:24:21,108 INFO L290 TraceCheckUtils]: 50: Hoare triple {41303#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {41303#false} is VALID [2022-02-21 04:24:21,108 INFO L290 TraceCheckUtils]: 51: Hoare triple {41303#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {41303#false} is VALID [2022-02-21 04:24:21,108 INFO L290 TraceCheckUtils]: 52: Hoare triple {41303#false} assume !(0 != activate_threads_~tmp___3~0#1); {41303#false} is VALID [2022-02-21 04:24:21,108 INFO L290 TraceCheckUtils]: 53: Hoare triple {41303#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {41303#false} is VALID [2022-02-21 04:24:21,109 INFO L290 TraceCheckUtils]: 54: Hoare triple {41303#false} assume 1 == ~t5_pc~0; {41303#false} is VALID [2022-02-21 04:24:21,109 INFO L290 TraceCheckUtils]: 55: Hoare triple {41303#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {41303#false} is VALID [2022-02-21 04:24:21,109 INFO L290 TraceCheckUtils]: 56: Hoare triple {41303#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {41303#false} is VALID [2022-02-21 04:24:21,109 INFO L290 TraceCheckUtils]: 57: Hoare triple {41303#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {41303#false} is VALID [2022-02-21 04:24:21,109 INFO L290 TraceCheckUtils]: 58: Hoare triple {41303#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {41303#false} is VALID [2022-02-21 04:24:21,109 INFO L290 TraceCheckUtils]: 59: Hoare triple {41303#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {41303#false} is VALID [2022-02-21 04:24:21,109 INFO L290 TraceCheckUtils]: 60: Hoare triple {41303#false} assume !(1 == ~t6_pc~0); {41303#false} is VALID [2022-02-21 04:24:21,109 INFO L290 TraceCheckUtils]: 61: Hoare triple {41303#false} is_transmit6_triggered_~__retres1~6#1 := 0; {41303#false} is VALID [2022-02-21 04:24:21,109 INFO L290 TraceCheckUtils]: 62: Hoare triple {41303#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {41303#false} is VALID [2022-02-21 04:24:21,110 INFO L290 TraceCheckUtils]: 63: Hoare triple {41303#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {41303#false} is VALID [2022-02-21 04:24:21,110 INFO L290 TraceCheckUtils]: 64: Hoare triple {41303#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {41303#false} is VALID [2022-02-21 04:24:21,110 INFO L290 TraceCheckUtils]: 65: Hoare triple {41303#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {41303#false} is VALID [2022-02-21 04:24:21,110 INFO L290 TraceCheckUtils]: 66: Hoare triple {41303#false} assume 1 == ~M_E~0;~M_E~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,110 INFO L290 TraceCheckUtils]: 67: Hoare triple {41303#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,110 INFO L290 TraceCheckUtils]: 68: Hoare triple {41303#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,110 INFO L290 TraceCheckUtils]: 69: Hoare triple {41303#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,110 INFO L290 TraceCheckUtils]: 70: Hoare triple {41303#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,110 INFO L290 TraceCheckUtils]: 71: Hoare triple {41303#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,111 INFO L290 TraceCheckUtils]: 72: Hoare triple {41303#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,111 INFO L290 TraceCheckUtils]: 73: Hoare triple {41303#false} assume !(1 == ~E_1~0); {41303#false} is VALID [2022-02-21 04:24:21,111 INFO L290 TraceCheckUtils]: 74: Hoare triple {41303#false} assume 1 == ~E_2~0;~E_2~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,111 INFO L290 TraceCheckUtils]: 75: Hoare triple {41303#false} assume 1 == ~E_3~0;~E_3~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,111 INFO L290 TraceCheckUtils]: 76: Hoare triple {41303#false} assume 1 == ~E_4~0;~E_4~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,111 INFO L290 TraceCheckUtils]: 77: Hoare triple {41303#false} assume 1 == ~E_5~0;~E_5~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,111 INFO L290 TraceCheckUtils]: 78: Hoare triple {41303#false} assume 1 == ~E_6~0;~E_6~0 := 2; {41303#false} is VALID [2022-02-21 04:24:21,111 INFO L290 TraceCheckUtils]: 79: Hoare triple {41303#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {41303#false} is VALID [2022-02-21 04:24:21,111 INFO L290 TraceCheckUtils]: 80: Hoare triple {41303#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {41303#false} is VALID [2022-02-21 04:24:21,112 INFO L290 TraceCheckUtils]: 81: Hoare triple {41303#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {41303#false} is VALID [2022-02-21 04:24:21,112 INFO L290 TraceCheckUtils]: 82: Hoare triple {41303#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {41303#false} is VALID [2022-02-21 04:24:21,112 INFO L290 TraceCheckUtils]: 83: Hoare triple {41303#false} assume !(0 == start_simulation_~tmp~3#1); {41303#false} is VALID [2022-02-21 04:24:21,112 INFO L290 TraceCheckUtils]: 84: Hoare triple {41303#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {41303#false} is VALID [2022-02-21 04:24:21,112 INFO L290 TraceCheckUtils]: 85: Hoare triple {41303#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {41303#false} is VALID [2022-02-21 04:24:21,112 INFO L290 TraceCheckUtils]: 86: Hoare triple {41303#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {41303#false} is VALID [2022-02-21 04:24:21,112 INFO L290 TraceCheckUtils]: 87: Hoare triple {41303#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {41303#false} is VALID [2022-02-21 04:24:21,112 INFO L290 TraceCheckUtils]: 88: Hoare triple {41303#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {41303#false} is VALID [2022-02-21 04:24:21,112 INFO L290 TraceCheckUtils]: 89: Hoare triple {41303#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {41303#false} is VALID [2022-02-21 04:24:21,112 INFO L290 TraceCheckUtils]: 90: Hoare triple {41303#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {41303#false} is VALID [2022-02-21 04:24:21,113 INFO L290 TraceCheckUtils]: 91: Hoare triple {41303#false} assume !(0 != start_simulation_~tmp___0~1#1); {41303#false} is VALID [2022-02-21 04:24:21,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:21,113 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:21,113 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [343394409] [2022-02-21 04:24:21,113 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [343394409] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:21,113 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:21,113 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:21,114 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [746470851] [2022-02-21 04:24:21,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:21,114 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:21,114 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:21,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:21,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:21,115 INFO L87 Difference]: Start difference. First operand 2893 states and 4237 transitions. cyclomatic complexity: 1347 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,348 INFO L93 Difference]: Finished difference Result 5347 states and 7793 transitions. [2022-02-21 04:24:22,348 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:22,348 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,431 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:22,431 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5347 states and 7793 transitions. [2022-02-21 04:24:23,063 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5234 [2022-02-21 04:24:23,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5347 states to 5347 states and 7793 transitions. [2022-02-21 04:24:23,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5347 [2022-02-21 04:24:23,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5347 [2022-02-21 04:24:23,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5347 states and 7793 transitions. [2022-02-21 04:24:23,655 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:23,655 INFO L681 BuchiCegarLoop]: Abstraction has 5347 states and 7793 transitions. [2022-02-21 04:24:23,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5347 states and 7793 transitions. [2022-02-21 04:24:23,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5347 to 5335. [2022-02-21 04:24:23,713 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:23,720 INFO L82 GeneralOperation]: Start isEquivalent. First operand 5347 states and 7793 transitions. Second operand has 5335 states, 5335 states have (on average 1.458481724461106) internal successors, (7781), 5334 states have internal predecessors, (7781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,725 INFO L74 IsIncluded]: Start isIncluded. First operand 5347 states and 7793 transitions. Second operand has 5335 states, 5335 states have (on average 1.458481724461106) internal successors, (7781), 5334 states have internal predecessors, (7781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,731 INFO L87 Difference]: Start difference. First operand 5347 states and 7793 transitions. Second operand has 5335 states, 5335 states have (on average 1.458481724461106) internal successors, (7781), 5334 states have internal predecessors, (7781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,322 INFO L93 Difference]: Finished difference Result 5347 states and 7793 transitions. [2022-02-21 04:24:24,322 INFO L276 IsEmpty]: Start isEmpty. Operand 5347 states and 7793 transitions. [2022-02-21 04:24:24,325 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:24,325 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:24,330 INFO L74 IsIncluded]: Start isIncluded. First operand has 5335 states, 5335 states have (on average 1.458481724461106) internal successors, (7781), 5334 states have internal predecessors, (7781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5347 states and 7793 transitions. [2022-02-21 04:24:24,333 INFO L87 Difference]: Start difference. First operand has 5335 states, 5335 states have (on average 1.458481724461106) internal successors, (7781), 5334 states have internal predecessors, (7781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5347 states and 7793 transitions. [2022-02-21 04:24:24,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,932 INFO L93 Difference]: Finished difference Result 5347 states and 7793 transitions. [2022-02-21 04:24:24,932 INFO L276 IsEmpty]: Start isEmpty. Operand 5347 states and 7793 transitions. [2022-02-21 04:24:24,936 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:24,936 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:24,936 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:24,936 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:24,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5335 states, 5335 states have (on average 1.458481724461106) internal successors, (7781), 5334 states have internal predecessors, (7781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5335 states to 5335 states and 7781 transitions. [2022-02-21 04:24:25,587 INFO L704 BuchiCegarLoop]: Abstraction has 5335 states and 7781 transitions. [2022-02-21 04:24:25,587 INFO L587 BuchiCegarLoop]: Abstraction has 5335 states and 7781 transitions. [2022-02-21 04:24:25,587 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:24:25,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5335 states and 7781 transitions. [2022-02-21 04:24:25,596 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5222 [2022-02-21 04:24:25,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:25,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:25,597 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:25,597 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:25,598 INFO L791 eck$LassoCheckResult]: Stem: 47356#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 47317#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 47245#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46658#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46654#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 46655#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 47186#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47336#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46746#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46747#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46905#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46765#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46766#L670 assume !(0 == ~M_E~0); 47144#L670-2 assume !(0 == ~T1_E~0); 47088#L675-1 assume !(0 == ~T2_E~0); 47089#L680-1 assume !(0 == ~T3_E~0); 47185#L685-1 assume !(0 == ~T4_E~0); 47148#L690-1 assume !(0 == ~T5_E~0); 47149#L695-1 assume !(0 == ~T6_E~0); 47223#L700-1 assume !(0 == ~E_1~0); 47213#L705-1 assume !(0 == ~E_2~0); 47214#L710-1 assume !(0 == ~E_3~0); 47086#L715-1 assume !(0 == ~E_4~0); 47011#L720-1 assume !(0 == ~E_5~0); 47012#L725-1 assume !(0 == ~E_6~0); 47065#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47113#L320 assume !(1 == ~m_pc~0); 47240#L320-2 is_master_triggered_~__retres1~0#1 := 0; 46948#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46949#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46906#L825 assume !(0 != activate_threads_~tmp~1#1); 46907#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46912#L339 assume !(1 == ~t1_pc~0); 46913#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46889#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46890#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46768#L833 assume !(0 != activate_threads_~tmp___0~0#1); 46769#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46679#L358 assume !(1 == ~t2_pc~0); 46680#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47207#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47146#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 47069#L841 assume !(0 != activate_threads_~tmp___1~0#1); 46901#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46902#L377 assume !(1 == ~t3_pc~0); 47165#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47166#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47161#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46910#L849 assume !(0 != activate_threads_~tmp___2~0#1); 46911#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46855#L396 assume !(1 == ~t4_pc~0); 46856#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46681#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46682#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47102#L857 assume !(0 != activate_threads_~tmp___3~0#1); 46823#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46824#L415 assume 1 == ~t5_pc~0; 46891#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46936#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47114#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47250#L865 assume !(0 != activate_threads_~tmp___4~0#1); 46724#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46725#L434 assume !(1 == ~t6_pc~0); 47044#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 47045#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47199#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47200#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46924#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46925#L743 assume !(1 == ~M_E~0); 46815#L743-2 assume !(1 == ~T1_E~0); 46816#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47105#L753-1 assume !(1 == ~T3_E~0); 47106#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47226#L763-1 assume !(1 == ~T5_E~0); 47278#L768-1 assume !(1 == ~T6_E~0); 46918#L773-1 assume !(1 == ~E_1~0); 46919#L778-1 assume !(1 == ~E_2~0); 46898#L783-1 assume !(1 == ~E_3~0); 46899#L788-1 assume !(1 == ~E_4~0); 47183#L793-1 assume !(1 == ~E_5~0); 47137#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 47138#L803-1 assume { :end_inline_reset_delta_events } true; 50846#L1024-2 [2022-02-21 04:24:25,598 INFO L793 eck$LassoCheckResult]: Loop: 50846#L1024-2 assume !false; 50845#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50840#L645 assume !false; 50839#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 50838#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 50831#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 50830#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 50828#L556 assume !(0 != eval_~tmp~0#1); 50829#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51341#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51339#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51337#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51335#L675-3 assume !(0 == ~T2_E~0); 51333#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51331#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51328#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51326#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51324#L700-3 assume !(0 == ~E_1~0); 51322#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51320#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51318#L715-3 assume !(0 == ~E_4~0); 51316#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51314#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51312#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51310#L320-21 assume !(1 == ~m_pc~0); 51308#L320-23 is_master_triggered_~__retres1~0#1 := 0; 51306#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51303#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 51301#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51299#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51297#L339-21 assume !(1 == ~t1_pc~0); 51294#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 51292#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51289#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 51287#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51285#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51283#L358-21 assume !(1 == ~t2_pc~0); 50687#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 51278#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51276#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 51274#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51269#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51266#L377-21 assume 1 == ~t3_pc~0; 51264#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51261#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51259#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 51257#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51255#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51253#L396-21 assume !(1 == ~t4_pc~0); 51251#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 51249#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51247#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 51245#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 51243#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51241#L415-21 assume 1 == ~t5_pc~0; 51237#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51235#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51233#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 51231#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51229#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51228#L434-21 assume !(1 == ~t6_pc~0); 51226#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 51225#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51224#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51222#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51220#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51218#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51216#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51214#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47335#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51211#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51208#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51206#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51204#L773-3 assume !(1 == ~E_1~0); 47285#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51201#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51198#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51196#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51194#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51192#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 50884#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 50879#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 50877#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 50873#L1043 assume !(0 == start_simulation_~tmp~3#1); 50872#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 50864#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 50858#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 50856#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 50854#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50852#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50851#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 50850#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 50846#L1024-2 [2022-02-21 04:24:25,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:25,598 INFO L85 PathProgramCache]: Analyzing trace with hash -1583318466, now seen corresponding path program 1 times [2022-02-21 04:24:25,598 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:25,598 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330177065] [2022-02-21 04:24:25,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:25,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:25,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:25,648 INFO L290 TraceCheckUtils]: 0: Hoare triple {62686#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,649 INFO L290 TraceCheckUtils]: 1: Hoare triple {62688#(<= ~t5_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,649 INFO L290 TraceCheckUtils]: 2: Hoare triple {62688#(<= ~t5_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,649 INFO L290 TraceCheckUtils]: 3: Hoare triple {62688#(<= ~t5_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,650 INFO L290 TraceCheckUtils]: 4: Hoare triple {62688#(<= ~t5_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,650 INFO L290 TraceCheckUtils]: 5: Hoare triple {62688#(<= ~t5_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,650 INFO L290 TraceCheckUtils]: 6: Hoare triple {62688#(<= ~t5_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,650 INFO L290 TraceCheckUtils]: 7: Hoare triple {62688#(<= ~t5_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,651 INFO L290 TraceCheckUtils]: 8: Hoare triple {62688#(<= ~t5_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,651 INFO L290 TraceCheckUtils]: 9: Hoare triple {62688#(<= ~t5_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,651 INFO L290 TraceCheckUtils]: 10: Hoare triple {62688#(<= ~t5_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,651 INFO L290 TraceCheckUtils]: 11: Hoare triple {62688#(<= ~t5_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,652 INFO L290 TraceCheckUtils]: 12: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~M_E~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,652 INFO L290 TraceCheckUtils]: 13: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~T1_E~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,652 INFO L290 TraceCheckUtils]: 14: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~T2_E~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,652 INFO L290 TraceCheckUtils]: 15: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~T3_E~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,653 INFO L290 TraceCheckUtils]: 16: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~T4_E~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,653 INFO L290 TraceCheckUtils]: 17: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~T5_E~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,653 INFO L290 TraceCheckUtils]: 18: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~T6_E~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,653 INFO L290 TraceCheckUtils]: 19: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~E_1~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,654 INFO L290 TraceCheckUtils]: 20: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~E_2~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,654 INFO L290 TraceCheckUtils]: 21: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~E_3~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,654 INFO L290 TraceCheckUtils]: 22: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~E_4~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,654 INFO L290 TraceCheckUtils]: 23: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~E_5~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,655 INFO L290 TraceCheckUtils]: 24: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 == ~E_6~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,655 INFO L290 TraceCheckUtils]: 25: Hoare triple {62688#(<= ~t5_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,655 INFO L290 TraceCheckUtils]: 26: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(1 == ~m_pc~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,655 INFO L290 TraceCheckUtils]: 27: Hoare triple {62688#(<= ~t5_pc~0 0)} is_master_triggered_~__retres1~0#1 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,656 INFO L290 TraceCheckUtils]: 28: Hoare triple {62688#(<= ~t5_pc~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,656 INFO L290 TraceCheckUtils]: 29: Hoare triple {62688#(<= ~t5_pc~0 0)} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,656 INFO L290 TraceCheckUtils]: 30: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 != activate_threads_~tmp~1#1); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,657 INFO L290 TraceCheckUtils]: 31: Hoare triple {62688#(<= ~t5_pc~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,657 INFO L290 TraceCheckUtils]: 32: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(1 == ~t1_pc~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,657 INFO L290 TraceCheckUtils]: 33: Hoare triple {62688#(<= ~t5_pc~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,657 INFO L290 TraceCheckUtils]: 34: Hoare triple {62688#(<= ~t5_pc~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,658 INFO L290 TraceCheckUtils]: 35: Hoare triple {62688#(<= ~t5_pc~0 0)} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,658 INFO L290 TraceCheckUtils]: 36: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,658 INFO L290 TraceCheckUtils]: 37: Hoare triple {62688#(<= ~t5_pc~0 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,658 INFO L290 TraceCheckUtils]: 38: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(1 == ~t2_pc~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,659 INFO L290 TraceCheckUtils]: 39: Hoare triple {62688#(<= ~t5_pc~0 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,659 INFO L290 TraceCheckUtils]: 40: Hoare triple {62688#(<= ~t5_pc~0 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,659 INFO L290 TraceCheckUtils]: 41: Hoare triple {62688#(<= ~t5_pc~0 0)} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,659 INFO L290 TraceCheckUtils]: 42: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 != activate_threads_~tmp___1~0#1); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,660 INFO L290 TraceCheckUtils]: 43: Hoare triple {62688#(<= ~t5_pc~0 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,660 INFO L290 TraceCheckUtils]: 44: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(1 == ~t3_pc~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,660 INFO L290 TraceCheckUtils]: 45: Hoare triple {62688#(<= ~t5_pc~0 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,660 INFO L290 TraceCheckUtils]: 46: Hoare triple {62688#(<= ~t5_pc~0 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,661 INFO L290 TraceCheckUtils]: 47: Hoare triple {62688#(<= ~t5_pc~0 0)} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,661 INFO L290 TraceCheckUtils]: 48: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 != activate_threads_~tmp___2~0#1); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,661 INFO L290 TraceCheckUtils]: 49: Hoare triple {62688#(<= ~t5_pc~0 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,661 INFO L290 TraceCheckUtils]: 50: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(1 == ~t4_pc~0); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,662 INFO L290 TraceCheckUtils]: 51: Hoare triple {62688#(<= ~t5_pc~0 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,662 INFO L290 TraceCheckUtils]: 52: Hoare triple {62688#(<= ~t5_pc~0 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,662 INFO L290 TraceCheckUtils]: 53: Hoare triple {62688#(<= ~t5_pc~0 0)} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,662 INFO L290 TraceCheckUtils]: 54: Hoare triple {62688#(<= ~t5_pc~0 0)} assume !(0 != activate_threads_~tmp___3~0#1); {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,663 INFO L290 TraceCheckUtils]: 55: Hoare triple {62688#(<= ~t5_pc~0 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {62688#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:24:25,663 INFO L290 TraceCheckUtils]: 56: Hoare triple {62688#(<= ~t5_pc~0 0)} assume 1 == ~t5_pc~0; {62687#false} is VALID [2022-02-21 04:24:25,663 INFO L290 TraceCheckUtils]: 57: Hoare triple {62687#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {62687#false} is VALID [2022-02-21 04:24:25,663 INFO L290 TraceCheckUtils]: 58: Hoare triple {62687#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {62687#false} is VALID [2022-02-21 04:24:25,663 INFO L290 TraceCheckUtils]: 59: Hoare triple {62687#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {62687#false} is VALID [2022-02-21 04:24:25,663 INFO L290 TraceCheckUtils]: 60: Hoare triple {62687#false} assume !(0 != activate_threads_~tmp___4~0#1); {62687#false} is VALID [2022-02-21 04:24:25,664 INFO L290 TraceCheckUtils]: 61: Hoare triple {62687#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {62687#false} is VALID [2022-02-21 04:24:25,664 INFO L290 TraceCheckUtils]: 62: Hoare triple {62687#false} assume !(1 == ~t6_pc~0); {62687#false} is VALID [2022-02-21 04:24:25,664 INFO L290 TraceCheckUtils]: 63: Hoare triple {62687#false} is_transmit6_triggered_~__retres1~6#1 := 0; {62687#false} is VALID [2022-02-21 04:24:25,664 INFO L290 TraceCheckUtils]: 64: Hoare triple {62687#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {62687#false} is VALID [2022-02-21 04:24:25,664 INFO L290 TraceCheckUtils]: 65: Hoare triple {62687#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {62687#false} is VALID [2022-02-21 04:24:25,664 INFO L290 TraceCheckUtils]: 66: Hoare triple {62687#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {62687#false} is VALID [2022-02-21 04:24:25,664 INFO L290 TraceCheckUtils]: 67: Hoare triple {62687#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {62687#false} is VALID [2022-02-21 04:24:25,664 INFO L290 TraceCheckUtils]: 68: Hoare triple {62687#false} assume !(1 == ~M_E~0); {62687#false} is VALID [2022-02-21 04:24:25,664 INFO L290 TraceCheckUtils]: 69: Hoare triple {62687#false} assume !(1 == ~T1_E~0); {62687#false} is VALID [2022-02-21 04:24:25,664 INFO L290 TraceCheckUtils]: 70: Hoare triple {62687#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {62687#false} is VALID [2022-02-21 04:24:25,665 INFO L290 TraceCheckUtils]: 71: Hoare triple {62687#false} assume !(1 == ~T3_E~0); {62687#false} is VALID [2022-02-21 04:24:25,665 INFO L290 TraceCheckUtils]: 72: Hoare triple {62687#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {62687#false} is VALID [2022-02-21 04:24:25,665 INFO L290 TraceCheckUtils]: 73: Hoare triple {62687#false} assume !(1 == ~T5_E~0); {62687#false} is VALID [2022-02-21 04:24:25,665 INFO L290 TraceCheckUtils]: 74: Hoare triple {62687#false} assume !(1 == ~T6_E~0); {62687#false} is VALID [2022-02-21 04:24:25,665 INFO L290 TraceCheckUtils]: 75: Hoare triple {62687#false} assume !(1 == ~E_1~0); {62687#false} is VALID [2022-02-21 04:24:25,665 INFO L290 TraceCheckUtils]: 76: Hoare triple {62687#false} assume !(1 == ~E_2~0); {62687#false} is VALID [2022-02-21 04:24:25,665 INFO L290 TraceCheckUtils]: 77: Hoare triple {62687#false} assume !(1 == ~E_3~0); {62687#false} is VALID [2022-02-21 04:24:25,665 INFO L290 TraceCheckUtils]: 78: Hoare triple {62687#false} assume !(1 == ~E_4~0); {62687#false} is VALID [2022-02-21 04:24:25,665 INFO L290 TraceCheckUtils]: 79: Hoare triple {62687#false} assume !(1 == ~E_5~0); {62687#false} is VALID [2022-02-21 04:24:25,665 INFO L290 TraceCheckUtils]: 80: Hoare triple {62687#false} assume 1 == ~E_6~0;~E_6~0 := 2; {62687#false} is VALID [2022-02-21 04:24:25,666 INFO L290 TraceCheckUtils]: 81: Hoare triple {62687#false} assume { :end_inline_reset_delta_events } true; {62687#false} is VALID [2022-02-21 04:24:25,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:25,666 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:25,666 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1330177065] [2022-02-21 04:24:25,666 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1330177065] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:25,666 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:25,666 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:25,666 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [434874181] [2022-02-21 04:24:25,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:25,667 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:25,667 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:25,667 INFO L85 PathProgramCache]: Analyzing trace with hash 32830498, now seen corresponding path program 1 times [2022-02-21 04:24:25,667 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:25,667 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308136152] [2022-02-21 04:24:25,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:25,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:25,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:25,700 INFO L290 TraceCheckUtils]: 0: Hoare triple {62689#true} assume !false; {62689#true} is VALID [2022-02-21 04:24:25,700 INFO L290 TraceCheckUtils]: 1: Hoare triple {62689#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {62689#true} is VALID [2022-02-21 04:24:25,700 INFO L290 TraceCheckUtils]: 2: Hoare triple {62689#true} assume !false; {62689#true} is VALID [2022-02-21 04:24:25,700 INFO L290 TraceCheckUtils]: 3: Hoare triple {62689#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {62689#true} is VALID [2022-02-21 04:24:25,701 INFO L290 TraceCheckUtils]: 4: Hoare triple {62689#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {62691#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~7#1|)} is VALID [2022-02-21 04:24:25,701 INFO L290 TraceCheckUtils]: 5: Hoare triple {62691#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~7#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {62692#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:24:25,701 INFO L290 TraceCheckUtils]: 6: Hoare triple {62692#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {62693#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:24:25,702 INFO L290 TraceCheckUtils]: 7: Hoare triple {62693#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {62690#false} is VALID [2022-02-21 04:24:25,702 INFO L290 TraceCheckUtils]: 8: Hoare triple {62690#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {62690#false} is VALID [2022-02-21 04:24:25,702 INFO L290 TraceCheckUtils]: 9: Hoare triple {62690#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {62690#false} is VALID [2022-02-21 04:24:25,702 INFO L290 TraceCheckUtils]: 10: Hoare triple {62690#false} assume 0 == ~M_E~0;~M_E~0 := 1; {62690#false} is VALID [2022-02-21 04:24:25,702 INFO L290 TraceCheckUtils]: 11: Hoare triple {62690#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {62690#false} is VALID [2022-02-21 04:24:25,702 INFO L290 TraceCheckUtils]: 12: Hoare triple {62690#false} assume !(0 == ~T2_E~0); {62690#false} is VALID [2022-02-21 04:24:25,702 INFO L290 TraceCheckUtils]: 13: Hoare triple {62690#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {62690#false} is VALID [2022-02-21 04:24:25,702 INFO L290 TraceCheckUtils]: 14: Hoare triple {62690#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {62690#false} is VALID [2022-02-21 04:24:25,702 INFO L290 TraceCheckUtils]: 15: Hoare triple {62690#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {62690#false} is VALID [2022-02-21 04:24:25,703 INFO L290 TraceCheckUtils]: 16: Hoare triple {62690#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {62690#false} is VALID [2022-02-21 04:24:25,703 INFO L290 TraceCheckUtils]: 17: Hoare triple {62690#false} assume !(0 == ~E_1~0); {62690#false} is VALID [2022-02-21 04:24:25,703 INFO L290 TraceCheckUtils]: 18: Hoare triple {62690#false} assume 0 == ~E_2~0;~E_2~0 := 1; {62690#false} is VALID [2022-02-21 04:24:25,703 INFO L290 TraceCheckUtils]: 19: Hoare triple {62690#false} assume 0 == ~E_3~0;~E_3~0 := 1; {62690#false} is VALID [2022-02-21 04:24:25,703 INFO L290 TraceCheckUtils]: 20: Hoare triple {62690#false} assume !(0 == ~E_4~0); {62690#false} is VALID [2022-02-21 04:24:25,703 INFO L290 TraceCheckUtils]: 21: Hoare triple {62690#false} assume 0 == ~E_5~0;~E_5~0 := 1; {62690#false} is VALID [2022-02-21 04:24:25,703 INFO L290 TraceCheckUtils]: 22: Hoare triple {62690#false} assume 0 == ~E_6~0;~E_6~0 := 1; {62690#false} is VALID [2022-02-21 04:24:25,703 INFO L290 TraceCheckUtils]: 23: Hoare triple {62690#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {62690#false} is VALID [2022-02-21 04:24:25,703 INFO L290 TraceCheckUtils]: 24: Hoare triple {62690#false} assume !(1 == ~m_pc~0); {62690#false} is VALID [2022-02-21 04:24:25,703 INFO L290 TraceCheckUtils]: 25: Hoare triple {62690#false} is_master_triggered_~__retres1~0#1 := 0; {62690#false} is VALID [2022-02-21 04:24:25,704 INFO L290 TraceCheckUtils]: 26: Hoare triple {62690#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {62690#false} is VALID [2022-02-21 04:24:25,704 INFO L290 TraceCheckUtils]: 27: Hoare triple {62690#false} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {62690#false} is VALID [2022-02-21 04:24:25,704 INFO L290 TraceCheckUtils]: 28: Hoare triple {62690#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {62690#false} is VALID [2022-02-21 04:24:25,704 INFO L290 TraceCheckUtils]: 29: Hoare triple {62690#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {62690#false} is VALID [2022-02-21 04:24:25,704 INFO L290 TraceCheckUtils]: 30: Hoare triple {62690#false} assume !(1 == ~t1_pc~0); {62690#false} is VALID [2022-02-21 04:24:25,704 INFO L290 TraceCheckUtils]: 31: Hoare triple {62690#false} is_transmit1_triggered_~__retres1~1#1 := 0; {62690#false} is VALID [2022-02-21 04:24:25,704 INFO L290 TraceCheckUtils]: 32: Hoare triple {62690#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {62690#false} is VALID [2022-02-21 04:24:25,704 INFO L290 TraceCheckUtils]: 33: Hoare triple {62690#false} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {62690#false} is VALID [2022-02-21 04:24:25,704 INFO L290 TraceCheckUtils]: 34: Hoare triple {62690#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {62690#false} is VALID [2022-02-21 04:24:25,704 INFO L290 TraceCheckUtils]: 35: Hoare triple {62690#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {62690#false} is VALID [2022-02-21 04:24:25,705 INFO L290 TraceCheckUtils]: 36: Hoare triple {62690#false} assume !(1 == ~t2_pc~0); {62690#false} is VALID [2022-02-21 04:24:25,705 INFO L290 TraceCheckUtils]: 37: Hoare triple {62690#false} is_transmit2_triggered_~__retres1~2#1 := 0; {62690#false} is VALID [2022-02-21 04:24:25,705 INFO L290 TraceCheckUtils]: 38: Hoare triple {62690#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {62690#false} is VALID [2022-02-21 04:24:25,705 INFO L290 TraceCheckUtils]: 39: Hoare triple {62690#false} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {62690#false} is VALID [2022-02-21 04:24:25,705 INFO L290 TraceCheckUtils]: 40: Hoare triple {62690#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {62690#false} is VALID [2022-02-21 04:24:25,705 INFO L290 TraceCheckUtils]: 41: Hoare triple {62690#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {62690#false} is VALID [2022-02-21 04:24:25,705 INFO L290 TraceCheckUtils]: 42: Hoare triple {62690#false} assume 1 == ~t3_pc~0; {62690#false} is VALID [2022-02-21 04:24:25,705 INFO L290 TraceCheckUtils]: 43: Hoare triple {62690#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {62690#false} is VALID [2022-02-21 04:24:25,705 INFO L290 TraceCheckUtils]: 44: Hoare triple {62690#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {62690#false} is VALID [2022-02-21 04:24:25,705 INFO L290 TraceCheckUtils]: 45: Hoare triple {62690#false} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {62690#false} is VALID [2022-02-21 04:24:25,706 INFO L290 TraceCheckUtils]: 46: Hoare triple {62690#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {62690#false} is VALID [2022-02-21 04:24:25,706 INFO L290 TraceCheckUtils]: 47: Hoare triple {62690#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {62690#false} is VALID [2022-02-21 04:24:25,706 INFO L290 TraceCheckUtils]: 48: Hoare triple {62690#false} assume !(1 == ~t4_pc~0); {62690#false} is VALID [2022-02-21 04:24:25,706 INFO L290 TraceCheckUtils]: 49: Hoare triple {62690#false} is_transmit4_triggered_~__retres1~4#1 := 0; {62690#false} is VALID [2022-02-21 04:24:25,706 INFO L290 TraceCheckUtils]: 50: Hoare triple {62690#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {62690#false} is VALID [2022-02-21 04:24:25,706 INFO L290 TraceCheckUtils]: 51: Hoare triple {62690#false} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {62690#false} is VALID [2022-02-21 04:24:25,706 INFO L290 TraceCheckUtils]: 52: Hoare triple {62690#false} assume !(0 != activate_threads_~tmp___3~0#1); {62690#false} is VALID [2022-02-21 04:24:25,706 INFO L290 TraceCheckUtils]: 53: Hoare triple {62690#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {62690#false} is VALID [2022-02-21 04:24:25,706 INFO L290 TraceCheckUtils]: 54: Hoare triple {62690#false} assume 1 == ~t5_pc~0; {62690#false} is VALID [2022-02-21 04:24:25,706 INFO L290 TraceCheckUtils]: 55: Hoare triple {62690#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {62690#false} is VALID [2022-02-21 04:24:25,707 INFO L290 TraceCheckUtils]: 56: Hoare triple {62690#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {62690#false} is VALID [2022-02-21 04:24:25,707 INFO L290 TraceCheckUtils]: 57: Hoare triple {62690#false} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {62690#false} is VALID [2022-02-21 04:24:25,707 INFO L290 TraceCheckUtils]: 58: Hoare triple {62690#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {62690#false} is VALID [2022-02-21 04:24:25,707 INFO L290 TraceCheckUtils]: 59: Hoare triple {62690#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {62690#false} is VALID [2022-02-21 04:24:25,707 INFO L290 TraceCheckUtils]: 60: Hoare triple {62690#false} assume !(1 == ~t6_pc~0); {62690#false} is VALID [2022-02-21 04:24:25,707 INFO L290 TraceCheckUtils]: 61: Hoare triple {62690#false} is_transmit6_triggered_~__retres1~6#1 := 0; {62690#false} is VALID [2022-02-21 04:24:25,707 INFO L290 TraceCheckUtils]: 62: Hoare triple {62690#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {62690#false} is VALID [2022-02-21 04:24:25,707 INFO L290 TraceCheckUtils]: 63: Hoare triple {62690#false} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {62690#false} is VALID [2022-02-21 04:24:25,707 INFO L290 TraceCheckUtils]: 64: Hoare triple {62690#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {62690#false} is VALID [2022-02-21 04:24:25,707 INFO L290 TraceCheckUtils]: 65: Hoare triple {62690#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {62690#false} is VALID [2022-02-21 04:24:25,708 INFO L290 TraceCheckUtils]: 66: Hoare triple {62690#false} assume 1 == ~M_E~0;~M_E~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,708 INFO L290 TraceCheckUtils]: 67: Hoare triple {62690#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,708 INFO L290 TraceCheckUtils]: 68: Hoare triple {62690#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,708 INFO L290 TraceCheckUtils]: 69: Hoare triple {62690#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,708 INFO L290 TraceCheckUtils]: 70: Hoare triple {62690#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,708 INFO L290 TraceCheckUtils]: 71: Hoare triple {62690#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,708 INFO L290 TraceCheckUtils]: 72: Hoare triple {62690#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,708 INFO L290 TraceCheckUtils]: 73: Hoare triple {62690#false} assume !(1 == ~E_1~0); {62690#false} is VALID [2022-02-21 04:24:25,708 INFO L290 TraceCheckUtils]: 74: Hoare triple {62690#false} assume 1 == ~E_2~0;~E_2~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,708 INFO L290 TraceCheckUtils]: 75: Hoare triple {62690#false} assume 1 == ~E_3~0;~E_3~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,709 INFO L290 TraceCheckUtils]: 76: Hoare triple {62690#false} assume 1 == ~E_4~0;~E_4~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,709 INFO L290 TraceCheckUtils]: 77: Hoare triple {62690#false} assume 1 == ~E_5~0;~E_5~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,709 INFO L290 TraceCheckUtils]: 78: Hoare triple {62690#false} assume 1 == ~E_6~0;~E_6~0 := 2; {62690#false} is VALID [2022-02-21 04:24:25,709 INFO L290 TraceCheckUtils]: 79: Hoare triple {62690#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {62690#false} is VALID [2022-02-21 04:24:25,709 INFO L290 TraceCheckUtils]: 80: Hoare triple {62690#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {62690#false} is VALID [2022-02-21 04:24:25,709 INFO L290 TraceCheckUtils]: 81: Hoare triple {62690#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {62690#false} is VALID [2022-02-21 04:24:25,709 INFO L290 TraceCheckUtils]: 82: Hoare triple {62690#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {62690#false} is VALID [2022-02-21 04:24:25,709 INFO L290 TraceCheckUtils]: 83: Hoare triple {62690#false} assume !(0 == start_simulation_~tmp~3#1); {62690#false} is VALID [2022-02-21 04:24:25,709 INFO L290 TraceCheckUtils]: 84: Hoare triple {62690#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {62690#false} is VALID [2022-02-21 04:24:25,709 INFO L290 TraceCheckUtils]: 85: Hoare triple {62690#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {62690#false} is VALID [2022-02-21 04:24:25,710 INFO L290 TraceCheckUtils]: 86: Hoare triple {62690#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {62690#false} is VALID [2022-02-21 04:24:25,710 INFO L290 TraceCheckUtils]: 87: Hoare triple {62690#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {62690#false} is VALID [2022-02-21 04:24:25,710 INFO L290 TraceCheckUtils]: 88: Hoare triple {62690#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {62690#false} is VALID [2022-02-21 04:24:25,710 INFO L290 TraceCheckUtils]: 89: Hoare triple {62690#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {62690#false} is VALID [2022-02-21 04:24:25,710 INFO L290 TraceCheckUtils]: 90: Hoare triple {62690#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {62690#false} is VALID [2022-02-21 04:24:25,710 INFO L290 TraceCheckUtils]: 91: Hoare triple {62690#false} assume !(0 != start_simulation_~tmp___0~1#1); {62690#false} is VALID [2022-02-21 04:24:25,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:25,710 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:25,711 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308136152] [2022-02-21 04:24:25,711 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308136152] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:25,711 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:25,711 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:25,711 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283338024] [2022-02-21 04:24:25,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:25,711 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:25,711 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:25,712 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:25,712 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:25,712 INFO L87 Difference]: Start difference. First operand 5335 states and 7781 transitions. cyclomatic complexity: 2452 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,556 INFO L93 Difference]: Finished difference Result 9904 states and 14392 transitions. [2022-02-21 04:24:28,556 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:28,557 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,603 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:28,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9904 states and 14392 transitions. [2022-02-21 04:24:30,878 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9752 [2022-02-21 04:24:32,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9904 states to 9904 states and 14392 transitions. [2022-02-21 04:24:32,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9904 [2022-02-21 04:24:32,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9904 [2022-02-21 04:24:32,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9904 states and 14392 transitions. [2022-02-21 04:24:32,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:32,909 INFO L681 BuchiCegarLoop]: Abstraction has 9904 states and 14392 transitions. [2022-02-21 04:24:32,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9904 states and 14392 transitions. [2022-02-21 04:24:33,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9904 to 9880. [2022-02-21 04:24:33,007 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:33,018 INFO L82 GeneralOperation]: Start isEquivalent. First operand 9904 states and 14392 transitions. Second operand has 9880 states, 9880 states have (on average 1.454251012145749) internal successors, (14368), 9879 states have internal predecessors, (14368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,029 INFO L74 IsIncluded]: Start isIncluded. First operand 9904 states and 14392 transitions. Second operand has 9880 states, 9880 states have (on average 1.454251012145749) internal successors, (14368), 9879 states have internal predecessors, (14368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,040 INFO L87 Difference]: Start difference. First operand 9904 states and 14392 transitions. Second operand has 9880 states, 9880 states have (on average 1.454251012145749) internal successors, (14368), 9879 states have internal predecessors, (14368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:35,101 INFO L93 Difference]: Finished difference Result 9904 states and 14392 transitions. [2022-02-21 04:24:35,101 INFO L276 IsEmpty]: Start isEmpty. Operand 9904 states and 14392 transitions. [2022-02-21 04:24:35,110 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:35,111 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:35,121 INFO L74 IsIncluded]: Start isIncluded. First operand has 9880 states, 9880 states have (on average 1.454251012145749) internal successors, (14368), 9879 states have internal predecessors, (14368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9904 states and 14392 transitions. [2022-02-21 04:24:35,130 INFO L87 Difference]: Start difference. First operand has 9880 states, 9880 states have (on average 1.454251012145749) internal successors, (14368), 9879 states have internal predecessors, (14368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9904 states and 14392 transitions. [2022-02-21 04:24:37,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:37,194 INFO L93 Difference]: Finished difference Result 9904 states and 14392 transitions. [2022-02-21 04:24:37,194 INFO L276 IsEmpty]: Start isEmpty. Operand 9904 states and 14392 transitions. [2022-02-21 04:24:37,202 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:37,202 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:37,202 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:37,202 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:37,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9880 states, 9880 states have (on average 1.454251012145749) internal successors, (14368), 9879 states have internal predecessors, (14368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9880 states to 9880 states and 14368 transitions. [2022-02-21 04:24:39,280 INFO L704 BuchiCegarLoop]: Abstraction has 9880 states and 14368 transitions. [2022-02-21 04:24:39,280 INFO L587 BuchiCegarLoop]: Abstraction has 9880 states and 14368 transitions. [2022-02-21 04:24:39,280 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:24:39,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9880 states and 14368 transitions. [2022-02-21 04:24:39,301 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9728 [2022-02-21 04:24:39,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:39,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:39,303 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:39,303 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:39,303 INFO L791 eck$LassoCheckResult]: Stem: 73317#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 73258#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 73192#L987 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 72602#L454 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 72598#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 72599#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 73135#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73290#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 72692#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 72693#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 72843#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 72710#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 72711#L670 assume !(0 == ~M_E~0); 73093#L670-2 assume !(0 == ~T1_E~0); 73035#L675-1 assume !(0 == ~T2_E~0); 73036#L680-1 assume !(0 == ~T3_E~0); 73133#L685-1 assume !(0 == ~T4_E~0); 73098#L690-1 assume !(0 == ~T5_E~0); 73099#L695-1 assume !(0 == ~T6_E~0); 73169#L700-1 assume !(0 == ~E_1~0); 73160#L705-1 assume !(0 == ~E_2~0); 73161#L710-1 assume !(0 == ~E_3~0); 73034#L715-1 assume !(0 == ~E_4~0); 72953#L720-1 assume !(0 == ~E_5~0); 72954#L725-1 assume !(0 == ~E_6~0); 73012#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73060#L320 assume !(1 == ~m_pc~0); 73189#L320-2 is_master_triggered_~__retres1~0#1 := 0; 72885#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72886#L332 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 72844#L825 assume !(0 != activate_threads_~tmp~1#1); 72845#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72852#L339 assume !(1 == ~t1_pc~0); 72853#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 72829#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72830#L351 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 72712#L833 assume !(0 != activate_threads_~tmp___0~0#1); 72713#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72623#L358 assume !(1 == ~t2_pc~0); 72624#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 73155#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73094#L370 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 73016#L841 assume !(0 != activate_threads_~tmp___1~0#1); 72841#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72842#L377 assume !(1 == ~t3_pc~0); 73115#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 73116#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73114#L389 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 72847#L849 assume !(0 != activate_threads_~tmp___2~0#1); 72848#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 72799#L396 assume !(1 == ~t4_pc~0); 72800#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 72625#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 72626#L408 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 73049#L857 assume !(0 != activate_threads_~tmp___3~0#1); 72767#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 72768#L415 assume !(1 == ~t5_pc~0); 72832#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 72875#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73061#L427 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 73197#L865 assume !(0 != activate_threads_~tmp___4~0#1); 72668#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72669#L434 assume !(1 == ~t6_pc~0); 72989#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 72990#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73146#L446 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 73147#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 72861#L873-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72862#L743 assume !(1 == ~M_E~0); 72758#L743-2 assume !(1 == ~T1_E~0); 72759#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73240#L753-1 assume !(1 == ~T3_E~0); 80847#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 80846#L763-1 assume !(1 == ~T5_E~0); 80845#L768-1 assume !(1 == ~T6_E~0); 72859#L773-1 assume !(1 == ~E_1~0); 72860#L778-1 assume !(1 == ~E_2~0); 72836#L783-1 assume !(1 == ~E_3~0); 72837#L788-1 assume !(1 == ~E_4~0); 73130#L793-1 assume !(1 == ~E_5~0); 73131#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 72731#L803-1 assume { :end_inline_reset_delta_events } true; 72732#L1024-2 [2022-02-21 04:24:39,304 INFO L793 eck$LassoCheckResult]: Loop: 72732#L1024-2 assume !false; 77526#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77519#L645 assume !false; 77520#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 77514#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 77500#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 77441#L542 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 77433#L556 assume !(0 != eval_~tmp~0#1); 77434#L660 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82345#L454-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82343#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 82341#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 82339#L675-3 assume !(0 == ~T2_E~0); 82337#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 82335#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 82333#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 82331#L695-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 82329#L700-3 assume !(0 == ~E_1~0); 82327#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 82325#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 81529#L715-3 assume !(0 == ~E_4~0); 81528#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 81527#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 81526#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81525#L320-21 assume !(1 == ~m_pc~0); 81523#L320-23 is_master_triggered_~__retres1~0#1 := 0; 81521#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81519#L332-7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81517#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81515#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81513#L339-21 assume 1 == ~t1_pc~0; 81511#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 81507#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81505#L351-7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81503#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 81499#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80985#L358-21 assume !(1 == ~t2_pc~0); 77834#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 77835#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77828#L370-7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77829#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77822#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77823#L377-21 assume !(1 == ~t3_pc~0); 77814#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 77815#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77808#L389-7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 77809#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77802#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77803#L396-21 assume !(1 == ~t4_pc~0); 77795#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 77796#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77789#L408-7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77790#L857-21 assume !(0 != activate_threads_~tmp___3~0#1); 77782#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77783#L415-21 assume !(1 == ~t5_pc~0); 77776#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 77777#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77770#L427-7 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 77771#L865-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 77764#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77765#L434-21 assume !(1 == ~t6_pc~0); 77755#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 77756#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77749#L446-7 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77750#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77743#L873-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77744#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 77736#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77737#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 77730#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77731#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77724#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77725#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77717#L773-3 assume !(1 == ~E_1~0); 77718#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77711#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77712#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77705#L793-3 assume 1 == ~E_5~0;~E_5~0 := 2; 77706#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 77698#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 77699#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 77648#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 77649#L542-1 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 77638#L1043 assume !(0 == start_simulation_~tmp~3#1); 77639#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 77607#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 77600#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 77601#L542-2 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 80809#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 80807#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80806#L1006 start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 77591#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 72732#L1024-2 [2022-02-21 04:24:39,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:39,304 INFO L85 PathProgramCache]: Analyzing trace with hash -944533987, now seen corresponding path program 1 times [2022-02-21 04:24:39,304 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:39,305 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1917715881] [2022-02-21 04:24:39,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:39,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:39,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:39,332 INFO L290 TraceCheckUtils]: 0: Hoare triple {102289#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; {102289#true} is VALID [2022-02-21 04:24:39,332 INFO L290 TraceCheckUtils]: 1: Hoare triple {102289#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {102289#true} is VALID [2022-02-21 04:24:39,332 INFO L290 TraceCheckUtils]: 2: Hoare triple {102289#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {102289#true} is VALID [2022-02-21 04:24:39,333 INFO L290 TraceCheckUtils]: 3: Hoare triple {102289#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {102289#true} is VALID [2022-02-21 04:24:39,333 INFO L290 TraceCheckUtils]: 4: Hoare triple {102289#true} assume 1 == ~m_i~0;~m_st~0 := 0; {102289#true} is VALID [2022-02-21 04:24:39,333 INFO L290 TraceCheckUtils]: 5: Hoare triple {102289#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {102289#true} is VALID [2022-02-21 04:24:39,333 INFO L290 TraceCheckUtils]: 6: Hoare triple {102289#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {102289#true} is VALID [2022-02-21 04:24:39,333 INFO L290 TraceCheckUtils]: 7: Hoare triple {102289#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {102289#true} is VALID [2022-02-21 04:24:39,333 INFO L290 TraceCheckUtils]: 8: Hoare triple {102289#true} assume 1 == ~t4_i~0;~t4_st~0 := 0; {102289#true} is VALID [2022-02-21 04:24:39,333 INFO L290 TraceCheckUtils]: 9: Hoare triple {102289#true} assume 1 == ~t5_i~0;~t5_st~0 := 0; {102289#true} is VALID [2022-02-21 04:24:39,333 INFO L290 TraceCheckUtils]: 10: Hoare triple {102289#true} assume 1 == ~t6_i~0;~t6_st~0 := 0; {102289#true} is VALID [2022-02-21 04:24:39,333 INFO L290 TraceCheckUtils]: 11: Hoare triple {102289#true} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {102289#true} is VALID [2022-02-21 04:24:39,333 INFO L290 TraceCheckUtils]: 12: Hoare triple {102289#true} assume !(0 == ~M_E~0); {102289#true} is VALID [2022-02-21 04:24:39,334 INFO L290 TraceCheckUtils]: 13: Hoare triple {102289#true} assume !(0 == ~T1_E~0); {102289#true} is VALID [2022-02-21 04:24:39,334 INFO L290 TraceCheckUtils]: 14: Hoare triple {102289#true} assume !(0 == ~T2_E~0); {102289#true} is VALID [2022-02-21 04:24:39,334 INFO L290 TraceCheckUtils]: 15: Hoare triple {102289#true} assume !(0 == ~T3_E~0); {102289#true} is VALID [2022-02-21 04:24:39,334 INFO L290 TraceCheckUtils]: 16: Hoare triple {102289#true} assume !(0 == ~T4_E~0); {102289#true} is VALID [2022-02-21 04:24:39,334 INFO L290 TraceCheckUtils]: 17: Hoare triple {102289#true} assume !(0 == ~T5_E~0); {102289#true} is VALID [2022-02-21 04:24:39,334 INFO L290 TraceCheckUtils]: 18: Hoare triple {102289#true} assume !(0 == ~T6_E~0); {102289#true} is VALID [2022-02-21 04:24:39,334 INFO L290 TraceCheckUtils]: 19: Hoare triple {102289#true} assume !(0 == ~E_1~0); {102289#true} is VALID [2022-02-21 04:24:39,334 INFO L290 TraceCheckUtils]: 20: Hoare triple {102289#true} assume !(0 == ~E_2~0); {102289#true} is VALID [2022-02-21 04:24:39,334 INFO L290 TraceCheckUtils]: 21: Hoare triple {102289#true} assume !(0 == ~E_3~0); {102289#true} is VALID [2022-02-21 04:24:39,334 INFO L290 TraceCheckUtils]: 22: Hoare triple {102289#true} assume !(0 == ~E_4~0); {102289#true} is VALID [2022-02-21 04:24:39,335 INFO L290 TraceCheckUtils]: 23: Hoare triple {102289#true} assume !(0 == ~E_5~0); {102289#true} is VALID [2022-02-21 04:24:39,335 INFO L290 TraceCheckUtils]: 24: Hoare triple {102289#true} assume !(0 == ~E_6~0); {102289#true} is VALID [2022-02-21 04:24:39,335 INFO L290 TraceCheckUtils]: 25: Hoare triple {102289#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {102289#true} is VALID [2022-02-21 04:24:39,335 INFO L290 TraceCheckUtils]: 26: Hoare triple {102289#true} assume !(1 == ~m_pc~0); {102289#true} is VALID [2022-02-21 04:24:39,335 INFO L290 TraceCheckUtils]: 27: Hoare triple {102289#true} is_master_triggered_~__retres1~0#1 := 0; {102289#true} is VALID [2022-02-21 04:24:39,335 INFO L290 TraceCheckUtils]: 28: Hoare triple {102289#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {102289#true} is VALID [2022-02-21 04:24:39,335 INFO L290 TraceCheckUtils]: 29: Hoare triple {102289#true} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {102289#true} is VALID [2022-02-21 04:24:39,335 INFO L290 TraceCheckUtils]: 30: Hoare triple {102289#true} assume !(0 != activate_threads_~tmp~1#1); {102289#true} is VALID [2022-02-21 04:24:39,335 INFO L290 TraceCheckUtils]: 31: Hoare triple {102289#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {102289#true} is VALID [2022-02-21 04:24:39,336 INFO L290 TraceCheckUtils]: 32: Hoare triple {102289#true} assume !(1 == ~t1_pc~0); {102289#true} is VALID [2022-02-21 04:24:39,336 INFO L290 TraceCheckUtils]: 33: Hoare triple {102289#true} is_transmit1_triggered_~__retres1~1#1 := 0; {102289#true} is VALID [2022-02-21 04:24:39,336 INFO L290 TraceCheckUtils]: 34: Hoare triple {102289#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {102289#true} is VALID [2022-02-21 04:24:39,336 INFO L290 TraceCheckUtils]: 35: Hoare triple {102289#true} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {102289#true} is VALID [2022-02-21 04:24:39,336 INFO L290 TraceCheckUtils]: 36: Hoare triple {102289#true} assume !(0 != activate_threads_~tmp___0~0#1); {102289#true} is VALID [2022-02-21 04:24:39,336 INFO L290 TraceCheckUtils]: 37: Hoare triple {102289#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {102289#true} is VALID [2022-02-21 04:24:39,336 INFO L290 TraceCheckUtils]: 38: Hoare triple {102289#true} assume !(1 == ~t2_pc~0); {102289#true} is VALID [2022-02-21 04:24:39,336 INFO L290 TraceCheckUtils]: 39: Hoare triple {102289#true} is_transmit2_triggered_~__retres1~2#1 := 0; {102289#true} is VALID [2022-02-21 04:24:39,336 INFO L290 TraceCheckUtils]: 40: Hoare triple {102289#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {102289#true} is VALID [2022-02-21 04:24:39,336 INFO L290 TraceCheckUtils]: 41: Hoare triple {102289#true} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {102289#true} is VALID [2022-02-21 04:24:39,337 INFO L290 TraceCheckUtils]: 42: Hoare triple {102289#true} assume !(0 != activate_threads_~tmp___1~0#1); {102289#true} is VALID [2022-02-21 04:24:39,337 INFO L290 TraceCheckUtils]: 43: Hoare triple {102289#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {102289#true} is VALID [2022-02-21 04:24:39,337 INFO L290 TraceCheckUtils]: 44: Hoare triple {102289#true} assume !(1 == ~t3_pc~0); {102289#true} is VALID [2022-02-21 04:24:39,337 INFO L290 TraceCheckUtils]: 45: Hoare triple {102289#true} is_transmit3_triggered_~__retres1~3#1 := 0; {102289#true} is VALID [2022-02-21 04:24:39,337 INFO L290 TraceCheckUtils]: 46: Hoare triple {102289#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {102289#true} is VALID [2022-02-21 04:24:39,337 INFO L290 TraceCheckUtils]: 47: Hoare triple {102289#true} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {102289#true} is VALID [2022-02-21 04:24:39,337 INFO L290 TraceCheckUtils]: 48: Hoare triple {102289#true} assume !(0 != activate_threads_~tmp___2~0#1); {102289#true} is VALID [2022-02-21 04:24:39,337 INFO L290 TraceCheckUtils]: 49: Hoare triple {102289#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {102289#true} is VALID [2022-02-21 04:24:39,337 INFO L290 TraceCheckUtils]: 50: Hoare triple {102289#true} assume !(1 == ~t4_pc~0); {102289#true} is VALID [2022-02-21 04:24:39,337 INFO L290 TraceCheckUtils]: 51: Hoare triple {102289#true} is_transmit4_triggered_~__retres1~4#1 := 0; {102289#true} is VALID [2022-02-21 04:24:39,338 INFO L290 TraceCheckUtils]: 52: Hoare triple {102289#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {102289#true} is VALID [2022-02-21 04:24:39,338 INFO L290 TraceCheckUtils]: 53: Hoare triple {102289#true} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {102289#true} is VALID [2022-02-21 04:24:39,338 INFO L290 TraceCheckUtils]: 54: Hoare triple {102289#true} assume !(0 != activate_threads_~tmp___3~0#1); {102289#true} is VALID [2022-02-21 04:24:39,338 INFO L290 TraceCheckUtils]: 55: Hoare triple {102289#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {102289#true} is VALID [2022-02-21 04:24:39,338 INFO L290 TraceCheckUtils]: 56: Hoare triple {102289#true} assume !(1 == ~t5_pc~0); {102289#true} is VALID [2022-02-21 04:24:39,338 INFO L290 TraceCheckUtils]: 57: Hoare triple {102289#true} is_transmit5_triggered_~__retres1~5#1 := 0; {102289#true} is VALID [2022-02-21 04:24:39,338 INFO L290 TraceCheckUtils]: 58: Hoare triple {102289#true} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {102289#true} is VALID [2022-02-21 04:24:39,338 INFO L290 TraceCheckUtils]: 59: Hoare triple {102289#true} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {102289#true} is VALID [2022-02-21 04:24:39,338 INFO L290 TraceCheckUtils]: 60: Hoare triple {102289#true} assume !(0 != activate_threads_~tmp___4~0#1); {102289#true} is VALID [2022-02-21 04:24:39,338 INFO L290 TraceCheckUtils]: 61: Hoare triple {102289#true} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {102289#true} is VALID [2022-02-21 04:24:39,339 INFO L290 TraceCheckUtils]: 62: Hoare triple {102289#true} assume !(1 == ~t6_pc~0); {102289#true} is VALID [2022-02-21 04:24:39,339 INFO L290 TraceCheckUtils]: 63: Hoare triple {102289#true} is_transmit6_triggered_~__retres1~6#1 := 0; {102291#(= |ULTIMATE.start_is_transmit6_triggered_~__retres1~6#1| 0)} is VALID [2022-02-21 04:24:39,339 INFO L290 TraceCheckUtils]: 64: Hoare triple {102291#(= |ULTIMATE.start_is_transmit6_triggered_~__retres1~6#1| 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {102292#(= |ULTIMATE.start_is_transmit6_triggered_#res#1| 0)} is VALID [2022-02-21 04:24:39,340 INFO L290 TraceCheckUtils]: 65: Hoare triple {102292#(= |ULTIMATE.start_is_transmit6_triggered_#res#1| 0)} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {102293#(= |ULTIMATE.start_activate_threads_~tmp___5~0#1| 0)} is VALID [2022-02-21 04:24:39,340 INFO L290 TraceCheckUtils]: 66: Hoare triple {102293#(= |ULTIMATE.start_activate_threads_~tmp___5~0#1| 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {102290#false} is VALID [2022-02-21 04:24:39,340 INFO L290 TraceCheckUtils]: 67: Hoare triple {102290#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {102290#false} is VALID [2022-02-21 04:24:39,340 INFO L290 TraceCheckUtils]: 68: Hoare triple {102290#false} assume !(1 == ~M_E~0); {102290#false} is VALID [2022-02-21 04:24:39,340 INFO L290 TraceCheckUtils]: 69: Hoare triple {102290#false} assume !(1 == ~T1_E~0); {102290#false} is VALID [2022-02-21 04:24:39,340 INFO L290 TraceCheckUtils]: 70: Hoare triple {102290#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {102290#false} is VALID [2022-02-21 04:24:39,340 INFO L290 TraceCheckUtils]: 71: Hoare triple {102290#false} assume !(1 == ~T3_E~0); {102290#false} is VALID [2022-02-21 04:24:39,340 INFO L290 TraceCheckUtils]: 72: Hoare triple {102290#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {102290#false} is VALID [2022-02-21 04:24:39,341 INFO L290 TraceCheckUtils]: 73: Hoare triple {102290#false} assume !(1 == ~T5_E~0); {102290#false} is VALID [2022-02-21 04:24:39,341 INFO L290 TraceCheckUtils]: 74: Hoare triple {102290#false} assume !(1 == ~T6_E~0); {102290#false} is VALID [2022-02-21 04:24:39,341 INFO L290 TraceCheckUtils]: 75: Hoare triple {102290#false} assume !(1 == ~E_1~0); {102290#false} is VALID [2022-02-21 04:24:39,341 INFO L290 TraceCheckUtils]: 76: Hoare triple {102290#false} assume !(1 == ~E_2~0); {102290#false} is VALID [2022-02-21 04:24:39,341 INFO L290 TraceCheckUtils]: 77: Hoare triple {102290#false} assume !(1 == ~E_3~0); {102290#false} is VALID [2022-02-21 04:24:39,341 INFO L290 TraceCheckUtils]: 78: Hoare triple {102290#false} assume !(1 == ~E_4~0); {102290#false} is VALID [2022-02-21 04:24:39,341 INFO L290 TraceCheckUtils]: 79: Hoare triple {102290#false} assume !(1 == ~E_5~0); {102290#false} is VALID [2022-02-21 04:24:39,341 INFO L290 TraceCheckUtils]: 80: Hoare triple {102290#false} assume 1 == ~E_6~0;~E_6~0 := 2; {102290#false} is VALID [2022-02-21 04:24:39,341 INFO L290 TraceCheckUtils]: 81: Hoare triple {102290#false} assume { :end_inline_reset_delta_events } true; {102290#false} is VALID [2022-02-21 04:24:39,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:39,342 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:39,342 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1917715881] [2022-02-21 04:24:39,342 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1917715881] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:39,343 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:39,343 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:39,344 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348446614] [2022-02-21 04:24:39,344 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:39,345 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:39,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:39,345 INFO L85 PathProgramCache]: Analyzing trace with hash 1301055489, now seen corresponding path program 1 times [2022-02-21 04:24:39,345 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:39,345 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165299078] [2022-02-21 04:24:39,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:39,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:39,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:39,374 INFO L290 TraceCheckUtils]: 0: Hoare triple {102294#true} assume !false; {102294#true} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 1: Hoare triple {102294#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {102294#true} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 2: Hoare triple {102294#true} assume !false; {102294#true} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 3: Hoare triple {102294#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {102294#true} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 4: Hoare triple {102294#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {102294#true} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 5: Hoare triple {102294#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {102294#true} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 6: Hoare triple {102294#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {102294#true} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 7: Hoare triple {102294#true} assume !(0 != eval_~tmp~0#1); {102294#true} is VALID [2022-02-21 04:24:39,375 INFO L290 TraceCheckUtils]: 8: Hoare triple {102294#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {102294#true} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 9: Hoare triple {102294#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {102294#true} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 10: Hoare triple {102294#true} assume 0 == ~M_E~0;~M_E~0 := 1; {102294#true} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 11: Hoare triple {102294#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {102294#true} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 12: Hoare triple {102294#true} assume !(0 == ~T2_E~0); {102294#true} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 13: Hoare triple {102294#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {102294#true} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 14: Hoare triple {102294#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {102294#true} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 15: Hoare triple {102294#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {102294#true} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 16: Hoare triple {102294#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {102294#true} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 17: Hoare triple {102294#true} assume !(0 == ~E_1~0); {102294#true} is VALID [2022-02-21 04:24:39,376 INFO L290 TraceCheckUtils]: 18: Hoare triple {102294#true} assume 0 == ~E_2~0;~E_2~0 := 1; {102294#true} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 19: Hoare triple {102294#true} assume 0 == ~E_3~0;~E_3~0 := 1; {102294#true} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 20: Hoare triple {102294#true} assume !(0 == ~E_4~0); {102294#true} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 21: Hoare triple {102294#true} assume 0 == ~E_5~0;~E_5~0 := 1; {102294#true} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 22: Hoare triple {102294#true} assume 0 == ~E_6~0;~E_6~0 := 1; {102294#true} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 23: Hoare triple {102294#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {102294#true} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 24: Hoare triple {102294#true} assume !(1 == ~m_pc~0); {102294#true} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 25: Hoare triple {102294#true} is_master_triggered_~__retres1~0#1 := 0; {102294#true} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 26: Hoare triple {102294#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {102294#true} is VALID [2022-02-21 04:24:39,377 INFO L290 TraceCheckUtils]: 27: Hoare triple {102294#true} activate_threads_#t~ret12#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {102294#true} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 28: Hoare triple {102294#true} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {102294#true} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 29: Hoare triple {102294#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {102294#true} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 30: Hoare triple {102294#true} assume 1 == ~t1_pc~0; {102294#true} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 31: Hoare triple {102294#true} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,378 INFO L290 TraceCheckUtils]: 32: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,379 INFO L290 TraceCheckUtils]: 33: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,379 INFO L290 TraceCheckUtils]: 34: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,379 INFO L290 TraceCheckUtils]: 35: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 36: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t2_pc~0); {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 37: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 38: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,380 INFO L290 TraceCheckUtils]: 39: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 40: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 41: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,381 INFO L290 TraceCheckUtils]: 42: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t3_pc~0); {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 43: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 44: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,382 INFO L290 TraceCheckUtils]: 45: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 46: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 47: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 48: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t4_pc~0); {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,383 INFO L290 TraceCheckUtils]: 49: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,384 INFO L290 TraceCheckUtils]: 50: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,384 INFO L290 TraceCheckUtils]: 51: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,384 INFO L290 TraceCheckUtils]: 52: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 53: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 54: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t5_pc~0); {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 55: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,385 INFO L290 TraceCheckUtils]: 56: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 57: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 58: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,386 INFO L290 TraceCheckUtils]: 59: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 60: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t6_pc~0); {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 61: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 62: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,387 INFO L290 TraceCheckUtils]: 63: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,388 INFO L290 TraceCheckUtils]: 64: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,388 INFO L290 TraceCheckUtils]: 65: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,388 INFO L290 TraceCheckUtils]: 66: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,389 INFO L290 TraceCheckUtils]: 67: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,389 INFO L290 TraceCheckUtils]: 68: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,389 INFO L290 TraceCheckUtils]: 69: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,390 INFO L290 TraceCheckUtils]: 70: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,390 INFO L290 TraceCheckUtils]: 71: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,390 INFO L290 TraceCheckUtils]: 72: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {102296#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:24:39,390 INFO L290 TraceCheckUtils]: 73: Hoare triple {102296#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {102295#false} is VALID [2022-02-21 04:24:39,390 INFO L290 TraceCheckUtils]: 74: Hoare triple {102295#false} assume 1 == ~E_2~0;~E_2~0 := 2; {102295#false} is VALID [2022-02-21 04:24:39,391 INFO L290 TraceCheckUtils]: 75: Hoare triple {102295#false} assume 1 == ~E_3~0;~E_3~0 := 2; {102295#false} is VALID [2022-02-21 04:24:39,391 INFO L290 TraceCheckUtils]: 76: Hoare triple {102295#false} assume 1 == ~E_4~0;~E_4~0 := 2; {102295#false} is VALID [2022-02-21 04:24:39,391 INFO L290 TraceCheckUtils]: 77: Hoare triple {102295#false} assume 1 == ~E_5~0;~E_5~0 := 2; {102295#false} is VALID [2022-02-21 04:24:39,391 INFO L290 TraceCheckUtils]: 78: Hoare triple {102295#false} assume 1 == ~E_6~0;~E_6~0 := 2; {102295#false} is VALID [2022-02-21 04:24:39,391 INFO L290 TraceCheckUtils]: 79: Hoare triple {102295#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {102295#false} is VALID [2022-02-21 04:24:39,391 INFO L290 TraceCheckUtils]: 80: Hoare triple {102295#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {102295#false} is VALID [2022-02-21 04:24:39,391 INFO L290 TraceCheckUtils]: 81: Hoare triple {102295#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {102295#false} is VALID [2022-02-21 04:24:39,391 INFO L290 TraceCheckUtils]: 82: Hoare triple {102295#false} start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; {102295#false} is VALID [2022-02-21 04:24:39,391 INFO L290 TraceCheckUtils]: 83: Hoare triple {102295#false} assume !(0 == start_simulation_~tmp~3#1); {102295#false} is VALID [2022-02-21 04:24:39,392 INFO L290 TraceCheckUtils]: 84: Hoare triple {102295#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {102295#false} is VALID [2022-02-21 04:24:39,392 INFO L290 TraceCheckUtils]: 85: Hoare triple {102295#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {102295#false} is VALID [2022-02-21 04:24:39,392 INFO L290 TraceCheckUtils]: 86: Hoare triple {102295#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {102295#false} is VALID [2022-02-21 04:24:39,392 INFO L290 TraceCheckUtils]: 87: Hoare triple {102295#false} stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; {102295#false} is VALID [2022-02-21 04:24:39,392 INFO L290 TraceCheckUtils]: 88: Hoare triple {102295#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {102295#false} is VALID [2022-02-21 04:24:39,392 INFO L290 TraceCheckUtils]: 89: Hoare triple {102295#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {102295#false} is VALID [2022-02-21 04:24:39,392 INFO L290 TraceCheckUtils]: 90: Hoare triple {102295#false} start_simulation_#t~ret21#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; {102295#false} is VALID [2022-02-21 04:24:39,392 INFO L290 TraceCheckUtils]: 91: Hoare triple {102295#false} assume !(0 != start_simulation_~tmp___0~1#1); {102295#false} is VALID [2022-02-21 04:24:39,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:39,393 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:39,393 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165299078] [2022-02-21 04:24:39,393 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1165299078] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:39,393 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:39,393 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:39,393 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701540812] [2022-02-21 04:24:39,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:39,394 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:39,394 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:39,394 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:24:39,394 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:24:39,394 INFO L87 Difference]: Start difference. First operand 9880 states and 14368 transitions. cyclomatic complexity: 4500 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:52,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:52,798 INFO L93 Difference]: Finished difference Result 22635 states and 33249 transitions. [2022-02-21 04:24:52,798 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:24:52,798 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:52,840 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 82 edges. 82 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:52,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22635 states and 33249 transitions. [2022-02-21 04:25:02,742 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 22316 [2022-02-21 04:25:12,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22635 states to 22635 states and 33249 transitions. [2022-02-21 04:25:12,717 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22635 [2022-02-21 04:25:12,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22635 [2022-02-21 04:25:12,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22635 states and 33249 transitions. [2022-02-21 04:25:12,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:12,734 INFO L681 BuchiCegarLoop]: Abstraction has 22635 states and 33249 transitions. [2022-02-21 04:25:12,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22635 states and 33249 transitions. [2022-02-21 04:25:12,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22635 to 10303. [2022-02-21 04:25:12,869 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:12,881 INFO L82 GeneralOperation]: Start isEquivalent. First operand 22635 states and 33249 transitions. Second operand has 10303 states, 10303 states have (on average 1.4356012811802388) internal successors, (14791), 10302 states have internal predecessors, (14791), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:12,892 INFO L74 IsIncluded]: Start isIncluded. First operand 22635 states and 33249 transitions. Second operand has 10303 states, 10303 states have (on average 1.4356012811802388) internal successors, (14791), 10302 states have internal predecessors, (14791), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:12,904 INFO L87 Difference]: Start difference. First operand 22635 states and 33249 transitions. Second operand has 10303 states, 10303 states have (on average 1.4356012811802388) internal successors, (14791), 10302 states have internal predecessors, (14791), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)