./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.07.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.07.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:24:10,802 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:24:10,803 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:24:10,835 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:24:10,836 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:24:10,839 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:24:10,842 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:24:10,847 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:24:10,848 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:24:10,853 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:24:10,854 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:24:10,855 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:24:10,855 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:24:10,857 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:24:10,858 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:24:10,859 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:24:10,860 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:24:10,861 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:24:10,864 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:24:10,868 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:24:10,869 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:24:10,870 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:24:10,871 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:24:10,872 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:24:10,875 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:24:10,875 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:24:10,876 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:24:10,877 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:24:10,877 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:24:10,878 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:24:10,879 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:24:10,879 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:24:10,880 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:24:10,881 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:24:10,882 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:24:10,883 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:24:10,883 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:24:10,883 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:24:10,883 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:24:10,884 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:24:10,884 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:24:10,885 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:24:10,913 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:24:10,914 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:24:10,914 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:24:10,914 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:24:10,915 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:24:10,915 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:24:10,915 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:24:10,916 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:24:10,916 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:24:10,916 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:24:10,917 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:24:10,917 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:24:10,917 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:24:10,917 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:24:10,917 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:24:10,917 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:24:10,918 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:24:10,918 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:24:10,918 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:24:10,918 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:24:10,918 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:24:10,918 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:24:10,918 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:24:10,919 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:24:10,919 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:24:10,919 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:24:10,919 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:24:10,919 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:24:10,919 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:24:10,920 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:24:10,920 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:24:10,920 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:24:10,921 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f [2022-02-21 04:24:11,122 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:24:11,144 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:24:11,146 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:24:11,147 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:24:11,147 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:24:11,148 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.07.cil.c [2022-02-21 04:24:11,190 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bcf926920/e032843d494c41c5a53e8d81d3de89a1/FLAG18d42b78b [2022-02-21 04:24:11,607 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:11,608 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.07.cil.c [2022-02-21 04:24:11,621 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bcf926920/e032843d494c41c5a53e8d81d3de89a1/FLAG18d42b78b [2022-02-21 04:24:11,634 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bcf926920/e032843d494c41c5a53e8d81d3de89a1 [2022-02-21 04:24:11,637 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:11,639 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:11,640 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:11,640 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:11,642 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:11,643 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:11" (1/1) ... [2022-02-21 04:24:11,644 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@39fd263b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:11, skipping insertion in model container [2022-02-21 04:24:11,644 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:11" (1/1) ... [2022-02-21 04:24:11,649 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:11,684 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:11,818 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.07.cil.c[706,719] [2022-02-21 04:24:11,912 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:11,926 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:11,934 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.07.cil.c[706,719] [2022-02-21 04:24:12,001 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:12,013 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:12,017 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12 WrapperNode [2022-02-21 04:24:12,017 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:12,018 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:12,018 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:12,018 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:12,023 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12" (1/1) ... [2022-02-21 04:24:12,042 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12" (1/1) ... [2022-02-21 04:24:12,095 INFO L137 Inliner]: procedures = 42, calls = 51, calls flagged for inlining = 46, calls inlined = 124, statements flattened = 1845 [2022-02-21 04:24:12,096 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:12,096 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:12,096 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:12,097 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:12,103 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12" (1/1) ... [2022-02-21 04:24:12,103 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12" (1/1) ... [2022-02-21 04:24:12,107 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12" (1/1) ... [2022-02-21 04:24:12,107 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12" (1/1) ... [2022-02-21 04:24:12,124 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12" (1/1) ... [2022-02-21 04:24:12,138 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12" (1/1) ... [2022-02-21 04:24:12,141 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12" (1/1) ... [2022-02-21 04:24:12,146 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:12,150 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:12,150 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:12,151 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:12,151 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12" (1/1) ... [2022-02-21 04:24:12,173 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:12,182 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:12,192 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:12,219 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:12,243 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:12,243 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:12,244 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:12,244 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:12,329 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:12,330 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:13,890 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:13,906 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:13,919 INFO L299 CfgBuilder]: Removed 11 assume(true) statements. [2022-02-21 04:24:13,924 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:13 BoogieIcfgContainer [2022-02-21 04:24:13,924 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:13,925 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:13,925 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:13,928 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:13,929 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:13,929 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:11" (1/3) ... [2022-02-21 04:24:13,929 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@66f6b878 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:13, skipping insertion in model container [2022-02-21 04:24:13,930 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:13,930 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:12" (2/3) ... [2022-02-21 04:24:13,930 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@66f6b878 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:13, skipping insertion in model container [2022-02-21 04:24:13,930 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:13,930 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:13" (3/3) ... [2022-02-21 04:24:13,931 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.07.cil.c [2022-02-21 04:24:13,996 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:13,996 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:13,996 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:13,997 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:13,997 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:13,997 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:13,997 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:13,997 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:14,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,180 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 670 [2022-02-21 04:24:14,180 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:14,180 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:14,189 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:14,189 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:14,189 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:14,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:14,226 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 670 [2022-02-21 04:24:14,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:14,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:14,233 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:14,233 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:14,243 INFO L791 eck$LassoCheckResult]: Stem: 386#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 711#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 717#L1111true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 453#L514true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 641#L521true assume !(1 == ~m_i~0);~m_st~0 := 2; 606#L521-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 635#L526-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 192#L531-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 552#L536-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 238#L541-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 142#L546-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 599#L551-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 125#L556-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 683#L754true assume !(0 == ~M_E~0); 728#L754-2true assume !(0 == ~T1_E~0); 512#L759-1true assume !(0 == ~T2_E~0); 380#L764-1true assume !(0 == ~T3_E~0); 342#L769-1true assume !(0 == ~T4_E~0); 381#L774-1true assume !(0 == ~T5_E~0); 625#L779-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 524#L784-1true assume !(0 == ~T7_E~0); 340#L789-1true assume !(0 == ~E_1~0); 424#L794-1true assume !(0 == ~E_2~0); 755#L799-1true assume !(0 == ~E_3~0); 349#L804-1true assume !(0 == ~E_4~0); 377#L809-1true assume !(0 == ~E_5~0); 553#L814-1true assume !(0 == ~E_6~0); 11#L819-1true assume 0 == ~E_7~0;~E_7~0 := 1; 170#L824-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 141#L361true assume 1 == ~m_pc~0; 666#L362true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 708#L372true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77#L373true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 624#L930true assume !(0 != activate_threads_~tmp~1#1); 269#L930-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 137#L380true assume !(1 == ~t1_pc~0); 756#L380-2true is_transmit1_triggered_~__retres1~1#1 := 0; 636#L391true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 325#L392true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 760#L938true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 462#L938-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 440#L399true assume 1 == ~t2_pc~0; 628#L400true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 645#L410true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 344#L411true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 174#L946true assume !(0 != activate_threads_~tmp___1~0#1); 416#L946-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15#L418true assume !(1 == ~t3_pc~0); 692#L418-2true is_transmit3_triggered_~__retres1~3#1 := 0; 555#L429true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 696#L430true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 768#L954true assume !(0 != activate_threads_~tmp___2~0#1); 364#L954-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 685#L437true assume 1 == ~t4_pc~0; 747#L438true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 495#L448true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 441#L449true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 204#L962true assume !(0 != activate_threads_~tmp___3~0#1); 591#L962-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 478#L456true assume !(1 == ~t5_pc~0); 333#L456-2true is_transmit5_triggered_~__retres1~5#1 := 0; 673#L467true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 274#L468true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 412#L970true assume !(0 != activate_threads_~tmp___4~0#1); 726#L970-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44#L475true assume 1 == ~t6_pc~0; 221#L476true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63#L486true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 694#L487true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 403#L978true assume !(0 != activate_threads_~tmp___5~0#1); 355#L978-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 551#L494true assume 1 == ~t7_pc~0; 301#L495true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 315#L505true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 265#L506true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 383#L986true assume !(0 != activate_threads_~tmp___6~0#1); 752#L986-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 659#L837true assume !(1 == ~M_E~0); 571#L837-2true assume !(1 == ~T1_E~0); 435#L842-1true assume !(1 == ~T2_E~0); 212#L847-1true assume !(1 == ~T3_E~0); 262#L852-1true assume !(1 == ~T4_E~0); 772#L857-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 179#L862-1true assume !(1 == ~T6_E~0); 188#L867-1true assume !(1 == ~T7_E~0); 237#L872-1true assume !(1 == ~E_1~0); 394#L877-1true assume !(1 == ~E_2~0); 581#L882-1true assume !(1 == ~E_3~0); 703#L887-1true assume !(1 == ~E_4~0); 456#L892-1true assume !(1 == ~E_5~0); 651#L897-1true assume 1 == ~E_6~0;~E_6~0 := 2; 197#L902-1true assume !(1 == ~E_7~0); 477#L907-1true assume { :end_inline_reset_delta_events } true; 229#L1148-2true [2022-02-21 04:24:14,251 INFO L793 eck$LassoCheckResult]: Loop: 229#L1148-2true assume !false; 12#L1149true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 112#L729true assume !true; 214#L744true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 215#L514-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 151#L754-3true assume 0 == ~M_E~0;~M_E~0 := 1; 18#L754-5true assume !(0 == ~T1_E~0); 534#L759-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 224#L764-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 609#L769-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 365#L774-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 93#L779-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 16#L784-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 765#L789-3true assume 0 == ~E_1~0;~E_1~0 := 1; 13#L794-3true assume !(0 == ~E_2~0); 35#L799-3true assume 0 == ~E_3~0;~E_3~0 := 1; 154#L804-3true assume 0 == ~E_4~0;~E_4~0 := 1; 291#L809-3true assume 0 == ~E_5~0;~E_5~0 := 1; 34#L814-3true assume 0 == ~E_6~0;~E_6~0 := 1; 529#L819-3true assume 0 == ~E_7~0;~E_7~0 := 1; 487#L824-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 234#L361-24true assume 1 == ~m_pc~0; 85#L362-8true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 300#L372-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 406#L373-8true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 556#L930-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 584#L930-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 347#L380-24true assume 1 == ~t1_pc~0; 585#L381-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 618#L391-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 253#L392-8true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 149#L938-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 442#L938-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 508#L399-24true assume 1 == ~t2_pc~0; 741#L400-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 114#L410-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49#L411-8true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 261#L946-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 146#L946-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 616#L418-24true assume !(1 == ~t3_pc~0); 33#L418-26true is_transmit3_triggered_~__retres1~3#1 := 0; 183#L429-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 147#L430-8true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95#L954-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 414#L954-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 560#L437-24true assume !(1 == ~t4_pc~0); 775#L437-26true is_transmit4_triggered_~__retres1~4#1 := 0; 733#L448-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 457#L449-8true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 86#L962-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 354#L962-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 637#L456-24true assume 1 == ~t5_pc~0; 329#L457-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 304#L467-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 110#L468-8true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 576#L970-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 271#L970-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 759#L475-24true assume !(1 == ~t6_pc~0); 586#L475-26true is_transmit6_triggered_~__retres1~6#1 := 0; 313#L486-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 670#L487-8true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 350#L978-24true assume !(0 != activate_threads_~tmp___5~0#1); 7#L978-26true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 308#L494-24true assume 1 == ~t7_pc~0; 246#L495-8true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 173#L505-8true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 532#L506-8true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 144#L986-24true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 490#L986-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 519#L837-3true assume !(1 == ~M_E~0); 661#L837-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 267#L842-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 603#L847-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 409#L852-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 312#L857-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 739#L862-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 699#L867-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 245#L872-3true assume !(1 == ~E_1~0); 303#L877-3true assume 1 == ~E_2~0;~E_2~0 := 2; 721#L882-3true assume 1 == ~E_3~0;~E_3~0 := 2; 358#L887-3true assume 1 == ~E_4~0;~E_4~0 := 2; 106#L892-3true assume 1 == ~E_5~0;~E_5~0 := 2; 518#L897-3true assume 1 == ~E_6~0;~E_6~0 := 2; 763#L902-3true assume 1 == ~E_7~0;~E_7~0 := 2; 194#L907-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 583#L569-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 370#L611-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 382#L612-1true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 679#L1167true assume !(0 == start_simulation_~tmp~3#1); 232#L1167-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 738#L569-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 255#L611-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 674#L612-2true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 306#L1122true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 222#L1129true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8#L1130true start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 124#L1180true assume !(0 != start_simulation_~tmp___0~1#1); 229#L1148-2true [2022-02-21 04:24:14,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:14,256 INFO L85 PathProgramCache]: Analyzing trace with hash -171938705, now seen corresponding path program 1 times [2022-02-21 04:24:14,261 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:14,262 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [253663515] [2022-02-21 04:24:14,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:14,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:14,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:14,438 INFO L290 TraceCheckUtils]: 0: Hoare triple {779#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {779#true} is VALID [2022-02-21 04:24:14,438 INFO L290 TraceCheckUtils]: 1: Hoare triple {779#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {781#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:14,439 INFO L290 TraceCheckUtils]: 2: Hoare triple {781#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {781#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:14,439 INFO L290 TraceCheckUtils]: 3: Hoare triple {781#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {781#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:14,440 INFO L290 TraceCheckUtils]: 4: Hoare triple {781#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {780#false} is VALID [2022-02-21 04:24:14,440 INFO L290 TraceCheckUtils]: 5: Hoare triple {780#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {780#false} is VALID [2022-02-21 04:24:14,440 INFO L290 TraceCheckUtils]: 6: Hoare triple {780#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {780#false} is VALID [2022-02-21 04:24:14,440 INFO L290 TraceCheckUtils]: 7: Hoare triple {780#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {780#false} is VALID [2022-02-21 04:24:14,440 INFO L290 TraceCheckUtils]: 8: Hoare triple {780#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {780#false} is VALID [2022-02-21 04:24:14,441 INFO L290 TraceCheckUtils]: 9: Hoare triple {780#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {780#false} is VALID [2022-02-21 04:24:14,441 INFO L290 TraceCheckUtils]: 10: Hoare triple {780#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {780#false} is VALID [2022-02-21 04:24:14,441 INFO L290 TraceCheckUtils]: 11: Hoare triple {780#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {780#false} is VALID [2022-02-21 04:24:14,441 INFO L290 TraceCheckUtils]: 12: Hoare triple {780#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {780#false} is VALID [2022-02-21 04:24:14,441 INFO L290 TraceCheckUtils]: 13: Hoare triple {780#false} assume !(0 == ~M_E~0); {780#false} is VALID [2022-02-21 04:24:14,441 INFO L290 TraceCheckUtils]: 14: Hoare triple {780#false} assume !(0 == ~T1_E~0); {780#false} is VALID [2022-02-21 04:24:14,442 INFO L290 TraceCheckUtils]: 15: Hoare triple {780#false} assume !(0 == ~T2_E~0); {780#false} is VALID [2022-02-21 04:24:14,442 INFO L290 TraceCheckUtils]: 16: Hoare triple {780#false} assume !(0 == ~T3_E~0); {780#false} is VALID [2022-02-21 04:24:14,442 INFO L290 TraceCheckUtils]: 17: Hoare triple {780#false} assume !(0 == ~T4_E~0); {780#false} is VALID [2022-02-21 04:24:14,442 INFO L290 TraceCheckUtils]: 18: Hoare triple {780#false} assume !(0 == ~T5_E~0); {780#false} is VALID [2022-02-21 04:24:14,442 INFO L290 TraceCheckUtils]: 19: Hoare triple {780#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {780#false} is VALID [2022-02-21 04:24:14,443 INFO L290 TraceCheckUtils]: 20: Hoare triple {780#false} assume !(0 == ~T7_E~0); {780#false} is VALID [2022-02-21 04:24:14,443 INFO L290 TraceCheckUtils]: 21: Hoare triple {780#false} assume !(0 == ~E_1~0); {780#false} is VALID [2022-02-21 04:24:14,443 INFO L290 TraceCheckUtils]: 22: Hoare triple {780#false} assume !(0 == ~E_2~0); {780#false} is VALID [2022-02-21 04:24:14,443 INFO L290 TraceCheckUtils]: 23: Hoare triple {780#false} assume !(0 == ~E_3~0); {780#false} is VALID [2022-02-21 04:24:14,443 INFO L290 TraceCheckUtils]: 24: Hoare triple {780#false} assume !(0 == ~E_4~0); {780#false} is VALID [2022-02-21 04:24:14,443 INFO L290 TraceCheckUtils]: 25: Hoare triple {780#false} assume !(0 == ~E_5~0); {780#false} is VALID [2022-02-21 04:24:14,444 INFO L290 TraceCheckUtils]: 26: Hoare triple {780#false} assume !(0 == ~E_6~0); {780#false} is VALID [2022-02-21 04:24:14,444 INFO L290 TraceCheckUtils]: 27: Hoare triple {780#false} assume 0 == ~E_7~0;~E_7~0 := 1; {780#false} is VALID [2022-02-21 04:24:14,444 INFO L290 TraceCheckUtils]: 28: Hoare triple {780#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {780#false} is VALID [2022-02-21 04:24:14,444 INFO L290 TraceCheckUtils]: 29: Hoare triple {780#false} assume 1 == ~m_pc~0; {780#false} is VALID [2022-02-21 04:24:14,444 INFO L290 TraceCheckUtils]: 30: Hoare triple {780#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {780#false} is VALID [2022-02-21 04:24:14,445 INFO L290 TraceCheckUtils]: 31: Hoare triple {780#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {780#false} is VALID [2022-02-21 04:24:14,445 INFO L290 TraceCheckUtils]: 32: Hoare triple {780#false} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {780#false} is VALID [2022-02-21 04:24:14,445 INFO L290 TraceCheckUtils]: 33: Hoare triple {780#false} assume !(0 != activate_threads_~tmp~1#1); {780#false} is VALID [2022-02-21 04:24:14,445 INFO L290 TraceCheckUtils]: 34: Hoare triple {780#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {780#false} is VALID [2022-02-21 04:24:14,445 INFO L290 TraceCheckUtils]: 35: Hoare triple {780#false} assume !(1 == ~t1_pc~0); {780#false} is VALID [2022-02-21 04:24:14,446 INFO L290 TraceCheckUtils]: 36: Hoare triple {780#false} is_transmit1_triggered_~__retres1~1#1 := 0; {780#false} is VALID [2022-02-21 04:24:14,446 INFO L290 TraceCheckUtils]: 37: Hoare triple {780#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {780#false} is VALID [2022-02-21 04:24:14,446 INFO L290 TraceCheckUtils]: 38: Hoare triple {780#false} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {780#false} is VALID [2022-02-21 04:24:14,446 INFO L290 TraceCheckUtils]: 39: Hoare triple {780#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {780#false} is VALID [2022-02-21 04:24:14,446 INFO L290 TraceCheckUtils]: 40: Hoare triple {780#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {780#false} is VALID [2022-02-21 04:24:14,446 INFO L290 TraceCheckUtils]: 41: Hoare triple {780#false} assume 1 == ~t2_pc~0; {780#false} is VALID [2022-02-21 04:24:14,447 INFO L290 TraceCheckUtils]: 42: Hoare triple {780#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {780#false} is VALID [2022-02-21 04:24:14,447 INFO L290 TraceCheckUtils]: 43: Hoare triple {780#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {780#false} is VALID [2022-02-21 04:24:14,447 INFO L290 TraceCheckUtils]: 44: Hoare triple {780#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {780#false} is VALID [2022-02-21 04:24:14,447 INFO L290 TraceCheckUtils]: 45: Hoare triple {780#false} assume !(0 != activate_threads_~tmp___1~0#1); {780#false} is VALID [2022-02-21 04:24:14,447 INFO L290 TraceCheckUtils]: 46: Hoare triple {780#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {780#false} is VALID [2022-02-21 04:24:14,448 INFO L290 TraceCheckUtils]: 47: Hoare triple {780#false} assume !(1 == ~t3_pc~0); {780#false} is VALID [2022-02-21 04:24:14,448 INFO L290 TraceCheckUtils]: 48: Hoare triple {780#false} is_transmit3_triggered_~__retres1~3#1 := 0; {780#false} is VALID [2022-02-21 04:24:14,448 INFO L290 TraceCheckUtils]: 49: Hoare triple {780#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {780#false} is VALID [2022-02-21 04:24:14,448 INFO L290 TraceCheckUtils]: 50: Hoare triple {780#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {780#false} is VALID [2022-02-21 04:24:14,448 INFO L290 TraceCheckUtils]: 51: Hoare triple {780#false} assume !(0 != activate_threads_~tmp___2~0#1); {780#false} is VALID [2022-02-21 04:24:14,448 INFO L290 TraceCheckUtils]: 52: Hoare triple {780#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {780#false} is VALID [2022-02-21 04:24:14,449 INFO L290 TraceCheckUtils]: 53: Hoare triple {780#false} assume 1 == ~t4_pc~0; {780#false} is VALID [2022-02-21 04:24:14,449 INFO L290 TraceCheckUtils]: 54: Hoare triple {780#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {780#false} is VALID [2022-02-21 04:24:14,449 INFO L290 TraceCheckUtils]: 55: Hoare triple {780#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {780#false} is VALID [2022-02-21 04:24:14,449 INFO L290 TraceCheckUtils]: 56: Hoare triple {780#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {780#false} is VALID [2022-02-21 04:24:14,449 INFO L290 TraceCheckUtils]: 57: Hoare triple {780#false} assume !(0 != activate_threads_~tmp___3~0#1); {780#false} is VALID [2022-02-21 04:24:14,449 INFO L290 TraceCheckUtils]: 58: Hoare triple {780#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {780#false} is VALID [2022-02-21 04:24:14,450 INFO L290 TraceCheckUtils]: 59: Hoare triple {780#false} assume !(1 == ~t5_pc~0); {780#false} is VALID [2022-02-21 04:24:14,450 INFO L290 TraceCheckUtils]: 60: Hoare triple {780#false} is_transmit5_triggered_~__retres1~5#1 := 0; {780#false} is VALID [2022-02-21 04:24:14,450 INFO L290 TraceCheckUtils]: 61: Hoare triple {780#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {780#false} is VALID [2022-02-21 04:24:14,450 INFO L290 TraceCheckUtils]: 62: Hoare triple {780#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {780#false} is VALID [2022-02-21 04:24:14,450 INFO L290 TraceCheckUtils]: 63: Hoare triple {780#false} assume !(0 != activate_threads_~tmp___4~0#1); {780#false} is VALID [2022-02-21 04:24:14,451 INFO L290 TraceCheckUtils]: 64: Hoare triple {780#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {780#false} is VALID [2022-02-21 04:24:14,451 INFO L290 TraceCheckUtils]: 65: Hoare triple {780#false} assume 1 == ~t6_pc~0; {780#false} is VALID [2022-02-21 04:24:14,451 INFO L290 TraceCheckUtils]: 66: Hoare triple {780#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {780#false} is VALID [2022-02-21 04:24:14,451 INFO L290 TraceCheckUtils]: 67: Hoare triple {780#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {780#false} is VALID [2022-02-21 04:24:14,451 INFO L290 TraceCheckUtils]: 68: Hoare triple {780#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {780#false} is VALID [2022-02-21 04:24:14,451 INFO L290 TraceCheckUtils]: 69: Hoare triple {780#false} assume !(0 != activate_threads_~tmp___5~0#1); {780#false} is VALID [2022-02-21 04:24:14,452 INFO L290 TraceCheckUtils]: 70: Hoare triple {780#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {780#false} is VALID [2022-02-21 04:24:14,452 INFO L290 TraceCheckUtils]: 71: Hoare triple {780#false} assume 1 == ~t7_pc~0; {780#false} is VALID [2022-02-21 04:24:14,452 INFO L290 TraceCheckUtils]: 72: Hoare triple {780#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {780#false} is VALID [2022-02-21 04:24:14,452 INFO L290 TraceCheckUtils]: 73: Hoare triple {780#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {780#false} is VALID [2022-02-21 04:24:14,452 INFO L290 TraceCheckUtils]: 74: Hoare triple {780#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {780#false} is VALID [2022-02-21 04:24:14,453 INFO L290 TraceCheckUtils]: 75: Hoare triple {780#false} assume !(0 != activate_threads_~tmp___6~0#1); {780#false} is VALID [2022-02-21 04:24:14,453 INFO L290 TraceCheckUtils]: 76: Hoare triple {780#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {780#false} is VALID [2022-02-21 04:24:14,453 INFO L290 TraceCheckUtils]: 77: Hoare triple {780#false} assume !(1 == ~M_E~0); {780#false} is VALID [2022-02-21 04:24:14,453 INFO L290 TraceCheckUtils]: 78: Hoare triple {780#false} assume !(1 == ~T1_E~0); {780#false} is VALID [2022-02-21 04:24:14,453 INFO L290 TraceCheckUtils]: 79: Hoare triple {780#false} assume !(1 == ~T2_E~0); {780#false} is VALID [2022-02-21 04:24:14,453 INFO L290 TraceCheckUtils]: 80: Hoare triple {780#false} assume !(1 == ~T3_E~0); {780#false} is VALID [2022-02-21 04:24:14,454 INFO L290 TraceCheckUtils]: 81: Hoare triple {780#false} assume !(1 == ~T4_E~0); {780#false} is VALID [2022-02-21 04:24:14,454 INFO L290 TraceCheckUtils]: 82: Hoare triple {780#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {780#false} is VALID [2022-02-21 04:24:14,454 INFO L290 TraceCheckUtils]: 83: Hoare triple {780#false} assume !(1 == ~T6_E~0); {780#false} is VALID [2022-02-21 04:24:14,454 INFO L290 TraceCheckUtils]: 84: Hoare triple {780#false} assume !(1 == ~T7_E~0); {780#false} is VALID [2022-02-21 04:24:14,454 INFO L290 TraceCheckUtils]: 85: Hoare triple {780#false} assume !(1 == ~E_1~0); {780#false} is VALID [2022-02-21 04:24:14,455 INFO L290 TraceCheckUtils]: 86: Hoare triple {780#false} assume !(1 == ~E_2~0); {780#false} is VALID [2022-02-21 04:24:14,455 INFO L290 TraceCheckUtils]: 87: Hoare triple {780#false} assume !(1 == ~E_3~0); {780#false} is VALID [2022-02-21 04:24:14,455 INFO L290 TraceCheckUtils]: 88: Hoare triple {780#false} assume !(1 == ~E_4~0); {780#false} is VALID [2022-02-21 04:24:14,455 INFO L290 TraceCheckUtils]: 89: Hoare triple {780#false} assume !(1 == ~E_5~0); {780#false} is VALID [2022-02-21 04:24:14,455 INFO L290 TraceCheckUtils]: 90: Hoare triple {780#false} assume 1 == ~E_6~0;~E_6~0 := 2; {780#false} is VALID [2022-02-21 04:24:14,455 INFO L290 TraceCheckUtils]: 91: Hoare triple {780#false} assume !(1 == ~E_7~0); {780#false} is VALID [2022-02-21 04:24:14,456 INFO L290 TraceCheckUtils]: 92: Hoare triple {780#false} assume { :end_inline_reset_delta_events } true; {780#false} is VALID [2022-02-21 04:24:14,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:14,457 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:14,457 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [253663515] [2022-02-21 04:24:14,458 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [253663515] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:14,458 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:14,458 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:14,459 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [720558832] [2022-02-21 04:24:14,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:14,462 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:14,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:14,463 INFO L85 PathProgramCache]: Analyzing trace with hash -1169217165, now seen corresponding path program 1 times [2022-02-21 04:24:14,463 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:14,463 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340178484] [2022-02-21 04:24:14,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:14,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:14,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:14,486 INFO L290 TraceCheckUtils]: 0: Hoare triple {782#true} assume !false; {782#true} is VALID [2022-02-21 04:24:14,486 INFO L290 TraceCheckUtils]: 1: Hoare triple {782#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {782#true} is VALID [2022-02-21 04:24:14,486 INFO L290 TraceCheckUtils]: 2: Hoare triple {782#true} assume !true; {783#false} is VALID [2022-02-21 04:24:14,487 INFO L290 TraceCheckUtils]: 3: Hoare triple {783#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {783#false} is VALID [2022-02-21 04:24:14,487 INFO L290 TraceCheckUtils]: 4: Hoare triple {783#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {783#false} is VALID [2022-02-21 04:24:14,487 INFO L290 TraceCheckUtils]: 5: Hoare triple {783#false} assume 0 == ~M_E~0;~M_E~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,487 INFO L290 TraceCheckUtils]: 6: Hoare triple {783#false} assume !(0 == ~T1_E~0); {783#false} is VALID [2022-02-21 04:24:14,487 INFO L290 TraceCheckUtils]: 7: Hoare triple {783#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,488 INFO L290 TraceCheckUtils]: 8: Hoare triple {783#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,488 INFO L290 TraceCheckUtils]: 9: Hoare triple {783#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,488 INFO L290 TraceCheckUtils]: 10: Hoare triple {783#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,488 INFO L290 TraceCheckUtils]: 11: Hoare triple {783#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,488 INFO L290 TraceCheckUtils]: 12: Hoare triple {783#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,488 INFO L290 TraceCheckUtils]: 13: Hoare triple {783#false} assume 0 == ~E_1~0;~E_1~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,489 INFO L290 TraceCheckUtils]: 14: Hoare triple {783#false} assume !(0 == ~E_2~0); {783#false} is VALID [2022-02-21 04:24:14,489 INFO L290 TraceCheckUtils]: 15: Hoare triple {783#false} assume 0 == ~E_3~0;~E_3~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,489 INFO L290 TraceCheckUtils]: 16: Hoare triple {783#false} assume 0 == ~E_4~0;~E_4~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,489 INFO L290 TraceCheckUtils]: 17: Hoare triple {783#false} assume 0 == ~E_5~0;~E_5~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,489 INFO L290 TraceCheckUtils]: 18: Hoare triple {783#false} assume 0 == ~E_6~0;~E_6~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,490 INFO L290 TraceCheckUtils]: 19: Hoare triple {783#false} assume 0 == ~E_7~0;~E_7~0 := 1; {783#false} is VALID [2022-02-21 04:24:14,490 INFO L290 TraceCheckUtils]: 20: Hoare triple {783#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {783#false} is VALID [2022-02-21 04:24:14,490 INFO L290 TraceCheckUtils]: 21: Hoare triple {783#false} assume 1 == ~m_pc~0; {783#false} is VALID [2022-02-21 04:24:14,490 INFO L290 TraceCheckUtils]: 22: Hoare triple {783#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {783#false} is VALID [2022-02-21 04:24:14,490 INFO L290 TraceCheckUtils]: 23: Hoare triple {783#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {783#false} is VALID [2022-02-21 04:24:14,490 INFO L290 TraceCheckUtils]: 24: Hoare triple {783#false} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {783#false} is VALID [2022-02-21 04:24:14,491 INFO L290 TraceCheckUtils]: 25: Hoare triple {783#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {783#false} is VALID [2022-02-21 04:24:14,491 INFO L290 TraceCheckUtils]: 26: Hoare triple {783#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {783#false} is VALID [2022-02-21 04:24:14,491 INFO L290 TraceCheckUtils]: 27: Hoare triple {783#false} assume 1 == ~t1_pc~0; {783#false} is VALID [2022-02-21 04:24:14,491 INFO L290 TraceCheckUtils]: 28: Hoare triple {783#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {783#false} is VALID [2022-02-21 04:24:14,491 INFO L290 TraceCheckUtils]: 29: Hoare triple {783#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {783#false} is VALID [2022-02-21 04:24:14,492 INFO L290 TraceCheckUtils]: 30: Hoare triple {783#false} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {783#false} is VALID [2022-02-21 04:24:14,492 INFO L290 TraceCheckUtils]: 31: Hoare triple {783#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {783#false} is VALID [2022-02-21 04:24:14,492 INFO L290 TraceCheckUtils]: 32: Hoare triple {783#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {783#false} is VALID [2022-02-21 04:24:14,492 INFO L290 TraceCheckUtils]: 33: Hoare triple {783#false} assume 1 == ~t2_pc~0; {783#false} is VALID [2022-02-21 04:24:14,492 INFO L290 TraceCheckUtils]: 34: Hoare triple {783#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {783#false} is VALID [2022-02-21 04:24:14,492 INFO L290 TraceCheckUtils]: 35: Hoare triple {783#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {783#false} is VALID [2022-02-21 04:24:14,493 INFO L290 TraceCheckUtils]: 36: Hoare triple {783#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {783#false} is VALID [2022-02-21 04:24:14,493 INFO L290 TraceCheckUtils]: 37: Hoare triple {783#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {783#false} is VALID [2022-02-21 04:24:14,493 INFO L290 TraceCheckUtils]: 38: Hoare triple {783#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {783#false} is VALID [2022-02-21 04:24:14,493 INFO L290 TraceCheckUtils]: 39: Hoare triple {783#false} assume !(1 == ~t3_pc~0); {783#false} is VALID [2022-02-21 04:24:14,493 INFO L290 TraceCheckUtils]: 40: Hoare triple {783#false} is_transmit3_triggered_~__retres1~3#1 := 0; {783#false} is VALID [2022-02-21 04:24:14,494 INFO L290 TraceCheckUtils]: 41: Hoare triple {783#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {783#false} is VALID [2022-02-21 04:24:14,494 INFO L290 TraceCheckUtils]: 42: Hoare triple {783#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {783#false} is VALID [2022-02-21 04:24:14,494 INFO L290 TraceCheckUtils]: 43: Hoare triple {783#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {783#false} is VALID [2022-02-21 04:24:14,494 INFO L290 TraceCheckUtils]: 44: Hoare triple {783#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {783#false} is VALID [2022-02-21 04:24:14,494 INFO L290 TraceCheckUtils]: 45: Hoare triple {783#false} assume !(1 == ~t4_pc~0); {783#false} is VALID [2022-02-21 04:24:14,495 INFO L290 TraceCheckUtils]: 46: Hoare triple {783#false} is_transmit4_triggered_~__retres1~4#1 := 0; {783#false} is VALID [2022-02-21 04:24:14,495 INFO L290 TraceCheckUtils]: 47: Hoare triple {783#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {783#false} is VALID [2022-02-21 04:24:14,495 INFO L290 TraceCheckUtils]: 48: Hoare triple {783#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {783#false} is VALID [2022-02-21 04:24:14,495 INFO L290 TraceCheckUtils]: 49: Hoare triple {783#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {783#false} is VALID [2022-02-21 04:24:14,495 INFO L290 TraceCheckUtils]: 50: Hoare triple {783#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {783#false} is VALID [2022-02-21 04:24:14,495 INFO L290 TraceCheckUtils]: 51: Hoare triple {783#false} assume 1 == ~t5_pc~0; {783#false} is VALID [2022-02-21 04:24:14,496 INFO L290 TraceCheckUtils]: 52: Hoare triple {783#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {783#false} is VALID [2022-02-21 04:24:14,496 INFO L290 TraceCheckUtils]: 53: Hoare triple {783#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {783#false} is VALID [2022-02-21 04:24:14,496 INFO L290 TraceCheckUtils]: 54: Hoare triple {783#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {783#false} is VALID [2022-02-21 04:24:14,496 INFO L290 TraceCheckUtils]: 55: Hoare triple {783#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {783#false} is VALID [2022-02-21 04:24:14,496 INFO L290 TraceCheckUtils]: 56: Hoare triple {783#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {783#false} is VALID [2022-02-21 04:24:14,497 INFO L290 TraceCheckUtils]: 57: Hoare triple {783#false} assume !(1 == ~t6_pc~0); {783#false} is VALID [2022-02-21 04:24:14,497 INFO L290 TraceCheckUtils]: 58: Hoare triple {783#false} is_transmit6_triggered_~__retres1~6#1 := 0; {783#false} is VALID [2022-02-21 04:24:14,497 INFO L290 TraceCheckUtils]: 59: Hoare triple {783#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {783#false} is VALID [2022-02-21 04:24:14,497 INFO L290 TraceCheckUtils]: 60: Hoare triple {783#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {783#false} is VALID [2022-02-21 04:24:14,497 INFO L290 TraceCheckUtils]: 61: Hoare triple {783#false} assume !(0 != activate_threads_~tmp___5~0#1); {783#false} is VALID [2022-02-21 04:24:14,497 INFO L290 TraceCheckUtils]: 62: Hoare triple {783#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {783#false} is VALID [2022-02-21 04:24:14,498 INFO L290 TraceCheckUtils]: 63: Hoare triple {783#false} assume 1 == ~t7_pc~0; {783#false} is VALID [2022-02-21 04:24:14,498 INFO L290 TraceCheckUtils]: 64: Hoare triple {783#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {783#false} is VALID [2022-02-21 04:24:14,498 INFO L290 TraceCheckUtils]: 65: Hoare triple {783#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {783#false} is VALID [2022-02-21 04:24:14,498 INFO L290 TraceCheckUtils]: 66: Hoare triple {783#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {783#false} is VALID [2022-02-21 04:24:14,498 INFO L290 TraceCheckUtils]: 67: Hoare triple {783#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {783#false} is VALID [2022-02-21 04:24:14,498 INFO L290 TraceCheckUtils]: 68: Hoare triple {783#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {783#false} is VALID [2022-02-21 04:24:14,499 INFO L290 TraceCheckUtils]: 69: Hoare triple {783#false} assume !(1 == ~M_E~0); {783#false} is VALID [2022-02-21 04:24:14,499 INFO L290 TraceCheckUtils]: 70: Hoare triple {783#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,499 INFO L290 TraceCheckUtils]: 71: Hoare triple {783#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,499 INFO L290 TraceCheckUtils]: 72: Hoare triple {783#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,499 INFO L290 TraceCheckUtils]: 73: Hoare triple {783#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,500 INFO L290 TraceCheckUtils]: 74: Hoare triple {783#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,500 INFO L290 TraceCheckUtils]: 75: Hoare triple {783#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,500 INFO L290 TraceCheckUtils]: 76: Hoare triple {783#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,500 INFO L290 TraceCheckUtils]: 77: Hoare triple {783#false} assume !(1 == ~E_1~0); {783#false} is VALID [2022-02-21 04:24:14,500 INFO L290 TraceCheckUtils]: 78: Hoare triple {783#false} assume 1 == ~E_2~0;~E_2~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,500 INFO L290 TraceCheckUtils]: 79: Hoare triple {783#false} assume 1 == ~E_3~0;~E_3~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,501 INFO L290 TraceCheckUtils]: 80: Hoare triple {783#false} assume 1 == ~E_4~0;~E_4~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,501 INFO L290 TraceCheckUtils]: 81: Hoare triple {783#false} assume 1 == ~E_5~0;~E_5~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,501 INFO L290 TraceCheckUtils]: 82: Hoare triple {783#false} assume 1 == ~E_6~0;~E_6~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,501 INFO L290 TraceCheckUtils]: 83: Hoare triple {783#false} assume 1 == ~E_7~0;~E_7~0 := 2; {783#false} is VALID [2022-02-21 04:24:14,501 INFO L290 TraceCheckUtils]: 84: Hoare triple {783#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {783#false} is VALID [2022-02-21 04:24:14,502 INFO L290 TraceCheckUtils]: 85: Hoare triple {783#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {783#false} is VALID [2022-02-21 04:24:14,502 INFO L290 TraceCheckUtils]: 86: Hoare triple {783#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {783#false} is VALID [2022-02-21 04:24:14,502 INFO L290 TraceCheckUtils]: 87: Hoare triple {783#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {783#false} is VALID [2022-02-21 04:24:14,502 INFO L290 TraceCheckUtils]: 88: Hoare triple {783#false} assume !(0 == start_simulation_~tmp~3#1); {783#false} is VALID [2022-02-21 04:24:14,502 INFO L290 TraceCheckUtils]: 89: Hoare triple {783#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {783#false} is VALID [2022-02-21 04:24:14,503 INFO L290 TraceCheckUtils]: 90: Hoare triple {783#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {783#false} is VALID [2022-02-21 04:24:14,503 INFO L290 TraceCheckUtils]: 91: Hoare triple {783#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {783#false} is VALID [2022-02-21 04:24:14,503 INFO L290 TraceCheckUtils]: 92: Hoare triple {783#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {783#false} is VALID [2022-02-21 04:24:14,503 INFO L290 TraceCheckUtils]: 93: Hoare triple {783#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {783#false} is VALID [2022-02-21 04:24:14,503 INFO L290 TraceCheckUtils]: 94: Hoare triple {783#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {783#false} is VALID [2022-02-21 04:24:14,503 INFO L290 TraceCheckUtils]: 95: Hoare triple {783#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {783#false} is VALID [2022-02-21 04:24:14,504 INFO L290 TraceCheckUtils]: 96: Hoare triple {783#false} assume !(0 != start_simulation_~tmp___0~1#1); {783#false} is VALID [2022-02-21 04:24:14,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:14,504 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:14,504 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340178484] [2022-02-21 04:24:14,505 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340178484] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:14,505 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:14,505 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:14,505 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952514638] [2022-02-21 04:24:14,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:14,506 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:14,507 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:14,526 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:14,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:14,531 INFO L87 Difference]: Start difference. First operand has 775 states, 774 states have (on average 1.5232558139534884) internal successors, (1179), 774 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:15,231 INFO L93 Difference]: Finished difference Result 774 states and 1154 transitions. [2022-02-21 04:24:15,231 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:15,232 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,305 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:15,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 774 states and 1154 transitions. [2022-02-21 04:24:15,333 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:15,358 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 774 states to 768 states and 1148 transitions. [2022-02-21 04:24:15,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-02-21 04:24:15,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-02-21 04:24:15,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1148 transitions. [2022-02-21 04:24:15,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:15,362 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1148 transitions. [2022-02-21 04:24:15,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1148 transitions. [2022-02-21 04:24:15,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-02-21 04:24:15,399 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:15,402 INFO L82 GeneralOperation]: Start isEquivalent. First operand 768 states and 1148 transitions. Second operand has 768 states, 768 states have (on average 1.4947916666666667) internal successors, (1148), 767 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,405 INFO L74 IsIncluded]: Start isIncluded. First operand 768 states and 1148 transitions. Second operand has 768 states, 768 states have (on average 1.4947916666666667) internal successors, (1148), 767 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,407 INFO L87 Difference]: Start difference. First operand 768 states and 1148 transitions. Second operand has 768 states, 768 states have (on average 1.4947916666666667) internal successors, (1148), 767 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:15,431 INFO L93 Difference]: Finished difference Result 768 states and 1148 transitions. [2022-02-21 04:24:15,432 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1148 transitions. [2022-02-21 04:24:15,434 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:15,434 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:15,436 INFO L74 IsIncluded]: Start isIncluded. First operand has 768 states, 768 states have (on average 1.4947916666666667) internal successors, (1148), 767 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1148 transitions. [2022-02-21 04:24:15,437 INFO L87 Difference]: Start difference. First operand has 768 states, 768 states have (on average 1.4947916666666667) internal successors, (1148), 767 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1148 transitions. [2022-02-21 04:24:15,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:15,459 INFO L93 Difference]: Finished difference Result 768 states and 1148 transitions. [2022-02-21 04:24:15,459 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1148 transitions. [2022-02-21 04:24:15,460 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:15,460 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:15,460 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:15,460 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:15,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4947916666666667) internal successors, (1148), 767 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1148 transitions. [2022-02-21 04:24:15,480 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1148 transitions. [2022-02-21 04:24:15,480 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1148 transitions. [2022-02-21 04:24:15,480 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:15,481 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1148 transitions. [2022-02-21 04:24:15,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:15,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:15,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:15,485 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:15,485 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:15,485 INFO L791 eck$LassoCheckResult]: Stem: 2325#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 2304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2305#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1765#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1766#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2182#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2183#L526-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2151#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2074#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2075#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2064#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2065#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2024#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2025#L754 assume !(0 == ~M_E~0); 2283#L754-2 assume !(0 == ~T1_E~0); 1967#L759-1 assume !(0 == ~T2_E~0); 1968#L764-1 assume !(0 == ~T3_E~0); 2312#L769-1 assume !(0 == ~T4_E~0); 2313#L774-1 assume !(0 == ~T5_E~0); 2213#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1998#L784-1 assume !(0 == ~T7_E~0); 1999#L789-1 assume !(0 == ~E_1~0); 1678#L794-1 assume !(0 == ~E_2~0); 1679#L799-1 assume !(0 == ~E_3~0); 2314#L804-1 assume !(0 == ~E_4~0); 2315#L809-1 assume !(0 == ~E_5~0); 2078#L814-1 assume !(0 == ~E_6~0); 1594#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1595#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2060#L361 assume 1 == ~m_pc~0; 2061#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2102#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1883#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1884#L930 assume !(0 != activate_threads_~tmp~1#1); 2208#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2054#L380 assume !(1 == ~t1_pc~0); 1728#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1727#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2233#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2308#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1804#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1729#L399 assume 1 == ~t2_pc~0; 1730#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1936#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2243#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2122#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1634#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1602#L418 assume !(1 == ~t3_pc~0); 1563#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1564#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2082#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2290#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2320#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2285#L437 assume 1 == ~t4_pc~0; 2286#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1904#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1732#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1733#L962 assume !(0 != activate_threads_~tmp___3~0#1); 2161#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1860#L456 assume !(1 == ~t5_pc~0); 1861#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1964#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2264#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1624#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1625#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1748#L475 assume 1 == ~t6_pc~0; 1749#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1824#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1825#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1584#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1585#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2067#L494 assume 1 == ~t7_pc~0; 2068#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2108#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2260#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2261#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2323#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2262#L837 assume !(1 == ~M_E~0); 2125#L837-2 assume !(1 == ~T1_E~0); 1711#L842-1 assume !(1 == ~T2_E~0); 1712#L847-1 assume !(1 == ~T3_E~0); 2178#L852-1 assume !(1 == ~T4_E~0); 2255#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2134#L862-1 assume !(1 == ~T6_E~0); 2135#L867-1 assume !(1 == ~T7_E~0); 2144#L872-1 assume !(1 == ~E_1~0); 2210#L877-1 assume !(1 == ~E_2~0); 2140#L882-1 assume !(1 == ~E_3~0); 2141#L887-1 assume !(1 == ~E_4~0); 1771#L892-1 assume !(1 == ~E_5~0); 1772#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2158#L902-1 assume !(1 == ~E_7~0); 1852#L907-1 assume { :end_inline_reset_delta_events } true; 1853#L1148-2 [2022-02-21 04:24:15,486 INFO L793 eck$LassoCheckResult]: Loop: 1853#L1148-2 assume !false; 1596#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1597#L729 assume !false; 1995#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1991#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1942#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2011#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2049#L626 assume !(0 != eval_~tmp~0#1); 2050#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2180#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2084#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1637#L754-5 assume !(0 == ~T1_E~0); 1638#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2020#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2188#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2189#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1952#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1613#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1614#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1598#L794-3 assume !(0 == ~E_2~0); 1599#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1693#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2090#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1686#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1687#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1886#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1887#L361-24 assume 1 == ~m_pc~0; 1923#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1924#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1606#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1607#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2083#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2147#L380-24 assume 1 == ~t1_pc~0; 2148#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1774#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2206#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2079#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1734#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1735#L399-24 assume 1 == ~t2_pc~0; 1947#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1997#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1775#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1776#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2071#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2072#L418-24 assume !(1 == ~t3_pc~0); 1682#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1683#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2073#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1951#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1626#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1627#L437-24 assume 1 == ~t4_pc~0; 1898#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1899#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1777#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1778#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1926#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2235#L456-24 assume 1 == ~t5_pc~0; 2236#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2296#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1989#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1990#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2129#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2263#L475-24 assume 1 == ~t6_pc~0; 1628#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1629#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2272#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2273#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 1571#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1572#L494-24 assume 1 == ~t7_pc~0; 2229#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2119#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2016#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2017#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1896#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1897#L837-3 assume !(1 == ~M_E~0); 1979#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2259#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2175#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1615#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1616#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2300#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2292#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2226#L872-3 assume !(1 == ~E_1~0); 2227#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2295#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2310#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1982#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1975#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1976#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2152#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2145#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1601#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2321#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2281#L1167 assume !(0 == start_simulation_~tmp~3#1); 2176#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2203#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2008#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2242#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2275#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2190#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1577#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1578#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1853#L1148-2 [2022-02-21 04:24:15,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:15,486 INFO L85 PathProgramCache]: Analyzing trace with hash 598794861, now seen corresponding path program 1 times [2022-02-21 04:24:15,486 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:15,487 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305188563] [2022-02-21 04:24:15,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:15,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:15,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:15,522 INFO L290 TraceCheckUtils]: 0: Hoare triple {3865#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {3865#true} is VALID [2022-02-21 04:24:15,522 INFO L290 TraceCheckUtils]: 1: Hoare triple {3865#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {3867#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:15,523 INFO L290 TraceCheckUtils]: 2: Hoare triple {3867#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {3867#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:15,523 INFO L290 TraceCheckUtils]: 3: Hoare triple {3867#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {3867#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:15,524 INFO L290 TraceCheckUtils]: 4: Hoare triple {3867#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {3867#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:15,524 INFO L290 TraceCheckUtils]: 5: Hoare triple {3867#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {3867#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:15,524 INFO L290 TraceCheckUtils]: 6: Hoare triple {3867#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {3866#false} is VALID [2022-02-21 04:24:15,524 INFO L290 TraceCheckUtils]: 7: Hoare triple {3866#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {3866#false} is VALID [2022-02-21 04:24:15,525 INFO L290 TraceCheckUtils]: 8: Hoare triple {3866#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {3866#false} is VALID [2022-02-21 04:24:15,525 INFO L290 TraceCheckUtils]: 9: Hoare triple {3866#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {3866#false} is VALID [2022-02-21 04:24:15,525 INFO L290 TraceCheckUtils]: 10: Hoare triple {3866#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {3866#false} is VALID [2022-02-21 04:24:15,525 INFO L290 TraceCheckUtils]: 11: Hoare triple {3866#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {3866#false} is VALID [2022-02-21 04:24:15,525 INFO L290 TraceCheckUtils]: 12: Hoare triple {3866#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {3866#false} is VALID [2022-02-21 04:24:15,525 INFO L290 TraceCheckUtils]: 13: Hoare triple {3866#false} assume !(0 == ~M_E~0); {3866#false} is VALID [2022-02-21 04:24:15,525 INFO L290 TraceCheckUtils]: 14: Hoare triple {3866#false} assume !(0 == ~T1_E~0); {3866#false} is VALID [2022-02-21 04:24:15,526 INFO L290 TraceCheckUtils]: 15: Hoare triple {3866#false} assume !(0 == ~T2_E~0); {3866#false} is VALID [2022-02-21 04:24:15,526 INFO L290 TraceCheckUtils]: 16: Hoare triple {3866#false} assume !(0 == ~T3_E~0); {3866#false} is VALID [2022-02-21 04:24:15,526 INFO L290 TraceCheckUtils]: 17: Hoare triple {3866#false} assume !(0 == ~T4_E~0); {3866#false} is VALID [2022-02-21 04:24:15,526 INFO L290 TraceCheckUtils]: 18: Hoare triple {3866#false} assume !(0 == ~T5_E~0); {3866#false} is VALID [2022-02-21 04:24:15,526 INFO L290 TraceCheckUtils]: 19: Hoare triple {3866#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {3866#false} is VALID [2022-02-21 04:24:15,526 INFO L290 TraceCheckUtils]: 20: Hoare triple {3866#false} assume !(0 == ~T7_E~0); {3866#false} is VALID [2022-02-21 04:24:15,527 INFO L290 TraceCheckUtils]: 21: Hoare triple {3866#false} assume !(0 == ~E_1~0); {3866#false} is VALID [2022-02-21 04:24:15,527 INFO L290 TraceCheckUtils]: 22: Hoare triple {3866#false} assume !(0 == ~E_2~0); {3866#false} is VALID [2022-02-21 04:24:15,527 INFO L290 TraceCheckUtils]: 23: Hoare triple {3866#false} assume !(0 == ~E_3~0); {3866#false} is VALID [2022-02-21 04:24:15,527 INFO L290 TraceCheckUtils]: 24: Hoare triple {3866#false} assume !(0 == ~E_4~0); {3866#false} is VALID [2022-02-21 04:24:15,527 INFO L290 TraceCheckUtils]: 25: Hoare triple {3866#false} assume !(0 == ~E_5~0); {3866#false} is VALID [2022-02-21 04:24:15,528 INFO L290 TraceCheckUtils]: 26: Hoare triple {3866#false} assume !(0 == ~E_6~0); {3866#false} is VALID [2022-02-21 04:24:15,528 INFO L290 TraceCheckUtils]: 27: Hoare triple {3866#false} assume 0 == ~E_7~0;~E_7~0 := 1; {3866#false} is VALID [2022-02-21 04:24:15,528 INFO L290 TraceCheckUtils]: 28: Hoare triple {3866#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3866#false} is VALID [2022-02-21 04:24:15,528 INFO L290 TraceCheckUtils]: 29: Hoare triple {3866#false} assume 1 == ~m_pc~0; {3866#false} is VALID [2022-02-21 04:24:15,528 INFO L290 TraceCheckUtils]: 30: Hoare triple {3866#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {3866#false} is VALID [2022-02-21 04:24:15,528 INFO L290 TraceCheckUtils]: 31: Hoare triple {3866#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3866#false} is VALID [2022-02-21 04:24:15,528 INFO L290 TraceCheckUtils]: 32: Hoare triple {3866#false} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {3866#false} is VALID [2022-02-21 04:24:15,529 INFO L290 TraceCheckUtils]: 33: Hoare triple {3866#false} assume !(0 != activate_threads_~tmp~1#1); {3866#false} is VALID [2022-02-21 04:24:15,529 INFO L290 TraceCheckUtils]: 34: Hoare triple {3866#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3866#false} is VALID [2022-02-21 04:24:15,529 INFO L290 TraceCheckUtils]: 35: Hoare triple {3866#false} assume !(1 == ~t1_pc~0); {3866#false} is VALID [2022-02-21 04:24:15,529 INFO L290 TraceCheckUtils]: 36: Hoare triple {3866#false} is_transmit1_triggered_~__retres1~1#1 := 0; {3866#false} is VALID [2022-02-21 04:24:15,529 INFO L290 TraceCheckUtils]: 37: Hoare triple {3866#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3866#false} is VALID [2022-02-21 04:24:15,530 INFO L290 TraceCheckUtils]: 38: Hoare triple {3866#false} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {3866#false} is VALID [2022-02-21 04:24:15,530 INFO L290 TraceCheckUtils]: 39: Hoare triple {3866#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {3866#false} is VALID [2022-02-21 04:24:15,530 INFO L290 TraceCheckUtils]: 40: Hoare triple {3866#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3866#false} is VALID [2022-02-21 04:24:15,530 INFO L290 TraceCheckUtils]: 41: Hoare triple {3866#false} assume 1 == ~t2_pc~0; {3866#false} is VALID [2022-02-21 04:24:15,530 INFO L290 TraceCheckUtils]: 42: Hoare triple {3866#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {3866#false} is VALID [2022-02-21 04:24:15,530 INFO L290 TraceCheckUtils]: 43: Hoare triple {3866#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3866#false} is VALID [2022-02-21 04:24:15,530 INFO L290 TraceCheckUtils]: 44: Hoare triple {3866#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {3866#false} is VALID [2022-02-21 04:24:15,531 INFO L290 TraceCheckUtils]: 45: Hoare triple {3866#false} assume !(0 != activate_threads_~tmp___1~0#1); {3866#false} is VALID [2022-02-21 04:24:15,531 INFO L290 TraceCheckUtils]: 46: Hoare triple {3866#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {3866#false} is VALID [2022-02-21 04:24:15,531 INFO L290 TraceCheckUtils]: 47: Hoare triple {3866#false} assume !(1 == ~t3_pc~0); {3866#false} is VALID [2022-02-21 04:24:15,531 INFO L290 TraceCheckUtils]: 48: Hoare triple {3866#false} is_transmit3_triggered_~__retres1~3#1 := 0; {3866#false} is VALID [2022-02-21 04:24:15,531 INFO L290 TraceCheckUtils]: 49: Hoare triple {3866#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {3866#false} is VALID [2022-02-21 04:24:15,532 INFO L290 TraceCheckUtils]: 50: Hoare triple {3866#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {3866#false} is VALID [2022-02-21 04:24:15,532 INFO L290 TraceCheckUtils]: 51: Hoare triple {3866#false} assume !(0 != activate_threads_~tmp___2~0#1); {3866#false} is VALID [2022-02-21 04:24:15,532 INFO L290 TraceCheckUtils]: 52: Hoare triple {3866#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {3866#false} is VALID [2022-02-21 04:24:15,532 INFO L290 TraceCheckUtils]: 53: Hoare triple {3866#false} assume 1 == ~t4_pc~0; {3866#false} is VALID [2022-02-21 04:24:15,532 INFO L290 TraceCheckUtils]: 54: Hoare triple {3866#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {3866#false} is VALID [2022-02-21 04:24:15,532 INFO L290 TraceCheckUtils]: 55: Hoare triple {3866#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {3866#false} is VALID [2022-02-21 04:24:15,533 INFO L290 TraceCheckUtils]: 56: Hoare triple {3866#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {3866#false} is VALID [2022-02-21 04:24:15,533 INFO L290 TraceCheckUtils]: 57: Hoare triple {3866#false} assume !(0 != activate_threads_~tmp___3~0#1); {3866#false} is VALID [2022-02-21 04:24:15,533 INFO L290 TraceCheckUtils]: 58: Hoare triple {3866#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {3866#false} is VALID [2022-02-21 04:24:15,533 INFO L290 TraceCheckUtils]: 59: Hoare triple {3866#false} assume !(1 == ~t5_pc~0); {3866#false} is VALID [2022-02-21 04:24:15,533 INFO L290 TraceCheckUtils]: 60: Hoare triple {3866#false} is_transmit5_triggered_~__retres1~5#1 := 0; {3866#false} is VALID [2022-02-21 04:24:15,533 INFO L290 TraceCheckUtils]: 61: Hoare triple {3866#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {3866#false} is VALID [2022-02-21 04:24:15,534 INFO L290 TraceCheckUtils]: 62: Hoare triple {3866#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {3866#false} is VALID [2022-02-21 04:24:15,534 INFO L290 TraceCheckUtils]: 63: Hoare triple {3866#false} assume !(0 != activate_threads_~tmp___4~0#1); {3866#false} is VALID [2022-02-21 04:24:15,534 INFO L290 TraceCheckUtils]: 64: Hoare triple {3866#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {3866#false} is VALID [2022-02-21 04:24:15,534 INFO L290 TraceCheckUtils]: 65: Hoare triple {3866#false} assume 1 == ~t6_pc~0; {3866#false} is VALID [2022-02-21 04:24:15,534 INFO L290 TraceCheckUtils]: 66: Hoare triple {3866#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {3866#false} is VALID [2022-02-21 04:24:15,534 INFO L290 TraceCheckUtils]: 67: Hoare triple {3866#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {3866#false} is VALID [2022-02-21 04:24:15,535 INFO L290 TraceCheckUtils]: 68: Hoare triple {3866#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {3866#false} is VALID [2022-02-21 04:24:15,535 INFO L290 TraceCheckUtils]: 69: Hoare triple {3866#false} assume !(0 != activate_threads_~tmp___5~0#1); {3866#false} is VALID [2022-02-21 04:24:15,535 INFO L290 TraceCheckUtils]: 70: Hoare triple {3866#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {3866#false} is VALID [2022-02-21 04:24:15,535 INFO L290 TraceCheckUtils]: 71: Hoare triple {3866#false} assume 1 == ~t7_pc~0; {3866#false} is VALID [2022-02-21 04:24:15,535 INFO L290 TraceCheckUtils]: 72: Hoare triple {3866#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {3866#false} is VALID [2022-02-21 04:24:15,535 INFO L290 TraceCheckUtils]: 73: Hoare triple {3866#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {3866#false} is VALID [2022-02-21 04:24:15,535 INFO L290 TraceCheckUtils]: 74: Hoare triple {3866#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {3866#false} is VALID [2022-02-21 04:24:15,536 INFO L290 TraceCheckUtils]: 75: Hoare triple {3866#false} assume !(0 != activate_threads_~tmp___6~0#1); {3866#false} is VALID [2022-02-21 04:24:15,536 INFO L290 TraceCheckUtils]: 76: Hoare triple {3866#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3866#false} is VALID [2022-02-21 04:24:15,536 INFO L290 TraceCheckUtils]: 77: Hoare triple {3866#false} assume !(1 == ~M_E~0); {3866#false} is VALID [2022-02-21 04:24:15,536 INFO L290 TraceCheckUtils]: 78: Hoare triple {3866#false} assume !(1 == ~T1_E~0); {3866#false} is VALID [2022-02-21 04:24:15,536 INFO L290 TraceCheckUtils]: 79: Hoare triple {3866#false} assume !(1 == ~T2_E~0); {3866#false} is VALID [2022-02-21 04:24:15,536 INFO L290 TraceCheckUtils]: 80: Hoare triple {3866#false} assume !(1 == ~T3_E~0); {3866#false} is VALID [2022-02-21 04:24:15,536 INFO L290 TraceCheckUtils]: 81: Hoare triple {3866#false} assume !(1 == ~T4_E~0); {3866#false} is VALID [2022-02-21 04:24:15,537 INFO L290 TraceCheckUtils]: 82: Hoare triple {3866#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {3866#false} is VALID [2022-02-21 04:24:15,537 INFO L290 TraceCheckUtils]: 83: Hoare triple {3866#false} assume !(1 == ~T6_E~0); {3866#false} is VALID [2022-02-21 04:24:15,537 INFO L290 TraceCheckUtils]: 84: Hoare triple {3866#false} assume !(1 == ~T7_E~0); {3866#false} is VALID [2022-02-21 04:24:15,537 INFO L290 TraceCheckUtils]: 85: Hoare triple {3866#false} assume !(1 == ~E_1~0); {3866#false} is VALID [2022-02-21 04:24:15,537 INFO L290 TraceCheckUtils]: 86: Hoare triple {3866#false} assume !(1 == ~E_2~0); {3866#false} is VALID [2022-02-21 04:24:15,537 INFO L290 TraceCheckUtils]: 87: Hoare triple {3866#false} assume !(1 == ~E_3~0); {3866#false} is VALID [2022-02-21 04:24:15,537 INFO L290 TraceCheckUtils]: 88: Hoare triple {3866#false} assume !(1 == ~E_4~0); {3866#false} is VALID [2022-02-21 04:24:15,538 INFO L290 TraceCheckUtils]: 89: Hoare triple {3866#false} assume !(1 == ~E_5~0); {3866#false} is VALID [2022-02-21 04:24:15,538 INFO L290 TraceCheckUtils]: 90: Hoare triple {3866#false} assume 1 == ~E_6~0;~E_6~0 := 2; {3866#false} is VALID [2022-02-21 04:24:15,538 INFO L290 TraceCheckUtils]: 91: Hoare triple {3866#false} assume !(1 == ~E_7~0); {3866#false} is VALID [2022-02-21 04:24:15,538 INFO L290 TraceCheckUtils]: 92: Hoare triple {3866#false} assume { :end_inline_reset_delta_events } true; {3866#false} is VALID [2022-02-21 04:24:15,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:15,539 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:15,539 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305188563] [2022-02-21 04:24:15,539 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305188563] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:15,539 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:15,539 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:15,539 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1310429638] [2022-02-21 04:24:15,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:15,540 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:15,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:15,540 INFO L85 PathProgramCache]: Analyzing trace with hash 1141273896, now seen corresponding path program 1 times [2022-02-21 04:24:15,541 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:15,541 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692559494] [2022-02-21 04:24:15,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:15,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:15,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:15,632 INFO L290 TraceCheckUtils]: 0: Hoare triple {3868#true} assume !false; {3868#true} is VALID [2022-02-21 04:24:15,633 INFO L290 TraceCheckUtils]: 1: Hoare triple {3868#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {3868#true} is VALID [2022-02-21 04:24:15,633 INFO L290 TraceCheckUtils]: 2: Hoare triple {3868#true} assume !false; {3868#true} is VALID [2022-02-21 04:24:15,633 INFO L290 TraceCheckUtils]: 3: Hoare triple {3868#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {3868#true} is VALID [2022-02-21 04:24:15,633 INFO L290 TraceCheckUtils]: 4: Hoare triple {3868#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {3868#true} is VALID [2022-02-21 04:24:15,633 INFO L290 TraceCheckUtils]: 5: Hoare triple {3868#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {3868#true} is VALID [2022-02-21 04:24:15,634 INFO L290 TraceCheckUtils]: 6: Hoare triple {3868#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {3868#true} is VALID [2022-02-21 04:24:15,634 INFO L290 TraceCheckUtils]: 7: Hoare triple {3868#true} assume !(0 != eval_~tmp~0#1); {3868#true} is VALID [2022-02-21 04:24:15,634 INFO L290 TraceCheckUtils]: 8: Hoare triple {3868#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {3868#true} is VALID [2022-02-21 04:24:15,634 INFO L290 TraceCheckUtils]: 9: Hoare triple {3868#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {3868#true} is VALID [2022-02-21 04:24:15,634 INFO L290 TraceCheckUtils]: 10: Hoare triple {3868#true} assume 0 == ~M_E~0;~M_E~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,635 INFO L290 TraceCheckUtils]: 11: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,635 INFO L290 TraceCheckUtils]: 12: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,639 INFO L290 TraceCheckUtils]: 13: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,639 INFO L290 TraceCheckUtils]: 14: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,640 INFO L290 TraceCheckUtils]: 15: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,640 INFO L290 TraceCheckUtils]: 16: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,640 INFO L290 TraceCheckUtils]: 17: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,640 INFO L290 TraceCheckUtils]: 18: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,641 INFO L290 TraceCheckUtils]: 19: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,641 INFO L290 TraceCheckUtils]: 20: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,641 INFO L290 TraceCheckUtils]: 21: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,642 INFO L290 TraceCheckUtils]: 22: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,642 INFO L290 TraceCheckUtils]: 23: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,642 INFO L290 TraceCheckUtils]: 24: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,643 INFO L290 TraceCheckUtils]: 25: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,643 INFO L290 TraceCheckUtils]: 26: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,643 INFO L290 TraceCheckUtils]: 27: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,643 INFO L290 TraceCheckUtils]: 28: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,644 INFO L290 TraceCheckUtils]: 29: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,644 INFO L290 TraceCheckUtils]: 30: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,645 INFO L290 TraceCheckUtils]: 31: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,645 INFO L290 TraceCheckUtils]: 32: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,645 INFO L290 TraceCheckUtils]: 33: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,646 INFO L290 TraceCheckUtils]: 34: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,646 INFO L290 TraceCheckUtils]: 35: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,646 INFO L290 TraceCheckUtils]: 36: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,647 INFO L290 TraceCheckUtils]: 37: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,647 INFO L290 TraceCheckUtils]: 38: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,647 INFO L290 TraceCheckUtils]: 39: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,648 INFO L290 TraceCheckUtils]: 40: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,648 INFO L290 TraceCheckUtils]: 41: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,648 INFO L290 TraceCheckUtils]: 42: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,649 INFO L290 TraceCheckUtils]: 43: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,649 INFO L290 TraceCheckUtils]: 44: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,649 INFO L290 TraceCheckUtils]: 45: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,649 INFO L290 TraceCheckUtils]: 46: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,650 INFO L290 TraceCheckUtils]: 47: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,650 INFO L290 TraceCheckUtils]: 48: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,650 INFO L290 TraceCheckUtils]: 49: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,651 INFO L290 TraceCheckUtils]: 50: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,651 INFO L290 TraceCheckUtils]: 51: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,651 INFO L290 TraceCheckUtils]: 52: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,652 INFO L290 TraceCheckUtils]: 53: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,652 INFO L290 TraceCheckUtils]: 54: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,652 INFO L290 TraceCheckUtils]: 55: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,653 INFO L290 TraceCheckUtils]: 56: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,653 INFO L290 TraceCheckUtils]: 57: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,653 INFO L290 TraceCheckUtils]: 58: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,653 INFO L290 TraceCheckUtils]: 59: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,654 INFO L290 TraceCheckUtils]: 60: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,654 INFO L290 TraceCheckUtils]: 61: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,654 INFO L290 TraceCheckUtils]: 62: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,655 INFO L290 TraceCheckUtils]: 63: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,655 INFO L290 TraceCheckUtils]: 64: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,655 INFO L290 TraceCheckUtils]: 65: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,656 INFO L290 TraceCheckUtils]: 66: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,656 INFO L290 TraceCheckUtils]: 67: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,656 INFO L290 TraceCheckUtils]: 68: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,657 INFO L290 TraceCheckUtils]: 69: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,657 INFO L290 TraceCheckUtils]: 70: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,657 INFO L290 TraceCheckUtils]: 71: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,657 INFO L290 TraceCheckUtils]: 72: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,658 INFO L290 TraceCheckUtils]: 73: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3870#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:15,658 INFO L290 TraceCheckUtils]: 74: Hoare triple {3870#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {3869#false} is VALID [2022-02-21 04:24:15,658 INFO L290 TraceCheckUtils]: 75: Hoare triple {3869#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,658 INFO L290 TraceCheckUtils]: 76: Hoare triple {3869#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,658 INFO L290 TraceCheckUtils]: 77: Hoare triple {3869#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,659 INFO L290 TraceCheckUtils]: 78: Hoare triple {3869#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,659 INFO L290 TraceCheckUtils]: 79: Hoare triple {3869#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,659 INFO L290 TraceCheckUtils]: 80: Hoare triple {3869#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,659 INFO L290 TraceCheckUtils]: 81: Hoare triple {3869#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,659 INFO L290 TraceCheckUtils]: 82: Hoare triple {3869#false} assume !(1 == ~E_1~0); {3869#false} is VALID [2022-02-21 04:24:15,659 INFO L290 TraceCheckUtils]: 83: Hoare triple {3869#false} assume 1 == ~E_2~0;~E_2~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,659 INFO L290 TraceCheckUtils]: 84: Hoare triple {3869#false} assume 1 == ~E_3~0;~E_3~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,660 INFO L290 TraceCheckUtils]: 85: Hoare triple {3869#false} assume 1 == ~E_4~0;~E_4~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,660 INFO L290 TraceCheckUtils]: 86: Hoare triple {3869#false} assume 1 == ~E_5~0;~E_5~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,660 INFO L290 TraceCheckUtils]: 87: Hoare triple {3869#false} assume 1 == ~E_6~0;~E_6~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,660 INFO L290 TraceCheckUtils]: 88: Hoare triple {3869#false} assume 1 == ~E_7~0;~E_7~0 := 2; {3869#false} is VALID [2022-02-21 04:24:15,660 INFO L290 TraceCheckUtils]: 89: Hoare triple {3869#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {3869#false} is VALID [2022-02-21 04:24:15,660 INFO L290 TraceCheckUtils]: 90: Hoare triple {3869#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {3869#false} is VALID [2022-02-21 04:24:15,660 INFO L290 TraceCheckUtils]: 91: Hoare triple {3869#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {3869#false} is VALID [2022-02-21 04:24:15,661 INFO L290 TraceCheckUtils]: 92: Hoare triple {3869#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {3869#false} is VALID [2022-02-21 04:24:15,661 INFO L290 TraceCheckUtils]: 93: Hoare triple {3869#false} assume !(0 == start_simulation_~tmp~3#1); {3869#false} is VALID [2022-02-21 04:24:15,661 INFO L290 TraceCheckUtils]: 94: Hoare triple {3869#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {3869#false} is VALID [2022-02-21 04:24:15,661 INFO L290 TraceCheckUtils]: 95: Hoare triple {3869#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {3869#false} is VALID [2022-02-21 04:24:15,661 INFO L290 TraceCheckUtils]: 96: Hoare triple {3869#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {3869#false} is VALID [2022-02-21 04:24:15,661 INFO L290 TraceCheckUtils]: 97: Hoare triple {3869#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {3869#false} is VALID [2022-02-21 04:24:15,661 INFO L290 TraceCheckUtils]: 98: Hoare triple {3869#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {3869#false} is VALID [2022-02-21 04:24:15,661 INFO L290 TraceCheckUtils]: 99: Hoare triple {3869#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {3869#false} is VALID [2022-02-21 04:24:15,662 INFO L290 TraceCheckUtils]: 100: Hoare triple {3869#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {3869#false} is VALID [2022-02-21 04:24:15,662 INFO L290 TraceCheckUtils]: 101: Hoare triple {3869#false} assume !(0 != start_simulation_~tmp___0~1#1); {3869#false} is VALID [2022-02-21 04:24:15,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:15,663 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:15,663 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1692559494] [2022-02-21 04:24:15,663 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1692559494] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:15,663 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:15,663 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:15,663 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378379756] [2022-02-21 04:24:15,664 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:15,664 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:15,664 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:15,664 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:15,665 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:15,665 INFO L87 Difference]: Start difference. First operand 768 states and 1148 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:16,324 INFO L93 Difference]: Finished difference Result 768 states and 1147 transitions. [2022-02-21 04:24:16,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:16,325 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,380 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:16,381 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1147 transitions. [2022-02-21 04:24:16,400 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:16,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1147 transitions. [2022-02-21 04:24:16,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-02-21 04:24:16,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-02-21 04:24:16,418 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1147 transitions. [2022-02-21 04:24:16,419 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:16,419 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1147 transitions. [2022-02-21 04:24:16,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1147 transitions. [2022-02-21 04:24:16,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-02-21 04:24:16,433 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:16,435 INFO L82 GeneralOperation]: Start isEquivalent. First operand 768 states and 1147 transitions. Second operand has 768 states, 768 states have (on average 1.4934895833333333) internal successors, (1147), 767 states have internal predecessors, (1147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,437 INFO L74 IsIncluded]: Start isIncluded. First operand 768 states and 1147 transitions. Second operand has 768 states, 768 states have (on average 1.4934895833333333) internal successors, (1147), 767 states have internal predecessors, (1147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,438 INFO L87 Difference]: Start difference. First operand 768 states and 1147 transitions. Second operand has 768 states, 768 states have (on average 1.4934895833333333) internal successors, (1147), 767 states have internal predecessors, (1147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:16,455 INFO L93 Difference]: Finished difference Result 768 states and 1147 transitions. [2022-02-21 04:24:16,456 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1147 transitions. [2022-02-21 04:24:16,457 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:16,457 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:16,459 INFO L74 IsIncluded]: Start isIncluded. First operand has 768 states, 768 states have (on average 1.4934895833333333) internal successors, (1147), 767 states have internal predecessors, (1147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1147 transitions. [2022-02-21 04:24:16,460 INFO L87 Difference]: Start difference. First operand has 768 states, 768 states have (on average 1.4934895833333333) internal successors, (1147), 767 states have internal predecessors, (1147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1147 transitions. [2022-02-21 04:24:16,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:16,476 INFO L93 Difference]: Finished difference Result 768 states and 1147 transitions. [2022-02-21 04:24:16,476 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1147 transitions. [2022-02-21 04:24:16,477 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:16,477 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:16,478 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:16,478 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:16,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4934895833333333) internal successors, (1147), 767 states have internal predecessors, (1147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:16,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1147 transitions. [2022-02-21 04:24:16,495 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1147 transitions. [2022-02-21 04:24:16,495 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1147 transitions. [2022-02-21 04:24:16,495 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:16,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1147 transitions. [2022-02-21 04:24:16,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:16,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:16,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:16,499 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:16,499 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:16,499 INFO L791 eck$LassoCheckResult]: Stem: 5406#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 5385#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5386#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4846#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4847#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 5263#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5264#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5232#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5155#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5156#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5145#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5146#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5105#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5106#L754 assume !(0 == ~M_E~0); 5364#L754-2 assume !(0 == ~T1_E~0); 5048#L759-1 assume !(0 == ~T2_E~0); 5049#L764-1 assume !(0 == ~T3_E~0); 5393#L769-1 assume !(0 == ~T4_E~0); 5394#L774-1 assume !(0 == ~T5_E~0); 5294#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5079#L784-1 assume !(0 == ~T7_E~0); 5080#L789-1 assume !(0 == ~E_1~0); 4759#L794-1 assume !(0 == ~E_2~0); 4760#L799-1 assume !(0 == ~E_3~0); 5395#L804-1 assume !(0 == ~E_4~0); 5396#L809-1 assume !(0 == ~E_5~0); 5159#L814-1 assume !(0 == ~E_6~0); 4675#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4676#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5141#L361 assume 1 == ~m_pc~0; 5142#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5183#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4964#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4965#L930 assume !(0 != activate_threads_~tmp~1#1); 5289#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5135#L380 assume !(1 == ~t1_pc~0); 4809#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4808#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5314#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5389#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4885#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4810#L399 assume 1 == ~t2_pc~0; 4811#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5017#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5324#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5203#L946 assume !(0 != activate_threads_~tmp___1~0#1); 4715#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4683#L418 assume !(1 == ~t3_pc~0); 4644#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4645#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5163#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5371#L954 assume !(0 != activate_threads_~tmp___2~0#1); 5401#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5366#L437 assume 1 == ~t4_pc~0; 5367#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4986#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4813#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4814#L962 assume !(0 != activate_threads_~tmp___3~0#1); 5242#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4941#L456 assume !(1 == ~t5_pc~0); 4942#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5045#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5345#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4705#L970 assume !(0 != activate_threads_~tmp___4~0#1); 4706#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4829#L475 assume 1 == ~t6_pc~0; 4830#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4905#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4906#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4665#L978 assume !(0 != activate_threads_~tmp___5~0#1); 4666#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5148#L494 assume 1 == ~t7_pc~0; 5149#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5189#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5341#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5342#L986 assume !(0 != activate_threads_~tmp___6~0#1); 5404#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5343#L837 assume !(1 == ~M_E~0); 5206#L837-2 assume !(1 == ~T1_E~0); 4792#L842-1 assume !(1 == ~T2_E~0); 4793#L847-1 assume !(1 == ~T3_E~0); 5259#L852-1 assume !(1 == ~T4_E~0); 5336#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5215#L862-1 assume !(1 == ~T6_E~0); 5216#L867-1 assume !(1 == ~T7_E~0); 5225#L872-1 assume !(1 == ~E_1~0); 5291#L877-1 assume !(1 == ~E_2~0); 5221#L882-1 assume !(1 == ~E_3~0); 5222#L887-1 assume !(1 == ~E_4~0); 4852#L892-1 assume !(1 == ~E_5~0); 4853#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5239#L902-1 assume !(1 == ~E_7~0); 4933#L907-1 assume { :end_inline_reset_delta_events } true; 4934#L1148-2 [2022-02-21 04:24:16,500 INFO L793 eck$LassoCheckResult]: Loop: 4934#L1148-2 assume !false; 4677#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4678#L729 assume !false; 5076#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5072#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5023#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5092#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5130#L626 assume !(0 != eval_~tmp~0#1); 5131#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5261#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5165#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4718#L754-5 assume !(0 == ~T1_E~0); 4719#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5101#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5269#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5270#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5033#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4694#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4695#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4679#L794-3 assume !(0 == ~E_2~0); 4680#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4771#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5171#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4767#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4768#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4967#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4968#L361-24 assume 1 == ~m_pc~0; 5004#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5005#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4687#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4688#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5164#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5228#L380-24 assume !(1 == ~t1_pc~0); 4854#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 4855#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5287#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5160#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4815#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4816#L399-24 assume 1 == ~t2_pc~0; 5028#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5078#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4856#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4857#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5152#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5153#L418-24 assume 1 == ~t3_pc~0; 5157#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4764#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5154#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5032#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4707#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4708#L437-24 assume 1 == ~t4_pc~0; 4979#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4980#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4858#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4859#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5007#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5316#L456-24 assume 1 == ~t5_pc~0; 5317#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5377#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5070#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5071#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5210#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5344#L475-24 assume 1 == ~t6_pc~0; 4709#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4710#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5353#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5354#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 4652#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4653#L494-24 assume !(1 == ~t7_pc~0); 5220#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 5200#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5097#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5098#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4977#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4978#L837-3 assume !(1 == ~M_E~0); 5060#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5340#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5256#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4696#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4697#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5381#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5373#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5307#L872-3 assume !(1 == ~E_1~0); 5308#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5376#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5391#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5063#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5056#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5057#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5233#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5226#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4682#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5402#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5362#L1167 assume !(0 == start_simulation_~tmp~3#1); 5257#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5284#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5089#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5323#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5356#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5271#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4658#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4659#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 4934#L1148-2 [2022-02-21 04:24:16,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:16,500 INFO L85 PathProgramCache]: Analyzing trace with hash 1185071083, now seen corresponding path program 1 times [2022-02-21 04:24:16,501 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:16,501 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1888198674] [2022-02-21 04:24:16,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:16,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:16,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:16,525 INFO L290 TraceCheckUtils]: 0: Hoare triple {6946#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {6946#true} is VALID [2022-02-21 04:24:16,525 INFO L290 TraceCheckUtils]: 1: Hoare triple {6946#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {6948#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:16,526 INFO L290 TraceCheckUtils]: 2: Hoare triple {6948#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {6948#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:16,526 INFO L290 TraceCheckUtils]: 3: Hoare triple {6948#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {6948#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:16,526 INFO L290 TraceCheckUtils]: 4: Hoare triple {6948#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {6948#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:16,527 INFO L290 TraceCheckUtils]: 5: Hoare triple {6948#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {6948#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:16,527 INFO L290 TraceCheckUtils]: 6: Hoare triple {6948#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {6948#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:16,527 INFO L290 TraceCheckUtils]: 7: Hoare triple {6948#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {6947#false} is VALID [2022-02-21 04:24:16,527 INFO L290 TraceCheckUtils]: 8: Hoare triple {6947#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {6947#false} is VALID [2022-02-21 04:24:16,527 INFO L290 TraceCheckUtils]: 9: Hoare triple {6947#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {6947#false} is VALID [2022-02-21 04:24:16,527 INFO L290 TraceCheckUtils]: 10: Hoare triple {6947#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {6947#false} is VALID [2022-02-21 04:24:16,528 INFO L290 TraceCheckUtils]: 11: Hoare triple {6947#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {6947#false} is VALID [2022-02-21 04:24:16,528 INFO L290 TraceCheckUtils]: 12: Hoare triple {6947#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {6947#false} is VALID [2022-02-21 04:24:16,528 INFO L290 TraceCheckUtils]: 13: Hoare triple {6947#false} assume !(0 == ~M_E~0); {6947#false} is VALID [2022-02-21 04:24:16,528 INFO L290 TraceCheckUtils]: 14: Hoare triple {6947#false} assume !(0 == ~T1_E~0); {6947#false} is VALID [2022-02-21 04:24:16,528 INFO L290 TraceCheckUtils]: 15: Hoare triple {6947#false} assume !(0 == ~T2_E~0); {6947#false} is VALID [2022-02-21 04:24:16,528 INFO L290 TraceCheckUtils]: 16: Hoare triple {6947#false} assume !(0 == ~T3_E~0); {6947#false} is VALID [2022-02-21 04:24:16,528 INFO L290 TraceCheckUtils]: 17: Hoare triple {6947#false} assume !(0 == ~T4_E~0); {6947#false} is VALID [2022-02-21 04:24:16,529 INFO L290 TraceCheckUtils]: 18: Hoare triple {6947#false} assume !(0 == ~T5_E~0); {6947#false} is VALID [2022-02-21 04:24:16,529 INFO L290 TraceCheckUtils]: 19: Hoare triple {6947#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {6947#false} is VALID [2022-02-21 04:24:16,529 INFO L290 TraceCheckUtils]: 20: Hoare triple {6947#false} assume !(0 == ~T7_E~0); {6947#false} is VALID [2022-02-21 04:24:16,529 INFO L290 TraceCheckUtils]: 21: Hoare triple {6947#false} assume !(0 == ~E_1~0); {6947#false} is VALID [2022-02-21 04:24:16,529 INFO L290 TraceCheckUtils]: 22: Hoare triple {6947#false} assume !(0 == ~E_2~0); {6947#false} is VALID [2022-02-21 04:24:16,529 INFO L290 TraceCheckUtils]: 23: Hoare triple {6947#false} assume !(0 == ~E_3~0); {6947#false} is VALID [2022-02-21 04:24:16,529 INFO L290 TraceCheckUtils]: 24: Hoare triple {6947#false} assume !(0 == ~E_4~0); {6947#false} is VALID [2022-02-21 04:24:16,529 INFO L290 TraceCheckUtils]: 25: Hoare triple {6947#false} assume !(0 == ~E_5~0); {6947#false} is VALID [2022-02-21 04:24:16,530 INFO L290 TraceCheckUtils]: 26: Hoare triple {6947#false} assume !(0 == ~E_6~0); {6947#false} is VALID [2022-02-21 04:24:16,530 INFO L290 TraceCheckUtils]: 27: Hoare triple {6947#false} assume 0 == ~E_7~0;~E_7~0 := 1; {6947#false} is VALID [2022-02-21 04:24:16,530 INFO L290 TraceCheckUtils]: 28: Hoare triple {6947#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6947#false} is VALID [2022-02-21 04:24:16,530 INFO L290 TraceCheckUtils]: 29: Hoare triple {6947#false} assume 1 == ~m_pc~0; {6947#false} is VALID [2022-02-21 04:24:16,530 INFO L290 TraceCheckUtils]: 30: Hoare triple {6947#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {6947#false} is VALID [2022-02-21 04:24:16,530 INFO L290 TraceCheckUtils]: 31: Hoare triple {6947#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6947#false} is VALID [2022-02-21 04:24:16,530 INFO L290 TraceCheckUtils]: 32: Hoare triple {6947#false} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {6947#false} is VALID [2022-02-21 04:24:16,530 INFO L290 TraceCheckUtils]: 33: Hoare triple {6947#false} assume !(0 != activate_threads_~tmp~1#1); {6947#false} is VALID [2022-02-21 04:24:16,531 INFO L290 TraceCheckUtils]: 34: Hoare triple {6947#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6947#false} is VALID [2022-02-21 04:24:16,531 INFO L290 TraceCheckUtils]: 35: Hoare triple {6947#false} assume !(1 == ~t1_pc~0); {6947#false} is VALID [2022-02-21 04:24:16,531 INFO L290 TraceCheckUtils]: 36: Hoare triple {6947#false} is_transmit1_triggered_~__retres1~1#1 := 0; {6947#false} is VALID [2022-02-21 04:24:16,531 INFO L290 TraceCheckUtils]: 37: Hoare triple {6947#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6947#false} is VALID [2022-02-21 04:24:16,531 INFO L290 TraceCheckUtils]: 38: Hoare triple {6947#false} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {6947#false} is VALID [2022-02-21 04:24:16,531 INFO L290 TraceCheckUtils]: 39: Hoare triple {6947#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {6947#false} is VALID [2022-02-21 04:24:16,531 INFO L290 TraceCheckUtils]: 40: Hoare triple {6947#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6947#false} is VALID [2022-02-21 04:24:16,531 INFO L290 TraceCheckUtils]: 41: Hoare triple {6947#false} assume 1 == ~t2_pc~0; {6947#false} is VALID [2022-02-21 04:24:16,532 INFO L290 TraceCheckUtils]: 42: Hoare triple {6947#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6947#false} is VALID [2022-02-21 04:24:16,532 INFO L290 TraceCheckUtils]: 43: Hoare triple {6947#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6947#false} is VALID [2022-02-21 04:24:16,532 INFO L290 TraceCheckUtils]: 44: Hoare triple {6947#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {6947#false} is VALID [2022-02-21 04:24:16,532 INFO L290 TraceCheckUtils]: 45: Hoare triple {6947#false} assume !(0 != activate_threads_~tmp___1~0#1); {6947#false} is VALID [2022-02-21 04:24:16,532 INFO L290 TraceCheckUtils]: 46: Hoare triple {6947#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6947#false} is VALID [2022-02-21 04:24:16,532 INFO L290 TraceCheckUtils]: 47: Hoare triple {6947#false} assume !(1 == ~t3_pc~0); {6947#false} is VALID [2022-02-21 04:24:16,532 INFO L290 TraceCheckUtils]: 48: Hoare triple {6947#false} is_transmit3_triggered_~__retres1~3#1 := 0; {6947#false} is VALID [2022-02-21 04:24:16,532 INFO L290 TraceCheckUtils]: 49: Hoare triple {6947#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6947#false} is VALID [2022-02-21 04:24:16,533 INFO L290 TraceCheckUtils]: 50: Hoare triple {6947#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {6947#false} is VALID [2022-02-21 04:24:16,533 INFO L290 TraceCheckUtils]: 51: Hoare triple {6947#false} assume !(0 != activate_threads_~tmp___2~0#1); {6947#false} is VALID [2022-02-21 04:24:16,533 INFO L290 TraceCheckUtils]: 52: Hoare triple {6947#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6947#false} is VALID [2022-02-21 04:24:16,533 INFO L290 TraceCheckUtils]: 53: Hoare triple {6947#false} assume 1 == ~t4_pc~0; {6947#false} is VALID [2022-02-21 04:24:16,533 INFO L290 TraceCheckUtils]: 54: Hoare triple {6947#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {6947#false} is VALID [2022-02-21 04:24:16,533 INFO L290 TraceCheckUtils]: 55: Hoare triple {6947#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6947#false} is VALID [2022-02-21 04:24:16,533 INFO L290 TraceCheckUtils]: 56: Hoare triple {6947#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {6947#false} is VALID [2022-02-21 04:24:16,533 INFO L290 TraceCheckUtils]: 57: Hoare triple {6947#false} assume !(0 != activate_threads_~tmp___3~0#1); {6947#false} is VALID [2022-02-21 04:24:16,534 INFO L290 TraceCheckUtils]: 58: Hoare triple {6947#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6947#false} is VALID [2022-02-21 04:24:16,534 INFO L290 TraceCheckUtils]: 59: Hoare triple {6947#false} assume !(1 == ~t5_pc~0); {6947#false} is VALID [2022-02-21 04:24:16,534 INFO L290 TraceCheckUtils]: 60: Hoare triple {6947#false} is_transmit5_triggered_~__retres1~5#1 := 0; {6947#false} is VALID [2022-02-21 04:24:16,534 INFO L290 TraceCheckUtils]: 61: Hoare triple {6947#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6947#false} is VALID [2022-02-21 04:24:16,534 INFO L290 TraceCheckUtils]: 62: Hoare triple {6947#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {6947#false} is VALID [2022-02-21 04:24:16,534 INFO L290 TraceCheckUtils]: 63: Hoare triple {6947#false} assume !(0 != activate_threads_~tmp___4~0#1); {6947#false} is VALID [2022-02-21 04:24:16,534 INFO L290 TraceCheckUtils]: 64: Hoare triple {6947#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {6947#false} is VALID [2022-02-21 04:24:16,535 INFO L290 TraceCheckUtils]: 65: Hoare triple {6947#false} assume 1 == ~t6_pc~0; {6947#false} is VALID [2022-02-21 04:24:16,535 INFO L290 TraceCheckUtils]: 66: Hoare triple {6947#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {6947#false} is VALID [2022-02-21 04:24:16,535 INFO L290 TraceCheckUtils]: 67: Hoare triple {6947#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {6947#false} is VALID [2022-02-21 04:24:16,535 INFO L290 TraceCheckUtils]: 68: Hoare triple {6947#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {6947#false} is VALID [2022-02-21 04:24:16,535 INFO L290 TraceCheckUtils]: 69: Hoare triple {6947#false} assume !(0 != activate_threads_~tmp___5~0#1); {6947#false} is VALID [2022-02-21 04:24:16,535 INFO L290 TraceCheckUtils]: 70: Hoare triple {6947#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {6947#false} is VALID [2022-02-21 04:24:16,535 INFO L290 TraceCheckUtils]: 71: Hoare triple {6947#false} assume 1 == ~t7_pc~0; {6947#false} is VALID [2022-02-21 04:24:16,535 INFO L290 TraceCheckUtils]: 72: Hoare triple {6947#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {6947#false} is VALID [2022-02-21 04:24:16,536 INFO L290 TraceCheckUtils]: 73: Hoare triple {6947#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {6947#false} is VALID [2022-02-21 04:24:16,536 INFO L290 TraceCheckUtils]: 74: Hoare triple {6947#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {6947#false} is VALID [2022-02-21 04:24:16,536 INFO L290 TraceCheckUtils]: 75: Hoare triple {6947#false} assume !(0 != activate_threads_~tmp___6~0#1); {6947#false} is VALID [2022-02-21 04:24:16,536 INFO L290 TraceCheckUtils]: 76: Hoare triple {6947#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6947#false} is VALID [2022-02-21 04:24:16,536 INFO L290 TraceCheckUtils]: 77: Hoare triple {6947#false} assume !(1 == ~M_E~0); {6947#false} is VALID [2022-02-21 04:24:16,536 INFO L290 TraceCheckUtils]: 78: Hoare triple {6947#false} assume !(1 == ~T1_E~0); {6947#false} is VALID [2022-02-21 04:24:16,536 INFO L290 TraceCheckUtils]: 79: Hoare triple {6947#false} assume !(1 == ~T2_E~0); {6947#false} is VALID [2022-02-21 04:24:16,536 INFO L290 TraceCheckUtils]: 80: Hoare triple {6947#false} assume !(1 == ~T3_E~0); {6947#false} is VALID [2022-02-21 04:24:16,537 INFO L290 TraceCheckUtils]: 81: Hoare triple {6947#false} assume !(1 == ~T4_E~0); {6947#false} is VALID [2022-02-21 04:24:16,537 INFO L290 TraceCheckUtils]: 82: Hoare triple {6947#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {6947#false} is VALID [2022-02-21 04:24:16,537 INFO L290 TraceCheckUtils]: 83: Hoare triple {6947#false} assume !(1 == ~T6_E~0); {6947#false} is VALID [2022-02-21 04:24:16,537 INFO L290 TraceCheckUtils]: 84: Hoare triple {6947#false} assume !(1 == ~T7_E~0); {6947#false} is VALID [2022-02-21 04:24:16,537 INFO L290 TraceCheckUtils]: 85: Hoare triple {6947#false} assume !(1 == ~E_1~0); {6947#false} is VALID [2022-02-21 04:24:16,537 INFO L290 TraceCheckUtils]: 86: Hoare triple {6947#false} assume !(1 == ~E_2~0); {6947#false} is VALID [2022-02-21 04:24:16,537 INFO L290 TraceCheckUtils]: 87: Hoare triple {6947#false} assume !(1 == ~E_3~0); {6947#false} is VALID [2022-02-21 04:24:16,537 INFO L290 TraceCheckUtils]: 88: Hoare triple {6947#false} assume !(1 == ~E_4~0); {6947#false} is VALID [2022-02-21 04:24:16,538 INFO L290 TraceCheckUtils]: 89: Hoare triple {6947#false} assume !(1 == ~E_5~0); {6947#false} is VALID [2022-02-21 04:24:16,538 INFO L290 TraceCheckUtils]: 90: Hoare triple {6947#false} assume 1 == ~E_6~0;~E_6~0 := 2; {6947#false} is VALID [2022-02-21 04:24:16,538 INFO L290 TraceCheckUtils]: 91: Hoare triple {6947#false} assume !(1 == ~E_7~0); {6947#false} is VALID [2022-02-21 04:24:16,538 INFO L290 TraceCheckUtils]: 92: Hoare triple {6947#false} assume { :end_inline_reset_delta_events } true; {6947#false} is VALID [2022-02-21 04:24:16,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:16,539 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:16,539 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1888198674] [2022-02-21 04:24:16,539 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1888198674] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:16,539 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:16,539 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:16,539 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221839310] [2022-02-21 04:24:16,539 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:16,540 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:16,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:16,540 INFO L85 PathProgramCache]: Analyzing trace with hash 1561027463, now seen corresponding path program 1 times [2022-02-21 04:24:16,540 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:16,540 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141622742] [2022-02-21 04:24:16,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:16,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:16,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:16,602 INFO L290 TraceCheckUtils]: 0: Hoare triple {6949#true} assume !false; {6949#true} is VALID [2022-02-21 04:24:16,603 INFO L290 TraceCheckUtils]: 1: Hoare triple {6949#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {6949#true} is VALID [2022-02-21 04:24:16,606 INFO L290 TraceCheckUtils]: 2: Hoare triple {6949#true} assume !false; {6949#true} is VALID [2022-02-21 04:24:16,607 INFO L290 TraceCheckUtils]: 3: Hoare triple {6949#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {6949#true} is VALID [2022-02-21 04:24:16,607 INFO L290 TraceCheckUtils]: 4: Hoare triple {6949#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {6949#true} is VALID [2022-02-21 04:24:16,607 INFO L290 TraceCheckUtils]: 5: Hoare triple {6949#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {6949#true} is VALID [2022-02-21 04:24:16,607 INFO L290 TraceCheckUtils]: 6: Hoare triple {6949#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {6949#true} is VALID [2022-02-21 04:24:16,607 INFO L290 TraceCheckUtils]: 7: Hoare triple {6949#true} assume !(0 != eval_~tmp~0#1); {6949#true} is VALID [2022-02-21 04:24:16,607 INFO L290 TraceCheckUtils]: 8: Hoare triple {6949#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {6949#true} is VALID [2022-02-21 04:24:16,607 INFO L290 TraceCheckUtils]: 9: Hoare triple {6949#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {6949#true} is VALID [2022-02-21 04:24:16,608 INFO L290 TraceCheckUtils]: 10: Hoare triple {6949#true} assume 0 == ~M_E~0;~M_E~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,608 INFO L290 TraceCheckUtils]: 11: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,608 INFO L290 TraceCheckUtils]: 12: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,609 INFO L290 TraceCheckUtils]: 13: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,609 INFO L290 TraceCheckUtils]: 14: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,609 INFO L290 TraceCheckUtils]: 15: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,610 INFO L290 TraceCheckUtils]: 16: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,610 INFO L290 TraceCheckUtils]: 17: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,610 INFO L290 TraceCheckUtils]: 18: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,610 INFO L290 TraceCheckUtils]: 19: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,611 INFO L290 TraceCheckUtils]: 20: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,611 INFO L290 TraceCheckUtils]: 21: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,618 INFO L290 TraceCheckUtils]: 22: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,618 INFO L290 TraceCheckUtils]: 23: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,619 INFO L290 TraceCheckUtils]: 24: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,620 INFO L290 TraceCheckUtils]: 25: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,620 INFO L290 TraceCheckUtils]: 26: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,620 INFO L290 TraceCheckUtils]: 27: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,620 INFO L290 TraceCheckUtils]: 28: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,621 INFO L290 TraceCheckUtils]: 29: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,621 INFO L290 TraceCheckUtils]: 30: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,621 INFO L290 TraceCheckUtils]: 31: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,622 INFO L290 TraceCheckUtils]: 32: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,622 INFO L290 TraceCheckUtils]: 33: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,622 INFO L290 TraceCheckUtils]: 34: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,623 INFO L290 TraceCheckUtils]: 35: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,623 INFO L290 TraceCheckUtils]: 36: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,623 INFO L290 TraceCheckUtils]: 37: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,623 INFO L290 TraceCheckUtils]: 38: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,624 INFO L290 TraceCheckUtils]: 39: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,624 INFO L290 TraceCheckUtils]: 40: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,624 INFO L290 TraceCheckUtils]: 41: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,625 INFO L290 TraceCheckUtils]: 42: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,625 INFO L290 TraceCheckUtils]: 43: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,625 INFO L290 TraceCheckUtils]: 44: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,625 INFO L290 TraceCheckUtils]: 45: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,626 INFO L290 TraceCheckUtils]: 46: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,626 INFO L290 TraceCheckUtils]: 47: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,626 INFO L290 TraceCheckUtils]: 48: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,626 INFO L290 TraceCheckUtils]: 49: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,627 INFO L290 TraceCheckUtils]: 50: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,627 INFO L290 TraceCheckUtils]: 51: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,627 INFO L290 TraceCheckUtils]: 52: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,628 INFO L290 TraceCheckUtils]: 53: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,628 INFO L290 TraceCheckUtils]: 54: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,628 INFO L290 TraceCheckUtils]: 55: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,628 INFO L290 TraceCheckUtils]: 56: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,629 INFO L290 TraceCheckUtils]: 57: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,629 INFO L290 TraceCheckUtils]: 58: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,629 INFO L290 TraceCheckUtils]: 59: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,630 INFO L290 TraceCheckUtils]: 60: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,630 INFO L290 TraceCheckUtils]: 61: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,630 INFO L290 TraceCheckUtils]: 62: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,630 INFO L290 TraceCheckUtils]: 63: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,631 INFO L290 TraceCheckUtils]: 64: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,631 INFO L290 TraceCheckUtils]: 65: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,631 INFO L290 TraceCheckUtils]: 66: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,632 INFO L290 TraceCheckUtils]: 67: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,632 INFO L290 TraceCheckUtils]: 68: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,632 INFO L290 TraceCheckUtils]: 69: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,632 INFO L290 TraceCheckUtils]: 70: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,633 INFO L290 TraceCheckUtils]: 71: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,633 INFO L290 TraceCheckUtils]: 72: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,633 INFO L290 TraceCheckUtils]: 73: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6951#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:16,633 INFO L290 TraceCheckUtils]: 74: Hoare triple {6951#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {6950#false} is VALID [2022-02-21 04:24:16,634 INFO L290 TraceCheckUtils]: 75: Hoare triple {6950#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,634 INFO L290 TraceCheckUtils]: 76: Hoare triple {6950#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,634 INFO L290 TraceCheckUtils]: 77: Hoare triple {6950#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,634 INFO L290 TraceCheckUtils]: 78: Hoare triple {6950#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,634 INFO L290 TraceCheckUtils]: 79: Hoare triple {6950#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,634 INFO L290 TraceCheckUtils]: 80: Hoare triple {6950#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,634 INFO L290 TraceCheckUtils]: 81: Hoare triple {6950#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,634 INFO L290 TraceCheckUtils]: 82: Hoare triple {6950#false} assume !(1 == ~E_1~0); {6950#false} is VALID [2022-02-21 04:24:16,634 INFO L290 TraceCheckUtils]: 83: Hoare triple {6950#false} assume 1 == ~E_2~0;~E_2~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,635 INFO L290 TraceCheckUtils]: 84: Hoare triple {6950#false} assume 1 == ~E_3~0;~E_3~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,635 INFO L290 TraceCheckUtils]: 85: Hoare triple {6950#false} assume 1 == ~E_4~0;~E_4~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,635 INFO L290 TraceCheckUtils]: 86: Hoare triple {6950#false} assume 1 == ~E_5~0;~E_5~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,635 INFO L290 TraceCheckUtils]: 87: Hoare triple {6950#false} assume 1 == ~E_6~0;~E_6~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,635 INFO L290 TraceCheckUtils]: 88: Hoare triple {6950#false} assume 1 == ~E_7~0;~E_7~0 := 2; {6950#false} is VALID [2022-02-21 04:24:16,635 INFO L290 TraceCheckUtils]: 89: Hoare triple {6950#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {6950#false} is VALID [2022-02-21 04:24:16,635 INFO L290 TraceCheckUtils]: 90: Hoare triple {6950#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {6950#false} is VALID [2022-02-21 04:24:16,635 INFO L290 TraceCheckUtils]: 91: Hoare triple {6950#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {6950#false} is VALID [2022-02-21 04:24:16,635 INFO L290 TraceCheckUtils]: 92: Hoare triple {6950#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {6950#false} is VALID [2022-02-21 04:24:16,636 INFO L290 TraceCheckUtils]: 93: Hoare triple {6950#false} assume !(0 == start_simulation_~tmp~3#1); {6950#false} is VALID [2022-02-21 04:24:16,636 INFO L290 TraceCheckUtils]: 94: Hoare triple {6950#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {6950#false} is VALID [2022-02-21 04:24:16,636 INFO L290 TraceCheckUtils]: 95: Hoare triple {6950#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {6950#false} is VALID [2022-02-21 04:24:16,636 INFO L290 TraceCheckUtils]: 96: Hoare triple {6950#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {6950#false} is VALID [2022-02-21 04:24:16,636 INFO L290 TraceCheckUtils]: 97: Hoare triple {6950#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {6950#false} is VALID [2022-02-21 04:24:16,636 INFO L290 TraceCheckUtils]: 98: Hoare triple {6950#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {6950#false} is VALID [2022-02-21 04:24:16,636 INFO L290 TraceCheckUtils]: 99: Hoare triple {6950#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {6950#false} is VALID [2022-02-21 04:24:16,636 INFO L290 TraceCheckUtils]: 100: Hoare triple {6950#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {6950#false} is VALID [2022-02-21 04:24:16,637 INFO L290 TraceCheckUtils]: 101: Hoare triple {6950#false} assume !(0 != start_simulation_~tmp___0~1#1); {6950#false} is VALID [2022-02-21 04:24:16,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:16,637 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:16,637 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141622742] [2022-02-21 04:24:16,638 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2141622742] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:16,638 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:16,638 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:16,638 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [421271349] [2022-02-21 04:24:16,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:16,638 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:16,639 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:16,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:16,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:16,639 INFO L87 Difference]: Start difference. First operand 768 states and 1147 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,191 INFO L93 Difference]: Finished difference Result 768 states and 1146 transitions. [2022-02-21 04:24:17,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:17,192 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,249 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:17,250 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1146 transitions. [2022-02-21 04:24:17,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:17,284 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1146 transitions. [2022-02-21 04:24:17,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-02-21 04:24:17,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-02-21 04:24:17,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1146 transitions. [2022-02-21 04:24:17,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:17,285 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1146 transitions. [2022-02-21 04:24:17,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1146 transitions. [2022-02-21 04:24:17,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-02-21 04:24:17,292 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:17,293 INFO L82 GeneralOperation]: Start isEquivalent. First operand 768 states and 1146 transitions. Second operand has 768 states, 768 states have (on average 1.4921875) internal successors, (1146), 767 states have internal predecessors, (1146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,294 INFO L74 IsIncluded]: Start isIncluded. First operand 768 states and 1146 transitions. Second operand has 768 states, 768 states have (on average 1.4921875) internal successors, (1146), 767 states have internal predecessors, (1146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,295 INFO L87 Difference]: Start difference. First operand 768 states and 1146 transitions. Second operand has 768 states, 768 states have (on average 1.4921875) internal successors, (1146), 767 states have internal predecessors, (1146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,311 INFO L93 Difference]: Finished difference Result 768 states and 1146 transitions. [2022-02-21 04:24:17,311 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1146 transitions. [2022-02-21 04:24:17,311 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:17,312 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:17,313 INFO L74 IsIncluded]: Start isIncluded. First operand has 768 states, 768 states have (on average 1.4921875) internal successors, (1146), 767 states have internal predecessors, (1146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1146 transitions. [2022-02-21 04:24:17,314 INFO L87 Difference]: Start difference. First operand has 768 states, 768 states have (on average 1.4921875) internal successors, (1146), 767 states have internal predecessors, (1146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1146 transitions. [2022-02-21 04:24:17,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,330 INFO L93 Difference]: Finished difference Result 768 states and 1146 transitions. [2022-02-21 04:24:17,330 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1146 transitions. [2022-02-21 04:24:17,331 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:17,331 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:17,331 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:17,331 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:17,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4921875) internal successors, (1146), 767 states have internal predecessors, (1146), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1146 transitions. [2022-02-21 04:24:17,348 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1146 transitions. [2022-02-21 04:24:17,348 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1146 transitions. [2022-02-21 04:24:17,348 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:17,348 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1146 transitions. [2022-02-21 04:24:17,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:17,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:17,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:17,356 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,356 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,356 INFO L791 eck$LassoCheckResult]: Stem: 8487#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8466#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8467#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7927#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7928#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 8344#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8345#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8313#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8236#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8237#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8226#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8227#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8186#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8187#L754 assume !(0 == ~M_E~0); 8445#L754-2 assume !(0 == ~T1_E~0); 8129#L759-1 assume !(0 == ~T2_E~0); 8130#L764-1 assume !(0 == ~T3_E~0); 8474#L769-1 assume !(0 == ~T4_E~0); 8475#L774-1 assume !(0 == ~T5_E~0); 8375#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8160#L784-1 assume !(0 == ~T7_E~0); 8161#L789-1 assume !(0 == ~E_1~0); 7840#L794-1 assume !(0 == ~E_2~0); 7841#L799-1 assume !(0 == ~E_3~0); 8476#L804-1 assume !(0 == ~E_4~0); 8477#L809-1 assume !(0 == ~E_5~0); 8240#L814-1 assume !(0 == ~E_6~0); 7756#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 7757#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8222#L361 assume 1 == ~m_pc~0; 8223#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8264#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8045#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8046#L930 assume !(0 != activate_threads_~tmp~1#1); 8370#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8216#L380 assume !(1 == ~t1_pc~0); 7890#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7889#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8395#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8471#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7966#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7891#L399 assume 1 == ~t2_pc~0; 7892#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8098#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8405#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8284#L946 assume !(0 != activate_threads_~tmp___1~0#1); 7796#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7764#L418 assume !(1 == ~t3_pc~0); 7725#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7726#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8244#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8452#L954 assume !(0 != activate_threads_~tmp___2~0#1); 8482#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8447#L437 assume 1 == ~t4_pc~0; 8448#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8067#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7894#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7895#L962 assume !(0 != activate_threads_~tmp___3~0#1); 8323#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8022#L456 assume !(1 == ~t5_pc~0); 8023#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8126#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8426#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7786#L970 assume !(0 != activate_threads_~tmp___4~0#1); 7787#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7910#L475 assume 1 == ~t6_pc~0; 7911#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7986#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7987#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7746#L978 assume !(0 != activate_threads_~tmp___5~0#1); 7747#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8229#L494 assume 1 == ~t7_pc~0; 8230#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8270#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8422#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8423#L986 assume !(0 != activate_threads_~tmp___6~0#1); 8485#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8424#L837 assume !(1 == ~M_E~0); 8287#L837-2 assume !(1 == ~T1_E~0); 7873#L842-1 assume !(1 == ~T2_E~0); 7874#L847-1 assume !(1 == ~T3_E~0); 8340#L852-1 assume !(1 == ~T4_E~0); 8417#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8296#L862-1 assume !(1 == ~T6_E~0); 8297#L867-1 assume !(1 == ~T7_E~0); 8306#L872-1 assume !(1 == ~E_1~0); 8372#L877-1 assume !(1 == ~E_2~0); 8302#L882-1 assume !(1 == ~E_3~0); 8303#L887-1 assume !(1 == ~E_4~0); 7933#L892-1 assume !(1 == ~E_5~0); 7934#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8320#L902-1 assume !(1 == ~E_7~0); 8014#L907-1 assume { :end_inline_reset_delta_events } true; 8015#L1148-2 [2022-02-21 04:24:17,356 INFO L793 eck$LassoCheckResult]: Loop: 8015#L1148-2 assume !false; 7758#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7759#L729 assume !false; 8157#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8153#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8104#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8173#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8211#L626 assume !(0 != eval_~tmp~0#1); 8212#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8342#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8246#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7799#L754-5 assume !(0 == ~T1_E~0); 7800#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8182#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8350#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8351#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8114#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7775#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7776#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7760#L794-3 assume !(0 == ~E_2~0); 7761#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7852#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8252#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7848#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7849#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8048#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8049#L361-24 assume 1 == ~m_pc~0; 8085#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8086#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7768#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7769#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8245#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8309#L380-24 assume 1 == ~t1_pc~0; 8310#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7936#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8368#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8241#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7896#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7897#L399-24 assume 1 == ~t2_pc~0; 8109#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8159#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7937#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7938#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8233#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8234#L418-24 assume !(1 == ~t3_pc~0); 7844#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7845#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8235#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8113#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7788#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7789#L437-24 assume 1 == ~t4_pc~0; 8060#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8061#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7939#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7940#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8088#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8397#L456-24 assume 1 == ~t5_pc~0; 8398#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8458#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8151#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8152#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8291#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8425#L475-24 assume !(1 == ~t6_pc~0); 7792#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7791#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8434#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8435#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 7733#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7734#L494-24 assume 1 == ~t7_pc~0; 8391#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8281#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8178#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8179#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8058#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8059#L837-3 assume !(1 == ~M_E~0); 8141#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8421#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8337#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7777#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7778#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8462#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8454#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8388#L872-3 assume !(1 == ~E_1~0); 8389#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8457#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8472#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8144#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8137#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8138#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8314#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8307#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7763#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8483#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8443#L1167 assume !(0 == start_simulation_~tmp~3#1); 8338#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8365#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8170#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8404#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8437#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8352#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7739#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7740#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 8015#L1148-2 [2022-02-21 04:24:17,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,357 INFO L85 PathProgramCache]: Analyzing trace with hash -1151321427, now seen corresponding path program 1 times [2022-02-21 04:24:17,358 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,358 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978565096] [2022-02-21 04:24:17,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,399 INFO L290 TraceCheckUtils]: 0: Hoare triple {10027#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {10027#true} is VALID [2022-02-21 04:24:17,400 INFO L290 TraceCheckUtils]: 1: Hoare triple {10027#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {10029#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:17,400 INFO L290 TraceCheckUtils]: 2: Hoare triple {10029#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10029#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:17,400 INFO L290 TraceCheckUtils]: 3: Hoare triple {10029#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10029#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:17,401 INFO L290 TraceCheckUtils]: 4: Hoare triple {10029#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {10029#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:17,401 INFO L290 TraceCheckUtils]: 5: Hoare triple {10029#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10029#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:17,401 INFO L290 TraceCheckUtils]: 6: Hoare triple {10029#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {10029#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:17,401 INFO L290 TraceCheckUtils]: 7: Hoare triple {10029#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {10029#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:17,402 INFO L290 TraceCheckUtils]: 8: Hoare triple {10029#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {10028#false} is VALID [2022-02-21 04:24:17,402 INFO L290 TraceCheckUtils]: 9: Hoare triple {10028#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {10028#false} is VALID [2022-02-21 04:24:17,402 INFO L290 TraceCheckUtils]: 10: Hoare triple {10028#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {10028#false} is VALID [2022-02-21 04:24:17,402 INFO L290 TraceCheckUtils]: 11: Hoare triple {10028#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {10028#false} is VALID [2022-02-21 04:24:17,402 INFO L290 TraceCheckUtils]: 12: Hoare triple {10028#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10028#false} is VALID [2022-02-21 04:24:17,402 INFO L290 TraceCheckUtils]: 13: Hoare triple {10028#false} assume !(0 == ~M_E~0); {10028#false} is VALID [2022-02-21 04:24:17,402 INFO L290 TraceCheckUtils]: 14: Hoare triple {10028#false} assume !(0 == ~T1_E~0); {10028#false} is VALID [2022-02-21 04:24:17,403 INFO L290 TraceCheckUtils]: 15: Hoare triple {10028#false} assume !(0 == ~T2_E~0); {10028#false} is VALID [2022-02-21 04:24:17,403 INFO L290 TraceCheckUtils]: 16: Hoare triple {10028#false} assume !(0 == ~T3_E~0); {10028#false} is VALID [2022-02-21 04:24:17,403 INFO L290 TraceCheckUtils]: 17: Hoare triple {10028#false} assume !(0 == ~T4_E~0); {10028#false} is VALID [2022-02-21 04:24:17,403 INFO L290 TraceCheckUtils]: 18: Hoare triple {10028#false} assume !(0 == ~T5_E~0); {10028#false} is VALID [2022-02-21 04:24:17,403 INFO L290 TraceCheckUtils]: 19: Hoare triple {10028#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10028#false} is VALID [2022-02-21 04:24:17,403 INFO L290 TraceCheckUtils]: 20: Hoare triple {10028#false} assume !(0 == ~T7_E~0); {10028#false} is VALID [2022-02-21 04:24:17,403 INFO L290 TraceCheckUtils]: 21: Hoare triple {10028#false} assume !(0 == ~E_1~0); {10028#false} is VALID [2022-02-21 04:24:17,403 INFO L290 TraceCheckUtils]: 22: Hoare triple {10028#false} assume !(0 == ~E_2~0); {10028#false} is VALID [2022-02-21 04:24:17,403 INFO L290 TraceCheckUtils]: 23: Hoare triple {10028#false} assume !(0 == ~E_3~0); {10028#false} is VALID [2022-02-21 04:24:17,403 INFO L290 TraceCheckUtils]: 24: Hoare triple {10028#false} assume !(0 == ~E_4~0); {10028#false} is VALID [2022-02-21 04:24:17,404 INFO L290 TraceCheckUtils]: 25: Hoare triple {10028#false} assume !(0 == ~E_5~0); {10028#false} is VALID [2022-02-21 04:24:17,404 INFO L290 TraceCheckUtils]: 26: Hoare triple {10028#false} assume !(0 == ~E_6~0); {10028#false} is VALID [2022-02-21 04:24:17,404 INFO L290 TraceCheckUtils]: 27: Hoare triple {10028#false} assume 0 == ~E_7~0;~E_7~0 := 1; {10028#false} is VALID [2022-02-21 04:24:17,404 INFO L290 TraceCheckUtils]: 28: Hoare triple {10028#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10028#false} is VALID [2022-02-21 04:24:17,404 INFO L290 TraceCheckUtils]: 29: Hoare triple {10028#false} assume 1 == ~m_pc~0; {10028#false} is VALID [2022-02-21 04:24:17,404 INFO L290 TraceCheckUtils]: 30: Hoare triple {10028#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {10028#false} is VALID [2022-02-21 04:24:17,404 INFO L290 TraceCheckUtils]: 31: Hoare triple {10028#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10028#false} is VALID [2022-02-21 04:24:17,404 INFO L290 TraceCheckUtils]: 32: Hoare triple {10028#false} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {10028#false} is VALID [2022-02-21 04:24:17,404 INFO L290 TraceCheckUtils]: 33: Hoare triple {10028#false} assume !(0 != activate_threads_~tmp~1#1); {10028#false} is VALID [2022-02-21 04:24:17,405 INFO L290 TraceCheckUtils]: 34: Hoare triple {10028#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10028#false} is VALID [2022-02-21 04:24:17,405 INFO L290 TraceCheckUtils]: 35: Hoare triple {10028#false} assume !(1 == ~t1_pc~0); {10028#false} is VALID [2022-02-21 04:24:17,405 INFO L290 TraceCheckUtils]: 36: Hoare triple {10028#false} is_transmit1_triggered_~__retres1~1#1 := 0; {10028#false} is VALID [2022-02-21 04:24:17,405 INFO L290 TraceCheckUtils]: 37: Hoare triple {10028#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10028#false} is VALID [2022-02-21 04:24:17,405 INFO L290 TraceCheckUtils]: 38: Hoare triple {10028#false} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {10028#false} is VALID [2022-02-21 04:24:17,405 INFO L290 TraceCheckUtils]: 39: Hoare triple {10028#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10028#false} is VALID [2022-02-21 04:24:17,405 INFO L290 TraceCheckUtils]: 40: Hoare triple {10028#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10028#false} is VALID [2022-02-21 04:24:17,405 INFO L290 TraceCheckUtils]: 41: Hoare triple {10028#false} assume 1 == ~t2_pc~0; {10028#false} is VALID [2022-02-21 04:24:17,405 INFO L290 TraceCheckUtils]: 42: Hoare triple {10028#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10028#false} is VALID [2022-02-21 04:24:17,406 INFO L290 TraceCheckUtils]: 43: Hoare triple {10028#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10028#false} is VALID [2022-02-21 04:24:17,406 INFO L290 TraceCheckUtils]: 44: Hoare triple {10028#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {10028#false} is VALID [2022-02-21 04:24:17,406 INFO L290 TraceCheckUtils]: 45: Hoare triple {10028#false} assume !(0 != activate_threads_~tmp___1~0#1); {10028#false} is VALID [2022-02-21 04:24:17,406 INFO L290 TraceCheckUtils]: 46: Hoare triple {10028#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10028#false} is VALID [2022-02-21 04:24:17,410 INFO L290 TraceCheckUtils]: 47: Hoare triple {10028#false} assume !(1 == ~t3_pc~0); {10028#false} is VALID [2022-02-21 04:24:17,410 INFO L290 TraceCheckUtils]: 48: Hoare triple {10028#false} is_transmit3_triggered_~__retres1~3#1 := 0; {10028#false} is VALID [2022-02-21 04:24:17,410 INFO L290 TraceCheckUtils]: 49: Hoare triple {10028#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10028#false} is VALID [2022-02-21 04:24:17,410 INFO L290 TraceCheckUtils]: 50: Hoare triple {10028#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10028#false} is VALID [2022-02-21 04:24:17,410 INFO L290 TraceCheckUtils]: 51: Hoare triple {10028#false} assume !(0 != activate_threads_~tmp___2~0#1); {10028#false} is VALID [2022-02-21 04:24:17,410 INFO L290 TraceCheckUtils]: 52: Hoare triple {10028#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10028#false} is VALID [2022-02-21 04:24:17,410 INFO L290 TraceCheckUtils]: 53: Hoare triple {10028#false} assume 1 == ~t4_pc~0; {10028#false} is VALID [2022-02-21 04:24:17,411 INFO L290 TraceCheckUtils]: 54: Hoare triple {10028#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10028#false} is VALID [2022-02-21 04:24:17,411 INFO L290 TraceCheckUtils]: 55: Hoare triple {10028#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10028#false} is VALID [2022-02-21 04:24:17,411 INFO L290 TraceCheckUtils]: 56: Hoare triple {10028#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {10028#false} is VALID [2022-02-21 04:24:17,411 INFO L290 TraceCheckUtils]: 57: Hoare triple {10028#false} assume !(0 != activate_threads_~tmp___3~0#1); {10028#false} is VALID [2022-02-21 04:24:17,411 INFO L290 TraceCheckUtils]: 58: Hoare triple {10028#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10028#false} is VALID [2022-02-21 04:24:17,411 INFO L290 TraceCheckUtils]: 59: Hoare triple {10028#false} assume !(1 == ~t5_pc~0); {10028#false} is VALID [2022-02-21 04:24:17,411 INFO L290 TraceCheckUtils]: 60: Hoare triple {10028#false} is_transmit5_triggered_~__retres1~5#1 := 0; {10028#false} is VALID [2022-02-21 04:24:17,411 INFO L290 TraceCheckUtils]: 61: Hoare triple {10028#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10028#false} is VALID [2022-02-21 04:24:17,411 INFO L290 TraceCheckUtils]: 62: Hoare triple {10028#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {10028#false} is VALID [2022-02-21 04:24:17,411 INFO L290 TraceCheckUtils]: 63: Hoare triple {10028#false} assume !(0 != activate_threads_~tmp___4~0#1); {10028#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 64: Hoare triple {10028#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10028#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 65: Hoare triple {10028#false} assume 1 == ~t6_pc~0; {10028#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 66: Hoare triple {10028#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10028#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 67: Hoare triple {10028#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10028#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 68: Hoare triple {10028#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {10028#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 69: Hoare triple {10028#false} assume !(0 != activate_threads_~tmp___5~0#1); {10028#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 70: Hoare triple {10028#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10028#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 71: Hoare triple {10028#false} assume 1 == ~t7_pc~0; {10028#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 72: Hoare triple {10028#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {10028#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 73: Hoare triple {10028#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10028#false} is VALID [2022-02-21 04:24:17,413 INFO L290 TraceCheckUtils]: 74: Hoare triple {10028#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10028#false} is VALID [2022-02-21 04:24:17,413 INFO L290 TraceCheckUtils]: 75: Hoare triple {10028#false} assume !(0 != activate_threads_~tmp___6~0#1); {10028#false} is VALID [2022-02-21 04:24:17,413 INFO L290 TraceCheckUtils]: 76: Hoare triple {10028#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10028#false} is VALID [2022-02-21 04:24:17,413 INFO L290 TraceCheckUtils]: 77: Hoare triple {10028#false} assume !(1 == ~M_E~0); {10028#false} is VALID [2022-02-21 04:24:17,413 INFO L290 TraceCheckUtils]: 78: Hoare triple {10028#false} assume !(1 == ~T1_E~0); {10028#false} is VALID [2022-02-21 04:24:17,413 INFO L290 TraceCheckUtils]: 79: Hoare triple {10028#false} assume !(1 == ~T2_E~0); {10028#false} is VALID [2022-02-21 04:24:17,413 INFO L290 TraceCheckUtils]: 80: Hoare triple {10028#false} assume !(1 == ~T3_E~0); {10028#false} is VALID [2022-02-21 04:24:17,413 INFO L290 TraceCheckUtils]: 81: Hoare triple {10028#false} assume !(1 == ~T4_E~0); {10028#false} is VALID [2022-02-21 04:24:17,413 INFO L290 TraceCheckUtils]: 82: Hoare triple {10028#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {10028#false} is VALID [2022-02-21 04:24:17,413 INFO L290 TraceCheckUtils]: 83: Hoare triple {10028#false} assume !(1 == ~T6_E~0); {10028#false} is VALID [2022-02-21 04:24:17,414 INFO L290 TraceCheckUtils]: 84: Hoare triple {10028#false} assume !(1 == ~T7_E~0); {10028#false} is VALID [2022-02-21 04:24:17,414 INFO L290 TraceCheckUtils]: 85: Hoare triple {10028#false} assume !(1 == ~E_1~0); {10028#false} is VALID [2022-02-21 04:24:17,414 INFO L290 TraceCheckUtils]: 86: Hoare triple {10028#false} assume !(1 == ~E_2~0); {10028#false} is VALID [2022-02-21 04:24:17,414 INFO L290 TraceCheckUtils]: 87: Hoare triple {10028#false} assume !(1 == ~E_3~0); {10028#false} is VALID [2022-02-21 04:24:17,414 INFO L290 TraceCheckUtils]: 88: Hoare triple {10028#false} assume !(1 == ~E_4~0); {10028#false} is VALID [2022-02-21 04:24:17,414 INFO L290 TraceCheckUtils]: 89: Hoare triple {10028#false} assume !(1 == ~E_5~0); {10028#false} is VALID [2022-02-21 04:24:17,414 INFO L290 TraceCheckUtils]: 90: Hoare triple {10028#false} assume 1 == ~E_6~0;~E_6~0 := 2; {10028#false} is VALID [2022-02-21 04:24:17,414 INFO L290 TraceCheckUtils]: 91: Hoare triple {10028#false} assume !(1 == ~E_7~0); {10028#false} is VALID [2022-02-21 04:24:17,414 INFO L290 TraceCheckUtils]: 92: Hoare triple {10028#false} assume { :end_inline_reset_delta_events } true; {10028#false} is VALID [2022-02-21 04:24:17,415 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,415 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,416 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1978565096] [2022-02-21 04:24:17,416 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1978565096] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,416 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,416 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:17,417 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1973951362] [2022-02-21 04:24:17,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,418 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:17,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1541265095, now seen corresponding path program 1 times [2022-02-21 04:24:17,419 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,421 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760754126] [2022-02-21 04:24:17,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,467 INFO L290 TraceCheckUtils]: 0: Hoare triple {10030#true} assume !false; {10030#true} is VALID [2022-02-21 04:24:17,468 INFO L290 TraceCheckUtils]: 1: Hoare triple {10030#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10030#true} is VALID [2022-02-21 04:24:17,468 INFO L290 TraceCheckUtils]: 2: Hoare triple {10030#true} assume !false; {10030#true} is VALID [2022-02-21 04:24:17,468 INFO L290 TraceCheckUtils]: 3: Hoare triple {10030#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {10030#true} is VALID [2022-02-21 04:24:17,468 INFO L290 TraceCheckUtils]: 4: Hoare triple {10030#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {10030#true} is VALID [2022-02-21 04:24:17,468 INFO L290 TraceCheckUtils]: 5: Hoare triple {10030#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {10030#true} is VALID [2022-02-21 04:24:17,468 INFO L290 TraceCheckUtils]: 6: Hoare triple {10030#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {10030#true} is VALID [2022-02-21 04:24:17,468 INFO L290 TraceCheckUtils]: 7: Hoare triple {10030#true} assume !(0 != eval_~tmp~0#1); {10030#true} is VALID [2022-02-21 04:24:17,468 INFO L290 TraceCheckUtils]: 8: Hoare triple {10030#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10030#true} is VALID [2022-02-21 04:24:17,469 INFO L290 TraceCheckUtils]: 9: Hoare triple {10030#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10030#true} is VALID [2022-02-21 04:24:17,469 INFO L290 TraceCheckUtils]: 10: Hoare triple {10030#true} assume 0 == ~M_E~0;~M_E~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,469 INFO L290 TraceCheckUtils]: 11: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,469 INFO L290 TraceCheckUtils]: 12: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,470 INFO L290 TraceCheckUtils]: 13: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,470 INFO L290 TraceCheckUtils]: 14: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,470 INFO L290 TraceCheckUtils]: 15: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,471 INFO L290 TraceCheckUtils]: 16: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,471 INFO L290 TraceCheckUtils]: 17: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,471 INFO L290 TraceCheckUtils]: 18: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,471 INFO L290 TraceCheckUtils]: 19: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,472 INFO L290 TraceCheckUtils]: 20: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,472 INFO L290 TraceCheckUtils]: 21: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,472 INFO L290 TraceCheckUtils]: 22: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,472 INFO L290 TraceCheckUtils]: 23: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,473 INFO L290 TraceCheckUtils]: 24: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,473 INFO L290 TraceCheckUtils]: 25: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,473 INFO L290 TraceCheckUtils]: 26: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,473 INFO L290 TraceCheckUtils]: 27: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,474 INFO L290 TraceCheckUtils]: 28: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,474 INFO L290 TraceCheckUtils]: 29: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,474 INFO L290 TraceCheckUtils]: 30: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,475 INFO L290 TraceCheckUtils]: 31: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,475 INFO L290 TraceCheckUtils]: 32: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,475 INFO L290 TraceCheckUtils]: 33: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,476 INFO L290 TraceCheckUtils]: 34: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,476 INFO L290 TraceCheckUtils]: 35: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,476 INFO L290 TraceCheckUtils]: 36: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,476 INFO L290 TraceCheckUtils]: 37: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,477 INFO L290 TraceCheckUtils]: 38: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,477 INFO L290 TraceCheckUtils]: 39: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,477 INFO L290 TraceCheckUtils]: 40: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,477 INFO L290 TraceCheckUtils]: 41: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,478 INFO L290 TraceCheckUtils]: 42: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,478 INFO L290 TraceCheckUtils]: 43: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,478 INFO L290 TraceCheckUtils]: 44: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,478 INFO L290 TraceCheckUtils]: 45: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,479 INFO L290 TraceCheckUtils]: 46: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,479 INFO L290 TraceCheckUtils]: 47: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,479 INFO L290 TraceCheckUtils]: 48: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,479 INFO L290 TraceCheckUtils]: 49: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,480 INFO L290 TraceCheckUtils]: 50: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,480 INFO L290 TraceCheckUtils]: 51: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,480 INFO L290 TraceCheckUtils]: 52: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,481 INFO L290 TraceCheckUtils]: 53: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,481 INFO L290 TraceCheckUtils]: 54: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,481 INFO L290 TraceCheckUtils]: 55: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,481 INFO L290 TraceCheckUtils]: 56: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,482 INFO L290 TraceCheckUtils]: 57: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,483 INFO L290 TraceCheckUtils]: 58: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,483 INFO L290 TraceCheckUtils]: 59: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,483 INFO L290 TraceCheckUtils]: 60: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,484 INFO L290 TraceCheckUtils]: 61: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,484 INFO L290 TraceCheckUtils]: 62: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,484 INFO L290 TraceCheckUtils]: 63: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,484 INFO L290 TraceCheckUtils]: 64: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,485 INFO L290 TraceCheckUtils]: 65: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,485 INFO L290 TraceCheckUtils]: 66: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,485 INFO L290 TraceCheckUtils]: 67: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,486 INFO L290 TraceCheckUtils]: 68: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,486 INFO L290 TraceCheckUtils]: 69: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,486 INFO L290 TraceCheckUtils]: 70: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,486 INFO L290 TraceCheckUtils]: 71: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,487 INFO L290 TraceCheckUtils]: 72: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,487 INFO L290 TraceCheckUtils]: 73: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10032#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:17,487 INFO L290 TraceCheckUtils]: 74: Hoare triple {10032#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {10031#false} is VALID [2022-02-21 04:24:17,487 INFO L290 TraceCheckUtils]: 75: Hoare triple {10031#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,487 INFO L290 TraceCheckUtils]: 76: Hoare triple {10031#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,488 INFO L290 TraceCheckUtils]: 77: Hoare triple {10031#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,488 INFO L290 TraceCheckUtils]: 78: Hoare triple {10031#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,488 INFO L290 TraceCheckUtils]: 79: Hoare triple {10031#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,488 INFO L290 TraceCheckUtils]: 80: Hoare triple {10031#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,488 INFO L290 TraceCheckUtils]: 81: Hoare triple {10031#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,488 INFO L290 TraceCheckUtils]: 82: Hoare triple {10031#false} assume !(1 == ~E_1~0); {10031#false} is VALID [2022-02-21 04:24:17,488 INFO L290 TraceCheckUtils]: 83: Hoare triple {10031#false} assume 1 == ~E_2~0;~E_2~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,488 INFO L290 TraceCheckUtils]: 84: Hoare triple {10031#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,488 INFO L290 TraceCheckUtils]: 85: Hoare triple {10031#false} assume 1 == ~E_4~0;~E_4~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,488 INFO L290 TraceCheckUtils]: 86: Hoare triple {10031#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,489 INFO L290 TraceCheckUtils]: 87: Hoare triple {10031#false} assume 1 == ~E_6~0;~E_6~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,489 INFO L290 TraceCheckUtils]: 88: Hoare triple {10031#false} assume 1 == ~E_7~0;~E_7~0 := 2; {10031#false} is VALID [2022-02-21 04:24:17,489 INFO L290 TraceCheckUtils]: 89: Hoare triple {10031#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {10031#false} is VALID [2022-02-21 04:24:17,489 INFO L290 TraceCheckUtils]: 90: Hoare triple {10031#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {10031#false} is VALID [2022-02-21 04:24:17,489 INFO L290 TraceCheckUtils]: 91: Hoare triple {10031#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {10031#false} is VALID [2022-02-21 04:24:17,489 INFO L290 TraceCheckUtils]: 92: Hoare triple {10031#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {10031#false} is VALID [2022-02-21 04:24:17,489 INFO L290 TraceCheckUtils]: 93: Hoare triple {10031#false} assume !(0 == start_simulation_~tmp~3#1); {10031#false} is VALID [2022-02-21 04:24:17,489 INFO L290 TraceCheckUtils]: 94: Hoare triple {10031#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {10031#false} is VALID [2022-02-21 04:24:17,489 INFO L290 TraceCheckUtils]: 95: Hoare triple {10031#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {10031#false} is VALID [2022-02-21 04:24:17,489 INFO L290 TraceCheckUtils]: 96: Hoare triple {10031#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {10031#false} is VALID [2022-02-21 04:24:17,490 INFO L290 TraceCheckUtils]: 97: Hoare triple {10031#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {10031#false} is VALID [2022-02-21 04:24:17,490 INFO L290 TraceCheckUtils]: 98: Hoare triple {10031#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {10031#false} is VALID [2022-02-21 04:24:17,490 INFO L290 TraceCheckUtils]: 99: Hoare triple {10031#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10031#false} is VALID [2022-02-21 04:24:17,490 INFO L290 TraceCheckUtils]: 100: Hoare triple {10031#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {10031#false} is VALID [2022-02-21 04:24:17,490 INFO L290 TraceCheckUtils]: 101: Hoare triple {10031#false} assume !(0 != start_simulation_~tmp___0~1#1); {10031#false} is VALID [2022-02-21 04:24:17,491 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,491 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,491 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760754126] [2022-02-21 04:24:17,491 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760754126] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,491 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,491 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:17,491 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382746350] [2022-02-21 04:24:17,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,492 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:17,492 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:17,492 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:17,492 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:17,493 INFO L87 Difference]: Start difference. First operand 768 states and 1146 transitions. cyclomatic complexity: 379 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,972 INFO L93 Difference]: Finished difference Result 768 states and 1145 transitions. [2022-02-21 04:24:17,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:17,972 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,036 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:18,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1145 transitions. [2022-02-21 04:24:18,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:18,069 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1145 transitions. [2022-02-21 04:24:18,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-02-21 04:24:18,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-02-21 04:24:18,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1145 transitions. [2022-02-21 04:24:18,071 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:18,071 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1145 transitions. [2022-02-21 04:24:18,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1145 transitions. [2022-02-21 04:24:18,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-02-21 04:24:18,077 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:18,079 INFO L82 GeneralOperation]: Start isEquivalent. First operand 768 states and 1145 transitions. Second operand has 768 states, 768 states have (on average 1.4908854166666667) internal successors, (1145), 767 states have internal predecessors, (1145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,080 INFO L74 IsIncluded]: Start isIncluded. First operand 768 states and 1145 transitions. Second operand has 768 states, 768 states have (on average 1.4908854166666667) internal successors, (1145), 767 states have internal predecessors, (1145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,081 INFO L87 Difference]: Start difference. First operand 768 states and 1145 transitions. Second operand has 768 states, 768 states have (on average 1.4908854166666667) internal successors, (1145), 767 states have internal predecessors, (1145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,096 INFO L93 Difference]: Finished difference Result 768 states and 1145 transitions. [2022-02-21 04:24:18,096 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1145 transitions. [2022-02-21 04:24:18,097 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:18,097 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:18,099 INFO L74 IsIncluded]: Start isIncluded. First operand has 768 states, 768 states have (on average 1.4908854166666667) internal successors, (1145), 767 states have internal predecessors, (1145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1145 transitions. [2022-02-21 04:24:18,100 INFO L87 Difference]: Start difference. First operand has 768 states, 768 states have (on average 1.4908854166666667) internal successors, (1145), 767 states have internal predecessors, (1145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1145 transitions. [2022-02-21 04:24:18,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,116 INFO L93 Difference]: Finished difference Result 768 states and 1145 transitions. [2022-02-21 04:24:18,116 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1145 transitions. [2022-02-21 04:24:18,117 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:18,117 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:18,118 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:18,118 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:18,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4908854166666667) internal successors, (1145), 767 states have internal predecessors, (1145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1145 transitions. [2022-02-21 04:24:18,135 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1145 transitions. [2022-02-21 04:24:18,135 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1145 transitions. [2022-02-21 04:24:18,135 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:18,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1145 transitions. [2022-02-21 04:24:18,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:18,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:18,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:18,138 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:18,138 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:18,138 INFO L791 eck$LassoCheckResult]: Stem: 11568#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11548#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11008#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11009#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 11425#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11426#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11394#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11317#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11318#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11307#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11308#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11267#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11268#L754 assume !(0 == ~M_E~0); 11526#L754-2 assume !(0 == ~T1_E~0); 11210#L759-1 assume !(0 == ~T2_E~0); 11211#L764-1 assume !(0 == ~T3_E~0); 11555#L769-1 assume !(0 == ~T4_E~0); 11556#L774-1 assume !(0 == ~T5_E~0); 11456#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11241#L784-1 assume !(0 == ~T7_E~0); 11242#L789-1 assume !(0 == ~E_1~0); 10921#L794-1 assume !(0 == ~E_2~0); 10922#L799-1 assume !(0 == ~E_3~0); 11557#L804-1 assume !(0 == ~E_4~0); 11558#L809-1 assume !(0 == ~E_5~0); 11321#L814-1 assume !(0 == ~E_6~0); 10839#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10840#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11303#L361 assume 1 == ~m_pc~0; 11304#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11345#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11126#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11127#L930 assume !(0 != activate_threads_~tmp~1#1); 11451#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11297#L380 assume !(1 == ~t1_pc~0); 10971#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10970#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11476#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11552#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11047#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10972#L399 assume 1 == ~t2_pc~0; 10973#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11179#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11486#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11365#L946 assume !(0 != activate_threads_~tmp___1~0#1); 10877#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10845#L418 assume !(1 == ~t3_pc~0); 10806#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10807#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11325#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11533#L954 assume !(0 != activate_threads_~tmp___2~0#1); 11563#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11528#L437 assume 1 == ~t4_pc~0; 11529#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11148#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10975#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10976#L962 assume !(0 != activate_threads_~tmp___3~0#1); 11404#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11103#L456 assume !(1 == ~t5_pc~0); 11104#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11207#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11507#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10867#L970 assume !(0 != activate_threads_~tmp___4~0#1); 10868#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10991#L475 assume 1 == ~t6_pc~0; 10992#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11067#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11068#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10827#L978 assume !(0 != activate_threads_~tmp___5~0#1); 10828#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11310#L494 assume 1 == ~t7_pc~0; 11311#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11351#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11503#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11504#L986 assume !(0 != activate_threads_~tmp___6~0#1); 11566#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11505#L837 assume !(1 == ~M_E~0); 11368#L837-2 assume !(1 == ~T1_E~0); 10954#L842-1 assume !(1 == ~T2_E~0); 10955#L847-1 assume !(1 == ~T3_E~0); 11421#L852-1 assume !(1 == ~T4_E~0); 11498#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11377#L862-1 assume !(1 == ~T6_E~0); 11378#L867-1 assume !(1 == ~T7_E~0); 11387#L872-1 assume !(1 == ~E_1~0); 11453#L877-1 assume !(1 == ~E_2~0); 11383#L882-1 assume !(1 == ~E_3~0); 11384#L887-1 assume !(1 == ~E_4~0); 11014#L892-1 assume !(1 == ~E_5~0); 11015#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11401#L902-1 assume !(1 == ~E_7~0); 11095#L907-1 assume { :end_inline_reset_delta_events } true; 11096#L1148-2 [2022-02-21 04:24:18,139 INFO L793 eck$LassoCheckResult]: Loop: 11096#L1148-2 assume !false; 10841#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10842#L729 assume !false; 11238#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11234#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11185#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11254#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11292#L626 assume !(0 != eval_~tmp~0#1); 11293#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11423#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11327#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10880#L754-5 assume !(0 == ~T1_E~0); 10881#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11263#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11431#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11432#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11195#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10856#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10857#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10837#L794-3 assume !(0 == ~E_2~0); 10838#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10933#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11333#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10929#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10930#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11129#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11130#L361-24 assume !(1 == ~m_pc~0); 11168#L361-26 is_master_triggered_~__retres1~0#1 := 0; 11167#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10849#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10850#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11326#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11390#L380-24 assume !(1 == ~t1_pc~0); 11016#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 11017#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11449#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11322#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10977#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10978#L399-24 assume 1 == ~t2_pc~0; 11190#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11240#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11018#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11019#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11314#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11315#L418-24 assume 1 == ~t3_pc~0; 11319#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10926#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11316#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11194#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10869#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10870#L437-24 assume 1 == ~t4_pc~0; 11141#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11142#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11020#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11021#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11169#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11478#L456-24 assume 1 == ~t5_pc~0; 11479#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11539#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11232#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11233#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11372#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11506#L475-24 assume 1 == ~t6_pc~0; 10871#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10872#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11515#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11516#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 10814#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10815#L494-24 assume 1 == ~t7_pc~0; 11472#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11362#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11259#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11260#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11139#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11140#L837-3 assume !(1 == ~M_E~0); 11222#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11502#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11418#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10858#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10859#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11543#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11535#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11469#L872-3 assume !(1 == ~E_1~0); 11470#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11538#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11553#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11225#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11218#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11219#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11395#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11388#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10844#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11564#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11524#L1167 assume !(0 == start_simulation_~tmp~3#1); 11419#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11446#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11251#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11485#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 11518#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11433#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10820#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 10821#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 11096#L1148-2 [2022-02-21 04:24:18,139 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:18,139 INFO L85 PathProgramCache]: Analyzing trace with hash 1267163051, now seen corresponding path program 1 times [2022-02-21 04:24:18,139 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:18,140 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330433425] [2022-02-21 04:24:18,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:18,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:18,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:18,157 INFO L290 TraceCheckUtils]: 0: Hoare triple {13108#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {13108#true} is VALID [2022-02-21 04:24:18,157 INFO L290 TraceCheckUtils]: 1: Hoare triple {13108#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {13110#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:18,158 INFO L290 TraceCheckUtils]: 2: Hoare triple {13110#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {13110#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:18,158 INFO L290 TraceCheckUtils]: 3: Hoare triple {13110#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {13110#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:18,158 INFO L290 TraceCheckUtils]: 4: Hoare triple {13110#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {13110#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:18,158 INFO L290 TraceCheckUtils]: 5: Hoare triple {13110#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {13110#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:18,159 INFO L290 TraceCheckUtils]: 6: Hoare triple {13110#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {13110#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:18,159 INFO L290 TraceCheckUtils]: 7: Hoare triple {13110#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {13110#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:18,159 INFO L290 TraceCheckUtils]: 8: Hoare triple {13110#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {13110#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:18,160 INFO L290 TraceCheckUtils]: 9: Hoare triple {13110#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {13109#false} is VALID [2022-02-21 04:24:18,160 INFO L290 TraceCheckUtils]: 10: Hoare triple {13109#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {13109#false} is VALID [2022-02-21 04:24:18,160 INFO L290 TraceCheckUtils]: 11: Hoare triple {13109#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {13109#false} is VALID [2022-02-21 04:24:18,160 INFO L290 TraceCheckUtils]: 12: Hoare triple {13109#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {13109#false} is VALID [2022-02-21 04:24:18,160 INFO L290 TraceCheckUtils]: 13: Hoare triple {13109#false} assume !(0 == ~M_E~0); {13109#false} is VALID [2022-02-21 04:24:18,160 INFO L290 TraceCheckUtils]: 14: Hoare triple {13109#false} assume !(0 == ~T1_E~0); {13109#false} is VALID [2022-02-21 04:24:18,160 INFO L290 TraceCheckUtils]: 15: Hoare triple {13109#false} assume !(0 == ~T2_E~0); {13109#false} is VALID [2022-02-21 04:24:18,160 INFO L290 TraceCheckUtils]: 16: Hoare triple {13109#false} assume !(0 == ~T3_E~0); {13109#false} is VALID [2022-02-21 04:24:18,160 INFO L290 TraceCheckUtils]: 17: Hoare triple {13109#false} assume !(0 == ~T4_E~0); {13109#false} is VALID [2022-02-21 04:24:18,161 INFO L290 TraceCheckUtils]: 18: Hoare triple {13109#false} assume !(0 == ~T5_E~0); {13109#false} is VALID [2022-02-21 04:24:18,161 INFO L290 TraceCheckUtils]: 19: Hoare triple {13109#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {13109#false} is VALID [2022-02-21 04:24:18,161 INFO L290 TraceCheckUtils]: 20: Hoare triple {13109#false} assume !(0 == ~T7_E~0); {13109#false} is VALID [2022-02-21 04:24:18,161 INFO L290 TraceCheckUtils]: 21: Hoare triple {13109#false} assume !(0 == ~E_1~0); {13109#false} is VALID [2022-02-21 04:24:18,161 INFO L290 TraceCheckUtils]: 22: Hoare triple {13109#false} assume !(0 == ~E_2~0); {13109#false} is VALID [2022-02-21 04:24:18,161 INFO L290 TraceCheckUtils]: 23: Hoare triple {13109#false} assume !(0 == ~E_3~0); {13109#false} is VALID [2022-02-21 04:24:18,161 INFO L290 TraceCheckUtils]: 24: Hoare triple {13109#false} assume !(0 == ~E_4~0); {13109#false} is VALID [2022-02-21 04:24:18,161 INFO L290 TraceCheckUtils]: 25: Hoare triple {13109#false} assume !(0 == ~E_5~0); {13109#false} is VALID [2022-02-21 04:24:18,161 INFO L290 TraceCheckUtils]: 26: Hoare triple {13109#false} assume !(0 == ~E_6~0); {13109#false} is VALID [2022-02-21 04:24:18,161 INFO L290 TraceCheckUtils]: 27: Hoare triple {13109#false} assume 0 == ~E_7~0;~E_7~0 := 1; {13109#false} is VALID [2022-02-21 04:24:18,162 INFO L290 TraceCheckUtils]: 28: Hoare triple {13109#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {13109#false} is VALID [2022-02-21 04:24:18,162 INFO L290 TraceCheckUtils]: 29: Hoare triple {13109#false} assume 1 == ~m_pc~0; {13109#false} is VALID [2022-02-21 04:24:18,162 INFO L290 TraceCheckUtils]: 30: Hoare triple {13109#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {13109#false} is VALID [2022-02-21 04:24:18,162 INFO L290 TraceCheckUtils]: 31: Hoare triple {13109#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {13109#false} is VALID [2022-02-21 04:24:18,162 INFO L290 TraceCheckUtils]: 32: Hoare triple {13109#false} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {13109#false} is VALID [2022-02-21 04:24:18,162 INFO L290 TraceCheckUtils]: 33: Hoare triple {13109#false} assume !(0 != activate_threads_~tmp~1#1); {13109#false} is VALID [2022-02-21 04:24:18,162 INFO L290 TraceCheckUtils]: 34: Hoare triple {13109#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {13109#false} is VALID [2022-02-21 04:24:18,162 INFO L290 TraceCheckUtils]: 35: Hoare triple {13109#false} assume !(1 == ~t1_pc~0); {13109#false} is VALID [2022-02-21 04:24:18,162 INFO L290 TraceCheckUtils]: 36: Hoare triple {13109#false} is_transmit1_triggered_~__retres1~1#1 := 0; {13109#false} is VALID [2022-02-21 04:24:18,162 INFO L290 TraceCheckUtils]: 37: Hoare triple {13109#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {13109#false} is VALID [2022-02-21 04:24:18,163 INFO L290 TraceCheckUtils]: 38: Hoare triple {13109#false} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {13109#false} is VALID [2022-02-21 04:24:18,163 INFO L290 TraceCheckUtils]: 39: Hoare triple {13109#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {13109#false} is VALID [2022-02-21 04:24:18,163 INFO L290 TraceCheckUtils]: 40: Hoare triple {13109#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {13109#false} is VALID [2022-02-21 04:24:18,163 INFO L290 TraceCheckUtils]: 41: Hoare triple {13109#false} assume 1 == ~t2_pc~0; {13109#false} is VALID [2022-02-21 04:24:18,163 INFO L290 TraceCheckUtils]: 42: Hoare triple {13109#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {13109#false} is VALID [2022-02-21 04:24:18,163 INFO L290 TraceCheckUtils]: 43: Hoare triple {13109#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {13109#false} is VALID [2022-02-21 04:24:18,163 INFO L290 TraceCheckUtils]: 44: Hoare triple {13109#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {13109#false} is VALID [2022-02-21 04:24:18,163 INFO L290 TraceCheckUtils]: 45: Hoare triple {13109#false} assume !(0 != activate_threads_~tmp___1~0#1); {13109#false} is VALID [2022-02-21 04:24:18,163 INFO L290 TraceCheckUtils]: 46: Hoare triple {13109#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {13109#false} is VALID [2022-02-21 04:24:18,164 INFO L290 TraceCheckUtils]: 47: Hoare triple {13109#false} assume !(1 == ~t3_pc~0); {13109#false} is VALID [2022-02-21 04:24:18,164 INFO L290 TraceCheckUtils]: 48: Hoare triple {13109#false} is_transmit3_triggered_~__retres1~3#1 := 0; {13109#false} is VALID [2022-02-21 04:24:18,164 INFO L290 TraceCheckUtils]: 49: Hoare triple {13109#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {13109#false} is VALID [2022-02-21 04:24:18,164 INFO L290 TraceCheckUtils]: 50: Hoare triple {13109#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {13109#false} is VALID [2022-02-21 04:24:18,164 INFO L290 TraceCheckUtils]: 51: Hoare triple {13109#false} assume !(0 != activate_threads_~tmp___2~0#1); {13109#false} is VALID [2022-02-21 04:24:18,164 INFO L290 TraceCheckUtils]: 52: Hoare triple {13109#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {13109#false} is VALID [2022-02-21 04:24:18,164 INFO L290 TraceCheckUtils]: 53: Hoare triple {13109#false} assume 1 == ~t4_pc~0; {13109#false} is VALID [2022-02-21 04:24:18,164 INFO L290 TraceCheckUtils]: 54: Hoare triple {13109#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {13109#false} is VALID [2022-02-21 04:24:18,164 INFO L290 TraceCheckUtils]: 55: Hoare triple {13109#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {13109#false} is VALID [2022-02-21 04:24:18,164 INFO L290 TraceCheckUtils]: 56: Hoare triple {13109#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {13109#false} is VALID [2022-02-21 04:24:18,165 INFO L290 TraceCheckUtils]: 57: Hoare triple {13109#false} assume !(0 != activate_threads_~tmp___3~0#1); {13109#false} is VALID [2022-02-21 04:24:18,165 INFO L290 TraceCheckUtils]: 58: Hoare triple {13109#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {13109#false} is VALID [2022-02-21 04:24:18,165 INFO L290 TraceCheckUtils]: 59: Hoare triple {13109#false} assume !(1 == ~t5_pc~0); {13109#false} is VALID [2022-02-21 04:24:18,165 INFO L290 TraceCheckUtils]: 60: Hoare triple {13109#false} is_transmit5_triggered_~__retres1~5#1 := 0; {13109#false} is VALID [2022-02-21 04:24:18,165 INFO L290 TraceCheckUtils]: 61: Hoare triple {13109#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {13109#false} is VALID [2022-02-21 04:24:18,165 INFO L290 TraceCheckUtils]: 62: Hoare triple {13109#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {13109#false} is VALID [2022-02-21 04:24:18,165 INFO L290 TraceCheckUtils]: 63: Hoare triple {13109#false} assume !(0 != activate_threads_~tmp___4~0#1); {13109#false} is VALID [2022-02-21 04:24:18,165 INFO L290 TraceCheckUtils]: 64: Hoare triple {13109#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {13109#false} is VALID [2022-02-21 04:24:18,165 INFO L290 TraceCheckUtils]: 65: Hoare triple {13109#false} assume 1 == ~t6_pc~0; {13109#false} is VALID [2022-02-21 04:24:18,165 INFO L290 TraceCheckUtils]: 66: Hoare triple {13109#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {13109#false} is VALID [2022-02-21 04:24:18,166 INFO L290 TraceCheckUtils]: 67: Hoare triple {13109#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {13109#false} is VALID [2022-02-21 04:24:18,166 INFO L290 TraceCheckUtils]: 68: Hoare triple {13109#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {13109#false} is VALID [2022-02-21 04:24:18,166 INFO L290 TraceCheckUtils]: 69: Hoare triple {13109#false} assume !(0 != activate_threads_~tmp___5~0#1); {13109#false} is VALID [2022-02-21 04:24:18,166 INFO L290 TraceCheckUtils]: 70: Hoare triple {13109#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {13109#false} is VALID [2022-02-21 04:24:18,166 INFO L290 TraceCheckUtils]: 71: Hoare triple {13109#false} assume 1 == ~t7_pc~0; {13109#false} is VALID [2022-02-21 04:24:18,166 INFO L290 TraceCheckUtils]: 72: Hoare triple {13109#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {13109#false} is VALID [2022-02-21 04:24:18,166 INFO L290 TraceCheckUtils]: 73: Hoare triple {13109#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {13109#false} is VALID [2022-02-21 04:24:18,166 INFO L290 TraceCheckUtils]: 74: Hoare triple {13109#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {13109#false} is VALID [2022-02-21 04:24:18,166 INFO L290 TraceCheckUtils]: 75: Hoare triple {13109#false} assume !(0 != activate_threads_~tmp___6~0#1); {13109#false} is VALID [2022-02-21 04:24:18,166 INFO L290 TraceCheckUtils]: 76: Hoare triple {13109#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {13109#false} is VALID [2022-02-21 04:24:18,167 INFO L290 TraceCheckUtils]: 77: Hoare triple {13109#false} assume !(1 == ~M_E~0); {13109#false} is VALID [2022-02-21 04:24:18,167 INFO L290 TraceCheckUtils]: 78: Hoare triple {13109#false} assume !(1 == ~T1_E~0); {13109#false} is VALID [2022-02-21 04:24:18,167 INFO L290 TraceCheckUtils]: 79: Hoare triple {13109#false} assume !(1 == ~T2_E~0); {13109#false} is VALID [2022-02-21 04:24:18,167 INFO L290 TraceCheckUtils]: 80: Hoare triple {13109#false} assume !(1 == ~T3_E~0); {13109#false} is VALID [2022-02-21 04:24:18,167 INFO L290 TraceCheckUtils]: 81: Hoare triple {13109#false} assume !(1 == ~T4_E~0); {13109#false} is VALID [2022-02-21 04:24:18,167 INFO L290 TraceCheckUtils]: 82: Hoare triple {13109#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {13109#false} is VALID [2022-02-21 04:24:18,167 INFO L290 TraceCheckUtils]: 83: Hoare triple {13109#false} assume !(1 == ~T6_E~0); {13109#false} is VALID [2022-02-21 04:24:18,167 INFO L290 TraceCheckUtils]: 84: Hoare triple {13109#false} assume !(1 == ~T7_E~0); {13109#false} is VALID [2022-02-21 04:24:18,167 INFO L290 TraceCheckUtils]: 85: Hoare triple {13109#false} assume !(1 == ~E_1~0); {13109#false} is VALID [2022-02-21 04:24:18,168 INFO L290 TraceCheckUtils]: 86: Hoare triple {13109#false} assume !(1 == ~E_2~0); {13109#false} is VALID [2022-02-21 04:24:18,168 INFO L290 TraceCheckUtils]: 87: Hoare triple {13109#false} assume !(1 == ~E_3~0); {13109#false} is VALID [2022-02-21 04:24:18,168 INFO L290 TraceCheckUtils]: 88: Hoare triple {13109#false} assume !(1 == ~E_4~0); {13109#false} is VALID [2022-02-21 04:24:18,168 INFO L290 TraceCheckUtils]: 89: Hoare triple {13109#false} assume !(1 == ~E_5~0); {13109#false} is VALID [2022-02-21 04:24:18,168 INFO L290 TraceCheckUtils]: 90: Hoare triple {13109#false} assume 1 == ~E_6~0;~E_6~0 := 2; {13109#false} is VALID [2022-02-21 04:24:18,168 INFO L290 TraceCheckUtils]: 91: Hoare triple {13109#false} assume !(1 == ~E_7~0); {13109#false} is VALID [2022-02-21 04:24:18,168 INFO L290 TraceCheckUtils]: 92: Hoare triple {13109#false} assume { :end_inline_reset_delta_events } true; {13109#false} is VALID [2022-02-21 04:24:18,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:18,169 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:18,169 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1330433425] [2022-02-21 04:24:18,169 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1330433425] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:18,169 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:18,169 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:18,169 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514652432] [2022-02-21 04:24:18,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:18,170 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:18,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:18,170 INFO L85 PathProgramCache]: Analyzing trace with hash -1026171705, now seen corresponding path program 1 times [2022-02-21 04:24:18,170 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:18,170 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815403482] [2022-02-21 04:24:18,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:18,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:18,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:18,193 INFO L290 TraceCheckUtils]: 0: Hoare triple {13111#true} assume !false; {13111#true} is VALID [2022-02-21 04:24:18,194 INFO L290 TraceCheckUtils]: 1: Hoare triple {13111#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {13111#true} is VALID [2022-02-21 04:24:18,194 INFO L290 TraceCheckUtils]: 2: Hoare triple {13111#true} assume !false; {13111#true} is VALID [2022-02-21 04:24:18,194 INFO L290 TraceCheckUtils]: 3: Hoare triple {13111#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {13111#true} is VALID [2022-02-21 04:24:18,194 INFO L290 TraceCheckUtils]: 4: Hoare triple {13111#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {13111#true} is VALID [2022-02-21 04:24:18,194 INFO L290 TraceCheckUtils]: 5: Hoare triple {13111#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {13111#true} is VALID [2022-02-21 04:24:18,194 INFO L290 TraceCheckUtils]: 6: Hoare triple {13111#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {13111#true} is VALID [2022-02-21 04:24:18,194 INFO L290 TraceCheckUtils]: 7: Hoare triple {13111#true} assume !(0 != eval_~tmp~0#1); {13111#true} is VALID [2022-02-21 04:24:18,194 INFO L290 TraceCheckUtils]: 8: Hoare triple {13111#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {13111#true} is VALID [2022-02-21 04:24:18,194 INFO L290 TraceCheckUtils]: 9: Hoare triple {13111#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {13111#true} is VALID [2022-02-21 04:24:18,195 INFO L290 TraceCheckUtils]: 10: Hoare triple {13111#true} assume 0 == ~M_E~0;~M_E~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,195 INFO L290 TraceCheckUtils]: 11: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,195 INFO L290 TraceCheckUtils]: 12: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,196 INFO L290 TraceCheckUtils]: 13: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,196 INFO L290 TraceCheckUtils]: 14: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,196 INFO L290 TraceCheckUtils]: 15: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,196 INFO L290 TraceCheckUtils]: 16: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,197 INFO L290 TraceCheckUtils]: 17: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,197 INFO L290 TraceCheckUtils]: 18: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,197 INFO L290 TraceCheckUtils]: 19: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,197 INFO L290 TraceCheckUtils]: 20: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,198 INFO L290 TraceCheckUtils]: 21: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,198 INFO L290 TraceCheckUtils]: 22: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,198 INFO L290 TraceCheckUtils]: 23: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,199 INFO L290 TraceCheckUtils]: 24: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,199 INFO L290 TraceCheckUtils]: 25: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,199 INFO L290 TraceCheckUtils]: 26: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,199 INFO L290 TraceCheckUtils]: 27: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,200 INFO L290 TraceCheckUtils]: 28: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,200 INFO L290 TraceCheckUtils]: 29: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,200 INFO L290 TraceCheckUtils]: 30: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,200 INFO L290 TraceCheckUtils]: 31: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,201 INFO L290 TraceCheckUtils]: 32: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,201 INFO L290 TraceCheckUtils]: 33: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,201 INFO L290 TraceCheckUtils]: 34: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,201 INFO L290 TraceCheckUtils]: 35: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,202 INFO L290 TraceCheckUtils]: 36: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,202 INFO L290 TraceCheckUtils]: 37: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,202 INFO L290 TraceCheckUtils]: 38: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,203 INFO L290 TraceCheckUtils]: 39: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,203 INFO L290 TraceCheckUtils]: 40: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,203 INFO L290 TraceCheckUtils]: 41: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,203 INFO L290 TraceCheckUtils]: 42: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,204 INFO L290 TraceCheckUtils]: 43: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,204 INFO L290 TraceCheckUtils]: 44: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,204 INFO L290 TraceCheckUtils]: 45: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,204 INFO L290 TraceCheckUtils]: 46: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,205 INFO L290 TraceCheckUtils]: 47: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,205 INFO L290 TraceCheckUtils]: 48: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,205 INFO L290 TraceCheckUtils]: 49: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,205 INFO L290 TraceCheckUtils]: 50: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,206 INFO L290 TraceCheckUtils]: 51: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,206 INFO L290 TraceCheckUtils]: 52: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,206 INFO L290 TraceCheckUtils]: 53: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,206 INFO L290 TraceCheckUtils]: 54: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,207 INFO L290 TraceCheckUtils]: 55: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,207 INFO L290 TraceCheckUtils]: 56: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,207 INFO L290 TraceCheckUtils]: 57: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,208 INFO L290 TraceCheckUtils]: 58: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,208 INFO L290 TraceCheckUtils]: 59: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,208 INFO L290 TraceCheckUtils]: 60: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,208 INFO L290 TraceCheckUtils]: 61: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,209 INFO L290 TraceCheckUtils]: 62: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,209 INFO L290 TraceCheckUtils]: 63: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,209 INFO L290 TraceCheckUtils]: 64: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,209 INFO L290 TraceCheckUtils]: 65: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,210 INFO L290 TraceCheckUtils]: 66: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,210 INFO L290 TraceCheckUtils]: 67: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,210 INFO L290 TraceCheckUtils]: 68: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,210 INFO L290 TraceCheckUtils]: 69: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,211 INFO L290 TraceCheckUtils]: 70: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,211 INFO L290 TraceCheckUtils]: 71: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,211 INFO L290 TraceCheckUtils]: 72: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,211 INFO L290 TraceCheckUtils]: 73: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {13113#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:18,212 INFO L290 TraceCheckUtils]: 74: Hoare triple {13113#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {13112#false} is VALID [2022-02-21 04:24:18,212 INFO L290 TraceCheckUtils]: 75: Hoare triple {13112#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,212 INFO L290 TraceCheckUtils]: 76: Hoare triple {13112#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,212 INFO L290 TraceCheckUtils]: 77: Hoare triple {13112#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,212 INFO L290 TraceCheckUtils]: 78: Hoare triple {13112#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,212 INFO L290 TraceCheckUtils]: 79: Hoare triple {13112#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,212 INFO L290 TraceCheckUtils]: 80: Hoare triple {13112#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,212 INFO L290 TraceCheckUtils]: 81: Hoare triple {13112#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,213 INFO L290 TraceCheckUtils]: 82: Hoare triple {13112#false} assume !(1 == ~E_1~0); {13112#false} is VALID [2022-02-21 04:24:18,213 INFO L290 TraceCheckUtils]: 83: Hoare triple {13112#false} assume 1 == ~E_2~0;~E_2~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,213 INFO L290 TraceCheckUtils]: 84: Hoare triple {13112#false} assume 1 == ~E_3~0;~E_3~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,213 INFO L290 TraceCheckUtils]: 85: Hoare triple {13112#false} assume 1 == ~E_4~0;~E_4~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,213 INFO L290 TraceCheckUtils]: 86: Hoare triple {13112#false} assume 1 == ~E_5~0;~E_5~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,213 INFO L290 TraceCheckUtils]: 87: Hoare triple {13112#false} assume 1 == ~E_6~0;~E_6~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,213 INFO L290 TraceCheckUtils]: 88: Hoare triple {13112#false} assume 1 == ~E_7~0;~E_7~0 := 2; {13112#false} is VALID [2022-02-21 04:24:18,213 INFO L290 TraceCheckUtils]: 89: Hoare triple {13112#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {13112#false} is VALID [2022-02-21 04:24:18,213 INFO L290 TraceCheckUtils]: 90: Hoare triple {13112#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {13112#false} is VALID [2022-02-21 04:24:18,213 INFO L290 TraceCheckUtils]: 91: Hoare triple {13112#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {13112#false} is VALID [2022-02-21 04:24:18,214 INFO L290 TraceCheckUtils]: 92: Hoare triple {13112#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {13112#false} is VALID [2022-02-21 04:24:18,214 INFO L290 TraceCheckUtils]: 93: Hoare triple {13112#false} assume !(0 == start_simulation_~tmp~3#1); {13112#false} is VALID [2022-02-21 04:24:18,214 INFO L290 TraceCheckUtils]: 94: Hoare triple {13112#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {13112#false} is VALID [2022-02-21 04:24:18,214 INFO L290 TraceCheckUtils]: 95: Hoare triple {13112#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {13112#false} is VALID [2022-02-21 04:24:18,214 INFO L290 TraceCheckUtils]: 96: Hoare triple {13112#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {13112#false} is VALID [2022-02-21 04:24:18,214 INFO L290 TraceCheckUtils]: 97: Hoare triple {13112#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {13112#false} is VALID [2022-02-21 04:24:18,214 INFO L290 TraceCheckUtils]: 98: Hoare triple {13112#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {13112#false} is VALID [2022-02-21 04:24:18,214 INFO L290 TraceCheckUtils]: 99: Hoare triple {13112#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {13112#false} is VALID [2022-02-21 04:24:18,214 INFO L290 TraceCheckUtils]: 100: Hoare triple {13112#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {13112#false} is VALID [2022-02-21 04:24:18,215 INFO L290 TraceCheckUtils]: 101: Hoare triple {13112#false} assume !(0 != start_simulation_~tmp___0~1#1); {13112#false} is VALID [2022-02-21 04:24:18,215 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:18,215 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:18,215 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815403482] [2022-02-21 04:24:18,215 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815403482] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:18,215 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:18,216 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:18,216 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [125688433] [2022-02-21 04:24:18,216 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:18,216 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:18,216 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:18,217 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:18,217 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:18,217 INFO L87 Difference]: Start difference. First operand 768 states and 1145 transitions. cyclomatic complexity: 378 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,687 INFO L93 Difference]: Finished difference Result 768 states and 1144 transitions. [2022-02-21 04:24:18,687 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:18,687 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,728 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:18,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1144 transitions. [2022-02-21 04:24:18,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:18,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1144 transitions. [2022-02-21 04:24:18,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-02-21 04:24:18,794 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-02-21 04:24:18,795 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1144 transitions. [2022-02-21 04:24:18,795 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:18,795 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1144 transitions. [2022-02-21 04:24:18,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1144 transitions. [2022-02-21 04:24:18,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-02-21 04:24:18,812 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:18,814 INFO L82 GeneralOperation]: Start isEquivalent. First operand 768 states and 1144 transitions. Second operand has 768 states, 768 states have (on average 1.4895833333333333) internal successors, (1144), 767 states have internal predecessors, (1144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,815 INFO L74 IsIncluded]: Start isIncluded. First operand 768 states and 1144 transitions. Second operand has 768 states, 768 states have (on average 1.4895833333333333) internal successors, (1144), 767 states have internal predecessors, (1144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,816 INFO L87 Difference]: Start difference. First operand 768 states and 1144 transitions. Second operand has 768 states, 768 states have (on average 1.4895833333333333) internal successors, (1144), 767 states have internal predecessors, (1144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,847 INFO L93 Difference]: Finished difference Result 768 states and 1144 transitions. [2022-02-21 04:24:18,847 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1144 transitions. [2022-02-21 04:24:18,848 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:18,848 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:18,850 INFO L74 IsIncluded]: Start isIncluded. First operand has 768 states, 768 states have (on average 1.4895833333333333) internal successors, (1144), 767 states have internal predecessors, (1144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1144 transitions. [2022-02-21 04:24:18,852 INFO L87 Difference]: Start difference. First operand has 768 states, 768 states have (on average 1.4895833333333333) internal successors, (1144), 767 states have internal predecessors, (1144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1144 transitions. [2022-02-21 04:24:18,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,909 INFO L93 Difference]: Finished difference Result 768 states and 1144 transitions. [2022-02-21 04:24:18,909 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1144 transitions. [2022-02-21 04:24:18,910 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:18,910 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:18,910 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:18,910 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:18,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4895833333333333) internal successors, (1144), 767 states have internal predecessors, (1144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1144 transitions. [2022-02-21 04:24:18,951 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1144 transitions. [2022-02-21 04:24:18,951 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1144 transitions. [2022-02-21 04:24:18,951 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:18,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1144 transitions. [2022-02-21 04:24:18,954 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:18,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:18,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:18,955 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:18,955 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:18,955 INFO L791 eck$LassoCheckResult]: Stem: 14649#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 14628#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14629#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14089#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14090#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 14506#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14507#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14475#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14398#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14399#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14388#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14389#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14348#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14349#L754 assume !(0 == ~M_E~0); 14607#L754-2 assume !(0 == ~T1_E~0); 14291#L759-1 assume !(0 == ~T2_E~0); 14292#L764-1 assume !(0 == ~T3_E~0); 14636#L769-1 assume !(0 == ~T4_E~0); 14637#L774-1 assume !(0 == ~T5_E~0); 14537#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14322#L784-1 assume !(0 == ~T7_E~0); 14323#L789-1 assume !(0 == ~E_1~0); 14002#L794-1 assume !(0 == ~E_2~0); 14003#L799-1 assume !(0 == ~E_3~0); 14638#L804-1 assume !(0 == ~E_4~0); 14639#L809-1 assume !(0 == ~E_5~0); 14402#L814-1 assume !(0 == ~E_6~0); 13920#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 13921#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14384#L361 assume 1 == ~m_pc~0; 14385#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14426#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14207#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14208#L930 assume !(0 != activate_threads_~tmp~1#1); 14532#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14378#L380 assume !(1 == ~t1_pc~0); 14052#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14051#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14557#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14633#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14128#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14053#L399 assume 1 == ~t2_pc~0; 14054#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14260#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14567#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14446#L946 assume !(0 != activate_threads_~tmp___1~0#1); 13958#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13926#L418 assume !(1 == ~t3_pc~0); 13887#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13888#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14406#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14614#L954 assume !(0 != activate_threads_~tmp___2~0#1); 14644#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14609#L437 assume 1 == ~t4_pc~0; 14610#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14229#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14056#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14057#L962 assume !(0 != activate_threads_~tmp___3~0#1); 14485#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14184#L456 assume !(1 == ~t5_pc~0); 14185#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14288#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14588#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13948#L970 assume !(0 != activate_threads_~tmp___4~0#1); 13949#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14072#L475 assume 1 == ~t6_pc~0; 14073#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14148#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14149#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13908#L978 assume !(0 != activate_threads_~tmp___5~0#1); 13909#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14391#L494 assume 1 == ~t7_pc~0; 14392#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14432#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14584#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14585#L986 assume !(0 != activate_threads_~tmp___6~0#1); 14647#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14586#L837 assume !(1 == ~M_E~0); 14449#L837-2 assume !(1 == ~T1_E~0); 14035#L842-1 assume !(1 == ~T2_E~0); 14036#L847-1 assume !(1 == ~T3_E~0); 14502#L852-1 assume !(1 == ~T4_E~0); 14579#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14458#L862-1 assume !(1 == ~T6_E~0); 14459#L867-1 assume !(1 == ~T7_E~0); 14468#L872-1 assume !(1 == ~E_1~0); 14534#L877-1 assume !(1 == ~E_2~0); 14464#L882-1 assume !(1 == ~E_3~0); 14465#L887-1 assume !(1 == ~E_4~0); 14095#L892-1 assume !(1 == ~E_5~0); 14096#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 14482#L902-1 assume !(1 == ~E_7~0); 14176#L907-1 assume { :end_inline_reset_delta_events } true; 14177#L1148-2 [2022-02-21 04:24:18,956 INFO L793 eck$LassoCheckResult]: Loop: 14177#L1148-2 assume !false; 13922#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13923#L729 assume !false; 14319#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14315#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14266#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14335#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14373#L626 assume !(0 != eval_~tmp~0#1); 14374#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14504#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14408#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13961#L754-5 assume !(0 == ~T1_E~0); 13962#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14344#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14512#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14513#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14276#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13937#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13938#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13918#L794-3 assume !(0 == ~E_2~0); 13919#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14014#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14414#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14010#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14011#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14210#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14211#L361-24 assume 1 == ~m_pc~0; 14247#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14248#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13930#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13931#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14407#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14471#L380-24 assume !(1 == ~t1_pc~0); 14097#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 14098#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14530#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14403#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14058#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14059#L399-24 assume !(1 == ~t2_pc~0); 14272#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 14321#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14099#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14100#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14395#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14396#L418-24 assume 1 == ~t3_pc~0; 14400#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14007#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14397#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14275#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13950#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13951#L437-24 assume !(1 == ~t4_pc~0); 14224#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 14223#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14101#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14102#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14250#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14559#L456-24 assume 1 == ~t5_pc~0; 14560#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14620#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14313#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14314#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14453#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14587#L475-24 assume 1 == ~t6_pc~0; 13952#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13953#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14596#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14597#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 13895#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13896#L494-24 assume 1 == ~t7_pc~0; 14553#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14443#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14340#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14341#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14220#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14221#L837-3 assume !(1 == ~M_E~0); 14303#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14583#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14499#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13939#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13940#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14624#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14616#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14550#L872-3 assume !(1 == ~E_1~0); 14551#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14619#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14634#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14306#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14299#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14300#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14476#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14469#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13925#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14645#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 14605#L1167 assume !(0 == start_simulation_~tmp~3#1); 14500#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14527#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14332#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14566#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 14599#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14514#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13901#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 13902#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 14177#L1148-2 [2022-02-21 04:24:18,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:18,956 INFO L85 PathProgramCache]: Analyzing trace with hash -1148673299, now seen corresponding path program 1 times [2022-02-21 04:24:18,956 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:18,956 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1358050406] [2022-02-21 04:24:18,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:18,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:18,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:18,982 INFO L290 TraceCheckUtils]: 0: Hoare triple {16189#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {16189#true} is VALID [2022-02-21 04:24:18,983 INFO L290 TraceCheckUtils]: 1: Hoare triple {16189#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {16191#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:18,983 INFO L290 TraceCheckUtils]: 2: Hoare triple {16191#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {16191#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:18,983 INFO L290 TraceCheckUtils]: 3: Hoare triple {16191#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {16191#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:18,984 INFO L290 TraceCheckUtils]: 4: Hoare triple {16191#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {16191#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:18,984 INFO L290 TraceCheckUtils]: 5: Hoare triple {16191#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {16191#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:18,984 INFO L290 TraceCheckUtils]: 6: Hoare triple {16191#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {16191#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:18,984 INFO L290 TraceCheckUtils]: 7: Hoare triple {16191#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {16191#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:18,985 INFO L290 TraceCheckUtils]: 8: Hoare triple {16191#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {16191#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:18,985 INFO L290 TraceCheckUtils]: 9: Hoare triple {16191#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {16191#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:18,985 INFO L290 TraceCheckUtils]: 10: Hoare triple {16191#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {16190#false} is VALID [2022-02-21 04:24:18,985 INFO L290 TraceCheckUtils]: 11: Hoare triple {16190#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {16190#false} is VALID [2022-02-21 04:24:18,985 INFO L290 TraceCheckUtils]: 12: Hoare triple {16190#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {16190#false} is VALID [2022-02-21 04:24:18,985 INFO L290 TraceCheckUtils]: 13: Hoare triple {16190#false} assume !(0 == ~M_E~0); {16190#false} is VALID [2022-02-21 04:24:18,985 INFO L290 TraceCheckUtils]: 14: Hoare triple {16190#false} assume !(0 == ~T1_E~0); {16190#false} is VALID [2022-02-21 04:24:18,986 INFO L290 TraceCheckUtils]: 15: Hoare triple {16190#false} assume !(0 == ~T2_E~0); {16190#false} is VALID [2022-02-21 04:24:18,986 INFO L290 TraceCheckUtils]: 16: Hoare triple {16190#false} assume !(0 == ~T3_E~0); {16190#false} is VALID [2022-02-21 04:24:18,986 INFO L290 TraceCheckUtils]: 17: Hoare triple {16190#false} assume !(0 == ~T4_E~0); {16190#false} is VALID [2022-02-21 04:24:18,986 INFO L290 TraceCheckUtils]: 18: Hoare triple {16190#false} assume !(0 == ~T5_E~0); {16190#false} is VALID [2022-02-21 04:24:18,986 INFO L290 TraceCheckUtils]: 19: Hoare triple {16190#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {16190#false} is VALID [2022-02-21 04:24:18,986 INFO L290 TraceCheckUtils]: 20: Hoare triple {16190#false} assume !(0 == ~T7_E~0); {16190#false} is VALID [2022-02-21 04:24:18,986 INFO L290 TraceCheckUtils]: 21: Hoare triple {16190#false} assume !(0 == ~E_1~0); {16190#false} is VALID [2022-02-21 04:24:18,986 INFO L290 TraceCheckUtils]: 22: Hoare triple {16190#false} assume !(0 == ~E_2~0); {16190#false} is VALID [2022-02-21 04:24:18,986 INFO L290 TraceCheckUtils]: 23: Hoare triple {16190#false} assume !(0 == ~E_3~0); {16190#false} is VALID [2022-02-21 04:24:18,986 INFO L290 TraceCheckUtils]: 24: Hoare triple {16190#false} assume !(0 == ~E_4~0); {16190#false} is VALID [2022-02-21 04:24:18,987 INFO L290 TraceCheckUtils]: 25: Hoare triple {16190#false} assume !(0 == ~E_5~0); {16190#false} is VALID [2022-02-21 04:24:18,987 INFO L290 TraceCheckUtils]: 26: Hoare triple {16190#false} assume !(0 == ~E_6~0); {16190#false} is VALID [2022-02-21 04:24:18,987 INFO L290 TraceCheckUtils]: 27: Hoare triple {16190#false} assume 0 == ~E_7~0;~E_7~0 := 1; {16190#false} is VALID [2022-02-21 04:24:18,987 INFO L290 TraceCheckUtils]: 28: Hoare triple {16190#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16190#false} is VALID [2022-02-21 04:24:18,987 INFO L290 TraceCheckUtils]: 29: Hoare triple {16190#false} assume 1 == ~m_pc~0; {16190#false} is VALID [2022-02-21 04:24:18,987 INFO L290 TraceCheckUtils]: 30: Hoare triple {16190#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {16190#false} is VALID [2022-02-21 04:24:18,987 INFO L290 TraceCheckUtils]: 31: Hoare triple {16190#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16190#false} is VALID [2022-02-21 04:24:18,987 INFO L290 TraceCheckUtils]: 32: Hoare triple {16190#false} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {16190#false} is VALID [2022-02-21 04:24:18,987 INFO L290 TraceCheckUtils]: 33: Hoare triple {16190#false} assume !(0 != activate_threads_~tmp~1#1); {16190#false} is VALID [2022-02-21 04:24:18,987 INFO L290 TraceCheckUtils]: 34: Hoare triple {16190#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16190#false} is VALID [2022-02-21 04:24:18,988 INFO L290 TraceCheckUtils]: 35: Hoare triple {16190#false} assume !(1 == ~t1_pc~0); {16190#false} is VALID [2022-02-21 04:24:18,988 INFO L290 TraceCheckUtils]: 36: Hoare triple {16190#false} is_transmit1_triggered_~__retres1~1#1 := 0; {16190#false} is VALID [2022-02-21 04:24:18,988 INFO L290 TraceCheckUtils]: 37: Hoare triple {16190#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16190#false} is VALID [2022-02-21 04:24:18,988 INFO L290 TraceCheckUtils]: 38: Hoare triple {16190#false} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {16190#false} is VALID [2022-02-21 04:24:18,988 INFO L290 TraceCheckUtils]: 39: Hoare triple {16190#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {16190#false} is VALID [2022-02-21 04:24:18,988 INFO L290 TraceCheckUtils]: 40: Hoare triple {16190#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16190#false} is VALID [2022-02-21 04:24:18,988 INFO L290 TraceCheckUtils]: 41: Hoare triple {16190#false} assume 1 == ~t2_pc~0; {16190#false} is VALID [2022-02-21 04:24:18,988 INFO L290 TraceCheckUtils]: 42: Hoare triple {16190#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {16190#false} is VALID [2022-02-21 04:24:18,988 INFO L290 TraceCheckUtils]: 43: Hoare triple {16190#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16190#false} is VALID [2022-02-21 04:24:18,988 INFO L290 TraceCheckUtils]: 44: Hoare triple {16190#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {16190#false} is VALID [2022-02-21 04:24:18,989 INFO L290 TraceCheckUtils]: 45: Hoare triple {16190#false} assume !(0 != activate_threads_~tmp___1~0#1); {16190#false} is VALID [2022-02-21 04:24:18,989 INFO L290 TraceCheckUtils]: 46: Hoare triple {16190#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16190#false} is VALID [2022-02-21 04:24:18,989 INFO L290 TraceCheckUtils]: 47: Hoare triple {16190#false} assume !(1 == ~t3_pc~0); {16190#false} is VALID [2022-02-21 04:24:18,989 INFO L290 TraceCheckUtils]: 48: Hoare triple {16190#false} is_transmit3_triggered_~__retres1~3#1 := 0; {16190#false} is VALID [2022-02-21 04:24:18,989 INFO L290 TraceCheckUtils]: 49: Hoare triple {16190#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16190#false} is VALID [2022-02-21 04:24:18,989 INFO L290 TraceCheckUtils]: 50: Hoare triple {16190#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {16190#false} is VALID [2022-02-21 04:24:18,989 INFO L290 TraceCheckUtils]: 51: Hoare triple {16190#false} assume !(0 != activate_threads_~tmp___2~0#1); {16190#false} is VALID [2022-02-21 04:24:18,989 INFO L290 TraceCheckUtils]: 52: Hoare triple {16190#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16190#false} is VALID [2022-02-21 04:24:19,003 INFO L290 TraceCheckUtils]: 53: Hoare triple {16190#false} assume 1 == ~t4_pc~0; {16190#false} is VALID [2022-02-21 04:24:19,003 INFO L290 TraceCheckUtils]: 54: Hoare triple {16190#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {16190#false} is VALID [2022-02-21 04:24:19,003 INFO L290 TraceCheckUtils]: 55: Hoare triple {16190#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16190#false} is VALID [2022-02-21 04:24:19,004 INFO L290 TraceCheckUtils]: 56: Hoare triple {16190#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {16190#false} is VALID [2022-02-21 04:24:19,004 INFO L290 TraceCheckUtils]: 57: Hoare triple {16190#false} assume !(0 != activate_threads_~tmp___3~0#1); {16190#false} is VALID [2022-02-21 04:24:19,004 INFO L290 TraceCheckUtils]: 58: Hoare triple {16190#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {16190#false} is VALID [2022-02-21 04:24:19,004 INFO L290 TraceCheckUtils]: 59: Hoare triple {16190#false} assume !(1 == ~t5_pc~0); {16190#false} is VALID [2022-02-21 04:24:19,004 INFO L290 TraceCheckUtils]: 60: Hoare triple {16190#false} is_transmit5_triggered_~__retres1~5#1 := 0; {16190#false} is VALID [2022-02-21 04:24:19,004 INFO L290 TraceCheckUtils]: 61: Hoare triple {16190#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {16190#false} is VALID [2022-02-21 04:24:19,004 INFO L290 TraceCheckUtils]: 62: Hoare triple {16190#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {16190#false} is VALID [2022-02-21 04:24:19,004 INFO L290 TraceCheckUtils]: 63: Hoare triple {16190#false} assume !(0 != activate_threads_~tmp___4~0#1); {16190#false} is VALID [2022-02-21 04:24:19,004 INFO L290 TraceCheckUtils]: 64: Hoare triple {16190#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {16190#false} is VALID [2022-02-21 04:24:19,004 INFO L290 TraceCheckUtils]: 65: Hoare triple {16190#false} assume 1 == ~t6_pc~0; {16190#false} is VALID [2022-02-21 04:24:19,005 INFO L290 TraceCheckUtils]: 66: Hoare triple {16190#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {16190#false} is VALID [2022-02-21 04:24:19,005 INFO L290 TraceCheckUtils]: 67: Hoare triple {16190#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {16190#false} is VALID [2022-02-21 04:24:19,005 INFO L290 TraceCheckUtils]: 68: Hoare triple {16190#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {16190#false} is VALID [2022-02-21 04:24:19,005 INFO L290 TraceCheckUtils]: 69: Hoare triple {16190#false} assume !(0 != activate_threads_~tmp___5~0#1); {16190#false} is VALID [2022-02-21 04:24:19,005 INFO L290 TraceCheckUtils]: 70: Hoare triple {16190#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {16190#false} is VALID [2022-02-21 04:24:19,005 INFO L290 TraceCheckUtils]: 71: Hoare triple {16190#false} assume 1 == ~t7_pc~0; {16190#false} is VALID [2022-02-21 04:24:19,005 INFO L290 TraceCheckUtils]: 72: Hoare triple {16190#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {16190#false} is VALID [2022-02-21 04:24:19,005 INFO L290 TraceCheckUtils]: 73: Hoare triple {16190#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {16190#false} is VALID [2022-02-21 04:24:19,005 INFO L290 TraceCheckUtils]: 74: Hoare triple {16190#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {16190#false} is VALID [2022-02-21 04:24:19,005 INFO L290 TraceCheckUtils]: 75: Hoare triple {16190#false} assume !(0 != activate_threads_~tmp___6~0#1); {16190#false} is VALID [2022-02-21 04:24:19,006 INFO L290 TraceCheckUtils]: 76: Hoare triple {16190#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16190#false} is VALID [2022-02-21 04:24:19,006 INFO L290 TraceCheckUtils]: 77: Hoare triple {16190#false} assume !(1 == ~M_E~0); {16190#false} is VALID [2022-02-21 04:24:19,006 INFO L290 TraceCheckUtils]: 78: Hoare triple {16190#false} assume !(1 == ~T1_E~0); {16190#false} is VALID [2022-02-21 04:24:19,006 INFO L290 TraceCheckUtils]: 79: Hoare triple {16190#false} assume !(1 == ~T2_E~0); {16190#false} is VALID [2022-02-21 04:24:19,006 INFO L290 TraceCheckUtils]: 80: Hoare triple {16190#false} assume !(1 == ~T3_E~0); {16190#false} is VALID [2022-02-21 04:24:19,006 INFO L290 TraceCheckUtils]: 81: Hoare triple {16190#false} assume !(1 == ~T4_E~0); {16190#false} is VALID [2022-02-21 04:24:19,006 INFO L290 TraceCheckUtils]: 82: Hoare triple {16190#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {16190#false} is VALID [2022-02-21 04:24:19,006 INFO L290 TraceCheckUtils]: 83: Hoare triple {16190#false} assume !(1 == ~T6_E~0); {16190#false} is VALID [2022-02-21 04:24:19,006 INFO L290 TraceCheckUtils]: 84: Hoare triple {16190#false} assume !(1 == ~T7_E~0); {16190#false} is VALID [2022-02-21 04:24:19,006 INFO L290 TraceCheckUtils]: 85: Hoare triple {16190#false} assume !(1 == ~E_1~0); {16190#false} is VALID [2022-02-21 04:24:19,007 INFO L290 TraceCheckUtils]: 86: Hoare triple {16190#false} assume !(1 == ~E_2~0); {16190#false} is VALID [2022-02-21 04:24:19,007 INFO L290 TraceCheckUtils]: 87: Hoare triple {16190#false} assume !(1 == ~E_3~0); {16190#false} is VALID [2022-02-21 04:24:19,007 INFO L290 TraceCheckUtils]: 88: Hoare triple {16190#false} assume !(1 == ~E_4~0); {16190#false} is VALID [2022-02-21 04:24:19,007 INFO L290 TraceCheckUtils]: 89: Hoare triple {16190#false} assume !(1 == ~E_5~0); {16190#false} is VALID [2022-02-21 04:24:19,007 INFO L290 TraceCheckUtils]: 90: Hoare triple {16190#false} assume 1 == ~E_6~0;~E_6~0 := 2; {16190#false} is VALID [2022-02-21 04:24:19,007 INFO L290 TraceCheckUtils]: 91: Hoare triple {16190#false} assume !(1 == ~E_7~0); {16190#false} is VALID [2022-02-21 04:24:19,007 INFO L290 TraceCheckUtils]: 92: Hoare triple {16190#false} assume { :end_inline_reset_delta_events } true; {16190#false} is VALID [2022-02-21 04:24:19,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:19,008 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:19,008 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1358050406] [2022-02-21 04:24:19,008 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1358050406] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:19,008 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:19,008 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:19,008 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1857136893] [2022-02-21 04:24:19,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:19,009 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:19,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:19,009 INFO L85 PathProgramCache]: Analyzing trace with hash -1101939098, now seen corresponding path program 1 times [2022-02-21 04:24:19,009 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:19,009 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856912351] [2022-02-21 04:24:19,009 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:19,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:19,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:19,047 INFO L290 TraceCheckUtils]: 0: Hoare triple {16192#true} assume !false; {16192#true} is VALID [2022-02-21 04:24:19,048 INFO L290 TraceCheckUtils]: 1: Hoare triple {16192#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {16192#true} is VALID [2022-02-21 04:24:19,048 INFO L290 TraceCheckUtils]: 2: Hoare triple {16192#true} assume !false; {16192#true} is VALID [2022-02-21 04:24:19,048 INFO L290 TraceCheckUtils]: 3: Hoare triple {16192#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {16192#true} is VALID [2022-02-21 04:24:19,048 INFO L290 TraceCheckUtils]: 4: Hoare triple {16192#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {16192#true} is VALID [2022-02-21 04:24:19,048 INFO L290 TraceCheckUtils]: 5: Hoare triple {16192#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {16192#true} is VALID [2022-02-21 04:24:19,048 INFO L290 TraceCheckUtils]: 6: Hoare triple {16192#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {16192#true} is VALID [2022-02-21 04:24:19,048 INFO L290 TraceCheckUtils]: 7: Hoare triple {16192#true} assume !(0 != eval_~tmp~0#1); {16192#true} is VALID [2022-02-21 04:24:19,048 INFO L290 TraceCheckUtils]: 8: Hoare triple {16192#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {16192#true} is VALID [2022-02-21 04:24:19,048 INFO L290 TraceCheckUtils]: 9: Hoare triple {16192#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {16192#true} is VALID [2022-02-21 04:24:19,048 INFO L290 TraceCheckUtils]: 10: Hoare triple {16192#true} assume 0 == ~M_E~0;~M_E~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,049 INFO L290 TraceCheckUtils]: 11: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,049 INFO L290 TraceCheckUtils]: 12: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,049 INFO L290 TraceCheckUtils]: 13: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,049 INFO L290 TraceCheckUtils]: 14: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,050 INFO L290 TraceCheckUtils]: 15: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,050 INFO L290 TraceCheckUtils]: 16: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,050 INFO L290 TraceCheckUtils]: 17: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,050 INFO L290 TraceCheckUtils]: 18: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,051 INFO L290 TraceCheckUtils]: 19: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,051 INFO L290 TraceCheckUtils]: 20: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,051 INFO L290 TraceCheckUtils]: 21: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,051 INFO L290 TraceCheckUtils]: 22: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,051 INFO L290 TraceCheckUtils]: 23: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,052 INFO L290 TraceCheckUtils]: 24: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,052 INFO L290 TraceCheckUtils]: 25: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,052 INFO L290 TraceCheckUtils]: 26: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,052 INFO L290 TraceCheckUtils]: 27: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,053 INFO L290 TraceCheckUtils]: 28: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,053 INFO L290 TraceCheckUtils]: 29: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,053 INFO L290 TraceCheckUtils]: 30: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,053 INFO L290 TraceCheckUtils]: 31: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,054 INFO L290 TraceCheckUtils]: 32: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,054 INFO L290 TraceCheckUtils]: 33: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,054 INFO L290 TraceCheckUtils]: 34: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,054 INFO L290 TraceCheckUtils]: 35: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,054 INFO L290 TraceCheckUtils]: 36: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,055 INFO L290 TraceCheckUtils]: 37: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,055 INFO L290 TraceCheckUtils]: 38: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,055 INFO L290 TraceCheckUtils]: 39: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,055 INFO L290 TraceCheckUtils]: 40: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,056 INFO L290 TraceCheckUtils]: 41: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,056 INFO L290 TraceCheckUtils]: 42: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,056 INFO L290 TraceCheckUtils]: 43: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,056 INFO L290 TraceCheckUtils]: 44: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,057 INFO L290 TraceCheckUtils]: 45: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,057 INFO L290 TraceCheckUtils]: 46: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,057 INFO L290 TraceCheckUtils]: 47: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,057 INFO L290 TraceCheckUtils]: 48: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,057 INFO L290 TraceCheckUtils]: 49: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,058 INFO L290 TraceCheckUtils]: 50: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,058 INFO L290 TraceCheckUtils]: 51: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,058 INFO L290 TraceCheckUtils]: 52: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,058 INFO L290 TraceCheckUtils]: 53: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,059 INFO L290 TraceCheckUtils]: 54: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,059 INFO L290 TraceCheckUtils]: 55: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,059 INFO L290 TraceCheckUtils]: 56: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,059 INFO L290 TraceCheckUtils]: 57: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,059 INFO L290 TraceCheckUtils]: 58: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,060 INFO L290 TraceCheckUtils]: 59: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,060 INFO L290 TraceCheckUtils]: 60: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,060 INFO L290 TraceCheckUtils]: 61: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,060 INFO L290 TraceCheckUtils]: 62: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,061 INFO L290 TraceCheckUtils]: 63: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,061 INFO L290 TraceCheckUtils]: 64: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,061 INFO L290 TraceCheckUtils]: 65: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,061 INFO L290 TraceCheckUtils]: 66: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,061 INFO L290 TraceCheckUtils]: 67: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,062 INFO L290 TraceCheckUtils]: 68: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,062 INFO L290 TraceCheckUtils]: 69: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,062 INFO L290 TraceCheckUtils]: 70: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,062 INFO L290 TraceCheckUtils]: 71: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,063 INFO L290 TraceCheckUtils]: 72: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,063 INFO L290 TraceCheckUtils]: 73: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16194#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,063 INFO L290 TraceCheckUtils]: 74: Hoare triple {16194#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {16193#false} is VALID [2022-02-21 04:24:19,063 INFO L290 TraceCheckUtils]: 75: Hoare triple {16193#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,063 INFO L290 TraceCheckUtils]: 76: Hoare triple {16193#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,063 INFO L290 TraceCheckUtils]: 77: Hoare triple {16193#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,064 INFO L290 TraceCheckUtils]: 78: Hoare triple {16193#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,064 INFO L290 TraceCheckUtils]: 79: Hoare triple {16193#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,064 INFO L290 TraceCheckUtils]: 80: Hoare triple {16193#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,064 INFO L290 TraceCheckUtils]: 81: Hoare triple {16193#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,064 INFO L290 TraceCheckUtils]: 82: Hoare triple {16193#false} assume !(1 == ~E_1~0); {16193#false} is VALID [2022-02-21 04:24:19,064 INFO L290 TraceCheckUtils]: 83: Hoare triple {16193#false} assume 1 == ~E_2~0;~E_2~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,064 INFO L290 TraceCheckUtils]: 84: Hoare triple {16193#false} assume 1 == ~E_3~0;~E_3~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,064 INFO L290 TraceCheckUtils]: 85: Hoare triple {16193#false} assume 1 == ~E_4~0;~E_4~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,064 INFO L290 TraceCheckUtils]: 86: Hoare triple {16193#false} assume 1 == ~E_5~0;~E_5~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,064 INFO L290 TraceCheckUtils]: 87: Hoare triple {16193#false} assume 1 == ~E_6~0;~E_6~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,065 INFO L290 TraceCheckUtils]: 88: Hoare triple {16193#false} assume 1 == ~E_7~0;~E_7~0 := 2; {16193#false} is VALID [2022-02-21 04:24:19,065 INFO L290 TraceCheckUtils]: 89: Hoare triple {16193#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {16193#false} is VALID [2022-02-21 04:24:19,065 INFO L290 TraceCheckUtils]: 90: Hoare triple {16193#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {16193#false} is VALID [2022-02-21 04:24:19,065 INFO L290 TraceCheckUtils]: 91: Hoare triple {16193#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {16193#false} is VALID [2022-02-21 04:24:19,065 INFO L290 TraceCheckUtils]: 92: Hoare triple {16193#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {16193#false} is VALID [2022-02-21 04:24:19,065 INFO L290 TraceCheckUtils]: 93: Hoare triple {16193#false} assume !(0 == start_simulation_~tmp~3#1); {16193#false} is VALID [2022-02-21 04:24:19,065 INFO L290 TraceCheckUtils]: 94: Hoare triple {16193#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {16193#false} is VALID [2022-02-21 04:24:19,065 INFO L290 TraceCheckUtils]: 95: Hoare triple {16193#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {16193#false} is VALID [2022-02-21 04:24:19,065 INFO L290 TraceCheckUtils]: 96: Hoare triple {16193#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {16193#false} is VALID [2022-02-21 04:24:19,065 INFO L290 TraceCheckUtils]: 97: Hoare triple {16193#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {16193#false} is VALID [2022-02-21 04:24:19,066 INFO L290 TraceCheckUtils]: 98: Hoare triple {16193#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {16193#false} is VALID [2022-02-21 04:24:19,066 INFO L290 TraceCheckUtils]: 99: Hoare triple {16193#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {16193#false} is VALID [2022-02-21 04:24:19,066 INFO L290 TraceCheckUtils]: 100: Hoare triple {16193#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {16193#false} is VALID [2022-02-21 04:24:19,066 INFO L290 TraceCheckUtils]: 101: Hoare triple {16193#false} assume !(0 != start_simulation_~tmp___0~1#1); {16193#false} is VALID [2022-02-21 04:24:19,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:19,066 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:19,066 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856912351] [2022-02-21 04:24:19,067 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856912351] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:19,067 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:19,067 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:19,067 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364257604] [2022-02-21 04:24:19,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:19,077 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:19,078 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:19,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:19,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:19,078 INFO L87 Difference]: Start difference. First operand 768 states and 1144 transitions. cyclomatic complexity: 377 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:19,491 INFO L93 Difference]: Finished difference Result 768 states and 1143 transitions. [2022-02-21 04:24:19,491 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:19,491 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,527 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:19,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1143 transitions. [2022-02-21 04:24:19,545 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:19,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1143 transitions. [2022-02-21 04:24:19,584 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-02-21 04:24:19,584 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-02-21 04:24:19,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1143 transitions. [2022-02-21 04:24:19,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:19,599 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1143 transitions. [2022-02-21 04:24:19,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1143 transitions. [2022-02-21 04:24:19,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-02-21 04:24:19,606 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:19,607 INFO L82 GeneralOperation]: Start isEquivalent. First operand 768 states and 1143 transitions. Second operand has 768 states, 768 states have (on average 1.48828125) internal successors, (1143), 767 states have internal predecessors, (1143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,608 INFO L74 IsIncluded]: Start isIncluded. First operand 768 states and 1143 transitions. Second operand has 768 states, 768 states have (on average 1.48828125) internal successors, (1143), 767 states have internal predecessors, (1143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,609 INFO L87 Difference]: Start difference. First operand 768 states and 1143 transitions. Second operand has 768 states, 768 states have (on average 1.48828125) internal successors, (1143), 767 states have internal predecessors, (1143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:19,651 INFO L93 Difference]: Finished difference Result 768 states and 1143 transitions. [2022-02-21 04:24:19,651 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1143 transitions. [2022-02-21 04:24:19,652 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:19,652 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:19,654 INFO L74 IsIncluded]: Start isIncluded. First operand has 768 states, 768 states have (on average 1.48828125) internal successors, (1143), 767 states have internal predecessors, (1143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1143 transitions. [2022-02-21 04:24:19,655 INFO L87 Difference]: Start difference. First operand has 768 states, 768 states have (on average 1.48828125) internal successors, (1143), 767 states have internal predecessors, (1143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1143 transitions. [2022-02-21 04:24:19,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:19,686 INFO L93 Difference]: Finished difference Result 768 states and 1143 transitions. [2022-02-21 04:24:19,687 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1143 transitions. [2022-02-21 04:24:19,687 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:19,688 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:19,688 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:19,688 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:19,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.48828125) internal successors, (1143), 767 states have internal predecessors, (1143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1143 transitions. [2022-02-21 04:24:19,705 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1143 transitions. [2022-02-21 04:24:19,705 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1143 transitions. [2022-02-21 04:24:19,705 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:19,705 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1143 transitions. [2022-02-21 04:24:19,708 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:19,708 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:19,708 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:19,709 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:19,709 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:19,710 INFO L791 eck$LassoCheckResult]: Stem: 17730#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 17709#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 17710#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17170#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17171#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 17587#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17588#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17556#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17479#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17480#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17469#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17470#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17429#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17430#L754 assume !(0 == ~M_E~0); 17688#L754-2 assume !(0 == ~T1_E~0); 17372#L759-1 assume !(0 == ~T2_E~0); 17373#L764-1 assume !(0 == ~T3_E~0); 17717#L769-1 assume !(0 == ~T4_E~0); 17718#L774-1 assume !(0 == ~T5_E~0); 17618#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17403#L784-1 assume !(0 == ~T7_E~0); 17404#L789-1 assume !(0 == ~E_1~0); 17083#L794-1 assume !(0 == ~E_2~0); 17084#L799-1 assume !(0 == ~E_3~0); 17719#L804-1 assume !(0 == ~E_4~0); 17720#L809-1 assume !(0 == ~E_5~0); 17483#L814-1 assume !(0 == ~E_6~0); 17001#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 17002#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17465#L361 assume 1 == ~m_pc~0; 17466#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17507#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17288#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17289#L930 assume !(0 != activate_threads_~tmp~1#1); 17613#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17459#L380 assume !(1 == ~t1_pc~0); 17133#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17132#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17638#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17714#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17209#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17134#L399 assume 1 == ~t2_pc~0; 17135#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17341#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17648#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17527#L946 assume !(0 != activate_threads_~tmp___1~0#1); 17039#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17007#L418 assume !(1 == ~t3_pc~0); 16968#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16969#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17487#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17695#L954 assume !(0 != activate_threads_~tmp___2~0#1); 17725#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17690#L437 assume 1 == ~t4_pc~0; 17691#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17310#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17137#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17138#L962 assume !(0 != activate_threads_~tmp___3~0#1); 17566#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17265#L456 assume !(1 == ~t5_pc~0); 17266#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17369#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17669#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17029#L970 assume !(0 != activate_threads_~tmp___4~0#1); 17030#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17153#L475 assume 1 == ~t6_pc~0; 17154#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17229#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17230#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16989#L978 assume !(0 != activate_threads_~tmp___5~0#1); 16990#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17472#L494 assume 1 == ~t7_pc~0; 17473#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17513#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17665#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17666#L986 assume !(0 != activate_threads_~tmp___6~0#1); 17728#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17667#L837 assume !(1 == ~M_E~0); 17530#L837-2 assume !(1 == ~T1_E~0); 17116#L842-1 assume !(1 == ~T2_E~0); 17117#L847-1 assume !(1 == ~T3_E~0); 17583#L852-1 assume !(1 == ~T4_E~0); 17660#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17539#L862-1 assume !(1 == ~T6_E~0); 17540#L867-1 assume !(1 == ~T7_E~0); 17549#L872-1 assume !(1 == ~E_1~0); 17615#L877-1 assume !(1 == ~E_2~0); 17545#L882-1 assume !(1 == ~E_3~0); 17546#L887-1 assume !(1 == ~E_4~0); 17176#L892-1 assume !(1 == ~E_5~0); 17177#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 17563#L902-1 assume !(1 == ~E_7~0); 17258#L907-1 assume { :end_inline_reset_delta_events } true; 17259#L1148-2 [2022-02-21 04:24:19,710 INFO L793 eck$LassoCheckResult]: Loop: 17259#L1148-2 assume !false; 17003#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17004#L729 assume !false; 17400#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 17396#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 17347#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 17416#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17454#L626 assume !(0 != eval_~tmp~0#1); 17455#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17585#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17489#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17042#L754-5 assume !(0 == ~T1_E~0); 17043#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17425#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17593#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17594#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17357#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17018#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17019#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16999#L794-3 assume !(0 == ~E_2~0); 17000#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17095#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17495#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17093#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17094#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17291#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17292#L361-24 assume 1 == ~m_pc~0; 17328#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17329#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17011#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17012#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17488#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17552#L380-24 assume 1 == ~t1_pc~0; 17553#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17179#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17611#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17484#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17139#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17140#L399-24 assume 1 == ~t2_pc~0; 17352#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17402#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17180#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17181#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17476#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17477#L418-24 assume 1 == ~t3_pc~0; 17481#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17088#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17478#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17356#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17031#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17032#L437-24 assume 1 == ~t4_pc~0; 17303#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17304#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17182#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17183#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17331#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17640#L456-24 assume 1 == ~t5_pc~0; 17641#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17701#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17394#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17395#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17534#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17668#L475-24 assume 1 == ~t6_pc~0; 17033#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17034#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17677#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17678#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 16976#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16977#L494-24 assume 1 == ~t7_pc~0; 17634#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17524#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17421#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17422#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17301#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17302#L837-3 assume !(1 == ~M_E~0); 17384#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17664#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17580#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17020#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17021#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17705#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17697#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17631#L872-3 assume !(1 == ~E_1~0); 17632#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17700#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17715#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17387#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17380#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17381#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17557#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 17550#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 17006#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 17726#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 17686#L1167 assume !(0 == start_simulation_~tmp~3#1); 17581#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 17608#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 17413#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 17647#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 17680#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17595#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16982#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 16983#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 17259#L1148-2 [2022-02-21 04:24:19,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:19,710 INFO L85 PathProgramCache]: Analyzing trace with hash 1821437803, now seen corresponding path program 1 times [2022-02-21 04:24:19,710 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:19,710 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769924559] [2022-02-21 04:24:19,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:19,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:19,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:19,737 INFO L290 TraceCheckUtils]: 0: Hoare triple {19270#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {19270#true} is VALID [2022-02-21 04:24:19,738 INFO L290 TraceCheckUtils]: 1: Hoare triple {19270#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {19272#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:19,738 INFO L290 TraceCheckUtils]: 2: Hoare triple {19272#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {19272#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:19,739 INFO L290 TraceCheckUtils]: 3: Hoare triple {19272#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {19272#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:19,739 INFO L290 TraceCheckUtils]: 4: Hoare triple {19272#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {19272#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:19,739 INFO L290 TraceCheckUtils]: 5: Hoare triple {19272#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {19272#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:19,740 INFO L290 TraceCheckUtils]: 6: Hoare triple {19272#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {19272#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:19,740 INFO L290 TraceCheckUtils]: 7: Hoare triple {19272#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {19272#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:19,740 INFO L290 TraceCheckUtils]: 8: Hoare triple {19272#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {19272#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:19,740 INFO L290 TraceCheckUtils]: 9: Hoare triple {19272#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {19272#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 10: Hoare triple {19272#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {19272#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 11: Hoare triple {19272#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {19271#false} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 12: Hoare triple {19271#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {19271#false} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 13: Hoare triple {19271#false} assume !(0 == ~M_E~0); {19271#false} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 14: Hoare triple {19271#false} assume !(0 == ~T1_E~0); {19271#false} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 15: Hoare triple {19271#false} assume !(0 == ~T2_E~0); {19271#false} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 16: Hoare triple {19271#false} assume !(0 == ~T3_E~0); {19271#false} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 17: Hoare triple {19271#false} assume !(0 == ~T4_E~0); {19271#false} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 18: Hoare triple {19271#false} assume !(0 == ~T5_E~0); {19271#false} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 19: Hoare triple {19271#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {19271#false} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 20: Hoare triple {19271#false} assume !(0 == ~T7_E~0); {19271#false} is VALID [2022-02-21 04:24:19,741 INFO L290 TraceCheckUtils]: 21: Hoare triple {19271#false} assume !(0 == ~E_1~0); {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 22: Hoare triple {19271#false} assume !(0 == ~E_2~0); {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 23: Hoare triple {19271#false} assume !(0 == ~E_3~0); {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 24: Hoare triple {19271#false} assume !(0 == ~E_4~0); {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 25: Hoare triple {19271#false} assume !(0 == ~E_5~0); {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 26: Hoare triple {19271#false} assume !(0 == ~E_6~0); {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 27: Hoare triple {19271#false} assume 0 == ~E_7~0;~E_7~0 := 1; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 28: Hoare triple {19271#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 29: Hoare triple {19271#false} assume 1 == ~m_pc~0; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 30: Hoare triple {19271#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 31: Hoare triple {19271#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 32: Hoare triple {19271#false} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 33: Hoare triple {19271#false} assume !(0 != activate_threads_~tmp~1#1); {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 34: Hoare triple {19271#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 35: Hoare triple {19271#false} assume !(1 == ~t1_pc~0); {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 36: Hoare triple {19271#false} is_transmit1_triggered_~__retres1~1#1 := 0; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 37: Hoare triple {19271#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 38: Hoare triple {19271#false} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 39: Hoare triple {19271#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 40: Hoare triple {19271#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 41: Hoare triple {19271#false} assume 1 == ~t2_pc~0; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 42: Hoare triple {19271#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 43: Hoare triple {19271#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {19271#false} is VALID [2022-02-21 04:24:19,742 INFO L290 TraceCheckUtils]: 44: Hoare triple {19271#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 45: Hoare triple {19271#false} assume !(0 != activate_threads_~tmp___1~0#1); {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 46: Hoare triple {19271#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 47: Hoare triple {19271#false} assume !(1 == ~t3_pc~0); {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 48: Hoare triple {19271#false} is_transmit3_triggered_~__retres1~3#1 := 0; {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 49: Hoare triple {19271#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 50: Hoare triple {19271#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 51: Hoare triple {19271#false} assume !(0 != activate_threads_~tmp___2~0#1); {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 52: Hoare triple {19271#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 53: Hoare triple {19271#false} assume 1 == ~t4_pc~0; {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 54: Hoare triple {19271#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 55: Hoare triple {19271#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 56: Hoare triple {19271#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 57: Hoare triple {19271#false} assume !(0 != activate_threads_~tmp___3~0#1); {19271#false} is VALID [2022-02-21 04:24:19,743 INFO L290 TraceCheckUtils]: 58: Hoare triple {19271#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {19271#false} is VALID [2022-02-21 04:24:19,768 INFO L290 TraceCheckUtils]: 59: Hoare triple {19271#false} assume !(1 == ~t5_pc~0); {19271#false} is VALID [2022-02-21 04:24:19,768 INFO L290 TraceCheckUtils]: 60: Hoare triple {19271#false} is_transmit5_triggered_~__retres1~5#1 := 0; {19271#false} is VALID [2022-02-21 04:24:19,768 INFO L290 TraceCheckUtils]: 61: Hoare triple {19271#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 62: Hoare triple {19271#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 63: Hoare triple {19271#false} assume !(0 != activate_threads_~tmp___4~0#1); {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 64: Hoare triple {19271#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 65: Hoare triple {19271#false} assume 1 == ~t6_pc~0; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 66: Hoare triple {19271#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 67: Hoare triple {19271#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 68: Hoare triple {19271#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 69: Hoare triple {19271#false} assume !(0 != activate_threads_~tmp___5~0#1); {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 70: Hoare triple {19271#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 71: Hoare triple {19271#false} assume 1 == ~t7_pc~0; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 72: Hoare triple {19271#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 73: Hoare triple {19271#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 74: Hoare triple {19271#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 75: Hoare triple {19271#false} assume !(0 != activate_threads_~tmp___6~0#1); {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 76: Hoare triple {19271#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {19271#false} is VALID [2022-02-21 04:24:19,769 INFO L290 TraceCheckUtils]: 77: Hoare triple {19271#false} assume !(1 == ~M_E~0); {19271#false} is VALID [2022-02-21 04:24:19,770 INFO L290 TraceCheckUtils]: 78: Hoare triple {19271#false} assume !(1 == ~T1_E~0); {19271#false} is VALID [2022-02-21 04:24:19,770 INFO L290 TraceCheckUtils]: 79: Hoare triple {19271#false} assume !(1 == ~T2_E~0); {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 80: Hoare triple {19271#false} assume !(1 == ~T3_E~0); {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 81: Hoare triple {19271#false} assume !(1 == ~T4_E~0); {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 82: Hoare triple {19271#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 83: Hoare triple {19271#false} assume !(1 == ~T6_E~0); {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 84: Hoare triple {19271#false} assume !(1 == ~T7_E~0); {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 85: Hoare triple {19271#false} assume !(1 == ~E_1~0); {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 86: Hoare triple {19271#false} assume !(1 == ~E_2~0); {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 87: Hoare triple {19271#false} assume !(1 == ~E_3~0); {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 88: Hoare triple {19271#false} assume !(1 == ~E_4~0); {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 89: Hoare triple {19271#false} assume !(1 == ~E_5~0); {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 90: Hoare triple {19271#false} assume 1 == ~E_6~0;~E_6~0 := 2; {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 91: Hoare triple {19271#false} assume !(1 == ~E_7~0); {19271#false} is VALID [2022-02-21 04:24:19,771 INFO L290 TraceCheckUtils]: 92: Hoare triple {19271#false} assume { :end_inline_reset_delta_events } true; {19271#false} is VALID [2022-02-21 04:24:19,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:19,772 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:19,772 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769924559] [2022-02-21 04:24:19,772 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1769924559] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:19,772 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:19,772 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:19,772 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856195798] [2022-02-21 04:24:19,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:19,772 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:19,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:19,773 INFO L85 PathProgramCache]: Analyzing trace with hash -2012046007, now seen corresponding path program 1 times [2022-02-21 04:24:19,773 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:19,773 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668226778] [2022-02-21 04:24:19,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:19,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:19,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:19,833 INFO L290 TraceCheckUtils]: 0: Hoare triple {19273#true} assume !false; {19273#true} is VALID [2022-02-21 04:24:19,833 INFO L290 TraceCheckUtils]: 1: Hoare triple {19273#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {19273#true} is VALID [2022-02-21 04:24:19,833 INFO L290 TraceCheckUtils]: 2: Hoare triple {19273#true} assume !false; {19273#true} is VALID [2022-02-21 04:24:19,833 INFO L290 TraceCheckUtils]: 3: Hoare triple {19273#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {19273#true} is VALID [2022-02-21 04:24:19,833 INFO L290 TraceCheckUtils]: 4: Hoare triple {19273#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {19273#true} is VALID [2022-02-21 04:24:19,833 INFO L290 TraceCheckUtils]: 5: Hoare triple {19273#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {19273#true} is VALID [2022-02-21 04:24:19,833 INFO L290 TraceCheckUtils]: 6: Hoare triple {19273#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {19273#true} is VALID [2022-02-21 04:24:19,834 INFO L290 TraceCheckUtils]: 7: Hoare triple {19273#true} assume !(0 != eval_~tmp~0#1); {19273#true} is VALID [2022-02-21 04:24:19,834 INFO L290 TraceCheckUtils]: 8: Hoare triple {19273#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {19273#true} is VALID [2022-02-21 04:24:19,834 INFO L290 TraceCheckUtils]: 9: Hoare triple {19273#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {19273#true} is VALID [2022-02-21 04:24:19,834 INFO L290 TraceCheckUtils]: 10: Hoare triple {19273#true} assume 0 == ~M_E~0;~M_E~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,834 INFO L290 TraceCheckUtils]: 11: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,835 INFO L290 TraceCheckUtils]: 12: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,835 INFO L290 TraceCheckUtils]: 13: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,835 INFO L290 TraceCheckUtils]: 14: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,835 INFO L290 TraceCheckUtils]: 15: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,836 INFO L290 TraceCheckUtils]: 16: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,836 INFO L290 TraceCheckUtils]: 17: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,836 INFO L290 TraceCheckUtils]: 18: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,836 INFO L290 TraceCheckUtils]: 19: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,837 INFO L290 TraceCheckUtils]: 20: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,837 INFO L290 TraceCheckUtils]: 21: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,837 INFO L290 TraceCheckUtils]: 22: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,837 INFO L290 TraceCheckUtils]: 23: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,838 INFO L290 TraceCheckUtils]: 24: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,838 INFO L290 TraceCheckUtils]: 25: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,838 INFO L290 TraceCheckUtils]: 26: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,838 INFO L290 TraceCheckUtils]: 27: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,839 INFO L290 TraceCheckUtils]: 28: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,839 INFO L290 TraceCheckUtils]: 29: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,839 INFO L290 TraceCheckUtils]: 30: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,839 INFO L290 TraceCheckUtils]: 31: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,840 INFO L290 TraceCheckUtils]: 32: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,840 INFO L290 TraceCheckUtils]: 33: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,840 INFO L290 TraceCheckUtils]: 34: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,841 INFO L290 TraceCheckUtils]: 35: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,841 INFO L290 TraceCheckUtils]: 36: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,841 INFO L290 TraceCheckUtils]: 37: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,841 INFO L290 TraceCheckUtils]: 38: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,842 INFO L290 TraceCheckUtils]: 39: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,842 INFO L290 TraceCheckUtils]: 40: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,842 INFO L290 TraceCheckUtils]: 41: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,842 INFO L290 TraceCheckUtils]: 42: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,843 INFO L290 TraceCheckUtils]: 43: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,843 INFO L290 TraceCheckUtils]: 44: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,843 INFO L290 TraceCheckUtils]: 45: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,855 INFO L290 TraceCheckUtils]: 46: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,856 INFO L290 TraceCheckUtils]: 47: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,856 INFO L290 TraceCheckUtils]: 48: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,856 INFO L290 TraceCheckUtils]: 49: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,857 INFO L290 TraceCheckUtils]: 50: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,857 INFO L290 TraceCheckUtils]: 51: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,857 INFO L290 TraceCheckUtils]: 52: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,858 INFO L290 TraceCheckUtils]: 53: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,858 INFO L290 TraceCheckUtils]: 54: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,858 INFO L290 TraceCheckUtils]: 55: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,859 INFO L290 TraceCheckUtils]: 56: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,859 INFO L290 TraceCheckUtils]: 57: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,859 INFO L290 TraceCheckUtils]: 58: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,860 INFO L290 TraceCheckUtils]: 59: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,860 INFO L290 TraceCheckUtils]: 60: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,860 INFO L290 TraceCheckUtils]: 61: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,860 INFO L290 TraceCheckUtils]: 62: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,861 INFO L290 TraceCheckUtils]: 63: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,861 INFO L290 TraceCheckUtils]: 64: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,861 INFO L290 TraceCheckUtils]: 65: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,862 INFO L290 TraceCheckUtils]: 66: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,862 INFO L290 TraceCheckUtils]: 67: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,862 INFO L290 TraceCheckUtils]: 68: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t7_pc~0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,862 INFO L290 TraceCheckUtils]: 69: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,863 INFO L290 TraceCheckUtils]: 70: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,863 INFO L290 TraceCheckUtils]: 71: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,863 INFO L290 TraceCheckUtils]: 72: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,864 INFO L290 TraceCheckUtils]: 73: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {19275#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:19,864 INFO L290 TraceCheckUtils]: 74: Hoare triple {19275#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {19274#false} is VALID [2022-02-21 04:24:19,864 INFO L290 TraceCheckUtils]: 75: Hoare triple {19274#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,864 INFO L290 TraceCheckUtils]: 76: Hoare triple {19274#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,864 INFO L290 TraceCheckUtils]: 77: Hoare triple {19274#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,864 INFO L290 TraceCheckUtils]: 78: Hoare triple {19274#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,865 INFO L290 TraceCheckUtils]: 79: Hoare triple {19274#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,865 INFO L290 TraceCheckUtils]: 80: Hoare triple {19274#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,865 INFO L290 TraceCheckUtils]: 81: Hoare triple {19274#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,865 INFO L290 TraceCheckUtils]: 82: Hoare triple {19274#false} assume !(1 == ~E_1~0); {19274#false} is VALID [2022-02-21 04:24:19,865 INFO L290 TraceCheckUtils]: 83: Hoare triple {19274#false} assume 1 == ~E_2~0;~E_2~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,865 INFO L290 TraceCheckUtils]: 84: Hoare triple {19274#false} assume 1 == ~E_3~0;~E_3~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,865 INFO L290 TraceCheckUtils]: 85: Hoare triple {19274#false} assume 1 == ~E_4~0;~E_4~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,865 INFO L290 TraceCheckUtils]: 86: Hoare triple {19274#false} assume 1 == ~E_5~0;~E_5~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,865 INFO L290 TraceCheckUtils]: 87: Hoare triple {19274#false} assume 1 == ~E_6~0;~E_6~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,866 INFO L290 TraceCheckUtils]: 88: Hoare triple {19274#false} assume 1 == ~E_7~0;~E_7~0 := 2; {19274#false} is VALID [2022-02-21 04:24:19,866 INFO L290 TraceCheckUtils]: 89: Hoare triple {19274#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {19274#false} is VALID [2022-02-21 04:24:19,866 INFO L290 TraceCheckUtils]: 90: Hoare triple {19274#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {19274#false} is VALID [2022-02-21 04:24:19,866 INFO L290 TraceCheckUtils]: 91: Hoare triple {19274#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {19274#false} is VALID [2022-02-21 04:24:19,866 INFO L290 TraceCheckUtils]: 92: Hoare triple {19274#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {19274#false} is VALID [2022-02-21 04:24:19,866 INFO L290 TraceCheckUtils]: 93: Hoare triple {19274#false} assume !(0 == start_simulation_~tmp~3#1); {19274#false} is VALID [2022-02-21 04:24:19,866 INFO L290 TraceCheckUtils]: 94: Hoare triple {19274#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {19274#false} is VALID [2022-02-21 04:24:19,866 INFO L290 TraceCheckUtils]: 95: Hoare triple {19274#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {19274#false} is VALID [2022-02-21 04:24:19,867 INFO L290 TraceCheckUtils]: 96: Hoare triple {19274#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {19274#false} is VALID [2022-02-21 04:24:19,867 INFO L290 TraceCheckUtils]: 97: Hoare triple {19274#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {19274#false} is VALID [2022-02-21 04:24:19,867 INFO L290 TraceCheckUtils]: 98: Hoare triple {19274#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {19274#false} is VALID [2022-02-21 04:24:19,867 INFO L290 TraceCheckUtils]: 99: Hoare triple {19274#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {19274#false} is VALID [2022-02-21 04:24:19,867 INFO L290 TraceCheckUtils]: 100: Hoare triple {19274#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {19274#false} is VALID [2022-02-21 04:24:19,867 INFO L290 TraceCheckUtils]: 101: Hoare triple {19274#false} assume !(0 != start_simulation_~tmp___0~1#1); {19274#false} is VALID [2022-02-21 04:24:19,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:19,868 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:19,868 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668226778] [2022-02-21 04:24:19,868 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1668226778] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:19,868 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:19,868 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:19,868 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1478608160] [2022-02-21 04:24:19,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:19,869 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:19,869 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:19,869 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:19,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:19,870 INFO L87 Difference]: Start difference. First operand 768 states and 1143 transitions. cyclomatic complexity: 376 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,345 INFO L93 Difference]: Finished difference Result 768 states and 1142 transitions. [2022-02-21 04:24:20,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:20,345 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,391 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:20,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 768 states and 1142 transitions. [2022-02-21 04:24:20,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:20,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 768 states to 768 states and 1142 transitions. [2022-02-21 04:24:20,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 768 [2022-02-21 04:24:20,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 768 [2022-02-21 04:24:20,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 768 states and 1142 transitions. [2022-02-21 04:24:20,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:20,428 INFO L681 BuchiCegarLoop]: Abstraction has 768 states and 1142 transitions. [2022-02-21 04:24:20,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 768 states and 1142 transitions. [2022-02-21 04:24:20,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 768 to 768. [2022-02-21 04:24:20,435 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:20,436 INFO L82 GeneralOperation]: Start isEquivalent. First operand 768 states and 1142 transitions. Second operand has 768 states, 768 states have (on average 1.4869791666666667) internal successors, (1142), 767 states have internal predecessors, (1142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,436 INFO L74 IsIncluded]: Start isIncluded. First operand 768 states and 1142 transitions. Second operand has 768 states, 768 states have (on average 1.4869791666666667) internal successors, (1142), 767 states have internal predecessors, (1142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,437 INFO L87 Difference]: Start difference. First operand 768 states and 1142 transitions. Second operand has 768 states, 768 states have (on average 1.4869791666666667) internal successors, (1142), 767 states have internal predecessors, (1142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,453 INFO L93 Difference]: Finished difference Result 768 states and 1142 transitions. [2022-02-21 04:24:20,453 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1142 transitions. [2022-02-21 04:24:20,454 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:20,454 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:20,455 INFO L74 IsIncluded]: Start isIncluded. First operand has 768 states, 768 states have (on average 1.4869791666666667) internal successors, (1142), 767 states have internal predecessors, (1142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1142 transitions. [2022-02-21 04:24:20,456 INFO L87 Difference]: Start difference. First operand has 768 states, 768 states have (on average 1.4869791666666667) internal successors, (1142), 767 states have internal predecessors, (1142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 768 states and 1142 transitions. [2022-02-21 04:24:20,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,471 INFO L93 Difference]: Finished difference Result 768 states and 1142 transitions. [2022-02-21 04:24:20,471 INFO L276 IsEmpty]: Start isEmpty. Operand 768 states and 1142 transitions. [2022-02-21 04:24:20,472 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:20,472 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:20,472 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:20,472 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:20,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 768 states, 768 states have (on average 1.4869791666666667) internal successors, (1142), 767 states have internal predecessors, (1142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 768 states to 768 states and 1142 transitions. [2022-02-21 04:24:20,488 INFO L704 BuchiCegarLoop]: Abstraction has 768 states and 1142 transitions. [2022-02-21 04:24:20,488 INFO L587 BuchiCegarLoop]: Abstraction has 768 states and 1142 transitions. [2022-02-21 04:24:20,488 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:20,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 768 states and 1142 transitions. [2022-02-21 04:24:20,491 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 667 [2022-02-21 04:24:20,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:20,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:20,492 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:20,492 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:20,492 INFO L791 eck$LassoCheckResult]: Stem: 20811#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 20790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 20791#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20251#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20252#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 20668#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20669#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20637#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20560#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20561#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20550#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20551#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20510#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20511#L754 assume !(0 == ~M_E~0); 20769#L754-2 assume !(0 == ~T1_E~0); 20453#L759-1 assume !(0 == ~T2_E~0); 20454#L764-1 assume !(0 == ~T3_E~0); 20798#L769-1 assume !(0 == ~T4_E~0); 20799#L774-1 assume !(0 == ~T5_E~0); 20699#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20484#L784-1 assume !(0 == ~T7_E~0); 20485#L789-1 assume !(0 == ~E_1~0); 20164#L794-1 assume !(0 == ~E_2~0); 20165#L799-1 assume !(0 == ~E_3~0); 20800#L804-1 assume !(0 == ~E_4~0); 20801#L809-1 assume !(0 == ~E_5~0); 20564#L814-1 assume !(0 == ~E_6~0); 20082#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 20083#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20546#L361 assume 1 == ~m_pc~0; 20547#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20588#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20369#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20370#L930 assume !(0 != activate_threads_~tmp~1#1); 20694#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20540#L380 assume !(1 == ~t1_pc~0); 20214#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20213#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20719#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20795#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20290#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20215#L399 assume 1 == ~t2_pc~0; 20216#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20422#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20729#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20608#L946 assume !(0 != activate_threads_~tmp___1~0#1); 20120#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20091#L418 assume !(1 == ~t3_pc~0); 20049#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20050#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20568#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20776#L954 assume !(0 != activate_threads_~tmp___2~0#1); 20806#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20771#L437 assume 1 == ~t4_pc~0; 20772#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20391#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20218#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20219#L962 assume !(0 != activate_threads_~tmp___3~0#1); 20647#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20346#L456 assume !(1 == ~t5_pc~0); 20347#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20450#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20750#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20110#L970 assume !(0 != activate_threads_~tmp___4~0#1); 20111#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20234#L475 assume 1 == ~t6_pc~0; 20235#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20310#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20311#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20070#L978 assume !(0 != activate_threads_~tmp___5~0#1); 20071#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20553#L494 assume 1 == ~t7_pc~0; 20554#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20594#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20746#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20747#L986 assume !(0 != activate_threads_~tmp___6~0#1); 20809#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20748#L837 assume !(1 == ~M_E~0); 20611#L837-2 assume !(1 == ~T1_E~0); 20197#L842-1 assume !(1 == ~T2_E~0); 20198#L847-1 assume !(1 == ~T3_E~0); 20664#L852-1 assume !(1 == ~T4_E~0); 20741#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20620#L862-1 assume !(1 == ~T6_E~0); 20621#L867-1 assume !(1 == ~T7_E~0); 20630#L872-1 assume !(1 == ~E_1~0); 20696#L877-1 assume !(1 == ~E_2~0); 20626#L882-1 assume !(1 == ~E_3~0); 20627#L887-1 assume !(1 == ~E_4~0); 20257#L892-1 assume !(1 == ~E_5~0); 20258#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 20644#L902-1 assume !(1 == ~E_7~0); 20339#L907-1 assume { :end_inline_reset_delta_events } true; 20340#L1148-2 [2022-02-21 04:24:20,492 INFO L793 eck$LassoCheckResult]: Loop: 20340#L1148-2 assume !false; 20084#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20085#L729 assume !false; 20481#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20477#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20428#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20497#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20535#L626 assume !(0 != eval_~tmp~0#1); 20536#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20666#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20570#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20123#L754-5 assume !(0 == ~T1_E~0); 20124#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20506#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20674#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20675#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20438#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20097#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20098#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20080#L794-3 assume !(0 == ~E_2~0); 20081#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20176#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20576#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20174#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20175#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20372#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20373#L361-24 assume 1 == ~m_pc~0; 20409#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20410#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20092#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20093#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20569#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20633#L380-24 assume !(1 == ~t1_pc~0); 20259#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 20260#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20692#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20565#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20220#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20221#L399-24 assume 1 == ~t2_pc~0; 20433#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20483#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20261#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20262#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20557#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20558#L418-24 assume 1 == ~t3_pc~0; 20562#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20169#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20559#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20437#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20112#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20113#L437-24 assume 1 == ~t4_pc~0; 20384#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20385#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20263#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20264#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20412#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20721#L456-24 assume 1 == ~t5_pc~0; 20722#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20782#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20475#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20476#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20615#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20749#L475-24 assume 1 == ~t6_pc~0; 20114#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20115#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20758#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20759#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 20057#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20058#L494-24 assume !(1 == ~t7_pc~0); 20625#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 20605#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20502#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20503#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20382#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20383#L837-3 assume !(1 == ~M_E~0); 20465#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20745#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20661#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20101#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20102#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20786#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20778#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20712#L872-3 assume !(1 == ~E_1~0); 20713#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20781#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20796#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20468#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20461#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20462#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20638#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20631#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20087#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20807#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 20767#L1167 assume !(0 == start_simulation_~tmp~3#1); 20662#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20689#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20494#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20728#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 20761#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20676#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20063#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 20064#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 20340#L1148-2 [2022-02-21 04:24:20,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:20,493 INFO L85 PathProgramCache]: Analyzing trace with hash 254679853, now seen corresponding path program 1 times [2022-02-21 04:24:20,493 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:20,493 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1358056253] [2022-02-21 04:24:20,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:20,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:20,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:20,527 INFO L290 TraceCheckUtils]: 0: Hoare triple {22351#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,527 INFO L290 TraceCheckUtils]: 1: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,527 INFO L290 TraceCheckUtils]: 2: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,528 INFO L290 TraceCheckUtils]: 3: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,528 INFO L290 TraceCheckUtils]: 4: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,528 INFO L290 TraceCheckUtils]: 5: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,529 INFO L290 TraceCheckUtils]: 6: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,529 INFO L290 TraceCheckUtils]: 7: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,529 INFO L290 TraceCheckUtils]: 8: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,529 INFO L290 TraceCheckUtils]: 9: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,530 INFO L290 TraceCheckUtils]: 10: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,530 INFO L290 TraceCheckUtils]: 11: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,530 INFO L290 TraceCheckUtils]: 12: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,530 INFO L290 TraceCheckUtils]: 13: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume !(0 == ~M_E~0); {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,531 INFO L290 TraceCheckUtils]: 14: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume !(0 == ~T1_E~0); {22353#(= ~T2_E~0 ~T6_E~0)} is VALID [2022-02-21 04:24:20,531 INFO L290 TraceCheckUtils]: 15: Hoare triple {22353#(= ~T2_E~0 ~T6_E~0)} assume !(0 == ~T2_E~0); {22354#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:24:20,531 INFO L290 TraceCheckUtils]: 16: Hoare triple {22354#(not (= ~T6_E~0 0))} assume !(0 == ~T3_E~0); {22354#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:24:20,531 INFO L290 TraceCheckUtils]: 17: Hoare triple {22354#(not (= ~T6_E~0 0))} assume !(0 == ~T4_E~0); {22354#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:24:20,532 INFO L290 TraceCheckUtils]: 18: Hoare triple {22354#(not (= ~T6_E~0 0))} assume !(0 == ~T5_E~0); {22354#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:24:20,532 INFO L290 TraceCheckUtils]: 19: Hoare triple {22354#(not (= ~T6_E~0 0))} assume 0 == ~T6_E~0;~T6_E~0 := 1; {22352#false} is VALID [2022-02-21 04:24:20,532 INFO L290 TraceCheckUtils]: 20: Hoare triple {22352#false} assume !(0 == ~T7_E~0); {22352#false} is VALID [2022-02-21 04:24:20,532 INFO L290 TraceCheckUtils]: 21: Hoare triple {22352#false} assume !(0 == ~E_1~0); {22352#false} is VALID [2022-02-21 04:24:20,532 INFO L290 TraceCheckUtils]: 22: Hoare triple {22352#false} assume !(0 == ~E_2~0); {22352#false} is VALID [2022-02-21 04:24:20,532 INFO L290 TraceCheckUtils]: 23: Hoare triple {22352#false} assume !(0 == ~E_3~0); {22352#false} is VALID [2022-02-21 04:24:20,532 INFO L290 TraceCheckUtils]: 24: Hoare triple {22352#false} assume !(0 == ~E_4~0); {22352#false} is VALID [2022-02-21 04:24:20,533 INFO L290 TraceCheckUtils]: 25: Hoare triple {22352#false} assume !(0 == ~E_5~0); {22352#false} is VALID [2022-02-21 04:24:20,533 INFO L290 TraceCheckUtils]: 26: Hoare triple {22352#false} assume !(0 == ~E_6~0); {22352#false} is VALID [2022-02-21 04:24:20,533 INFO L290 TraceCheckUtils]: 27: Hoare triple {22352#false} assume 0 == ~E_7~0;~E_7~0 := 1; {22352#false} is VALID [2022-02-21 04:24:20,533 INFO L290 TraceCheckUtils]: 28: Hoare triple {22352#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {22352#false} is VALID [2022-02-21 04:24:20,533 INFO L290 TraceCheckUtils]: 29: Hoare triple {22352#false} assume 1 == ~m_pc~0; {22352#false} is VALID [2022-02-21 04:24:20,533 INFO L290 TraceCheckUtils]: 30: Hoare triple {22352#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {22352#false} is VALID [2022-02-21 04:24:20,533 INFO L290 TraceCheckUtils]: 31: Hoare triple {22352#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {22352#false} is VALID [2022-02-21 04:24:20,533 INFO L290 TraceCheckUtils]: 32: Hoare triple {22352#false} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {22352#false} is VALID [2022-02-21 04:24:20,533 INFO L290 TraceCheckUtils]: 33: Hoare triple {22352#false} assume !(0 != activate_threads_~tmp~1#1); {22352#false} is VALID [2022-02-21 04:24:20,533 INFO L290 TraceCheckUtils]: 34: Hoare triple {22352#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {22352#false} is VALID [2022-02-21 04:24:20,534 INFO L290 TraceCheckUtils]: 35: Hoare triple {22352#false} assume !(1 == ~t1_pc~0); {22352#false} is VALID [2022-02-21 04:24:20,534 INFO L290 TraceCheckUtils]: 36: Hoare triple {22352#false} is_transmit1_triggered_~__retres1~1#1 := 0; {22352#false} is VALID [2022-02-21 04:24:20,534 INFO L290 TraceCheckUtils]: 37: Hoare triple {22352#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {22352#false} is VALID [2022-02-21 04:24:20,534 INFO L290 TraceCheckUtils]: 38: Hoare triple {22352#false} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {22352#false} is VALID [2022-02-21 04:24:20,534 INFO L290 TraceCheckUtils]: 39: Hoare triple {22352#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {22352#false} is VALID [2022-02-21 04:24:20,534 INFO L290 TraceCheckUtils]: 40: Hoare triple {22352#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {22352#false} is VALID [2022-02-21 04:24:20,534 INFO L290 TraceCheckUtils]: 41: Hoare triple {22352#false} assume 1 == ~t2_pc~0; {22352#false} is VALID [2022-02-21 04:24:20,534 INFO L290 TraceCheckUtils]: 42: Hoare triple {22352#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {22352#false} is VALID [2022-02-21 04:24:20,534 INFO L290 TraceCheckUtils]: 43: Hoare triple {22352#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {22352#false} is VALID [2022-02-21 04:24:20,534 INFO L290 TraceCheckUtils]: 44: Hoare triple {22352#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {22352#false} is VALID [2022-02-21 04:24:20,535 INFO L290 TraceCheckUtils]: 45: Hoare triple {22352#false} assume !(0 != activate_threads_~tmp___1~0#1); {22352#false} is VALID [2022-02-21 04:24:20,535 INFO L290 TraceCheckUtils]: 46: Hoare triple {22352#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {22352#false} is VALID [2022-02-21 04:24:20,535 INFO L290 TraceCheckUtils]: 47: Hoare triple {22352#false} assume !(1 == ~t3_pc~0); {22352#false} is VALID [2022-02-21 04:24:20,535 INFO L290 TraceCheckUtils]: 48: Hoare triple {22352#false} is_transmit3_triggered_~__retres1~3#1 := 0; {22352#false} is VALID [2022-02-21 04:24:20,535 INFO L290 TraceCheckUtils]: 49: Hoare triple {22352#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {22352#false} is VALID [2022-02-21 04:24:20,535 INFO L290 TraceCheckUtils]: 50: Hoare triple {22352#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {22352#false} is VALID [2022-02-21 04:24:20,535 INFO L290 TraceCheckUtils]: 51: Hoare triple {22352#false} assume !(0 != activate_threads_~tmp___2~0#1); {22352#false} is VALID [2022-02-21 04:24:20,535 INFO L290 TraceCheckUtils]: 52: Hoare triple {22352#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {22352#false} is VALID [2022-02-21 04:24:20,535 INFO L290 TraceCheckUtils]: 53: Hoare triple {22352#false} assume 1 == ~t4_pc~0; {22352#false} is VALID [2022-02-21 04:24:20,536 INFO L290 TraceCheckUtils]: 54: Hoare triple {22352#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {22352#false} is VALID [2022-02-21 04:24:20,536 INFO L290 TraceCheckUtils]: 55: Hoare triple {22352#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {22352#false} is VALID [2022-02-21 04:24:20,536 INFO L290 TraceCheckUtils]: 56: Hoare triple {22352#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {22352#false} is VALID [2022-02-21 04:24:20,536 INFO L290 TraceCheckUtils]: 57: Hoare triple {22352#false} assume !(0 != activate_threads_~tmp___3~0#1); {22352#false} is VALID [2022-02-21 04:24:20,536 INFO L290 TraceCheckUtils]: 58: Hoare triple {22352#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {22352#false} is VALID [2022-02-21 04:24:20,536 INFO L290 TraceCheckUtils]: 59: Hoare triple {22352#false} assume !(1 == ~t5_pc~0); {22352#false} is VALID [2022-02-21 04:24:20,536 INFO L290 TraceCheckUtils]: 60: Hoare triple {22352#false} is_transmit5_triggered_~__retres1~5#1 := 0; {22352#false} is VALID [2022-02-21 04:24:20,536 INFO L290 TraceCheckUtils]: 61: Hoare triple {22352#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {22352#false} is VALID [2022-02-21 04:24:20,536 INFO L290 TraceCheckUtils]: 62: Hoare triple {22352#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {22352#false} is VALID [2022-02-21 04:24:20,536 INFO L290 TraceCheckUtils]: 63: Hoare triple {22352#false} assume !(0 != activate_threads_~tmp___4~0#1); {22352#false} is VALID [2022-02-21 04:24:20,537 INFO L290 TraceCheckUtils]: 64: Hoare triple {22352#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {22352#false} is VALID [2022-02-21 04:24:20,537 INFO L290 TraceCheckUtils]: 65: Hoare triple {22352#false} assume 1 == ~t6_pc~0; {22352#false} is VALID [2022-02-21 04:24:20,537 INFO L290 TraceCheckUtils]: 66: Hoare triple {22352#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {22352#false} is VALID [2022-02-21 04:24:20,537 INFO L290 TraceCheckUtils]: 67: Hoare triple {22352#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {22352#false} is VALID [2022-02-21 04:24:20,537 INFO L290 TraceCheckUtils]: 68: Hoare triple {22352#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {22352#false} is VALID [2022-02-21 04:24:20,537 INFO L290 TraceCheckUtils]: 69: Hoare triple {22352#false} assume !(0 != activate_threads_~tmp___5~0#1); {22352#false} is VALID [2022-02-21 04:24:20,537 INFO L290 TraceCheckUtils]: 70: Hoare triple {22352#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {22352#false} is VALID [2022-02-21 04:24:20,537 INFO L290 TraceCheckUtils]: 71: Hoare triple {22352#false} assume 1 == ~t7_pc~0; {22352#false} is VALID [2022-02-21 04:24:20,537 INFO L290 TraceCheckUtils]: 72: Hoare triple {22352#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {22352#false} is VALID [2022-02-21 04:24:20,537 INFO L290 TraceCheckUtils]: 73: Hoare triple {22352#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {22352#false} is VALID [2022-02-21 04:24:20,538 INFO L290 TraceCheckUtils]: 74: Hoare triple {22352#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {22352#false} is VALID [2022-02-21 04:24:20,538 INFO L290 TraceCheckUtils]: 75: Hoare triple {22352#false} assume !(0 != activate_threads_~tmp___6~0#1); {22352#false} is VALID [2022-02-21 04:24:20,538 INFO L290 TraceCheckUtils]: 76: Hoare triple {22352#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {22352#false} is VALID [2022-02-21 04:24:20,538 INFO L290 TraceCheckUtils]: 77: Hoare triple {22352#false} assume !(1 == ~M_E~0); {22352#false} is VALID [2022-02-21 04:24:20,538 INFO L290 TraceCheckUtils]: 78: Hoare triple {22352#false} assume !(1 == ~T1_E~0); {22352#false} is VALID [2022-02-21 04:24:20,538 INFO L290 TraceCheckUtils]: 79: Hoare triple {22352#false} assume !(1 == ~T2_E~0); {22352#false} is VALID [2022-02-21 04:24:20,538 INFO L290 TraceCheckUtils]: 80: Hoare triple {22352#false} assume !(1 == ~T3_E~0); {22352#false} is VALID [2022-02-21 04:24:20,538 INFO L290 TraceCheckUtils]: 81: Hoare triple {22352#false} assume !(1 == ~T4_E~0); {22352#false} is VALID [2022-02-21 04:24:20,538 INFO L290 TraceCheckUtils]: 82: Hoare triple {22352#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {22352#false} is VALID [2022-02-21 04:24:20,538 INFO L290 TraceCheckUtils]: 83: Hoare triple {22352#false} assume !(1 == ~T6_E~0); {22352#false} is VALID [2022-02-21 04:24:20,539 INFO L290 TraceCheckUtils]: 84: Hoare triple {22352#false} assume !(1 == ~T7_E~0); {22352#false} is VALID [2022-02-21 04:24:20,539 INFO L290 TraceCheckUtils]: 85: Hoare triple {22352#false} assume !(1 == ~E_1~0); {22352#false} is VALID [2022-02-21 04:24:20,539 INFO L290 TraceCheckUtils]: 86: Hoare triple {22352#false} assume !(1 == ~E_2~0); {22352#false} is VALID [2022-02-21 04:24:20,539 INFO L290 TraceCheckUtils]: 87: Hoare triple {22352#false} assume !(1 == ~E_3~0); {22352#false} is VALID [2022-02-21 04:24:20,539 INFO L290 TraceCheckUtils]: 88: Hoare triple {22352#false} assume !(1 == ~E_4~0); {22352#false} is VALID [2022-02-21 04:24:20,539 INFO L290 TraceCheckUtils]: 89: Hoare triple {22352#false} assume !(1 == ~E_5~0); {22352#false} is VALID [2022-02-21 04:24:20,539 INFO L290 TraceCheckUtils]: 90: Hoare triple {22352#false} assume 1 == ~E_6~0;~E_6~0 := 2; {22352#false} is VALID [2022-02-21 04:24:20,539 INFO L290 TraceCheckUtils]: 91: Hoare triple {22352#false} assume !(1 == ~E_7~0); {22352#false} is VALID [2022-02-21 04:24:20,539 INFO L290 TraceCheckUtils]: 92: Hoare triple {22352#false} assume { :end_inline_reset_delta_events } true; {22352#false} is VALID [2022-02-21 04:24:20,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:20,540 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:20,540 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1358056253] [2022-02-21 04:24:20,540 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1358056253] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:20,541 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:20,541 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:20,541 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272620444] [2022-02-21 04:24:20,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:20,542 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:20,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:20,542 INFO L85 PathProgramCache]: Analyzing trace with hash 1561027463, now seen corresponding path program 2 times [2022-02-21 04:24:20,542 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:20,544 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2125135492] [2022-02-21 04:24:20,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:20,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:20,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:20,570 INFO L290 TraceCheckUtils]: 0: Hoare triple {22355#true} assume !false; {22355#true} is VALID [2022-02-21 04:24:20,570 INFO L290 TraceCheckUtils]: 1: Hoare triple {22355#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {22355#true} is VALID [2022-02-21 04:24:20,570 INFO L290 TraceCheckUtils]: 2: Hoare triple {22355#true} assume !false; {22355#true} is VALID [2022-02-21 04:24:20,570 INFO L290 TraceCheckUtils]: 3: Hoare triple {22355#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {22355#true} is VALID [2022-02-21 04:24:20,570 INFO L290 TraceCheckUtils]: 4: Hoare triple {22355#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {22355#true} is VALID [2022-02-21 04:24:20,570 INFO L290 TraceCheckUtils]: 5: Hoare triple {22355#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {22355#true} is VALID [2022-02-21 04:24:20,570 INFO L290 TraceCheckUtils]: 6: Hoare triple {22355#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {22355#true} is VALID [2022-02-21 04:24:20,570 INFO L290 TraceCheckUtils]: 7: Hoare triple {22355#true} assume !(0 != eval_~tmp~0#1); {22355#true} is VALID [2022-02-21 04:24:20,571 INFO L290 TraceCheckUtils]: 8: Hoare triple {22355#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {22355#true} is VALID [2022-02-21 04:24:20,571 INFO L290 TraceCheckUtils]: 9: Hoare triple {22355#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {22355#true} is VALID [2022-02-21 04:24:20,571 INFO L290 TraceCheckUtils]: 10: Hoare triple {22355#true} assume 0 == ~M_E~0;~M_E~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,571 INFO L290 TraceCheckUtils]: 11: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,572 INFO L290 TraceCheckUtils]: 12: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,572 INFO L290 TraceCheckUtils]: 13: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,572 INFO L290 TraceCheckUtils]: 14: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,572 INFO L290 TraceCheckUtils]: 15: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,573 INFO L290 TraceCheckUtils]: 16: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,573 INFO L290 TraceCheckUtils]: 17: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,573 INFO L290 TraceCheckUtils]: 18: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,573 INFO L290 TraceCheckUtils]: 19: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,574 INFO L290 TraceCheckUtils]: 20: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,574 INFO L290 TraceCheckUtils]: 21: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,574 INFO L290 TraceCheckUtils]: 22: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,574 INFO L290 TraceCheckUtils]: 23: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,575 INFO L290 TraceCheckUtils]: 24: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,575 INFO L290 TraceCheckUtils]: 25: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,575 INFO L290 TraceCheckUtils]: 26: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,575 INFO L290 TraceCheckUtils]: 27: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,576 INFO L290 TraceCheckUtils]: 28: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,576 INFO L290 TraceCheckUtils]: 29: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,576 INFO L290 TraceCheckUtils]: 30: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,577 INFO L290 TraceCheckUtils]: 31: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,577 INFO L290 TraceCheckUtils]: 32: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,577 INFO L290 TraceCheckUtils]: 33: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,577 INFO L290 TraceCheckUtils]: 34: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,578 INFO L290 TraceCheckUtils]: 35: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,578 INFO L290 TraceCheckUtils]: 36: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,578 INFO L290 TraceCheckUtils]: 37: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,578 INFO L290 TraceCheckUtils]: 38: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,579 INFO L290 TraceCheckUtils]: 39: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,579 INFO L290 TraceCheckUtils]: 40: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,579 INFO L290 TraceCheckUtils]: 41: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,579 INFO L290 TraceCheckUtils]: 42: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,580 INFO L290 TraceCheckUtils]: 43: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,580 INFO L290 TraceCheckUtils]: 44: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,580 INFO L290 TraceCheckUtils]: 45: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,580 INFO L290 TraceCheckUtils]: 46: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,581 INFO L290 TraceCheckUtils]: 47: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,581 INFO L290 TraceCheckUtils]: 48: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,581 INFO L290 TraceCheckUtils]: 49: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,581 INFO L290 TraceCheckUtils]: 50: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,582 INFO L290 TraceCheckUtils]: 51: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,582 INFO L290 TraceCheckUtils]: 52: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,582 INFO L290 TraceCheckUtils]: 53: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,583 INFO L290 TraceCheckUtils]: 54: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,583 INFO L290 TraceCheckUtils]: 55: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,583 INFO L290 TraceCheckUtils]: 56: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,583 INFO L290 TraceCheckUtils]: 57: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,584 INFO L290 TraceCheckUtils]: 58: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,584 INFO L290 TraceCheckUtils]: 59: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,584 INFO L290 TraceCheckUtils]: 60: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,584 INFO L290 TraceCheckUtils]: 61: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,585 INFO L290 TraceCheckUtils]: 62: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,585 INFO L290 TraceCheckUtils]: 63: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,585 INFO L290 TraceCheckUtils]: 64: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,585 INFO L290 TraceCheckUtils]: 65: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,586 INFO L290 TraceCheckUtils]: 66: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,586 INFO L290 TraceCheckUtils]: 67: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,586 INFO L290 TraceCheckUtils]: 68: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,586 INFO L290 TraceCheckUtils]: 69: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,587 INFO L290 TraceCheckUtils]: 70: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,587 INFO L290 TraceCheckUtils]: 71: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,587 INFO L290 TraceCheckUtils]: 72: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,588 INFO L290 TraceCheckUtils]: 73: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {22357#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:20,588 INFO L290 TraceCheckUtils]: 74: Hoare triple {22357#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {22356#false} is VALID [2022-02-21 04:24:20,588 INFO L290 TraceCheckUtils]: 75: Hoare triple {22356#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,588 INFO L290 TraceCheckUtils]: 76: Hoare triple {22356#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,588 INFO L290 TraceCheckUtils]: 77: Hoare triple {22356#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,588 INFO L290 TraceCheckUtils]: 78: Hoare triple {22356#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,588 INFO L290 TraceCheckUtils]: 79: Hoare triple {22356#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,589 INFO L290 TraceCheckUtils]: 80: Hoare triple {22356#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,589 INFO L290 TraceCheckUtils]: 81: Hoare triple {22356#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,589 INFO L290 TraceCheckUtils]: 82: Hoare triple {22356#false} assume !(1 == ~E_1~0); {22356#false} is VALID [2022-02-21 04:24:20,589 INFO L290 TraceCheckUtils]: 83: Hoare triple {22356#false} assume 1 == ~E_2~0;~E_2~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,589 INFO L290 TraceCheckUtils]: 84: Hoare triple {22356#false} assume 1 == ~E_3~0;~E_3~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,589 INFO L290 TraceCheckUtils]: 85: Hoare triple {22356#false} assume 1 == ~E_4~0;~E_4~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,589 INFO L290 TraceCheckUtils]: 86: Hoare triple {22356#false} assume 1 == ~E_5~0;~E_5~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,589 INFO L290 TraceCheckUtils]: 87: Hoare triple {22356#false} assume 1 == ~E_6~0;~E_6~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,589 INFO L290 TraceCheckUtils]: 88: Hoare triple {22356#false} assume 1 == ~E_7~0;~E_7~0 := 2; {22356#false} is VALID [2022-02-21 04:24:20,589 INFO L290 TraceCheckUtils]: 89: Hoare triple {22356#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {22356#false} is VALID [2022-02-21 04:24:20,590 INFO L290 TraceCheckUtils]: 90: Hoare triple {22356#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {22356#false} is VALID [2022-02-21 04:24:20,590 INFO L290 TraceCheckUtils]: 91: Hoare triple {22356#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {22356#false} is VALID [2022-02-21 04:24:20,590 INFO L290 TraceCheckUtils]: 92: Hoare triple {22356#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {22356#false} is VALID [2022-02-21 04:24:20,590 INFO L290 TraceCheckUtils]: 93: Hoare triple {22356#false} assume !(0 == start_simulation_~tmp~3#1); {22356#false} is VALID [2022-02-21 04:24:20,590 INFO L290 TraceCheckUtils]: 94: Hoare triple {22356#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {22356#false} is VALID [2022-02-21 04:24:20,590 INFO L290 TraceCheckUtils]: 95: Hoare triple {22356#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {22356#false} is VALID [2022-02-21 04:24:20,590 INFO L290 TraceCheckUtils]: 96: Hoare triple {22356#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {22356#false} is VALID [2022-02-21 04:24:20,590 INFO L290 TraceCheckUtils]: 97: Hoare triple {22356#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {22356#false} is VALID [2022-02-21 04:24:20,590 INFO L290 TraceCheckUtils]: 98: Hoare triple {22356#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {22356#false} is VALID [2022-02-21 04:24:20,590 INFO L290 TraceCheckUtils]: 99: Hoare triple {22356#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {22356#false} is VALID [2022-02-21 04:24:20,591 INFO L290 TraceCheckUtils]: 100: Hoare triple {22356#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {22356#false} is VALID [2022-02-21 04:24:20,591 INFO L290 TraceCheckUtils]: 101: Hoare triple {22356#false} assume !(0 != start_simulation_~tmp___0~1#1); {22356#false} is VALID [2022-02-21 04:24:20,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:20,591 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:20,593 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2125135492] [2022-02-21 04:24:20,594 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2125135492] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:20,594 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:20,594 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:20,594 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1773561297] [2022-02-21 04:24:20,594 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:20,594 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:20,595 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:20,595 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:20,595 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:20,595 INFO L87 Difference]: Start difference. First operand 768 states and 1142 transitions. cyclomatic complexity: 375 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:21,843 INFO L93 Difference]: Finished difference Result 1448 states and 2148 transitions. [2022-02-21 04:24:21,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:21,843 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,879 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:21,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1448 states and 2148 transitions. [2022-02-21 04:24:21,974 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-02-21 04:24:22,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1448 states to 1448 states and 2148 transitions. [2022-02-21 04:24:22,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1448 [2022-02-21 04:24:22,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1448 [2022-02-21 04:24:22,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1448 states and 2148 transitions. [2022-02-21 04:24:22,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:22,090 INFO L681 BuchiCegarLoop]: Abstraction has 1448 states and 2148 transitions. [2022-02-21 04:24:22,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1448 states and 2148 transitions. [2022-02-21 04:24:22,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1448 to 1448. [2022-02-21 04:24:22,122 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:22,124 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1448 states and 2148 transitions. Second operand has 1448 states, 1448 states have (on average 1.4834254143646408) internal successors, (2148), 1447 states have internal predecessors, (2148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,125 INFO L74 IsIncluded]: Start isIncluded. First operand 1448 states and 2148 transitions. Second operand has 1448 states, 1448 states have (on average 1.4834254143646408) internal successors, (2148), 1447 states have internal predecessors, (2148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,128 INFO L87 Difference]: Start difference. First operand 1448 states and 2148 transitions. Second operand has 1448 states, 1448 states have (on average 1.4834254143646408) internal successors, (2148), 1447 states have internal predecessors, (2148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,218 INFO L93 Difference]: Finished difference Result 1448 states and 2148 transitions. [2022-02-21 04:24:22,218 INFO L276 IsEmpty]: Start isEmpty. Operand 1448 states and 2148 transitions. [2022-02-21 04:24:22,221 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:22,235 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:22,237 INFO L74 IsIncluded]: Start isIncluded. First operand has 1448 states, 1448 states have (on average 1.4834254143646408) internal successors, (2148), 1447 states have internal predecessors, (2148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1448 states and 2148 transitions. [2022-02-21 04:24:22,239 INFO L87 Difference]: Start difference. First operand has 1448 states, 1448 states have (on average 1.4834254143646408) internal successors, (2148), 1447 states have internal predecessors, (2148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1448 states and 2148 transitions. [2022-02-21 04:24:22,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,335 INFO L93 Difference]: Finished difference Result 1448 states and 2148 transitions. [2022-02-21 04:24:22,335 INFO L276 IsEmpty]: Start isEmpty. Operand 1448 states and 2148 transitions. [2022-02-21 04:24:22,341 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:22,341 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:22,341 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:22,342 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:22,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1448 states, 1448 states have (on average 1.4834254143646408) internal successors, (2148), 1447 states have internal predecessors, (2148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 2148 transitions. [2022-02-21 04:24:22,461 INFO L704 BuchiCegarLoop]: Abstraction has 1448 states and 2148 transitions. [2022-02-21 04:24:22,461 INFO L587 BuchiCegarLoop]: Abstraction has 1448 states and 2148 transitions. [2022-02-21 04:24:22,461 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:22,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1448 states and 2148 transitions. [2022-02-21 04:24:22,465 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-02-21 04:24:22,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:22,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:22,466 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,466 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,467 INFO L791 eck$LassoCheckResult]: Stem: 24605#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 24577#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 24578#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24017#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24018#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 24443#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24444#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24412#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24333#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24334#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24323#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24324#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24279#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24280#L754 assume !(0 == ~M_E~0); 24553#L754-2 assume !(0 == ~T1_E~0); 24220#L759-1 assume !(0 == ~T2_E~0); 24221#L764-1 assume !(0 == ~T3_E~0); 24587#L769-1 assume !(0 == ~T4_E~0); 24588#L774-1 assume !(0 == ~T5_E~0); 24476#L779-1 assume !(0 == ~T6_E~0); 24251#L784-1 assume !(0 == ~T7_E~0); 24252#L789-1 assume !(0 == ~E_1~0); 23928#L794-1 assume !(0 == ~E_2~0); 23929#L799-1 assume !(0 == ~E_3~0); 24590#L804-1 assume !(0 == ~E_4~0); 24591#L809-1 assume !(0 == ~E_5~0); 24337#L814-1 assume !(0 == ~E_6~0); 23846#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 23847#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24319#L361 assume 1 == ~m_pc~0; 24320#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24362#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24135#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 24136#L930 assume !(0 != activate_threads_~tmp~1#1); 24471#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24311#L380 assume !(1 == ~t1_pc~0); 23980#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23979#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24497#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24582#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24056#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23981#L399 assume 1 == ~t2_pc~0; 23982#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24189#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24507#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24383#L946 assume !(0 != activate_threads_~tmp___1~0#1); 23884#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23855#L418 assume !(1 == ~t3_pc~0); 23813#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23814#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24341#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24562#L954 assume !(0 != activate_threads_~tmp___2~0#1); 24598#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24556#L437 assume 1 == ~t4_pc~0; 24557#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24157#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23984#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23985#L962 assume !(0 != activate_threads_~tmp___3~0#1); 24422#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24112#L456 assume !(1 == ~t5_pc~0); 24113#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24217#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24531#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23874#L970 assume !(0 != activate_threads_~tmp___4~0#1); 23875#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24000#L475 assume 1 == ~t6_pc~0; 24001#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24076#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24077#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23834#L978 assume !(0 != activate_threads_~tmp___5~0#1); 23835#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24326#L494 assume 1 == ~t7_pc~0; 24327#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24368#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24526#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24527#L986 assume !(0 != activate_threads_~tmp___6~0#1); 24603#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24528#L837 assume !(1 == ~M_E~0); 24386#L837-2 assume !(1 == ~T1_E~0); 23962#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23963#L847-1 assume !(1 == ~T3_E~0); 24439#L852-1 assume !(1 == ~T4_E~0); 24521#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24395#L862-1 assume !(1 == ~T6_E~0); 24396#L867-1 assume !(1 == ~T7_E~0); 24405#L872-1 assume !(1 == ~E_1~0); 24473#L877-1 assume !(1 == ~E_2~0); 24401#L882-1 assume !(1 == ~E_3~0); 24402#L887-1 assume !(1 == ~E_4~0); 24023#L892-1 assume !(1 == ~E_5~0); 24024#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 24634#L902-1 assume !(1 == ~E_7~0); 24632#L907-1 assume { :end_inline_reset_delta_events } true; 24464#L1148-2 [2022-02-21 04:24:22,467 INFO L793 eck$LassoCheckResult]: Loop: 24464#L1148-2 assume !false; 23848#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23849#L729 assume !false; 24248#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 24244#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 24195#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 24614#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24612#L626 assume !(0 != eval_~tmp~0#1); 24611#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24610#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24609#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24608#L754-5 assume !(0 == ~T1_E~0); 24607#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24453#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24449#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24450#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24200#L779-3 assume !(0 == ~T6_E~0); 23861#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23862#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23844#L794-3 assume !(0 == ~E_2~0); 23845#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23944#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24349#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23939#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23940#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24138#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24139#L361-24 assume 1 == ~m_pc~0; 24176#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24177#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23856#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23857#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24342#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24408#L380-24 assume !(1 == ~t1_pc~0); 24025#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 24026#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24469#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24338#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23986#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23987#L399-24 assume 1 == ~t2_pc~0; 24201#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24250#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24027#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24028#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24330#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24331#L418-24 assume !(1 == ~t3_pc~0); 23932#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 23933#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24332#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24205#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23876#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23877#L437-24 assume 1 == ~t4_pc~0; 24150#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24151#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24029#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24030#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24179#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24499#L456-24 assume 1 == ~t5_pc~0; 24500#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24568#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24242#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24243#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24390#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24529#L475-24 assume 1 == ~t6_pc~0; 23878#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23879#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24539#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24540#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 23821#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23822#L494-24 assume !(1 == ~t7_pc~0); 24400#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 24381#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24270#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24271#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24148#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24149#L837-3 assume !(1 == ~M_E~0); 24232#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24525#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24436#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23865#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23866#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24572#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24564#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24491#L872-3 assume !(1 == ~E_1~0); 24492#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24567#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24585#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24235#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24230#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24231#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24413#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 24406#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 23851#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 24600#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 24550#L1167 assume !(0 == start_simulation_~tmp~3#1); 24437#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 24466#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 24261#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 24506#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 24542#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24451#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23827#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 23828#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 24464#L1148-2 [2022-02-21 04:24:22,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:22,468 INFO L85 PathProgramCache]: Analyzing trace with hash -2141947347, now seen corresponding path program 1 times [2022-02-21 04:24:22,468 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:22,468 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236007603] [2022-02-21 04:24:22,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:22,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:22,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:22,522 INFO L290 TraceCheckUtils]: 0: Hoare triple {28155#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,522 INFO L290 TraceCheckUtils]: 1: Hoare triple {28157#(<= 2 ~E_7~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,523 INFO L290 TraceCheckUtils]: 2: Hoare triple {28157#(<= 2 ~E_7~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,523 INFO L290 TraceCheckUtils]: 3: Hoare triple {28157#(<= 2 ~E_7~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,523 INFO L290 TraceCheckUtils]: 4: Hoare triple {28157#(<= 2 ~E_7~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,523 INFO L290 TraceCheckUtils]: 5: Hoare triple {28157#(<= 2 ~E_7~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,523 INFO L290 TraceCheckUtils]: 6: Hoare triple {28157#(<= 2 ~E_7~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,524 INFO L290 TraceCheckUtils]: 7: Hoare triple {28157#(<= 2 ~E_7~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,524 INFO L290 TraceCheckUtils]: 8: Hoare triple {28157#(<= 2 ~E_7~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,524 INFO L290 TraceCheckUtils]: 9: Hoare triple {28157#(<= 2 ~E_7~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,524 INFO L290 TraceCheckUtils]: 10: Hoare triple {28157#(<= 2 ~E_7~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,525 INFO L290 TraceCheckUtils]: 11: Hoare triple {28157#(<= 2 ~E_7~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,525 INFO L290 TraceCheckUtils]: 12: Hoare triple {28157#(<= 2 ~E_7~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,525 INFO L290 TraceCheckUtils]: 13: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~M_E~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,525 INFO L290 TraceCheckUtils]: 14: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~T1_E~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,526 INFO L290 TraceCheckUtils]: 15: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~T2_E~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,526 INFO L290 TraceCheckUtils]: 16: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~T3_E~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,526 INFO L290 TraceCheckUtils]: 17: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~T4_E~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,526 INFO L290 TraceCheckUtils]: 18: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~T5_E~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,526 INFO L290 TraceCheckUtils]: 19: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~T6_E~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,527 INFO L290 TraceCheckUtils]: 20: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~T7_E~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,527 INFO L290 TraceCheckUtils]: 21: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~E_1~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,527 INFO L290 TraceCheckUtils]: 22: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~E_2~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,527 INFO L290 TraceCheckUtils]: 23: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~E_3~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,528 INFO L290 TraceCheckUtils]: 24: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~E_4~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,529 INFO L290 TraceCheckUtils]: 25: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~E_5~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,529 INFO L290 TraceCheckUtils]: 26: Hoare triple {28157#(<= 2 ~E_7~0)} assume !(0 == ~E_6~0); {28157#(<= 2 ~E_7~0)} is VALID [2022-02-21 04:24:22,530 INFO L290 TraceCheckUtils]: 27: Hoare triple {28157#(<= 2 ~E_7~0)} assume 0 == ~E_7~0;~E_7~0 := 1; {28156#false} is VALID [2022-02-21 04:24:22,530 INFO L290 TraceCheckUtils]: 28: Hoare triple {28156#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28156#false} is VALID [2022-02-21 04:24:22,530 INFO L290 TraceCheckUtils]: 29: Hoare triple {28156#false} assume 1 == ~m_pc~0; {28156#false} is VALID [2022-02-21 04:24:22,530 INFO L290 TraceCheckUtils]: 30: Hoare triple {28156#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {28156#false} is VALID [2022-02-21 04:24:22,530 INFO L290 TraceCheckUtils]: 31: Hoare triple {28156#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28156#false} is VALID [2022-02-21 04:24:22,530 INFO L290 TraceCheckUtils]: 32: Hoare triple {28156#false} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {28156#false} is VALID [2022-02-21 04:24:22,530 INFO L290 TraceCheckUtils]: 33: Hoare triple {28156#false} assume !(0 != activate_threads_~tmp~1#1); {28156#false} is VALID [2022-02-21 04:24:22,530 INFO L290 TraceCheckUtils]: 34: Hoare triple {28156#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28156#false} is VALID [2022-02-21 04:24:22,530 INFO L290 TraceCheckUtils]: 35: Hoare triple {28156#false} assume !(1 == ~t1_pc~0); {28156#false} is VALID [2022-02-21 04:24:22,531 INFO L290 TraceCheckUtils]: 36: Hoare triple {28156#false} is_transmit1_triggered_~__retres1~1#1 := 0; {28156#false} is VALID [2022-02-21 04:24:22,543 INFO L290 TraceCheckUtils]: 37: Hoare triple {28156#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28156#false} is VALID [2022-02-21 04:24:22,543 INFO L290 TraceCheckUtils]: 38: Hoare triple {28156#false} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {28156#false} is VALID [2022-02-21 04:24:22,543 INFO L290 TraceCheckUtils]: 39: Hoare triple {28156#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {28156#false} is VALID [2022-02-21 04:24:22,543 INFO L290 TraceCheckUtils]: 40: Hoare triple {28156#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28156#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 41: Hoare triple {28156#false} assume 1 == ~t2_pc~0; {28156#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 42: Hoare triple {28156#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {28156#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 43: Hoare triple {28156#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28156#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 44: Hoare triple {28156#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {28156#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 45: Hoare triple {28156#false} assume !(0 != activate_threads_~tmp___1~0#1); {28156#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 46: Hoare triple {28156#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28156#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 47: Hoare triple {28156#false} assume !(1 == ~t3_pc~0); {28156#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 48: Hoare triple {28156#false} is_transmit3_triggered_~__retres1~3#1 := 0; {28156#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 49: Hoare triple {28156#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28156#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 50: Hoare triple {28156#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {28156#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 51: Hoare triple {28156#false} assume !(0 != activate_threads_~tmp___2~0#1); {28156#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 52: Hoare triple {28156#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28156#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 53: Hoare triple {28156#false} assume 1 == ~t4_pc~0; {28156#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 54: Hoare triple {28156#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {28156#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 55: Hoare triple {28156#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28156#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 56: Hoare triple {28156#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {28156#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 57: Hoare triple {28156#false} assume !(0 != activate_threads_~tmp___3~0#1); {28156#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 58: Hoare triple {28156#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {28156#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 59: Hoare triple {28156#false} assume !(1 == ~t5_pc~0); {28156#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 60: Hoare triple {28156#false} is_transmit5_triggered_~__retres1~5#1 := 0; {28156#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 61: Hoare triple {28156#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {28156#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 62: Hoare triple {28156#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {28156#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 63: Hoare triple {28156#false} assume !(0 != activate_threads_~tmp___4~0#1); {28156#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 64: Hoare triple {28156#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {28156#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 65: Hoare triple {28156#false} assume 1 == ~t6_pc~0; {28156#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 66: Hoare triple {28156#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {28156#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 67: Hoare triple {28156#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {28156#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 68: Hoare triple {28156#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {28156#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 69: Hoare triple {28156#false} assume !(0 != activate_threads_~tmp___5~0#1); {28156#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 70: Hoare triple {28156#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {28156#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 71: Hoare triple {28156#false} assume 1 == ~t7_pc~0; {28156#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 72: Hoare triple {28156#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {28156#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 73: Hoare triple {28156#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {28156#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 74: Hoare triple {28156#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {28156#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 75: Hoare triple {28156#false} assume !(0 != activate_threads_~tmp___6~0#1); {28156#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 76: Hoare triple {28156#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28156#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 77: Hoare triple {28156#false} assume !(1 == ~M_E~0); {28156#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 78: Hoare triple {28156#false} assume !(1 == ~T1_E~0); {28156#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 79: Hoare triple {28156#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {28156#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 80: Hoare triple {28156#false} assume !(1 == ~T3_E~0); {28156#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 81: Hoare triple {28156#false} assume !(1 == ~T4_E~0); {28156#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 82: Hoare triple {28156#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {28156#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 83: Hoare triple {28156#false} assume !(1 == ~T6_E~0); {28156#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 84: Hoare triple {28156#false} assume !(1 == ~T7_E~0); {28156#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 85: Hoare triple {28156#false} assume !(1 == ~E_1~0); {28156#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 86: Hoare triple {28156#false} assume !(1 == ~E_2~0); {28156#false} is VALID [2022-02-21 04:24:22,549 INFO L290 TraceCheckUtils]: 87: Hoare triple {28156#false} assume !(1 == ~E_3~0); {28156#false} is VALID [2022-02-21 04:24:22,549 INFO L290 TraceCheckUtils]: 88: Hoare triple {28156#false} assume !(1 == ~E_4~0); {28156#false} is VALID [2022-02-21 04:24:22,549 INFO L290 TraceCheckUtils]: 89: Hoare triple {28156#false} assume !(1 == ~E_5~0); {28156#false} is VALID [2022-02-21 04:24:22,549 INFO L290 TraceCheckUtils]: 90: Hoare triple {28156#false} assume 1 == ~E_6~0;~E_6~0 := 2; {28156#false} is VALID [2022-02-21 04:24:22,549 INFO L290 TraceCheckUtils]: 91: Hoare triple {28156#false} assume !(1 == ~E_7~0); {28156#false} is VALID [2022-02-21 04:24:22,549 INFO L290 TraceCheckUtils]: 92: Hoare triple {28156#false} assume { :end_inline_reset_delta_events } true; {28156#false} is VALID [2022-02-21 04:24:22,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:22,550 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:22,550 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236007603] [2022-02-21 04:24:22,550 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236007603] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:22,550 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:22,550 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:22,550 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312578824] [2022-02-21 04:24:22,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:22,551 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:22,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:22,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1539194716, now seen corresponding path program 1 times [2022-02-21 04:24:22,551 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:22,551 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309684629] [2022-02-21 04:24:22,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:22,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:22,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:22,597 INFO L290 TraceCheckUtils]: 0: Hoare triple {28158#true} assume !false; {28158#true} is VALID [2022-02-21 04:24:22,597 INFO L290 TraceCheckUtils]: 1: Hoare triple {28158#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {28158#true} is VALID [2022-02-21 04:24:22,597 INFO L290 TraceCheckUtils]: 2: Hoare triple {28158#true} assume !false; {28158#true} is VALID [2022-02-21 04:24:22,597 INFO L290 TraceCheckUtils]: 3: Hoare triple {28158#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {28158#true} is VALID [2022-02-21 04:24:22,597 INFO L290 TraceCheckUtils]: 4: Hoare triple {28158#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {28158#true} is VALID [2022-02-21 04:24:22,597 INFO L290 TraceCheckUtils]: 5: Hoare triple {28158#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {28158#true} is VALID [2022-02-21 04:24:22,597 INFO L290 TraceCheckUtils]: 6: Hoare triple {28158#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {28158#true} is VALID [2022-02-21 04:24:22,597 INFO L290 TraceCheckUtils]: 7: Hoare triple {28158#true} assume !(0 != eval_~tmp~0#1); {28158#true} is VALID [2022-02-21 04:24:22,597 INFO L290 TraceCheckUtils]: 8: Hoare triple {28158#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {28158#true} is VALID [2022-02-21 04:24:22,597 INFO L290 TraceCheckUtils]: 9: Hoare triple {28158#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {28158#true} is VALID [2022-02-21 04:24:22,598 INFO L290 TraceCheckUtils]: 10: Hoare triple {28158#true} assume 0 == ~M_E~0;~M_E~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,598 INFO L290 TraceCheckUtils]: 11: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,598 INFO L290 TraceCheckUtils]: 12: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,598 INFO L290 TraceCheckUtils]: 13: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,599 INFO L290 TraceCheckUtils]: 14: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,599 INFO L290 TraceCheckUtils]: 15: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,599 INFO L290 TraceCheckUtils]: 16: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T6_E~0); {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,599 INFO L290 TraceCheckUtils]: 17: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,600 INFO L290 TraceCheckUtils]: 18: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,600 INFO L290 TraceCheckUtils]: 19: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,600 INFO L290 TraceCheckUtils]: 20: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,600 INFO L290 TraceCheckUtils]: 21: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,600 INFO L290 TraceCheckUtils]: 22: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,601 INFO L290 TraceCheckUtils]: 23: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,601 INFO L290 TraceCheckUtils]: 24: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,601 INFO L290 TraceCheckUtils]: 25: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,601 INFO L290 TraceCheckUtils]: 26: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,602 INFO L290 TraceCheckUtils]: 27: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,602 INFO L290 TraceCheckUtils]: 28: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,602 INFO L290 TraceCheckUtils]: 29: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,602 INFO L290 TraceCheckUtils]: 30: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,603 INFO L290 TraceCheckUtils]: 31: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,603 INFO L290 TraceCheckUtils]: 32: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,603 INFO L290 TraceCheckUtils]: 33: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,603 INFO L290 TraceCheckUtils]: 34: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,604 INFO L290 TraceCheckUtils]: 35: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,604 INFO L290 TraceCheckUtils]: 36: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,604 INFO L290 TraceCheckUtils]: 37: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,604 INFO L290 TraceCheckUtils]: 38: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,604 INFO L290 TraceCheckUtils]: 39: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,605 INFO L290 TraceCheckUtils]: 40: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,605 INFO L290 TraceCheckUtils]: 41: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,605 INFO L290 TraceCheckUtils]: 42: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,605 INFO L290 TraceCheckUtils]: 43: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,606 INFO L290 TraceCheckUtils]: 44: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,606 INFO L290 TraceCheckUtils]: 45: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,606 INFO L290 TraceCheckUtils]: 46: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,606 INFO L290 TraceCheckUtils]: 47: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,607 INFO L290 TraceCheckUtils]: 48: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,607 INFO L290 TraceCheckUtils]: 49: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,607 INFO L290 TraceCheckUtils]: 50: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,607 INFO L290 TraceCheckUtils]: 51: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,607 INFO L290 TraceCheckUtils]: 52: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,608 INFO L290 TraceCheckUtils]: 53: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,608 INFO L290 TraceCheckUtils]: 54: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,608 INFO L290 TraceCheckUtils]: 55: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,608 INFO L290 TraceCheckUtils]: 56: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,609 INFO L290 TraceCheckUtils]: 57: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,609 INFO L290 TraceCheckUtils]: 58: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,609 INFO L290 TraceCheckUtils]: 59: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,609 INFO L290 TraceCheckUtils]: 60: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,610 INFO L290 TraceCheckUtils]: 61: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,610 INFO L290 TraceCheckUtils]: 62: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,610 INFO L290 TraceCheckUtils]: 63: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,610 INFO L290 TraceCheckUtils]: 64: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,610 INFO L290 TraceCheckUtils]: 65: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,611 INFO L290 TraceCheckUtils]: 66: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,611 INFO L290 TraceCheckUtils]: 67: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,611 INFO L290 TraceCheckUtils]: 68: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,611 INFO L290 TraceCheckUtils]: 69: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,612 INFO L290 TraceCheckUtils]: 70: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,612 INFO L290 TraceCheckUtils]: 71: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,612 INFO L290 TraceCheckUtils]: 72: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,612 INFO L290 TraceCheckUtils]: 73: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28160#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 74: Hoare triple {28160#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {28159#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 75: Hoare triple {28159#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 76: Hoare triple {28159#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 77: Hoare triple {28159#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 78: Hoare triple {28159#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 79: Hoare triple {28159#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 80: Hoare triple {28159#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 81: Hoare triple {28159#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 82: Hoare triple {28159#false} assume !(1 == ~E_1~0); {28159#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 83: Hoare triple {28159#false} assume 1 == ~E_2~0;~E_2~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 84: Hoare triple {28159#false} assume 1 == ~E_3~0;~E_3~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 85: Hoare triple {28159#false} assume 1 == ~E_4~0;~E_4~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 86: Hoare triple {28159#false} assume 1 == ~E_5~0;~E_5~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 87: Hoare triple {28159#false} assume 1 == ~E_6~0;~E_6~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 88: Hoare triple {28159#false} assume 1 == ~E_7~0;~E_7~0 := 2; {28159#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 89: Hoare triple {28159#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {28159#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 90: Hoare triple {28159#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {28159#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 91: Hoare triple {28159#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {28159#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 92: Hoare triple {28159#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {28159#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 93: Hoare triple {28159#false} assume !(0 == start_simulation_~tmp~3#1); {28159#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 94: Hoare triple {28159#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {28159#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 95: Hoare triple {28159#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {28159#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 96: Hoare triple {28159#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {28159#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 97: Hoare triple {28159#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {28159#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 98: Hoare triple {28159#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {28159#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 99: Hoare triple {28159#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {28159#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 100: Hoare triple {28159#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {28159#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 101: Hoare triple {28159#false} assume !(0 != start_simulation_~tmp___0~1#1); {28159#false} is VALID [2022-02-21 04:24:22,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:22,616 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:22,616 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309684629] [2022-02-21 04:24:22,616 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [309684629] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:22,616 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:22,616 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:22,622 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [848012230] [2022-02-21 04:24:22,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:22,622 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:22,623 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:22,623 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:22,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:22,624 INFO L87 Difference]: Start difference. First operand 1448 states and 2148 transitions. cyclomatic complexity: 702 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,121 INFO L93 Difference]: Finished difference Result 1448 states and 2122 transitions. [2022-02-21 04:24:23,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:23,122 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,158 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:23,158 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1448 states and 2122 transitions. [2022-02-21 04:24:23,266 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-02-21 04:24:23,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1448 states to 1448 states and 2122 transitions. [2022-02-21 04:24:23,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1448 [2022-02-21 04:24:23,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1448 [2022-02-21 04:24:23,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1448 states and 2122 transitions. [2022-02-21 04:24:23,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:23,369 INFO L681 BuchiCegarLoop]: Abstraction has 1448 states and 2122 transitions. [2022-02-21 04:24:23,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1448 states and 2122 transitions. [2022-02-21 04:24:23,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1448 to 1448. [2022-02-21 04:24:23,394 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:23,396 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1448 states and 2122 transitions. Second operand has 1448 states, 1448 states have (on average 1.4654696132596685) internal successors, (2122), 1447 states have internal predecessors, (2122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,397 INFO L74 IsIncluded]: Start isIncluded. First operand 1448 states and 2122 transitions. Second operand has 1448 states, 1448 states have (on average 1.4654696132596685) internal successors, (2122), 1447 states have internal predecessors, (2122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,398 INFO L87 Difference]: Start difference. First operand 1448 states and 2122 transitions. Second operand has 1448 states, 1448 states have (on average 1.4654696132596685) internal successors, (2122), 1447 states have internal predecessors, (2122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,491 INFO L93 Difference]: Finished difference Result 1448 states and 2122 transitions. [2022-02-21 04:24:23,492 INFO L276 IsEmpty]: Start isEmpty. Operand 1448 states and 2122 transitions. [2022-02-21 04:24:23,493 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:23,493 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:23,495 INFO L74 IsIncluded]: Start isIncluded. First operand has 1448 states, 1448 states have (on average 1.4654696132596685) internal successors, (2122), 1447 states have internal predecessors, (2122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1448 states and 2122 transitions. [2022-02-21 04:24:23,496 INFO L87 Difference]: Start difference. First operand has 1448 states, 1448 states have (on average 1.4654696132596685) internal successors, (2122), 1447 states have internal predecessors, (2122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1448 states and 2122 transitions. [2022-02-21 04:24:23,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,593 INFO L93 Difference]: Finished difference Result 1448 states and 2122 transitions. [2022-02-21 04:24:23,593 INFO L276 IsEmpty]: Start isEmpty. Operand 1448 states and 2122 transitions. [2022-02-21 04:24:23,594 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:23,595 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:23,595 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:23,595 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:23,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1448 states, 1448 states have (on average 1.4654696132596685) internal successors, (2122), 1447 states have internal predecessors, (2122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 2122 transitions. [2022-02-21 04:24:23,693 INFO L704 BuchiCegarLoop]: Abstraction has 1448 states and 2122 transitions. [2022-02-21 04:24:23,693 INFO L587 BuchiCegarLoop]: Abstraction has 1448 states and 2122 transitions. [2022-02-21 04:24:23,693 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:24:23,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1448 states and 2122 transitions. [2022-02-21 04:24:23,697 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1334 [2022-02-21 04:24:23,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:23,712 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:23,713 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,713 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,713 INFO L791 eck$LassoCheckResult]: Stem: 30421#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 30390#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 30391#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29816#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29817#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 30244#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30245#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30211#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30130#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30131#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30120#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30121#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30077#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30078#L754 assume !(0 == ~M_E~0); 30365#L754-2 assume !(0 == ~T1_E~0); 30017#L759-1 assume !(0 == ~T2_E~0); 30018#L764-1 assume !(0 == ~T3_E~0); 30402#L769-1 assume !(0 == ~T4_E~0); 30403#L774-1 assume !(0 == ~T5_E~0); 30283#L779-1 assume !(0 == ~T6_E~0); 30049#L784-1 assume !(0 == ~T7_E~0); 30050#L789-1 assume !(0 == ~E_1~0); 29729#L794-1 assume !(0 == ~E_2~0); 29730#L799-1 assume !(0 == ~E_3~0); 30406#L804-1 assume !(0 == ~E_4~0); 30407#L809-1 assume !(0 == ~E_5~0); 30134#L814-1 assume !(0 == ~E_6~0); 29645#L819-1 assume !(0 == ~E_7~0); 29646#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30116#L361 assume 1 == ~m_pc~0; 30117#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30159#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29934#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29935#L930 assume !(0 != activate_threads_~tmp~1#1); 30277#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30109#L380 assume !(1 == ~t1_pc~0); 29780#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29779#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30304#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30396#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29855#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29781#L399 assume 1 == ~t2_pc~0; 29782#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29986#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30316#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30180#L946 assume !(0 != activate_threads_~tmp___1~0#1); 29685#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29653#L418 assume !(1 == ~t3_pc~0); 29614#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29615#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30138#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30374#L954 assume !(0 != activate_threads_~tmp___2~0#1); 30414#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30366#L437 assume 1 == ~t4_pc~0; 30367#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29955#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29784#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29785#L962 assume !(0 != activate_threads_~tmp___3~0#1); 30221#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29911#L456 assume !(1 == ~t5_pc~0); 29912#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30014#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30343#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29675#L970 assume !(0 != activate_threads_~tmp___4~0#1); 29676#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29800#L475 assume 1 == ~t6_pc~0; 29801#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29875#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29876#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29635#L978 assume !(0 != activate_threads_~tmp___5~0#1); 29636#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30123#L494 assume !(1 == ~t7_pc~0); 30125#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 30165#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30338#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30339#L986 assume !(0 != activate_threads_~tmp___6~0#1); 30418#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30340#L837 assume !(1 == ~M_E~0); 30183#L837-2 assume !(1 == ~T1_E~0); 29762#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29763#L847-1 assume !(1 == ~T3_E~0); 30331#L852-1 assume !(1 == ~T4_E~0); 30332#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30192#L862-1 assume !(1 == ~T6_E~0); 30193#L867-1 assume !(1 == ~T7_E~0); 30202#L872-1 assume !(1 == ~E_1~0); 30280#L877-1 assume !(1 == ~E_2~0); 30198#L882-1 assume !(1 == ~E_3~0); 30199#L887-1 assume !(1 == ~E_4~0); 29822#L892-1 assume !(1 == ~E_5~0); 29823#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 30458#L902-1 assume !(1 == ~E_7~0); 30447#L907-1 assume { :end_inline_reset_delta_events } true; 30267#L1148-2 [2022-02-21 04:24:23,713 INFO L793 eck$LassoCheckResult]: Loop: 30267#L1148-2 assume !false; 29647#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29648#L729 assume !false; 30046#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30042#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 29992#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30429#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30427#L626 assume !(0 != eval_~tmp~0#1); 30426#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30425#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30424#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30423#L754-5 assume !(0 == ~T1_E~0); 30422#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30259#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30252#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30253#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30002#L779-3 assume !(0 == ~T6_E~0); 29664#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29665#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29649#L794-3 assume !(0 == ~E_2~0); 29650#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29744#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30146#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29739#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29740#L819-3 assume !(0 == ~E_7~0); 29940#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29941#L361-24 assume 1 == ~m_pc~0; 29974#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29975#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29657#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29658#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30139#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30204#L380-24 assume !(1 == ~t1_pc~0); 29824#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 29825#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30274#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30135#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29786#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29787#L399-24 assume 1 == ~t2_pc~0; 29997#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30048#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29826#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29827#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30127#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30128#L418-24 assume 1 == ~t3_pc~0; 30132#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29734#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30129#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30001#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29677#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29678#L437-24 assume 1 == ~t4_pc~0; 29949#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29950#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29828#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29829#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29977#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30306#L456-24 assume 1 == ~t5_pc~0; 30307#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30380#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30040#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30041#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30187#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30342#L475-24 assume !(1 == ~t6_pc~0); 29681#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 29680#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30352#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30353#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 29620#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29621#L494-24 assume !(1 == ~t7_pc~0); 30197#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 30176#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30069#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30070#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29947#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29948#L837-3 assume !(1 == ~M_E~0); 30030#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30843#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30337#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30840#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30838#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30836#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30412#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30832#L872-3 assume !(1 == ~E_1~0); 30830#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30828#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30826#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30824#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30821#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30819#L902-3 assume !(1 == ~E_7~0); 30817#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30549#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30541#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30539#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 30536#L1167 assume !(0 == start_simulation_~tmp~3#1); 30533#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 30508#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 30314#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 30315#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 30355#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30451#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30449#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 30448#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 30267#L1148-2 [2022-02-21 04:24:23,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:23,714 INFO L85 PathProgramCache]: Analyzing trace with hash 1307665866, now seen corresponding path program 1 times [2022-02-21 04:24:23,714 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:23,714 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966996578] [2022-02-21 04:24:23,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:23,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:23,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:23,746 INFO L290 TraceCheckUtils]: 0: Hoare triple {33956#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,747 INFO L290 TraceCheckUtils]: 1: Hoare triple {33958#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,747 INFO L290 TraceCheckUtils]: 2: Hoare triple {33958#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,747 INFO L290 TraceCheckUtils]: 3: Hoare triple {33958#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,748 INFO L290 TraceCheckUtils]: 4: Hoare triple {33958#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,748 INFO L290 TraceCheckUtils]: 5: Hoare triple {33958#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,748 INFO L290 TraceCheckUtils]: 6: Hoare triple {33958#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,748 INFO L290 TraceCheckUtils]: 7: Hoare triple {33958#(= ~m_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,748 INFO L290 TraceCheckUtils]: 8: Hoare triple {33958#(= ~m_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,749 INFO L290 TraceCheckUtils]: 9: Hoare triple {33958#(= ~m_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,749 INFO L290 TraceCheckUtils]: 10: Hoare triple {33958#(= ~m_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,749 INFO L290 TraceCheckUtils]: 11: Hoare triple {33958#(= ~m_pc~0 0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,749 INFO L290 TraceCheckUtils]: 12: Hoare triple {33958#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,750 INFO L290 TraceCheckUtils]: 13: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,750 INFO L290 TraceCheckUtils]: 14: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,750 INFO L290 TraceCheckUtils]: 15: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,750 INFO L290 TraceCheckUtils]: 16: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~T3_E~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,750 INFO L290 TraceCheckUtils]: 17: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~T4_E~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,751 INFO L290 TraceCheckUtils]: 18: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~T5_E~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,751 INFO L290 TraceCheckUtils]: 19: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~T6_E~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,751 INFO L290 TraceCheckUtils]: 20: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~T7_E~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,751 INFO L290 TraceCheckUtils]: 21: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,751 INFO L290 TraceCheckUtils]: 22: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,752 INFO L290 TraceCheckUtils]: 23: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~E_3~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,752 INFO L290 TraceCheckUtils]: 24: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~E_4~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,752 INFO L290 TraceCheckUtils]: 25: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~E_5~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,752 INFO L290 TraceCheckUtils]: 26: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~E_6~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 27: Hoare triple {33958#(= ~m_pc~0 0)} assume !(0 == ~E_7~0); {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 28: Hoare triple {33958#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {33958#(= ~m_pc~0 0)} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 29: Hoare triple {33958#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {33957#false} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 30: Hoare triple {33957#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {33957#false} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 31: Hoare triple {33957#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {33957#false} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 32: Hoare triple {33957#false} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {33957#false} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 33: Hoare triple {33957#false} assume !(0 != activate_threads_~tmp~1#1); {33957#false} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 34: Hoare triple {33957#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {33957#false} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 35: Hoare triple {33957#false} assume !(1 == ~t1_pc~0); {33957#false} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 36: Hoare triple {33957#false} is_transmit1_triggered_~__retres1~1#1 := 0; {33957#false} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 37: Hoare triple {33957#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {33957#false} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 38: Hoare triple {33957#false} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {33957#false} is VALID [2022-02-21 04:24:23,753 INFO L290 TraceCheckUtils]: 39: Hoare triple {33957#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 40: Hoare triple {33957#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 41: Hoare triple {33957#false} assume 1 == ~t2_pc~0; {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 42: Hoare triple {33957#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 43: Hoare triple {33957#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 44: Hoare triple {33957#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 45: Hoare triple {33957#false} assume !(0 != activate_threads_~tmp___1~0#1); {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 46: Hoare triple {33957#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 47: Hoare triple {33957#false} assume !(1 == ~t3_pc~0); {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 48: Hoare triple {33957#false} is_transmit3_triggered_~__retres1~3#1 := 0; {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 49: Hoare triple {33957#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 50: Hoare triple {33957#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 51: Hoare triple {33957#false} assume !(0 != activate_threads_~tmp___2~0#1); {33957#false} is VALID [2022-02-21 04:24:23,754 INFO L290 TraceCheckUtils]: 52: Hoare triple {33957#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {33957#false} is VALID [2022-02-21 04:24:23,755 INFO L290 TraceCheckUtils]: 53: Hoare triple {33957#false} assume 1 == ~t4_pc~0; {33957#false} is VALID [2022-02-21 04:24:23,755 INFO L290 TraceCheckUtils]: 54: Hoare triple {33957#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {33957#false} is VALID [2022-02-21 04:24:23,755 INFO L290 TraceCheckUtils]: 55: Hoare triple {33957#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {33957#false} is VALID [2022-02-21 04:24:23,755 INFO L290 TraceCheckUtils]: 56: Hoare triple {33957#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {33957#false} is VALID [2022-02-21 04:24:23,755 INFO L290 TraceCheckUtils]: 57: Hoare triple {33957#false} assume !(0 != activate_threads_~tmp___3~0#1); {33957#false} is VALID [2022-02-21 04:24:23,755 INFO L290 TraceCheckUtils]: 58: Hoare triple {33957#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {33957#false} is VALID [2022-02-21 04:24:23,755 INFO L290 TraceCheckUtils]: 59: Hoare triple {33957#false} assume !(1 == ~t5_pc~0); {33957#false} is VALID [2022-02-21 04:24:23,755 INFO L290 TraceCheckUtils]: 60: Hoare triple {33957#false} is_transmit5_triggered_~__retres1~5#1 := 0; {33957#false} is VALID [2022-02-21 04:24:23,755 INFO L290 TraceCheckUtils]: 61: Hoare triple {33957#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {33957#false} is VALID [2022-02-21 04:24:23,755 INFO L290 TraceCheckUtils]: 62: Hoare triple {33957#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {33957#false} is VALID [2022-02-21 04:24:23,756 INFO L290 TraceCheckUtils]: 63: Hoare triple {33957#false} assume !(0 != activate_threads_~tmp___4~0#1); {33957#false} is VALID [2022-02-21 04:24:23,756 INFO L290 TraceCheckUtils]: 64: Hoare triple {33957#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {33957#false} is VALID [2022-02-21 04:24:23,756 INFO L290 TraceCheckUtils]: 65: Hoare triple {33957#false} assume 1 == ~t6_pc~0; {33957#false} is VALID [2022-02-21 04:24:23,756 INFO L290 TraceCheckUtils]: 66: Hoare triple {33957#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {33957#false} is VALID [2022-02-21 04:24:23,756 INFO L290 TraceCheckUtils]: 67: Hoare triple {33957#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {33957#false} is VALID [2022-02-21 04:24:23,756 INFO L290 TraceCheckUtils]: 68: Hoare triple {33957#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {33957#false} is VALID [2022-02-21 04:24:23,756 INFO L290 TraceCheckUtils]: 69: Hoare triple {33957#false} assume !(0 != activate_threads_~tmp___5~0#1); {33957#false} is VALID [2022-02-21 04:24:23,756 INFO L290 TraceCheckUtils]: 70: Hoare triple {33957#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {33957#false} is VALID [2022-02-21 04:24:23,756 INFO L290 TraceCheckUtils]: 71: Hoare triple {33957#false} assume !(1 == ~t7_pc~0); {33957#false} is VALID [2022-02-21 04:24:23,756 INFO L290 TraceCheckUtils]: 72: Hoare triple {33957#false} is_transmit7_triggered_~__retres1~7#1 := 0; {33957#false} is VALID [2022-02-21 04:24:23,757 INFO L290 TraceCheckUtils]: 73: Hoare triple {33957#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {33957#false} is VALID [2022-02-21 04:24:23,757 INFO L290 TraceCheckUtils]: 74: Hoare triple {33957#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {33957#false} is VALID [2022-02-21 04:24:23,757 INFO L290 TraceCheckUtils]: 75: Hoare triple {33957#false} assume !(0 != activate_threads_~tmp___6~0#1); {33957#false} is VALID [2022-02-21 04:24:23,757 INFO L290 TraceCheckUtils]: 76: Hoare triple {33957#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {33957#false} is VALID [2022-02-21 04:24:23,757 INFO L290 TraceCheckUtils]: 77: Hoare triple {33957#false} assume !(1 == ~M_E~0); {33957#false} is VALID [2022-02-21 04:24:23,757 INFO L290 TraceCheckUtils]: 78: Hoare triple {33957#false} assume !(1 == ~T1_E~0); {33957#false} is VALID [2022-02-21 04:24:23,757 INFO L290 TraceCheckUtils]: 79: Hoare triple {33957#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {33957#false} is VALID [2022-02-21 04:24:23,757 INFO L290 TraceCheckUtils]: 80: Hoare triple {33957#false} assume !(1 == ~T3_E~0); {33957#false} is VALID [2022-02-21 04:24:23,757 INFO L290 TraceCheckUtils]: 81: Hoare triple {33957#false} assume !(1 == ~T4_E~0); {33957#false} is VALID [2022-02-21 04:24:23,757 INFO L290 TraceCheckUtils]: 82: Hoare triple {33957#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {33957#false} is VALID [2022-02-21 04:24:23,758 INFO L290 TraceCheckUtils]: 83: Hoare triple {33957#false} assume !(1 == ~T6_E~0); {33957#false} is VALID [2022-02-21 04:24:23,758 INFO L290 TraceCheckUtils]: 84: Hoare triple {33957#false} assume !(1 == ~T7_E~0); {33957#false} is VALID [2022-02-21 04:24:23,758 INFO L290 TraceCheckUtils]: 85: Hoare triple {33957#false} assume !(1 == ~E_1~0); {33957#false} is VALID [2022-02-21 04:24:23,758 INFO L290 TraceCheckUtils]: 86: Hoare triple {33957#false} assume !(1 == ~E_2~0); {33957#false} is VALID [2022-02-21 04:24:23,758 INFO L290 TraceCheckUtils]: 87: Hoare triple {33957#false} assume !(1 == ~E_3~0); {33957#false} is VALID [2022-02-21 04:24:23,758 INFO L290 TraceCheckUtils]: 88: Hoare triple {33957#false} assume !(1 == ~E_4~0); {33957#false} is VALID [2022-02-21 04:24:23,758 INFO L290 TraceCheckUtils]: 89: Hoare triple {33957#false} assume !(1 == ~E_5~0); {33957#false} is VALID [2022-02-21 04:24:23,758 INFO L290 TraceCheckUtils]: 90: Hoare triple {33957#false} assume 1 == ~E_6~0;~E_6~0 := 2; {33957#false} is VALID [2022-02-21 04:24:23,758 INFO L290 TraceCheckUtils]: 91: Hoare triple {33957#false} assume !(1 == ~E_7~0); {33957#false} is VALID [2022-02-21 04:24:23,758 INFO L290 TraceCheckUtils]: 92: Hoare triple {33957#false} assume { :end_inline_reset_delta_events } true; {33957#false} is VALID [2022-02-21 04:24:23,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:23,759 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:23,759 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1966996578] [2022-02-21 04:24:23,759 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1966996578] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:23,759 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:23,759 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:23,759 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2066268837] [2022-02-21 04:24:23,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:23,761 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:23,761 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:23,761 INFO L85 PathProgramCache]: Analyzing trace with hash -169639712, now seen corresponding path program 1 times [2022-02-21 04:24:23,761 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:23,761 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670370594] [2022-02-21 04:24:23,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:23,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:23,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:23,806 INFO L290 TraceCheckUtils]: 0: Hoare triple {33959#true} assume !false; {33959#true} is VALID [2022-02-21 04:24:23,807 INFO L290 TraceCheckUtils]: 1: Hoare triple {33959#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {33959#true} is VALID [2022-02-21 04:24:23,807 INFO L290 TraceCheckUtils]: 2: Hoare triple {33959#true} assume !false; {33959#true} is VALID [2022-02-21 04:24:23,807 INFO L290 TraceCheckUtils]: 3: Hoare triple {33959#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {33959#true} is VALID [2022-02-21 04:24:23,807 INFO L290 TraceCheckUtils]: 4: Hoare triple {33959#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {33959#true} is VALID [2022-02-21 04:24:23,807 INFO L290 TraceCheckUtils]: 5: Hoare triple {33959#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {33959#true} is VALID [2022-02-21 04:24:23,807 INFO L290 TraceCheckUtils]: 6: Hoare triple {33959#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {33959#true} is VALID [2022-02-21 04:24:23,807 INFO L290 TraceCheckUtils]: 7: Hoare triple {33959#true} assume !(0 != eval_~tmp~0#1); {33959#true} is VALID [2022-02-21 04:24:23,807 INFO L290 TraceCheckUtils]: 8: Hoare triple {33959#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {33959#true} is VALID [2022-02-21 04:24:23,807 INFO L290 TraceCheckUtils]: 9: Hoare triple {33959#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {33959#true} is VALID [2022-02-21 04:24:23,808 INFO L290 TraceCheckUtils]: 10: Hoare triple {33959#true} assume 0 == ~M_E~0;~M_E~0 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,808 INFO L290 TraceCheckUtils]: 11: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,808 INFO L290 TraceCheckUtils]: 12: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,809 INFO L290 TraceCheckUtils]: 13: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,809 INFO L290 TraceCheckUtils]: 14: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,809 INFO L290 TraceCheckUtils]: 15: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,809 INFO L290 TraceCheckUtils]: 16: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T6_E~0); {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,810 INFO L290 TraceCheckUtils]: 17: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,810 INFO L290 TraceCheckUtils]: 18: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,810 INFO L290 TraceCheckUtils]: 19: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,810 INFO L290 TraceCheckUtils]: 20: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,811 INFO L290 TraceCheckUtils]: 21: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,811 INFO L290 TraceCheckUtils]: 22: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,811 INFO L290 TraceCheckUtils]: 23: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,811 INFO L290 TraceCheckUtils]: 24: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_7~0); {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,812 INFO L290 TraceCheckUtils]: 25: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,812 INFO L290 TraceCheckUtils]: 26: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,812 INFO L290 TraceCheckUtils]: 27: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,812 INFO L290 TraceCheckUtils]: 28: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,813 INFO L290 TraceCheckUtils]: 29: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,813 INFO L290 TraceCheckUtils]: 30: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,813 INFO L290 TraceCheckUtils]: 31: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,813 INFO L290 TraceCheckUtils]: 32: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,814 INFO L290 TraceCheckUtils]: 33: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,814 INFO L290 TraceCheckUtils]: 34: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,814 INFO L290 TraceCheckUtils]: 35: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,814 INFO L290 TraceCheckUtils]: 36: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,815 INFO L290 TraceCheckUtils]: 37: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,815 INFO L290 TraceCheckUtils]: 38: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,815 INFO L290 TraceCheckUtils]: 39: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,815 INFO L290 TraceCheckUtils]: 40: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,816 INFO L290 TraceCheckUtils]: 41: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,816 INFO L290 TraceCheckUtils]: 42: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,816 INFO L290 TraceCheckUtils]: 43: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,816 INFO L290 TraceCheckUtils]: 44: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,817 INFO L290 TraceCheckUtils]: 45: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,817 INFO L290 TraceCheckUtils]: 46: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,817 INFO L290 TraceCheckUtils]: 47: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,817 INFO L290 TraceCheckUtils]: 48: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,818 INFO L290 TraceCheckUtils]: 49: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,818 INFO L290 TraceCheckUtils]: 50: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,818 INFO L290 TraceCheckUtils]: 51: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,818 INFO L290 TraceCheckUtils]: 52: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,819 INFO L290 TraceCheckUtils]: 53: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,819 INFO L290 TraceCheckUtils]: 54: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,819 INFO L290 TraceCheckUtils]: 55: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,820 INFO L290 TraceCheckUtils]: 56: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,820 INFO L290 TraceCheckUtils]: 57: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,820 INFO L290 TraceCheckUtils]: 58: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,820 INFO L290 TraceCheckUtils]: 59: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,821 INFO L290 TraceCheckUtils]: 60: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,821 INFO L290 TraceCheckUtils]: 61: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,821 INFO L290 TraceCheckUtils]: 62: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,821 INFO L290 TraceCheckUtils]: 63: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,822 INFO L290 TraceCheckUtils]: 64: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,822 INFO L290 TraceCheckUtils]: 65: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,822 INFO L290 TraceCheckUtils]: 66: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,822 INFO L290 TraceCheckUtils]: 67: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,823 INFO L290 TraceCheckUtils]: 68: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,823 INFO L290 TraceCheckUtils]: 69: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,823 INFO L290 TraceCheckUtils]: 70: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,824 INFO L290 TraceCheckUtils]: 71: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,824 INFO L290 TraceCheckUtils]: 72: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,824 INFO L290 TraceCheckUtils]: 73: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {33961#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:23,824 INFO L290 TraceCheckUtils]: 74: Hoare triple {33961#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {33960#false} is VALID [2022-02-21 04:24:23,824 INFO L290 TraceCheckUtils]: 75: Hoare triple {33960#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,825 INFO L290 TraceCheckUtils]: 76: Hoare triple {33960#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,825 INFO L290 TraceCheckUtils]: 77: Hoare triple {33960#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,825 INFO L290 TraceCheckUtils]: 78: Hoare triple {33960#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,825 INFO L290 TraceCheckUtils]: 79: Hoare triple {33960#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,825 INFO L290 TraceCheckUtils]: 80: Hoare triple {33960#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,825 INFO L290 TraceCheckUtils]: 81: Hoare triple {33960#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,825 INFO L290 TraceCheckUtils]: 82: Hoare triple {33960#false} assume !(1 == ~E_1~0); {33960#false} is VALID [2022-02-21 04:24:23,825 INFO L290 TraceCheckUtils]: 83: Hoare triple {33960#false} assume 1 == ~E_2~0;~E_2~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,825 INFO L290 TraceCheckUtils]: 84: Hoare triple {33960#false} assume 1 == ~E_3~0;~E_3~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,825 INFO L290 TraceCheckUtils]: 85: Hoare triple {33960#false} assume 1 == ~E_4~0;~E_4~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,826 INFO L290 TraceCheckUtils]: 86: Hoare triple {33960#false} assume 1 == ~E_5~0;~E_5~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,826 INFO L290 TraceCheckUtils]: 87: Hoare triple {33960#false} assume 1 == ~E_6~0;~E_6~0 := 2; {33960#false} is VALID [2022-02-21 04:24:23,826 INFO L290 TraceCheckUtils]: 88: Hoare triple {33960#false} assume !(1 == ~E_7~0); {33960#false} is VALID [2022-02-21 04:24:23,826 INFO L290 TraceCheckUtils]: 89: Hoare triple {33960#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {33960#false} is VALID [2022-02-21 04:24:23,826 INFO L290 TraceCheckUtils]: 90: Hoare triple {33960#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {33960#false} is VALID [2022-02-21 04:24:23,826 INFO L290 TraceCheckUtils]: 91: Hoare triple {33960#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {33960#false} is VALID [2022-02-21 04:24:23,826 INFO L290 TraceCheckUtils]: 92: Hoare triple {33960#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {33960#false} is VALID [2022-02-21 04:24:23,826 INFO L290 TraceCheckUtils]: 93: Hoare triple {33960#false} assume !(0 == start_simulation_~tmp~3#1); {33960#false} is VALID [2022-02-21 04:24:23,826 INFO L290 TraceCheckUtils]: 94: Hoare triple {33960#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {33960#false} is VALID [2022-02-21 04:24:23,826 INFO L290 TraceCheckUtils]: 95: Hoare triple {33960#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {33960#false} is VALID [2022-02-21 04:24:23,827 INFO L290 TraceCheckUtils]: 96: Hoare triple {33960#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {33960#false} is VALID [2022-02-21 04:24:23,827 INFO L290 TraceCheckUtils]: 97: Hoare triple {33960#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {33960#false} is VALID [2022-02-21 04:24:23,827 INFO L290 TraceCheckUtils]: 98: Hoare triple {33960#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {33960#false} is VALID [2022-02-21 04:24:23,827 INFO L290 TraceCheckUtils]: 99: Hoare triple {33960#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {33960#false} is VALID [2022-02-21 04:24:23,827 INFO L290 TraceCheckUtils]: 100: Hoare triple {33960#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {33960#false} is VALID [2022-02-21 04:24:23,827 INFO L290 TraceCheckUtils]: 101: Hoare triple {33960#false} assume !(0 != start_simulation_~tmp___0~1#1); {33960#false} is VALID [2022-02-21 04:24:23,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:23,828 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:23,828 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [670370594] [2022-02-21 04:24:23,828 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [670370594] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:23,828 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:23,828 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:23,828 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1867922323] [2022-02-21 04:24:23,829 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:23,829 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:23,829 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:23,829 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:23,829 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:23,830 INFO L87 Difference]: Start difference. First operand 1448 states and 2122 transitions. cyclomatic complexity: 676 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,700 INFO L93 Difference]: Finished difference Result 2759 states and 4004 transitions. [2022-02-21 04:24:24,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:24,700 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,747 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:24,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2759 states and 4004 transitions. [2022-02-21 04:24:24,937 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2644 [2022-02-21 04:24:25,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2759 states to 2759 states and 4004 transitions. [2022-02-21 04:24:25,127 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2759 [2022-02-21 04:24:25,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2759 [2022-02-21 04:24:25,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2759 states and 4004 transitions. [2022-02-21 04:24:25,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:25,131 INFO L681 BuchiCegarLoop]: Abstraction has 2759 states and 4004 transitions. [2022-02-21 04:24:25,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2759 states and 4004 transitions. [2022-02-21 04:24:25,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2759 to 2645. [2022-02-21 04:24:25,160 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:25,163 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2759 states and 4004 transitions. Second operand has 2645 states, 2645 states have (on average 1.454820415879017) internal successors, (3848), 2644 states have internal predecessors, (3848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,165 INFO L74 IsIncluded]: Start isIncluded. First operand 2759 states and 4004 transitions. Second operand has 2645 states, 2645 states have (on average 1.454820415879017) internal successors, (3848), 2644 states have internal predecessors, (3848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,168 INFO L87 Difference]: Start difference. First operand 2759 states and 4004 transitions. Second operand has 2645 states, 2645 states have (on average 1.454820415879017) internal successors, (3848), 2644 states have internal predecessors, (3848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:25,346 INFO L93 Difference]: Finished difference Result 2759 states and 4004 transitions. [2022-02-21 04:24:25,346 INFO L276 IsEmpty]: Start isEmpty. Operand 2759 states and 4004 transitions. [2022-02-21 04:24:25,349 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:25,349 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:25,352 INFO L74 IsIncluded]: Start isIncluded. First operand has 2645 states, 2645 states have (on average 1.454820415879017) internal successors, (3848), 2644 states have internal predecessors, (3848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2759 states and 4004 transitions. [2022-02-21 04:24:25,354 INFO L87 Difference]: Start difference. First operand has 2645 states, 2645 states have (on average 1.454820415879017) internal successors, (3848), 2644 states have internal predecessors, (3848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2759 states and 4004 transitions. [2022-02-21 04:24:25,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:25,511 INFO L93 Difference]: Finished difference Result 2759 states and 4004 transitions. [2022-02-21 04:24:25,511 INFO L276 IsEmpty]: Start isEmpty. Operand 2759 states and 4004 transitions. [2022-02-21 04:24:25,543 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:25,543 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:25,543 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:25,543 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:25,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2645 states, 2645 states have (on average 1.454820415879017) internal successors, (3848), 2644 states have internal predecessors, (3848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2645 states to 2645 states and 3848 transitions. [2022-02-21 04:24:25,694 INFO L704 BuchiCegarLoop]: Abstraction has 2645 states and 3848 transitions. [2022-02-21 04:24:25,694 INFO L587 BuchiCegarLoop]: Abstraction has 2645 states and 3848 transitions. [2022-02-21 04:24:25,694 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:24:25,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2645 states and 3848 transitions. [2022-02-21 04:24:25,699 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2530 [2022-02-21 04:24:25,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:25,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:25,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:25,700 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:25,701 INFO L791 eck$LassoCheckResult]: Stem: 37578#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 37534#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 37535#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36928#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36929#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 37381#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37382#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37343#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37249#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37250#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37241#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37242#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37198#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37199#L754 assume !(0 == ~M_E~0); 37506#L754-2 assume !(0 == ~T1_E~0); 37136#L759-1 assume !(0 == ~T2_E~0); 37137#L764-1 assume !(0 == ~T3_E~0); 37553#L769-1 assume !(0 == ~T4_E~0); 37554#L774-1 assume !(0 == ~T5_E~0); 37418#L779-1 assume !(0 == ~T6_E~0); 37168#L784-1 assume !(0 == ~T7_E~0); 37169#L789-1 assume !(0 == ~E_1~0); 36837#L794-1 assume !(0 == ~E_2~0); 36838#L799-1 assume !(0 == ~E_3~0); 37557#L804-1 assume !(0 == ~E_4~0); 37558#L809-1 assume !(0 == ~E_5~0); 37254#L814-1 assume !(0 == ~E_6~0); 36757#L819-1 assume !(0 == ~E_7~0); 36758#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37238#L361 assume !(1 == ~m_pc~0); 37239#L361-2 is_master_triggered_~__retres1~0#1 := 0; 37285#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37047#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37048#L930 assume !(0 != activate_threads_~tmp~1#1); 37413#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37231#L380 assume !(1 == ~t1_pc~0); 36892#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 36891#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37439#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37541#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36967#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36893#L399 assume 1 == ~t2_pc~0; 36894#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37102#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37456#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37309#L946 assume !(0 != activate_threads_~tmp___1~0#1); 36797#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36765#L418 assume !(1 == ~t3_pc~0); 36726#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36727#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37258#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37516#L954 assume !(0 != activate_threads_~tmp___2~0#1); 37566#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37507#L437 assume 1 == ~t4_pc~0; 37508#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37068#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36896#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36897#L962 assume !(0 != activate_threads_~tmp___3~0#1); 37354#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37019#L456 assume !(1 == ~t5_pc~0); 37020#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 37133#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37483#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36784#L970 assume !(0 != activate_threads_~tmp___4~0#1); 36785#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36909#L475 assume 1 == ~t6_pc~0; 36910#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36988#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36989#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36747#L978 assume !(0 != activate_threads_~tmp___5~0#1); 36748#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37245#L494 assume !(1 == ~t7_pc~0); 37247#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 37293#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37476#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37477#L986 assume !(0 != activate_threads_~tmp___6~0#1); 37573#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37478#L837 assume !(1 == ~M_E~0); 37313#L837-2 assume !(1 == ~T1_E~0); 36874#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36875#L847-1 assume !(1 == ~T3_E~0); 37469#L852-1 assume !(1 == ~T4_E~0); 37470#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37323#L862-1 assume !(1 == ~T6_E~0); 37324#L867-1 assume !(1 == ~T7_E~0); 37334#L872-1 assume !(1 == ~E_1~0); 37417#L877-1 assume !(1 == ~E_2~0); 37330#L882-1 assume !(1 == ~E_3~0); 37331#L887-1 assume !(1 == ~E_4~0); 36934#L892-1 assume !(1 == ~E_5~0); 36935#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 37348#L902-1 assume !(1 == ~E_7~0); 37349#L907-1 assume { :end_inline_reset_delta_events } true; 37799#L1148-2 [2022-02-21 04:24:25,701 INFO L793 eck$LassoCheckResult]: Loop: 37799#L1148-2 assume !false; 37800#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37788#L729 assume !false; 37789#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 37671#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 37667#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 37652#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37653#L626 assume !(0 != eval_~tmp~0#1); 38032#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38030#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38028#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38026#L754-5 assume !(0 == ~T1_E~0); 38023#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38024#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38533#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38532#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38531#L779-3 assume !(0 == ~T6_E~0); 38530#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38529#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38528#L794-3 assume !(0 == ~E_2~0); 38527#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38526#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38525#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38524#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38523#L819-3 assume !(0 == ~E_7~0); 38522#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38521#L361-24 assume !(1 == ~m_pc~0); 38520#L361-26 is_master_triggered_~__retres1~0#1 := 0; 38519#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38518#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38517#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38516#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37995#L380-24 assume !(1 == ~t1_pc~0); 37996#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 38505#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38504#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 38503#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38502#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38501#L399-24 assume 1 == ~t2_pc~0; 38499#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38498#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38497#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 38496#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37968#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37969#L418-24 assume !(1 == ~t3_pc~0); 38489#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 38488#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38487#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38486#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38485#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37949#L437-24 assume 1 == ~t4_pc~0; 37946#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37945#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37942#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37940#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37937#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37938#L456-24 assume !(1 == ~t5_pc~0); 37930#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 37928#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37924#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37925#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38465#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37915#L475-24 assume !(1 == ~t6_pc~0); 37916#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 37907#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37905#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37902#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 37903#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37897#L494-24 assume !(1 == ~t7_pc~0); 37894#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 37891#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37889#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37887#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37885#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37883#L837-3 assume !(1 == ~M_E~0); 37880#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37878#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37876#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37874#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37872#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37870#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37868#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37866#L872-3 assume !(1 == ~E_1~0); 37863#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37864#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37856#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37857#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37849#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37850#L902-3 assume !(1 == ~E_7~0); 37843#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 37844#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 38110#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 38109#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 38107#L1167 assume !(0 == start_simulation_~tmp~3#1); 38106#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 38102#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 38097#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 38096#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 38095#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38094#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37805#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 37806#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 37799#L1148-2 [2022-02-21 04:24:25,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:25,701 INFO L85 PathProgramCache]: Analyzing trace with hash 2012584553, now seen corresponding path program 1 times [2022-02-21 04:24:25,702 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:25,702 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124988366] [2022-02-21 04:24:25,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:25,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:25,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:25,732 INFO L290 TraceCheckUtils]: 0: Hoare triple {44887#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {44887#true} is VALID [2022-02-21 04:24:25,733 INFO L290 TraceCheckUtils]: 1: Hoare triple {44887#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {44887#true} is VALID [2022-02-21 04:24:25,733 INFO L290 TraceCheckUtils]: 2: Hoare triple {44887#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {44887#true} is VALID [2022-02-21 04:24:25,733 INFO L290 TraceCheckUtils]: 3: Hoare triple {44887#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {44887#true} is VALID [2022-02-21 04:24:25,733 INFO L290 TraceCheckUtils]: 4: Hoare triple {44887#true} assume 1 == ~m_i~0;~m_st~0 := 0; {44887#true} is VALID [2022-02-21 04:24:25,733 INFO L290 TraceCheckUtils]: 5: Hoare triple {44887#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {44887#true} is VALID [2022-02-21 04:24:25,733 INFO L290 TraceCheckUtils]: 6: Hoare triple {44887#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {44887#true} is VALID [2022-02-21 04:24:25,733 INFO L290 TraceCheckUtils]: 7: Hoare triple {44887#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {44887#true} is VALID [2022-02-21 04:24:25,733 INFO L290 TraceCheckUtils]: 8: Hoare triple {44887#true} assume 1 == ~t4_i~0;~t4_st~0 := 0; {44887#true} is VALID [2022-02-21 04:24:25,733 INFO L290 TraceCheckUtils]: 9: Hoare triple {44887#true} assume 1 == ~t5_i~0;~t5_st~0 := 0; {44887#true} is VALID [2022-02-21 04:24:25,734 INFO L290 TraceCheckUtils]: 10: Hoare triple {44887#true} assume 1 == ~t6_i~0;~t6_st~0 := 0; {44887#true} is VALID [2022-02-21 04:24:25,734 INFO L290 TraceCheckUtils]: 11: Hoare triple {44887#true} assume 1 == ~t7_i~0;~t7_st~0 := 0; {44887#true} is VALID [2022-02-21 04:24:25,734 INFO L290 TraceCheckUtils]: 12: Hoare triple {44887#true} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {44887#true} is VALID [2022-02-21 04:24:25,734 INFO L290 TraceCheckUtils]: 13: Hoare triple {44887#true} assume !(0 == ~M_E~0); {44887#true} is VALID [2022-02-21 04:24:25,734 INFO L290 TraceCheckUtils]: 14: Hoare triple {44887#true} assume !(0 == ~T1_E~0); {44887#true} is VALID [2022-02-21 04:24:25,734 INFO L290 TraceCheckUtils]: 15: Hoare triple {44887#true} assume !(0 == ~T2_E~0); {44887#true} is VALID [2022-02-21 04:24:25,734 INFO L290 TraceCheckUtils]: 16: Hoare triple {44887#true} assume !(0 == ~T3_E~0); {44887#true} is VALID [2022-02-21 04:24:25,734 INFO L290 TraceCheckUtils]: 17: Hoare triple {44887#true} assume !(0 == ~T4_E~0); {44887#true} is VALID [2022-02-21 04:24:25,735 INFO L290 TraceCheckUtils]: 18: Hoare triple {44887#true} assume !(0 == ~T5_E~0); {44887#true} is VALID [2022-02-21 04:24:25,735 INFO L290 TraceCheckUtils]: 19: Hoare triple {44887#true} assume !(0 == ~T6_E~0); {44887#true} is VALID [2022-02-21 04:24:25,735 INFO L290 TraceCheckUtils]: 20: Hoare triple {44887#true} assume !(0 == ~T7_E~0); {44887#true} is VALID [2022-02-21 04:24:25,735 INFO L290 TraceCheckUtils]: 21: Hoare triple {44887#true} assume !(0 == ~E_1~0); {44887#true} is VALID [2022-02-21 04:24:25,735 INFO L290 TraceCheckUtils]: 22: Hoare triple {44887#true} assume !(0 == ~E_2~0); {44887#true} is VALID [2022-02-21 04:24:25,735 INFO L290 TraceCheckUtils]: 23: Hoare triple {44887#true} assume !(0 == ~E_3~0); {44887#true} is VALID [2022-02-21 04:24:25,735 INFO L290 TraceCheckUtils]: 24: Hoare triple {44887#true} assume !(0 == ~E_4~0); {44887#true} is VALID [2022-02-21 04:24:25,735 INFO L290 TraceCheckUtils]: 25: Hoare triple {44887#true} assume !(0 == ~E_5~0); {44887#true} is VALID [2022-02-21 04:24:25,735 INFO L290 TraceCheckUtils]: 26: Hoare triple {44887#true} assume !(0 == ~E_6~0); {44887#true} is VALID [2022-02-21 04:24:25,736 INFO L290 TraceCheckUtils]: 27: Hoare triple {44887#true} assume !(0 == ~E_7~0); {44887#true} is VALID [2022-02-21 04:24:25,736 INFO L290 TraceCheckUtils]: 28: Hoare triple {44887#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {44887#true} is VALID [2022-02-21 04:24:25,736 INFO L290 TraceCheckUtils]: 29: Hoare triple {44887#true} assume !(1 == ~m_pc~0); {44887#true} is VALID [2022-02-21 04:24:25,736 INFO L290 TraceCheckUtils]: 30: Hoare triple {44887#true} is_master_triggered_~__retres1~0#1 := 0; {44887#true} is VALID [2022-02-21 04:24:25,736 INFO L290 TraceCheckUtils]: 31: Hoare triple {44887#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {44887#true} is VALID [2022-02-21 04:24:25,736 INFO L290 TraceCheckUtils]: 32: Hoare triple {44887#true} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {44887#true} is VALID [2022-02-21 04:24:25,736 INFO L290 TraceCheckUtils]: 33: Hoare triple {44887#true} assume !(0 != activate_threads_~tmp~1#1); {44887#true} is VALID [2022-02-21 04:24:25,736 INFO L290 TraceCheckUtils]: 34: Hoare triple {44887#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {44887#true} is VALID [2022-02-21 04:24:25,736 INFO L290 TraceCheckUtils]: 35: Hoare triple {44887#true} assume !(1 == ~t1_pc~0); {44887#true} is VALID [2022-02-21 04:24:25,737 INFO L290 TraceCheckUtils]: 36: Hoare triple {44887#true} is_transmit1_triggered_~__retres1~1#1 := 0; {44889#(= |ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1| 0)} is VALID [2022-02-21 04:24:25,737 INFO L290 TraceCheckUtils]: 37: Hoare triple {44889#(= |ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1| 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {44890#(= |ULTIMATE.start_is_transmit1_triggered_#res#1| 0)} is VALID [2022-02-21 04:24:25,738 INFO L290 TraceCheckUtils]: 38: Hoare triple {44890#(= |ULTIMATE.start_is_transmit1_triggered_#res#1| 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {44891#(= |ULTIMATE.start_activate_threads_~tmp___0~0#1| 0)} is VALID [2022-02-21 04:24:25,738 INFO L290 TraceCheckUtils]: 39: Hoare triple {44891#(= |ULTIMATE.start_activate_threads_~tmp___0~0#1| 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {44888#false} is VALID [2022-02-21 04:24:25,738 INFO L290 TraceCheckUtils]: 40: Hoare triple {44888#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {44888#false} is VALID [2022-02-21 04:24:25,738 INFO L290 TraceCheckUtils]: 41: Hoare triple {44888#false} assume 1 == ~t2_pc~0; {44888#false} is VALID [2022-02-21 04:24:25,738 INFO L290 TraceCheckUtils]: 42: Hoare triple {44888#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {44888#false} is VALID [2022-02-21 04:24:25,738 INFO L290 TraceCheckUtils]: 43: Hoare triple {44888#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {44888#false} is VALID [2022-02-21 04:24:25,738 INFO L290 TraceCheckUtils]: 44: Hoare triple {44888#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {44888#false} is VALID [2022-02-21 04:24:25,738 INFO L290 TraceCheckUtils]: 45: Hoare triple {44888#false} assume !(0 != activate_threads_~tmp___1~0#1); {44888#false} is VALID [2022-02-21 04:24:25,739 INFO L290 TraceCheckUtils]: 46: Hoare triple {44888#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {44888#false} is VALID [2022-02-21 04:24:25,739 INFO L290 TraceCheckUtils]: 47: Hoare triple {44888#false} assume !(1 == ~t3_pc~0); {44888#false} is VALID [2022-02-21 04:24:25,739 INFO L290 TraceCheckUtils]: 48: Hoare triple {44888#false} is_transmit3_triggered_~__retres1~3#1 := 0; {44888#false} is VALID [2022-02-21 04:24:25,739 INFO L290 TraceCheckUtils]: 49: Hoare triple {44888#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {44888#false} is VALID [2022-02-21 04:24:25,739 INFO L290 TraceCheckUtils]: 50: Hoare triple {44888#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {44888#false} is VALID [2022-02-21 04:24:25,739 INFO L290 TraceCheckUtils]: 51: Hoare triple {44888#false} assume !(0 != activate_threads_~tmp___2~0#1); {44888#false} is VALID [2022-02-21 04:24:25,739 INFO L290 TraceCheckUtils]: 52: Hoare triple {44888#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {44888#false} is VALID [2022-02-21 04:24:25,739 INFO L290 TraceCheckUtils]: 53: Hoare triple {44888#false} assume 1 == ~t4_pc~0; {44888#false} is VALID [2022-02-21 04:24:25,740 INFO L290 TraceCheckUtils]: 54: Hoare triple {44888#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {44888#false} is VALID [2022-02-21 04:24:25,740 INFO L290 TraceCheckUtils]: 55: Hoare triple {44888#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {44888#false} is VALID [2022-02-21 04:24:25,740 INFO L290 TraceCheckUtils]: 56: Hoare triple {44888#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {44888#false} is VALID [2022-02-21 04:24:25,740 INFO L290 TraceCheckUtils]: 57: Hoare triple {44888#false} assume !(0 != activate_threads_~tmp___3~0#1); {44888#false} is VALID [2022-02-21 04:24:25,740 INFO L290 TraceCheckUtils]: 58: Hoare triple {44888#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {44888#false} is VALID [2022-02-21 04:24:25,740 INFO L290 TraceCheckUtils]: 59: Hoare triple {44888#false} assume !(1 == ~t5_pc~0); {44888#false} is VALID [2022-02-21 04:24:25,740 INFO L290 TraceCheckUtils]: 60: Hoare triple {44888#false} is_transmit5_triggered_~__retres1~5#1 := 0; {44888#false} is VALID [2022-02-21 04:24:25,740 INFO L290 TraceCheckUtils]: 61: Hoare triple {44888#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {44888#false} is VALID [2022-02-21 04:24:25,740 INFO L290 TraceCheckUtils]: 62: Hoare triple {44888#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {44888#false} is VALID [2022-02-21 04:24:25,741 INFO L290 TraceCheckUtils]: 63: Hoare triple {44888#false} assume !(0 != activate_threads_~tmp___4~0#1); {44888#false} is VALID [2022-02-21 04:24:25,741 INFO L290 TraceCheckUtils]: 64: Hoare triple {44888#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {44888#false} is VALID [2022-02-21 04:24:25,741 INFO L290 TraceCheckUtils]: 65: Hoare triple {44888#false} assume 1 == ~t6_pc~0; {44888#false} is VALID [2022-02-21 04:24:25,741 INFO L290 TraceCheckUtils]: 66: Hoare triple {44888#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {44888#false} is VALID [2022-02-21 04:24:25,741 INFO L290 TraceCheckUtils]: 67: Hoare triple {44888#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {44888#false} is VALID [2022-02-21 04:24:25,741 INFO L290 TraceCheckUtils]: 68: Hoare triple {44888#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {44888#false} is VALID [2022-02-21 04:24:25,741 INFO L290 TraceCheckUtils]: 69: Hoare triple {44888#false} assume !(0 != activate_threads_~tmp___5~0#1); {44888#false} is VALID [2022-02-21 04:24:25,741 INFO L290 TraceCheckUtils]: 70: Hoare triple {44888#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {44888#false} is VALID [2022-02-21 04:24:25,741 INFO L290 TraceCheckUtils]: 71: Hoare triple {44888#false} assume !(1 == ~t7_pc~0); {44888#false} is VALID [2022-02-21 04:24:25,742 INFO L290 TraceCheckUtils]: 72: Hoare triple {44888#false} is_transmit7_triggered_~__retres1~7#1 := 0; {44888#false} is VALID [2022-02-21 04:24:25,742 INFO L290 TraceCheckUtils]: 73: Hoare triple {44888#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {44888#false} is VALID [2022-02-21 04:24:25,742 INFO L290 TraceCheckUtils]: 74: Hoare triple {44888#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {44888#false} is VALID [2022-02-21 04:24:25,742 INFO L290 TraceCheckUtils]: 75: Hoare triple {44888#false} assume !(0 != activate_threads_~tmp___6~0#1); {44888#false} is VALID [2022-02-21 04:24:25,742 INFO L290 TraceCheckUtils]: 76: Hoare triple {44888#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {44888#false} is VALID [2022-02-21 04:24:25,742 INFO L290 TraceCheckUtils]: 77: Hoare triple {44888#false} assume !(1 == ~M_E~0); {44888#false} is VALID [2022-02-21 04:24:25,742 INFO L290 TraceCheckUtils]: 78: Hoare triple {44888#false} assume !(1 == ~T1_E~0); {44888#false} is VALID [2022-02-21 04:24:25,742 INFO L290 TraceCheckUtils]: 79: Hoare triple {44888#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {44888#false} is VALID [2022-02-21 04:24:25,742 INFO L290 TraceCheckUtils]: 80: Hoare triple {44888#false} assume !(1 == ~T3_E~0); {44888#false} is VALID [2022-02-21 04:24:25,743 INFO L290 TraceCheckUtils]: 81: Hoare triple {44888#false} assume !(1 == ~T4_E~0); {44888#false} is VALID [2022-02-21 04:24:25,743 INFO L290 TraceCheckUtils]: 82: Hoare triple {44888#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {44888#false} is VALID [2022-02-21 04:24:25,743 INFO L290 TraceCheckUtils]: 83: Hoare triple {44888#false} assume !(1 == ~T6_E~0); {44888#false} is VALID [2022-02-21 04:24:25,743 INFO L290 TraceCheckUtils]: 84: Hoare triple {44888#false} assume !(1 == ~T7_E~0); {44888#false} is VALID [2022-02-21 04:24:25,743 INFO L290 TraceCheckUtils]: 85: Hoare triple {44888#false} assume !(1 == ~E_1~0); {44888#false} is VALID [2022-02-21 04:24:25,743 INFO L290 TraceCheckUtils]: 86: Hoare triple {44888#false} assume !(1 == ~E_2~0); {44888#false} is VALID [2022-02-21 04:24:25,743 INFO L290 TraceCheckUtils]: 87: Hoare triple {44888#false} assume !(1 == ~E_3~0); {44888#false} is VALID [2022-02-21 04:24:25,743 INFO L290 TraceCheckUtils]: 88: Hoare triple {44888#false} assume !(1 == ~E_4~0); {44888#false} is VALID [2022-02-21 04:24:25,744 INFO L290 TraceCheckUtils]: 89: Hoare triple {44888#false} assume !(1 == ~E_5~0); {44888#false} is VALID [2022-02-21 04:24:25,744 INFO L290 TraceCheckUtils]: 90: Hoare triple {44888#false} assume 1 == ~E_6~0;~E_6~0 := 2; {44888#false} is VALID [2022-02-21 04:24:25,744 INFO L290 TraceCheckUtils]: 91: Hoare triple {44888#false} assume !(1 == ~E_7~0); {44888#false} is VALID [2022-02-21 04:24:25,744 INFO L290 TraceCheckUtils]: 92: Hoare triple {44888#false} assume { :end_inline_reset_delta_events } true; {44888#false} is VALID [2022-02-21 04:24:25,744 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:25,744 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:25,744 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124988366] [2022-02-21 04:24:25,745 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1124988366] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:25,745 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:25,745 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:25,745 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481505762] [2022-02-21 04:24:25,745 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:25,745 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:25,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:25,746 INFO L85 PathProgramCache]: Analyzing trace with hash 1754793277, now seen corresponding path program 1 times [2022-02-21 04:24:25,746 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:25,746 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977735631] [2022-02-21 04:24:25,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:25,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:25,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:25,768 INFO L290 TraceCheckUtils]: 0: Hoare triple {44892#true} assume !false; {44892#true} is VALID [2022-02-21 04:24:25,769 INFO L290 TraceCheckUtils]: 1: Hoare triple {44892#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {44892#true} is VALID [2022-02-21 04:24:25,769 INFO L290 TraceCheckUtils]: 2: Hoare triple {44892#true} assume !false; {44892#true} is VALID [2022-02-21 04:24:25,769 INFO L290 TraceCheckUtils]: 3: Hoare triple {44892#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {44892#true} is VALID [2022-02-21 04:24:25,769 INFO L290 TraceCheckUtils]: 4: Hoare triple {44892#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {44892#true} is VALID [2022-02-21 04:24:25,769 INFO L290 TraceCheckUtils]: 5: Hoare triple {44892#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {44892#true} is VALID [2022-02-21 04:24:25,769 INFO L290 TraceCheckUtils]: 6: Hoare triple {44892#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {44892#true} is VALID [2022-02-21 04:24:25,769 INFO L290 TraceCheckUtils]: 7: Hoare triple {44892#true} assume !(0 != eval_~tmp~0#1); {44892#true} is VALID [2022-02-21 04:24:25,769 INFO L290 TraceCheckUtils]: 8: Hoare triple {44892#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {44892#true} is VALID [2022-02-21 04:24:25,770 INFO L290 TraceCheckUtils]: 9: Hoare triple {44892#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {44892#true} is VALID [2022-02-21 04:24:25,770 INFO L290 TraceCheckUtils]: 10: Hoare triple {44892#true} assume 0 == ~M_E~0;~M_E~0 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,770 INFO L290 TraceCheckUtils]: 11: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,770 INFO L290 TraceCheckUtils]: 12: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,771 INFO L290 TraceCheckUtils]: 13: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,771 INFO L290 TraceCheckUtils]: 14: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,771 INFO L290 TraceCheckUtils]: 15: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,772 INFO L290 TraceCheckUtils]: 16: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T6_E~0); {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,772 INFO L290 TraceCheckUtils]: 17: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,772 INFO L290 TraceCheckUtils]: 18: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,772 INFO L290 TraceCheckUtils]: 19: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,773 INFO L290 TraceCheckUtils]: 20: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,773 INFO L290 TraceCheckUtils]: 21: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,773 INFO L290 TraceCheckUtils]: 22: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,773 INFO L290 TraceCheckUtils]: 23: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,774 INFO L290 TraceCheckUtils]: 24: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_7~0); {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,774 INFO L290 TraceCheckUtils]: 25: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,774 INFO L290 TraceCheckUtils]: 26: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,775 INFO L290 TraceCheckUtils]: 27: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,775 INFO L290 TraceCheckUtils]: 28: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,775 INFO L290 TraceCheckUtils]: 29: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,775 INFO L290 TraceCheckUtils]: 30: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,776 INFO L290 TraceCheckUtils]: 31: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,776 INFO L290 TraceCheckUtils]: 32: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,776 INFO L290 TraceCheckUtils]: 33: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,777 INFO L290 TraceCheckUtils]: 34: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,777 INFO L290 TraceCheckUtils]: 35: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,777 INFO L290 TraceCheckUtils]: 36: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,777 INFO L290 TraceCheckUtils]: 37: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,778 INFO L290 TraceCheckUtils]: 38: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,778 INFO L290 TraceCheckUtils]: 39: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,778 INFO L290 TraceCheckUtils]: 40: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,779 INFO L290 TraceCheckUtils]: 41: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,779 INFO L290 TraceCheckUtils]: 42: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,779 INFO L290 TraceCheckUtils]: 43: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,779 INFO L290 TraceCheckUtils]: 44: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,780 INFO L290 TraceCheckUtils]: 45: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,780 INFO L290 TraceCheckUtils]: 46: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,780 INFO L290 TraceCheckUtils]: 47: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,780 INFO L290 TraceCheckUtils]: 48: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,781 INFO L290 TraceCheckUtils]: 49: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,781 INFO L290 TraceCheckUtils]: 50: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,781 INFO L290 TraceCheckUtils]: 51: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,782 INFO L290 TraceCheckUtils]: 52: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,782 INFO L290 TraceCheckUtils]: 53: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,782 INFO L290 TraceCheckUtils]: 54: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,782 INFO L290 TraceCheckUtils]: 55: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,783 INFO L290 TraceCheckUtils]: 56: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,783 INFO L290 TraceCheckUtils]: 57: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,783 INFO L290 TraceCheckUtils]: 58: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,784 INFO L290 TraceCheckUtils]: 59: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,784 INFO L290 TraceCheckUtils]: 60: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,784 INFO L290 TraceCheckUtils]: 61: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,784 INFO L290 TraceCheckUtils]: 62: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,785 INFO L290 TraceCheckUtils]: 63: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,785 INFO L290 TraceCheckUtils]: 64: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,785 INFO L290 TraceCheckUtils]: 65: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,785 INFO L290 TraceCheckUtils]: 66: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,786 INFO L290 TraceCheckUtils]: 67: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,786 INFO L290 TraceCheckUtils]: 68: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,786 INFO L290 TraceCheckUtils]: 69: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,787 INFO L290 TraceCheckUtils]: 70: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,787 INFO L290 TraceCheckUtils]: 71: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,787 INFO L290 TraceCheckUtils]: 72: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,787 INFO L290 TraceCheckUtils]: 73: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {44894#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:25,788 INFO L290 TraceCheckUtils]: 74: Hoare triple {44894#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {44893#false} is VALID [2022-02-21 04:24:25,788 INFO L290 TraceCheckUtils]: 75: Hoare triple {44893#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,788 INFO L290 TraceCheckUtils]: 76: Hoare triple {44893#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,788 INFO L290 TraceCheckUtils]: 77: Hoare triple {44893#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,788 INFO L290 TraceCheckUtils]: 78: Hoare triple {44893#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,788 INFO L290 TraceCheckUtils]: 79: Hoare triple {44893#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,788 INFO L290 TraceCheckUtils]: 80: Hoare triple {44893#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,789 INFO L290 TraceCheckUtils]: 81: Hoare triple {44893#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,789 INFO L290 TraceCheckUtils]: 82: Hoare triple {44893#false} assume !(1 == ~E_1~0); {44893#false} is VALID [2022-02-21 04:24:25,789 INFO L290 TraceCheckUtils]: 83: Hoare triple {44893#false} assume 1 == ~E_2~0;~E_2~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,789 INFO L290 TraceCheckUtils]: 84: Hoare triple {44893#false} assume 1 == ~E_3~0;~E_3~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,789 INFO L290 TraceCheckUtils]: 85: Hoare triple {44893#false} assume 1 == ~E_4~0;~E_4~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,789 INFO L290 TraceCheckUtils]: 86: Hoare triple {44893#false} assume 1 == ~E_5~0;~E_5~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,789 INFO L290 TraceCheckUtils]: 87: Hoare triple {44893#false} assume 1 == ~E_6~0;~E_6~0 := 2; {44893#false} is VALID [2022-02-21 04:24:25,789 INFO L290 TraceCheckUtils]: 88: Hoare triple {44893#false} assume !(1 == ~E_7~0); {44893#false} is VALID [2022-02-21 04:24:25,789 INFO L290 TraceCheckUtils]: 89: Hoare triple {44893#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {44893#false} is VALID [2022-02-21 04:24:25,790 INFO L290 TraceCheckUtils]: 90: Hoare triple {44893#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {44893#false} is VALID [2022-02-21 04:24:25,790 INFO L290 TraceCheckUtils]: 91: Hoare triple {44893#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {44893#false} is VALID [2022-02-21 04:24:25,790 INFO L290 TraceCheckUtils]: 92: Hoare triple {44893#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {44893#false} is VALID [2022-02-21 04:24:25,790 INFO L290 TraceCheckUtils]: 93: Hoare triple {44893#false} assume !(0 == start_simulation_~tmp~3#1); {44893#false} is VALID [2022-02-21 04:24:25,790 INFO L290 TraceCheckUtils]: 94: Hoare triple {44893#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {44893#false} is VALID [2022-02-21 04:24:25,790 INFO L290 TraceCheckUtils]: 95: Hoare triple {44893#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {44893#false} is VALID [2022-02-21 04:24:25,790 INFO L290 TraceCheckUtils]: 96: Hoare triple {44893#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {44893#false} is VALID [2022-02-21 04:24:25,790 INFO L290 TraceCheckUtils]: 97: Hoare triple {44893#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {44893#false} is VALID [2022-02-21 04:24:25,790 INFO L290 TraceCheckUtils]: 98: Hoare triple {44893#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {44893#false} is VALID [2022-02-21 04:24:25,791 INFO L290 TraceCheckUtils]: 99: Hoare triple {44893#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {44893#false} is VALID [2022-02-21 04:24:25,791 INFO L290 TraceCheckUtils]: 100: Hoare triple {44893#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {44893#false} is VALID [2022-02-21 04:24:25,791 INFO L290 TraceCheckUtils]: 101: Hoare triple {44893#false} assume !(0 != start_simulation_~tmp___0~1#1); {44893#false} is VALID [2022-02-21 04:24:25,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:25,791 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:25,791 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977735631] [2022-02-21 04:24:25,792 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [977735631] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:25,792 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:25,792 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:25,792 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1056300500] [2022-02-21 04:24:25,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:25,792 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:25,792 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:25,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:24:25,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:24:25,793 INFO L87 Difference]: Start difference. First operand 2645 states and 3848 transitions. cyclomatic complexity: 1207 Second operand has 5 states, 5 states have (on average 18.6) internal successors, (93), 5 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:29,440 INFO L93 Difference]: Finished difference Result 7326 states and 10627 transitions. [2022-02-21 04:24:29,440 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:24:29,440 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 18.6) internal successors, (93), 5 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,493 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:29,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7326 states and 10627 transitions. [2022-02-21 04:24:30,887 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7060 [2022-02-21 04:24:32,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7326 states to 7326 states and 10627 transitions. [2022-02-21 04:24:32,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7326 [2022-02-21 04:24:32,173 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7326 [2022-02-21 04:24:32,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7326 states and 10627 transitions. [2022-02-21 04:24:32,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:32,178 INFO L681 BuchiCegarLoop]: Abstraction has 7326 states and 10627 transitions. [2022-02-21 04:24:32,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7326 states and 10627 transitions. [2022-02-21 04:24:32,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7326 to 2750. [2022-02-21 04:24:32,257 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:32,260 INFO L82 GeneralOperation]: Start isEquivalent. First operand 7326 states and 10627 transitions. Second operand has 2750 states, 2750 states have (on average 1.4374545454545455) internal successors, (3953), 2749 states have internal predecessors, (3953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,261 INFO L74 IsIncluded]: Start isIncluded. First operand 7326 states and 10627 transitions. Second operand has 2750 states, 2750 states have (on average 1.4374545454545455) internal successors, (3953), 2749 states have internal predecessors, (3953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,263 INFO L87 Difference]: Start difference. First operand 7326 states and 10627 transitions. Second operand has 2750 states, 2750 states have (on average 1.4374545454545455) internal successors, (3953), 2749 states have internal predecessors, (3953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:33,342 INFO L93 Difference]: Finished difference Result 7326 states and 10627 transitions. [2022-02-21 04:24:33,342 INFO L276 IsEmpty]: Start isEmpty. Operand 7326 states and 10627 transitions. [2022-02-21 04:24:33,349 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:33,349 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:33,352 INFO L74 IsIncluded]: Start isIncluded. First operand has 2750 states, 2750 states have (on average 1.4374545454545455) internal successors, (3953), 2749 states have internal predecessors, (3953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7326 states and 10627 transitions. [2022-02-21 04:24:33,354 INFO L87 Difference]: Start difference. First operand has 2750 states, 2750 states have (on average 1.4374545454545455) internal successors, (3953), 2749 states have internal predecessors, (3953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7326 states and 10627 transitions. [2022-02-21 04:24:34,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:34,485 INFO L93 Difference]: Finished difference Result 7326 states and 10627 transitions. [2022-02-21 04:24:34,485 INFO L276 IsEmpty]: Start isEmpty. Operand 7326 states and 10627 transitions. [2022-02-21 04:24:34,493 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:34,493 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:34,493 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:34,493 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:34,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2750 states, 2750 states have (on average 1.4374545454545455) internal successors, (3953), 2749 states have internal predecessors, (3953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2750 states to 2750 states and 3953 transitions. [2022-02-21 04:24:34,666 INFO L704 BuchiCegarLoop]: Abstraction has 2750 states and 3953 transitions. [2022-02-21 04:24:34,666 INFO L587 BuchiCegarLoop]: Abstraction has 2750 states and 3953 transitions. [2022-02-21 04:24:34,666 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:24:34,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2750 states and 3953 transitions. [2022-02-21 04:24:34,671 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2632 [2022-02-21 04:24:34,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:34,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:34,672 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:34,672 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:34,672 INFO L791 eck$LassoCheckResult]: Stem: 53173#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 53108#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 53109#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52435#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52436#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 52917#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52918#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52868#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52771#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52772#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52760#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 52761#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52714#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52715#L754 assume !(0 == ~M_E~0); 53059#L754-2 assume !(0 == ~T1_E~0); 52646#L759-1 assume !(0 == ~T2_E~0); 52647#L764-1 assume !(0 == ~T3_E~0); 53129#L769-1 assume !(0 == ~T4_E~0); 53130#L774-1 assume !(0 == ~T5_E~0); 52958#L779-1 assume !(0 == ~T6_E~0); 52682#L784-1 assume !(0 == ~T7_E~0); 52683#L789-1 assume !(0 == ~E_1~0); 52346#L794-1 assume !(0 == ~E_2~0); 52347#L799-1 assume !(0 == ~E_3~0); 53134#L804-1 assume !(0 == ~E_4~0); 53135#L809-1 assume !(0 == ~E_5~0); 52775#L814-1 assume !(0 == ~E_6~0); 52265#L819-1 assume !(0 == ~E_7~0); 52266#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52756#L361 assume !(1 == ~m_pc~0); 52757#L361-2 is_master_triggered_~__retres1~0#1 := 0; 52803#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52558#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 52559#L930 assume !(0 != activate_threads_~tmp~1#1); 52950#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52749#L380 assume !(1 == ~t1_pc~0); 52399#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52982#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52983#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53172#L938 assume !(0 != activate_threads_~tmp___0~0#1); 52478#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52400#L399 assume 1 == ~t2_pc~0; 52401#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52615#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52999#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 52827#L946 assume !(0 != activate_threads_~tmp___1~0#1); 52301#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52269#L418 assume !(1 == ~t3_pc~0); 52230#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 52231#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52779#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 53083#L954 assume !(0 != activate_threads_~tmp___2~0#1); 53154#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53062#L437 assume 1 == ~t4_pc~0; 53063#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52580#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52403#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52404#L962 assume !(0 != activate_threads_~tmp___3~0#1); 52882#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52535#L456 assume !(1 == ~t5_pc~0); 52536#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52643#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53031#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 52291#L970 assume !(0 != activate_threads_~tmp___4~0#1); 52292#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52419#L475 assume 1 == ~t6_pc~0; 52420#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52499#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52500#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52251#L978 assume !(0 != activate_threads_~tmp___5~0#1); 52252#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52764#L494 assume !(1 == ~t7_pc~0); 52766#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 52809#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53026#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53027#L986 assume !(0 != activate_threads_~tmp___6~0#1); 53168#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53028#L837 assume !(1 == ~M_E~0); 52830#L837-2 assume !(1 == ~T1_E~0); 52381#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52382#L847-1 assume !(1 == ~T3_E~0); 53848#L852-1 assume !(1 == ~T4_E~0); 53847#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53846#L862-1 assume !(1 == ~T6_E~0); 52842#L867-1 assume !(1 == ~T7_E~0); 53845#L872-1 assume !(1 == ~E_1~0); 53843#L877-1 assume !(1 == ~E_2~0); 52853#L882-1 assume !(1 == ~E_3~0); 52854#L887-1 assume !(1 == ~E_4~0); 52443#L892-1 assume !(1 == ~E_5~0); 52444#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 53015#L902-1 assume !(1 == ~E_7~0); 52527#L907-1 assume { :end_inline_reset_delta_events } true; 52528#L1148-2 [2022-02-21 04:24:34,673 INFO L793 eck$LassoCheckResult]: Loop: 52528#L1148-2 assume !false; 52942#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53716#L729 assume !false; 53161#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 52675#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 52621#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 53707#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 53706#L626 assume !(0 != eval_~tmp~0#1); 53705#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53703#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53701#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53699#L754-5 assume !(0 == ~T1_E~0); 53696#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53695#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53694#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53693#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52626#L779-3 assume !(0 == ~T6_E~0); 52278#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52279#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53671#L794-3 assume !(0 == ~E_2~0); 53670#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53669#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 53668#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53667#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53666#L819-3 assume !(0 == ~E_7~0); 52562#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52563#L361-24 assume !(1 == ~m_pc~0); 52951#L361-26 is_master_triggered_~__retres1~0#1 := 0; 54357#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54356#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54355#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 54354#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54353#L380-24 assume !(1 == ~t1_pc~0); 54352#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 54350#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54348#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54346#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 54344#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54343#L399-24 assume 1 == ~t2_pc~0; 54341#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54340#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54339#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54338#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54337#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54336#L418-24 assume !(1 == ~t3_pc~0); 54334#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 54333#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54332#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 54331#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54330#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54329#L437-24 assume 1 == ~t4_pc~0; 54327#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54326#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54325#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54324#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54323#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54322#L456-24 assume !(1 == ~t5_pc~0); 54320#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 54319#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54318#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 54317#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 54316#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54315#L475-24 assume 1 == ~t6_pc~0; 54313#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53100#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53041#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53042#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 52236#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52237#L494-24 assume !(1 == ~t7_pc~0); 54074#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 54073#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54072#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54071#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54069#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54068#L837-3 assume !(1 == ~M_E~0); 54067#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54066#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52903#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52282#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52283#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53099#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53085#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52974#L872-3 assume !(1 == ~E_1~0); 52975#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53092#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53124#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53143#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54048#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54046#L902-3 assume !(1 == ~E_7~0); 52869#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 52859#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 52268#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 53159#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 53054#L1167 assume !(0 == start_simulation_~tmp~3#1); 52904#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 52944#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 52689#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 52998#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 53094#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 52927#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52244#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 52245#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 52528#L1148-2 [2022-02-21 04:24:34,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:34,673 INFO L85 PathProgramCache]: Analyzing trace with hash -1406363737, now seen corresponding path program 1 times [2022-02-21 04:24:34,673 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:34,673 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905111785] [2022-02-21 04:24:34,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:34,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:34,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:34,699 INFO L290 TraceCheckUtils]: 0: Hoare triple {69630#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,699 INFO L290 TraceCheckUtils]: 1: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,699 INFO L290 TraceCheckUtils]: 2: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,700 INFO L290 TraceCheckUtils]: 3: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,700 INFO L290 TraceCheckUtils]: 4: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,700 INFO L290 TraceCheckUtils]: 5: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,700 INFO L290 TraceCheckUtils]: 6: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,700 INFO L290 TraceCheckUtils]: 7: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,701 INFO L290 TraceCheckUtils]: 8: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,701 INFO L290 TraceCheckUtils]: 9: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,701 INFO L290 TraceCheckUtils]: 10: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,701 INFO L290 TraceCheckUtils]: 11: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,702 INFO L290 TraceCheckUtils]: 12: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,702 INFO L290 TraceCheckUtils]: 13: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~M_E~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,702 INFO L290 TraceCheckUtils]: 14: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T1_E~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,703 INFO L290 TraceCheckUtils]: 15: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T2_E~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,703 INFO L290 TraceCheckUtils]: 16: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T3_E~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,703 INFO L290 TraceCheckUtils]: 17: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T4_E~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,703 INFO L290 TraceCheckUtils]: 18: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T5_E~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 19: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T6_E~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 20: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T7_E~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 21: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_1~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 22: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_2~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,705 INFO L290 TraceCheckUtils]: 23: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_3~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,705 INFO L290 TraceCheckUtils]: 24: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_4~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,705 INFO L290 TraceCheckUtils]: 25: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_5~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,705 INFO L290 TraceCheckUtils]: 26: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_6~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 27: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_7~0); {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 28: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {69632#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 29: Hoare triple {69632#(= ~m_pc~0 ~t2_pc~0)} assume !(1 == ~m_pc~0); {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 30: Hoare triple {69633#(not (= ~t2_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,707 INFO L290 TraceCheckUtils]: 31: Hoare triple {69633#(not (= ~t2_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,707 INFO L290 TraceCheckUtils]: 32: Hoare triple {69633#(not (= ~t2_pc~0 1))} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,707 INFO L290 TraceCheckUtils]: 33: Hoare triple {69633#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 34: Hoare triple {69633#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 35: Hoare triple {69633#(not (= ~t2_pc~0 1))} assume !(1 == ~t1_pc~0); {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 36: Hoare triple {69633#(not (= ~t2_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 37: Hoare triple {69633#(not (= ~t2_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 38: Hoare triple {69633#(not (= ~t2_pc~0 1))} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 39: Hoare triple {69633#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 40: Hoare triple {69633#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {69633#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 41: Hoare triple {69633#(not (= ~t2_pc~0 1))} assume 1 == ~t2_pc~0; {69631#false} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 42: Hoare triple {69631#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {69631#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 43: Hoare triple {69631#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {69631#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 44: Hoare triple {69631#false} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {69631#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 45: Hoare triple {69631#false} assume !(0 != activate_threads_~tmp___1~0#1); {69631#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 46: Hoare triple {69631#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {69631#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 47: Hoare triple {69631#false} assume !(1 == ~t3_pc~0); {69631#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 48: Hoare triple {69631#false} is_transmit3_triggered_~__retres1~3#1 := 0; {69631#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 49: Hoare triple {69631#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {69631#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 50: Hoare triple {69631#false} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {69631#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 51: Hoare triple {69631#false} assume !(0 != activate_threads_~tmp___2~0#1); {69631#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 52: Hoare triple {69631#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {69631#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 53: Hoare triple {69631#false} assume 1 == ~t4_pc~0; {69631#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 54: Hoare triple {69631#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {69631#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 55: Hoare triple {69631#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {69631#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 56: Hoare triple {69631#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {69631#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 57: Hoare triple {69631#false} assume !(0 != activate_threads_~tmp___3~0#1); {69631#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 58: Hoare triple {69631#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {69631#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 59: Hoare triple {69631#false} assume !(1 == ~t5_pc~0); {69631#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 60: Hoare triple {69631#false} is_transmit5_triggered_~__retres1~5#1 := 0; {69631#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 61: Hoare triple {69631#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {69631#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 62: Hoare triple {69631#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {69631#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 63: Hoare triple {69631#false} assume !(0 != activate_threads_~tmp___4~0#1); {69631#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 64: Hoare triple {69631#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {69631#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 65: Hoare triple {69631#false} assume 1 == ~t6_pc~0; {69631#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 66: Hoare triple {69631#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {69631#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 67: Hoare triple {69631#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {69631#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 68: Hoare triple {69631#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {69631#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 69: Hoare triple {69631#false} assume !(0 != activate_threads_~tmp___5~0#1); {69631#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 70: Hoare triple {69631#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {69631#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 71: Hoare triple {69631#false} assume !(1 == ~t7_pc~0); {69631#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 72: Hoare triple {69631#false} is_transmit7_triggered_~__retres1~7#1 := 0; {69631#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 73: Hoare triple {69631#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {69631#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 74: Hoare triple {69631#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {69631#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 75: Hoare triple {69631#false} assume !(0 != activate_threads_~tmp___6~0#1); {69631#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 76: Hoare triple {69631#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {69631#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 77: Hoare triple {69631#false} assume !(1 == ~M_E~0); {69631#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 78: Hoare triple {69631#false} assume !(1 == ~T1_E~0); {69631#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 79: Hoare triple {69631#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {69631#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 80: Hoare triple {69631#false} assume !(1 == ~T3_E~0); {69631#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 81: Hoare triple {69631#false} assume !(1 == ~T4_E~0); {69631#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 82: Hoare triple {69631#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {69631#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 83: Hoare triple {69631#false} assume !(1 == ~T6_E~0); {69631#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 84: Hoare triple {69631#false} assume !(1 == ~T7_E~0); {69631#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 85: Hoare triple {69631#false} assume !(1 == ~E_1~0); {69631#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 86: Hoare triple {69631#false} assume !(1 == ~E_2~0); {69631#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 87: Hoare triple {69631#false} assume !(1 == ~E_3~0); {69631#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 88: Hoare triple {69631#false} assume !(1 == ~E_4~0); {69631#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 89: Hoare triple {69631#false} assume !(1 == ~E_5~0); {69631#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 90: Hoare triple {69631#false} assume 1 == ~E_6~0;~E_6~0 := 2; {69631#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 91: Hoare triple {69631#false} assume !(1 == ~E_7~0); {69631#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 92: Hoare triple {69631#false} assume { :end_inline_reset_delta_events } true; {69631#false} is VALID [2022-02-21 04:24:34,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:34,715 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:34,715 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905111785] [2022-02-21 04:24:34,715 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905111785] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:34,717 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:34,717 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:34,718 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178793273] [2022-02-21 04:24:34,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:34,718 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:34,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:34,718 INFO L85 PathProgramCache]: Analyzing trace with hash 622834652, now seen corresponding path program 1 times [2022-02-21 04:24:34,718 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:34,719 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961086949] [2022-02-21 04:24:34,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:34,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:34,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:34,739 INFO L290 TraceCheckUtils]: 0: Hoare triple {69634#true} assume !false; {69634#true} is VALID [2022-02-21 04:24:34,740 INFO L290 TraceCheckUtils]: 1: Hoare triple {69634#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {69634#true} is VALID [2022-02-21 04:24:34,740 INFO L290 TraceCheckUtils]: 2: Hoare triple {69634#true} assume !false; {69634#true} is VALID [2022-02-21 04:24:34,740 INFO L290 TraceCheckUtils]: 3: Hoare triple {69634#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {69634#true} is VALID [2022-02-21 04:24:34,740 INFO L290 TraceCheckUtils]: 4: Hoare triple {69634#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {69634#true} is VALID [2022-02-21 04:24:34,740 INFO L290 TraceCheckUtils]: 5: Hoare triple {69634#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {69634#true} is VALID [2022-02-21 04:24:34,740 INFO L290 TraceCheckUtils]: 6: Hoare triple {69634#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {69634#true} is VALID [2022-02-21 04:24:34,740 INFO L290 TraceCheckUtils]: 7: Hoare triple {69634#true} assume !(0 != eval_~tmp~0#1); {69634#true} is VALID [2022-02-21 04:24:34,740 INFO L290 TraceCheckUtils]: 8: Hoare triple {69634#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {69634#true} is VALID [2022-02-21 04:24:34,741 INFO L290 TraceCheckUtils]: 9: Hoare triple {69634#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {69634#true} is VALID [2022-02-21 04:24:34,741 INFO L290 TraceCheckUtils]: 10: Hoare triple {69634#true} assume 0 == ~M_E~0;~M_E~0 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,741 INFO L290 TraceCheckUtils]: 11: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,741 INFO L290 TraceCheckUtils]: 12: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,742 INFO L290 TraceCheckUtils]: 13: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,742 INFO L290 TraceCheckUtils]: 14: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,742 INFO L290 TraceCheckUtils]: 15: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,742 INFO L290 TraceCheckUtils]: 16: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T6_E~0); {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,743 INFO L290 TraceCheckUtils]: 17: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,743 INFO L290 TraceCheckUtils]: 18: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,743 INFO L290 TraceCheckUtils]: 19: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,743 INFO L290 TraceCheckUtils]: 20: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,744 INFO L290 TraceCheckUtils]: 21: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,744 INFO L290 TraceCheckUtils]: 22: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,744 INFO L290 TraceCheckUtils]: 23: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,745 INFO L290 TraceCheckUtils]: 24: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_7~0); {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,745 INFO L290 TraceCheckUtils]: 25: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,745 INFO L290 TraceCheckUtils]: 26: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,745 INFO L290 TraceCheckUtils]: 27: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,746 INFO L290 TraceCheckUtils]: 28: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,746 INFO L290 TraceCheckUtils]: 29: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,746 INFO L290 TraceCheckUtils]: 30: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,746 INFO L290 TraceCheckUtils]: 31: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,747 INFO L290 TraceCheckUtils]: 32: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,747 INFO L290 TraceCheckUtils]: 33: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,747 INFO L290 TraceCheckUtils]: 34: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,747 INFO L290 TraceCheckUtils]: 35: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,748 INFO L290 TraceCheckUtils]: 36: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___0~0#1); {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,748 INFO L290 TraceCheckUtils]: 37: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,748 INFO L290 TraceCheckUtils]: 38: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t2_pc~0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,748 INFO L290 TraceCheckUtils]: 39: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,749 INFO L290 TraceCheckUtils]: 40: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,749 INFO L290 TraceCheckUtils]: 41: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,749 INFO L290 TraceCheckUtils]: 42: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,750 INFO L290 TraceCheckUtils]: 43: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,750 INFO L290 TraceCheckUtils]: 44: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,750 INFO L290 TraceCheckUtils]: 45: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,750 INFO L290 TraceCheckUtils]: 46: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,751 INFO L290 TraceCheckUtils]: 47: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,751 INFO L290 TraceCheckUtils]: 48: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,751 INFO L290 TraceCheckUtils]: 49: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,751 INFO L290 TraceCheckUtils]: 50: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t4_pc~0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,752 INFO L290 TraceCheckUtils]: 51: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,752 INFO L290 TraceCheckUtils]: 52: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,752 INFO L290 TraceCheckUtils]: 53: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,753 INFO L290 TraceCheckUtils]: 54: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,753 INFO L290 TraceCheckUtils]: 55: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,753 INFO L290 TraceCheckUtils]: 56: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,754 INFO L290 TraceCheckUtils]: 57: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,754 INFO L290 TraceCheckUtils]: 58: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,754 INFO L290 TraceCheckUtils]: 59: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,755 INFO L290 TraceCheckUtils]: 60: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,755 INFO L290 TraceCheckUtils]: 61: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,755 INFO L290 TraceCheckUtils]: 62: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t6_pc~0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,755 INFO L290 TraceCheckUtils]: 63: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,756 INFO L290 TraceCheckUtils]: 64: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,756 INFO L290 TraceCheckUtils]: 65: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,756 INFO L290 TraceCheckUtils]: 66: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,756 INFO L290 TraceCheckUtils]: 67: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,757 INFO L290 TraceCheckUtils]: 68: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,757 INFO L290 TraceCheckUtils]: 69: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,757 INFO L290 TraceCheckUtils]: 70: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,757 INFO L290 TraceCheckUtils]: 71: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,758 INFO L290 TraceCheckUtils]: 72: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,758 INFO L290 TraceCheckUtils]: 73: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {69636#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:34,758 INFO L290 TraceCheckUtils]: 74: Hoare triple {69636#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {69635#false} is VALID [2022-02-21 04:24:34,758 INFO L290 TraceCheckUtils]: 75: Hoare triple {69635#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,758 INFO L290 TraceCheckUtils]: 76: Hoare triple {69635#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,759 INFO L290 TraceCheckUtils]: 77: Hoare triple {69635#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,759 INFO L290 TraceCheckUtils]: 78: Hoare triple {69635#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,759 INFO L290 TraceCheckUtils]: 79: Hoare triple {69635#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,759 INFO L290 TraceCheckUtils]: 80: Hoare triple {69635#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,759 INFO L290 TraceCheckUtils]: 81: Hoare triple {69635#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,759 INFO L290 TraceCheckUtils]: 82: Hoare triple {69635#false} assume !(1 == ~E_1~0); {69635#false} is VALID [2022-02-21 04:24:34,759 INFO L290 TraceCheckUtils]: 83: Hoare triple {69635#false} assume 1 == ~E_2~0;~E_2~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,759 INFO L290 TraceCheckUtils]: 84: Hoare triple {69635#false} assume 1 == ~E_3~0;~E_3~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,759 INFO L290 TraceCheckUtils]: 85: Hoare triple {69635#false} assume 1 == ~E_4~0;~E_4~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,760 INFO L290 TraceCheckUtils]: 86: Hoare triple {69635#false} assume 1 == ~E_5~0;~E_5~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,760 INFO L290 TraceCheckUtils]: 87: Hoare triple {69635#false} assume 1 == ~E_6~0;~E_6~0 := 2; {69635#false} is VALID [2022-02-21 04:24:34,760 INFO L290 TraceCheckUtils]: 88: Hoare triple {69635#false} assume !(1 == ~E_7~0); {69635#false} is VALID [2022-02-21 04:24:34,760 INFO L290 TraceCheckUtils]: 89: Hoare triple {69635#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {69635#false} is VALID [2022-02-21 04:24:34,760 INFO L290 TraceCheckUtils]: 90: Hoare triple {69635#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {69635#false} is VALID [2022-02-21 04:24:34,760 INFO L290 TraceCheckUtils]: 91: Hoare triple {69635#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {69635#false} is VALID [2022-02-21 04:24:34,760 INFO L290 TraceCheckUtils]: 92: Hoare triple {69635#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {69635#false} is VALID [2022-02-21 04:24:34,760 INFO L290 TraceCheckUtils]: 93: Hoare triple {69635#false} assume !(0 == start_simulation_~tmp~3#1); {69635#false} is VALID [2022-02-21 04:24:34,760 INFO L290 TraceCheckUtils]: 94: Hoare triple {69635#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {69635#false} is VALID [2022-02-21 04:24:34,760 INFO L290 TraceCheckUtils]: 95: Hoare triple {69635#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {69635#false} is VALID [2022-02-21 04:24:34,761 INFO L290 TraceCheckUtils]: 96: Hoare triple {69635#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {69635#false} is VALID [2022-02-21 04:24:34,761 INFO L290 TraceCheckUtils]: 97: Hoare triple {69635#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {69635#false} is VALID [2022-02-21 04:24:34,761 INFO L290 TraceCheckUtils]: 98: Hoare triple {69635#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {69635#false} is VALID [2022-02-21 04:24:34,761 INFO L290 TraceCheckUtils]: 99: Hoare triple {69635#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {69635#false} is VALID [2022-02-21 04:24:34,761 INFO L290 TraceCheckUtils]: 100: Hoare triple {69635#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {69635#false} is VALID [2022-02-21 04:24:34,761 INFO L290 TraceCheckUtils]: 101: Hoare triple {69635#false} assume !(0 != start_simulation_~tmp___0~1#1); {69635#false} is VALID [2022-02-21 04:24:34,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:34,762 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:34,762 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961086949] [2022-02-21 04:24:34,762 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961086949] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:34,762 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:34,762 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:34,762 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787409167] [2022-02-21 04:24:34,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:34,762 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:34,763 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:34,763 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:34,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:34,763 INFO L87 Difference]: Start difference. First operand 2750 states and 3953 transitions. cyclomatic complexity: 1207 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:37,373 INFO L93 Difference]: Finished difference Result 6499 states and 9249 transitions. [2022-02-21 04:24:37,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:37,374 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,436 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:37,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6499 states and 9249 transitions. [2022-02-21 04:24:38,412 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6246 [2022-02-21 04:24:39,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6499 states to 6499 states and 9249 transitions. [2022-02-21 04:24:39,440 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6499 [2022-02-21 04:24:39,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6499 [2022-02-21 04:24:39,443 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6499 states and 9249 transitions. [2022-02-21 04:24:39,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:39,447 INFO L681 BuchiCegarLoop]: Abstraction has 6499 states and 9249 transitions. [2022-02-21 04:24:39,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6499 states and 9249 transitions. [2022-02-21 04:24:39,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6499 to 5099. [2022-02-21 04:24:39,519 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:39,524 INFO L82 GeneralOperation]: Start isEquivalent. First operand 6499 states and 9249 transitions. Second operand has 5099 states, 5099 states have (on average 1.4300843302608355) internal successors, (7292), 5098 states have internal predecessors, (7292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,528 INFO L74 IsIncluded]: Start isIncluded. First operand 6499 states and 9249 transitions. Second operand has 5099 states, 5099 states have (on average 1.4300843302608355) internal successors, (7292), 5098 states have internal predecessors, (7292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,533 INFO L87 Difference]: Start difference. First operand 6499 states and 9249 transitions. Second operand has 5099 states, 5099 states have (on average 1.4300843302608355) internal successors, (7292), 5098 states have internal predecessors, (7292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,412 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:40,412 INFO L93 Difference]: Finished difference Result 6499 states and 9249 transitions. [2022-02-21 04:24:40,412 INFO L276 IsEmpty]: Start isEmpty. Operand 6499 states and 9249 transitions. [2022-02-21 04:24:40,418 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:40,419 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:40,423 INFO L74 IsIncluded]: Start isIncluded. First operand has 5099 states, 5099 states have (on average 1.4300843302608355) internal successors, (7292), 5098 states have internal predecessors, (7292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6499 states and 9249 transitions. [2022-02-21 04:24:40,426 INFO L87 Difference]: Start difference. First operand has 5099 states, 5099 states have (on average 1.4300843302608355) internal successors, (7292), 5098 states have internal predecessors, (7292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6499 states and 9249 transitions. [2022-02-21 04:24:41,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:41,301 INFO L93 Difference]: Finished difference Result 6499 states and 9249 transitions. [2022-02-21 04:24:41,301 INFO L276 IsEmpty]: Start isEmpty. Operand 6499 states and 9249 transitions. [2022-02-21 04:24:41,308 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:41,308 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:41,308 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:41,308 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:41,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5099 states, 5099 states have (on average 1.4300843302608355) internal successors, (7292), 5098 states have internal predecessors, (7292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5099 states to 5099 states and 7292 transitions. [2022-02-21 04:24:41,879 INFO L704 BuchiCegarLoop]: Abstraction has 5099 states and 7292 transitions. [2022-02-21 04:24:41,879 INFO L587 BuchiCegarLoop]: Abstraction has 5099 states and 7292 transitions. [2022-02-21 04:24:41,879 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:24:41,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5099 states and 7292 transitions. [2022-02-21 04:24:41,888 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4980 [2022-02-21 04:24:41,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:41,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:41,890 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:41,890 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:41,891 INFO L791 eck$LassoCheckResult]: Stem: 77013#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 76966#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 76967#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76347#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76348#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 76803#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76804#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76766#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76675#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76676#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76667#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76668#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76626#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76627#L754 assume !(0 == ~M_E~0); 76927#L754-2 assume !(0 == ~T1_E~0); 76555#L759-1 assume !(0 == ~T2_E~0); 76556#L764-1 assume !(0 == ~T3_E~0); 76981#L769-1 assume !(0 == ~T4_E~0); 76982#L774-1 assume !(0 == ~T5_E~0); 76836#L779-1 assume !(0 == ~T6_E~0); 76593#L784-1 assume !(0 == ~T7_E~0); 76594#L789-1 assume !(0 == ~E_1~0); 76255#L794-1 assume !(0 == ~E_2~0); 76256#L799-1 assume !(0 == ~E_3~0); 76984#L804-1 assume !(0 == ~E_4~0); 76985#L809-1 assume !(0 == ~E_5~0); 76680#L814-1 assume !(0 == ~E_6~0); 76174#L819-1 assume !(0 == ~E_7~0); 76175#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76664#L361 assume !(1 == ~m_pc~0); 76665#L361-2 is_master_triggered_~__retres1~0#1 := 0; 76705#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76470#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 76471#L930 assume !(0 != activate_threads_~tmp~1#1); 76832#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76658#L380 assume !(1 == ~t1_pc~0); 76311#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 76857#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76858#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76974#L938 assume !(0 != activate_threads_~tmp___0~0#1); 76388#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76312#L399 assume !(1 == ~t2_pc~0); 76313#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76526#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76870#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76729#L946 assume !(0 != activate_threads_~tmp___1~0#1); 76214#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76182#L418 assume !(1 == ~t3_pc~0); 76143#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 76144#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76684#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 76943#L954 assume !(0 != activate_threads_~tmp___2~0#1); 77000#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76929#L437 assume 1 == ~t4_pc~0; 76930#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 76491#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76314#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76315#L962 assume !(0 != activate_threads_~tmp___3~0#1); 76776#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76440#L456 assume !(1 == ~t5_pc~0); 76441#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 76552#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76905#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76201#L970 assume !(0 != activate_threads_~tmp___4~0#1); 76202#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76327#L475 assume 1 == ~t6_pc~0; 76328#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76407#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76408#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76164#L978 assume !(0 != activate_threads_~tmp___5~0#1); 76165#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76671#L494 assume !(1 == ~t7_pc~0); 76673#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 76713#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76895#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76896#L986 assume !(0 != activate_threads_~tmp___6~0#1); 77009#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76897#L837 assume !(1 == ~M_E~0); 76732#L837-2 assume !(1 == ~T1_E~0); 76293#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76294#L847-1 assume !(1 == ~T3_E~0); 76800#L852-1 assume !(1 == ~T4_E~0); 77021#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77022#L862-1 assume !(1 == ~T6_E~0); 76742#L867-1 assume !(1 == ~T7_E~0); 76756#L872-1 assume !(1 == ~E_1~0); 77019#L877-1 assume !(1 == ~E_2~0); 77020#L882-1 assume !(1 == ~E_3~0); 76955#L887-1 assume !(1 == ~E_4~0); 76956#L892-1 assume !(1 == ~E_5~0); 76883#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 76884#L902-1 assume !(1 == ~E_7~0); 76436#L907-1 assume { :end_inline_reset_delta_events } true; 76437#L1148-2 [2022-02-21 04:24:41,891 INFO L793 eck$LassoCheckResult]: Loop: 76437#L1148-2 assume !false; 76176#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76177#L729 assume !false; 76588#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 76582#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 76532#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 76608#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 76651#L626 assume !(0 != eval_~tmp~0#1); 76652#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76801#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76688#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 76215#L754-5 assume !(0 == ~T1_E~0); 76216#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 80856#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 80938#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 80937#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 80936#L779-3 assume !(0 == ~T6_E~0); 80935#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 80934#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 80933#L794-3 assume !(0 == ~E_2~0); 80932#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80931#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 80930#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 80929#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 80928#L819-3 assume !(0 == ~E_7~0); 80927#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80926#L361-24 assume !(1 == ~m_pc~0); 80925#L361-26 is_master_triggered_~__retres1~0#1 := 0; 80924#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80923#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 80922#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 80921#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80920#L380-24 assume !(1 == ~t1_pc~0); 80917#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 80915#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80914#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 80913#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 80911#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80910#L399-24 assume !(1 == ~t2_pc~0); 79141#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 80909#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80908#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 80907#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80906#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80905#L418-24 assume !(1 == ~t3_pc~0); 80903#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 80902#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80901#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 80900#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 80899#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 80898#L437-24 assume !(1 == ~t4_pc~0); 80897#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 80895#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80894#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 80893#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 80892#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80891#L456-24 assume !(1 == ~t5_pc~0); 80889#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 80888#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80887#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 80886#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 80885#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80884#L475-24 assume !(1 == ~t6_pc~0); 80883#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 80881#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80880#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 80879#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 80878#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 80877#L494-24 assume !(1 == ~t7_pc~0); 80875#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 80874#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 80873#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 80872#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 80871#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 80870#L837-3 assume !(1 == ~M_E~0); 80869#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 80868#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76900#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 80867#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 80866#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 80828#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76947#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 76853#L872-3 assume !(1 == ~E_1~0); 76854#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 76952#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76978#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 76573#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 76568#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 76569#L902-3 assume !(1 == ~E_7~0); 76767#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 76759#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 76181#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 77003#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 76925#L1167 assume !(0 == start_simulation_~tmp~3#1); 76798#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 76825#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 76604#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 76869#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 76918#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76811#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 76157#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 76158#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 76437#L1148-2 [2022-02-21 04:24:41,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:41,892 INFO L85 PathProgramCache]: Analyzing trace with hash -2107931962, now seen corresponding path program 1 times [2022-02-21 04:24:41,892 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:41,892 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963888117] [2022-02-21 04:24:41,892 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:41,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:41,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:41,918 INFO L290 TraceCheckUtils]: 0: Hoare triple {94238#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,918 INFO L290 TraceCheckUtils]: 1: Hoare triple {94240#(<= ~t4_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,919 INFO L290 TraceCheckUtils]: 2: Hoare triple {94240#(<= ~t4_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,919 INFO L290 TraceCheckUtils]: 3: Hoare triple {94240#(<= ~t4_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,919 INFO L290 TraceCheckUtils]: 4: Hoare triple {94240#(<= ~t4_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,919 INFO L290 TraceCheckUtils]: 5: Hoare triple {94240#(<= ~t4_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,920 INFO L290 TraceCheckUtils]: 6: Hoare triple {94240#(<= ~t4_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,920 INFO L290 TraceCheckUtils]: 7: Hoare triple {94240#(<= ~t4_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,920 INFO L290 TraceCheckUtils]: 8: Hoare triple {94240#(<= ~t4_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,920 INFO L290 TraceCheckUtils]: 9: Hoare triple {94240#(<= ~t4_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,921 INFO L290 TraceCheckUtils]: 10: Hoare triple {94240#(<= ~t4_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,921 INFO L290 TraceCheckUtils]: 11: Hoare triple {94240#(<= ~t4_pc~0 0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,921 INFO L290 TraceCheckUtils]: 12: Hoare triple {94240#(<= ~t4_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,921 INFO L290 TraceCheckUtils]: 13: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~M_E~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,922 INFO L290 TraceCheckUtils]: 14: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~T1_E~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,922 INFO L290 TraceCheckUtils]: 15: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~T2_E~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,922 INFO L290 TraceCheckUtils]: 16: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~T3_E~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,922 INFO L290 TraceCheckUtils]: 17: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~T4_E~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,923 INFO L290 TraceCheckUtils]: 18: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~T5_E~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,923 INFO L290 TraceCheckUtils]: 19: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~T6_E~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,923 INFO L290 TraceCheckUtils]: 20: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~T7_E~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,923 INFO L290 TraceCheckUtils]: 21: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~E_1~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,924 INFO L290 TraceCheckUtils]: 22: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~E_2~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,924 INFO L290 TraceCheckUtils]: 23: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~E_3~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,924 INFO L290 TraceCheckUtils]: 24: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~E_4~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,924 INFO L290 TraceCheckUtils]: 25: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~E_5~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,925 INFO L290 TraceCheckUtils]: 26: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~E_6~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,925 INFO L290 TraceCheckUtils]: 27: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 == ~E_7~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,925 INFO L290 TraceCheckUtils]: 28: Hoare triple {94240#(<= ~t4_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,925 INFO L290 TraceCheckUtils]: 29: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(1 == ~m_pc~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,926 INFO L290 TraceCheckUtils]: 30: Hoare triple {94240#(<= ~t4_pc~0 0)} is_master_triggered_~__retres1~0#1 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,926 INFO L290 TraceCheckUtils]: 31: Hoare triple {94240#(<= ~t4_pc~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,926 INFO L290 TraceCheckUtils]: 32: Hoare triple {94240#(<= ~t4_pc~0 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,927 INFO L290 TraceCheckUtils]: 33: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp~1#1); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,927 INFO L290 TraceCheckUtils]: 34: Hoare triple {94240#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,927 INFO L290 TraceCheckUtils]: 35: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(1 == ~t1_pc~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,927 INFO L290 TraceCheckUtils]: 36: Hoare triple {94240#(<= ~t4_pc~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,928 INFO L290 TraceCheckUtils]: 37: Hoare triple {94240#(<= ~t4_pc~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,928 INFO L290 TraceCheckUtils]: 38: Hoare triple {94240#(<= ~t4_pc~0 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,928 INFO L290 TraceCheckUtils]: 39: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,928 INFO L290 TraceCheckUtils]: 40: Hoare triple {94240#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,929 INFO L290 TraceCheckUtils]: 41: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(1 == ~t2_pc~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,929 INFO L290 TraceCheckUtils]: 42: Hoare triple {94240#(<= ~t4_pc~0 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,929 INFO L290 TraceCheckUtils]: 43: Hoare triple {94240#(<= ~t4_pc~0 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,929 INFO L290 TraceCheckUtils]: 44: Hoare triple {94240#(<= ~t4_pc~0 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,930 INFO L290 TraceCheckUtils]: 45: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___1~0#1); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,930 INFO L290 TraceCheckUtils]: 46: Hoare triple {94240#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,930 INFO L290 TraceCheckUtils]: 47: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(1 == ~t3_pc~0); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,930 INFO L290 TraceCheckUtils]: 48: Hoare triple {94240#(<= ~t4_pc~0 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,931 INFO L290 TraceCheckUtils]: 49: Hoare triple {94240#(<= ~t4_pc~0 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,931 INFO L290 TraceCheckUtils]: 50: Hoare triple {94240#(<= ~t4_pc~0 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,931 INFO L290 TraceCheckUtils]: 51: Hoare triple {94240#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___2~0#1); {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,931 INFO L290 TraceCheckUtils]: 52: Hoare triple {94240#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {94240#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:24:41,932 INFO L290 TraceCheckUtils]: 53: Hoare triple {94240#(<= ~t4_pc~0 0)} assume 1 == ~t4_pc~0; {94239#false} is VALID [2022-02-21 04:24:41,932 INFO L290 TraceCheckUtils]: 54: Hoare triple {94239#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {94239#false} is VALID [2022-02-21 04:24:41,932 INFO L290 TraceCheckUtils]: 55: Hoare triple {94239#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {94239#false} is VALID [2022-02-21 04:24:41,932 INFO L290 TraceCheckUtils]: 56: Hoare triple {94239#false} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {94239#false} is VALID [2022-02-21 04:24:41,932 INFO L290 TraceCheckUtils]: 57: Hoare triple {94239#false} assume !(0 != activate_threads_~tmp___3~0#1); {94239#false} is VALID [2022-02-21 04:24:41,932 INFO L290 TraceCheckUtils]: 58: Hoare triple {94239#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {94239#false} is VALID [2022-02-21 04:24:41,932 INFO L290 TraceCheckUtils]: 59: Hoare triple {94239#false} assume !(1 == ~t5_pc~0); {94239#false} is VALID [2022-02-21 04:24:41,932 INFO L290 TraceCheckUtils]: 60: Hoare triple {94239#false} is_transmit5_triggered_~__retres1~5#1 := 0; {94239#false} is VALID [2022-02-21 04:24:41,933 INFO L290 TraceCheckUtils]: 61: Hoare triple {94239#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {94239#false} is VALID [2022-02-21 04:24:41,933 INFO L290 TraceCheckUtils]: 62: Hoare triple {94239#false} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {94239#false} is VALID [2022-02-21 04:24:41,933 INFO L290 TraceCheckUtils]: 63: Hoare triple {94239#false} assume !(0 != activate_threads_~tmp___4~0#1); {94239#false} is VALID [2022-02-21 04:24:41,933 INFO L290 TraceCheckUtils]: 64: Hoare triple {94239#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {94239#false} is VALID [2022-02-21 04:24:41,933 INFO L290 TraceCheckUtils]: 65: Hoare triple {94239#false} assume 1 == ~t6_pc~0; {94239#false} is VALID [2022-02-21 04:24:41,933 INFO L290 TraceCheckUtils]: 66: Hoare triple {94239#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {94239#false} is VALID [2022-02-21 04:24:41,933 INFO L290 TraceCheckUtils]: 67: Hoare triple {94239#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {94239#false} is VALID [2022-02-21 04:24:41,933 INFO L290 TraceCheckUtils]: 68: Hoare triple {94239#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {94239#false} is VALID [2022-02-21 04:24:41,933 INFO L290 TraceCheckUtils]: 69: Hoare triple {94239#false} assume !(0 != activate_threads_~tmp___5~0#1); {94239#false} is VALID [2022-02-21 04:24:41,933 INFO L290 TraceCheckUtils]: 70: Hoare triple {94239#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {94239#false} is VALID [2022-02-21 04:24:41,934 INFO L290 TraceCheckUtils]: 71: Hoare triple {94239#false} assume !(1 == ~t7_pc~0); {94239#false} is VALID [2022-02-21 04:24:41,934 INFO L290 TraceCheckUtils]: 72: Hoare triple {94239#false} is_transmit7_triggered_~__retres1~7#1 := 0; {94239#false} is VALID [2022-02-21 04:24:41,934 INFO L290 TraceCheckUtils]: 73: Hoare triple {94239#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {94239#false} is VALID [2022-02-21 04:24:41,934 INFO L290 TraceCheckUtils]: 74: Hoare triple {94239#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {94239#false} is VALID [2022-02-21 04:24:41,934 INFO L290 TraceCheckUtils]: 75: Hoare triple {94239#false} assume !(0 != activate_threads_~tmp___6~0#1); {94239#false} is VALID [2022-02-21 04:24:41,934 INFO L290 TraceCheckUtils]: 76: Hoare triple {94239#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {94239#false} is VALID [2022-02-21 04:24:41,934 INFO L290 TraceCheckUtils]: 77: Hoare triple {94239#false} assume !(1 == ~M_E~0); {94239#false} is VALID [2022-02-21 04:24:41,934 INFO L290 TraceCheckUtils]: 78: Hoare triple {94239#false} assume !(1 == ~T1_E~0); {94239#false} is VALID [2022-02-21 04:24:41,934 INFO L290 TraceCheckUtils]: 79: Hoare triple {94239#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {94239#false} is VALID [2022-02-21 04:24:41,934 INFO L290 TraceCheckUtils]: 80: Hoare triple {94239#false} assume !(1 == ~T3_E~0); {94239#false} is VALID [2022-02-21 04:24:41,935 INFO L290 TraceCheckUtils]: 81: Hoare triple {94239#false} assume !(1 == ~T4_E~0); {94239#false} is VALID [2022-02-21 04:24:41,935 INFO L290 TraceCheckUtils]: 82: Hoare triple {94239#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {94239#false} is VALID [2022-02-21 04:24:41,935 INFO L290 TraceCheckUtils]: 83: Hoare triple {94239#false} assume !(1 == ~T6_E~0); {94239#false} is VALID [2022-02-21 04:24:41,935 INFO L290 TraceCheckUtils]: 84: Hoare triple {94239#false} assume !(1 == ~T7_E~0); {94239#false} is VALID [2022-02-21 04:24:41,935 INFO L290 TraceCheckUtils]: 85: Hoare triple {94239#false} assume !(1 == ~E_1~0); {94239#false} is VALID [2022-02-21 04:24:41,935 INFO L290 TraceCheckUtils]: 86: Hoare triple {94239#false} assume !(1 == ~E_2~0); {94239#false} is VALID [2022-02-21 04:24:41,935 INFO L290 TraceCheckUtils]: 87: Hoare triple {94239#false} assume !(1 == ~E_3~0); {94239#false} is VALID [2022-02-21 04:24:41,935 INFO L290 TraceCheckUtils]: 88: Hoare triple {94239#false} assume !(1 == ~E_4~0); {94239#false} is VALID [2022-02-21 04:24:41,935 INFO L290 TraceCheckUtils]: 89: Hoare triple {94239#false} assume !(1 == ~E_5~0); {94239#false} is VALID [2022-02-21 04:24:41,935 INFO L290 TraceCheckUtils]: 90: Hoare triple {94239#false} assume 1 == ~E_6~0;~E_6~0 := 2; {94239#false} is VALID [2022-02-21 04:24:41,936 INFO L290 TraceCheckUtils]: 91: Hoare triple {94239#false} assume !(1 == ~E_7~0); {94239#false} is VALID [2022-02-21 04:24:41,936 INFO L290 TraceCheckUtils]: 92: Hoare triple {94239#false} assume { :end_inline_reset_delta_events } true; {94239#false} is VALID [2022-02-21 04:24:41,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:41,936 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:41,936 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1963888117] [2022-02-21 04:24:41,936 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1963888117] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:41,936 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:41,937 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:41,937 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1939031574] [2022-02-21 04:24:41,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:41,938 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:41,938 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:41,938 INFO L85 PathProgramCache]: Analyzing trace with hash 1026176313, now seen corresponding path program 1 times [2022-02-21 04:24:41,938 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:41,938 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355492169] [2022-02-21 04:24:41,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:41,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:41,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:41,958 INFO L290 TraceCheckUtils]: 0: Hoare triple {94241#true} assume !false; {94241#true} is VALID [2022-02-21 04:24:41,958 INFO L290 TraceCheckUtils]: 1: Hoare triple {94241#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {94241#true} is VALID [2022-02-21 04:24:41,958 INFO L290 TraceCheckUtils]: 2: Hoare triple {94241#true} assume !false; {94241#true} is VALID [2022-02-21 04:24:41,959 INFO L290 TraceCheckUtils]: 3: Hoare triple {94241#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {94241#true} is VALID [2022-02-21 04:24:41,959 INFO L290 TraceCheckUtils]: 4: Hoare triple {94241#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {94241#true} is VALID [2022-02-21 04:24:41,959 INFO L290 TraceCheckUtils]: 5: Hoare triple {94241#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {94241#true} is VALID [2022-02-21 04:24:41,959 INFO L290 TraceCheckUtils]: 6: Hoare triple {94241#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {94241#true} is VALID [2022-02-21 04:24:41,959 INFO L290 TraceCheckUtils]: 7: Hoare triple {94241#true} assume !(0 != eval_~tmp~0#1); {94241#true} is VALID [2022-02-21 04:24:41,959 INFO L290 TraceCheckUtils]: 8: Hoare triple {94241#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {94241#true} is VALID [2022-02-21 04:24:41,959 INFO L290 TraceCheckUtils]: 9: Hoare triple {94241#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {94241#true} is VALID [2022-02-21 04:24:41,960 INFO L290 TraceCheckUtils]: 10: Hoare triple {94241#true} assume 0 == ~M_E~0;~M_E~0 := 1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,960 INFO L290 TraceCheckUtils]: 11: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,960 INFO L290 TraceCheckUtils]: 12: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,960 INFO L290 TraceCheckUtils]: 13: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,961 INFO L290 TraceCheckUtils]: 14: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,961 INFO L290 TraceCheckUtils]: 15: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,961 INFO L290 TraceCheckUtils]: 16: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T6_E~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,961 INFO L290 TraceCheckUtils]: 17: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,962 INFO L290 TraceCheckUtils]: 18: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,962 INFO L290 TraceCheckUtils]: 19: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,962 INFO L290 TraceCheckUtils]: 20: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,962 INFO L290 TraceCheckUtils]: 21: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,963 INFO L290 TraceCheckUtils]: 22: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,963 INFO L290 TraceCheckUtils]: 23: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,963 INFO L290 TraceCheckUtils]: 24: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_7~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,963 INFO L290 TraceCheckUtils]: 25: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,964 INFO L290 TraceCheckUtils]: 26: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,964 INFO L290 TraceCheckUtils]: 27: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,964 INFO L290 TraceCheckUtils]: 28: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,965 INFO L290 TraceCheckUtils]: 29: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,965 INFO L290 TraceCheckUtils]: 30: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,965 INFO L290 TraceCheckUtils]: 31: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,966 INFO L290 TraceCheckUtils]: 32: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,966 INFO L290 TraceCheckUtils]: 33: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,966 INFO L290 TraceCheckUtils]: 34: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,966 INFO L290 TraceCheckUtils]: 35: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,967 INFO L290 TraceCheckUtils]: 36: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___0~0#1); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,967 INFO L290 TraceCheckUtils]: 37: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,967 INFO L290 TraceCheckUtils]: 38: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,967 INFO L290 TraceCheckUtils]: 39: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,968 INFO L290 TraceCheckUtils]: 40: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,968 INFO L290 TraceCheckUtils]: 41: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,968 INFO L290 TraceCheckUtils]: 42: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,969 INFO L290 TraceCheckUtils]: 43: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,969 INFO L290 TraceCheckUtils]: 44: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t3_pc~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,969 INFO L290 TraceCheckUtils]: 45: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,969 INFO L290 TraceCheckUtils]: 46: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,970 INFO L290 TraceCheckUtils]: 47: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,970 INFO L290 TraceCheckUtils]: 48: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,970 INFO L290 TraceCheckUtils]: 49: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,970 INFO L290 TraceCheckUtils]: 50: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,971 INFO L290 TraceCheckUtils]: 51: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,971 INFO L290 TraceCheckUtils]: 52: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,971 INFO L290 TraceCheckUtils]: 53: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,971 INFO L290 TraceCheckUtils]: 54: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,972 INFO L290 TraceCheckUtils]: 55: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,972 INFO L290 TraceCheckUtils]: 56: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t5_pc~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,972 INFO L290 TraceCheckUtils]: 57: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,972 INFO L290 TraceCheckUtils]: 58: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,973 INFO L290 TraceCheckUtils]: 59: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,973 INFO L290 TraceCheckUtils]: 60: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,973 INFO L290 TraceCheckUtils]: 61: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,973 INFO L290 TraceCheckUtils]: 62: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,974 INFO L290 TraceCheckUtils]: 63: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,974 INFO L290 TraceCheckUtils]: 64: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,974 INFO L290 TraceCheckUtils]: 65: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,974 INFO L290 TraceCheckUtils]: 66: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,975 INFO L290 TraceCheckUtils]: 67: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,975 INFO L290 TraceCheckUtils]: 68: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,975 INFO L290 TraceCheckUtils]: 69: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,975 INFO L290 TraceCheckUtils]: 70: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,976 INFO L290 TraceCheckUtils]: 71: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,976 INFO L290 TraceCheckUtils]: 72: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,976 INFO L290 TraceCheckUtils]: 73: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {94243#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:41,977 INFO L290 TraceCheckUtils]: 74: Hoare triple {94243#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {94242#false} is VALID [2022-02-21 04:24:41,977 INFO L290 TraceCheckUtils]: 75: Hoare triple {94242#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,977 INFO L290 TraceCheckUtils]: 76: Hoare triple {94242#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,977 INFO L290 TraceCheckUtils]: 77: Hoare triple {94242#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,977 INFO L290 TraceCheckUtils]: 78: Hoare triple {94242#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,977 INFO L290 TraceCheckUtils]: 79: Hoare triple {94242#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,977 INFO L290 TraceCheckUtils]: 80: Hoare triple {94242#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,977 INFO L290 TraceCheckUtils]: 81: Hoare triple {94242#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,977 INFO L290 TraceCheckUtils]: 82: Hoare triple {94242#false} assume !(1 == ~E_1~0); {94242#false} is VALID [2022-02-21 04:24:41,977 INFO L290 TraceCheckUtils]: 83: Hoare triple {94242#false} assume 1 == ~E_2~0;~E_2~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,978 INFO L290 TraceCheckUtils]: 84: Hoare triple {94242#false} assume 1 == ~E_3~0;~E_3~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,978 INFO L290 TraceCheckUtils]: 85: Hoare triple {94242#false} assume 1 == ~E_4~0;~E_4~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,978 INFO L290 TraceCheckUtils]: 86: Hoare triple {94242#false} assume 1 == ~E_5~0;~E_5~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,978 INFO L290 TraceCheckUtils]: 87: Hoare triple {94242#false} assume 1 == ~E_6~0;~E_6~0 := 2; {94242#false} is VALID [2022-02-21 04:24:41,978 INFO L290 TraceCheckUtils]: 88: Hoare triple {94242#false} assume !(1 == ~E_7~0); {94242#false} is VALID [2022-02-21 04:24:41,978 INFO L290 TraceCheckUtils]: 89: Hoare triple {94242#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {94242#false} is VALID [2022-02-21 04:24:41,978 INFO L290 TraceCheckUtils]: 90: Hoare triple {94242#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {94242#false} is VALID [2022-02-21 04:24:41,978 INFO L290 TraceCheckUtils]: 91: Hoare triple {94242#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {94242#false} is VALID [2022-02-21 04:24:41,978 INFO L290 TraceCheckUtils]: 92: Hoare triple {94242#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {94242#false} is VALID [2022-02-21 04:24:41,978 INFO L290 TraceCheckUtils]: 93: Hoare triple {94242#false} assume !(0 == start_simulation_~tmp~3#1); {94242#false} is VALID [2022-02-21 04:24:41,979 INFO L290 TraceCheckUtils]: 94: Hoare triple {94242#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {94242#false} is VALID [2022-02-21 04:24:41,979 INFO L290 TraceCheckUtils]: 95: Hoare triple {94242#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {94242#false} is VALID [2022-02-21 04:24:41,979 INFO L290 TraceCheckUtils]: 96: Hoare triple {94242#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {94242#false} is VALID [2022-02-21 04:24:41,979 INFO L290 TraceCheckUtils]: 97: Hoare triple {94242#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {94242#false} is VALID [2022-02-21 04:24:41,979 INFO L290 TraceCheckUtils]: 98: Hoare triple {94242#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {94242#false} is VALID [2022-02-21 04:24:41,979 INFO L290 TraceCheckUtils]: 99: Hoare triple {94242#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {94242#false} is VALID [2022-02-21 04:24:41,979 INFO L290 TraceCheckUtils]: 100: Hoare triple {94242#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {94242#false} is VALID [2022-02-21 04:24:41,979 INFO L290 TraceCheckUtils]: 101: Hoare triple {94242#false} assume !(0 != start_simulation_~tmp___0~1#1); {94242#false} is VALID [2022-02-21 04:24:41,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:41,980 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:41,980 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355492169] [2022-02-21 04:24:41,980 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355492169] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:41,980 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:41,980 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:41,980 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790315937] [2022-02-21 04:24:41,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:41,981 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:41,981 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:41,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:41,981 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:41,982 INFO L87 Difference]: Start difference. First operand 5099 states and 7292 transitions. cyclomatic complexity: 2197 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:44,626 INFO L93 Difference]: Finished difference Result 9538 states and 13577 transitions. [2022-02-21 04:24:44,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:44,626 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,685 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:44,686 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9538 states and 13577 transitions. [2022-02-21 04:24:46,612 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9400 [2022-02-21 04:24:48,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9538 states to 9538 states and 13577 transitions. [2022-02-21 04:24:48,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9538 [2022-02-21 04:24:48,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9538 [2022-02-21 04:24:48,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9538 states and 13577 transitions. [2022-02-21 04:24:48,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:48,558 INFO L681 BuchiCegarLoop]: Abstraction has 9538 states and 13577 transitions. [2022-02-21 04:24:48,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9538 states and 13577 transitions. [2022-02-21 04:24:48,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9538 to 9522. [2022-02-21 04:24:48,632 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:48,642 INFO L82 GeneralOperation]: Start isEquivalent. First operand 9538 states and 13577 transitions. Second operand has 9522 states, 9522 states have (on average 1.424175593362739) internal successors, (13561), 9521 states have internal predecessors, (13561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:48,649 INFO L74 IsIncluded]: Start isIncluded. First operand 9538 states and 13577 transitions. Second operand has 9522 states, 9522 states have (on average 1.424175593362739) internal successors, (13561), 9521 states have internal predecessors, (13561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:48,657 INFO L87 Difference]: Start difference. First operand 9538 states and 13577 transitions. Second operand has 9522 states, 9522 states have (on average 1.424175593362739) internal successors, (13561), 9521 states have internal predecessors, (13561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:50,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:50,496 INFO L93 Difference]: Finished difference Result 9538 states and 13577 transitions. [2022-02-21 04:24:50,496 INFO L276 IsEmpty]: Start isEmpty. Operand 9538 states and 13577 transitions. [2022-02-21 04:24:50,505 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:50,505 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:50,513 INFO L74 IsIncluded]: Start isIncluded. First operand has 9522 states, 9522 states have (on average 1.424175593362739) internal successors, (13561), 9521 states have internal predecessors, (13561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9538 states and 13577 transitions. [2022-02-21 04:24:50,522 INFO L87 Difference]: Start difference. First operand has 9522 states, 9522 states have (on average 1.424175593362739) internal successors, (13561), 9521 states have internal predecessors, (13561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 9538 states and 13577 transitions. [2022-02-21 04:24:52,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:52,513 INFO L93 Difference]: Finished difference Result 9538 states and 13577 transitions. [2022-02-21 04:24:52,513 INFO L276 IsEmpty]: Start isEmpty. Operand 9538 states and 13577 transitions. [2022-02-21 04:24:52,524 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:52,524 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:52,524 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:52,524 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:52,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9522 states, 9522 states have (on average 1.424175593362739) internal successors, (13561), 9521 states have internal predecessors, (13561), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:54,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9522 states to 9522 states and 13561 transitions. [2022-02-21 04:24:54,555 INFO L704 BuchiCegarLoop]: Abstraction has 9522 states and 13561 transitions. [2022-02-21 04:24:54,555 INFO L587 BuchiCegarLoop]: Abstraction has 9522 states and 13561 transitions. [2022-02-21 04:24:54,555 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:24:54,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9522 states and 13561 transitions. [2022-02-21 04:24:54,574 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9384 [2022-02-21 04:24:54,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:54,575 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:54,576 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:54,576 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:54,576 INFO L791 eck$LassoCheckResult]: Stem: 104667#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 104615#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 104616#L1111 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 103988#L514 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103989#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 104455#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 104456#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104413#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104321#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104322#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 104312#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 104313#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 104266#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 104267#L754 assume !(0 == ~M_E~0); 104582#L754-2 assume !(0 == ~T1_E~0); 104192#L759-1 assume !(0 == ~T2_E~0); 104193#L764-1 assume !(0 == ~T3_E~0); 104634#L769-1 assume !(0 == ~T4_E~0); 104635#L774-1 assume !(0 == ~T5_E~0); 104494#L779-1 assume !(0 == ~T6_E~0); 104233#L784-1 assume !(0 == ~T7_E~0); 104234#L789-1 assume !(0 == ~E_1~0); 103900#L794-1 assume !(0 == ~E_2~0); 103901#L799-1 assume !(0 == ~E_3~0); 104637#L804-1 assume !(0 == ~E_4~0); 104638#L809-1 assume !(0 == ~E_5~0); 104325#L814-1 assume !(0 == ~E_6~0); 103820#L819-1 assume !(0 == ~E_7~0); 103821#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104307#L361 assume !(1 == ~m_pc~0); 104308#L361-2 is_master_triggered_~__retres1~0#1 := 0; 104351#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104108#L373 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 104109#L930 assume !(0 != activate_threads_~tmp~1#1); 104489#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104300#L380 assume !(1 == ~t1_pc~0); 103952#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 104514#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104515#L392 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 104625#L938 assume !(0 != activate_threads_~tmp___0~0#1); 104028#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103953#L399 assume !(1 == ~t2_pc~0); 103954#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 104163#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104527#L411 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 104378#L946 assume !(0 != activate_threads_~tmp___1~0#1); 103856#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103827#L418 assume !(1 == ~t3_pc~0); 103787#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 103788#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104330#L430 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104593#L954 assume !(0 != activate_threads_~tmp___2~0#1); 104653#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104585#L437 assume !(1 == ~t4_pc~0); 104458#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 104130#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103955#L449 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 103956#L962 assume !(0 != activate_threads_~tmp___3~0#1); 104424#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104084#L456 assume !(1 == ~t5_pc~0); 104085#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 104189#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 104557#L468 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 103846#L970 assume !(0 != activate_threads_~tmp___4~0#1); 103847#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103971#L475 assume 1 == ~t6_pc~0; 103972#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 104047#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 104048#L487 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 103808#L978 assume !(0 != activate_threads_~tmp___5~0#1); 103809#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 104314#L494 assume !(1 == ~t7_pc~0); 104316#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 104357#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 104553#L506 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 104554#L986 assume !(0 != activate_threads_~tmp___6~0#1); 104662#L986-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104555#L837 assume !(1 == ~M_E~0); 104381#L837-2 assume !(1 == ~T1_E~0); 103933#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103934#L847-1 assume !(1 == ~T3_E~0); 111193#L852-1 assume !(1 == ~T4_E~0); 111192#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 111191#L862-1 assume !(1 == ~T6_E~0); 104392#L867-1 assume !(1 == ~T7_E~0); 111190#L872-1 assume !(1 == ~E_1~0); 104672#L877-1 assume !(1 == ~E_2~0); 104673#L882-1 assume !(1 == ~E_3~0); 104602#L887-1 assume !(1 == ~E_4~0); 104603#L892-1 assume !(1 == ~E_5~0); 104543#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 104544#L902-1 assume !(1 == ~E_7~0); 104077#L907-1 assume { :end_inline_reset_delta_events } true; 104078#L1148-2 [2022-02-21 04:24:54,576 INFO L793 eck$LassoCheckResult]: Loop: 104078#L1148-2 assume !false; 111369#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 111368#L729 assume !false; 111367#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 111354#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 108964#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 108955#L612 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 108953#L626 assume !(0 != eval_~tmp~0#1); 104450#L744 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 104451#L514-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 104332#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 103859#L754-5 assume !(0 == ~T1_E~0); 103860#L759-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 112987#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 104461#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 104462#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 104174#L779-3 assume !(0 == ~T6_E~0); 104175#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 112879#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 112877#L794-3 assume !(0 == ~E_2~0); 112875#L799-3 assume 0 == ~E_3~0;~E_3~0 := 1; 112873#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 112871#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 112869#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 112866#L819-3 assume !(0 == ~E_7~0); 112864#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112862#L361-24 assume !(1 == ~m_pc~0); 112860#L361-26 is_master_triggered_~__retres1~0#1 := 0; 112858#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112855#L373-8 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 112853#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 112851#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112850#L380-24 assume 1 == ~t1_pc~0; 112849#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 112847#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112845#L392-8 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 112842#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 112360#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112165#L399-24 assume !(1 == ~t2_pc~0); 112163#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 112161#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112159#L411-8 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 112156#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 112154#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112152#L418-24 assume 1 == ~t3_pc~0; 112149#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 112146#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112144#L430-8 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 112142#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 112140#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112138#L437-24 assume !(1 == ~t4_pc~0); 112136#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 112134#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112131#L449-8 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 112129#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 112127#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112125#L456-24 assume 1 == ~t5_pc~0; 112123#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 112120#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112117#L468-8 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 112115#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 112113#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112111#L475-24 assume !(1 == ~t6_pc~0); 112109#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 112105#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112103#L487-8 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 112101#L978-24 assume !(0 != activate_threads_~tmp___5~0#1); 112099#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112097#L494-24 assume !(1 == ~t7_pc~0); 112094#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 112092#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112090#L506-8 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 112088#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 112087#L986-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112085#L837-3 assume !(1 == ~M_E~0); 112083#L837-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 112081#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112078#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112076#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 112074#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 112072#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 112069#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 112067#L872-3 assume !(1 == ~E_1~0); 112065#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 112063#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 112062#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 112061#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 112060#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 112059#L902-3 assume !(1 == ~E_7~0); 112058#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 112056#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 112049#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 112048#L612-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 112045#L1167 assume !(0 == start_simulation_~tmp~3#1); 112042#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 112015#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 112009#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 112006#L612-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 112004#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 112002#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 112000#L1130 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 111998#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 104078#L1148-2 [2022-02-21 04:24:54,577 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:54,577 INFO L85 PathProgramCache]: Analyzing trace with hash -1707940763, now seen corresponding path program 1 times [2022-02-21 04:24:54,577 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:54,577 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515912151] [2022-02-21 04:24:54,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:54,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:54,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:54,602 INFO L290 TraceCheckUtils]: 0: Hoare triple {132383#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,603 INFO L290 TraceCheckUtils]: 1: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,603 INFO L290 TraceCheckUtils]: 2: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,603 INFO L290 TraceCheckUtils]: 3: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,604 INFO L290 TraceCheckUtils]: 4: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,604 INFO L290 TraceCheckUtils]: 5: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,604 INFO L290 TraceCheckUtils]: 6: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,605 INFO L290 TraceCheckUtils]: 7: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,605 INFO L290 TraceCheckUtils]: 8: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,605 INFO L290 TraceCheckUtils]: 9: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,605 INFO L290 TraceCheckUtils]: 10: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,606 INFO L290 TraceCheckUtils]: 11: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,606 INFO L290 TraceCheckUtils]: 12: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,606 INFO L290 TraceCheckUtils]: 13: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~M_E~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,606 INFO L290 TraceCheckUtils]: 14: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~T1_E~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,607 INFO L290 TraceCheckUtils]: 15: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~T2_E~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,607 INFO L290 TraceCheckUtils]: 16: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~T3_E~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,607 INFO L290 TraceCheckUtils]: 17: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~T4_E~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,608 INFO L290 TraceCheckUtils]: 18: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~T5_E~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,608 INFO L290 TraceCheckUtils]: 19: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~T6_E~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,608 INFO L290 TraceCheckUtils]: 20: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~T7_E~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,608 INFO L290 TraceCheckUtils]: 21: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~E_1~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,609 INFO L290 TraceCheckUtils]: 22: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~E_2~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,609 INFO L290 TraceCheckUtils]: 23: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~E_3~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,609 INFO L290 TraceCheckUtils]: 24: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~E_4~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,609 INFO L290 TraceCheckUtils]: 25: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~E_5~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,610 INFO L290 TraceCheckUtils]: 26: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~E_6~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,610 INFO L290 TraceCheckUtils]: 27: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(0 == ~E_7~0); {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,610 INFO L290 TraceCheckUtils]: 28: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {132385#(= ~m_pc~0 ~t6_pc~0)} is VALID [2022-02-21 04:24:54,611 INFO L290 TraceCheckUtils]: 29: Hoare triple {132385#(= ~m_pc~0 ~t6_pc~0)} assume !(1 == ~m_pc~0); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,611 INFO L290 TraceCheckUtils]: 30: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_master_triggered_~__retres1~0#1 := 0; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,611 INFO L290 TraceCheckUtils]: 31: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,612 INFO L290 TraceCheckUtils]: 32: Hoare triple {132386#(not (= 1 ~t6_pc~0))} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,612 INFO L290 TraceCheckUtils]: 33: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume !(0 != activate_threads_~tmp~1#1); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,612 INFO L290 TraceCheckUtils]: 34: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,612 INFO L290 TraceCheckUtils]: 35: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume !(1 == ~t1_pc~0); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,613 INFO L290 TraceCheckUtils]: 36: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_transmit1_triggered_~__retres1~1#1 := 0; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,613 INFO L290 TraceCheckUtils]: 37: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,613 INFO L290 TraceCheckUtils]: 38: Hoare triple {132386#(not (= 1 ~t6_pc~0))} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,614 INFO L290 TraceCheckUtils]: 39: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume !(0 != activate_threads_~tmp___0~0#1); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,614 INFO L290 TraceCheckUtils]: 40: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,614 INFO L290 TraceCheckUtils]: 41: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume !(1 == ~t2_pc~0); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,614 INFO L290 TraceCheckUtils]: 42: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_transmit2_triggered_~__retres1~2#1 := 0; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,615 INFO L290 TraceCheckUtils]: 43: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,615 INFO L290 TraceCheckUtils]: 44: Hoare triple {132386#(not (= 1 ~t6_pc~0))} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,615 INFO L290 TraceCheckUtils]: 45: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume !(0 != activate_threads_~tmp___1~0#1); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,616 INFO L290 TraceCheckUtils]: 46: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,616 INFO L290 TraceCheckUtils]: 47: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume !(1 == ~t3_pc~0); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,616 INFO L290 TraceCheckUtils]: 48: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_transmit3_triggered_~__retres1~3#1 := 0; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,617 INFO L290 TraceCheckUtils]: 49: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,617 INFO L290 TraceCheckUtils]: 50: Hoare triple {132386#(not (= 1 ~t6_pc~0))} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,617 INFO L290 TraceCheckUtils]: 51: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume !(0 != activate_threads_~tmp___2~0#1); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,617 INFO L290 TraceCheckUtils]: 52: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,618 INFO L290 TraceCheckUtils]: 53: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume !(1 == ~t4_pc~0); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,618 INFO L290 TraceCheckUtils]: 54: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_transmit4_triggered_~__retres1~4#1 := 0; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,618 INFO L290 TraceCheckUtils]: 55: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,619 INFO L290 TraceCheckUtils]: 56: Hoare triple {132386#(not (= 1 ~t6_pc~0))} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,619 INFO L290 TraceCheckUtils]: 57: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume !(0 != activate_threads_~tmp___3~0#1); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,619 INFO L290 TraceCheckUtils]: 58: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,620 INFO L290 TraceCheckUtils]: 59: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume !(1 == ~t5_pc~0); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,620 INFO L290 TraceCheckUtils]: 60: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_transmit5_triggered_~__retres1~5#1 := 0; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,620 INFO L290 TraceCheckUtils]: 61: Hoare triple {132386#(not (= 1 ~t6_pc~0))} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,620 INFO L290 TraceCheckUtils]: 62: Hoare triple {132386#(not (= 1 ~t6_pc~0))} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,621 INFO L290 TraceCheckUtils]: 63: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume !(0 != activate_threads_~tmp___4~0#1); {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,621 INFO L290 TraceCheckUtils]: 64: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {132386#(not (= 1 ~t6_pc~0))} is VALID [2022-02-21 04:24:54,621 INFO L290 TraceCheckUtils]: 65: Hoare triple {132386#(not (= 1 ~t6_pc~0))} assume 1 == ~t6_pc~0; {132384#false} is VALID [2022-02-21 04:24:54,621 INFO L290 TraceCheckUtils]: 66: Hoare triple {132384#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {132384#false} is VALID [2022-02-21 04:24:54,622 INFO L290 TraceCheckUtils]: 67: Hoare triple {132384#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {132384#false} is VALID [2022-02-21 04:24:54,622 INFO L290 TraceCheckUtils]: 68: Hoare triple {132384#false} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {132384#false} is VALID [2022-02-21 04:24:54,622 INFO L290 TraceCheckUtils]: 69: Hoare triple {132384#false} assume !(0 != activate_threads_~tmp___5~0#1); {132384#false} is VALID [2022-02-21 04:24:54,622 INFO L290 TraceCheckUtils]: 70: Hoare triple {132384#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {132384#false} is VALID [2022-02-21 04:24:54,622 INFO L290 TraceCheckUtils]: 71: Hoare triple {132384#false} assume !(1 == ~t7_pc~0); {132384#false} is VALID [2022-02-21 04:24:54,622 INFO L290 TraceCheckUtils]: 72: Hoare triple {132384#false} is_transmit7_triggered_~__retres1~7#1 := 0; {132384#false} is VALID [2022-02-21 04:24:54,622 INFO L290 TraceCheckUtils]: 73: Hoare triple {132384#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {132384#false} is VALID [2022-02-21 04:24:54,622 INFO L290 TraceCheckUtils]: 74: Hoare triple {132384#false} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {132384#false} is VALID [2022-02-21 04:24:54,622 INFO L290 TraceCheckUtils]: 75: Hoare triple {132384#false} assume !(0 != activate_threads_~tmp___6~0#1); {132384#false} is VALID [2022-02-21 04:24:54,622 INFO L290 TraceCheckUtils]: 76: Hoare triple {132384#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {132384#false} is VALID [2022-02-21 04:24:54,623 INFO L290 TraceCheckUtils]: 77: Hoare triple {132384#false} assume !(1 == ~M_E~0); {132384#false} is VALID [2022-02-21 04:24:54,623 INFO L290 TraceCheckUtils]: 78: Hoare triple {132384#false} assume !(1 == ~T1_E~0); {132384#false} is VALID [2022-02-21 04:24:54,623 INFO L290 TraceCheckUtils]: 79: Hoare triple {132384#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {132384#false} is VALID [2022-02-21 04:24:54,623 INFO L290 TraceCheckUtils]: 80: Hoare triple {132384#false} assume !(1 == ~T3_E~0); {132384#false} is VALID [2022-02-21 04:24:54,623 INFO L290 TraceCheckUtils]: 81: Hoare triple {132384#false} assume !(1 == ~T4_E~0); {132384#false} is VALID [2022-02-21 04:24:54,623 INFO L290 TraceCheckUtils]: 82: Hoare triple {132384#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {132384#false} is VALID [2022-02-21 04:24:54,623 INFO L290 TraceCheckUtils]: 83: Hoare triple {132384#false} assume !(1 == ~T6_E~0); {132384#false} is VALID [2022-02-21 04:24:54,623 INFO L290 TraceCheckUtils]: 84: Hoare triple {132384#false} assume !(1 == ~T7_E~0); {132384#false} is VALID [2022-02-21 04:24:54,623 INFO L290 TraceCheckUtils]: 85: Hoare triple {132384#false} assume !(1 == ~E_1~0); {132384#false} is VALID [2022-02-21 04:24:54,623 INFO L290 TraceCheckUtils]: 86: Hoare triple {132384#false} assume !(1 == ~E_2~0); {132384#false} is VALID [2022-02-21 04:24:54,624 INFO L290 TraceCheckUtils]: 87: Hoare triple {132384#false} assume !(1 == ~E_3~0); {132384#false} is VALID [2022-02-21 04:24:54,624 INFO L290 TraceCheckUtils]: 88: Hoare triple {132384#false} assume !(1 == ~E_4~0); {132384#false} is VALID [2022-02-21 04:24:54,624 INFO L290 TraceCheckUtils]: 89: Hoare triple {132384#false} assume !(1 == ~E_5~0); {132384#false} is VALID [2022-02-21 04:24:54,624 INFO L290 TraceCheckUtils]: 90: Hoare triple {132384#false} assume 1 == ~E_6~0;~E_6~0 := 2; {132384#false} is VALID [2022-02-21 04:24:54,624 INFO L290 TraceCheckUtils]: 91: Hoare triple {132384#false} assume !(1 == ~E_7~0); {132384#false} is VALID [2022-02-21 04:24:54,624 INFO L290 TraceCheckUtils]: 92: Hoare triple {132384#false} assume { :end_inline_reset_delta_events } true; {132384#false} is VALID [2022-02-21 04:24:54,624 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:54,624 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:54,625 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [515912151] [2022-02-21 04:24:54,625 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [515912151] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:54,625 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:54,625 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:54,625 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2102599674] [2022-02-21 04:24:54,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:54,627 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:54,627 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:54,627 INFO L85 PathProgramCache]: Analyzing trace with hash -993927842, now seen corresponding path program 1 times [2022-02-21 04:24:54,627 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:54,627 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445378371] [2022-02-21 04:24:54,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:54,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:54,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:54,649 INFO L290 TraceCheckUtils]: 0: Hoare triple {132387#true} assume !false; {132387#true} is VALID [2022-02-21 04:24:54,650 INFO L290 TraceCheckUtils]: 1: Hoare triple {132387#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {132387#true} is VALID [2022-02-21 04:24:54,650 INFO L290 TraceCheckUtils]: 2: Hoare triple {132387#true} assume !false; {132387#true} is VALID [2022-02-21 04:24:54,650 INFO L290 TraceCheckUtils]: 3: Hoare triple {132387#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {132387#true} is VALID [2022-02-21 04:24:54,650 INFO L290 TraceCheckUtils]: 4: Hoare triple {132387#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {132387#true} is VALID [2022-02-21 04:24:54,650 INFO L290 TraceCheckUtils]: 5: Hoare triple {132387#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {132387#true} is VALID [2022-02-21 04:24:54,650 INFO L290 TraceCheckUtils]: 6: Hoare triple {132387#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {132387#true} is VALID [2022-02-21 04:24:54,650 INFO L290 TraceCheckUtils]: 7: Hoare triple {132387#true} assume !(0 != eval_~tmp~0#1); {132387#true} is VALID [2022-02-21 04:24:54,650 INFO L290 TraceCheckUtils]: 8: Hoare triple {132387#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {132387#true} is VALID [2022-02-21 04:24:54,650 INFO L290 TraceCheckUtils]: 9: Hoare triple {132387#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {132387#true} is VALID [2022-02-21 04:24:54,651 INFO L290 TraceCheckUtils]: 10: Hoare triple {132387#true} assume 0 == ~M_E~0;~M_E~0 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,651 INFO L290 TraceCheckUtils]: 11: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T1_E~0); {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,651 INFO L290 TraceCheckUtils]: 12: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T2_E~0;~T2_E~0 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,652 INFO L290 TraceCheckUtils]: 13: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,652 INFO L290 TraceCheckUtils]: 14: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,652 INFO L290 TraceCheckUtils]: 15: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,652 INFO L290 TraceCheckUtils]: 16: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~T6_E~0); {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,653 INFO L290 TraceCheckUtils]: 17: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,653 INFO L290 TraceCheckUtils]: 18: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,653 INFO L290 TraceCheckUtils]: 19: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_2~0); {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,653 INFO L290 TraceCheckUtils]: 20: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,654 INFO L290 TraceCheckUtils]: 21: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,654 INFO L290 TraceCheckUtils]: 22: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,654 INFO L290 TraceCheckUtils]: 23: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,654 INFO L290 TraceCheckUtils]: 24: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume !(0 == ~E_7~0); {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,655 INFO L290 TraceCheckUtils]: 25: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,655 INFO L290 TraceCheckUtils]: 26: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,655 INFO L290 TraceCheckUtils]: 27: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,656 INFO L290 TraceCheckUtils]: 28: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,656 INFO L290 TraceCheckUtils]: 29: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret13#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,656 INFO L290 TraceCheckUtils]: 30: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,656 INFO L290 TraceCheckUtils]: 31: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,657 INFO L290 TraceCheckUtils]: 32: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t1_pc~0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,657 INFO L290 TraceCheckUtils]: 33: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,657 INFO L290 TraceCheckUtils]: 34: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,657 INFO L290 TraceCheckUtils]: 35: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,658 INFO L290 TraceCheckUtils]: 36: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,658 INFO L290 TraceCheckUtils]: 37: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,658 INFO L290 TraceCheckUtils]: 38: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t2_pc~0); {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,658 INFO L290 TraceCheckUtils]: 39: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,659 INFO L290 TraceCheckUtils]: 40: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,659 INFO L290 TraceCheckUtils]: 41: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,659 INFO L290 TraceCheckUtils]: 42: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,660 INFO L290 TraceCheckUtils]: 43: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,660 INFO L290 TraceCheckUtils]: 44: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t3_pc~0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,660 INFO L290 TraceCheckUtils]: 45: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,660 INFO L290 TraceCheckUtils]: 46: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,661 INFO L290 TraceCheckUtils]: 47: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,661 INFO L290 TraceCheckUtils]: 48: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,661 INFO L290 TraceCheckUtils]: 49: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,661 INFO L290 TraceCheckUtils]: 50: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t4_pc~0); {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,662 INFO L290 TraceCheckUtils]: 51: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,662 INFO L290 TraceCheckUtils]: 52: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,662 INFO L290 TraceCheckUtils]: 53: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,663 INFO L290 TraceCheckUtils]: 54: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,663 INFO L290 TraceCheckUtils]: 55: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,663 INFO L290 TraceCheckUtils]: 56: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~t5_pc~0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,663 INFO L290 TraceCheckUtils]: 57: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,664 INFO L290 TraceCheckUtils]: 58: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,664 INFO L290 TraceCheckUtils]: 59: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,664 INFO L290 TraceCheckUtils]: 60: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,664 INFO L290 TraceCheckUtils]: 61: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,665 INFO L290 TraceCheckUtils]: 62: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t6_pc~0); {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,665 INFO L290 TraceCheckUtils]: 63: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,665 INFO L290 TraceCheckUtils]: 64: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,665 INFO L290 TraceCheckUtils]: 65: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,666 INFO L290 TraceCheckUtils]: 66: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,666 INFO L290 TraceCheckUtils]: 67: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,666 INFO L290 TraceCheckUtils]: 68: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t7_pc~0); {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,667 INFO L290 TraceCheckUtils]: 69: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,667 INFO L290 TraceCheckUtils]: 70: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,667 INFO L290 TraceCheckUtils]: 71: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,667 INFO L290 TraceCheckUtils]: 72: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,668 INFO L290 TraceCheckUtils]: 73: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {132389#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:24:54,668 INFO L290 TraceCheckUtils]: 74: Hoare triple {132389#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {132388#false} is VALID [2022-02-21 04:24:54,668 INFO L290 TraceCheckUtils]: 75: Hoare triple {132388#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,668 INFO L290 TraceCheckUtils]: 76: Hoare triple {132388#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,668 INFO L290 TraceCheckUtils]: 77: Hoare triple {132388#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,668 INFO L290 TraceCheckUtils]: 78: Hoare triple {132388#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,668 INFO L290 TraceCheckUtils]: 79: Hoare triple {132388#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,668 INFO L290 TraceCheckUtils]: 80: Hoare triple {132388#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,669 INFO L290 TraceCheckUtils]: 81: Hoare triple {132388#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,669 INFO L290 TraceCheckUtils]: 82: Hoare triple {132388#false} assume !(1 == ~E_1~0); {132388#false} is VALID [2022-02-21 04:24:54,669 INFO L290 TraceCheckUtils]: 83: Hoare triple {132388#false} assume 1 == ~E_2~0;~E_2~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,669 INFO L290 TraceCheckUtils]: 84: Hoare triple {132388#false} assume 1 == ~E_3~0;~E_3~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,669 INFO L290 TraceCheckUtils]: 85: Hoare triple {132388#false} assume 1 == ~E_4~0;~E_4~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,669 INFO L290 TraceCheckUtils]: 86: Hoare triple {132388#false} assume 1 == ~E_5~0;~E_5~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,669 INFO L290 TraceCheckUtils]: 87: Hoare triple {132388#false} assume 1 == ~E_6~0;~E_6~0 := 2; {132388#false} is VALID [2022-02-21 04:24:54,669 INFO L290 TraceCheckUtils]: 88: Hoare triple {132388#false} assume !(1 == ~E_7~0); {132388#false} is VALID [2022-02-21 04:24:54,669 INFO L290 TraceCheckUtils]: 89: Hoare triple {132388#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {132388#false} is VALID [2022-02-21 04:24:54,669 INFO L290 TraceCheckUtils]: 90: Hoare triple {132388#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {132388#false} is VALID [2022-02-21 04:24:54,670 INFO L290 TraceCheckUtils]: 91: Hoare triple {132388#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {132388#false} is VALID [2022-02-21 04:24:54,670 INFO L290 TraceCheckUtils]: 92: Hoare triple {132388#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {132388#false} is VALID [2022-02-21 04:24:54,670 INFO L290 TraceCheckUtils]: 93: Hoare triple {132388#false} assume !(0 == start_simulation_~tmp~3#1); {132388#false} is VALID [2022-02-21 04:24:54,670 INFO L290 TraceCheckUtils]: 94: Hoare triple {132388#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {132388#false} is VALID [2022-02-21 04:24:54,670 INFO L290 TraceCheckUtils]: 95: Hoare triple {132388#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {132388#false} is VALID [2022-02-21 04:24:54,670 INFO L290 TraceCheckUtils]: 96: Hoare triple {132388#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {132388#false} is VALID [2022-02-21 04:24:54,670 INFO L290 TraceCheckUtils]: 97: Hoare triple {132388#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {132388#false} is VALID [2022-02-21 04:24:54,670 INFO L290 TraceCheckUtils]: 98: Hoare triple {132388#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {132388#false} is VALID [2022-02-21 04:24:54,670 INFO L290 TraceCheckUtils]: 99: Hoare triple {132388#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {132388#false} is VALID [2022-02-21 04:24:54,670 INFO L290 TraceCheckUtils]: 100: Hoare triple {132388#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {132388#false} is VALID [2022-02-21 04:24:54,671 INFO L290 TraceCheckUtils]: 101: Hoare triple {132388#false} assume !(0 != start_simulation_~tmp___0~1#1); {132388#false} is VALID [2022-02-21 04:24:54,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:54,671 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:54,671 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445378371] [2022-02-21 04:24:54,672 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445378371] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:54,672 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:54,672 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:54,672 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [380149390] [2022-02-21 04:24:54,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:54,673 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:54,673 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:54,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:54,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:54,674 INFO L87 Difference]: Start difference. First operand 9522 states and 13561 transitions. cyclomatic complexity: 4047 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:07,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:07,619 INFO L93 Difference]: Finished difference Result 22429 states and 31670 transitions. [2022-02-21 04:25:07,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:25:07,619 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:07,688 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:07,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22429 states and 31670 transitions. [2022-02-21 04:25:19,284 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21732