./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.08.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.08.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:24:13,003 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:24:13,005 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:24:13,041 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:24:13,041 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:24:13,044 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:24:13,045 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:24:13,048 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:24:13,049 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:24:13,051 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:24:13,052 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:24:13,053 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:24:13,053 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:24:13,057 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:24:13,058 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:24:13,059 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:24:13,062 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:24:13,063 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:24:13,063 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:24:13,065 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:24:13,068 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:24:13,069 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:24:13,070 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:24:13,071 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:24:13,072 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:24:13,073 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:24:13,074 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:24:13,074 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:24:13,075 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:24:13,075 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:24:13,076 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:24:13,076 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:24:13,077 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:24:13,078 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:24:13,079 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:24:13,079 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:24:13,079 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:24:13,080 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:24:13,080 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:24:13,080 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:24:13,081 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:24:13,081 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:24:13,105 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:24:13,105 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:24:13,106 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:24:13,106 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:24:13,107 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:24:13,107 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:24:13,107 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:24:13,107 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:24:13,107 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:24:13,108 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:24:13,108 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:24:13,108 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:24:13,108 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:24:13,109 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:24:13,109 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:24:13,109 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:24:13,109 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:24:13,109 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:24:13,109 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:24:13,109 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:24:13,110 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:24:13,110 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:24:13,110 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:24:13,110 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:24:13,110 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:24:13,110 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:24:13,111 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:24:13,111 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:24:13,111 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:24:13,111 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:24:13,111 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:24:13,112 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:24:13,112 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 [2022-02-21 04:24:13,290 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:24:13,305 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:24:13,307 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:24:13,308 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:24:13,308 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:24:13,309 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.08.cil.c [2022-02-21 04:24:13,377 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/81ddee855/25b3f73a42264d129da5625b7dc1a391/FLAG937e2733a [2022-02-21 04:24:13,761 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:13,762 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.08.cil.c [2022-02-21 04:24:13,769 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/81ddee855/25b3f73a42264d129da5625b7dc1a391/FLAG937e2733a [2022-02-21 04:24:13,781 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/81ddee855/25b3f73a42264d129da5625b7dc1a391 [2022-02-21 04:24:13,783 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:13,784 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:13,785 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:13,785 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:13,787 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:13,788 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:13" (1/1) ... [2022-02-21 04:24:13,789 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@526d4e2b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:13, skipping insertion in model container [2022-02-21 04:24:13,789 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:13" (1/1) ... [2022-02-21 04:24:13,794 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:13,830 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:13,950 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.08.cil.c[706,719] [2022-02-21 04:24:14,031 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:14,038 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:14,046 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.08.cil.c[706,719] [2022-02-21 04:24:14,098 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:14,133 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:14,134 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14 WrapperNode [2022-02-21 04:24:14,134 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:14,134 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:14,135 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:14,135 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:14,145 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,153 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,217 INFO L137 Inliner]: procedures = 44, calls = 54, calls flagged for inlining = 49, calls inlined = 146, statements flattened = 2198 [2022-02-21 04:24:14,218 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:14,219 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:14,219 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:14,219 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:14,225 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,226 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,234 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,246 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,263 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,280 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,284 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,307 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:14,308 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:14,308 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:14,308 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:14,309 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,314 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:14,324 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:14,334 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:14,336 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:14,365 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:14,366 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:14,366 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:14,366 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:14,431 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:14,432 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:15,534 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:15,552 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:15,552 INFO L299 CfgBuilder]: Removed 12 assume(true) statements. [2022-02-21 04:24:15,555 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:15 BoogieIcfgContainer [2022-02-21 04:24:15,555 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:15,556 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:15,556 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:15,558 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:15,559 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:15,559 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:13" (1/3) ... [2022-02-21 04:24:15,560 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@604cde10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:15, skipping insertion in model container [2022-02-21 04:24:15,560 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:15,560 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14" (2/3) ... [2022-02-21 04:24:15,560 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@604cde10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:15, skipping insertion in model container [2022-02-21 04:24:15,560 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:15,560 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:15" (3/3) ... [2022-02-21 04:24:15,561 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.08.cil.c [2022-02-21 04:24:15,602 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:15,602 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:15,602 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:15,602 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:15,602 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:15,602 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:15,603 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:15,603 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:15,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,802 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 814 [2022-02-21 04:24:15,802 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:15,802 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:15,814 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:15,815 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:15,815 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:15,817 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:15,881 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 814 [2022-02-21 04:24:15,881 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:15,881 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:15,886 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:15,887 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:15,898 INFO L791 eck$LassoCheckResult]: Stem: 422#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 841#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 848#L1235true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47#L574true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 671#L581true assume !(1 == ~m_i~0);~m_st~0 := 2; 193#L581-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 808#L586-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 664#L591-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 637#L596-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 232#L601-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 672#L606-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 405#L611-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 752#L616-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 287#L621-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 697#L838true assume !(0 == ~M_E~0); 413#L838-2true assume !(0 == ~T1_E~0); 28#L843-1true assume !(0 == ~T2_E~0); 86#L848-1true assume !(0 == ~T3_E~0); 426#L853-1true assume !(0 == ~T4_E~0); 278#L858-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 3#L863-1true assume !(0 == ~T6_E~0); 745#L868-1true assume !(0 == ~T7_E~0); 864#L873-1true assume !(0 == ~T8_E~0); 740#L878-1true assume !(0 == ~E_1~0); 706#L883-1true assume !(0 == ~E_2~0); 778#L888-1true assume !(0 == ~E_3~0); 383#L893-1true assume !(0 == ~E_4~0); 779#L898-1true assume 0 == ~E_5~0;~E_5~0 := 1; 913#L903-1true assume !(0 == ~E_6~0); 704#L908-1true assume !(0 == ~E_7~0); 496#L913-1true assume !(0 == ~E_8~0); 34#L918-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 513#L402true assume !(1 == ~m_pc~0); 262#L402-2true is_master_triggered_~__retres1~0#1 := 0; 98#L413true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 920#L414true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 236#L1035true assume !(0 != activate_threads_~tmp~1#1); 271#L1035-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 693#L421true assume 1 == ~t1_pc~0; 807#L422true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 883#L432true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 264#L433true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 308#L1043true assume !(0 != activate_threads_~tmp___0~0#1); 767#L1043-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 896#L440true assume 1 == ~t2_pc~0; 21#L441true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 103#L451true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 865#L452true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 816#L1051true assume !(0 != activate_threads_~tmp___1~0#1); 515#L1051-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 211#L459true assume !(1 == ~t3_pc~0); 686#L459-2true is_transmit3_triggered_~__retres1~3#1 := 0; 763#L470true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 446#L471true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 94#L1059true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 921#L1059-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100#L478true assume 1 == ~t4_pc~0; 387#L479true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 662#L489true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 809#L490true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 196#L1067true assume !(0 != activate_threads_~tmp___3~0#1); 56#L1067-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 423#L497true assume !(1 == ~t5_pc~0); 354#L497-2true is_transmit5_triggered_~__retres1~5#1 := 0; 450#L508true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 245#L509true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 768#L1075true assume !(0 != activate_threads_~tmp___4~0#1); 678#L1075-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 875#L516true assume 1 == ~t6_pc~0; 876#L517true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 404#L527true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 844#L528true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122#L1083true assume !(0 != activate_threads_~tmp___5~0#1); 462#L1083-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 400#L535true assume !(1 == ~t7_pc~0); 783#L535-2true is_transmit7_triggered_~__retres1~7#1 := 0; 461#L546true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 589#L547true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 489#L1091true assume !(0 != activate_threads_~tmp___6~0#1); 482#L1091-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 673#L554true assume 1 == ~t8_pc~0; 430#L555true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 810#L565true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 535#L566true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171#L1099true assume !(0 != activate_threads_~tmp___7~0#1); 490#L1099-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9#L931true assume !(1 == ~M_E~0); 726#L931-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 805#L936-1true assume !(1 == ~T2_E~0); 891#L941-1true assume !(1 == ~T3_E~0); 272#L946-1true assume !(1 == ~T4_E~0); 689#L951-1true assume !(1 == ~T5_E~0); 131#L956-1true assume !(1 == ~T6_E~0); 877#L961-1true assume !(1 == ~T7_E~0); 384#L966-1true assume !(1 == ~T8_E~0); 484#L971-1true assume 1 == ~E_1~0;~E_1~0 := 2; 829#L976-1true assume !(1 == ~E_2~0); 455#L981-1true assume !(1 == ~E_3~0); 275#L986-1true assume !(1 == ~E_4~0); 148#L991-1true assume !(1 == ~E_5~0); 854#L996-1true assume !(1 == ~E_6~0); 757#L1001-1true assume !(1 == ~E_7~0); 421#L1006-1true assume !(1 == ~E_8~0); 690#L1011-1true assume { :end_inline_reset_delta_events } true; 39#L1272-2true [2022-02-21 04:24:15,899 INFO L793 eck$LassoCheckResult]: Loop: 39#L1272-2true assume !false; 417#L1273true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40#L813true assume false; 424#L828true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 552#L574-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 642#L838-3true assume !(0 == ~M_E~0); 467#L838-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 789#L843-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 345#L848-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 385#L853-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 571#L858-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 444#L863-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 434#L868-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 453#L873-3true assume !(0 == ~T8_E~0); 160#L878-3true assume 0 == ~E_1~0;~E_1~0 := 1; 22#L883-3true assume 0 == ~E_2~0;~E_2~0 := 1; 657#L888-3true assume 0 == ~E_3~0;~E_3~0 := 1; 23#L893-3true assume 0 == ~E_4~0;~E_4~0 := 1; 289#L898-3true assume 0 == ~E_5~0;~E_5~0 := 1; 592#L903-3true assume 0 == ~E_6~0;~E_6~0 := 1; 777#L908-3true assume 0 == ~E_7~0;~E_7~0 := 1; 297#L913-3true assume !(0 == ~E_8~0); 43#L918-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 885#L402-27true assume 1 == ~m_pc~0; 17#L403-9true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 835#L413-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 292#L414-9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 732#L1035-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 623#L1035-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 659#L421-27true assume !(1 == ~t1_pc~0); 156#L421-29true is_transmit1_triggered_~__retres1~1#1 := 0; 815#L432-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 318#L433-9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 758#L1043-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 881#L1043-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 401#L440-27true assume 1 == ~t2_pc~0; 859#L441-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 929#L451-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 207#L452-9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 325#L1051-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 411#L1051-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 150#L459-27true assume 1 == ~t3_pc~0; 458#L460-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 831#L470-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189#L471-9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 399#L1059-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 743#L1059-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 878#L478-27true assume !(1 == ~t4_pc~0); 143#L478-29true is_transmit4_triggered_~__retres1~4#1 := 0; 406#L489-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 886#L490-9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 541#L1067-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 744#L1067-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 593#L497-27true assume !(1 == ~t5_pc~0); 240#L497-29true is_transmit5_triggered_~__retres1~5#1 := 0; 165#L508-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 341#L509-9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134#L1075-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 665#L1075-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 293#L516-27true assume 1 == ~t6_pc~0; 337#L517-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 200#L527-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 294#L528-9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 415#L1083-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 755#L1083-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 246#L535-27true assume !(1 == ~t7_pc~0); 521#L535-29true is_transmit7_triggered_~__retres1~7#1 := 0; 926#L546-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 554#L547-9true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 825#L1091-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 220#L1091-29true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 766#L554-27true assume !(1 == ~t8_pc~0); 30#L554-29true is_transmit8_triggered_~__retres1~8#1 := 0; 102#L565-9true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 309#L566-9true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 329#L1099-27true assume !(0 != activate_threads_~tmp___7~0#1); 158#L1099-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 517#L931-3true assume 1 == ~M_E~0;~M_E~0 := 2; 92#L931-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 218#L936-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 304#L941-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 519#L946-3true assume !(1 == ~T4_E~0); 169#L951-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 502#L956-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 364#L961-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 225#L966-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 710#L971-3true assume 1 == ~E_1~0;~E_1~0 := 2; 403#L976-3true assume 1 == ~E_2~0;~E_2~0 := 2; 38#L981-3true assume 1 == ~E_3~0;~E_3~0 := 2; 159#L986-3true assume !(1 == ~E_4~0); 33#L991-3true assume 1 == ~E_5~0;~E_5~0 := 2; 470#L996-3true assume 1 == ~E_6~0;~E_6~0 := 2; 596#L1001-3true assume 1 == ~E_7~0;~E_7~0 := 2; 213#L1006-3true assume 1 == ~E_8~0;~E_8~0 := 2; 504#L1011-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 54#L634-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 307#L681-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 228#L682-1true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 773#L1291true assume !(0 == start_simulation_~tmp~3#1); 741#L1291-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 285#L634-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5#L681-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 564#L682-2true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 714#L1246true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 258#L1253true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 438#L1254true start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 542#L1304true assume !(0 != start_simulation_~tmp___0~1#1); 39#L1272-2true [2022-02-21 04:24:15,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:15,904 INFO L85 PathProgramCache]: Analyzing trace with hash -1897256038, now seen corresponding path program 1 times [2022-02-21 04:24:15,910 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:15,911 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218842817] [2022-02-21 04:24:15,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:15,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:16,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:16,110 INFO L290 TraceCheckUtils]: 0: Hoare triple {935#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {935#true} is VALID [2022-02-21 04:24:16,111 INFO L290 TraceCheckUtils]: 1: Hoare triple {935#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {937#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:16,111 INFO L290 TraceCheckUtils]: 2: Hoare triple {937#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {937#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:16,112 INFO L290 TraceCheckUtils]: 3: Hoare triple {937#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {937#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:16,113 INFO L290 TraceCheckUtils]: 4: Hoare triple {937#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {936#false} is VALID [2022-02-21 04:24:16,113 INFO L290 TraceCheckUtils]: 5: Hoare triple {936#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {936#false} is VALID [2022-02-21 04:24:16,113 INFO L290 TraceCheckUtils]: 6: Hoare triple {936#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {936#false} is VALID [2022-02-21 04:24:16,114 INFO L290 TraceCheckUtils]: 7: Hoare triple {936#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {936#false} is VALID [2022-02-21 04:24:16,114 INFO L290 TraceCheckUtils]: 8: Hoare triple {936#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {936#false} is VALID [2022-02-21 04:24:16,114 INFO L290 TraceCheckUtils]: 9: Hoare triple {936#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {936#false} is VALID [2022-02-21 04:24:16,115 INFO L290 TraceCheckUtils]: 10: Hoare triple {936#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {936#false} is VALID [2022-02-21 04:24:16,115 INFO L290 TraceCheckUtils]: 11: Hoare triple {936#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {936#false} is VALID [2022-02-21 04:24:16,115 INFO L290 TraceCheckUtils]: 12: Hoare triple {936#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {936#false} is VALID [2022-02-21 04:24:16,115 INFO L290 TraceCheckUtils]: 13: Hoare triple {936#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {936#false} is VALID [2022-02-21 04:24:16,115 INFO L290 TraceCheckUtils]: 14: Hoare triple {936#false} assume !(0 == ~M_E~0); {936#false} is VALID [2022-02-21 04:24:16,116 INFO L290 TraceCheckUtils]: 15: Hoare triple {936#false} assume !(0 == ~T1_E~0); {936#false} is VALID [2022-02-21 04:24:16,116 INFO L290 TraceCheckUtils]: 16: Hoare triple {936#false} assume !(0 == ~T2_E~0); {936#false} is VALID [2022-02-21 04:24:16,116 INFO L290 TraceCheckUtils]: 17: Hoare triple {936#false} assume !(0 == ~T3_E~0); {936#false} is VALID [2022-02-21 04:24:16,116 INFO L290 TraceCheckUtils]: 18: Hoare triple {936#false} assume !(0 == ~T4_E~0); {936#false} is VALID [2022-02-21 04:24:16,116 INFO L290 TraceCheckUtils]: 19: Hoare triple {936#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {936#false} is VALID [2022-02-21 04:24:16,117 INFO L290 TraceCheckUtils]: 20: Hoare triple {936#false} assume !(0 == ~T6_E~0); {936#false} is VALID [2022-02-21 04:24:16,117 INFO L290 TraceCheckUtils]: 21: Hoare triple {936#false} assume !(0 == ~T7_E~0); {936#false} is VALID [2022-02-21 04:24:16,117 INFO L290 TraceCheckUtils]: 22: Hoare triple {936#false} assume !(0 == ~T8_E~0); {936#false} is VALID [2022-02-21 04:24:16,117 INFO L290 TraceCheckUtils]: 23: Hoare triple {936#false} assume !(0 == ~E_1~0); {936#false} is VALID [2022-02-21 04:24:16,118 INFO L290 TraceCheckUtils]: 24: Hoare triple {936#false} assume !(0 == ~E_2~0); {936#false} is VALID [2022-02-21 04:24:16,118 INFO L290 TraceCheckUtils]: 25: Hoare triple {936#false} assume !(0 == ~E_3~0); {936#false} is VALID [2022-02-21 04:24:16,118 INFO L290 TraceCheckUtils]: 26: Hoare triple {936#false} assume !(0 == ~E_4~0); {936#false} is VALID [2022-02-21 04:24:16,119 INFO L290 TraceCheckUtils]: 27: Hoare triple {936#false} assume 0 == ~E_5~0;~E_5~0 := 1; {936#false} is VALID [2022-02-21 04:24:16,119 INFO L290 TraceCheckUtils]: 28: Hoare triple {936#false} assume !(0 == ~E_6~0); {936#false} is VALID [2022-02-21 04:24:16,119 INFO L290 TraceCheckUtils]: 29: Hoare triple {936#false} assume !(0 == ~E_7~0); {936#false} is VALID [2022-02-21 04:24:16,119 INFO L290 TraceCheckUtils]: 30: Hoare triple {936#false} assume !(0 == ~E_8~0); {936#false} is VALID [2022-02-21 04:24:16,120 INFO L290 TraceCheckUtils]: 31: Hoare triple {936#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {936#false} is VALID [2022-02-21 04:24:16,120 INFO L290 TraceCheckUtils]: 32: Hoare triple {936#false} assume !(1 == ~m_pc~0); {936#false} is VALID [2022-02-21 04:24:16,120 INFO L290 TraceCheckUtils]: 33: Hoare triple {936#false} is_master_triggered_~__retres1~0#1 := 0; {936#false} is VALID [2022-02-21 04:24:16,120 INFO L290 TraceCheckUtils]: 34: Hoare triple {936#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {936#false} is VALID [2022-02-21 04:24:16,120 INFO L290 TraceCheckUtils]: 35: Hoare triple {936#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {936#false} is VALID [2022-02-21 04:24:16,121 INFO L290 TraceCheckUtils]: 36: Hoare triple {936#false} assume !(0 != activate_threads_~tmp~1#1); {936#false} is VALID [2022-02-21 04:24:16,121 INFO L290 TraceCheckUtils]: 37: Hoare triple {936#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {936#false} is VALID [2022-02-21 04:24:16,121 INFO L290 TraceCheckUtils]: 38: Hoare triple {936#false} assume 1 == ~t1_pc~0; {936#false} is VALID [2022-02-21 04:24:16,121 INFO L290 TraceCheckUtils]: 39: Hoare triple {936#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {936#false} is VALID [2022-02-21 04:24:16,122 INFO L290 TraceCheckUtils]: 40: Hoare triple {936#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {936#false} is VALID [2022-02-21 04:24:16,122 INFO L290 TraceCheckUtils]: 41: Hoare triple {936#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {936#false} is VALID [2022-02-21 04:24:16,122 INFO L290 TraceCheckUtils]: 42: Hoare triple {936#false} assume !(0 != activate_threads_~tmp___0~0#1); {936#false} is VALID [2022-02-21 04:24:16,122 INFO L290 TraceCheckUtils]: 43: Hoare triple {936#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {936#false} is VALID [2022-02-21 04:24:16,123 INFO L290 TraceCheckUtils]: 44: Hoare triple {936#false} assume 1 == ~t2_pc~0; {936#false} is VALID [2022-02-21 04:24:16,123 INFO L290 TraceCheckUtils]: 45: Hoare triple {936#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {936#false} is VALID [2022-02-21 04:24:16,124 INFO L290 TraceCheckUtils]: 46: Hoare triple {936#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {936#false} is VALID [2022-02-21 04:24:16,124 INFO L290 TraceCheckUtils]: 47: Hoare triple {936#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {936#false} is VALID [2022-02-21 04:24:16,124 INFO L290 TraceCheckUtils]: 48: Hoare triple {936#false} assume !(0 != activate_threads_~tmp___1~0#1); {936#false} is VALID [2022-02-21 04:24:16,124 INFO L290 TraceCheckUtils]: 49: Hoare triple {936#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {936#false} is VALID [2022-02-21 04:24:16,126 INFO L290 TraceCheckUtils]: 50: Hoare triple {936#false} assume !(1 == ~t3_pc~0); {936#false} is VALID [2022-02-21 04:24:16,127 INFO L290 TraceCheckUtils]: 51: Hoare triple {936#false} is_transmit3_triggered_~__retres1~3#1 := 0; {936#false} is VALID [2022-02-21 04:24:16,127 INFO L290 TraceCheckUtils]: 52: Hoare triple {936#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {936#false} is VALID [2022-02-21 04:24:16,128 INFO L290 TraceCheckUtils]: 53: Hoare triple {936#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {936#false} is VALID [2022-02-21 04:24:16,128 INFO L290 TraceCheckUtils]: 54: Hoare triple {936#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {936#false} is VALID [2022-02-21 04:24:16,129 INFO L290 TraceCheckUtils]: 55: Hoare triple {936#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {936#false} is VALID [2022-02-21 04:24:16,129 INFO L290 TraceCheckUtils]: 56: Hoare triple {936#false} assume 1 == ~t4_pc~0; {936#false} is VALID [2022-02-21 04:24:16,130 INFO L290 TraceCheckUtils]: 57: Hoare triple {936#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {936#false} is VALID [2022-02-21 04:24:16,130 INFO L290 TraceCheckUtils]: 58: Hoare triple {936#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {936#false} is VALID [2022-02-21 04:24:16,130 INFO L290 TraceCheckUtils]: 59: Hoare triple {936#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {936#false} is VALID [2022-02-21 04:24:16,130 INFO L290 TraceCheckUtils]: 60: Hoare triple {936#false} assume !(0 != activate_threads_~tmp___3~0#1); {936#false} is VALID [2022-02-21 04:24:16,131 INFO L290 TraceCheckUtils]: 61: Hoare triple {936#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {936#false} is VALID [2022-02-21 04:24:16,131 INFO L290 TraceCheckUtils]: 62: Hoare triple {936#false} assume !(1 == ~t5_pc~0); {936#false} is VALID [2022-02-21 04:24:16,131 INFO L290 TraceCheckUtils]: 63: Hoare triple {936#false} is_transmit5_triggered_~__retres1~5#1 := 0; {936#false} is VALID [2022-02-21 04:24:16,132 INFO L290 TraceCheckUtils]: 64: Hoare triple {936#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {936#false} is VALID [2022-02-21 04:24:16,133 INFO L290 TraceCheckUtils]: 65: Hoare triple {936#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {936#false} is VALID [2022-02-21 04:24:16,134 INFO L290 TraceCheckUtils]: 66: Hoare triple {936#false} assume !(0 != activate_threads_~tmp___4~0#1); {936#false} is VALID [2022-02-21 04:24:16,134 INFO L290 TraceCheckUtils]: 67: Hoare triple {936#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {936#false} is VALID [2022-02-21 04:24:16,134 INFO L290 TraceCheckUtils]: 68: Hoare triple {936#false} assume 1 == ~t6_pc~0; {936#false} is VALID [2022-02-21 04:24:16,134 INFO L290 TraceCheckUtils]: 69: Hoare triple {936#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {936#false} is VALID [2022-02-21 04:24:16,135 INFO L290 TraceCheckUtils]: 70: Hoare triple {936#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {936#false} is VALID [2022-02-21 04:24:16,135 INFO L290 TraceCheckUtils]: 71: Hoare triple {936#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {936#false} is VALID [2022-02-21 04:24:16,135 INFO L290 TraceCheckUtils]: 72: Hoare triple {936#false} assume !(0 != activate_threads_~tmp___5~0#1); {936#false} is VALID [2022-02-21 04:24:16,135 INFO L290 TraceCheckUtils]: 73: Hoare triple {936#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {936#false} is VALID [2022-02-21 04:24:16,139 INFO L290 TraceCheckUtils]: 74: Hoare triple {936#false} assume !(1 == ~t7_pc~0); {936#false} is VALID [2022-02-21 04:24:16,140 INFO L290 TraceCheckUtils]: 75: Hoare triple {936#false} is_transmit7_triggered_~__retres1~7#1 := 0; {936#false} is VALID [2022-02-21 04:24:16,140 INFO L290 TraceCheckUtils]: 76: Hoare triple {936#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {936#false} is VALID [2022-02-21 04:24:16,140 INFO L290 TraceCheckUtils]: 77: Hoare triple {936#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {936#false} is VALID [2022-02-21 04:24:16,140 INFO L290 TraceCheckUtils]: 78: Hoare triple {936#false} assume !(0 != activate_threads_~tmp___6~0#1); {936#false} is VALID [2022-02-21 04:24:16,140 INFO L290 TraceCheckUtils]: 79: Hoare triple {936#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {936#false} is VALID [2022-02-21 04:24:16,141 INFO L290 TraceCheckUtils]: 80: Hoare triple {936#false} assume 1 == ~t8_pc~0; {936#false} is VALID [2022-02-21 04:24:16,141 INFO L290 TraceCheckUtils]: 81: Hoare triple {936#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {936#false} is VALID [2022-02-21 04:24:16,141 INFO L290 TraceCheckUtils]: 82: Hoare triple {936#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {936#false} is VALID [2022-02-21 04:24:16,141 INFO L290 TraceCheckUtils]: 83: Hoare triple {936#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {936#false} is VALID [2022-02-21 04:24:16,141 INFO L290 TraceCheckUtils]: 84: Hoare triple {936#false} assume !(0 != activate_threads_~tmp___7~0#1); {936#false} is VALID [2022-02-21 04:24:16,142 INFO L290 TraceCheckUtils]: 85: Hoare triple {936#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {936#false} is VALID [2022-02-21 04:24:16,142 INFO L290 TraceCheckUtils]: 86: Hoare triple {936#false} assume !(1 == ~M_E~0); {936#false} is VALID [2022-02-21 04:24:16,142 INFO L290 TraceCheckUtils]: 87: Hoare triple {936#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {936#false} is VALID [2022-02-21 04:24:16,142 INFO L290 TraceCheckUtils]: 88: Hoare triple {936#false} assume !(1 == ~T2_E~0); {936#false} is VALID [2022-02-21 04:24:16,142 INFO L290 TraceCheckUtils]: 89: Hoare triple {936#false} assume !(1 == ~T3_E~0); {936#false} is VALID [2022-02-21 04:24:16,143 INFO L290 TraceCheckUtils]: 90: Hoare triple {936#false} assume !(1 == ~T4_E~0); {936#false} is VALID [2022-02-21 04:24:16,143 INFO L290 TraceCheckUtils]: 91: Hoare triple {936#false} assume !(1 == ~T5_E~0); {936#false} is VALID [2022-02-21 04:24:16,143 INFO L290 TraceCheckUtils]: 92: Hoare triple {936#false} assume !(1 == ~T6_E~0); {936#false} is VALID [2022-02-21 04:24:16,143 INFO L290 TraceCheckUtils]: 93: Hoare triple {936#false} assume !(1 == ~T7_E~0); {936#false} is VALID [2022-02-21 04:24:16,143 INFO L290 TraceCheckUtils]: 94: Hoare triple {936#false} assume !(1 == ~T8_E~0); {936#false} is VALID [2022-02-21 04:24:16,144 INFO L290 TraceCheckUtils]: 95: Hoare triple {936#false} assume 1 == ~E_1~0;~E_1~0 := 2; {936#false} is VALID [2022-02-21 04:24:16,144 INFO L290 TraceCheckUtils]: 96: Hoare triple {936#false} assume !(1 == ~E_2~0); {936#false} is VALID [2022-02-21 04:24:16,144 INFO L290 TraceCheckUtils]: 97: Hoare triple {936#false} assume !(1 == ~E_3~0); {936#false} is VALID [2022-02-21 04:24:16,144 INFO L290 TraceCheckUtils]: 98: Hoare triple {936#false} assume !(1 == ~E_4~0); {936#false} is VALID [2022-02-21 04:24:16,144 INFO L290 TraceCheckUtils]: 99: Hoare triple {936#false} assume !(1 == ~E_5~0); {936#false} is VALID [2022-02-21 04:24:16,144 INFO L290 TraceCheckUtils]: 100: Hoare triple {936#false} assume !(1 == ~E_6~0); {936#false} is VALID [2022-02-21 04:24:16,145 INFO L290 TraceCheckUtils]: 101: Hoare triple {936#false} assume !(1 == ~E_7~0); {936#false} is VALID [2022-02-21 04:24:16,145 INFO L290 TraceCheckUtils]: 102: Hoare triple {936#false} assume !(1 == ~E_8~0); {936#false} is VALID [2022-02-21 04:24:16,145 INFO L290 TraceCheckUtils]: 103: Hoare triple {936#false} assume { :end_inline_reset_delta_events } true; {936#false} is VALID [2022-02-21 04:24:16,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:16,147 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:16,147 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218842817] [2022-02-21 04:24:16,148 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1218842817] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:16,148 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:16,149 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:16,150 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561855486] [2022-02-21 04:24:16,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:16,154 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:16,156 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:16,157 INFO L85 PathProgramCache]: Analyzing trace with hash -650170989, now seen corresponding path program 1 times [2022-02-21 04:24:16,157 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:16,157 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506888485] [2022-02-21 04:24:16,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:16,157 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:16,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:16,209 INFO L290 TraceCheckUtils]: 0: Hoare triple {938#true} assume !false; {938#true} is VALID [2022-02-21 04:24:16,209 INFO L290 TraceCheckUtils]: 1: Hoare triple {938#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {938#true} is VALID [2022-02-21 04:24:16,211 INFO L290 TraceCheckUtils]: 2: Hoare triple {938#true} assume false; {939#false} is VALID [2022-02-21 04:24:16,211 INFO L290 TraceCheckUtils]: 3: Hoare triple {939#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {939#false} is VALID [2022-02-21 04:24:16,211 INFO L290 TraceCheckUtils]: 4: Hoare triple {939#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {939#false} is VALID [2022-02-21 04:24:16,212 INFO L290 TraceCheckUtils]: 5: Hoare triple {939#false} assume !(0 == ~M_E~0); {939#false} is VALID [2022-02-21 04:24:16,212 INFO L290 TraceCheckUtils]: 6: Hoare triple {939#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,212 INFO L290 TraceCheckUtils]: 7: Hoare triple {939#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,212 INFO L290 TraceCheckUtils]: 8: Hoare triple {939#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,212 INFO L290 TraceCheckUtils]: 9: Hoare triple {939#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,213 INFO L290 TraceCheckUtils]: 10: Hoare triple {939#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,214 INFO L290 TraceCheckUtils]: 11: Hoare triple {939#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,214 INFO L290 TraceCheckUtils]: 12: Hoare triple {939#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,215 INFO L290 TraceCheckUtils]: 13: Hoare triple {939#false} assume !(0 == ~T8_E~0); {939#false} is VALID [2022-02-21 04:24:16,216 INFO L290 TraceCheckUtils]: 14: Hoare triple {939#false} assume 0 == ~E_1~0;~E_1~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,222 INFO L290 TraceCheckUtils]: 15: Hoare triple {939#false} assume 0 == ~E_2~0;~E_2~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,223 INFO L290 TraceCheckUtils]: 16: Hoare triple {939#false} assume 0 == ~E_3~0;~E_3~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,223 INFO L290 TraceCheckUtils]: 17: Hoare triple {939#false} assume 0 == ~E_4~0;~E_4~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,223 INFO L290 TraceCheckUtils]: 18: Hoare triple {939#false} assume 0 == ~E_5~0;~E_5~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,226 INFO L290 TraceCheckUtils]: 19: Hoare triple {939#false} assume 0 == ~E_6~0;~E_6~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,226 INFO L290 TraceCheckUtils]: 20: Hoare triple {939#false} assume 0 == ~E_7~0;~E_7~0 := 1; {939#false} is VALID [2022-02-21 04:24:16,227 INFO L290 TraceCheckUtils]: 21: Hoare triple {939#false} assume !(0 == ~E_8~0); {939#false} is VALID [2022-02-21 04:24:16,227 INFO L290 TraceCheckUtils]: 22: Hoare triple {939#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {939#false} is VALID [2022-02-21 04:24:16,227 INFO L290 TraceCheckUtils]: 23: Hoare triple {939#false} assume 1 == ~m_pc~0; {939#false} is VALID [2022-02-21 04:24:16,227 INFO L290 TraceCheckUtils]: 24: Hoare triple {939#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {939#false} is VALID [2022-02-21 04:24:16,227 INFO L290 TraceCheckUtils]: 25: Hoare triple {939#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {939#false} is VALID [2022-02-21 04:24:16,228 INFO L290 TraceCheckUtils]: 26: Hoare triple {939#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {939#false} is VALID [2022-02-21 04:24:16,228 INFO L290 TraceCheckUtils]: 27: Hoare triple {939#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {939#false} is VALID [2022-02-21 04:24:16,228 INFO L290 TraceCheckUtils]: 28: Hoare triple {939#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {939#false} is VALID [2022-02-21 04:24:16,228 INFO L290 TraceCheckUtils]: 29: Hoare triple {939#false} assume !(1 == ~t1_pc~0); {939#false} is VALID [2022-02-21 04:24:16,228 INFO L290 TraceCheckUtils]: 30: Hoare triple {939#false} is_transmit1_triggered_~__retres1~1#1 := 0; {939#false} is VALID [2022-02-21 04:24:16,228 INFO L290 TraceCheckUtils]: 31: Hoare triple {939#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {939#false} is VALID [2022-02-21 04:24:16,229 INFO L290 TraceCheckUtils]: 32: Hoare triple {939#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {939#false} is VALID [2022-02-21 04:24:16,229 INFO L290 TraceCheckUtils]: 33: Hoare triple {939#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {939#false} is VALID [2022-02-21 04:24:16,229 INFO L290 TraceCheckUtils]: 34: Hoare triple {939#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {939#false} is VALID [2022-02-21 04:24:16,230 INFO L290 TraceCheckUtils]: 35: Hoare triple {939#false} assume 1 == ~t2_pc~0; {939#false} is VALID [2022-02-21 04:24:16,230 INFO L290 TraceCheckUtils]: 36: Hoare triple {939#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {939#false} is VALID [2022-02-21 04:24:16,230 INFO L290 TraceCheckUtils]: 37: Hoare triple {939#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {939#false} is VALID [2022-02-21 04:24:16,230 INFO L290 TraceCheckUtils]: 38: Hoare triple {939#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {939#false} is VALID [2022-02-21 04:24:16,231 INFO L290 TraceCheckUtils]: 39: Hoare triple {939#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {939#false} is VALID [2022-02-21 04:24:16,231 INFO L290 TraceCheckUtils]: 40: Hoare triple {939#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {939#false} is VALID [2022-02-21 04:24:16,231 INFO L290 TraceCheckUtils]: 41: Hoare triple {939#false} assume 1 == ~t3_pc~0; {939#false} is VALID [2022-02-21 04:24:16,231 INFO L290 TraceCheckUtils]: 42: Hoare triple {939#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {939#false} is VALID [2022-02-21 04:24:16,231 INFO L290 TraceCheckUtils]: 43: Hoare triple {939#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {939#false} is VALID [2022-02-21 04:24:16,231 INFO L290 TraceCheckUtils]: 44: Hoare triple {939#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {939#false} is VALID [2022-02-21 04:24:16,232 INFO L290 TraceCheckUtils]: 45: Hoare triple {939#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {939#false} is VALID [2022-02-21 04:24:16,232 INFO L290 TraceCheckUtils]: 46: Hoare triple {939#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {939#false} is VALID [2022-02-21 04:24:16,232 INFO L290 TraceCheckUtils]: 47: Hoare triple {939#false} assume !(1 == ~t4_pc~0); {939#false} is VALID [2022-02-21 04:24:16,232 INFO L290 TraceCheckUtils]: 48: Hoare triple {939#false} is_transmit4_triggered_~__retres1~4#1 := 0; {939#false} is VALID [2022-02-21 04:24:16,232 INFO L290 TraceCheckUtils]: 49: Hoare triple {939#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {939#false} is VALID [2022-02-21 04:24:16,232 INFO L290 TraceCheckUtils]: 50: Hoare triple {939#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {939#false} is VALID [2022-02-21 04:24:16,233 INFO L290 TraceCheckUtils]: 51: Hoare triple {939#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {939#false} is VALID [2022-02-21 04:24:16,233 INFO L290 TraceCheckUtils]: 52: Hoare triple {939#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {939#false} is VALID [2022-02-21 04:24:16,233 INFO L290 TraceCheckUtils]: 53: Hoare triple {939#false} assume !(1 == ~t5_pc~0); {939#false} is VALID [2022-02-21 04:24:16,233 INFO L290 TraceCheckUtils]: 54: Hoare triple {939#false} is_transmit5_triggered_~__retres1~5#1 := 0; {939#false} is VALID [2022-02-21 04:24:16,233 INFO L290 TraceCheckUtils]: 55: Hoare triple {939#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {939#false} is VALID [2022-02-21 04:24:16,234 INFO L290 TraceCheckUtils]: 56: Hoare triple {939#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {939#false} is VALID [2022-02-21 04:24:16,234 INFO L290 TraceCheckUtils]: 57: Hoare triple {939#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {939#false} is VALID [2022-02-21 04:24:16,234 INFO L290 TraceCheckUtils]: 58: Hoare triple {939#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {939#false} is VALID [2022-02-21 04:24:16,234 INFO L290 TraceCheckUtils]: 59: Hoare triple {939#false} assume 1 == ~t6_pc~0; {939#false} is VALID [2022-02-21 04:24:16,234 INFO L290 TraceCheckUtils]: 60: Hoare triple {939#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {939#false} is VALID [2022-02-21 04:24:16,234 INFO L290 TraceCheckUtils]: 61: Hoare triple {939#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {939#false} is VALID [2022-02-21 04:24:16,235 INFO L290 TraceCheckUtils]: 62: Hoare triple {939#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {939#false} is VALID [2022-02-21 04:24:16,235 INFO L290 TraceCheckUtils]: 63: Hoare triple {939#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {939#false} is VALID [2022-02-21 04:24:16,235 INFO L290 TraceCheckUtils]: 64: Hoare triple {939#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {939#false} is VALID [2022-02-21 04:24:16,235 INFO L290 TraceCheckUtils]: 65: Hoare triple {939#false} assume !(1 == ~t7_pc~0); {939#false} is VALID [2022-02-21 04:24:16,235 INFO L290 TraceCheckUtils]: 66: Hoare triple {939#false} is_transmit7_triggered_~__retres1~7#1 := 0; {939#false} is VALID [2022-02-21 04:24:16,235 INFO L290 TraceCheckUtils]: 67: Hoare triple {939#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {939#false} is VALID [2022-02-21 04:24:16,236 INFO L290 TraceCheckUtils]: 68: Hoare triple {939#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {939#false} is VALID [2022-02-21 04:24:16,236 INFO L290 TraceCheckUtils]: 69: Hoare triple {939#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {939#false} is VALID [2022-02-21 04:24:16,237 INFO L290 TraceCheckUtils]: 70: Hoare triple {939#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {939#false} is VALID [2022-02-21 04:24:16,237 INFO L290 TraceCheckUtils]: 71: Hoare triple {939#false} assume !(1 == ~t8_pc~0); {939#false} is VALID [2022-02-21 04:24:16,239 INFO L290 TraceCheckUtils]: 72: Hoare triple {939#false} is_transmit8_triggered_~__retres1~8#1 := 0; {939#false} is VALID [2022-02-21 04:24:16,239 INFO L290 TraceCheckUtils]: 73: Hoare triple {939#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {939#false} is VALID [2022-02-21 04:24:16,240 INFO L290 TraceCheckUtils]: 74: Hoare triple {939#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {939#false} is VALID [2022-02-21 04:24:16,240 INFO L290 TraceCheckUtils]: 75: Hoare triple {939#false} assume !(0 != activate_threads_~tmp___7~0#1); {939#false} is VALID [2022-02-21 04:24:16,240 INFO L290 TraceCheckUtils]: 76: Hoare triple {939#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {939#false} is VALID [2022-02-21 04:24:16,240 INFO L290 TraceCheckUtils]: 77: Hoare triple {939#false} assume 1 == ~M_E~0;~M_E~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,240 INFO L290 TraceCheckUtils]: 78: Hoare triple {939#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,240 INFO L290 TraceCheckUtils]: 79: Hoare triple {939#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,241 INFO L290 TraceCheckUtils]: 80: Hoare triple {939#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,242 INFO L290 TraceCheckUtils]: 81: Hoare triple {939#false} assume !(1 == ~T4_E~0); {939#false} is VALID [2022-02-21 04:24:16,242 INFO L290 TraceCheckUtils]: 82: Hoare triple {939#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,242 INFO L290 TraceCheckUtils]: 83: Hoare triple {939#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,242 INFO L290 TraceCheckUtils]: 84: Hoare triple {939#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,242 INFO L290 TraceCheckUtils]: 85: Hoare triple {939#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,242 INFO L290 TraceCheckUtils]: 86: Hoare triple {939#false} assume 1 == ~E_1~0;~E_1~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,243 INFO L290 TraceCheckUtils]: 87: Hoare triple {939#false} assume 1 == ~E_2~0;~E_2~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,243 INFO L290 TraceCheckUtils]: 88: Hoare triple {939#false} assume 1 == ~E_3~0;~E_3~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,243 INFO L290 TraceCheckUtils]: 89: Hoare triple {939#false} assume !(1 == ~E_4~0); {939#false} is VALID [2022-02-21 04:24:16,244 INFO L290 TraceCheckUtils]: 90: Hoare triple {939#false} assume 1 == ~E_5~0;~E_5~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,244 INFO L290 TraceCheckUtils]: 91: Hoare triple {939#false} assume 1 == ~E_6~0;~E_6~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,244 INFO L290 TraceCheckUtils]: 92: Hoare triple {939#false} assume 1 == ~E_7~0;~E_7~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,244 INFO L290 TraceCheckUtils]: 93: Hoare triple {939#false} assume 1 == ~E_8~0;~E_8~0 := 2; {939#false} is VALID [2022-02-21 04:24:16,244 INFO L290 TraceCheckUtils]: 94: Hoare triple {939#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {939#false} is VALID [2022-02-21 04:24:16,245 INFO L290 TraceCheckUtils]: 95: Hoare triple {939#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {939#false} is VALID [2022-02-21 04:24:16,245 INFO L290 TraceCheckUtils]: 96: Hoare triple {939#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {939#false} is VALID [2022-02-21 04:24:16,245 INFO L290 TraceCheckUtils]: 97: Hoare triple {939#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {939#false} is VALID [2022-02-21 04:24:16,245 INFO L290 TraceCheckUtils]: 98: Hoare triple {939#false} assume !(0 == start_simulation_~tmp~3#1); {939#false} is VALID [2022-02-21 04:24:16,245 INFO L290 TraceCheckUtils]: 99: Hoare triple {939#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {939#false} is VALID [2022-02-21 04:24:16,248 INFO L290 TraceCheckUtils]: 100: Hoare triple {939#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {939#false} is VALID [2022-02-21 04:24:16,248 INFO L290 TraceCheckUtils]: 101: Hoare triple {939#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {939#false} is VALID [2022-02-21 04:24:16,248 INFO L290 TraceCheckUtils]: 102: Hoare triple {939#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {939#false} is VALID [2022-02-21 04:24:16,249 INFO L290 TraceCheckUtils]: 103: Hoare triple {939#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {939#false} is VALID [2022-02-21 04:24:16,249 INFO L290 TraceCheckUtils]: 104: Hoare triple {939#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {939#false} is VALID [2022-02-21 04:24:16,249 INFO L290 TraceCheckUtils]: 105: Hoare triple {939#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {939#false} is VALID [2022-02-21 04:24:16,249 INFO L290 TraceCheckUtils]: 106: Hoare triple {939#false} assume !(0 != start_simulation_~tmp___0~1#1); {939#false} is VALID [2022-02-21 04:24:16,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:16,251 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:16,251 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1506888485] [2022-02-21 04:24:16,251 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1506888485] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:16,251 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:16,252 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:16,252 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1787561411] [2022-02-21 04:24:16,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:16,253 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:16,254 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:16,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:16,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:16,280 INFO L87 Difference]: Start difference. First operand has 931 states, 930 states have (on average 1.5182795698924731) internal successors, (1412), 930 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,099 INFO L93 Difference]: Finished difference Result 930 states and 1385 transitions. [2022-02-21 04:24:17,099 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:17,100 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,170 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:17,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 930 states and 1385 transitions. [2022-02-21 04:24:17,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:17,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 930 states to 924 states and 1379 transitions. [2022-02-21 04:24:17,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-02-21 04:24:17,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-02-21 04:24:17,239 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1379 transitions. [2022-02-21 04:24:17,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:17,242 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1379 transitions. [2022-02-21 04:24:17,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1379 transitions. [2022-02-21 04:24:17,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-02-21 04:24:17,282 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:17,285 INFO L82 GeneralOperation]: Start isEquivalent. First operand 924 states and 1379 transitions. Second operand has 924 states, 924 states have (on average 1.4924242424242424) internal successors, (1379), 923 states have internal predecessors, (1379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,288 INFO L74 IsIncluded]: Start isIncluded. First operand 924 states and 1379 transitions. Second operand has 924 states, 924 states have (on average 1.4924242424242424) internal successors, (1379), 923 states have internal predecessors, (1379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,291 INFO L87 Difference]: Start difference. First operand 924 states and 1379 transitions. Second operand has 924 states, 924 states have (on average 1.4924242424242424) internal successors, (1379), 923 states have internal predecessors, (1379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,322 INFO L93 Difference]: Finished difference Result 924 states and 1379 transitions. [2022-02-21 04:24:17,322 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1379 transitions. [2022-02-21 04:24:17,326 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:17,326 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:17,328 INFO L74 IsIncluded]: Start isIncluded. First operand has 924 states, 924 states have (on average 1.4924242424242424) internal successors, (1379), 923 states have internal predecessors, (1379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1379 transitions. [2022-02-21 04:24:17,329 INFO L87 Difference]: Start difference. First operand has 924 states, 924 states have (on average 1.4924242424242424) internal successors, (1379), 923 states have internal predecessors, (1379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1379 transitions. [2022-02-21 04:24:17,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:17,355 INFO L93 Difference]: Finished difference Result 924 states and 1379 transitions. [2022-02-21 04:24:17,355 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1379 transitions. [2022-02-21 04:24:17,357 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:17,357 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:17,357 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:17,357 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:17,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4924242424242424) internal successors, (1379), 923 states have internal predecessors, (1379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1379 transitions. [2022-02-21 04:24:17,384 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1379 transitions. [2022-02-21 04:24:17,384 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1379 transitions. [2022-02-21 04:24:17,384 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:17,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1379 transitions. [2022-02-21 04:24:17,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:17,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:17,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:17,389 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,389 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,389 INFO L791 eck$LassoCheckResult]: Stem: 2546#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2789#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1961#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1962#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 2233#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2234#L586-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2731#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2721#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2301#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2302#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2526#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2527#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2383#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2384#L838 assume !(0 == ~M_E~0); 2533#L838-2 assume !(0 == ~T1_E~0); 1923#L843-1 assume !(0 == ~T2_E~0); 1924#L848-1 assume !(0 == ~T3_E~0); 2043#L853-1 assume !(0 == ~T4_E~0); 2369#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1870#L863-1 assume !(0 == ~T6_E~0); 1871#L868-1 assume !(0 == ~T7_E~0); 2763#L873-1 assume !(0 == ~T8_E~0); 2761#L878-1 assume !(0 == ~E_1~0); 2750#L883-1 assume !(0 == ~E_2~0); 2751#L888-1 assume !(0 == ~E_3~0); 2498#L893-1 assume !(0 == ~E_4~0); 2499#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2775#L903-1 assume !(0 == ~E_6~0); 2749#L908-1 assume !(0 == ~E_7~0); 2623#L913-1 assume !(0 == ~E_8~0); 1937#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1938#L402 assume !(1 == ~m_pc~0); 2146#L402-2 is_master_triggered_~__retres1~0#1 := 0; 2064#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2065#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2307#L1035 assume !(0 != activate_threads_~tmp~1#1); 2308#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2360#L421 assume 1 == ~t1_pc~0; 2745#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2764#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2352#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2353#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 2411#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2772#L440 assume 1 == ~t2_pc~0; 1907#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1908#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2074#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2783#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 2637#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2261#L459 assume !(1 == ~t3_pc~0); 2262#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2744#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2568#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2058#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2059#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2068#L478 assume 1 == ~t4_pc~0; 2069#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2503#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2730#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2239#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1982#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1983#L497 assume !(1 == ~t5_pc~0); 2029#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2030#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2321#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2322#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 2737#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2738#L516 assume 1 == ~t6_pc~0; 2792#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2524#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2525#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2113#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 2114#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2515#L535 assume !(1 == ~t7_pc~0); 2516#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2585#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2586#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2614#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 2604#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2605#L554 assume 1 == ~t8_pc~0; 2554#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1899#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2655#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2201#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 2202#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1883#L931 assume !(1 == ~M_E~0); 1884#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2758#L936-1 assume !(1 == ~T2_E~0); 2781#L941-1 assume !(1 == ~T3_E~0); 2361#L946-1 assume !(1 == ~T4_E~0); 2362#L951-1 assume !(1 == ~T5_E~0); 2128#L956-1 assume !(1 == ~T6_E~0); 2129#L961-1 assume !(1 == ~T7_E~0); 2500#L966-1 assume !(1 == ~T8_E~0); 2501#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2607#L976-1 assume !(1 == ~E_2~0); 2577#L981-1 assume !(1 == ~E_3~0); 2366#L986-1 assume !(1 == ~E_4~0); 2158#L991-1 assume !(1 == ~E_5~0); 2159#L996-1 assume !(1 == ~E_6~0); 2768#L1001-1 assume !(1 == ~E_7~0); 2544#L1006-1 assume !(1 == ~E_8~0); 2545#L1011-1 assume { :end_inline_reset_delta_events } true; 1946#L1272-2 [2022-02-21 04:24:17,391 INFO L793 eck$LassoCheckResult]: Loop: 1946#L1272-2 assume !false; 1947#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1948#L813 assume !false; 1949#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2695#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1951#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2495#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2505#L696 assume !(0 != eval_~tmp~0#1); 2548#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2549#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2670#L838-3 assume !(0 == ~M_E~0); 2590#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2591#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2453#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2454#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2502#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2565#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2557#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2558#L873-3 assume !(0 == ~T8_E~0); 2181#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1910#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1911#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1912#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1913#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2387#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2696#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2400#L913-3 assume !(0 == ~E_8~0); 1953#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1954#L402-27 assume 1 == ~m_pc~0; 1900#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1901#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2390#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2391#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2709#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2710#L421-27 assume !(1 == ~t1_pc~0); 2173#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2174#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2423#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2424#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2769#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2518#L440-27 assume 1 == ~t2_pc~0; 2519#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2692#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2257#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2258#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2432#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2161#L459-27 assume !(1 == ~t3_pc~0); 2162#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2580#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2225#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2226#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2514#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2762#L478-27 assume 1 == ~t4_pc~0; 2784#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2152#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2528#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2660#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2661#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2697#L497-27 assume 1 == ~t5_pc~0; 2698#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2190#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2191#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2134#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2135#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2392#L516-27 assume 1 == ~t6_pc~0; 2393#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2247#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2248#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2395#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2535#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2324#L535-27 assume 1 == ~t7_pc~0; 2325#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2641#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2671#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2672#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2278#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2279#L554-27 assume !(1 == ~t8_pc~0); 1927#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1928#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2073#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2412#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 2178#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2179#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2054#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2055#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2275#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2407#L946-3 assume !(1 == ~T4_E~0); 2196#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2197#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2476#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2285#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2286#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2523#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1944#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1945#L986-3 assume !(1 == ~E_4~0); 1935#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1936#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2595#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2266#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2267#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1977#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1979#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2293#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2294#L1291 assume !(0 == start_simulation_~tmp~3#1); 2473#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2379#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1874#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1875#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2679#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2343#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2344#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2560#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1946#L1272-2 [2022-02-21 04:24:17,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,391 INFO L85 PathProgramCache]: Analyzing trace with hash 500214492, now seen corresponding path program 1 times [2022-02-21 04:24:17,391 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,391 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [270795469] [2022-02-21 04:24:17,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,435 INFO L290 TraceCheckUtils]: 0: Hoare triple {4645#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {4645#true} is VALID [2022-02-21 04:24:17,436 INFO L290 TraceCheckUtils]: 1: Hoare triple {4645#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {4647#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:17,436 INFO L290 TraceCheckUtils]: 2: Hoare triple {4647#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {4647#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:17,436 INFO L290 TraceCheckUtils]: 3: Hoare triple {4647#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {4647#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:17,437 INFO L290 TraceCheckUtils]: 4: Hoare triple {4647#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {4647#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:17,437 INFO L290 TraceCheckUtils]: 5: Hoare triple {4647#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {4647#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:17,437 INFO L290 TraceCheckUtils]: 6: Hoare triple {4647#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {4646#false} is VALID [2022-02-21 04:24:17,437 INFO L290 TraceCheckUtils]: 7: Hoare triple {4646#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {4646#false} is VALID [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 8: Hoare triple {4646#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {4646#false} is VALID [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 9: Hoare triple {4646#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {4646#false} is VALID [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 10: Hoare triple {4646#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {4646#false} is VALID [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 11: Hoare triple {4646#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {4646#false} is VALID [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 12: Hoare triple {4646#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {4646#false} is VALID [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 13: Hoare triple {4646#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {4646#false} is VALID [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 14: Hoare triple {4646#false} assume !(0 == ~M_E~0); {4646#false} is VALID [2022-02-21 04:24:17,438 INFO L290 TraceCheckUtils]: 15: Hoare triple {4646#false} assume !(0 == ~T1_E~0); {4646#false} is VALID [2022-02-21 04:24:17,439 INFO L290 TraceCheckUtils]: 16: Hoare triple {4646#false} assume !(0 == ~T2_E~0); {4646#false} is VALID [2022-02-21 04:24:17,439 INFO L290 TraceCheckUtils]: 17: Hoare triple {4646#false} assume !(0 == ~T3_E~0); {4646#false} is VALID [2022-02-21 04:24:17,439 INFO L290 TraceCheckUtils]: 18: Hoare triple {4646#false} assume !(0 == ~T4_E~0); {4646#false} is VALID [2022-02-21 04:24:17,439 INFO L290 TraceCheckUtils]: 19: Hoare triple {4646#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {4646#false} is VALID [2022-02-21 04:24:17,439 INFO L290 TraceCheckUtils]: 20: Hoare triple {4646#false} assume !(0 == ~T6_E~0); {4646#false} is VALID [2022-02-21 04:24:17,439 INFO L290 TraceCheckUtils]: 21: Hoare triple {4646#false} assume !(0 == ~T7_E~0); {4646#false} is VALID [2022-02-21 04:24:17,439 INFO L290 TraceCheckUtils]: 22: Hoare triple {4646#false} assume !(0 == ~T8_E~0); {4646#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 23: Hoare triple {4646#false} assume !(0 == ~E_1~0); {4646#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 24: Hoare triple {4646#false} assume !(0 == ~E_2~0); {4646#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 25: Hoare triple {4646#false} assume !(0 == ~E_3~0); {4646#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 26: Hoare triple {4646#false} assume !(0 == ~E_4~0); {4646#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 27: Hoare triple {4646#false} assume 0 == ~E_5~0;~E_5~0 := 1; {4646#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 28: Hoare triple {4646#false} assume !(0 == ~E_6~0); {4646#false} is VALID [2022-02-21 04:24:17,440 INFO L290 TraceCheckUtils]: 29: Hoare triple {4646#false} assume !(0 == ~E_7~0); {4646#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 30: Hoare triple {4646#false} assume !(0 == ~E_8~0); {4646#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 31: Hoare triple {4646#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4646#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 32: Hoare triple {4646#false} assume !(1 == ~m_pc~0); {4646#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 33: Hoare triple {4646#false} is_master_triggered_~__retres1~0#1 := 0; {4646#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 34: Hoare triple {4646#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4646#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 35: Hoare triple {4646#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {4646#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 36: Hoare triple {4646#false} assume !(0 != activate_threads_~tmp~1#1); {4646#false} is VALID [2022-02-21 04:24:17,441 INFO L290 TraceCheckUtils]: 37: Hoare triple {4646#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4646#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 38: Hoare triple {4646#false} assume 1 == ~t1_pc~0; {4646#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 39: Hoare triple {4646#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {4646#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 40: Hoare triple {4646#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4646#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 41: Hoare triple {4646#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {4646#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 42: Hoare triple {4646#false} assume !(0 != activate_threads_~tmp___0~0#1); {4646#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 43: Hoare triple {4646#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4646#false} is VALID [2022-02-21 04:24:17,442 INFO L290 TraceCheckUtils]: 44: Hoare triple {4646#false} assume 1 == ~t2_pc~0; {4646#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 45: Hoare triple {4646#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {4646#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 46: Hoare triple {4646#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4646#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 47: Hoare triple {4646#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {4646#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 48: Hoare triple {4646#false} assume !(0 != activate_threads_~tmp___1~0#1); {4646#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 49: Hoare triple {4646#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4646#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 50: Hoare triple {4646#false} assume !(1 == ~t3_pc~0); {4646#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 51: Hoare triple {4646#false} is_transmit3_triggered_~__retres1~3#1 := 0; {4646#false} is VALID [2022-02-21 04:24:17,443 INFO L290 TraceCheckUtils]: 52: Hoare triple {4646#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4646#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 53: Hoare triple {4646#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {4646#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 54: Hoare triple {4646#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {4646#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 55: Hoare triple {4646#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {4646#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 56: Hoare triple {4646#false} assume 1 == ~t4_pc~0; {4646#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 57: Hoare triple {4646#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {4646#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 58: Hoare triple {4646#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {4646#false} is VALID [2022-02-21 04:24:17,444 INFO L290 TraceCheckUtils]: 59: Hoare triple {4646#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {4646#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 60: Hoare triple {4646#false} assume !(0 != activate_threads_~tmp___3~0#1); {4646#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 61: Hoare triple {4646#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {4646#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 62: Hoare triple {4646#false} assume !(1 == ~t5_pc~0); {4646#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 63: Hoare triple {4646#false} is_transmit5_triggered_~__retres1~5#1 := 0; {4646#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 64: Hoare triple {4646#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {4646#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 65: Hoare triple {4646#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {4646#false} is VALID [2022-02-21 04:24:17,445 INFO L290 TraceCheckUtils]: 66: Hoare triple {4646#false} assume !(0 != activate_threads_~tmp___4~0#1); {4646#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 67: Hoare triple {4646#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {4646#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 68: Hoare triple {4646#false} assume 1 == ~t6_pc~0; {4646#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 69: Hoare triple {4646#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {4646#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 70: Hoare triple {4646#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {4646#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 71: Hoare triple {4646#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {4646#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 72: Hoare triple {4646#false} assume !(0 != activate_threads_~tmp___5~0#1); {4646#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 73: Hoare triple {4646#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {4646#false} is VALID [2022-02-21 04:24:17,446 INFO L290 TraceCheckUtils]: 74: Hoare triple {4646#false} assume !(1 == ~t7_pc~0); {4646#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 75: Hoare triple {4646#false} is_transmit7_triggered_~__retres1~7#1 := 0; {4646#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 76: Hoare triple {4646#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {4646#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 77: Hoare triple {4646#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {4646#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 78: Hoare triple {4646#false} assume !(0 != activate_threads_~tmp___6~0#1); {4646#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 79: Hoare triple {4646#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {4646#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 80: Hoare triple {4646#false} assume 1 == ~t8_pc~0; {4646#false} is VALID [2022-02-21 04:24:17,447 INFO L290 TraceCheckUtils]: 81: Hoare triple {4646#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {4646#false} is VALID [2022-02-21 04:24:17,448 INFO L290 TraceCheckUtils]: 82: Hoare triple {4646#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {4646#false} is VALID [2022-02-21 04:24:17,448 INFO L290 TraceCheckUtils]: 83: Hoare triple {4646#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {4646#false} is VALID [2022-02-21 04:24:17,448 INFO L290 TraceCheckUtils]: 84: Hoare triple {4646#false} assume !(0 != activate_threads_~tmp___7~0#1); {4646#false} is VALID [2022-02-21 04:24:17,448 INFO L290 TraceCheckUtils]: 85: Hoare triple {4646#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4646#false} is VALID [2022-02-21 04:24:17,466 INFO L290 TraceCheckUtils]: 86: Hoare triple {4646#false} assume !(1 == ~M_E~0); {4646#false} is VALID [2022-02-21 04:24:17,469 INFO L290 TraceCheckUtils]: 87: Hoare triple {4646#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {4646#false} is VALID [2022-02-21 04:24:17,469 INFO L290 TraceCheckUtils]: 88: Hoare triple {4646#false} assume !(1 == ~T2_E~0); {4646#false} is VALID [2022-02-21 04:24:17,469 INFO L290 TraceCheckUtils]: 89: Hoare triple {4646#false} assume !(1 == ~T3_E~0); {4646#false} is VALID [2022-02-21 04:24:17,469 INFO L290 TraceCheckUtils]: 90: Hoare triple {4646#false} assume !(1 == ~T4_E~0); {4646#false} is VALID [2022-02-21 04:24:17,469 INFO L290 TraceCheckUtils]: 91: Hoare triple {4646#false} assume !(1 == ~T5_E~0); {4646#false} is VALID [2022-02-21 04:24:17,470 INFO L290 TraceCheckUtils]: 92: Hoare triple {4646#false} assume !(1 == ~T6_E~0); {4646#false} is VALID [2022-02-21 04:24:17,470 INFO L290 TraceCheckUtils]: 93: Hoare triple {4646#false} assume !(1 == ~T7_E~0); {4646#false} is VALID [2022-02-21 04:24:17,470 INFO L290 TraceCheckUtils]: 94: Hoare triple {4646#false} assume !(1 == ~T8_E~0); {4646#false} is VALID [2022-02-21 04:24:17,470 INFO L290 TraceCheckUtils]: 95: Hoare triple {4646#false} assume 1 == ~E_1~0;~E_1~0 := 2; {4646#false} is VALID [2022-02-21 04:24:17,470 INFO L290 TraceCheckUtils]: 96: Hoare triple {4646#false} assume !(1 == ~E_2~0); {4646#false} is VALID [2022-02-21 04:24:17,470 INFO L290 TraceCheckUtils]: 97: Hoare triple {4646#false} assume !(1 == ~E_3~0); {4646#false} is VALID [2022-02-21 04:24:17,470 INFO L290 TraceCheckUtils]: 98: Hoare triple {4646#false} assume !(1 == ~E_4~0); {4646#false} is VALID [2022-02-21 04:24:17,471 INFO L290 TraceCheckUtils]: 99: Hoare triple {4646#false} assume !(1 == ~E_5~0); {4646#false} is VALID [2022-02-21 04:24:17,471 INFO L290 TraceCheckUtils]: 100: Hoare triple {4646#false} assume !(1 == ~E_6~0); {4646#false} is VALID [2022-02-21 04:24:17,471 INFO L290 TraceCheckUtils]: 101: Hoare triple {4646#false} assume !(1 == ~E_7~0); {4646#false} is VALID [2022-02-21 04:24:17,471 INFO L290 TraceCheckUtils]: 102: Hoare triple {4646#false} assume !(1 == ~E_8~0); {4646#false} is VALID [2022-02-21 04:24:17,471 INFO L290 TraceCheckUtils]: 103: Hoare triple {4646#false} assume { :end_inline_reset_delta_events } true; {4646#false} is VALID [2022-02-21 04:24:17,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,472 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,472 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [270795469] [2022-02-21 04:24:17,472 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [270795469] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,472 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,472 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:17,472 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [782235913] [2022-02-21 04:24:17,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,473 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:17,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,473 INFO L85 PathProgramCache]: Analyzing trace with hash 1268138686, now seen corresponding path program 1 times [2022-02-21 04:24:17,474 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,474 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713018620] [2022-02-21 04:24:17,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,524 INFO L290 TraceCheckUtils]: 0: Hoare triple {4648#true} assume !false; {4648#true} is VALID [2022-02-21 04:24:17,525 INFO L290 TraceCheckUtils]: 1: Hoare triple {4648#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {4648#true} is VALID [2022-02-21 04:24:17,525 INFO L290 TraceCheckUtils]: 2: Hoare triple {4648#true} assume !false; {4648#true} is VALID [2022-02-21 04:24:17,525 INFO L290 TraceCheckUtils]: 3: Hoare triple {4648#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {4648#true} is VALID [2022-02-21 04:24:17,525 INFO L290 TraceCheckUtils]: 4: Hoare triple {4648#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {4648#true} is VALID [2022-02-21 04:24:17,525 INFO L290 TraceCheckUtils]: 5: Hoare triple {4648#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {4648#true} is VALID [2022-02-21 04:24:17,525 INFO L290 TraceCheckUtils]: 6: Hoare triple {4648#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {4648#true} is VALID [2022-02-21 04:24:17,526 INFO L290 TraceCheckUtils]: 7: Hoare triple {4648#true} assume !(0 != eval_~tmp~0#1); {4648#true} is VALID [2022-02-21 04:24:17,526 INFO L290 TraceCheckUtils]: 8: Hoare triple {4648#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {4648#true} is VALID [2022-02-21 04:24:17,526 INFO L290 TraceCheckUtils]: 9: Hoare triple {4648#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {4648#true} is VALID [2022-02-21 04:24:17,526 INFO L290 TraceCheckUtils]: 10: Hoare triple {4648#true} assume !(0 == ~M_E~0); {4648#true} is VALID [2022-02-21 04:24:17,526 INFO L290 TraceCheckUtils]: 11: Hoare triple {4648#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {4648#true} is VALID [2022-02-21 04:24:17,526 INFO L290 TraceCheckUtils]: 12: Hoare triple {4648#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {4648#true} is VALID [2022-02-21 04:24:17,526 INFO L290 TraceCheckUtils]: 13: Hoare triple {4648#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {4648#true} is VALID [2022-02-21 04:24:17,527 INFO L290 TraceCheckUtils]: 14: Hoare triple {4648#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,527 INFO L290 TraceCheckUtils]: 15: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,527 INFO L290 TraceCheckUtils]: 16: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,528 INFO L290 TraceCheckUtils]: 17: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,528 INFO L290 TraceCheckUtils]: 18: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,528 INFO L290 TraceCheckUtils]: 19: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,529 INFO L290 TraceCheckUtils]: 20: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,529 INFO L290 TraceCheckUtils]: 21: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,530 INFO L290 TraceCheckUtils]: 22: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,530 INFO L290 TraceCheckUtils]: 23: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,530 INFO L290 TraceCheckUtils]: 24: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,531 INFO L290 TraceCheckUtils]: 25: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,531 INFO L290 TraceCheckUtils]: 26: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,532 INFO L290 TraceCheckUtils]: 27: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,532 INFO L290 TraceCheckUtils]: 28: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~m_pc~0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,532 INFO L290 TraceCheckUtils]: 29: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,533 INFO L290 TraceCheckUtils]: 30: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,533 INFO L290 TraceCheckUtils]: 31: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,533 INFO L290 TraceCheckUtils]: 32: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,533 INFO L290 TraceCheckUtils]: 33: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,534 INFO L290 TraceCheckUtils]: 34: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t1_pc~0); {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,534 INFO L290 TraceCheckUtils]: 35: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,534 INFO L290 TraceCheckUtils]: 36: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,535 INFO L290 TraceCheckUtils]: 37: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,535 INFO L290 TraceCheckUtils]: 38: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,535 INFO L290 TraceCheckUtils]: 39: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,535 INFO L290 TraceCheckUtils]: 40: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t2_pc~0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,536 INFO L290 TraceCheckUtils]: 41: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,536 INFO L290 TraceCheckUtils]: 42: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,536 INFO L290 TraceCheckUtils]: 43: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,536 INFO L290 TraceCheckUtils]: 44: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,537 INFO L290 TraceCheckUtils]: 45: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,537 INFO L290 TraceCheckUtils]: 46: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t3_pc~0); {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,537 INFO L290 TraceCheckUtils]: 47: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,538 INFO L290 TraceCheckUtils]: 48: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,538 INFO L290 TraceCheckUtils]: 49: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,538 INFO L290 TraceCheckUtils]: 50: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,538 INFO L290 TraceCheckUtils]: 51: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,539 INFO L290 TraceCheckUtils]: 52: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t4_pc~0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,539 INFO L290 TraceCheckUtils]: 53: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,539 INFO L290 TraceCheckUtils]: 54: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,539 INFO L290 TraceCheckUtils]: 55: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,540 INFO L290 TraceCheckUtils]: 56: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,540 INFO L290 TraceCheckUtils]: 57: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,540 INFO L290 TraceCheckUtils]: 58: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t5_pc~0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,541 INFO L290 TraceCheckUtils]: 59: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,541 INFO L290 TraceCheckUtils]: 60: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,541 INFO L290 TraceCheckUtils]: 61: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,541 INFO L290 TraceCheckUtils]: 62: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,542 INFO L290 TraceCheckUtils]: 63: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,542 INFO L290 TraceCheckUtils]: 64: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t6_pc~0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,542 INFO L290 TraceCheckUtils]: 65: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,542 INFO L290 TraceCheckUtils]: 66: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,543 INFO L290 TraceCheckUtils]: 67: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,543 INFO L290 TraceCheckUtils]: 68: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,543 INFO L290 TraceCheckUtils]: 69: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,544 INFO L290 TraceCheckUtils]: 70: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t7_pc~0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,544 INFO L290 TraceCheckUtils]: 71: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,544 INFO L290 TraceCheckUtils]: 72: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,544 INFO L290 TraceCheckUtils]: 73: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,545 INFO L290 TraceCheckUtils]: 74: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,545 INFO L290 TraceCheckUtils]: 75: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,545 INFO L290 TraceCheckUtils]: 76: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t8_pc~0); {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,545 INFO L290 TraceCheckUtils]: 77: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,546 INFO L290 TraceCheckUtils]: 78: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,546 INFO L290 TraceCheckUtils]: 79: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,546 INFO L290 TraceCheckUtils]: 80: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,547 INFO L290 TraceCheckUtils]: 81: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,547 INFO L290 TraceCheckUtils]: 82: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,547 INFO L290 TraceCheckUtils]: 83: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,547 INFO L290 TraceCheckUtils]: 84: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,548 INFO L290 TraceCheckUtils]: 85: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {4650#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:17,549 INFO L290 TraceCheckUtils]: 86: Hoare triple {4650#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {4649#false} is VALID [2022-02-21 04:24:17,549 INFO L290 TraceCheckUtils]: 87: Hoare triple {4649#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {4649#false} is VALID [2022-02-21 04:24:17,549 INFO L290 TraceCheckUtils]: 88: Hoare triple {4649#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {4649#false} is VALID [2022-02-21 04:24:17,549 INFO L290 TraceCheckUtils]: 89: Hoare triple {4649#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {4649#false} is VALID [2022-02-21 04:24:17,549 INFO L290 TraceCheckUtils]: 90: Hoare triple {4649#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {4649#false} is VALID [2022-02-21 04:24:17,549 INFO L290 TraceCheckUtils]: 91: Hoare triple {4649#false} assume 1 == ~E_1~0;~E_1~0 := 2; {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 92: Hoare triple {4649#false} assume 1 == ~E_2~0;~E_2~0 := 2; {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 93: Hoare triple {4649#false} assume 1 == ~E_3~0;~E_3~0 := 2; {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 94: Hoare triple {4649#false} assume !(1 == ~E_4~0); {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 95: Hoare triple {4649#false} assume 1 == ~E_5~0;~E_5~0 := 2; {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 96: Hoare triple {4649#false} assume 1 == ~E_6~0;~E_6~0 := 2; {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 97: Hoare triple {4649#false} assume 1 == ~E_7~0;~E_7~0 := 2; {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 98: Hoare triple {4649#false} assume 1 == ~E_8~0;~E_8~0 := 2; {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 99: Hoare triple {4649#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 100: Hoare triple {4649#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 101: Hoare triple {4649#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 102: Hoare triple {4649#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 103: Hoare triple {4649#false} assume !(0 == start_simulation_~tmp~3#1); {4649#false} is VALID [2022-02-21 04:24:17,550 INFO L290 TraceCheckUtils]: 104: Hoare triple {4649#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {4649#false} is VALID [2022-02-21 04:24:17,551 INFO L290 TraceCheckUtils]: 105: Hoare triple {4649#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {4649#false} is VALID [2022-02-21 04:24:17,551 INFO L290 TraceCheckUtils]: 106: Hoare triple {4649#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {4649#false} is VALID [2022-02-21 04:24:17,551 INFO L290 TraceCheckUtils]: 107: Hoare triple {4649#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {4649#false} is VALID [2022-02-21 04:24:17,551 INFO L290 TraceCheckUtils]: 108: Hoare triple {4649#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {4649#false} is VALID [2022-02-21 04:24:17,551 INFO L290 TraceCheckUtils]: 109: Hoare triple {4649#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {4649#false} is VALID [2022-02-21 04:24:17,551 INFO L290 TraceCheckUtils]: 110: Hoare triple {4649#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {4649#false} is VALID [2022-02-21 04:24:17,551 INFO L290 TraceCheckUtils]: 111: Hoare triple {4649#false} assume !(0 != start_simulation_~tmp___0~1#1); {4649#false} is VALID [2022-02-21 04:24:17,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,552 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,552 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1713018620] [2022-02-21 04:24:17,552 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1713018620] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,552 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,552 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:17,552 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531775071] [2022-02-21 04:24:17,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,553 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:17,553 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:17,553 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:17,553 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:17,553 INFO L87 Difference]: Start difference. First operand 924 states and 1379 transitions. cyclomatic complexity: 456 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,182 INFO L93 Difference]: Finished difference Result 924 states and 1378 transitions. [2022-02-21 04:24:18,182 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:18,182 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,241 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:18,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1378 transitions. [2022-02-21 04:24:18,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:18,341 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1378 transitions. [2022-02-21 04:24:18,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-02-21 04:24:18,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-02-21 04:24:18,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1378 transitions. [2022-02-21 04:24:18,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:18,344 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1378 transitions. [2022-02-21 04:24:18,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1378 transitions. [2022-02-21 04:24:18,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-02-21 04:24:18,356 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:18,358 INFO L82 GeneralOperation]: Start isEquivalent. First operand 924 states and 1378 transitions. Second operand has 924 states, 924 states have (on average 1.4913419913419914) internal successors, (1378), 923 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,360 INFO L74 IsIncluded]: Start isIncluded. First operand 924 states and 1378 transitions. Second operand has 924 states, 924 states have (on average 1.4913419913419914) internal successors, (1378), 923 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,362 INFO L87 Difference]: Start difference. First operand 924 states and 1378 transitions. Second operand has 924 states, 924 states have (on average 1.4913419913419914) internal successors, (1378), 923 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,387 INFO L93 Difference]: Finished difference Result 924 states and 1378 transitions. [2022-02-21 04:24:18,387 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1378 transitions. [2022-02-21 04:24:18,388 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:18,388 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:18,390 INFO L74 IsIncluded]: Start isIncluded. First operand has 924 states, 924 states have (on average 1.4913419913419914) internal successors, (1378), 923 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1378 transitions. [2022-02-21 04:24:18,392 INFO L87 Difference]: Start difference. First operand has 924 states, 924 states have (on average 1.4913419913419914) internal successors, (1378), 923 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1378 transitions. [2022-02-21 04:24:18,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,427 INFO L93 Difference]: Finished difference Result 924 states and 1378 transitions. [2022-02-21 04:24:18,427 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1378 transitions. [2022-02-21 04:24:18,428 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:18,428 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:18,428 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:18,428 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:18,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4913419913419914) internal successors, (1378), 923 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1378 transitions. [2022-02-21 04:24:18,451 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1378 transitions. [2022-02-21 04:24:18,451 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1378 transitions. [2022-02-21 04:24:18,451 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:18,451 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1378 transitions. [2022-02-21 04:24:18,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:18,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:18,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:18,461 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:18,461 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:18,462 INFO L791 eck$LassoCheckResult]: Stem: 6251#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 6252#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6494#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5666#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5667#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 5938#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5939#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6436#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6426#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6006#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6007#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6231#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6232#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6088#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6089#L838 assume !(0 == ~M_E~0); 6238#L838-2 assume !(0 == ~T1_E~0); 5628#L843-1 assume !(0 == ~T2_E~0); 5629#L848-1 assume !(0 == ~T3_E~0); 5748#L853-1 assume !(0 == ~T4_E~0); 6074#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5575#L863-1 assume !(0 == ~T6_E~0); 5576#L868-1 assume !(0 == ~T7_E~0); 6468#L873-1 assume !(0 == ~T8_E~0); 6466#L878-1 assume !(0 == ~E_1~0); 6455#L883-1 assume !(0 == ~E_2~0); 6456#L888-1 assume !(0 == ~E_3~0); 6203#L893-1 assume !(0 == ~E_4~0); 6204#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6480#L903-1 assume !(0 == ~E_6~0); 6454#L908-1 assume !(0 == ~E_7~0); 6328#L913-1 assume !(0 == ~E_8~0); 5642#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5643#L402 assume !(1 == ~m_pc~0); 5851#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5769#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5770#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6012#L1035 assume !(0 != activate_threads_~tmp~1#1); 6013#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6065#L421 assume 1 == ~t1_pc~0; 6450#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6469#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6057#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6058#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 6116#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6477#L440 assume 1 == ~t2_pc~0; 5612#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5613#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5779#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6488#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 6342#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5966#L459 assume !(1 == ~t3_pc~0); 5967#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6449#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6273#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5763#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5764#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5773#L478 assume 1 == ~t4_pc~0; 5774#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6208#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6435#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5944#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5687#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5688#L497 assume !(1 == ~t5_pc~0); 5734#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5735#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6026#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6027#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 6442#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6443#L516 assume 1 == ~t6_pc~0; 6497#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6229#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6230#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5818#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5819#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6220#L535 assume !(1 == ~t7_pc~0); 6221#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6290#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6291#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6319#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 6309#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6310#L554 assume 1 == ~t8_pc~0; 6259#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5604#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6360#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5906#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5907#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5588#L931 assume !(1 == ~M_E~0); 5589#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6463#L936-1 assume !(1 == ~T2_E~0); 6486#L941-1 assume !(1 == ~T3_E~0); 6066#L946-1 assume !(1 == ~T4_E~0); 6067#L951-1 assume !(1 == ~T5_E~0); 5833#L956-1 assume !(1 == ~T6_E~0); 5834#L961-1 assume !(1 == ~T7_E~0); 6205#L966-1 assume !(1 == ~T8_E~0); 6206#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6312#L976-1 assume !(1 == ~E_2~0); 6282#L981-1 assume !(1 == ~E_3~0); 6071#L986-1 assume !(1 == ~E_4~0); 5863#L991-1 assume !(1 == ~E_5~0); 5864#L996-1 assume !(1 == ~E_6~0); 6473#L1001-1 assume !(1 == ~E_7~0); 6249#L1006-1 assume !(1 == ~E_8~0); 6250#L1011-1 assume { :end_inline_reset_delta_events } true; 5651#L1272-2 [2022-02-21 04:24:18,462 INFO L793 eck$LassoCheckResult]: Loop: 5651#L1272-2 assume !false; 5652#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5653#L813 assume !false; 5654#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6400#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5656#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6200#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6210#L696 assume !(0 != eval_~tmp~0#1); 6253#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6254#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6375#L838-3 assume !(0 == ~M_E~0); 6295#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6296#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6158#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6159#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6207#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6270#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6262#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6263#L873-3 assume !(0 == ~T8_E~0); 5886#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5615#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5616#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5617#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5618#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6092#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6401#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6105#L913-3 assume !(0 == ~E_8~0); 5658#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5659#L402-27 assume 1 == ~m_pc~0; 5605#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5606#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6095#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6096#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6414#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6415#L421-27 assume !(1 == ~t1_pc~0); 5878#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5879#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6128#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6129#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6474#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6223#L440-27 assume 1 == ~t2_pc~0; 6224#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6397#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5962#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5963#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6137#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5866#L459-27 assume !(1 == ~t3_pc~0); 5867#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 6285#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5930#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5931#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6219#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6467#L478-27 assume !(1 == ~t4_pc~0); 5856#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5857#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6233#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6365#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6366#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6402#L497-27 assume 1 == ~t5_pc~0; 6403#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5895#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5896#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5839#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5840#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6097#L516-27 assume 1 == ~t6_pc~0; 6098#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5952#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5953#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6100#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6240#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6029#L535-27 assume 1 == ~t7_pc~0; 6030#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6346#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6376#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6377#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5983#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5984#L554-27 assume !(1 == ~t8_pc~0); 5632#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 5633#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5778#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6117#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 5883#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5884#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5759#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5760#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5980#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6112#L946-3 assume !(1 == ~T4_E~0); 5901#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5902#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6181#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5990#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5991#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6228#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5649#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5650#L986-3 assume !(1 == ~E_4~0); 5640#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5641#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6300#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5971#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5972#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5682#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5684#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5998#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5999#L1291 assume !(0 == start_simulation_~tmp~3#1); 6178#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6084#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5579#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5580#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 6384#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6048#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6049#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6265#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 5651#L1272-2 [2022-02-21 04:24:18,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:18,464 INFO L85 PathProgramCache]: Analyzing trace with hash -1888349538, now seen corresponding path program 1 times [2022-02-21 04:24:18,464 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:18,464 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336952604] [2022-02-21 04:24:18,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:18,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:18,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:18,512 INFO L290 TraceCheckUtils]: 0: Hoare triple {8350#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {8350#true} is VALID [2022-02-21 04:24:18,512 INFO L290 TraceCheckUtils]: 1: Hoare triple {8350#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {8352#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:18,513 INFO L290 TraceCheckUtils]: 2: Hoare triple {8352#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {8352#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:18,513 INFO L290 TraceCheckUtils]: 3: Hoare triple {8352#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {8352#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:18,513 INFO L290 TraceCheckUtils]: 4: Hoare triple {8352#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {8352#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:18,513 INFO L290 TraceCheckUtils]: 5: Hoare triple {8352#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {8352#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:18,514 INFO L290 TraceCheckUtils]: 6: Hoare triple {8352#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {8352#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:18,514 INFO L290 TraceCheckUtils]: 7: Hoare triple {8352#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {8351#false} is VALID [2022-02-21 04:24:18,514 INFO L290 TraceCheckUtils]: 8: Hoare triple {8351#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {8351#false} is VALID [2022-02-21 04:24:18,514 INFO L290 TraceCheckUtils]: 9: Hoare triple {8351#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {8351#false} is VALID [2022-02-21 04:24:18,514 INFO L290 TraceCheckUtils]: 10: Hoare triple {8351#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {8351#false} is VALID [2022-02-21 04:24:18,515 INFO L290 TraceCheckUtils]: 11: Hoare triple {8351#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {8351#false} is VALID [2022-02-21 04:24:18,515 INFO L290 TraceCheckUtils]: 12: Hoare triple {8351#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {8351#false} is VALID [2022-02-21 04:24:18,515 INFO L290 TraceCheckUtils]: 13: Hoare triple {8351#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {8351#false} is VALID [2022-02-21 04:24:18,515 INFO L290 TraceCheckUtils]: 14: Hoare triple {8351#false} assume !(0 == ~M_E~0); {8351#false} is VALID [2022-02-21 04:24:18,515 INFO L290 TraceCheckUtils]: 15: Hoare triple {8351#false} assume !(0 == ~T1_E~0); {8351#false} is VALID [2022-02-21 04:24:18,515 INFO L290 TraceCheckUtils]: 16: Hoare triple {8351#false} assume !(0 == ~T2_E~0); {8351#false} is VALID [2022-02-21 04:24:18,515 INFO L290 TraceCheckUtils]: 17: Hoare triple {8351#false} assume !(0 == ~T3_E~0); {8351#false} is VALID [2022-02-21 04:24:18,515 INFO L290 TraceCheckUtils]: 18: Hoare triple {8351#false} assume !(0 == ~T4_E~0); {8351#false} is VALID [2022-02-21 04:24:18,516 INFO L290 TraceCheckUtils]: 19: Hoare triple {8351#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {8351#false} is VALID [2022-02-21 04:24:18,516 INFO L290 TraceCheckUtils]: 20: Hoare triple {8351#false} assume !(0 == ~T6_E~0); {8351#false} is VALID [2022-02-21 04:24:18,516 INFO L290 TraceCheckUtils]: 21: Hoare triple {8351#false} assume !(0 == ~T7_E~0); {8351#false} is VALID [2022-02-21 04:24:18,516 INFO L290 TraceCheckUtils]: 22: Hoare triple {8351#false} assume !(0 == ~T8_E~0); {8351#false} is VALID [2022-02-21 04:24:18,516 INFO L290 TraceCheckUtils]: 23: Hoare triple {8351#false} assume !(0 == ~E_1~0); {8351#false} is VALID [2022-02-21 04:24:18,516 INFO L290 TraceCheckUtils]: 24: Hoare triple {8351#false} assume !(0 == ~E_2~0); {8351#false} is VALID [2022-02-21 04:24:18,516 INFO L290 TraceCheckUtils]: 25: Hoare triple {8351#false} assume !(0 == ~E_3~0); {8351#false} is VALID [2022-02-21 04:24:18,516 INFO L290 TraceCheckUtils]: 26: Hoare triple {8351#false} assume !(0 == ~E_4~0); {8351#false} is VALID [2022-02-21 04:24:18,517 INFO L290 TraceCheckUtils]: 27: Hoare triple {8351#false} assume 0 == ~E_5~0;~E_5~0 := 1; {8351#false} is VALID [2022-02-21 04:24:18,517 INFO L290 TraceCheckUtils]: 28: Hoare triple {8351#false} assume !(0 == ~E_6~0); {8351#false} is VALID [2022-02-21 04:24:18,517 INFO L290 TraceCheckUtils]: 29: Hoare triple {8351#false} assume !(0 == ~E_7~0); {8351#false} is VALID [2022-02-21 04:24:18,517 INFO L290 TraceCheckUtils]: 30: Hoare triple {8351#false} assume !(0 == ~E_8~0); {8351#false} is VALID [2022-02-21 04:24:18,517 INFO L290 TraceCheckUtils]: 31: Hoare triple {8351#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8351#false} is VALID [2022-02-21 04:24:18,517 INFO L290 TraceCheckUtils]: 32: Hoare triple {8351#false} assume !(1 == ~m_pc~0); {8351#false} is VALID [2022-02-21 04:24:18,517 INFO L290 TraceCheckUtils]: 33: Hoare triple {8351#false} is_master_triggered_~__retres1~0#1 := 0; {8351#false} is VALID [2022-02-21 04:24:18,517 INFO L290 TraceCheckUtils]: 34: Hoare triple {8351#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8351#false} is VALID [2022-02-21 04:24:18,518 INFO L290 TraceCheckUtils]: 35: Hoare triple {8351#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8351#false} is VALID [2022-02-21 04:24:18,518 INFO L290 TraceCheckUtils]: 36: Hoare triple {8351#false} assume !(0 != activate_threads_~tmp~1#1); {8351#false} is VALID [2022-02-21 04:24:18,518 INFO L290 TraceCheckUtils]: 37: Hoare triple {8351#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8351#false} is VALID [2022-02-21 04:24:18,518 INFO L290 TraceCheckUtils]: 38: Hoare triple {8351#false} assume 1 == ~t1_pc~0; {8351#false} is VALID [2022-02-21 04:24:18,518 INFO L290 TraceCheckUtils]: 39: Hoare triple {8351#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {8351#false} is VALID [2022-02-21 04:24:18,518 INFO L290 TraceCheckUtils]: 40: Hoare triple {8351#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8351#false} is VALID [2022-02-21 04:24:18,518 INFO L290 TraceCheckUtils]: 41: Hoare triple {8351#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8351#false} is VALID [2022-02-21 04:24:18,518 INFO L290 TraceCheckUtils]: 42: Hoare triple {8351#false} assume !(0 != activate_threads_~tmp___0~0#1); {8351#false} is VALID [2022-02-21 04:24:18,519 INFO L290 TraceCheckUtils]: 43: Hoare triple {8351#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8351#false} is VALID [2022-02-21 04:24:18,519 INFO L290 TraceCheckUtils]: 44: Hoare triple {8351#false} assume 1 == ~t2_pc~0; {8351#false} is VALID [2022-02-21 04:24:18,519 INFO L290 TraceCheckUtils]: 45: Hoare triple {8351#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8351#false} is VALID [2022-02-21 04:24:18,519 INFO L290 TraceCheckUtils]: 46: Hoare triple {8351#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8351#false} is VALID [2022-02-21 04:24:18,519 INFO L290 TraceCheckUtils]: 47: Hoare triple {8351#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {8351#false} is VALID [2022-02-21 04:24:18,519 INFO L290 TraceCheckUtils]: 48: Hoare triple {8351#false} assume !(0 != activate_threads_~tmp___1~0#1); {8351#false} is VALID [2022-02-21 04:24:18,519 INFO L290 TraceCheckUtils]: 49: Hoare triple {8351#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8351#false} is VALID [2022-02-21 04:24:18,519 INFO L290 TraceCheckUtils]: 50: Hoare triple {8351#false} assume !(1 == ~t3_pc~0); {8351#false} is VALID [2022-02-21 04:24:18,519 INFO L290 TraceCheckUtils]: 51: Hoare triple {8351#false} is_transmit3_triggered_~__retres1~3#1 := 0; {8351#false} is VALID [2022-02-21 04:24:18,520 INFO L290 TraceCheckUtils]: 52: Hoare triple {8351#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8351#false} is VALID [2022-02-21 04:24:18,520 INFO L290 TraceCheckUtils]: 53: Hoare triple {8351#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {8351#false} is VALID [2022-02-21 04:24:18,520 INFO L290 TraceCheckUtils]: 54: Hoare triple {8351#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {8351#false} is VALID [2022-02-21 04:24:18,520 INFO L290 TraceCheckUtils]: 55: Hoare triple {8351#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8351#false} is VALID [2022-02-21 04:24:18,520 INFO L290 TraceCheckUtils]: 56: Hoare triple {8351#false} assume 1 == ~t4_pc~0; {8351#false} is VALID [2022-02-21 04:24:18,520 INFO L290 TraceCheckUtils]: 57: Hoare triple {8351#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8351#false} is VALID [2022-02-21 04:24:18,520 INFO L290 TraceCheckUtils]: 58: Hoare triple {8351#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8351#false} is VALID [2022-02-21 04:24:18,520 INFO L290 TraceCheckUtils]: 59: Hoare triple {8351#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {8351#false} is VALID [2022-02-21 04:24:18,521 INFO L290 TraceCheckUtils]: 60: Hoare triple {8351#false} assume !(0 != activate_threads_~tmp___3~0#1); {8351#false} is VALID [2022-02-21 04:24:18,521 INFO L290 TraceCheckUtils]: 61: Hoare triple {8351#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8351#false} is VALID [2022-02-21 04:24:18,521 INFO L290 TraceCheckUtils]: 62: Hoare triple {8351#false} assume !(1 == ~t5_pc~0); {8351#false} is VALID [2022-02-21 04:24:18,521 INFO L290 TraceCheckUtils]: 63: Hoare triple {8351#false} is_transmit5_triggered_~__retres1~5#1 := 0; {8351#false} is VALID [2022-02-21 04:24:18,521 INFO L290 TraceCheckUtils]: 64: Hoare triple {8351#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8351#false} is VALID [2022-02-21 04:24:18,521 INFO L290 TraceCheckUtils]: 65: Hoare triple {8351#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {8351#false} is VALID [2022-02-21 04:24:18,521 INFO L290 TraceCheckUtils]: 66: Hoare triple {8351#false} assume !(0 != activate_threads_~tmp___4~0#1); {8351#false} is VALID [2022-02-21 04:24:18,521 INFO L290 TraceCheckUtils]: 67: Hoare triple {8351#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8351#false} is VALID [2022-02-21 04:24:18,522 INFO L290 TraceCheckUtils]: 68: Hoare triple {8351#false} assume 1 == ~t6_pc~0; {8351#false} is VALID [2022-02-21 04:24:18,522 INFO L290 TraceCheckUtils]: 69: Hoare triple {8351#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {8351#false} is VALID [2022-02-21 04:24:18,522 INFO L290 TraceCheckUtils]: 70: Hoare triple {8351#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8351#false} is VALID [2022-02-21 04:24:18,522 INFO L290 TraceCheckUtils]: 71: Hoare triple {8351#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8351#false} is VALID [2022-02-21 04:24:18,522 INFO L290 TraceCheckUtils]: 72: Hoare triple {8351#false} assume !(0 != activate_threads_~tmp___5~0#1); {8351#false} is VALID [2022-02-21 04:24:18,522 INFO L290 TraceCheckUtils]: 73: Hoare triple {8351#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {8351#false} is VALID [2022-02-21 04:24:18,523 INFO L290 TraceCheckUtils]: 74: Hoare triple {8351#false} assume !(1 == ~t7_pc~0); {8351#false} is VALID [2022-02-21 04:24:18,525 INFO L290 TraceCheckUtils]: 75: Hoare triple {8351#false} is_transmit7_triggered_~__retres1~7#1 := 0; {8351#false} is VALID [2022-02-21 04:24:18,526 INFO L290 TraceCheckUtils]: 76: Hoare triple {8351#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {8351#false} is VALID [2022-02-21 04:24:18,526 INFO L290 TraceCheckUtils]: 77: Hoare triple {8351#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {8351#false} is VALID [2022-02-21 04:24:18,526 INFO L290 TraceCheckUtils]: 78: Hoare triple {8351#false} assume !(0 != activate_threads_~tmp___6~0#1); {8351#false} is VALID [2022-02-21 04:24:18,526 INFO L290 TraceCheckUtils]: 79: Hoare triple {8351#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {8351#false} is VALID [2022-02-21 04:24:18,526 INFO L290 TraceCheckUtils]: 80: Hoare triple {8351#false} assume 1 == ~t8_pc~0; {8351#false} is VALID [2022-02-21 04:24:18,527 INFO L290 TraceCheckUtils]: 81: Hoare triple {8351#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {8351#false} is VALID [2022-02-21 04:24:18,527 INFO L290 TraceCheckUtils]: 82: Hoare triple {8351#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {8351#false} is VALID [2022-02-21 04:24:18,527 INFO L290 TraceCheckUtils]: 83: Hoare triple {8351#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {8351#false} is VALID [2022-02-21 04:24:18,530 INFO L290 TraceCheckUtils]: 84: Hoare triple {8351#false} assume !(0 != activate_threads_~tmp___7~0#1); {8351#false} is VALID [2022-02-21 04:24:18,531 INFO L290 TraceCheckUtils]: 85: Hoare triple {8351#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8351#false} is VALID [2022-02-21 04:24:18,531 INFO L290 TraceCheckUtils]: 86: Hoare triple {8351#false} assume !(1 == ~M_E~0); {8351#false} is VALID [2022-02-21 04:24:18,531 INFO L290 TraceCheckUtils]: 87: Hoare triple {8351#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {8351#false} is VALID [2022-02-21 04:24:18,531 INFO L290 TraceCheckUtils]: 88: Hoare triple {8351#false} assume !(1 == ~T2_E~0); {8351#false} is VALID [2022-02-21 04:24:18,531 INFO L290 TraceCheckUtils]: 89: Hoare triple {8351#false} assume !(1 == ~T3_E~0); {8351#false} is VALID [2022-02-21 04:24:18,531 INFO L290 TraceCheckUtils]: 90: Hoare triple {8351#false} assume !(1 == ~T4_E~0); {8351#false} is VALID [2022-02-21 04:24:18,532 INFO L290 TraceCheckUtils]: 91: Hoare triple {8351#false} assume !(1 == ~T5_E~0); {8351#false} is VALID [2022-02-21 04:24:18,532 INFO L290 TraceCheckUtils]: 92: Hoare triple {8351#false} assume !(1 == ~T6_E~0); {8351#false} is VALID [2022-02-21 04:24:18,532 INFO L290 TraceCheckUtils]: 93: Hoare triple {8351#false} assume !(1 == ~T7_E~0); {8351#false} is VALID [2022-02-21 04:24:18,532 INFO L290 TraceCheckUtils]: 94: Hoare triple {8351#false} assume !(1 == ~T8_E~0); {8351#false} is VALID [2022-02-21 04:24:18,532 INFO L290 TraceCheckUtils]: 95: Hoare triple {8351#false} assume 1 == ~E_1~0;~E_1~0 := 2; {8351#false} is VALID [2022-02-21 04:24:18,532 INFO L290 TraceCheckUtils]: 96: Hoare triple {8351#false} assume !(1 == ~E_2~0); {8351#false} is VALID [2022-02-21 04:24:18,532 INFO L290 TraceCheckUtils]: 97: Hoare triple {8351#false} assume !(1 == ~E_3~0); {8351#false} is VALID [2022-02-21 04:24:18,532 INFO L290 TraceCheckUtils]: 98: Hoare triple {8351#false} assume !(1 == ~E_4~0); {8351#false} is VALID [2022-02-21 04:24:18,532 INFO L290 TraceCheckUtils]: 99: Hoare triple {8351#false} assume !(1 == ~E_5~0); {8351#false} is VALID [2022-02-21 04:24:18,533 INFO L290 TraceCheckUtils]: 100: Hoare triple {8351#false} assume !(1 == ~E_6~0); {8351#false} is VALID [2022-02-21 04:24:18,533 INFO L290 TraceCheckUtils]: 101: Hoare triple {8351#false} assume !(1 == ~E_7~0); {8351#false} is VALID [2022-02-21 04:24:18,533 INFO L290 TraceCheckUtils]: 102: Hoare triple {8351#false} assume !(1 == ~E_8~0); {8351#false} is VALID [2022-02-21 04:24:18,533 INFO L290 TraceCheckUtils]: 103: Hoare triple {8351#false} assume { :end_inline_reset_delta_events } true; {8351#false} is VALID [2022-02-21 04:24:18,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:18,534 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:18,534 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336952604] [2022-02-21 04:24:18,534 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [336952604] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:18,534 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:18,534 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:18,534 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935342058] [2022-02-21 04:24:18,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:18,535 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:18,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:18,535 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 1 times [2022-02-21 04:24:18,535 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:18,536 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614765958] [2022-02-21 04:24:18,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:18,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:18,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:18,585 INFO L290 TraceCheckUtils]: 0: Hoare triple {8353#true} assume !false; {8353#true} is VALID [2022-02-21 04:24:18,585 INFO L290 TraceCheckUtils]: 1: Hoare triple {8353#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {8353#true} is VALID [2022-02-21 04:24:18,585 INFO L290 TraceCheckUtils]: 2: Hoare triple {8353#true} assume !false; {8353#true} is VALID [2022-02-21 04:24:18,586 INFO L290 TraceCheckUtils]: 3: Hoare triple {8353#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {8353#true} is VALID [2022-02-21 04:24:18,586 INFO L290 TraceCheckUtils]: 4: Hoare triple {8353#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {8353#true} is VALID [2022-02-21 04:24:18,586 INFO L290 TraceCheckUtils]: 5: Hoare triple {8353#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {8353#true} is VALID [2022-02-21 04:24:18,586 INFO L290 TraceCheckUtils]: 6: Hoare triple {8353#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {8353#true} is VALID [2022-02-21 04:24:18,586 INFO L290 TraceCheckUtils]: 7: Hoare triple {8353#true} assume !(0 != eval_~tmp~0#1); {8353#true} is VALID [2022-02-21 04:24:18,586 INFO L290 TraceCheckUtils]: 8: Hoare triple {8353#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {8353#true} is VALID [2022-02-21 04:24:18,586 INFO L290 TraceCheckUtils]: 9: Hoare triple {8353#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {8353#true} is VALID [2022-02-21 04:24:18,586 INFO L290 TraceCheckUtils]: 10: Hoare triple {8353#true} assume !(0 == ~M_E~0); {8353#true} is VALID [2022-02-21 04:24:18,586 INFO L290 TraceCheckUtils]: 11: Hoare triple {8353#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {8353#true} is VALID [2022-02-21 04:24:18,587 INFO L290 TraceCheckUtils]: 12: Hoare triple {8353#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {8353#true} is VALID [2022-02-21 04:24:18,587 INFO L290 TraceCheckUtils]: 13: Hoare triple {8353#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {8353#true} is VALID [2022-02-21 04:24:18,587 INFO L290 TraceCheckUtils]: 14: Hoare triple {8353#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,587 INFO L290 TraceCheckUtils]: 15: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,588 INFO L290 TraceCheckUtils]: 16: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,588 INFO L290 TraceCheckUtils]: 17: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,588 INFO L290 TraceCheckUtils]: 18: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,588 INFO L290 TraceCheckUtils]: 19: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,589 INFO L290 TraceCheckUtils]: 20: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,589 INFO L290 TraceCheckUtils]: 21: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,589 INFO L290 TraceCheckUtils]: 22: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,589 INFO L290 TraceCheckUtils]: 23: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,590 INFO L290 TraceCheckUtils]: 24: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,590 INFO L290 TraceCheckUtils]: 25: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,590 INFO L290 TraceCheckUtils]: 26: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,590 INFO L290 TraceCheckUtils]: 27: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,591 INFO L290 TraceCheckUtils]: 28: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~m_pc~0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,591 INFO L290 TraceCheckUtils]: 29: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,591 INFO L290 TraceCheckUtils]: 30: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,591 INFO L290 TraceCheckUtils]: 31: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,592 INFO L290 TraceCheckUtils]: 32: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,592 INFO L290 TraceCheckUtils]: 33: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,592 INFO L290 TraceCheckUtils]: 34: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t1_pc~0); {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,592 INFO L290 TraceCheckUtils]: 35: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,593 INFO L290 TraceCheckUtils]: 36: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,593 INFO L290 TraceCheckUtils]: 37: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,593 INFO L290 TraceCheckUtils]: 38: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,593 INFO L290 TraceCheckUtils]: 39: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,594 INFO L290 TraceCheckUtils]: 40: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t2_pc~0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,594 INFO L290 TraceCheckUtils]: 41: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,594 INFO L290 TraceCheckUtils]: 42: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,595 INFO L290 TraceCheckUtils]: 43: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,595 INFO L290 TraceCheckUtils]: 44: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,595 INFO L290 TraceCheckUtils]: 45: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,595 INFO L290 TraceCheckUtils]: 46: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t3_pc~0); {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,596 INFO L290 TraceCheckUtils]: 47: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,596 INFO L290 TraceCheckUtils]: 48: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,596 INFO L290 TraceCheckUtils]: 49: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,596 INFO L290 TraceCheckUtils]: 50: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,597 INFO L290 TraceCheckUtils]: 51: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,597 INFO L290 TraceCheckUtils]: 52: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t4_pc~0); {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,597 INFO L290 TraceCheckUtils]: 53: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,597 INFO L290 TraceCheckUtils]: 54: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,598 INFO L290 TraceCheckUtils]: 55: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,598 INFO L290 TraceCheckUtils]: 56: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,598 INFO L290 TraceCheckUtils]: 57: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,598 INFO L290 TraceCheckUtils]: 58: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t5_pc~0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,599 INFO L290 TraceCheckUtils]: 59: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,599 INFO L290 TraceCheckUtils]: 60: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,599 INFO L290 TraceCheckUtils]: 61: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,599 INFO L290 TraceCheckUtils]: 62: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,600 INFO L290 TraceCheckUtils]: 63: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,600 INFO L290 TraceCheckUtils]: 64: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t6_pc~0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,600 INFO L290 TraceCheckUtils]: 65: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,600 INFO L290 TraceCheckUtils]: 66: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,601 INFO L290 TraceCheckUtils]: 67: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,601 INFO L290 TraceCheckUtils]: 68: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,601 INFO L290 TraceCheckUtils]: 69: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,601 INFO L290 TraceCheckUtils]: 70: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t7_pc~0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,602 INFO L290 TraceCheckUtils]: 71: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,602 INFO L290 TraceCheckUtils]: 72: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,602 INFO L290 TraceCheckUtils]: 73: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,602 INFO L290 TraceCheckUtils]: 74: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,603 INFO L290 TraceCheckUtils]: 75: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,603 INFO L290 TraceCheckUtils]: 76: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t8_pc~0); {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,603 INFO L290 TraceCheckUtils]: 77: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,604 INFO L290 TraceCheckUtils]: 78: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,604 INFO L290 TraceCheckUtils]: 79: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,604 INFO L290 TraceCheckUtils]: 80: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,604 INFO L290 TraceCheckUtils]: 81: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,605 INFO L290 TraceCheckUtils]: 82: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,605 INFO L290 TraceCheckUtils]: 83: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,605 INFO L290 TraceCheckUtils]: 84: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,605 INFO L290 TraceCheckUtils]: 85: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8355#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:18,606 INFO L290 TraceCheckUtils]: 86: Hoare triple {8355#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {8354#false} is VALID [2022-02-21 04:24:18,606 INFO L290 TraceCheckUtils]: 87: Hoare triple {8354#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {8354#false} is VALID [2022-02-21 04:24:18,606 INFO L290 TraceCheckUtils]: 88: Hoare triple {8354#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {8354#false} is VALID [2022-02-21 04:24:18,606 INFO L290 TraceCheckUtils]: 89: Hoare triple {8354#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {8354#false} is VALID [2022-02-21 04:24:18,606 INFO L290 TraceCheckUtils]: 90: Hoare triple {8354#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {8354#false} is VALID [2022-02-21 04:24:18,606 INFO L290 TraceCheckUtils]: 91: Hoare triple {8354#false} assume 1 == ~E_1~0;~E_1~0 := 2; {8354#false} is VALID [2022-02-21 04:24:18,606 INFO L290 TraceCheckUtils]: 92: Hoare triple {8354#false} assume 1 == ~E_2~0;~E_2~0 := 2; {8354#false} is VALID [2022-02-21 04:24:18,606 INFO L290 TraceCheckUtils]: 93: Hoare triple {8354#false} assume 1 == ~E_3~0;~E_3~0 := 2; {8354#false} is VALID [2022-02-21 04:24:18,607 INFO L290 TraceCheckUtils]: 94: Hoare triple {8354#false} assume !(1 == ~E_4~0); {8354#false} is VALID [2022-02-21 04:24:18,607 INFO L290 TraceCheckUtils]: 95: Hoare triple {8354#false} assume 1 == ~E_5~0;~E_5~0 := 2; {8354#false} is VALID [2022-02-21 04:24:18,607 INFO L290 TraceCheckUtils]: 96: Hoare triple {8354#false} assume 1 == ~E_6~0;~E_6~0 := 2; {8354#false} is VALID [2022-02-21 04:24:18,607 INFO L290 TraceCheckUtils]: 97: Hoare triple {8354#false} assume 1 == ~E_7~0;~E_7~0 := 2; {8354#false} is VALID [2022-02-21 04:24:18,607 INFO L290 TraceCheckUtils]: 98: Hoare triple {8354#false} assume 1 == ~E_8~0;~E_8~0 := 2; {8354#false} is VALID [2022-02-21 04:24:18,607 INFO L290 TraceCheckUtils]: 99: Hoare triple {8354#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {8354#false} is VALID [2022-02-21 04:24:18,607 INFO L290 TraceCheckUtils]: 100: Hoare triple {8354#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {8354#false} is VALID [2022-02-21 04:24:18,607 INFO L290 TraceCheckUtils]: 101: Hoare triple {8354#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {8354#false} is VALID [2022-02-21 04:24:18,607 INFO L290 TraceCheckUtils]: 102: Hoare triple {8354#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {8354#false} is VALID [2022-02-21 04:24:18,608 INFO L290 TraceCheckUtils]: 103: Hoare triple {8354#false} assume !(0 == start_simulation_~tmp~3#1); {8354#false} is VALID [2022-02-21 04:24:18,608 INFO L290 TraceCheckUtils]: 104: Hoare triple {8354#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {8354#false} is VALID [2022-02-21 04:24:18,608 INFO L290 TraceCheckUtils]: 105: Hoare triple {8354#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {8354#false} is VALID [2022-02-21 04:24:18,608 INFO L290 TraceCheckUtils]: 106: Hoare triple {8354#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {8354#false} is VALID [2022-02-21 04:24:18,608 INFO L290 TraceCheckUtils]: 107: Hoare triple {8354#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {8354#false} is VALID [2022-02-21 04:24:18,608 INFO L290 TraceCheckUtils]: 108: Hoare triple {8354#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {8354#false} is VALID [2022-02-21 04:24:18,608 INFO L290 TraceCheckUtils]: 109: Hoare triple {8354#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {8354#false} is VALID [2022-02-21 04:24:18,608 INFO L290 TraceCheckUtils]: 110: Hoare triple {8354#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {8354#false} is VALID [2022-02-21 04:24:18,608 INFO L290 TraceCheckUtils]: 111: Hoare triple {8354#false} assume !(0 != start_simulation_~tmp___0~1#1); {8354#false} is VALID [2022-02-21 04:24:18,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:18,609 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:18,609 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614765958] [2022-02-21 04:24:18,609 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [614765958] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:18,609 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:18,609 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:18,610 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39670314] [2022-02-21 04:24:18,610 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:18,610 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:18,610 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:18,610 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:18,611 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:18,611 INFO L87 Difference]: Start difference. First operand 924 states and 1378 transitions. cyclomatic complexity: 455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:19,253 INFO L93 Difference]: Finished difference Result 924 states and 1377 transitions. [2022-02-21 04:24:19,253 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:19,253 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,323 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:19,324 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1377 transitions. [2022-02-21 04:24:19,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:19,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1377 transitions. [2022-02-21 04:24:19,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-02-21 04:24:19,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-02-21 04:24:19,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1377 transitions. [2022-02-21 04:24:19,374 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:19,374 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1377 transitions. [2022-02-21 04:24:19,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1377 transitions. [2022-02-21 04:24:19,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-02-21 04:24:19,383 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:19,385 INFO L82 GeneralOperation]: Start isEquivalent. First operand 924 states and 1377 transitions. Second operand has 924 states, 924 states have (on average 1.4902597402597402) internal successors, (1377), 923 states have internal predecessors, (1377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,386 INFO L74 IsIncluded]: Start isIncluded. First operand 924 states and 1377 transitions. Second operand has 924 states, 924 states have (on average 1.4902597402597402) internal successors, (1377), 923 states have internal predecessors, (1377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,388 INFO L87 Difference]: Start difference. First operand 924 states and 1377 transitions. Second operand has 924 states, 924 states have (on average 1.4902597402597402) internal successors, (1377), 923 states have internal predecessors, (1377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:19,410 INFO L93 Difference]: Finished difference Result 924 states and 1377 transitions. [2022-02-21 04:24:19,410 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1377 transitions. [2022-02-21 04:24:19,412 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:19,412 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:19,413 INFO L74 IsIncluded]: Start isIncluded. First operand has 924 states, 924 states have (on average 1.4902597402597402) internal successors, (1377), 923 states have internal predecessors, (1377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1377 transitions. [2022-02-21 04:24:19,415 INFO L87 Difference]: Start difference. First operand has 924 states, 924 states have (on average 1.4902597402597402) internal successors, (1377), 923 states have internal predecessors, (1377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1377 transitions. [2022-02-21 04:24:19,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:19,438 INFO L93 Difference]: Finished difference Result 924 states and 1377 transitions. [2022-02-21 04:24:19,438 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1377 transitions. [2022-02-21 04:24:19,439 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:19,440 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:19,440 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:19,440 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:19,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4902597402597402) internal successors, (1377), 923 states have internal predecessors, (1377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1377 transitions. [2022-02-21 04:24:19,464 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1377 transitions. [2022-02-21 04:24:19,464 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1377 transitions. [2022-02-21 04:24:19,464 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:19,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1377 transitions. [2022-02-21 04:24:19,467 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:19,467 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:19,468 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:19,469 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:19,469 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:19,469 INFO L791 eck$LassoCheckResult]: Stem: 9956#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9957#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10199#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9371#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9372#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 9643#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9644#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10141#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10131#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9711#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9712#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9936#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9937#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9793#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9794#L838 assume !(0 == ~M_E~0); 9943#L838-2 assume !(0 == ~T1_E~0); 9333#L843-1 assume !(0 == ~T2_E~0); 9334#L848-1 assume !(0 == ~T3_E~0); 9453#L853-1 assume !(0 == ~T4_E~0); 9779#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9280#L863-1 assume !(0 == ~T6_E~0); 9281#L868-1 assume !(0 == ~T7_E~0); 10173#L873-1 assume !(0 == ~T8_E~0); 10171#L878-1 assume !(0 == ~E_1~0); 10160#L883-1 assume !(0 == ~E_2~0); 10161#L888-1 assume !(0 == ~E_3~0); 9908#L893-1 assume !(0 == ~E_4~0); 9909#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10185#L903-1 assume !(0 == ~E_6~0); 10159#L908-1 assume !(0 == ~E_7~0); 10033#L913-1 assume !(0 == ~E_8~0); 9347#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9348#L402 assume !(1 == ~m_pc~0); 9556#L402-2 is_master_triggered_~__retres1~0#1 := 0; 9474#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9475#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9717#L1035 assume !(0 != activate_threads_~tmp~1#1); 9718#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9770#L421 assume 1 == ~t1_pc~0; 10155#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10174#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9762#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9763#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 9821#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10182#L440 assume 1 == ~t2_pc~0; 9317#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9318#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9484#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10193#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 10047#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9671#L459 assume !(1 == ~t3_pc~0); 9672#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10154#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9978#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9468#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9469#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9478#L478 assume 1 == ~t4_pc~0; 9479#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9913#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10140#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9649#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 9392#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9393#L497 assume !(1 == ~t5_pc~0); 9439#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9440#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9731#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9732#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 10147#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10148#L516 assume 1 == ~t6_pc~0; 10202#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9934#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9935#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9523#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 9524#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9925#L535 assume !(1 == ~t7_pc~0); 9926#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9995#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9996#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10024#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 10014#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10015#L554 assume 1 == ~t8_pc~0; 9964#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9309#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10065#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9611#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 9612#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9293#L931 assume !(1 == ~M_E~0); 9294#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10168#L936-1 assume !(1 == ~T2_E~0); 10191#L941-1 assume !(1 == ~T3_E~0); 9771#L946-1 assume !(1 == ~T4_E~0); 9772#L951-1 assume !(1 == ~T5_E~0); 9538#L956-1 assume !(1 == ~T6_E~0); 9539#L961-1 assume !(1 == ~T7_E~0); 9910#L966-1 assume !(1 == ~T8_E~0); 9911#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10017#L976-1 assume !(1 == ~E_2~0); 9987#L981-1 assume !(1 == ~E_3~0); 9776#L986-1 assume !(1 == ~E_4~0); 9568#L991-1 assume !(1 == ~E_5~0); 9569#L996-1 assume !(1 == ~E_6~0); 10178#L1001-1 assume !(1 == ~E_7~0); 9954#L1006-1 assume !(1 == ~E_8~0); 9955#L1011-1 assume { :end_inline_reset_delta_events } true; 9356#L1272-2 [2022-02-21 04:24:19,470 INFO L793 eck$LassoCheckResult]: Loop: 9356#L1272-2 assume !false; 9357#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9358#L813 assume !false; 9359#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10105#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9361#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9905#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9915#L696 assume !(0 != eval_~tmp~0#1); 9958#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9959#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10080#L838-3 assume !(0 == ~M_E~0); 10000#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10001#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9863#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9864#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9912#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9975#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9967#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9968#L873-3 assume !(0 == ~T8_E~0); 9591#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9320#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9321#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9322#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9323#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9797#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10106#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9810#L913-3 assume !(0 == ~E_8~0); 9363#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9364#L402-27 assume !(1 == ~m_pc~0); 9312#L402-29 is_master_triggered_~__retres1~0#1 := 0; 9311#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9800#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9801#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10119#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10120#L421-27 assume !(1 == ~t1_pc~0); 9583#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 9584#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9833#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9834#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10179#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9928#L440-27 assume 1 == ~t2_pc~0; 9929#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10102#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9667#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9668#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9842#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9571#L459-27 assume !(1 == ~t3_pc~0); 9572#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 9990#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9635#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9636#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9924#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10172#L478-27 assume 1 == ~t4_pc~0; 10194#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9562#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9938#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10070#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10071#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10107#L497-27 assume 1 == ~t5_pc~0; 10108#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9600#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9601#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9544#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9545#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9802#L516-27 assume 1 == ~t6_pc~0; 9803#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9657#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9658#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9805#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9945#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9734#L535-27 assume 1 == ~t7_pc~0; 9735#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10051#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10081#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10082#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9688#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9689#L554-27 assume !(1 == ~t8_pc~0); 9337#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 9338#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9483#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9822#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 9588#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9589#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9464#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9465#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9685#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9817#L946-3 assume !(1 == ~T4_E~0); 9606#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9607#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9886#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9695#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9696#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9933#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9354#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9355#L986-3 assume !(1 == ~E_4~0); 9345#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9346#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10005#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9676#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9677#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9387#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9389#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9703#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 9704#L1291 assume !(0 == start_simulation_~tmp~3#1); 9883#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9789#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9284#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9285#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 10089#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9753#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9754#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 9970#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 9356#L1272-2 [2022-02-21 04:24:19,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:19,470 INFO L85 PathProgramCache]: Analyzing trace with hash 805546652, now seen corresponding path program 1 times [2022-02-21 04:24:19,470 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:19,471 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1645311305] [2022-02-21 04:24:19,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:19,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:19,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:19,491 INFO L290 TraceCheckUtils]: 0: Hoare triple {12055#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {12055#true} is VALID [2022-02-21 04:24:19,492 INFO L290 TraceCheckUtils]: 1: Hoare triple {12055#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {12057#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:19,492 INFO L290 TraceCheckUtils]: 2: Hoare triple {12057#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {12057#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:19,493 INFO L290 TraceCheckUtils]: 3: Hoare triple {12057#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {12057#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:19,493 INFO L290 TraceCheckUtils]: 4: Hoare triple {12057#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {12057#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:19,493 INFO L290 TraceCheckUtils]: 5: Hoare triple {12057#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {12057#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:19,494 INFO L290 TraceCheckUtils]: 6: Hoare triple {12057#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {12057#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:19,494 INFO L290 TraceCheckUtils]: 7: Hoare triple {12057#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {12057#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:19,494 INFO L290 TraceCheckUtils]: 8: Hoare triple {12057#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {12056#false} is VALID [2022-02-21 04:24:19,494 INFO L290 TraceCheckUtils]: 9: Hoare triple {12056#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {12056#false} is VALID [2022-02-21 04:24:19,494 INFO L290 TraceCheckUtils]: 10: Hoare triple {12056#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {12056#false} is VALID [2022-02-21 04:24:19,495 INFO L290 TraceCheckUtils]: 11: Hoare triple {12056#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {12056#false} is VALID [2022-02-21 04:24:19,495 INFO L290 TraceCheckUtils]: 12: Hoare triple {12056#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {12056#false} is VALID [2022-02-21 04:24:19,495 INFO L290 TraceCheckUtils]: 13: Hoare triple {12056#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {12056#false} is VALID [2022-02-21 04:24:19,495 INFO L290 TraceCheckUtils]: 14: Hoare triple {12056#false} assume !(0 == ~M_E~0); {12056#false} is VALID [2022-02-21 04:24:19,495 INFO L290 TraceCheckUtils]: 15: Hoare triple {12056#false} assume !(0 == ~T1_E~0); {12056#false} is VALID [2022-02-21 04:24:19,495 INFO L290 TraceCheckUtils]: 16: Hoare triple {12056#false} assume !(0 == ~T2_E~0); {12056#false} is VALID [2022-02-21 04:24:19,495 INFO L290 TraceCheckUtils]: 17: Hoare triple {12056#false} assume !(0 == ~T3_E~0); {12056#false} is VALID [2022-02-21 04:24:19,495 INFO L290 TraceCheckUtils]: 18: Hoare triple {12056#false} assume !(0 == ~T4_E~0); {12056#false} is VALID [2022-02-21 04:24:19,496 INFO L290 TraceCheckUtils]: 19: Hoare triple {12056#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {12056#false} is VALID [2022-02-21 04:24:19,496 INFO L290 TraceCheckUtils]: 20: Hoare triple {12056#false} assume !(0 == ~T6_E~0); {12056#false} is VALID [2022-02-21 04:24:19,496 INFO L290 TraceCheckUtils]: 21: Hoare triple {12056#false} assume !(0 == ~T7_E~0); {12056#false} is VALID [2022-02-21 04:24:19,496 INFO L290 TraceCheckUtils]: 22: Hoare triple {12056#false} assume !(0 == ~T8_E~0); {12056#false} is VALID [2022-02-21 04:24:19,496 INFO L290 TraceCheckUtils]: 23: Hoare triple {12056#false} assume !(0 == ~E_1~0); {12056#false} is VALID [2022-02-21 04:24:19,496 INFO L290 TraceCheckUtils]: 24: Hoare triple {12056#false} assume !(0 == ~E_2~0); {12056#false} is VALID [2022-02-21 04:24:19,496 INFO L290 TraceCheckUtils]: 25: Hoare triple {12056#false} assume !(0 == ~E_3~0); {12056#false} is VALID [2022-02-21 04:24:19,496 INFO L290 TraceCheckUtils]: 26: Hoare triple {12056#false} assume !(0 == ~E_4~0); {12056#false} is VALID [2022-02-21 04:24:19,496 INFO L290 TraceCheckUtils]: 27: Hoare triple {12056#false} assume 0 == ~E_5~0;~E_5~0 := 1; {12056#false} is VALID [2022-02-21 04:24:19,497 INFO L290 TraceCheckUtils]: 28: Hoare triple {12056#false} assume !(0 == ~E_6~0); {12056#false} is VALID [2022-02-21 04:24:19,497 INFO L290 TraceCheckUtils]: 29: Hoare triple {12056#false} assume !(0 == ~E_7~0); {12056#false} is VALID [2022-02-21 04:24:19,497 INFO L290 TraceCheckUtils]: 30: Hoare triple {12056#false} assume !(0 == ~E_8~0); {12056#false} is VALID [2022-02-21 04:24:19,497 INFO L290 TraceCheckUtils]: 31: Hoare triple {12056#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {12056#false} is VALID [2022-02-21 04:24:19,497 INFO L290 TraceCheckUtils]: 32: Hoare triple {12056#false} assume !(1 == ~m_pc~0); {12056#false} is VALID [2022-02-21 04:24:19,497 INFO L290 TraceCheckUtils]: 33: Hoare triple {12056#false} is_master_triggered_~__retres1~0#1 := 0; {12056#false} is VALID [2022-02-21 04:24:19,497 INFO L290 TraceCheckUtils]: 34: Hoare triple {12056#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {12056#false} is VALID [2022-02-21 04:24:19,497 INFO L290 TraceCheckUtils]: 35: Hoare triple {12056#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {12056#false} is VALID [2022-02-21 04:24:19,498 INFO L290 TraceCheckUtils]: 36: Hoare triple {12056#false} assume !(0 != activate_threads_~tmp~1#1); {12056#false} is VALID [2022-02-21 04:24:19,498 INFO L290 TraceCheckUtils]: 37: Hoare triple {12056#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {12056#false} is VALID [2022-02-21 04:24:19,498 INFO L290 TraceCheckUtils]: 38: Hoare triple {12056#false} assume 1 == ~t1_pc~0; {12056#false} is VALID [2022-02-21 04:24:19,498 INFO L290 TraceCheckUtils]: 39: Hoare triple {12056#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {12056#false} is VALID [2022-02-21 04:24:19,498 INFO L290 TraceCheckUtils]: 40: Hoare triple {12056#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {12056#false} is VALID [2022-02-21 04:24:19,498 INFO L290 TraceCheckUtils]: 41: Hoare triple {12056#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {12056#false} is VALID [2022-02-21 04:24:19,498 INFO L290 TraceCheckUtils]: 42: Hoare triple {12056#false} assume !(0 != activate_threads_~tmp___0~0#1); {12056#false} is VALID [2022-02-21 04:24:19,499 INFO L290 TraceCheckUtils]: 43: Hoare triple {12056#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {12056#false} is VALID [2022-02-21 04:24:19,499 INFO L290 TraceCheckUtils]: 44: Hoare triple {12056#false} assume 1 == ~t2_pc~0; {12056#false} is VALID [2022-02-21 04:24:19,499 INFO L290 TraceCheckUtils]: 45: Hoare triple {12056#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {12056#false} is VALID [2022-02-21 04:24:19,499 INFO L290 TraceCheckUtils]: 46: Hoare triple {12056#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {12056#false} is VALID [2022-02-21 04:24:19,499 INFO L290 TraceCheckUtils]: 47: Hoare triple {12056#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {12056#false} is VALID [2022-02-21 04:24:19,499 INFO L290 TraceCheckUtils]: 48: Hoare triple {12056#false} assume !(0 != activate_threads_~tmp___1~0#1); {12056#false} is VALID [2022-02-21 04:24:19,499 INFO L290 TraceCheckUtils]: 49: Hoare triple {12056#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {12056#false} is VALID [2022-02-21 04:24:19,499 INFO L290 TraceCheckUtils]: 50: Hoare triple {12056#false} assume !(1 == ~t3_pc~0); {12056#false} is VALID [2022-02-21 04:24:19,500 INFO L290 TraceCheckUtils]: 51: Hoare triple {12056#false} is_transmit3_triggered_~__retres1~3#1 := 0; {12056#false} is VALID [2022-02-21 04:24:19,500 INFO L290 TraceCheckUtils]: 52: Hoare triple {12056#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {12056#false} is VALID [2022-02-21 04:24:19,500 INFO L290 TraceCheckUtils]: 53: Hoare triple {12056#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {12056#false} is VALID [2022-02-21 04:24:19,500 INFO L290 TraceCheckUtils]: 54: Hoare triple {12056#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {12056#false} is VALID [2022-02-21 04:24:19,500 INFO L290 TraceCheckUtils]: 55: Hoare triple {12056#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {12056#false} is VALID [2022-02-21 04:24:19,500 INFO L290 TraceCheckUtils]: 56: Hoare triple {12056#false} assume 1 == ~t4_pc~0; {12056#false} is VALID [2022-02-21 04:24:19,500 INFO L290 TraceCheckUtils]: 57: Hoare triple {12056#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {12056#false} is VALID [2022-02-21 04:24:19,500 INFO L290 TraceCheckUtils]: 58: Hoare triple {12056#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {12056#false} is VALID [2022-02-21 04:24:19,501 INFO L290 TraceCheckUtils]: 59: Hoare triple {12056#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {12056#false} is VALID [2022-02-21 04:24:19,501 INFO L290 TraceCheckUtils]: 60: Hoare triple {12056#false} assume !(0 != activate_threads_~tmp___3~0#1); {12056#false} is VALID [2022-02-21 04:24:19,501 INFO L290 TraceCheckUtils]: 61: Hoare triple {12056#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {12056#false} is VALID [2022-02-21 04:24:19,501 INFO L290 TraceCheckUtils]: 62: Hoare triple {12056#false} assume !(1 == ~t5_pc~0); {12056#false} is VALID [2022-02-21 04:24:19,501 INFO L290 TraceCheckUtils]: 63: Hoare triple {12056#false} is_transmit5_triggered_~__retres1~5#1 := 0; {12056#false} is VALID [2022-02-21 04:24:19,501 INFO L290 TraceCheckUtils]: 64: Hoare triple {12056#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {12056#false} is VALID [2022-02-21 04:24:19,501 INFO L290 TraceCheckUtils]: 65: Hoare triple {12056#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {12056#false} is VALID [2022-02-21 04:24:19,501 INFO L290 TraceCheckUtils]: 66: Hoare triple {12056#false} assume !(0 != activate_threads_~tmp___4~0#1); {12056#false} is VALID [2022-02-21 04:24:19,502 INFO L290 TraceCheckUtils]: 67: Hoare triple {12056#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {12056#false} is VALID [2022-02-21 04:24:19,502 INFO L290 TraceCheckUtils]: 68: Hoare triple {12056#false} assume 1 == ~t6_pc~0; {12056#false} is VALID [2022-02-21 04:24:19,502 INFO L290 TraceCheckUtils]: 69: Hoare triple {12056#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {12056#false} is VALID [2022-02-21 04:24:19,502 INFO L290 TraceCheckUtils]: 70: Hoare triple {12056#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {12056#false} is VALID [2022-02-21 04:24:19,502 INFO L290 TraceCheckUtils]: 71: Hoare triple {12056#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {12056#false} is VALID [2022-02-21 04:24:19,502 INFO L290 TraceCheckUtils]: 72: Hoare triple {12056#false} assume !(0 != activate_threads_~tmp___5~0#1); {12056#false} is VALID [2022-02-21 04:24:19,502 INFO L290 TraceCheckUtils]: 73: Hoare triple {12056#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {12056#false} is VALID [2022-02-21 04:24:19,503 INFO L290 TraceCheckUtils]: 74: Hoare triple {12056#false} assume !(1 == ~t7_pc~0); {12056#false} is VALID [2022-02-21 04:24:19,503 INFO L290 TraceCheckUtils]: 75: Hoare triple {12056#false} is_transmit7_triggered_~__retres1~7#1 := 0; {12056#false} is VALID [2022-02-21 04:24:19,503 INFO L290 TraceCheckUtils]: 76: Hoare triple {12056#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {12056#false} is VALID [2022-02-21 04:24:19,503 INFO L290 TraceCheckUtils]: 77: Hoare triple {12056#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {12056#false} is VALID [2022-02-21 04:24:19,503 INFO L290 TraceCheckUtils]: 78: Hoare triple {12056#false} assume !(0 != activate_threads_~tmp___6~0#1); {12056#false} is VALID [2022-02-21 04:24:19,503 INFO L290 TraceCheckUtils]: 79: Hoare triple {12056#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {12056#false} is VALID [2022-02-21 04:24:19,503 INFO L290 TraceCheckUtils]: 80: Hoare triple {12056#false} assume 1 == ~t8_pc~0; {12056#false} is VALID [2022-02-21 04:24:19,504 INFO L290 TraceCheckUtils]: 81: Hoare triple {12056#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {12056#false} is VALID [2022-02-21 04:24:19,504 INFO L290 TraceCheckUtils]: 82: Hoare triple {12056#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {12056#false} is VALID [2022-02-21 04:24:19,504 INFO L290 TraceCheckUtils]: 83: Hoare triple {12056#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {12056#false} is VALID [2022-02-21 04:24:19,504 INFO L290 TraceCheckUtils]: 84: Hoare triple {12056#false} assume !(0 != activate_threads_~tmp___7~0#1); {12056#false} is VALID [2022-02-21 04:24:19,504 INFO L290 TraceCheckUtils]: 85: Hoare triple {12056#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {12056#false} is VALID [2022-02-21 04:24:19,504 INFO L290 TraceCheckUtils]: 86: Hoare triple {12056#false} assume !(1 == ~M_E~0); {12056#false} is VALID [2022-02-21 04:24:19,504 INFO L290 TraceCheckUtils]: 87: Hoare triple {12056#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {12056#false} is VALID [2022-02-21 04:24:19,504 INFO L290 TraceCheckUtils]: 88: Hoare triple {12056#false} assume !(1 == ~T2_E~0); {12056#false} is VALID [2022-02-21 04:24:19,505 INFO L290 TraceCheckUtils]: 89: Hoare triple {12056#false} assume !(1 == ~T3_E~0); {12056#false} is VALID [2022-02-21 04:24:19,505 INFO L290 TraceCheckUtils]: 90: Hoare triple {12056#false} assume !(1 == ~T4_E~0); {12056#false} is VALID [2022-02-21 04:24:19,505 INFO L290 TraceCheckUtils]: 91: Hoare triple {12056#false} assume !(1 == ~T5_E~0); {12056#false} is VALID [2022-02-21 04:24:19,505 INFO L290 TraceCheckUtils]: 92: Hoare triple {12056#false} assume !(1 == ~T6_E~0); {12056#false} is VALID [2022-02-21 04:24:19,505 INFO L290 TraceCheckUtils]: 93: Hoare triple {12056#false} assume !(1 == ~T7_E~0); {12056#false} is VALID [2022-02-21 04:24:19,505 INFO L290 TraceCheckUtils]: 94: Hoare triple {12056#false} assume !(1 == ~T8_E~0); {12056#false} is VALID [2022-02-21 04:24:19,505 INFO L290 TraceCheckUtils]: 95: Hoare triple {12056#false} assume 1 == ~E_1~0;~E_1~0 := 2; {12056#false} is VALID [2022-02-21 04:24:19,505 INFO L290 TraceCheckUtils]: 96: Hoare triple {12056#false} assume !(1 == ~E_2~0); {12056#false} is VALID [2022-02-21 04:24:19,506 INFO L290 TraceCheckUtils]: 97: Hoare triple {12056#false} assume !(1 == ~E_3~0); {12056#false} is VALID [2022-02-21 04:24:19,506 INFO L290 TraceCheckUtils]: 98: Hoare triple {12056#false} assume !(1 == ~E_4~0); {12056#false} is VALID [2022-02-21 04:24:19,506 INFO L290 TraceCheckUtils]: 99: Hoare triple {12056#false} assume !(1 == ~E_5~0); {12056#false} is VALID [2022-02-21 04:24:19,506 INFO L290 TraceCheckUtils]: 100: Hoare triple {12056#false} assume !(1 == ~E_6~0); {12056#false} is VALID [2022-02-21 04:24:19,506 INFO L290 TraceCheckUtils]: 101: Hoare triple {12056#false} assume !(1 == ~E_7~0); {12056#false} is VALID [2022-02-21 04:24:19,506 INFO L290 TraceCheckUtils]: 102: Hoare triple {12056#false} assume !(1 == ~E_8~0); {12056#false} is VALID [2022-02-21 04:24:19,506 INFO L290 TraceCheckUtils]: 103: Hoare triple {12056#false} assume { :end_inline_reset_delta_events } true; {12056#false} is VALID [2022-02-21 04:24:19,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:19,507 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:19,507 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1645311305] [2022-02-21 04:24:19,507 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1645311305] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:19,507 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:19,507 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:19,508 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749134429] [2022-02-21 04:24:19,508 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:19,508 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:19,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:19,509 INFO L85 PathProgramCache]: Analyzing trace with hash 813232605, now seen corresponding path program 1 times [2022-02-21 04:24:19,509 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:19,509 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015032031] [2022-02-21 04:24:19,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:19,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:19,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:19,537 INFO L290 TraceCheckUtils]: 0: Hoare triple {12058#true} assume !false; {12058#true} is VALID [2022-02-21 04:24:19,538 INFO L290 TraceCheckUtils]: 1: Hoare triple {12058#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {12058#true} is VALID [2022-02-21 04:24:19,538 INFO L290 TraceCheckUtils]: 2: Hoare triple {12058#true} assume !false; {12058#true} is VALID [2022-02-21 04:24:19,538 INFO L290 TraceCheckUtils]: 3: Hoare triple {12058#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {12058#true} is VALID [2022-02-21 04:24:19,538 INFO L290 TraceCheckUtils]: 4: Hoare triple {12058#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {12058#true} is VALID [2022-02-21 04:24:19,538 INFO L290 TraceCheckUtils]: 5: Hoare triple {12058#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {12058#true} is VALID [2022-02-21 04:24:19,538 INFO L290 TraceCheckUtils]: 6: Hoare triple {12058#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {12058#true} is VALID [2022-02-21 04:24:19,538 INFO L290 TraceCheckUtils]: 7: Hoare triple {12058#true} assume !(0 != eval_~tmp~0#1); {12058#true} is VALID [2022-02-21 04:24:19,539 INFO L290 TraceCheckUtils]: 8: Hoare triple {12058#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {12058#true} is VALID [2022-02-21 04:24:19,539 INFO L290 TraceCheckUtils]: 9: Hoare triple {12058#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {12058#true} is VALID [2022-02-21 04:24:19,539 INFO L290 TraceCheckUtils]: 10: Hoare triple {12058#true} assume !(0 == ~M_E~0); {12058#true} is VALID [2022-02-21 04:24:19,539 INFO L290 TraceCheckUtils]: 11: Hoare triple {12058#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {12058#true} is VALID [2022-02-21 04:24:19,539 INFO L290 TraceCheckUtils]: 12: Hoare triple {12058#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {12058#true} is VALID [2022-02-21 04:24:19,539 INFO L290 TraceCheckUtils]: 13: Hoare triple {12058#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {12058#true} is VALID [2022-02-21 04:24:19,540 INFO L290 TraceCheckUtils]: 14: Hoare triple {12058#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,540 INFO L290 TraceCheckUtils]: 15: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,540 INFO L290 TraceCheckUtils]: 16: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,541 INFO L290 TraceCheckUtils]: 17: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,541 INFO L290 TraceCheckUtils]: 18: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,541 INFO L290 TraceCheckUtils]: 19: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,542 INFO L290 TraceCheckUtils]: 20: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,542 INFO L290 TraceCheckUtils]: 21: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,542 INFO L290 TraceCheckUtils]: 22: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,542 INFO L290 TraceCheckUtils]: 23: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,543 INFO L290 TraceCheckUtils]: 24: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,543 INFO L290 TraceCheckUtils]: 25: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,543 INFO L290 TraceCheckUtils]: 26: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,544 INFO L290 TraceCheckUtils]: 27: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,544 INFO L290 TraceCheckUtils]: 28: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~m_pc~0); {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,544 INFO L290 TraceCheckUtils]: 29: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,545 INFO L290 TraceCheckUtils]: 30: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,545 INFO L290 TraceCheckUtils]: 31: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,545 INFO L290 TraceCheckUtils]: 32: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,545 INFO L290 TraceCheckUtils]: 33: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,546 INFO L290 TraceCheckUtils]: 34: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t1_pc~0); {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,546 INFO L290 TraceCheckUtils]: 35: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,546 INFO L290 TraceCheckUtils]: 36: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,547 INFO L290 TraceCheckUtils]: 37: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,547 INFO L290 TraceCheckUtils]: 38: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,547 INFO L290 TraceCheckUtils]: 39: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,548 INFO L290 TraceCheckUtils]: 40: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t2_pc~0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,548 INFO L290 TraceCheckUtils]: 41: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,548 INFO L290 TraceCheckUtils]: 42: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,548 INFO L290 TraceCheckUtils]: 43: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,549 INFO L290 TraceCheckUtils]: 44: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,549 INFO L290 TraceCheckUtils]: 45: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,549 INFO L290 TraceCheckUtils]: 46: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t3_pc~0); {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,550 INFO L290 TraceCheckUtils]: 47: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,550 INFO L290 TraceCheckUtils]: 48: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,550 INFO L290 TraceCheckUtils]: 49: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,550 INFO L290 TraceCheckUtils]: 50: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,551 INFO L290 TraceCheckUtils]: 51: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,551 INFO L290 TraceCheckUtils]: 52: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t4_pc~0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,551 INFO L290 TraceCheckUtils]: 53: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,552 INFO L290 TraceCheckUtils]: 54: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,552 INFO L290 TraceCheckUtils]: 55: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,552 INFO L290 TraceCheckUtils]: 56: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,553 INFO L290 TraceCheckUtils]: 57: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,553 INFO L290 TraceCheckUtils]: 58: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t5_pc~0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,553 INFO L290 TraceCheckUtils]: 59: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,553 INFO L290 TraceCheckUtils]: 60: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,554 INFO L290 TraceCheckUtils]: 61: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,554 INFO L290 TraceCheckUtils]: 62: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,554 INFO L290 TraceCheckUtils]: 63: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,555 INFO L290 TraceCheckUtils]: 64: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t6_pc~0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,555 INFO L290 TraceCheckUtils]: 65: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,555 INFO L290 TraceCheckUtils]: 66: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,556 INFO L290 TraceCheckUtils]: 67: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,556 INFO L290 TraceCheckUtils]: 68: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,556 INFO L290 TraceCheckUtils]: 69: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,556 INFO L290 TraceCheckUtils]: 70: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t7_pc~0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,557 INFO L290 TraceCheckUtils]: 71: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,560 INFO L290 TraceCheckUtils]: 72: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,560 INFO L290 TraceCheckUtils]: 73: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,561 INFO L290 TraceCheckUtils]: 74: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,561 INFO L290 TraceCheckUtils]: 75: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,561 INFO L290 TraceCheckUtils]: 76: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t8_pc~0); {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,561 INFO L290 TraceCheckUtils]: 77: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,562 INFO L290 TraceCheckUtils]: 78: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,562 INFO L290 TraceCheckUtils]: 79: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,562 INFO L290 TraceCheckUtils]: 80: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,563 INFO L290 TraceCheckUtils]: 81: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,563 INFO L290 TraceCheckUtils]: 82: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,563 INFO L290 TraceCheckUtils]: 83: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,564 INFO L290 TraceCheckUtils]: 84: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,564 INFO L290 TraceCheckUtils]: 85: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {12060#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:19,564 INFO L290 TraceCheckUtils]: 86: Hoare triple {12060#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {12059#false} is VALID [2022-02-21 04:24:19,564 INFO L290 TraceCheckUtils]: 87: Hoare triple {12059#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {12059#false} is VALID [2022-02-21 04:24:19,564 INFO L290 TraceCheckUtils]: 88: Hoare triple {12059#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {12059#false} is VALID [2022-02-21 04:24:19,565 INFO L290 TraceCheckUtils]: 89: Hoare triple {12059#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {12059#false} is VALID [2022-02-21 04:24:19,565 INFO L290 TraceCheckUtils]: 90: Hoare triple {12059#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {12059#false} is VALID [2022-02-21 04:24:19,565 INFO L290 TraceCheckUtils]: 91: Hoare triple {12059#false} assume 1 == ~E_1~0;~E_1~0 := 2; {12059#false} is VALID [2022-02-21 04:24:19,565 INFO L290 TraceCheckUtils]: 92: Hoare triple {12059#false} assume 1 == ~E_2~0;~E_2~0 := 2; {12059#false} is VALID [2022-02-21 04:24:19,565 INFO L290 TraceCheckUtils]: 93: Hoare triple {12059#false} assume 1 == ~E_3~0;~E_3~0 := 2; {12059#false} is VALID [2022-02-21 04:24:19,565 INFO L290 TraceCheckUtils]: 94: Hoare triple {12059#false} assume !(1 == ~E_4~0); {12059#false} is VALID [2022-02-21 04:24:19,565 INFO L290 TraceCheckUtils]: 95: Hoare triple {12059#false} assume 1 == ~E_5~0;~E_5~0 := 2; {12059#false} is VALID [2022-02-21 04:24:19,565 INFO L290 TraceCheckUtils]: 96: Hoare triple {12059#false} assume 1 == ~E_6~0;~E_6~0 := 2; {12059#false} is VALID [2022-02-21 04:24:19,566 INFO L290 TraceCheckUtils]: 97: Hoare triple {12059#false} assume 1 == ~E_7~0;~E_7~0 := 2; {12059#false} is VALID [2022-02-21 04:24:19,566 INFO L290 TraceCheckUtils]: 98: Hoare triple {12059#false} assume 1 == ~E_8~0;~E_8~0 := 2; {12059#false} is VALID [2022-02-21 04:24:19,566 INFO L290 TraceCheckUtils]: 99: Hoare triple {12059#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {12059#false} is VALID [2022-02-21 04:24:19,566 INFO L290 TraceCheckUtils]: 100: Hoare triple {12059#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {12059#false} is VALID [2022-02-21 04:24:19,566 INFO L290 TraceCheckUtils]: 101: Hoare triple {12059#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {12059#false} is VALID [2022-02-21 04:24:19,566 INFO L290 TraceCheckUtils]: 102: Hoare triple {12059#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {12059#false} is VALID [2022-02-21 04:24:19,566 INFO L290 TraceCheckUtils]: 103: Hoare triple {12059#false} assume !(0 == start_simulation_~tmp~3#1); {12059#false} is VALID [2022-02-21 04:24:19,566 INFO L290 TraceCheckUtils]: 104: Hoare triple {12059#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {12059#false} is VALID [2022-02-21 04:24:19,567 INFO L290 TraceCheckUtils]: 105: Hoare triple {12059#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {12059#false} is VALID [2022-02-21 04:24:19,567 INFO L290 TraceCheckUtils]: 106: Hoare triple {12059#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {12059#false} is VALID [2022-02-21 04:24:19,567 INFO L290 TraceCheckUtils]: 107: Hoare triple {12059#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {12059#false} is VALID [2022-02-21 04:24:19,567 INFO L290 TraceCheckUtils]: 108: Hoare triple {12059#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {12059#false} is VALID [2022-02-21 04:24:19,567 INFO L290 TraceCheckUtils]: 109: Hoare triple {12059#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {12059#false} is VALID [2022-02-21 04:24:19,567 INFO L290 TraceCheckUtils]: 110: Hoare triple {12059#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {12059#false} is VALID [2022-02-21 04:24:19,567 INFO L290 TraceCheckUtils]: 111: Hoare triple {12059#false} assume !(0 != start_simulation_~tmp___0~1#1); {12059#false} is VALID [2022-02-21 04:24:19,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:19,568 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:19,568 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015032031] [2022-02-21 04:24:19,568 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2015032031] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:19,569 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:19,569 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:19,569 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550322273] [2022-02-21 04:24:19,569 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:19,569 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:19,569 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:19,570 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:19,570 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:19,570 INFO L87 Difference]: Start difference. First operand 924 states and 1377 transitions. cyclomatic complexity: 454 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,239 INFO L93 Difference]: Finished difference Result 924 states and 1376 transitions. [2022-02-21 04:24:20,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:20,239 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,310 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:20,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1376 transitions. [2022-02-21 04:24:20,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:20,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1376 transitions. [2022-02-21 04:24:20,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-02-21 04:24:20,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-02-21 04:24:20,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1376 transitions. [2022-02-21 04:24:20,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:20,357 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1376 transitions. [2022-02-21 04:24:20,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1376 transitions. [2022-02-21 04:24:20,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-02-21 04:24:20,365 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:20,367 INFO L82 GeneralOperation]: Start isEquivalent. First operand 924 states and 1376 transitions. Second operand has 924 states, 924 states have (on average 1.4891774891774892) internal successors, (1376), 923 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,368 INFO L74 IsIncluded]: Start isIncluded. First operand 924 states and 1376 transitions. Second operand has 924 states, 924 states have (on average 1.4891774891774892) internal successors, (1376), 923 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,369 INFO L87 Difference]: Start difference. First operand 924 states and 1376 transitions. Second operand has 924 states, 924 states have (on average 1.4891774891774892) internal successors, (1376), 923 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,392 INFO L93 Difference]: Finished difference Result 924 states and 1376 transitions. [2022-02-21 04:24:20,392 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1376 transitions. [2022-02-21 04:24:20,393 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:20,393 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:20,394 INFO L74 IsIncluded]: Start isIncluded. First operand has 924 states, 924 states have (on average 1.4891774891774892) internal successors, (1376), 923 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1376 transitions. [2022-02-21 04:24:20,396 INFO L87 Difference]: Start difference. First operand has 924 states, 924 states have (on average 1.4891774891774892) internal successors, (1376), 923 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1376 transitions. [2022-02-21 04:24:20,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,418 INFO L93 Difference]: Finished difference Result 924 states and 1376 transitions. [2022-02-21 04:24:20,418 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1376 transitions. [2022-02-21 04:24:20,419 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:20,419 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:20,419 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:20,420 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:20,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4891774891774892) internal successors, (1376), 923 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1376 transitions. [2022-02-21 04:24:20,443 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1376 transitions. [2022-02-21 04:24:20,443 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1376 transitions. [2022-02-21 04:24:20,443 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:20,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1376 transitions. [2022-02-21 04:24:20,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:20,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:20,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:20,447 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:20,447 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:20,447 INFO L791 eck$LassoCheckResult]: Stem: 13661#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 13662#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13904#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13076#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13077#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 13348#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13349#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13846#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13837#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13416#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13417#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13642#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13643#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13498#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13499#L838 assume !(0 == ~M_E~0); 13649#L838-2 assume !(0 == ~T1_E~0); 13038#L843-1 assume !(0 == ~T2_E~0); 13039#L848-1 assume !(0 == ~T3_E~0); 13158#L853-1 assume !(0 == ~T4_E~0); 13486#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12987#L863-1 assume !(0 == ~T6_E~0); 12988#L868-1 assume !(0 == ~T7_E~0); 13878#L873-1 assume !(0 == ~T8_E~0); 13876#L878-1 assume !(0 == ~E_1~0); 13865#L883-1 assume !(0 == ~E_2~0); 13866#L888-1 assume !(0 == ~E_3~0); 13613#L893-1 assume !(0 == ~E_4~0); 13614#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13890#L903-1 assume !(0 == ~E_6~0); 13864#L908-1 assume !(0 == ~E_7~0); 13740#L913-1 assume !(0 == ~E_8~0); 13052#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13053#L402 assume !(1 == ~m_pc~0); 13265#L402-2 is_master_triggered_~__retres1~0#1 := 0; 13179#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13180#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13422#L1035 assume !(0 != activate_threads_~tmp~1#1); 13423#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13475#L421 assume 1 == ~t1_pc~0; 13860#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13882#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13467#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13468#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 13527#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13887#L440 assume 1 == ~t2_pc~0; 13022#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13023#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13189#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13898#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 13752#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13380#L459 assume !(1 == ~t3_pc~0); 13381#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13859#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13684#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13173#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13174#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13183#L478 assume 1 == ~t4_pc~0; 13184#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13618#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13845#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13354#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 13099#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13100#L497 assume !(1 == ~t5_pc~0); 13144#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13145#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13436#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13437#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 13853#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13854#L516 assume 1 == ~t6_pc~0; 13907#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13639#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13640#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13228#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 13229#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13630#L535 assume !(1 == ~t7_pc~0); 13631#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13700#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13701#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13729#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 13720#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13721#L554 assume 1 == ~t8_pc~0; 13670#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13014#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13770#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13319#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 13320#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12998#L931 assume !(1 == ~M_E~0); 12999#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13873#L936-1 assume !(1 == ~T2_E~0); 13896#L941-1 assume !(1 == ~T3_E~0); 13476#L946-1 assume !(1 == ~T4_E~0); 13477#L951-1 assume !(1 == ~T5_E~0); 13243#L956-1 assume !(1 == ~T6_E~0); 13244#L961-1 assume !(1 == ~T7_E~0); 13615#L966-1 assume !(1 == ~T8_E~0); 13616#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13723#L976-1 assume !(1 == ~E_2~0); 13692#L981-1 assume !(1 == ~E_3~0); 13481#L986-1 assume !(1 == ~E_4~0); 13273#L991-1 assume !(1 == ~E_5~0); 13274#L996-1 assume !(1 == ~E_6~0); 13883#L1001-1 assume !(1 == ~E_7~0); 13659#L1006-1 assume !(1 == ~E_8~0); 13660#L1011-1 assume { :end_inline_reset_delta_events } true; 13061#L1272-2 [2022-02-21 04:24:20,447 INFO L793 eck$LassoCheckResult]: Loop: 13061#L1272-2 assume !false; 13062#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13063#L813 assume !false; 13064#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13810#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13066#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13612#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13620#L696 assume !(0 != eval_~tmp~0#1); 13663#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13664#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13787#L838-3 assume !(0 == ~M_E~0); 13705#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13706#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13569#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13570#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13617#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13680#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13672#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13673#L873-3 assume !(0 == ~T8_E~0); 13295#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13025#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13026#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13027#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13028#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13502#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13811#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13515#L913-3 assume !(0 == ~E_8~0); 13068#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13069#L402-27 assume 1 == ~m_pc~0; 13015#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13016#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13505#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13506#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13824#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13825#L421-27 assume 1 == ~t1_pc~0; 13735#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13289#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13538#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13539#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13884#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13633#L440-27 assume 1 == ~t2_pc~0; 13634#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13806#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13372#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13373#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13547#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13276#L459-27 assume !(1 == ~t3_pc~0); 13277#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 13695#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13340#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13341#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13629#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13877#L478-27 assume !(1 == ~t4_pc~0); 13266#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 13267#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13641#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13775#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13776#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13812#L497-27 assume 1 == ~t5_pc~0; 13813#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13305#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13306#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13249#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13250#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13507#L516-27 assume 1 == ~t6_pc~0; 13508#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13359#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13360#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13510#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13650#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13439#L535-27 assume 1 == ~t7_pc~0; 13440#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13756#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13785#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13786#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13393#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13394#L554-27 assume !(1 == ~t8_pc~0); 13042#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 13043#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13188#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13526#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 13293#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13294#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13169#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13170#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13390#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13522#L946-3 assume !(1 == ~T4_E~0); 13311#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13312#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13591#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13400#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13401#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13638#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13059#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13060#L986-3 assume !(1 == ~E_4~0); 13050#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13051#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13710#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13378#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13379#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13092#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13094#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13408#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 13409#L1291 assume !(0 == start_simulation_~tmp~3#1); 13588#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13494#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 12989#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 12990#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 13794#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13458#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13459#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 13675#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 13061#L1272-2 [2022-02-21 04:24:20,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:20,448 INFO L85 PathProgramCache]: Analyzing trace with hash 1862277854, now seen corresponding path program 1 times [2022-02-21 04:24:20,448 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:20,448 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102466969] [2022-02-21 04:24:20,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:20,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:20,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:20,469 INFO L290 TraceCheckUtils]: 0: Hoare triple {15760#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {15760#true} is VALID [2022-02-21 04:24:20,470 INFO L290 TraceCheckUtils]: 1: Hoare triple {15760#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {15762#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:20,470 INFO L290 TraceCheckUtils]: 2: Hoare triple {15762#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {15762#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:20,470 INFO L290 TraceCheckUtils]: 3: Hoare triple {15762#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {15762#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:20,470 INFO L290 TraceCheckUtils]: 4: Hoare triple {15762#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {15762#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:20,471 INFO L290 TraceCheckUtils]: 5: Hoare triple {15762#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {15762#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:20,471 INFO L290 TraceCheckUtils]: 6: Hoare triple {15762#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {15762#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:20,471 INFO L290 TraceCheckUtils]: 7: Hoare triple {15762#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {15762#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:20,471 INFO L290 TraceCheckUtils]: 8: Hoare triple {15762#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {15762#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:20,471 INFO L290 TraceCheckUtils]: 9: Hoare triple {15762#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 10: Hoare triple {15761#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 11: Hoare triple {15761#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 12: Hoare triple {15761#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 13: Hoare triple {15761#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 14: Hoare triple {15761#false} assume !(0 == ~M_E~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 15: Hoare triple {15761#false} assume !(0 == ~T1_E~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 16: Hoare triple {15761#false} assume !(0 == ~T2_E~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 17: Hoare triple {15761#false} assume !(0 == ~T3_E~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 18: Hoare triple {15761#false} assume !(0 == ~T4_E~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 19: Hoare triple {15761#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 20: Hoare triple {15761#false} assume !(0 == ~T6_E~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 21: Hoare triple {15761#false} assume !(0 == ~T7_E~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 22: Hoare triple {15761#false} assume !(0 == ~T8_E~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 23: Hoare triple {15761#false} assume !(0 == ~E_1~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 24: Hoare triple {15761#false} assume !(0 == ~E_2~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 25: Hoare triple {15761#false} assume !(0 == ~E_3~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 26: Hoare triple {15761#false} assume !(0 == ~E_4~0); {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 27: Hoare triple {15761#false} assume 0 == ~E_5~0;~E_5~0 := 1; {15761#false} is VALID [2022-02-21 04:24:20,472 INFO L290 TraceCheckUtils]: 28: Hoare triple {15761#false} assume !(0 == ~E_6~0); {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 29: Hoare triple {15761#false} assume !(0 == ~E_7~0); {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 30: Hoare triple {15761#false} assume !(0 == ~E_8~0); {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 31: Hoare triple {15761#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 32: Hoare triple {15761#false} assume !(1 == ~m_pc~0); {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 33: Hoare triple {15761#false} is_master_triggered_~__retres1~0#1 := 0; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 34: Hoare triple {15761#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 35: Hoare triple {15761#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 36: Hoare triple {15761#false} assume !(0 != activate_threads_~tmp~1#1); {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 37: Hoare triple {15761#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 38: Hoare triple {15761#false} assume 1 == ~t1_pc~0; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 39: Hoare triple {15761#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 40: Hoare triple {15761#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 41: Hoare triple {15761#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 42: Hoare triple {15761#false} assume !(0 != activate_threads_~tmp___0~0#1); {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 43: Hoare triple {15761#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 44: Hoare triple {15761#false} assume 1 == ~t2_pc~0; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 45: Hoare triple {15761#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {15761#false} is VALID [2022-02-21 04:24:20,473 INFO L290 TraceCheckUtils]: 46: Hoare triple {15761#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 47: Hoare triple {15761#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 48: Hoare triple {15761#false} assume !(0 != activate_threads_~tmp___1~0#1); {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 49: Hoare triple {15761#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 50: Hoare triple {15761#false} assume !(1 == ~t3_pc~0); {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 51: Hoare triple {15761#false} is_transmit3_triggered_~__retres1~3#1 := 0; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 52: Hoare triple {15761#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 53: Hoare triple {15761#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 54: Hoare triple {15761#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 55: Hoare triple {15761#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 56: Hoare triple {15761#false} assume 1 == ~t4_pc~0; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 57: Hoare triple {15761#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 58: Hoare triple {15761#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 59: Hoare triple {15761#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 60: Hoare triple {15761#false} assume !(0 != activate_threads_~tmp___3~0#1); {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 61: Hoare triple {15761#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 62: Hoare triple {15761#false} assume !(1 == ~t5_pc~0); {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 63: Hoare triple {15761#false} is_transmit5_triggered_~__retres1~5#1 := 0; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 64: Hoare triple {15761#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {15761#false} is VALID [2022-02-21 04:24:20,474 INFO L290 TraceCheckUtils]: 65: Hoare triple {15761#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 66: Hoare triple {15761#false} assume !(0 != activate_threads_~tmp___4~0#1); {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 67: Hoare triple {15761#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 68: Hoare triple {15761#false} assume 1 == ~t6_pc~0; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 69: Hoare triple {15761#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 70: Hoare triple {15761#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 71: Hoare triple {15761#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 72: Hoare triple {15761#false} assume !(0 != activate_threads_~tmp___5~0#1); {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 73: Hoare triple {15761#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 74: Hoare triple {15761#false} assume !(1 == ~t7_pc~0); {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 75: Hoare triple {15761#false} is_transmit7_triggered_~__retres1~7#1 := 0; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 76: Hoare triple {15761#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 77: Hoare triple {15761#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 78: Hoare triple {15761#false} assume !(0 != activate_threads_~tmp___6~0#1); {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 79: Hoare triple {15761#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 80: Hoare triple {15761#false} assume 1 == ~t8_pc~0; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 81: Hoare triple {15761#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 82: Hoare triple {15761#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 83: Hoare triple {15761#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {15761#false} is VALID [2022-02-21 04:24:20,475 INFO L290 TraceCheckUtils]: 84: Hoare triple {15761#false} assume !(0 != activate_threads_~tmp___7~0#1); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 85: Hoare triple {15761#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 86: Hoare triple {15761#false} assume !(1 == ~M_E~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 87: Hoare triple {15761#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 88: Hoare triple {15761#false} assume !(1 == ~T2_E~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 89: Hoare triple {15761#false} assume !(1 == ~T3_E~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 90: Hoare triple {15761#false} assume !(1 == ~T4_E~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 91: Hoare triple {15761#false} assume !(1 == ~T5_E~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 92: Hoare triple {15761#false} assume !(1 == ~T6_E~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 93: Hoare triple {15761#false} assume !(1 == ~T7_E~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 94: Hoare triple {15761#false} assume !(1 == ~T8_E~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 95: Hoare triple {15761#false} assume 1 == ~E_1~0;~E_1~0 := 2; {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 96: Hoare triple {15761#false} assume !(1 == ~E_2~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 97: Hoare triple {15761#false} assume !(1 == ~E_3~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 98: Hoare triple {15761#false} assume !(1 == ~E_4~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 99: Hoare triple {15761#false} assume !(1 == ~E_5~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 100: Hoare triple {15761#false} assume !(1 == ~E_6~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 101: Hoare triple {15761#false} assume !(1 == ~E_7~0); {15761#false} is VALID [2022-02-21 04:24:20,476 INFO L290 TraceCheckUtils]: 102: Hoare triple {15761#false} assume !(1 == ~E_8~0); {15761#false} is VALID [2022-02-21 04:24:20,477 INFO L290 TraceCheckUtils]: 103: Hoare triple {15761#false} assume { :end_inline_reset_delta_events } true; {15761#false} is VALID [2022-02-21 04:24:20,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:20,477 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:20,477 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102466969] [2022-02-21 04:24:20,477 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1102466969] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:20,477 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:20,477 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:20,477 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [58332] [2022-02-21 04:24:20,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:20,478 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:20,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:20,478 INFO L85 PathProgramCache]: Analyzing trace with hash 638807166, now seen corresponding path program 1 times [2022-02-21 04:24:20,478 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:20,478 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974330059] [2022-02-21 04:24:20,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:20,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:20,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:20,501 INFO L290 TraceCheckUtils]: 0: Hoare triple {15763#true} assume !false; {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 1: Hoare triple {15763#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 2: Hoare triple {15763#true} assume !false; {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 3: Hoare triple {15763#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 4: Hoare triple {15763#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 5: Hoare triple {15763#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 6: Hoare triple {15763#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 7: Hoare triple {15763#true} assume !(0 != eval_~tmp~0#1); {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 8: Hoare triple {15763#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 9: Hoare triple {15763#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 10: Hoare triple {15763#true} assume !(0 == ~M_E~0); {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 11: Hoare triple {15763#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 12: Hoare triple {15763#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {15763#true} is VALID [2022-02-21 04:24:20,502 INFO L290 TraceCheckUtils]: 13: Hoare triple {15763#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {15763#true} is VALID [2022-02-21 04:24:20,503 INFO L290 TraceCheckUtils]: 14: Hoare triple {15763#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,503 INFO L290 TraceCheckUtils]: 15: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,503 INFO L290 TraceCheckUtils]: 16: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,503 INFO L290 TraceCheckUtils]: 17: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,504 INFO L290 TraceCheckUtils]: 18: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,504 INFO L290 TraceCheckUtils]: 19: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,504 INFO L290 TraceCheckUtils]: 20: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,504 INFO L290 TraceCheckUtils]: 21: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,504 INFO L290 TraceCheckUtils]: 22: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,505 INFO L290 TraceCheckUtils]: 23: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,505 INFO L290 TraceCheckUtils]: 24: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,505 INFO L290 TraceCheckUtils]: 25: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,505 INFO L290 TraceCheckUtils]: 26: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,506 INFO L290 TraceCheckUtils]: 27: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,506 INFO L290 TraceCheckUtils]: 28: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~m_pc~0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,506 INFO L290 TraceCheckUtils]: 29: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,506 INFO L290 TraceCheckUtils]: 30: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,507 INFO L290 TraceCheckUtils]: 31: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,507 INFO L290 TraceCheckUtils]: 32: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,507 INFO L290 TraceCheckUtils]: 33: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,507 INFO L290 TraceCheckUtils]: 34: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t1_pc~0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,508 INFO L290 TraceCheckUtils]: 35: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,508 INFO L290 TraceCheckUtils]: 36: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,508 INFO L290 TraceCheckUtils]: 37: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,508 INFO L290 TraceCheckUtils]: 38: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,509 INFO L290 TraceCheckUtils]: 39: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,509 INFO L290 TraceCheckUtils]: 40: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t2_pc~0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,509 INFO L290 TraceCheckUtils]: 41: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,509 INFO L290 TraceCheckUtils]: 42: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,509 INFO L290 TraceCheckUtils]: 43: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,510 INFO L290 TraceCheckUtils]: 44: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,510 INFO L290 TraceCheckUtils]: 45: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,510 INFO L290 TraceCheckUtils]: 46: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t3_pc~0); {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,510 INFO L290 TraceCheckUtils]: 47: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,511 INFO L290 TraceCheckUtils]: 48: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,511 INFO L290 TraceCheckUtils]: 49: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,511 INFO L290 TraceCheckUtils]: 50: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,511 INFO L290 TraceCheckUtils]: 51: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,512 INFO L290 TraceCheckUtils]: 52: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t4_pc~0); {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,512 INFO L290 TraceCheckUtils]: 53: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,512 INFO L290 TraceCheckUtils]: 54: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,512 INFO L290 TraceCheckUtils]: 55: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,513 INFO L290 TraceCheckUtils]: 56: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,513 INFO L290 TraceCheckUtils]: 57: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,513 INFO L290 TraceCheckUtils]: 58: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t5_pc~0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,513 INFO L290 TraceCheckUtils]: 59: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,514 INFO L290 TraceCheckUtils]: 60: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,514 INFO L290 TraceCheckUtils]: 61: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,514 INFO L290 TraceCheckUtils]: 62: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,514 INFO L290 TraceCheckUtils]: 63: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,514 INFO L290 TraceCheckUtils]: 64: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t6_pc~0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,515 INFO L290 TraceCheckUtils]: 65: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,515 INFO L290 TraceCheckUtils]: 66: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,515 INFO L290 TraceCheckUtils]: 67: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,515 INFO L290 TraceCheckUtils]: 68: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,516 INFO L290 TraceCheckUtils]: 69: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,516 INFO L290 TraceCheckUtils]: 70: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t7_pc~0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,516 INFO L290 TraceCheckUtils]: 71: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,516 INFO L290 TraceCheckUtils]: 72: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,517 INFO L290 TraceCheckUtils]: 73: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,517 INFO L290 TraceCheckUtils]: 74: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,517 INFO L290 TraceCheckUtils]: 75: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,517 INFO L290 TraceCheckUtils]: 76: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t8_pc~0); {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,517 INFO L290 TraceCheckUtils]: 77: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,518 INFO L290 TraceCheckUtils]: 78: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,518 INFO L290 TraceCheckUtils]: 79: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,518 INFO L290 TraceCheckUtils]: 80: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,518 INFO L290 TraceCheckUtils]: 81: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,519 INFO L290 TraceCheckUtils]: 82: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,519 INFO L290 TraceCheckUtils]: 83: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,519 INFO L290 TraceCheckUtils]: 84: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,519 INFO L290 TraceCheckUtils]: 85: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {15765#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 86: Hoare triple {15765#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 87: Hoare triple {15764#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 88: Hoare triple {15764#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 89: Hoare triple {15764#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 90: Hoare triple {15764#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 91: Hoare triple {15764#false} assume 1 == ~E_1~0;~E_1~0 := 2; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 92: Hoare triple {15764#false} assume 1 == ~E_2~0;~E_2~0 := 2; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 93: Hoare triple {15764#false} assume 1 == ~E_3~0;~E_3~0 := 2; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 94: Hoare triple {15764#false} assume !(1 == ~E_4~0); {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 95: Hoare triple {15764#false} assume 1 == ~E_5~0;~E_5~0 := 2; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 96: Hoare triple {15764#false} assume 1 == ~E_6~0;~E_6~0 := 2; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 97: Hoare triple {15764#false} assume 1 == ~E_7~0;~E_7~0 := 2; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 98: Hoare triple {15764#false} assume 1 == ~E_8~0;~E_8~0 := 2; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 99: Hoare triple {15764#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 100: Hoare triple {15764#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {15764#false} is VALID [2022-02-21 04:24:20,520 INFO L290 TraceCheckUtils]: 101: Hoare triple {15764#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {15764#false} is VALID [2022-02-21 04:24:20,521 INFO L290 TraceCheckUtils]: 102: Hoare triple {15764#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {15764#false} is VALID [2022-02-21 04:24:20,521 INFO L290 TraceCheckUtils]: 103: Hoare triple {15764#false} assume !(0 == start_simulation_~tmp~3#1); {15764#false} is VALID [2022-02-21 04:24:20,521 INFO L290 TraceCheckUtils]: 104: Hoare triple {15764#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {15764#false} is VALID [2022-02-21 04:24:20,521 INFO L290 TraceCheckUtils]: 105: Hoare triple {15764#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {15764#false} is VALID [2022-02-21 04:24:20,521 INFO L290 TraceCheckUtils]: 106: Hoare triple {15764#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {15764#false} is VALID [2022-02-21 04:24:20,521 INFO L290 TraceCheckUtils]: 107: Hoare triple {15764#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {15764#false} is VALID [2022-02-21 04:24:20,521 INFO L290 TraceCheckUtils]: 108: Hoare triple {15764#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {15764#false} is VALID [2022-02-21 04:24:20,521 INFO L290 TraceCheckUtils]: 109: Hoare triple {15764#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {15764#false} is VALID [2022-02-21 04:24:20,521 INFO L290 TraceCheckUtils]: 110: Hoare triple {15764#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {15764#false} is VALID [2022-02-21 04:24:20,521 INFO L290 TraceCheckUtils]: 111: Hoare triple {15764#false} assume !(0 != start_simulation_~tmp___0~1#1); {15764#false} is VALID [2022-02-21 04:24:20,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:20,521 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:20,522 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974330059] [2022-02-21 04:24:20,522 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [974330059] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:20,522 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:20,522 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:20,522 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010844996] [2022-02-21 04:24:20,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:20,522 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:20,522 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:20,523 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:20,523 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:20,523 INFO L87 Difference]: Start difference. First operand 924 states and 1376 transitions. cyclomatic complexity: 453 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:21,146 INFO L93 Difference]: Finished difference Result 924 states and 1375 transitions. [2022-02-21 04:24:21,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:21,146 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,209 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:21,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1375 transitions. [2022-02-21 04:24:21,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:21,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1375 transitions. [2022-02-21 04:24:21,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-02-21 04:24:21,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-02-21 04:24:21,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1375 transitions. [2022-02-21 04:24:21,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:21,256 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1375 transitions. [2022-02-21 04:24:21,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1375 transitions. [2022-02-21 04:24:21,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-02-21 04:24:21,265 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:21,266 INFO L82 GeneralOperation]: Start isEquivalent. First operand 924 states and 1375 transitions. Second operand has 924 states, 924 states have (on average 1.4880952380952381) internal successors, (1375), 923 states have internal predecessors, (1375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,267 INFO L74 IsIncluded]: Start isIncluded. First operand 924 states and 1375 transitions. Second operand has 924 states, 924 states have (on average 1.4880952380952381) internal successors, (1375), 923 states have internal predecessors, (1375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,268 INFO L87 Difference]: Start difference. First operand 924 states and 1375 transitions. Second operand has 924 states, 924 states have (on average 1.4880952380952381) internal successors, (1375), 923 states have internal predecessors, (1375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:21,289 INFO L93 Difference]: Finished difference Result 924 states and 1375 transitions. [2022-02-21 04:24:21,289 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1375 transitions. [2022-02-21 04:24:21,290 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:21,290 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:21,291 INFO L74 IsIncluded]: Start isIncluded. First operand has 924 states, 924 states have (on average 1.4880952380952381) internal successors, (1375), 923 states have internal predecessors, (1375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1375 transitions. [2022-02-21 04:24:21,295 INFO L87 Difference]: Start difference. First operand has 924 states, 924 states have (on average 1.4880952380952381) internal successors, (1375), 923 states have internal predecessors, (1375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1375 transitions. [2022-02-21 04:24:21,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:21,317 INFO L93 Difference]: Finished difference Result 924 states and 1375 transitions. [2022-02-21 04:24:21,317 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1375 transitions. [2022-02-21 04:24:21,337 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:21,337 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:21,337 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:21,337 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:21,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4880952380952381) internal successors, (1375), 923 states have internal predecessors, (1375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,359 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1375 transitions. [2022-02-21 04:24:21,359 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1375 transitions. [2022-02-21 04:24:21,359 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1375 transitions. [2022-02-21 04:24:21,359 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:21,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1375 transitions. [2022-02-21 04:24:21,362 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:21,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:21,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:21,363 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:21,363 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:21,364 INFO L791 eck$LassoCheckResult]: Stem: 17366#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 17367#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17609#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16781#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16782#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 17053#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17054#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17551#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17541#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17121#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17122#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17346#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17347#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17203#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17204#L838 assume !(0 == ~M_E~0); 17354#L838-2 assume !(0 == ~T1_E~0); 16743#L843-1 assume !(0 == ~T2_E~0); 16744#L848-1 assume !(0 == ~T3_E~0); 16863#L853-1 assume !(0 == ~T4_E~0); 17191#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16690#L863-1 assume !(0 == ~T6_E~0); 16691#L868-1 assume !(0 == ~T7_E~0); 17583#L873-1 assume !(0 == ~T8_E~0); 17581#L878-1 assume !(0 == ~E_1~0); 17570#L883-1 assume !(0 == ~E_2~0); 17571#L888-1 assume !(0 == ~E_3~0); 17318#L893-1 assume !(0 == ~E_4~0); 17319#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17595#L903-1 assume !(0 == ~E_6~0); 17569#L908-1 assume !(0 == ~E_7~0); 17443#L913-1 assume !(0 == ~E_8~0); 16757#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16758#L402 assume !(1 == ~m_pc~0); 16968#L402-2 is_master_triggered_~__retres1~0#1 := 0; 16884#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16885#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17127#L1035 assume !(0 != activate_threads_~tmp~1#1); 17128#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17180#L421 assume 1 == ~t1_pc~0; 17565#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17584#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17172#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17173#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 17232#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17592#L440 assume 1 == ~t2_pc~0; 16727#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16728#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16894#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17603#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 17457#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17085#L459 assume !(1 == ~t3_pc~0); 17086#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17564#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17389#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16878#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16879#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16888#L478 assume 1 == ~t4_pc~0; 16889#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17323#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17550#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17059#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 16804#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16805#L497 assume !(1 == ~t5_pc~0); 16849#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16850#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17141#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17142#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 17557#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17558#L516 assume 1 == ~t6_pc~0; 17612#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17344#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17345#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16933#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 16934#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17335#L535 assume !(1 == ~t7_pc~0); 17336#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17405#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17406#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17434#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 17424#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17425#L554 assume 1 == ~t8_pc~0; 17374#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16719#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17475#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17024#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 17025#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16703#L931 assume !(1 == ~M_E~0); 16704#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17578#L936-1 assume !(1 == ~T2_E~0); 17601#L941-1 assume !(1 == ~T3_E~0); 17181#L946-1 assume !(1 == ~T4_E~0); 17182#L951-1 assume !(1 == ~T5_E~0); 16948#L956-1 assume !(1 == ~T6_E~0); 16949#L961-1 assume !(1 == ~T7_E~0); 17320#L966-1 assume !(1 == ~T8_E~0); 17321#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 17427#L976-1 assume !(1 == ~E_2~0); 17397#L981-1 assume !(1 == ~E_3~0); 17186#L986-1 assume !(1 == ~E_4~0); 16978#L991-1 assume !(1 == ~E_5~0); 16979#L996-1 assume !(1 == ~E_6~0); 17588#L1001-1 assume !(1 == ~E_7~0); 17364#L1006-1 assume !(1 == ~E_8~0); 17365#L1011-1 assume { :end_inline_reset_delta_events } true; 16766#L1272-2 [2022-02-21 04:24:21,364 INFO L793 eck$LassoCheckResult]: Loop: 16766#L1272-2 assume !false; 16767#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16768#L813 assume !false; 16769#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17515#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16771#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17315#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17325#L696 assume !(0 != eval_~tmp~0#1); 17368#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17369#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17492#L838-3 assume !(0 == ~M_E~0); 17410#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17411#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17273#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17274#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17322#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17385#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17377#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17378#L873-3 assume !(0 == ~T8_E~0); 17003#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16730#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16731#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16732#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16733#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17209#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17518#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17220#L913-3 assume !(0 == ~E_8~0); 16773#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16774#L402-27 assume 1 == ~m_pc~0; 16720#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16721#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17214#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17215#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17530#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17531#L421-27 assume !(1 == ~t1_pc~0); 16993#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 16994#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17243#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17244#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17589#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17338#L440-27 assume 1 == ~t2_pc~0; 17339#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17512#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17077#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17078#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17252#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16981#L459-27 assume !(1 == ~t3_pc~0); 16982#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 17400#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17045#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17046#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17334#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17582#L478-27 assume 1 == ~t4_pc~0; 17604#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16972#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17348#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17478#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17479#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17516#L497-27 assume !(1 == ~t5_pc~0); 17133#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 17009#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17010#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16954#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16955#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17210#L516-27 assume 1 == ~t6_pc~0; 17211#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17060#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17061#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17213#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17355#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17144#L535-27 assume 1 == ~t7_pc~0; 17145#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17460#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17490#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17491#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17096#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17097#L554-27 assume !(1 == ~t8_pc~0); 16747#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 16748#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16893#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17231#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 16998#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16999#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16874#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16875#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17095#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17227#L946-3 assume !(1 == ~T4_E~0); 17016#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17017#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17296#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17105#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17106#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17343#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16764#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16765#L986-3 assume !(1 == ~E_4~0); 16755#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16756#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17415#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17083#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17084#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16797#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16799#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17113#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 17114#L1291 assume !(0 == start_simulation_~tmp~3#1); 17293#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17198#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16694#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16695#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 17499#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17163#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17164#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 17380#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 16766#L1272-2 [2022-02-21 04:24:21,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:21,364 INFO L85 PathProgramCache]: Analyzing trace with hash 510892636, now seen corresponding path program 1 times [2022-02-21 04:24:21,364 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:21,364 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2105514687] [2022-02-21 04:24:21,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:21,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:21,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:21,381 INFO L290 TraceCheckUtils]: 0: Hoare triple {19465#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {19465#true} is VALID [2022-02-21 04:24:21,382 INFO L290 TraceCheckUtils]: 1: Hoare triple {19465#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {19467#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:21,382 INFO L290 TraceCheckUtils]: 2: Hoare triple {19467#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {19467#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:21,382 INFO L290 TraceCheckUtils]: 3: Hoare triple {19467#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {19467#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:21,382 INFO L290 TraceCheckUtils]: 4: Hoare triple {19467#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {19467#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:21,383 INFO L290 TraceCheckUtils]: 5: Hoare triple {19467#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {19467#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:21,383 INFO L290 TraceCheckUtils]: 6: Hoare triple {19467#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {19467#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:21,383 INFO L290 TraceCheckUtils]: 7: Hoare triple {19467#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {19467#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:21,383 INFO L290 TraceCheckUtils]: 8: Hoare triple {19467#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {19467#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 9: Hoare triple {19467#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {19467#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 10: Hoare triple {19467#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {19466#false} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 11: Hoare triple {19466#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {19466#false} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 12: Hoare triple {19466#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {19466#false} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 13: Hoare triple {19466#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {19466#false} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 14: Hoare triple {19466#false} assume !(0 == ~M_E~0); {19466#false} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 15: Hoare triple {19466#false} assume !(0 == ~T1_E~0); {19466#false} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 16: Hoare triple {19466#false} assume !(0 == ~T2_E~0); {19466#false} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 17: Hoare triple {19466#false} assume !(0 == ~T3_E~0); {19466#false} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 18: Hoare triple {19466#false} assume !(0 == ~T4_E~0); {19466#false} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 19: Hoare triple {19466#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {19466#false} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 20: Hoare triple {19466#false} assume !(0 == ~T6_E~0); {19466#false} is VALID [2022-02-21 04:24:21,384 INFO L290 TraceCheckUtils]: 21: Hoare triple {19466#false} assume !(0 == ~T7_E~0); {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 22: Hoare triple {19466#false} assume !(0 == ~T8_E~0); {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 23: Hoare triple {19466#false} assume !(0 == ~E_1~0); {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 24: Hoare triple {19466#false} assume !(0 == ~E_2~0); {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 25: Hoare triple {19466#false} assume !(0 == ~E_3~0); {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 26: Hoare triple {19466#false} assume !(0 == ~E_4~0); {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 27: Hoare triple {19466#false} assume 0 == ~E_5~0;~E_5~0 := 1; {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 28: Hoare triple {19466#false} assume !(0 == ~E_6~0); {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 29: Hoare triple {19466#false} assume !(0 == ~E_7~0); {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 30: Hoare triple {19466#false} assume !(0 == ~E_8~0); {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 31: Hoare triple {19466#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 32: Hoare triple {19466#false} assume !(1 == ~m_pc~0); {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 33: Hoare triple {19466#false} is_master_triggered_~__retres1~0#1 := 0; {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 34: Hoare triple {19466#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 35: Hoare triple {19466#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 36: Hoare triple {19466#false} assume !(0 != activate_threads_~tmp~1#1); {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 37: Hoare triple {19466#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 38: Hoare triple {19466#false} assume 1 == ~t1_pc~0; {19466#false} is VALID [2022-02-21 04:24:21,385 INFO L290 TraceCheckUtils]: 39: Hoare triple {19466#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 40: Hoare triple {19466#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 41: Hoare triple {19466#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 42: Hoare triple {19466#false} assume !(0 != activate_threads_~tmp___0~0#1); {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 43: Hoare triple {19466#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 44: Hoare triple {19466#false} assume 1 == ~t2_pc~0; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 45: Hoare triple {19466#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 46: Hoare triple {19466#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 47: Hoare triple {19466#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 48: Hoare triple {19466#false} assume !(0 != activate_threads_~tmp___1~0#1); {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 49: Hoare triple {19466#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 50: Hoare triple {19466#false} assume !(1 == ~t3_pc~0); {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 51: Hoare triple {19466#false} is_transmit3_triggered_~__retres1~3#1 := 0; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 52: Hoare triple {19466#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 53: Hoare triple {19466#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 54: Hoare triple {19466#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 55: Hoare triple {19466#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 56: Hoare triple {19466#false} assume 1 == ~t4_pc~0; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 57: Hoare triple {19466#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {19466#false} is VALID [2022-02-21 04:24:21,386 INFO L290 TraceCheckUtils]: 58: Hoare triple {19466#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 59: Hoare triple {19466#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 60: Hoare triple {19466#false} assume !(0 != activate_threads_~tmp___3~0#1); {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 61: Hoare triple {19466#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 62: Hoare triple {19466#false} assume !(1 == ~t5_pc~0); {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 63: Hoare triple {19466#false} is_transmit5_triggered_~__retres1~5#1 := 0; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 64: Hoare triple {19466#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 65: Hoare triple {19466#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 66: Hoare triple {19466#false} assume !(0 != activate_threads_~tmp___4~0#1); {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 67: Hoare triple {19466#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 68: Hoare triple {19466#false} assume 1 == ~t6_pc~0; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 69: Hoare triple {19466#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 70: Hoare triple {19466#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 71: Hoare triple {19466#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 72: Hoare triple {19466#false} assume !(0 != activate_threads_~tmp___5~0#1); {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 73: Hoare triple {19466#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 74: Hoare triple {19466#false} assume !(1 == ~t7_pc~0); {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 75: Hoare triple {19466#false} is_transmit7_triggered_~__retres1~7#1 := 0; {19466#false} is VALID [2022-02-21 04:24:21,387 INFO L290 TraceCheckUtils]: 76: Hoare triple {19466#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 77: Hoare triple {19466#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 78: Hoare triple {19466#false} assume !(0 != activate_threads_~tmp___6~0#1); {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 79: Hoare triple {19466#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 80: Hoare triple {19466#false} assume 1 == ~t8_pc~0; {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 81: Hoare triple {19466#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 82: Hoare triple {19466#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 83: Hoare triple {19466#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 84: Hoare triple {19466#false} assume !(0 != activate_threads_~tmp___7~0#1); {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 85: Hoare triple {19466#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 86: Hoare triple {19466#false} assume !(1 == ~M_E~0); {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 87: Hoare triple {19466#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 88: Hoare triple {19466#false} assume !(1 == ~T2_E~0); {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 89: Hoare triple {19466#false} assume !(1 == ~T3_E~0); {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 90: Hoare triple {19466#false} assume !(1 == ~T4_E~0); {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 91: Hoare triple {19466#false} assume !(1 == ~T5_E~0); {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 92: Hoare triple {19466#false} assume !(1 == ~T6_E~0); {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 93: Hoare triple {19466#false} assume !(1 == ~T7_E~0); {19466#false} is VALID [2022-02-21 04:24:21,388 INFO L290 TraceCheckUtils]: 94: Hoare triple {19466#false} assume !(1 == ~T8_E~0); {19466#false} is VALID [2022-02-21 04:24:21,389 INFO L290 TraceCheckUtils]: 95: Hoare triple {19466#false} assume 1 == ~E_1~0;~E_1~0 := 2; {19466#false} is VALID [2022-02-21 04:24:21,389 INFO L290 TraceCheckUtils]: 96: Hoare triple {19466#false} assume !(1 == ~E_2~0); {19466#false} is VALID [2022-02-21 04:24:21,389 INFO L290 TraceCheckUtils]: 97: Hoare triple {19466#false} assume !(1 == ~E_3~0); {19466#false} is VALID [2022-02-21 04:24:21,389 INFO L290 TraceCheckUtils]: 98: Hoare triple {19466#false} assume !(1 == ~E_4~0); {19466#false} is VALID [2022-02-21 04:24:21,389 INFO L290 TraceCheckUtils]: 99: Hoare triple {19466#false} assume !(1 == ~E_5~0); {19466#false} is VALID [2022-02-21 04:24:21,389 INFO L290 TraceCheckUtils]: 100: Hoare triple {19466#false} assume !(1 == ~E_6~0); {19466#false} is VALID [2022-02-21 04:24:21,389 INFO L290 TraceCheckUtils]: 101: Hoare triple {19466#false} assume !(1 == ~E_7~0); {19466#false} is VALID [2022-02-21 04:24:21,389 INFO L290 TraceCheckUtils]: 102: Hoare triple {19466#false} assume !(1 == ~E_8~0); {19466#false} is VALID [2022-02-21 04:24:21,389 INFO L290 TraceCheckUtils]: 103: Hoare triple {19466#false} assume { :end_inline_reset_delta_events } true; {19466#false} is VALID [2022-02-21 04:24:21,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:21,389 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:21,389 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2105514687] [2022-02-21 04:24:21,390 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2105514687] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:21,390 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:21,390 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:21,390 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645300852] [2022-02-21 04:24:21,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:21,390 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:21,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:21,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1370939933, now seen corresponding path program 1 times [2022-02-21 04:24:21,391 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:21,391 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407770071] [2022-02-21 04:24:21,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:21,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:21,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:21,413 INFO L290 TraceCheckUtils]: 0: Hoare triple {19468#true} assume !false; {19468#true} is VALID [2022-02-21 04:24:21,413 INFO L290 TraceCheckUtils]: 1: Hoare triple {19468#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {19468#true} is VALID [2022-02-21 04:24:21,413 INFO L290 TraceCheckUtils]: 2: Hoare triple {19468#true} assume !false; {19468#true} is VALID [2022-02-21 04:24:21,413 INFO L290 TraceCheckUtils]: 3: Hoare triple {19468#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {19468#true} is VALID [2022-02-21 04:24:21,413 INFO L290 TraceCheckUtils]: 4: Hoare triple {19468#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {19468#true} is VALID [2022-02-21 04:24:21,414 INFO L290 TraceCheckUtils]: 5: Hoare triple {19468#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {19468#true} is VALID [2022-02-21 04:24:21,414 INFO L290 TraceCheckUtils]: 6: Hoare triple {19468#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {19468#true} is VALID [2022-02-21 04:24:21,414 INFO L290 TraceCheckUtils]: 7: Hoare triple {19468#true} assume !(0 != eval_~tmp~0#1); {19468#true} is VALID [2022-02-21 04:24:21,414 INFO L290 TraceCheckUtils]: 8: Hoare triple {19468#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {19468#true} is VALID [2022-02-21 04:24:21,414 INFO L290 TraceCheckUtils]: 9: Hoare triple {19468#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {19468#true} is VALID [2022-02-21 04:24:21,414 INFO L290 TraceCheckUtils]: 10: Hoare triple {19468#true} assume !(0 == ~M_E~0); {19468#true} is VALID [2022-02-21 04:24:21,414 INFO L290 TraceCheckUtils]: 11: Hoare triple {19468#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {19468#true} is VALID [2022-02-21 04:24:21,414 INFO L290 TraceCheckUtils]: 12: Hoare triple {19468#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {19468#true} is VALID [2022-02-21 04:24:21,414 INFO L290 TraceCheckUtils]: 13: Hoare triple {19468#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {19468#true} is VALID [2022-02-21 04:24:21,414 INFO L290 TraceCheckUtils]: 14: Hoare triple {19468#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,414 INFO L290 TraceCheckUtils]: 15: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,415 INFO L290 TraceCheckUtils]: 16: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,415 INFO L290 TraceCheckUtils]: 17: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,415 INFO L290 TraceCheckUtils]: 18: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,415 INFO L290 TraceCheckUtils]: 19: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,416 INFO L290 TraceCheckUtils]: 20: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,416 INFO L290 TraceCheckUtils]: 21: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,416 INFO L290 TraceCheckUtils]: 22: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,416 INFO L290 TraceCheckUtils]: 23: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,417 INFO L290 TraceCheckUtils]: 24: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,417 INFO L290 TraceCheckUtils]: 25: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,417 INFO L290 TraceCheckUtils]: 26: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,417 INFO L290 TraceCheckUtils]: 27: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,417 INFO L290 TraceCheckUtils]: 28: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~m_pc~0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,418 INFO L290 TraceCheckUtils]: 29: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,418 INFO L290 TraceCheckUtils]: 30: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,418 INFO L290 TraceCheckUtils]: 31: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,418 INFO L290 TraceCheckUtils]: 32: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,419 INFO L290 TraceCheckUtils]: 33: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,419 INFO L290 TraceCheckUtils]: 34: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t1_pc~0); {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,419 INFO L290 TraceCheckUtils]: 35: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,419 INFO L290 TraceCheckUtils]: 36: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,420 INFO L290 TraceCheckUtils]: 37: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,420 INFO L290 TraceCheckUtils]: 38: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,420 INFO L290 TraceCheckUtils]: 39: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,420 INFO L290 TraceCheckUtils]: 40: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t2_pc~0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,421 INFO L290 TraceCheckUtils]: 41: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,421 INFO L290 TraceCheckUtils]: 42: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,421 INFO L290 TraceCheckUtils]: 43: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,421 INFO L290 TraceCheckUtils]: 44: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,421 INFO L290 TraceCheckUtils]: 45: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,422 INFO L290 TraceCheckUtils]: 46: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t3_pc~0); {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,422 INFO L290 TraceCheckUtils]: 47: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,422 INFO L290 TraceCheckUtils]: 48: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,422 INFO L290 TraceCheckUtils]: 49: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,423 INFO L290 TraceCheckUtils]: 50: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,423 INFO L290 TraceCheckUtils]: 51: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,423 INFO L290 TraceCheckUtils]: 52: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t4_pc~0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,423 INFO L290 TraceCheckUtils]: 53: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,424 INFO L290 TraceCheckUtils]: 54: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,424 INFO L290 TraceCheckUtils]: 55: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,424 INFO L290 TraceCheckUtils]: 56: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,424 INFO L290 TraceCheckUtils]: 57: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,424 INFO L290 TraceCheckUtils]: 58: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t5_pc~0); {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,425 INFO L290 TraceCheckUtils]: 59: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,425 INFO L290 TraceCheckUtils]: 60: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,425 INFO L290 TraceCheckUtils]: 61: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,425 INFO L290 TraceCheckUtils]: 62: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,426 INFO L290 TraceCheckUtils]: 63: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,426 INFO L290 TraceCheckUtils]: 64: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t6_pc~0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,426 INFO L290 TraceCheckUtils]: 65: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,426 INFO L290 TraceCheckUtils]: 66: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,427 INFO L290 TraceCheckUtils]: 67: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,427 INFO L290 TraceCheckUtils]: 68: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,427 INFO L290 TraceCheckUtils]: 69: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,427 INFO L290 TraceCheckUtils]: 70: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t7_pc~0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,427 INFO L290 TraceCheckUtils]: 71: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,428 INFO L290 TraceCheckUtils]: 72: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,428 INFO L290 TraceCheckUtils]: 73: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,428 INFO L290 TraceCheckUtils]: 74: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,428 INFO L290 TraceCheckUtils]: 75: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,429 INFO L290 TraceCheckUtils]: 76: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t8_pc~0); {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,429 INFO L290 TraceCheckUtils]: 77: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,429 INFO L290 TraceCheckUtils]: 78: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,429 INFO L290 TraceCheckUtils]: 79: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,430 INFO L290 TraceCheckUtils]: 80: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,430 INFO L290 TraceCheckUtils]: 81: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,430 INFO L290 TraceCheckUtils]: 82: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,430 INFO L290 TraceCheckUtils]: 83: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,430 INFO L290 TraceCheckUtils]: 84: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,431 INFO L290 TraceCheckUtils]: 85: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {19470#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:21,431 INFO L290 TraceCheckUtils]: 86: Hoare triple {19470#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {19469#false} is VALID [2022-02-21 04:24:21,431 INFO L290 TraceCheckUtils]: 87: Hoare triple {19469#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {19469#false} is VALID [2022-02-21 04:24:21,431 INFO L290 TraceCheckUtils]: 88: Hoare triple {19469#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {19469#false} is VALID [2022-02-21 04:24:21,431 INFO L290 TraceCheckUtils]: 89: Hoare triple {19469#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {19469#false} is VALID [2022-02-21 04:24:21,431 INFO L290 TraceCheckUtils]: 90: Hoare triple {19469#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {19469#false} is VALID [2022-02-21 04:24:21,431 INFO L290 TraceCheckUtils]: 91: Hoare triple {19469#false} assume 1 == ~E_1~0;~E_1~0 := 2; {19469#false} is VALID [2022-02-21 04:24:21,431 INFO L290 TraceCheckUtils]: 92: Hoare triple {19469#false} assume 1 == ~E_2~0;~E_2~0 := 2; {19469#false} is VALID [2022-02-21 04:24:21,431 INFO L290 TraceCheckUtils]: 93: Hoare triple {19469#false} assume 1 == ~E_3~0;~E_3~0 := 2; {19469#false} is VALID [2022-02-21 04:24:21,431 INFO L290 TraceCheckUtils]: 94: Hoare triple {19469#false} assume !(1 == ~E_4~0); {19469#false} is VALID [2022-02-21 04:24:21,431 INFO L290 TraceCheckUtils]: 95: Hoare triple {19469#false} assume 1 == ~E_5~0;~E_5~0 := 2; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 96: Hoare triple {19469#false} assume 1 == ~E_6~0;~E_6~0 := 2; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 97: Hoare triple {19469#false} assume 1 == ~E_7~0;~E_7~0 := 2; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 98: Hoare triple {19469#false} assume 1 == ~E_8~0;~E_8~0 := 2; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 99: Hoare triple {19469#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 100: Hoare triple {19469#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 101: Hoare triple {19469#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 102: Hoare triple {19469#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 103: Hoare triple {19469#false} assume !(0 == start_simulation_~tmp~3#1); {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 104: Hoare triple {19469#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 105: Hoare triple {19469#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 106: Hoare triple {19469#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 107: Hoare triple {19469#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 108: Hoare triple {19469#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 109: Hoare triple {19469#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 110: Hoare triple {19469#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {19469#false} is VALID [2022-02-21 04:24:21,432 INFO L290 TraceCheckUtils]: 111: Hoare triple {19469#false} assume !(0 != start_simulation_~tmp___0~1#1); {19469#false} is VALID [2022-02-21 04:24:21,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:21,433 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:21,433 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1407770071] [2022-02-21 04:24:21,433 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1407770071] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:21,433 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:21,433 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:21,433 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [718812411] [2022-02-21 04:24:21,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:21,434 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:21,434 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:21,434 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:21,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:21,434 INFO L87 Difference]: Start difference. First operand 924 states and 1375 transitions. cyclomatic complexity: 452 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,076 INFO L93 Difference]: Finished difference Result 924 states and 1374 transitions. [2022-02-21 04:24:22,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:22,077 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,144 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:22,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1374 transitions. [2022-02-21 04:24:22,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:22,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1374 transitions. [2022-02-21 04:24:22,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-02-21 04:24:22,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-02-21 04:24:22,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1374 transitions. [2022-02-21 04:24:22,189 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:22,189 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1374 transitions. [2022-02-21 04:24:22,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1374 transitions. [2022-02-21 04:24:22,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-02-21 04:24:22,197 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:22,198 INFO L82 GeneralOperation]: Start isEquivalent. First operand 924 states and 1374 transitions. Second operand has 924 states, 924 states have (on average 1.4870129870129871) internal successors, (1374), 923 states have internal predecessors, (1374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,199 INFO L74 IsIncluded]: Start isIncluded. First operand 924 states and 1374 transitions. Second operand has 924 states, 924 states have (on average 1.4870129870129871) internal successors, (1374), 923 states have internal predecessors, (1374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,200 INFO L87 Difference]: Start difference. First operand 924 states and 1374 transitions. Second operand has 924 states, 924 states have (on average 1.4870129870129871) internal successors, (1374), 923 states have internal predecessors, (1374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,220 INFO L93 Difference]: Finished difference Result 924 states and 1374 transitions. [2022-02-21 04:24:22,220 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1374 transitions. [2022-02-21 04:24:22,221 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:22,221 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:22,223 INFO L74 IsIncluded]: Start isIncluded. First operand has 924 states, 924 states have (on average 1.4870129870129871) internal successors, (1374), 923 states have internal predecessors, (1374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1374 transitions. [2022-02-21 04:24:22,223 INFO L87 Difference]: Start difference. First operand has 924 states, 924 states have (on average 1.4870129870129871) internal successors, (1374), 923 states have internal predecessors, (1374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1374 transitions. [2022-02-21 04:24:22,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,244 INFO L93 Difference]: Finished difference Result 924 states and 1374 transitions. [2022-02-21 04:24:22,244 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1374 transitions. [2022-02-21 04:24:22,245 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:22,245 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:22,245 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:22,245 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:22,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4870129870129871) internal successors, (1374), 923 states have internal predecessors, (1374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1374 transitions. [2022-02-21 04:24:22,266 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1374 transitions. [2022-02-21 04:24:22,266 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1374 transitions. [2022-02-21 04:24:22,266 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:22,267 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1374 transitions. [2022-02-21 04:24:22,269 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:22,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:22,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:22,270 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,270 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,271 INFO L791 eck$LassoCheckResult]: Stem: 21071#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 21072#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 21314#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20486#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20487#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 20758#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20759#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21256#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21246#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20826#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20827#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21051#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21052#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20908#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20909#L838 assume !(0 == ~M_E~0); 21058#L838-2 assume !(0 == ~T1_E~0); 20448#L843-1 assume !(0 == ~T2_E~0); 20449#L848-1 assume !(0 == ~T3_E~0); 20568#L853-1 assume !(0 == ~T4_E~0); 20894#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20395#L863-1 assume !(0 == ~T6_E~0); 20396#L868-1 assume !(0 == ~T7_E~0); 21288#L873-1 assume !(0 == ~T8_E~0); 21286#L878-1 assume !(0 == ~E_1~0); 21275#L883-1 assume !(0 == ~E_2~0); 21276#L888-1 assume !(0 == ~E_3~0); 21023#L893-1 assume !(0 == ~E_4~0); 21024#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 21300#L903-1 assume !(0 == ~E_6~0); 21274#L908-1 assume !(0 == ~E_7~0); 21148#L913-1 assume !(0 == ~E_8~0); 20462#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20463#L402 assume !(1 == ~m_pc~0); 20671#L402-2 is_master_triggered_~__retres1~0#1 := 0; 20589#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20590#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20832#L1035 assume !(0 != activate_threads_~tmp~1#1); 20833#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20885#L421 assume 1 == ~t1_pc~0; 21270#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21289#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20877#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20878#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 20936#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21297#L440 assume 1 == ~t2_pc~0; 20432#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20433#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20599#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21308#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 21162#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20786#L459 assume !(1 == ~t3_pc~0); 20787#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21269#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21093#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20583#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20584#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20593#L478 assume 1 == ~t4_pc~0; 20594#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21028#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21255#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20764#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 20507#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20508#L497 assume !(1 == ~t5_pc~0); 20554#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20555#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20846#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20847#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 21262#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21263#L516 assume 1 == ~t6_pc~0; 21317#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21049#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21050#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20638#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 20639#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21040#L535 assume !(1 == ~t7_pc~0); 21041#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21110#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21111#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21139#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 21129#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21130#L554 assume 1 == ~t8_pc~0; 21079#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20424#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21180#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20726#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 20727#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20408#L931 assume !(1 == ~M_E~0); 20409#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21283#L936-1 assume !(1 == ~T2_E~0); 21306#L941-1 assume !(1 == ~T3_E~0); 20886#L946-1 assume !(1 == ~T4_E~0); 20887#L951-1 assume !(1 == ~T5_E~0); 20653#L956-1 assume !(1 == ~T6_E~0); 20654#L961-1 assume !(1 == ~T7_E~0); 21025#L966-1 assume !(1 == ~T8_E~0); 21026#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21132#L976-1 assume !(1 == ~E_2~0); 21102#L981-1 assume !(1 == ~E_3~0); 20891#L986-1 assume !(1 == ~E_4~0); 20683#L991-1 assume !(1 == ~E_5~0); 20684#L996-1 assume !(1 == ~E_6~0); 21293#L1001-1 assume !(1 == ~E_7~0); 21069#L1006-1 assume !(1 == ~E_8~0); 21070#L1011-1 assume { :end_inline_reset_delta_events } true; 20471#L1272-2 [2022-02-21 04:24:22,271 INFO L793 eck$LassoCheckResult]: Loop: 20471#L1272-2 assume !false; 20472#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20473#L813 assume !false; 20474#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 21220#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20476#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 21020#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21030#L696 assume !(0 != eval_~tmp~0#1); 21073#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21074#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21195#L838-3 assume !(0 == ~M_E~0); 21115#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21116#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20978#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20979#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21027#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21090#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21082#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21083#L873-3 assume !(0 == ~T8_E~0); 20706#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20435#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20436#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20437#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20438#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20912#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21221#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20925#L913-3 assume !(0 == ~E_8~0); 20478#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20479#L402-27 assume 1 == ~m_pc~0; 20425#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20426#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20915#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20916#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21234#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21235#L421-27 assume !(1 == ~t1_pc~0); 20698#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 20699#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20948#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20949#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21294#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21043#L440-27 assume 1 == ~t2_pc~0; 21044#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21217#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20782#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20783#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20957#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20686#L459-27 assume 1 == ~t3_pc~0; 20688#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21105#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20750#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20751#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21039#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21287#L478-27 assume !(1 == ~t4_pc~0); 20676#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 20677#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21053#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21185#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21186#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21222#L497-27 assume 1 == ~t5_pc~0; 21223#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20715#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20716#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20659#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20660#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20917#L516-27 assume 1 == ~t6_pc~0; 20918#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20772#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20773#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20920#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21060#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20849#L535-27 assume 1 == ~t7_pc~0; 20850#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21166#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21196#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21197#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20803#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20804#L554-27 assume !(1 == ~t8_pc~0); 20452#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 20453#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20598#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20937#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 20703#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20704#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20579#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20580#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20800#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20932#L946-3 assume !(1 == ~T4_E~0); 20721#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20722#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21001#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20810#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20811#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21048#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20469#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20470#L986-3 assume !(1 == ~E_4~0); 20460#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20461#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21120#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20791#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20792#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20502#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20504#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20818#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 20819#L1291 assume !(0 == start_simulation_~tmp~3#1); 20998#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20904#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20399#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20400#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 21204#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20868#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20869#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 21085#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 20471#L1272-2 [2022-02-21 04:24:22,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:22,271 INFO L85 PathProgramCache]: Analyzing trace with hash 2129867550, now seen corresponding path program 1 times [2022-02-21 04:24:22,271 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:22,271 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296289357] [2022-02-21 04:24:22,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:22,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:22,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:22,288 INFO L290 TraceCheckUtils]: 0: Hoare triple {23170#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {23170#true} is VALID [2022-02-21 04:24:22,288 INFO L290 TraceCheckUtils]: 1: Hoare triple {23170#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {23172#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:22,288 INFO L290 TraceCheckUtils]: 2: Hoare triple {23172#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {23172#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:22,289 INFO L290 TraceCheckUtils]: 3: Hoare triple {23172#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {23172#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:22,289 INFO L290 TraceCheckUtils]: 4: Hoare triple {23172#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {23172#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:22,289 INFO L290 TraceCheckUtils]: 5: Hoare triple {23172#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {23172#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:22,289 INFO L290 TraceCheckUtils]: 6: Hoare triple {23172#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {23172#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:22,289 INFO L290 TraceCheckUtils]: 7: Hoare triple {23172#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {23172#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:22,290 INFO L290 TraceCheckUtils]: 8: Hoare triple {23172#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {23172#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:22,290 INFO L290 TraceCheckUtils]: 9: Hoare triple {23172#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {23172#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:22,290 INFO L290 TraceCheckUtils]: 10: Hoare triple {23172#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {23172#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:22,290 INFO L290 TraceCheckUtils]: 11: Hoare triple {23172#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {23171#false} is VALID [2022-02-21 04:24:22,290 INFO L290 TraceCheckUtils]: 12: Hoare triple {23171#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {23171#false} is VALID [2022-02-21 04:24:22,290 INFO L290 TraceCheckUtils]: 13: Hoare triple {23171#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {23171#false} is VALID [2022-02-21 04:24:22,290 INFO L290 TraceCheckUtils]: 14: Hoare triple {23171#false} assume !(0 == ~M_E~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 15: Hoare triple {23171#false} assume !(0 == ~T1_E~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 16: Hoare triple {23171#false} assume !(0 == ~T2_E~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 17: Hoare triple {23171#false} assume !(0 == ~T3_E~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 18: Hoare triple {23171#false} assume !(0 == ~T4_E~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 19: Hoare triple {23171#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 20: Hoare triple {23171#false} assume !(0 == ~T6_E~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 21: Hoare triple {23171#false} assume !(0 == ~T7_E~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 22: Hoare triple {23171#false} assume !(0 == ~T8_E~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 23: Hoare triple {23171#false} assume !(0 == ~E_1~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 24: Hoare triple {23171#false} assume !(0 == ~E_2~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 25: Hoare triple {23171#false} assume !(0 == ~E_3~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 26: Hoare triple {23171#false} assume !(0 == ~E_4~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 27: Hoare triple {23171#false} assume 0 == ~E_5~0;~E_5~0 := 1; {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 28: Hoare triple {23171#false} assume !(0 == ~E_6~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 29: Hoare triple {23171#false} assume !(0 == ~E_7~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 30: Hoare triple {23171#false} assume !(0 == ~E_8~0); {23171#false} is VALID [2022-02-21 04:24:22,291 INFO L290 TraceCheckUtils]: 31: Hoare triple {23171#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 32: Hoare triple {23171#false} assume !(1 == ~m_pc~0); {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 33: Hoare triple {23171#false} is_master_triggered_~__retres1~0#1 := 0; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 34: Hoare triple {23171#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 35: Hoare triple {23171#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 36: Hoare triple {23171#false} assume !(0 != activate_threads_~tmp~1#1); {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 37: Hoare triple {23171#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 38: Hoare triple {23171#false} assume 1 == ~t1_pc~0; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 39: Hoare triple {23171#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 40: Hoare triple {23171#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 41: Hoare triple {23171#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 42: Hoare triple {23171#false} assume !(0 != activate_threads_~tmp___0~0#1); {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 43: Hoare triple {23171#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 44: Hoare triple {23171#false} assume 1 == ~t2_pc~0; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 45: Hoare triple {23171#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 46: Hoare triple {23171#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 47: Hoare triple {23171#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 48: Hoare triple {23171#false} assume !(0 != activate_threads_~tmp___1~0#1); {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 49: Hoare triple {23171#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23171#false} is VALID [2022-02-21 04:24:22,292 INFO L290 TraceCheckUtils]: 50: Hoare triple {23171#false} assume !(1 == ~t3_pc~0); {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 51: Hoare triple {23171#false} is_transmit3_triggered_~__retres1~3#1 := 0; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 52: Hoare triple {23171#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 53: Hoare triple {23171#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 54: Hoare triple {23171#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 55: Hoare triple {23171#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 56: Hoare triple {23171#false} assume 1 == ~t4_pc~0; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 57: Hoare triple {23171#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 58: Hoare triple {23171#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 59: Hoare triple {23171#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 60: Hoare triple {23171#false} assume !(0 != activate_threads_~tmp___3~0#1); {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 61: Hoare triple {23171#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 62: Hoare triple {23171#false} assume !(1 == ~t5_pc~0); {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 63: Hoare triple {23171#false} is_transmit5_triggered_~__retres1~5#1 := 0; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 64: Hoare triple {23171#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 65: Hoare triple {23171#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 66: Hoare triple {23171#false} assume !(0 != activate_threads_~tmp___4~0#1); {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 67: Hoare triple {23171#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23171#false} is VALID [2022-02-21 04:24:22,293 INFO L290 TraceCheckUtils]: 68: Hoare triple {23171#false} assume 1 == ~t6_pc~0; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 69: Hoare triple {23171#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 70: Hoare triple {23171#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 71: Hoare triple {23171#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 72: Hoare triple {23171#false} assume !(0 != activate_threads_~tmp___5~0#1); {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 73: Hoare triple {23171#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 74: Hoare triple {23171#false} assume !(1 == ~t7_pc~0); {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 75: Hoare triple {23171#false} is_transmit7_triggered_~__retres1~7#1 := 0; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 76: Hoare triple {23171#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 77: Hoare triple {23171#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 78: Hoare triple {23171#false} assume !(0 != activate_threads_~tmp___6~0#1); {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 79: Hoare triple {23171#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 80: Hoare triple {23171#false} assume 1 == ~t8_pc~0; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 81: Hoare triple {23171#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 82: Hoare triple {23171#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 83: Hoare triple {23171#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 84: Hoare triple {23171#false} assume !(0 != activate_threads_~tmp___7~0#1); {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 85: Hoare triple {23171#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23171#false} is VALID [2022-02-21 04:24:22,294 INFO L290 TraceCheckUtils]: 86: Hoare triple {23171#false} assume !(1 == ~M_E~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 87: Hoare triple {23171#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 88: Hoare triple {23171#false} assume !(1 == ~T2_E~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 89: Hoare triple {23171#false} assume !(1 == ~T3_E~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 90: Hoare triple {23171#false} assume !(1 == ~T4_E~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 91: Hoare triple {23171#false} assume !(1 == ~T5_E~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 92: Hoare triple {23171#false} assume !(1 == ~T6_E~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 93: Hoare triple {23171#false} assume !(1 == ~T7_E~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 94: Hoare triple {23171#false} assume !(1 == ~T8_E~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 95: Hoare triple {23171#false} assume 1 == ~E_1~0;~E_1~0 := 2; {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 96: Hoare triple {23171#false} assume !(1 == ~E_2~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 97: Hoare triple {23171#false} assume !(1 == ~E_3~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 98: Hoare triple {23171#false} assume !(1 == ~E_4~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 99: Hoare triple {23171#false} assume !(1 == ~E_5~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 100: Hoare triple {23171#false} assume !(1 == ~E_6~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 101: Hoare triple {23171#false} assume !(1 == ~E_7~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 102: Hoare triple {23171#false} assume !(1 == ~E_8~0); {23171#false} is VALID [2022-02-21 04:24:22,295 INFO L290 TraceCheckUtils]: 103: Hoare triple {23171#false} assume { :end_inline_reset_delta_events } true; {23171#false} is VALID [2022-02-21 04:24:22,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:22,296 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:22,296 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296289357] [2022-02-21 04:24:22,296 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1296289357] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:22,296 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:22,296 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:22,296 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893767516] [2022-02-21 04:24:22,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:22,296 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:22,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:22,297 INFO L85 PathProgramCache]: Analyzing trace with hash 539629054, now seen corresponding path program 1 times [2022-02-21 04:24:22,297 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:22,297 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336529739] [2022-02-21 04:24:22,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:22,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:22,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 0: Hoare triple {23173#true} assume !false; {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 1: Hoare triple {23173#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 2: Hoare triple {23173#true} assume !false; {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 3: Hoare triple {23173#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 4: Hoare triple {23173#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 5: Hoare triple {23173#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 6: Hoare triple {23173#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 7: Hoare triple {23173#true} assume !(0 != eval_~tmp~0#1); {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 8: Hoare triple {23173#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 9: Hoare triple {23173#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 10: Hoare triple {23173#true} assume !(0 == ~M_E~0); {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 11: Hoare triple {23173#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 12: Hoare triple {23173#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {23173#true} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 13: Hoare triple {23173#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {23173#true} is VALID [2022-02-21 04:24:22,325 INFO L290 TraceCheckUtils]: 14: Hoare triple {23173#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,325 INFO L290 TraceCheckUtils]: 15: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,325 INFO L290 TraceCheckUtils]: 16: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,325 INFO L290 TraceCheckUtils]: 17: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,326 INFO L290 TraceCheckUtils]: 18: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,326 INFO L290 TraceCheckUtils]: 19: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,326 INFO L290 TraceCheckUtils]: 20: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,326 INFO L290 TraceCheckUtils]: 21: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,326 INFO L290 TraceCheckUtils]: 22: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,351 INFO L290 TraceCheckUtils]: 23: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,352 INFO L290 TraceCheckUtils]: 24: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,352 INFO L290 TraceCheckUtils]: 25: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,352 INFO L290 TraceCheckUtils]: 26: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,353 INFO L290 TraceCheckUtils]: 27: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,353 INFO L290 TraceCheckUtils]: 28: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~m_pc~0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,353 INFO L290 TraceCheckUtils]: 29: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,353 INFO L290 TraceCheckUtils]: 30: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,354 INFO L290 TraceCheckUtils]: 31: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,354 INFO L290 TraceCheckUtils]: 32: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,354 INFO L290 TraceCheckUtils]: 33: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,354 INFO L290 TraceCheckUtils]: 34: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t1_pc~0); {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,355 INFO L290 TraceCheckUtils]: 35: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,355 INFO L290 TraceCheckUtils]: 36: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,355 INFO L290 TraceCheckUtils]: 37: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,356 INFO L290 TraceCheckUtils]: 38: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,356 INFO L290 TraceCheckUtils]: 39: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,356 INFO L290 TraceCheckUtils]: 40: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t2_pc~0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,356 INFO L290 TraceCheckUtils]: 41: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,357 INFO L290 TraceCheckUtils]: 42: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,357 INFO L290 TraceCheckUtils]: 43: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,357 INFO L290 TraceCheckUtils]: 44: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,357 INFO L290 TraceCheckUtils]: 45: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,358 INFO L290 TraceCheckUtils]: 46: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t3_pc~0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,358 INFO L290 TraceCheckUtils]: 47: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,358 INFO L290 TraceCheckUtils]: 48: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,358 INFO L290 TraceCheckUtils]: 49: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,359 INFO L290 TraceCheckUtils]: 50: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,359 INFO L290 TraceCheckUtils]: 51: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,359 INFO L290 TraceCheckUtils]: 52: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t4_pc~0); {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,359 INFO L290 TraceCheckUtils]: 53: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,360 INFO L290 TraceCheckUtils]: 54: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,360 INFO L290 TraceCheckUtils]: 55: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,360 INFO L290 TraceCheckUtils]: 56: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,360 INFO L290 TraceCheckUtils]: 57: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,361 INFO L290 TraceCheckUtils]: 58: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t5_pc~0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,361 INFO L290 TraceCheckUtils]: 59: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,361 INFO L290 TraceCheckUtils]: 60: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,362 INFO L290 TraceCheckUtils]: 61: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,362 INFO L290 TraceCheckUtils]: 62: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,362 INFO L290 TraceCheckUtils]: 63: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,362 INFO L290 TraceCheckUtils]: 64: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t6_pc~0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,363 INFO L290 TraceCheckUtils]: 65: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,363 INFO L290 TraceCheckUtils]: 66: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,363 INFO L290 TraceCheckUtils]: 67: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,363 INFO L290 TraceCheckUtils]: 68: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,364 INFO L290 TraceCheckUtils]: 69: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,364 INFO L290 TraceCheckUtils]: 70: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t7_pc~0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,364 INFO L290 TraceCheckUtils]: 71: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,364 INFO L290 TraceCheckUtils]: 72: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,365 INFO L290 TraceCheckUtils]: 73: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,365 INFO L290 TraceCheckUtils]: 74: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,365 INFO L290 TraceCheckUtils]: 75: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,365 INFO L290 TraceCheckUtils]: 76: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t8_pc~0); {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,366 INFO L290 TraceCheckUtils]: 77: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,366 INFO L290 TraceCheckUtils]: 78: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,366 INFO L290 TraceCheckUtils]: 79: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,366 INFO L290 TraceCheckUtils]: 80: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,367 INFO L290 TraceCheckUtils]: 81: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,367 INFO L290 TraceCheckUtils]: 82: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,367 INFO L290 TraceCheckUtils]: 83: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,368 INFO L290 TraceCheckUtils]: 84: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,368 INFO L290 TraceCheckUtils]: 85: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {23175#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:22,368 INFO L290 TraceCheckUtils]: 86: Hoare triple {23175#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {23174#false} is VALID [2022-02-21 04:24:22,368 INFO L290 TraceCheckUtils]: 87: Hoare triple {23174#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {23174#false} is VALID [2022-02-21 04:24:22,368 INFO L290 TraceCheckUtils]: 88: Hoare triple {23174#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {23174#false} is VALID [2022-02-21 04:24:22,368 INFO L290 TraceCheckUtils]: 89: Hoare triple {23174#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {23174#false} is VALID [2022-02-21 04:24:22,368 INFO L290 TraceCheckUtils]: 90: Hoare triple {23174#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {23174#false} is VALID [2022-02-21 04:24:22,368 INFO L290 TraceCheckUtils]: 91: Hoare triple {23174#false} assume 1 == ~E_1~0;~E_1~0 := 2; {23174#false} is VALID [2022-02-21 04:24:22,368 INFO L290 TraceCheckUtils]: 92: Hoare triple {23174#false} assume 1 == ~E_2~0;~E_2~0 := 2; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 93: Hoare triple {23174#false} assume 1 == ~E_3~0;~E_3~0 := 2; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 94: Hoare triple {23174#false} assume !(1 == ~E_4~0); {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 95: Hoare triple {23174#false} assume 1 == ~E_5~0;~E_5~0 := 2; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 96: Hoare triple {23174#false} assume 1 == ~E_6~0;~E_6~0 := 2; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 97: Hoare triple {23174#false} assume 1 == ~E_7~0;~E_7~0 := 2; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 98: Hoare triple {23174#false} assume 1 == ~E_8~0;~E_8~0 := 2; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 99: Hoare triple {23174#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 100: Hoare triple {23174#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 101: Hoare triple {23174#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 102: Hoare triple {23174#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 103: Hoare triple {23174#false} assume !(0 == start_simulation_~tmp~3#1); {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 104: Hoare triple {23174#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 105: Hoare triple {23174#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 106: Hoare triple {23174#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 107: Hoare triple {23174#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 108: Hoare triple {23174#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 109: Hoare triple {23174#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 110: Hoare triple {23174#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {23174#false} is VALID [2022-02-21 04:24:22,369 INFO L290 TraceCheckUtils]: 111: Hoare triple {23174#false} assume !(0 != start_simulation_~tmp___0~1#1); {23174#false} is VALID [2022-02-21 04:24:22,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:22,370 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:22,370 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1336529739] [2022-02-21 04:24:22,370 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1336529739] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:22,370 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:22,370 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:22,370 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44902539] [2022-02-21 04:24:22,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:22,371 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:22,371 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:22,371 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:22,371 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:22,371 INFO L87 Difference]: Start difference. First operand 924 states and 1374 transitions. cyclomatic complexity: 451 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,950 INFO L93 Difference]: Finished difference Result 924 states and 1373 transitions. [2022-02-21 04:24:22,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:22,950 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,016 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:23,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1373 transitions. [2022-02-21 04:24:23,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:23,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1373 transitions. [2022-02-21 04:24:23,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-02-21 04:24:23,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-02-21 04:24:23,059 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1373 transitions. [2022-02-21 04:24:23,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:23,060 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1373 transitions. [2022-02-21 04:24:23,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1373 transitions. [2022-02-21 04:24:23,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-02-21 04:24:23,068 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:23,069 INFO L82 GeneralOperation]: Start isEquivalent. First operand 924 states and 1373 transitions. Second operand has 924 states, 924 states have (on average 1.4859307359307359) internal successors, (1373), 923 states have internal predecessors, (1373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,070 INFO L74 IsIncluded]: Start isIncluded. First operand 924 states and 1373 transitions. Second operand has 924 states, 924 states have (on average 1.4859307359307359) internal successors, (1373), 923 states have internal predecessors, (1373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,070 INFO L87 Difference]: Start difference. First operand 924 states and 1373 transitions. Second operand has 924 states, 924 states have (on average 1.4859307359307359) internal successors, (1373), 923 states have internal predecessors, (1373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,090 INFO L93 Difference]: Finished difference Result 924 states and 1373 transitions. [2022-02-21 04:24:23,090 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1373 transitions. [2022-02-21 04:24:23,093 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:23,093 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:23,094 INFO L74 IsIncluded]: Start isIncluded. First operand has 924 states, 924 states have (on average 1.4859307359307359) internal successors, (1373), 923 states have internal predecessors, (1373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1373 transitions. [2022-02-21 04:24:23,095 INFO L87 Difference]: Start difference. First operand has 924 states, 924 states have (on average 1.4859307359307359) internal successors, (1373), 923 states have internal predecessors, (1373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1373 transitions. [2022-02-21 04:24:23,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,115 INFO L93 Difference]: Finished difference Result 924 states and 1373 transitions. [2022-02-21 04:24:23,115 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1373 transitions. [2022-02-21 04:24:23,116 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:23,116 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:23,116 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:23,116 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:23,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4859307359307359) internal successors, (1373), 923 states have internal predecessors, (1373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1373 transitions. [2022-02-21 04:24:23,136 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1373 transitions. [2022-02-21 04:24:23,136 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1373 transitions. [2022-02-21 04:24:23,136 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:23,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1373 transitions. [2022-02-21 04:24:23,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:23,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:23,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:23,140 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,140 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,140 INFO L791 eck$LassoCheckResult]: Stem: 24776#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 24777#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25019#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24191#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24192#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 24463#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24464#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24961#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24951#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24531#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24532#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24756#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24757#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24613#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24614#L838 assume !(0 == ~M_E~0); 24763#L838-2 assume !(0 == ~T1_E~0); 24153#L843-1 assume !(0 == ~T2_E~0); 24154#L848-1 assume !(0 == ~T3_E~0); 24273#L853-1 assume !(0 == ~T4_E~0); 24599#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24100#L863-1 assume !(0 == ~T6_E~0); 24101#L868-1 assume !(0 == ~T7_E~0); 24993#L873-1 assume !(0 == ~T8_E~0); 24991#L878-1 assume !(0 == ~E_1~0); 24980#L883-1 assume !(0 == ~E_2~0); 24981#L888-1 assume !(0 == ~E_3~0); 24728#L893-1 assume !(0 == ~E_4~0); 24729#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 25005#L903-1 assume !(0 == ~E_6~0); 24979#L908-1 assume !(0 == ~E_7~0); 24853#L913-1 assume !(0 == ~E_8~0); 24167#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24168#L402 assume !(1 == ~m_pc~0); 24376#L402-2 is_master_triggered_~__retres1~0#1 := 0; 24294#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24295#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24537#L1035 assume !(0 != activate_threads_~tmp~1#1); 24538#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24590#L421 assume 1 == ~t1_pc~0; 24975#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24994#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24582#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24583#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 24641#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25002#L440 assume 1 == ~t2_pc~0; 24137#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24138#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24304#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25013#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 24867#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24491#L459 assume !(1 == ~t3_pc~0); 24492#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 24974#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24798#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24288#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24289#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24298#L478 assume 1 == ~t4_pc~0; 24299#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24733#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24960#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24469#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 24212#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24213#L497 assume !(1 == ~t5_pc~0); 24259#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24260#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24551#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24552#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 24967#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24968#L516 assume 1 == ~t6_pc~0; 25022#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24754#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24755#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24343#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 24344#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24745#L535 assume !(1 == ~t7_pc~0); 24746#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24815#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24816#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24844#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 24834#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24835#L554 assume 1 == ~t8_pc~0; 24784#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24129#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24885#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24431#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 24432#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24113#L931 assume !(1 == ~M_E~0); 24114#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24988#L936-1 assume !(1 == ~T2_E~0); 25011#L941-1 assume !(1 == ~T3_E~0); 24591#L946-1 assume !(1 == ~T4_E~0); 24592#L951-1 assume !(1 == ~T5_E~0); 24358#L956-1 assume !(1 == ~T6_E~0); 24359#L961-1 assume !(1 == ~T7_E~0); 24730#L966-1 assume !(1 == ~T8_E~0); 24731#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 24837#L976-1 assume !(1 == ~E_2~0); 24807#L981-1 assume !(1 == ~E_3~0); 24596#L986-1 assume !(1 == ~E_4~0); 24388#L991-1 assume !(1 == ~E_5~0); 24389#L996-1 assume !(1 == ~E_6~0); 24998#L1001-1 assume !(1 == ~E_7~0); 24774#L1006-1 assume !(1 == ~E_8~0); 24775#L1011-1 assume { :end_inline_reset_delta_events } true; 24176#L1272-2 [2022-02-21 04:24:23,140 INFO L793 eck$LassoCheckResult]: Loop: 24176#L1272-2 assume !false; 24177#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24178#L813 assume !false; 24179#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 24925#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 24181#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24725#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24735#L696 assume !(0 != eval_~tmp~0#1); 24778#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24779#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24900#L838-3 assume !(0 == ~M_E~0); 24820#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24821#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24683#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24684#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24732#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24795#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24787#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24788#L873-3 assume !(0 == ~T8_E~0); 24411#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24140#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24141#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24142#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24143#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24617#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24926#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24630#L913-3 assume !(0 == ~E_8~0); 24183#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24184#L402-27 assume 1 == ~m_pc~0; 24130#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24131#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24620#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24621#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24939#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24940#L421-27 assume !(1 == ~t1_pc~0); 24403#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 24404#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24653#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24654#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24999#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24748#L440-27 assume 1 == ~t2_pc~0; 24749#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24922#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24487#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24488#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24662#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24391#L459-27 assume !(1 == ~t3_pc~0); 24392#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 24810#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24455#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24456#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24744#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24992#L478-27 assume 1 == ~t4_pc~0; 25014#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24382#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24758#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24890#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24891#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24927#L497-27 assume 1 == ~t5_pc~0; 24928#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24420#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24421#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24364#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24365#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24622#L516-27 assume !(1 == ~t6_pc~0); 24624#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 24477#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24478#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24625#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24765#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24554#L535-27 assume 1 == ~t7_pc~0; 24555#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24871#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24901#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24902#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24508#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24509#L554-27 assume 1 == ~t8_pc~0; 24705#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24158#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24303#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24642#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 24408#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24409#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24284#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24285#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24505#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24637#L946-3 assume !(1 == ~T4_E~0); 24426#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24427#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24706#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24515#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24516#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24753#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24174#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24175#L986-3 assume !(1 == ~E_4~0); 24165#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24166#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24825#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24496#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24497#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 24207#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 24209#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24523#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 24524#L1291 assume !(0 == start_simulation_~tmp~3#1); 24703#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 24609#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 24104#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24105#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 24909#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24573#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24574#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 24790#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 24176#L1272-2 [2022-02-21 04:24:23,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:23,141 INFO L85 PathProgramCache]: Analyzing trace with hash -1281590756, now seen corresponding path program 1 times [2022-02-21 04:24:23,141 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:23,141 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [869491098] [2022-02-21 04:24:23,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:23,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:23,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:23,165 INFO L290 TraceCheckUtils]: 0: Hoare triple {26875#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {26875#true} is VALID [2022-02-21 04:24:23,166 INFO L290 TraceCheckUtils]: 1: Hoare triple {26875#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {26877#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:23,166 INFO L290 TraceCheckUtils]: 2: Hoare triple {26877#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {26877#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:23,166 INFO L290 TraceCheckUtils]: 3: Hoare triple {26877#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {26877#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:23,166 INFO L290 TraceCheckUtils]: 4: Hoare triple {26877#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {26877#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:23,167 INFO L290 TraceCheckUtils]: 5: Hoare triple {26877#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {26877#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:23,167 INFO L290 TraceCheckUtils]: 6: Hoare triple {26877#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {26877#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:23,167 INFO L290 TraceCheckUtils]: 7: Hoare triple {26877#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {26877#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:23,167 INFO L290 TraceCheckUtils]: 8: Hoare triple {26877#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {26877#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:23,167 INFO L290 TraceCheckUtils]: 9: Hoare triple {26877#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {26877#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:23,168 INFO L290 TraceCheckUtils]: 10: Hoare triple {26877#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {26877#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:23,168 INFO L290 TraceCheckUtils]: 11: Hoare triple {26877#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {26877#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:23,168 INFO L290 TraceCheckUtils]: 12: Hoare triple {26877#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {26876#false} is VALID [2022-02-21 04:24:23,168 INFO L290 TraceCheckUtils]: 13: Hoare triple {26876#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {26876#false} is VALID [2022-02-21 04:24:23,168 INFO L290 TraceCheckUtils]: 14: Hoare triple {26876#false} assume !(0 == ~M_E~0); {26876#false} is VALID [2022-02-21 04:24:23,168 INFO L290 TraceCheckUtils]: 15: Hoare triple {26876#false} assume !(0 == ~T1_E~0); {26876#false} is VALID [2022-02-21 04:24:23,168 INFO L290 TraceCheckUtils]: 16: Hoare triple {26876#false} assume !(0 == ~T2_E~0); {26876#false} is VALID [2022-02-21 04:24:23,168 INFO L290 TraceCheckUtils]: 17: Hoare triple {26876#false} assume !(0 == ~T3_E~0); {26876#false} is VALID [2022-02-21 04:24:23,168 INFO L290 TraceCheckUtils]: 18: Hoare triple {26876#false} assume !(0 == ~T4_E~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 19: Hoare triple {26876#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 20: Hoare triple {26876#false} assume !(0 == ~T6_E~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 21: Hoare triple {26876#false} assume !(0 == ~T7_E~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 22: Hoare triple {26876#false} assume !(0 == ~T8_E~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 23: Hoare triple {26876#false} assume !(0 == ~E_1~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 24: Hoare triple {26876#false} assume !(0 == ~E_2~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 25: Hoare triple {26876#false} assume !(0 == ~E_3~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 26: Hoare triple {26876#false} assume !(0 == ~E_4~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 27: Hoare triple {26876#false} assume 0 == ~E_5~0;~E_5~0 := 1; {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 28: Hoare triple {26876#false} assume !(0 == ~E_6~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 29: Hoare triple {26876#false} assume !(0 == ~E_7~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 30: Hoare triple {26876#false} assume !(0 == ~E_8~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 31: Hoare triple {26876#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 32: Hoare triple {26876#false} assume !(1 == ~m_pc~0); {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 33: Hoare triple {26876#false} is_master_triggered_~__retres1~0#1 := 0; {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 34: Hoare triple {26876#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 35: Hoare triple {26876#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {26876#false} is VALID [2022-02-21 04:24:23,169 INFO L290 TraceCheckUtils]: 36: Hoare triple {26876#false} assume !(0 != activate_threads_~tmp~1#1); {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 37: Hoare triple {26876#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 38: Hoare triple {26876#false} assume 1 == ~t1_pc~0; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 39: Hoare triple {26876#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 40: Hoare triple {26876#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 41: Hoare triple {26876#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 42: Hoare triple {26876#false} assume !(0 != activate_threads_~tmp___0~0#1); {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 43: Hoare triple {26876#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 44: Hoare triple {26876#false} assume 1 == ~t2_pc~0; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 45: Hoare triple {26876#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 46: Hoare triple {26876#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 47: Hoare triple {26876#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 48: Hoare triple {26876#false} assume !(0 != activate_threads_~tmp___1~0#1); {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 49: Hoare triple {26876#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 50: Hoare triple {26876#false} assume !(1 == ~t3_pc~0); {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 51: Hoare triple {26876#false} is_transmit3_triggered_~__retres1~3#1 := 0; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 52: Hoare triple {26876#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 53: Hoare triple {26876#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 54: Hoare triple {26876#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26876#false} is VALID [2022-02-21 04:24:23,170 INFO L290 TraceCheckUtils]: 55: Hoare triple {26876#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 56: Hoare triple {26876#false} assume 1 == ~t4_pc~0; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 57: Hoare triple {26876#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 58: Hoare triple {26876#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 59: Hoare triple {26876#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 60: Hoare triple {26876#false} assume !(0 != activate_threads_~tmp___3~0#1); {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 61: Hoare triple {26876#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 62: Hoare triple {26876#false} assume !(1 == ~t5_pc~0); {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 63: Hoare triple {26876#false} is_transmit5_triggered_~__retres1~5#1 := 0; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 64: Hoare triple {26876#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 65: Hoare triple {26876#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 66: Hoare triple {26876#false} assume !(0 != activate_threads_~tmp___4~0#1); {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 67: Hoare triple {26876#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 68: Hoare triple {26876#false} assume 1 == ~t6_pc~0; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 69: Hoare triple {26876#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 70: Hoare triple {26876#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 71: Hoare triple {26876#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 72: Hoare triple {26876#false} assume !(0 != activate_threads_~tmp___5~0#1); {26876#false} is VALID [2022-02-21 04:24:23,171 INFO L290 TraceCheckUtils]: 73: Hoare triple {26876#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 74: Hoare triple {26876#false} assume !(1 == ~t7_pc~0); {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 75: Hoare triple {26876#false} is_transmit7_triggered_~__retres1~7#1 := 0; {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 76: Hoare triple {26876#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 77: Hoare triple {26876#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 78: Hoare triple {26876#false} assume !(0 != activate_threads_~tmp___6~0#1); {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 79: Hoare triple {26876#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 80: Hoare triple {26876#false} assume 1 == ~t8_pc~0; {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 81: Hoare triple {26876#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 82: Hoare triple {26876#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 83: Hoare triple {26876#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 84: Hoare triple {26876#false} assume !(0 != activate_threads_~tmp___7~0#1); {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 85: Hoare triple {26876#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 86: Hoare triple {26876#false} assume !(1 == ~M_E~0); {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 87: Hoare triple {26876#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 88: Hoare triple {26876#false} assume !(1 == ~T2_E~0); {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 89: Hoare triple {26876#false} assume !(1 == ~T3_E~0); {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 90: Hoare triple {26876#false} assume !(1 == ~T4_E~0); {26876#false} is VALID [2022-02-21 04:24:23,172 INFO L290 TraceCheckUtils]: 91: Hoare triple {26876#false} assume !(1 == ~T5_E~0); {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 92: Hoare triple {26876#false} assume !(1 == ~T6_E~0); {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 93: Hoare triple {26876#false} assume !(1 == ~T7_E~0); {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 94: Hoare triple {26876#false} assume !(1 == ~T8_E~0); {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 95: Hoare triple {26876#false} assume 1 == ~E_1~0;~E_1~0 := 2; {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 96: Hoare triple {26876#false} assume !(1 == ~E_2~0); {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 97: Hoare triple {26876#false} assume !(1 == ~E_3~0); {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 98: Hoare triple {26876#false} assume !(1 == ~E_4~0); {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 99: Hoare triple {26876#false} assume !(1 == ~E_5~0); {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 100: Hoare triple {26876#false} assume !(1 == ~E_6~0); {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 101: Hoare triple {26876#false} assume !(1 == ~E_7~0); {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 102: Hoare triple {26876#false} assume !(1 == ~E_8~0); {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L290 TraceCheckUtils]: 103: Hoare triple {26876#false} assume { :end_inline_reset_delta_events } true; {26876#false} is VALID [2022-02-21 04:24:23,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:23,173 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:23,174 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [869491098] [2022-02-21 04:24:23,174 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [869491098] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:23,175 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:23,175 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:23,175 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595092190] [2022-02-21 04:24:23,175 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:23,175 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:23,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:23,175 INFO L85 PathProgramCache]: Analyzing trace with hash 170822718, now seen corresponding path program 1 times [2022-02-21 04:24:23,175 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:23,178 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762970835] [2022-02-21 04:24:23,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:23,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:23,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:23,232 INFO L290 TraceCheckUtils]: 0: Hoare triple {26878#true} assume !false; {26878#true} is VALID [2022-02-21 04:24:23,232 INFO L290 TraceCheckUtils]: 1: Hoare triple {26878#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {26878#true} is VALID [2022-02-21 04:24:23,232 INFO L290 TraceCheckUtils]: 2: Hoare triple {26878#true} assume !false; {26878#true} is VALID [2022-02-21 04:24:23,232 INFO L290 TraceCheckUtils]: 3: Hoare triple {26878#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {26878#true} is VALID [2022-02-21 04:24:23,232 INFO L290 TraceCheckUtils]: 4: Hoare triple {26878#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {26878#true} is VALID [2022-02-21 04:24:23,232 INFO L290 TraceCheckUtils]: 5: Hoare triple {26878#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {26878#true} is VALID [2022-02-21 04:24:23,232 INFO L290 TraceCheckUtils]: 6: Hoare triple {26878#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {26878#true} is VALID [2022-02-21 04:24:23,232 INFO L290 TraceCheckUtils]: 7: Hoare triple {26878#true} assume !(0 != eval_~tmp~0#1); {26878#true} is VALID [2022-02-21 04:24:23,232 INFO L290 TraceCheckUtils]: 8: Hoare triple {26878#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {26878#true} is VALID [2022-02-21 04:24:23,232 INFO L290 TraceCheckUtils]: 9: Hoare triple {26878#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {26878#true} is VALID [2022-02-21 04:24:23,232 INFO L290 TraceCheckUtils]: 10: Hoare triple {26878#true} assume !(0 == ~M_E~0); {26878#true} is VALID [2022-02-21 04:24:23,233 INFO L290 TraceCheckUtils]: 11: Hoare triple {26878#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {26878#true} is VALID [2022-02-21 04:24:23,233 INFO L290 TraceCheckUtils]: 12: Hoare triple {26878#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {26878#true} is VALID [2022-02-21 04:24:23,233 INFO L290 TraceCheckUtils]: 13: Hoare triple {26878#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {26878#true} is VALID [2022-02-21 04:24:23,233 INFO L290 TraceCheckUtils]: 14: Hoare triple {26878#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,233 INFO L290 TraceCheckUtils]: 15: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,233 INFO L290 TraceCheckUtils]: 16: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,234 INFO L290 TraceCheckUtils]: 17: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,234 INFO L290 TraceCheckUtils]: 18: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,234 INFO L290 TraceCheckUtils]: 19: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,235 INFO L290 TraceCheckUtils]: 20: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,235 INFO L290 TraceCheckUtils]: 21: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,235 INFO L290 TraceCheckUtils]: 22: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,235 INFO L290 TraceCheckUtils]: 23: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,236 INFO L290 TraceCheckUtils]: 24: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,236 INFO L290 TraceCheckUtils]: 25: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,236 INFO L290 TraceCheckUtils]: 26: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,236 INFO L290 TraceCheckUtils]: 27: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,237 INFO L290 TraceCheckUtils]: 28: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~m_pc~0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,237 INFO L290 TraceCheckUtils]: 29: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,237 INFO L290 TraceCheckUtils]: 30: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,237 INFO L290 TraceCheckUtils]: 31: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,238 INFO L290 TraceCheckUtils]: 32: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,238 INFO L290 TraceCheckUtils]: 33: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,238 INFO L290 TraceCheckUtils]: 34: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t1_pc~0); {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,238 INFO L290 TraceCheckUtils]: 35: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,239 INFO L290 TraceCheckUtils]: 36: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,239 INFO L290 TraceCheckUtils]: 37: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,239 INFO L290 TraceCheckUtils]: 38: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,240 INFO L290 TraceCheckUtils]: 39: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,240 INFO L290 TraceCheckUtils]: 40: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t2_pc~0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,240 INFO L290 TraceCheckUtils]: 41: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,240 INFO L290 TraceCheckUtils]: 42: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,241 INFO L290 TraceCheckUtils]: 43: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,241 INFO L290 TraceCheckUtils]: 44: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,241 INFO L290 TraceCheckUtils]: 45: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,241 INFO L290 TraceCheckUtils]: 46: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t3_pc~0); {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,242 INFO L290 TraceCheckUtils]: 47: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,242 INFO L290 TraceCheckUtils]: 48: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,242 INFO L290 TraceCheckUtils]: 49: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,242 INFO L290 TraceCheckUtils]: 50: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,243 INFO L290 TraceCheckUtils]: 51: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,243 INFO L290 TraceCheckUtils]: 52: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t4_pc~0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,243 INFO L290 TraceCheckUtils]: 53: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,243 INFO L290 TraceCheckUtils]: 54: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,244 INFO L290 TraceCheckUtils]: 55: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,244 INFO L290 TraceCheckUtils]: 56: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,244 INFO L290 TraceCheckUtils]: 57: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,245 INFO L290 TraceCheckUtils]: 58: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t5_pc~0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,245 INFO L290 TraceCheckUtils]: 59: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,245 INFO L290 TraceCheckUtils]: 60: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,245 INFO L290 TraceCheckUtils]: 61: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,246 INFO L290 TraceCheckUtils]: 62: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,246 INFO L290 TraceCheckUtils]: 63: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,246 INFO L290 TraceCheckUtils]: 64: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t6_pc~0); {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,246 INFO L290 TraceCheckUtils]: 65: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,247 INFO L290 TraceCheckUtils]: 66: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,247 INFO L290 TraceCheckUtils]: 67: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,247 INFO L290 TraceCheckUtils]: 68: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,247 INFO L290 TraceCheckUtils]: 69: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,248 INFO L290 TraceCheckUtils]: 70: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t7_pc~0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,248 INFO L290 TraceCheckUtils]: 71: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,248 INFO L290 TraceCheckUtils]: 72: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,248 INFO L290 TraceCheckUtils]: 73: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,249 INFO L290 TraceCheckUtils]: 74: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,249 INFO L290 TraceCheckUtils]: 75: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,249 INFO L290 TraceCheckUtils]: 76: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t8_pc~0; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,250 INFO L290 TraceCheckUtils]: 77: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,250 INFO L290 TraceCheckUtils]: 78: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,250 INFO L290 TraceCheckUtils]: 79: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,250 INFO L290 TraceCheckUtils]: 80: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,251 INFO L290 TraceCheckUtils]: 81: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,251 INFO L290 TraceCheckUtils]: 82: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,251 INFO L290 TraceCheckUtils]: 83: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,251 INFO L290 TraceCheckUtils]: 84: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,252 INFO L290 TraceCheckUtils]: 85: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26880#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:23,252 INFO L290 TraceCheckUtils]: 86: Hoare triple {26880#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {26879#false} is VALID [2022-02-21 04:24:23,252 INFO L290 TraceCheckUtils]: 87: Hoare triple {26879#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {26879#false} is VALID [2022-02-21 04:24:23,252 INFO L290 TraceCheckUtils]: 88: Hoare triple {26879#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {26879#false} is VALID [2022-02-21 04:24:23,252 INFO L290 TraceCheckUtils]: 89: Hoare triple {26879#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {26879#false} is VALID [2022-02-21 04:24:23,252 INFO L290 TraceCheckUtils]: 90: Hoare triple {26879#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {26879#false} is VALID [2022-02-21 04:24:23,252 INFO L290 TraceCheckUtils]: 91: Hoare triple {26879#false} assume 1 == ~E_1~0;~E_1~0 := 2; {26879#false} is VALID [2022-02-21 04:24:23,252 INFO L290 TraceCheckUtils]: 92: Hoare triple {26879#false} assume 1 == ~E_2~0;~E_2~0 := 2; {26879#false} is VALID [2022-02-21 04:24:23,252 INFO L290 TraceCheckUtils]: 93: Hoare triple {26879#false} assume 1 == ~E_3~0;~E_3~0 := 2; {26879#false} is VALID [2022-02-21 04:24:23,252 INFO L290 TraceCheckUtils]: 94: Hoare triple {26879#false} assume !(1 == ~E_4~0); {26879#false} is VALID [2022-02-21 04:24:23,252 INFO L290 TraceCheckUtils]: 95: Hoare triple {26879#false} assume 1 == ~E_5~0;~E_5~0 := 2; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 96: Hoare triple {26879#false} assume 1 == ~E_6~0;~E_6~0 := 2; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 97: Hoare triple {26879#false} assume 1 == ~E_7~0;~E_7~0 := 2; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 98: Hoare triple {26879#false} assume 1 == ~E_8~0;~E_8~0 := 2; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 99: Hoare triple {26879#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 100: Hoare triple {26879#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 101: Hoare triple {26879#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 102: Hoare triple {26879#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 103: Hoare triple {26879#false} assume !(0 == start_simulation_~tmp~3#1); {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 104: Hoare triple {26879#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 105: Hoare triple {26879#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 106: Hoare triple {26879#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 107: Hoare triple {26879#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 108: Hoare triple {26879#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 109: Hoare triple {26879#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 110: Hoare triple {26879#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {26879#false} is VALID [2022-02-21 04:24:23,253 INFO L290 TraceCheckUtils]: 111: Hoare triple {26879#false} assume !(0 != start_simulation_~tmp___0~1#1); {26879#false} is VALID [2022-02-21 04:24:23,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:23,254 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:23,254 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762970835] [2022-02-21 04:24:23,254 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1762970835] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:23,254 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:23,254 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:23,254 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [952516726] [2022-02-21 04:24:23,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:23,254 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:23,254 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:23,255 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:23,255 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:23,255 INFO L87 Difference]: Start difference. First operand 924 states and 1373 transitions. cyclomatic complexity: 450 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,856 INFO L93 Difference]: Finished difference Result 924 states and 1372 transitions. [2022-02-21 04:24:23,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:23,856 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,911 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:23,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1372 transitions. [2022-02-21 04:24:23,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:23,954 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1372 transitions. [2022-02-21 04:24:23,955 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-02-21 04:24:23,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-02-21 04:24:23,955 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1372 transitions. [2022-02-21 04:24:23,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:23,956 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1372 transitions. [2022-02-21 04:24:23,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1372 transitions. [2022-02-21 04:24:23,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-02-21 04:24:23,964 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:23,966 INFO L82 GeneralOperation]: Start isEquivalent. First operand 924 states and 1372 transitions. Second operand has 924 states, 924 states have (on average 1.4848484848484849) internal successors, (1372), 923 states have internal predecessors, (1372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,966 INFO L74 IsIncluded]: Start isIncluded. First operand 924 states and 1372 transitions. Second operand has 924 states, 924 states have (on average 1.4848484848484849) internal successors, (1372), 923 states have internal predecessors, (1372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,967 INFO L87 Difference]: Start difference. First operand 924 states and 1372 transitions. Second operand has 924 states, 924 states have (on average 1.4848484848484849) internal successors, (1372), 923 states have internal predecessors, (1372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,987 INFO L93 Difference]: Finished difference Result 924 states and 1372 transitions. [2022-02-21 04:24:23,987 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1372 transitions. [2022-02-21 04:24:23,989 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:23,989 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:23,990 INFO L74 IsIncluded]: Start isIncluded. First operand has 924 states, 924 states have (on average 1.4848484848484849) internal successors, (1372), 923 states have internal predecessors, (1372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1372 transitions. [2022-02-21 04:24:23,991 INFO L87 Difference]: Start difference. First operand has 924 states, 924 states have (on average 1.4848484848484849) internal successors, (1372), 923 states have internal predecessors, (1372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1372 transitions. [2022-02-21 04:24:24,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,011 INFO L93 Difference]: Finished difference Result 924 states and 1372 transitions. [2022-02-21 04:24:24,012 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1372 transitions. [2022-02-21 04:24:24,013 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:24,013 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:24,013 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:24,013 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:24,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4848484848484849) internal successors, (1372), 923 states have internal predecessors, (1372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1372 transitions. [2022-02-21 04:24:24,034 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1372 transitions. [2022-02-21 04:24:24,034 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1372 transitions. [2022-02-21 04:24:24,034 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:24,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1372 transitions. [2022-02-21 04:24:24,037 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:24,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:24,037 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:24,038 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:24,038 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:24,038 INFO L791 eck$LassoCheckResult]: Stem: 28481#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 28482#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 28724#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27896#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27897#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 28168#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28169#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28666#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28656#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28236#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28237#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28461#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28462#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28318#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28319#L838 assume !(0 == ~M_E~0); 28468#L838-2 assume !(0 == ~T1_E~0); 27858#L843-1 assume !(0 == ~T2_E~0); 27859#L848-1 assume !(0 == ~T3_E~0); 27978#L853-1 assume !(0 == ~T4_E~0); 28304#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27805#L863-1 assume !(0 == ~T6_E~0); 27806#L868-1 assume !(0 == ~T7_E~0); 28698#L873-1 assume !(0 == ~T8_E~0); 28696#L878-1 assume !(0 == ~E_1~0); 28685#L883-1 assume !(0 == ~E_2~0); 28686#L888-1 assume !(0 == ~E_3~0); 28433#L893-1 assume !(0 == ~E_4~0); 28434#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 28710#L903-1 assume !(0 == ~E_6~0); 28684#L908-1 assume !(0 == ~E_7~0); 28558#L913-1 assume !(0 == ~E_8~0); 27872#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27873#L402 assume !(1 == ~m_pc~0); 28081#L402-2 is_master_triggered_~__retres1~0#1 := 0; 27999#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28000#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28242#L1035 assume !(0 != activate_threads_~tmp~1#1); 28243#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28295#L421 assume 1 == ~t1_pc~0; 28680#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28699#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28287#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28288#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 28346#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28707#L440 assume 1 == ~t2_pc~0; 27842#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27843#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28009#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28718#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 28572#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28196#L459 assume !(1 == ~t3_pc~0); 28197#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28679#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28503#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27993#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27994#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28003#L478 assume 1 == ~t4_pc~0; 28004#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28438#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28665#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28174#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 27917#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27918#L497 assume !(1 == ~t5_pc~0); 27964#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 27965#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28256#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28257#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 28672#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28673#L516 assume 1 == ~t6_pc~0; 28727#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28459#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28460#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28048#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 28049#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28450#L535 assume !(1 == ~t7_pc~0); 28451#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28520#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28521#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28549#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 28539#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28540#L554 assume 1 == ~t8_pc~0; 28489#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27834#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28590#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28136#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 28137#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27818#L931 assume !(1 == ~M_E~0); 27819#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28693#L936-1 assume !(1 == ~T2_E~0); 28716#L941-1 assume !(1 == ~T3_E~0); 28296#L946-1 assume !(1 == ~T4_E~0); 28297#L951-1 assume !(1 == ~T5_E~0); 28063#L956-1 assume !(1 == ~T6_E~0); 28064#L961-1 assume !(1 == ~T7_E~0); 28435#L966-1 assume !(1 == ~T8_E~0); 28436#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28542#L976-1 assume !(1 == ~E_2~0); 28512#L981-1 assume !(1 == ~E_3~0); 28301#L986-1 assume !(1 == ~E_4~0); 28093#L991-1 assume !(1 == ~E_5~0); 28094#L996-1 assume !(1 == ~E_6~0); 28703#L1001-1 assume !(1 == ~E_7~0); 28479#L1006-1 assume !(1 == ~E_8~0); 28480#L1011-1 assume { :end_inline_reset_delta_events } true; 27881#L1272-2 [2022-02-21 04:24:24,038 INFO L793 eck$LassoCheckResult]: Loop: 27881#L1272-2 assume !false; 27882#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27883#L813 assume !false; 27884#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 28630#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 27886#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 28430#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28440#L696 assume !(0 != eval_~tmp~0#1); 28483#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28484#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28605#L838-3 assume !(0 == ~M_E~0); 28525#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28526#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28388#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28389#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28437#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28500#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28492#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28493#L873-3 assume !(0 == ~T8_E~0); 28116#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27845#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27846#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27847#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27848#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28322#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28631#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28335#L913-3 assume !(0 == ~E_8~0); 27888#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27889#L402-27 assume 1 == ~m_pc~0; 27835#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27836#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28325#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28326#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28644#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28645#L421-27 assume !(1 == ~t1_pc~0); 28108#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 28109#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28358#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28359#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28704#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28453#L440-27 assume 1 == ~t2_pc~0; 28454#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28627#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28192#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28193#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28367#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28096#L459-27 assume !(1 == ~t3_pc~0); 28097#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 28515#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28160#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28161#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28449#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28697#L478-27 assume !(1 == ~t4_pc~0); 28086#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 28087#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28463#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28595#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28596#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28632#L497-27 assume 1 == ~t5_pc~0; 28633#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28125#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28126#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28069#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28070#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28327#L516-27 assume 1 == ~t6_pc~0; 28328#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28182#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28183#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28330#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 28470#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28259#L535-27 assume 1 == ~t7_pc~0; 28260#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28576#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28606#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28607#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28213#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28214#L554-27 assume !(1 == ~t8_pc~0); 27862#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 27863#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28008#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28347#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 28113#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28114#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27989#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27990#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28210#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28342#L946-3 assume !(1 == ~T4_E~0); 28131#L951-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28132#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28411#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28220#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28221#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28458#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27879#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27880#L986-3 assume !(1 == ~E_4~0); 27870#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27871#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28530#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28201#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28202#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 27912#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 27914#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 28228#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 28229#L1291 assume !(0 == start_simulation_~tmp~3#1); 28408#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 28314#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 27809#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 27810#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 28614#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28278#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28279#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 28495#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 27881#L1272-2 [2022-02-21 04:24:24,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:24,039 INFO L85 PathProgramCache]: Analyzing trace with hash -1253090466, now seen corresponding path program 1 times [2022-02-21 04:24:24,039 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:24,039 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133258221] [2022-02-21 04:24:24,039 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:24,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:24,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,062 INFO L290 TraceCheckUtils]: 0: Hoare triple {30580#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,063 INFO L290 TraceCheckUtils]: 1: Hoare triple {30582#(<= 2 ~T5_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,063 INFO L290 TraceCheckUtils]: 2: Hoare triple {30582#(<= 2 ~T5_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,063 INFO L290 TraceCheckUtils]: 3: Hoare triple {30582#(<= 2 ~T5_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,064 INFO L290 TraceCheckUtils]: 4: Hoare triple {30582#(<= 2 ~T5_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,064 INFO L290 TraceCheckUtils]: 5: Hoare triple {30582#(<= 2 ~T5_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,064 INFO L290 TraceCheckUtils]: 6: Hoare triple {30582#(<= 2 ~T5_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,064 INFO L290 TraceCheckUtils]: 7: Hoare triple {30582#(<= 2 ~T5_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,065 INFO L290 TraceCheckUtils]: 8: Hoare triple {30582#(<= 2 ~T5_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,065 INFO L290 TraceCheckUtils]: 9: Hoare triple {30582#(<= 2 ~T5_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,065 INFO L290 TraceCheckUtils]: 10: Hoare triple {30582#(<= 2 ~T5_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,065 INFO L290 TraceCheckUtils]: 11: Hoare triple {30582#(<= 2 ~T5_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,066 INFO L290 TraceCheckUtils]: 12: Hoare triple {30582#(<= 2 ~T5_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,066 INFO L290 TraceCheckUtils]: 13: Hoare triple {30582#(<= 2 ~T5_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,066 INFO L290 TraceCheckUtils]: 14: Hoare triple {30582#(<= 2 ~T5_E~0)} assume !(0 == ~M_E~0); {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,066 INFO L290 TraceCheckUtils]: 15: Hoare triple {30582#(<= 2 ~T5_E~0)} assume !(0 == ~T1_E~0); {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,067 INFO L290 TraceCheckUtils]: 16: Hoare triple {30582#(<= 2 ~T5_E~0)} assume !(0 == ~T2_E~0); {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,067 INFO L290 TraceCheckUtils]: 17: Hoare triple {30582#(<= 2 ~T5_E~0)} assume !(0 == ~T3_E~0); {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,067 INFO L290 TraceCheckUtils]: 18: Hoare triple {30582#(<= 2 ~T5_E~0)} assume !(0 == ~T4_E~0); {30582#(<= 2 ~T5_E~0)} is VALID [2022-02-21 04:24:24,067 INFO L290 TraceCheckUtils]: 19: Hoare triple {30582#(<= 2 ~T5_E~0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {30581#false} is VALID [2022-02-21 04:24:24,067 INFO L290 TraceCheckUtils]: 20: Hoare triple {30581#false} assume !(0 == ~T6_E~0); {30581#false} is VALID [2022-02-21 04:24:24,068 INFO L290 TraceCheckUtils]: 21: Hoare triple {30581#false} assume !(0 == ~T7_E~0); {30581#false} is VALID [2022-02-21 04:24:24,068 INFO L290 TraceCheckUtils]: 22: Hoare triple {30581#false} assume !(0 == ~T8_E~0); {30581#false} is VALID [2022-02-21 04:24:24,068 INFO L290 TraceCheckUtils]: 23: Hoare triple {30581#false} assume !(0 == ~E_1~0); {30581#false} is VALID [2022-02-21 04:24:24,068 INFO L290 TraceCheckUtils]: 24: Hoare triple {30581#false} assume !(0 == ~E_2~0); {30581#false} is VALID [2022-02-21 04:24:24,068 INFO L290 TraceCheckUtils]: 25: Hoare triple {30581#false} assume !(0 == ~E_3~0); {30581#false} is VALID [2022-02-21 04:24:24,068 INFO L290 TraceCheckUtils]: 26: Hoare triple {30581#false} assume !(0 == ~E_4~0); {30581#false} is VALID [2022-02-21 04:24:24,068 INFO L290 TraceCheckUtils]: 27: Hoare triple {30581#false} assume 0 == ~E_5~0;~E_5~0 := 1; {30581#false} is VALID [2022-02-21 04:24:24,068 INFO L290 TraceCheckUtils]: 28: Hoare triple {30581#false} assume !(0 == ~E_6~0); {30581#false} is VALID [2022-02-21 04:24:24,068 INFO L290 TraceCheckUtils]: 29: Hoare triple {30581#false} assume !(0 == ~E_7~0); {30581#false} is VALID [2022-02-21 04:24:24,069 INFO L290 TraceCheckUtils]: 30: Hoare triple {30581#false} assume !(0 == ~E_8~0); {30581#false} is VALID [2022-02-21 04:24:24,069 INFO L290 TraceCheckUtils]: 31: Hoare triple {30581#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {30581#false} is VALID [2022-02-21 04:24:24,069 INFO L290 TraceCheckUtils]: 32: Hoare triple {30581#false} assume !(1 == ~m_pc~0); {30581#false} is VALID [2022-02-21 04:24:24,069 INFO L290 TraceCheckUtils]: 33: Hoare triple {30581#false} is_master_triggered_~__retres1~0#1 := 0; {30581#false} is VALID [2022-02-21 04:24:24,069 INFO L290 TraceCheckUtils]: 34: Hoare triple {30581#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {30581#false} is VALID [2022-02-21 04:24:24,069 INFO L290 TraceCheckUtils]: 35: Hoare triple {30581#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {30581#false} is VALID [2022-02-21 04:24:24,069 INFO L290 TraceCheckUtils]: 36: Hoare triple {30581#false} assume !(0 != activate_threads_~tmp~1#1); {30581#false} is VALID [2022-02-21 04:24:24,069 INFO L290 TraceCheckUtils]: 37: Hoare triple {30581#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {30581#false} is VALID [2022-02-21 04:24:24,069 INFO L290 TraceCheckUtils]: 38: Hoare triple {30581#false} assume 1 == ~t1_pc~0; {30581#false} is VALID [2022-02-21 04:24:24,070 INFO L290 TraceCheckUtils]: 39: Hoare triple {30581#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {30581#false} is VALID [2022-02-21 04:24:24,070 INFO L290 TraceCheckUtils]: 40: Hoare triple {30581#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {30581#false} is VALID [2022-02-21 04:24:24,070 INFO L290 TraceCheckUtils]: 41: Hoare triple {30581#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {30581#false} is VALID [2022-02-21 04:24:24,070 INFO L290 TraceCheckUtils]: 42: Hoare triple {30581#false} assume !(0 != activate_threads_~tmp___0~0#1); {30581#false} is VALID [2022-02-21 04:24:24,070 INFO L290 TraceCheckUtils]: 43: Hoare triple {30581#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {30581#false} is VALID [2022-02-21 04:24:24,070 INFO L290 TraceCheckUtils]: 44: Hoare triple {30581#false} assume 1 == ~t2_pc~0; {30581#false} is VALID [2022-02-21 04:24:24,070 INFO L290 TraceCheckUtils]: 45: Hoare triple {30581#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {30581#false} is VALID [2022-02-21 04:24:24,070 INFO L290 TraceCheckUtils]: 46: Hoare triple {30581#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {30581#false} is VALID [2022-02-21 04:24:24,070 INFO L290 TraceCheckUtils]: 47: Hoare triple {30581#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {30581#false} is VALID [2022-02-21 04:24:24,071 INFO L290 TraceCheckUtils]: 48: Hoare triple {30581#false} assume !(0 != activate_threads_~tmp___1~0#1); {30581#false} is VALID [2022-02-21 04:24:24,071 INFO L290 TraceCheckUtils]: 49: Hoare triple {30581#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {30581#false} is VALID [2022-02-21 04:24:24,071 INFO L290 TraceCheckUtils]: 50: Hoare triple {30581#false} assume !(1 == ~t3_pc~0); {30581#false} is VALID [2022-02-21 04:24:24,071 INFO L290 TraceCheckUtils]: 51: Hoare triple {30581#false} is_transmit3_triggered_~__retres1~3#1 := 0; {30581#false} is VALID [2022-02-21 04:24:24,071 INFO L290 TraceCheckUtils]: 52: Hoare triple {30581#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {30581#false} is VALID [2022-02-21 04:24:24,071 INFO L290 TraceCheckUtils]: 53: Hoare triple {30581#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {30581#false} is VALID [2022-02-21 04:24:24,071 INFO L290 TraceCheckUtils]: 54: Hoare triple {30581#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {30581#false} is VALID [2022-02-21 04:24:24,071 INFO L290 TraceCheckUtils]: 55: Hoare triple {30581#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {30581#false} is VALID [2022-02-21 04:24:24,071 INFO L290 TraceCheckUtils]: 56: Hoare triple {30581#false} assume 1 == ~t4_pc~0; {30581#false} is VALID [2022-02-21 04:24:24,072 INFO L290 TraceCheckUtils]: 57: Hoare triple {30581#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {30581#false} is VALID [2022-02-21 04:24:24,072 INFO L290 TraceCheckUtils]: 58: Hoare triple {30581#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {30581#false} is VALID [2022-02-21 04:24:24,072 INFO L290 TraceCheckUtils]: 59: Hoare triple {30581#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {30581#false} is VALID [2022-02-21 04:24:24,072 INFO L290 TraceCheckUtils]: 60: Hoare triple {30581#false} assume !(0 != activate_threads_~tmp___3~0#1); {30581#false} is VALID [2022-02-21 04:24:24,072 INFO L290 TraceCheckUtils]: 61: Hoare triple {30581#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {30581#false} is VALID [2022-02-21 04:24:24,072 INFO L290 TraceCheckUtils]: 62: Hoare triple {30581#false} assume !(1 == ~t5_pc~0); {30581#false} is VALID [2022-02-21 04:24:24,072 INFO L290 TraceCheckUtils]: 63: Hoare triple {30581#false} is_transmit5_triggered_~__retres1~5#1 := 0; {30581#false} is VALID [2022-02-21 04:24:24,072 INFO L290 TraceCheckUtils]: 64: Hoare triple {30581#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {30581#false} is VALID [2022-02-21 04:24:24,072 INFO L290 TraceCheckUtils]: 65: Hoare triple {30581#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {30581#false} is VALID [2022-02-21 04:24:24,073 INFO L290 TraceCheckUtils]: 66: Hoare triple {30581#false} assume !(0 != activate_threads_~tmp___4~0#1); {30581#false} is VALID [2022-02-21 04:24:24,073 INFO L290 TraceCheckUtils]: 67: Hoare triple {30581#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {30581#false} is VALID [2022-02-21 04:24:24,073 INFO L290 TraceCheckUtils]: 68: Hoare triple {30581#false} assume 1 == ~t6_pc~0; {30581#false} is VALID [2022-02-21 04:24:24,073 INFO L290 TraceCheckUtils]: 69: Hoare triple {30581#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {30581#false} is VALID [2022-02-21 04:24:24,073 INFO L290 TraceCheckUtils]: 70: Hoare triple {30581#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {30581#false} is VALID [2022-02-21 04:24:24,073 INFO L290 TraceCheckUtils]: 71: Hoare triple {30581#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {30581#false} is VALID [2022-02-21 04:24:24,073 INFO L290 TraceCheckUtils]: 72: Hoare triple {30581#false} assume !(0 != activate_threads_~tmp___5~0#1); {30581#false} is VALID [2022-02-21 04:24:24,073 INFO L290 TraceCheckUtils]: 73: Hoare triple {30581#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {30581#false} is VALID [2022-02-21 04:24:24,073 INFO L290 TraceCheckUtils]: 74: Hoare triple {30581#false} assume !(1 == ~t7_pc~0); {30581#false} is VALID [2022-02-21 04:24:24,074 INFO L290 TraceCheckUtils]: 75: Hoare triple {30581#false} is_transmit7_triggered_~__retres1~7#1 := 0; {30581#false} is VALID [2022-02-21 04:24:24,074 INFO L290 TraceCheckUtils]: 76: Hoare triple {30581#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {30581#false} is VALID [2022-02-21 04:24:24,074 INFO L290 TraceCheckUtils]: 77: Hoare triple {30581#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {30581#false} is VALID [2022-02-21 04:24:24,074 INFO L290 TraceCheckUtils]: 78: Hoare triple {30581#false} assume !(0 != activate_threads_~tmp___6~0#1); {30581#false} is VALID [2022-02-21 04:24:24,074 INFO L290 TraceCheckUtils]: 79: Hoare triple {30581#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {30581#false} is VALID [2022-02-21 04:24:24,074 INFO L290 TraceCheckUtils]: 80: Hoare triple {30581#false} assume 1 == ~t8_pc~0; {30581#false} is VALID [2022-02-21 04:24:24,074 INFO L290 TraceCheckUtils]: 81: Hoare triple {30581#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {30581#false} is VALID [2022-02-21 04:24:24,074 INFO L290 TraceCheckUtils]: 82: Hoare triple {30581#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {30581#false} is VALID [2022-02-21 04:24:24,074 INFO L290 TraceCheckUtils]: 83: Hoare triple {30581#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {30581#false} is VALID [2022-02-21 04:24:24,075 INFO L290 TraceCheckUtils]: 84: Hoare triple {30581#false} assume !(0 != activate_threads_~tmp___7~0#1); {30581#false} is VALID [2022-02-21 04:24:24,075 INFO L290 TraceCheckUtils]: 85: Hoare triple {30581#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {30581#false} is VALID [2022-02-21 04:24:24,075 INFO L290 TraceCheckUtils]: 86: Hoare triple {30581#false} assume !(1 == ~M_E~0); {30581#false} is VALID [2022-02-21 04:24:24,075 INFO L290 TraceCheckUtils]: 87: Hoare triple {30581#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {30581#false} is VALID [2022-02-21 04:24:24,075 INFO L290 TraceCheckUtils]: 88: Hoare triple {30581#false} assume !(1 == ~T2_E~0); {30581#false} is VALID [2022-02-21 04:24:24,075 INFO L290 TraceCheckUtils]: 89: Hoare triple {30581#false} assume !(1 == ~T3_E~0); {30581#false} is VALID [2022-02-21 04:24:24,075 INFO L290 TraceCheckUtils]: 90: Hoare triple {30581#false} assume !(1 == ~T4_E~0); {30581#false} is VALID [2022-02-21 04:24:24,075 INFO L290 TraceCheckUtils]: 91: Hoare triple {30581#false} assume !(1 == ~T5_E~0); {30581#false} is VALID [2022-02-21 04:24:24,075 INFO L290 TraceCheckUtils]: 92: Hoare triple {30581#false} assume !(1 == ~T6_E~0); {30581#false} is VALID [2022-02-21 04:24:24,076 INFO L290 TraceCheckUtils]: 93: Hoare triple {30581#false} assume !(1 == ~T7_E~0); {30581#false} is VALID [2022-02-21 04:24:24,076 INFO L290 TraceCheckUtils]: 94: Hoare triple {30581#false} assume !(1 == ~T8_E~0); {30581#false} is VALID [2022-02-21 04:24:24,076 INFO L290 TraceCheckUtils]: 95: Hoare triple {30581#false} assume 1 == ~E_1~0;~E_1~0 := 2; {30581#false} is VALID [2022-02-21 04:24:24,076 INFO L290 TraceCheckUtils]: 96: Hoare triple {30581#false} assume !(1 == ~E_2~0); {30581#false} is VALID [2022-02-21 04:24:24,076 INFO L290 TraceCheckUtils]: 97: Hoare triple {30581#false} assume !(1 == ~E_3~0); {30581#false} is VALID [2022-02-21 04:24:24,076 INFO L290 TraceCheckUtils]: 98: Hoare triple {30581#false} assume !(1 == ~E_4~0); {30581#false} is VALID [2022-02-21 04:24:24,076 INFO L290 TraceCheckUtils]: 99: Hoare triple {30581#false} assume !(1 == ~E_5~0); {30581#false} is VALID [2022-02-21 04:24:24,076 INFO L290 TraceCheckUtils]: 100: Hoare triple {30581#false} assume !(1 == ~E_6~0); {30581#false} is VALID [2022-02-21 04:24:24,076 INFO L290 TraceCheckUtils]: 101: Hoare triple {30581#false} assume !(1 == ~E_7~0); {30581#false} is VALID [2022-02-21 04:24:24,076 INFO L290 TraceCheckUtils]: 102: Hoare triple {30581#false} assume !(1 == ~E_8~0); {30581#false} is VALID [2022-02-21 04:24:24,077 INFO L290 TraceCheckUtils]: 103: Hoare triple {30581#false} assume { :end_inline_reset_delta_events } true; {30581#false} is VALID [2022-02-21 04:24:24,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,077 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,077 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133258221] [2022-02-21 04:24:24,077 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2133258221] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,077 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,078 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:24,078 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [867319221] [2022-02-21 04:24:24,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,078 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:24,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:24,078 INFO L85 PathProgramCache]: Analyzing trace with hash -638345507, now seen corresponding path program 2 times [2022-02-21 04:24:24,079 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:24,079 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923591542] [2022-02-21 04:24:24,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:24,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:24,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,099 INFO L290 TraceCheckUtils]: 0: Hoare triple {30583#true} assume !false; {30583#true} is VALID [2022-02-21 04:24:24,099 INFO L290 TraceCheckUtils]: 1: Hoare triple {30583#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {30583#true} is VALID [2022-02-21 04:24:24,099 INFO L290 TraceCheckUtils]: 2: Hoare triple {30583#true} assume !false; {30583#true} is VALID [2022-02-21 04:24:24,099 INFO L290 TraceCheckUtils]: 3: Hoare triple {30583#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {30583#true} is VALID [2022-02-21 04:24:24,099 INFO L290 TraceCheckUtils]: 4: Hoare triple {30583#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {30583#true} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 5: Hoare triple {30583#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {30583#true} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 6: Hoare triple {30583#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {30583#true} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 7: Hoare triple {30583#true} assume !(0 != eval_~tmp~0#1); {30583#true} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 8: Hoare triple {30583#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {30583#true} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 9: Hoare triple {30583#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {30583#true} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 10: Hoare triple {30583#true} assume !(0 == ~M_E~0); {30583#true} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 11: Hoare triple {30583#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {30583#true} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 12: Hoare triple {30583#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {30583#true} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 13: Hoare triple {30583#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {30583#true} is VALID [2022-02-21 04:24:24,101 INFO L290 TraceCheckUtils]: 14: Hoare triple {30583#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,101 INFO L290 TraceCheckUtils]: 15: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,101 INFO L290 TraceCheckUtils]: 16: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,102 INFO L290 TraceCheckUtils]: 17: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,102 INFO L290 TraceCheckUtils]: 18: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,102 INFO L290 TraceCheckUtils]: 19: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,102 INFO L290 TraceCheckUtils]: 20: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,103 INFO L290 TraceCheckUtils]: 21: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,103 INFO L290 TraceCheckUtils]: 22: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,103 INFO L290 TraceCheckUtils]: 23: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,103 INFO L290 TraceCheckUtils]: 24: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,104 INFO L290 TraceCheckUtils]: 25: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,104 INFO L290 TraceCheckUtils]: 26: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,104 INFO L290 TraceCheckUtils]: 27: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,104 INFO L290 TraceCheckUtils]: 28: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~m_pc~0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,105 INFO L290 TraceCheckUtils]: 29: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,105 INFO L290 TraceCheckUtils]: 30: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,105 INFO L290 TraceCheckUtils]: 31: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,105 INFO L290 TraceCheckUtils]: 32: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,106 INFO L290 TraceCheckUtils]: 33: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,106 INFO L290 TraceCheckUtils]: 34: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t1_pc~0); {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,106 INFO L290 TraceCheckUtils]: 35: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,106 INFO L290 TraceCheckUtils]: 36: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,107 INFO L290 TraceCheckUtils]: 37: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,107 INFO L290 TraceCheckUtils]: 38: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,107 INFO L290 TraceCheckUtils]: 39: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,107 INFO L290 TraceCheckUtils]: 40: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t2_pc~0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,108 INFO L290 TraceCheckUtils]: 41: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,108 INFO L290 TraceCheckUtils]: 42: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,108 INFO L290 TraceCheckUtils]: 43: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,108 INFO L290 TraceCheckUtils]: 44: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,109 INFO L290 TraceCheckUtils]: 45: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,109 INFO L290 TraceCheckUtils]: 46: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t3_pc~0); {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,109 INFO L290 TraceCheckUtils]: 47: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,109 INFO L290 TraceCheckUtils]: 48: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,110 INFO L290 TraceCheckUtils]: 49: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,110 INFO L290 TraceCheckUtils]: 50: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,110 INFO L290 TraceCheckUtils]: 51: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,110 INFO L290 TraceCheckUtils]: 52: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t4_pc~0); {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,111 INFO L290 TraceCheckUtils]: 53: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,111 INFO L290 TraceCheckUtils]: 54: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,111 INFO L290 TraceCheckUtils]: 55: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,111 INFO L290 TraceCheckUtils]: 56: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,112 INFO L290 TraceCheckUtils]: 57: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,112 INFO L290 TraceCheckUtils]: 58: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t5_pc~0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,112 INFO L290 TraceCheckUtils]: 59: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,112 INFO L290 TraceCheckUtils]: 60: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,113 INFO L290 TraceCheckUtils]: 61: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,113 INFO L290 TraceCheckUtils]: 62: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,113 INFO L290 TraceCheckUtils]: 63: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,113 INFO L290 TraceCheckUtils]: 64: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t6_pc~0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 65: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 66: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 67: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 68: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 69: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 70: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t7_pc~0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 71: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 72: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,116 INFO L290 TraceCheckUtils]: 73: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,116 INFO L290 TraceCheckUtils]: 74: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,116 INFO L290 TraceCheckUtils]: 75: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,116 INFO L290 TraceCheckUtils]: 76: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t8_pc~0); {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,117 INFO L290 TraceCheckUtils]: 77: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,117 INFO L290 TraceCheckUtils]: 78: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,117 INFO L290 TraceCheckUtils]: 79: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,117 INFO L290 TraceCheckUtils]: 80: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,118 INFO L290 TraceCheckUtils]: 81: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,118 INFO L290 TraceCheckUtils]: 82: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,118 INFO L290 TraceCheckUtils]: 83: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,118 INFO L290 TraceCheckUtils]: 84: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,119 INFO L290 TraceCheckUtils]: 85: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {30585#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,119 INFO L290 TraceCheckUtils]: 86: Hoare triple {30585#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {30584#false} is VALID [2022-02-21 04:24:24,119 INFO L290 TraceCheckUtils]: 87: Hoare triple {30584#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {30584#false} is VALID [2022-02-21 04:24:24,119 INFO L290 TraceCheckUtils]: 88: Hoare triple {30584#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {30584#false} is VALID [2022-02-21 04:24:24,119 INFO L290 TraceCheckUtils]: 89: Hoare triple {30584#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {30584#false} is VALID [2022-02-21 04:24:24,119 INFO L290 TraceCheckUtils]: 90: Hoare triple {30584#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {30584#false} is VALID [2022-02-21 04:24:24,119 INFO L290 TraceCheckUtils]: 91: Hoare triple {30584#false} assume 1 == ~E_1~0;~E_1~0 := 2; {30584#false} is VALID [2022-02-21 04:24:24,119 INFO L290 TraceCheckUtils]: 92: Hoare triple {30584#false} assume 1 == ~E_2~0;~E_2~0 := 2; {30584#false} is VALID [2022-02-21 04:24:24,120 INFO L290 TraceCheckUtils]: 93: Hoare triple {30584#false} assume 1 == ~E_3~0;~E_3~0 := 2; {30584#false} is VALID [2022-02-21 04:24:24,120 INFO L290 TraceCheckUtils]: 94: Hoare triple {30584#false} assume !(1 == ~E_4~0); {30584#false} is VALID [2022-02-21 04:24:24,120 INFO L290 TraceCheckUtils]: 95: Hoare triple {30584#false} assume 1 == ~E_5~0;~E_5~0 := 2; {30584#false} is VALID [2022-02-21 04:24:24,120 INFO L290 TraceCheckUtils]: 96: Hoare triple {30584#false} assume 1 == ~E_6~0;~E_6~0 := 2; {30584#false} is VALID [2022-02-21 04:24:24,120 INFO L290 TraceCheckUtils]: 97: Hoare triple {30584#false} assume 1 == ~E_7~0;~E_7~0 := 2; {30584#false} is VALID [2022-02-21 04:24:24,120 INFO L290 TraceCheckUtils]: 98: Hoare triple {30584#false} assume 1 == ~E_8~0;~E_8~0 := 2; {30584#false} is VALID [2022-02-21 04:24:24,120 INFO L290 TraceCheckUtils]: 99: Hoare triple {30584#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {30584#false} is VALID [2022-02-21 04:24:24,120 INFO L290 TraceCheckUtils]: 100: Hoare triple {30584#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {30584#false} is VALID [2022-02-21 04:24:24,120 INFO L290 TraceCheckUtils]: 101: Hoare triple {30584#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {30584#false} is VALID [2022-02-21 04:24:24,121 INFO L290 TraceCheckUtils]: 102: Hoare triple {30584#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {30584#false} is VALID [2022-02-21 04:24:24,121 INFO L290 TraceCheckUtils]: 103: Hoare triple {30584#false} assume !(0 == start_simulation_~tmp~3#1); {30584#false} is VALID [2022-02-21 04:24:24,121 INFO L290 TraceCheckUtils]: 104: Hoare triple {30584#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {30584#false} is VALID [2022-02-21 04:24:24,121 INFO L290 TraceCheckUtils]: 105: Hoare triple {30584#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {30584#false} is VALID [2022-02-21 04:24:24,121 INFO L290 TraceCheckUtils]: 106: Hoare triple {30584#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {30584#false} is VALID [2022-02-21 04:24:24,121 INFO L290 TraceCheckUtils]: 107: Hoare triple {30584#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {30584#false} is VALID [2022-02-21 04:24:24,121 INFO L290 TraceCheckUtils]: 108: Hoare triple {30584#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {30584#false} is VALID [2022-02-21 04:24:24,121 INFO L290 TraceCheckUtils]: 109: Hoare triple {30584#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {30584#false} is VALID [2022-02-21 04:24:24,121 INFO L290 TraceCheckUtils]: 110: Hoare triple {30584#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {30584#false} is VALID [2022-02-21 04:24:24,122 INFO L290 TraceCheckUtils]: 111: Hoare triple {30584#false} assume !(0 != start_simulation_~tmp___0~1#1); {30584#false} is VALID [2022-02-21 04:24:24,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,122 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,122 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923591542] [2022-02-21 04:24:24,122 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1923591542] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,122 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,123 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:24,123 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27667057] [2022-02-21 04:24:24,123 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,123 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:24,123 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:24,124 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:24,124 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:24,124 INFO L87 Difference]: Start difference. First operand 924 states and 1372 transitions. cyclomatic complexity: 449 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,724 INFO L93 Difference]: Finished difference Result 924 states and 1367 transitions. [2022-02-21 04:24:24,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:24,724 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,783 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:24,784 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 924 states and 1367 transitions. [2022-02-21 04:24:24,805 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:24,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 924 states to 924 states and 1367 transitions. [2022-02-21 04:24:24,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2022-02-21 04:24:24,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2022-02-21 04:24:24,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 924 states and 1367 transitions. [2022-02-21 04:24:24,826 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:24,827 INFO L681 BuchiCegarLoop]: Abstraction has 924 states and 1367 transitions. [2022-02-21 04:24:24,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 924 states and 1367 transitions. [2022-02-21 04:24:24,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 924 to 924. [2022-02-21 04:24:24,834 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:24,835 INFO L82 GeneralOperation]: Start isEquivalent. First operand 924 states and 1367 transitions. Second operand has 924 states, 924 states have (on average 1.4794372294372293) internal successors, (1367), 923 states have internal predecessors, (1367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,835 INFO L74 IsIncluded]: Start isIncluded. First operand 924 states and 1367 transitions. Second operand has 924 states, 924 states have (on average 1.4794372294372293) internal successors, (1367), 923 states have internal predecessors, (1367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,836 INFO L87 Difference]: Start difference. First operand 924 states and 1367 transitions. Second operand has 924 states, 924 states have (on average 1.4794372294372293) internal successors, (1367), 923 states have internal predecessors, (1367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,856 INFO L93 Difference]: Finished difference Result 924 states and 1367 transitions. [2022-02-21 04:24:24,856 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1367 transitions. [2022-02-21 04:24:24,857 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:24,857 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:24,858 INFO L74 IsIncluded]: Start isIncluded. First operand has 924 states, 924 states have (on average 1.4794372294372293) internal successors, (1367), 923 states have internal predecessors, (1367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1367 transitions. [2022-02-21 04:24:24,859 INFO L87 Difference]: Start difference. First operand has 924 states, 924 states have (on average 1.4794372294372293) internal successors, (1367), 923 states have internal predecessors, (1367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 924 states and 1367 transitions. [2022-02-21 04:24:24,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,878 INFO L93 Difference]: Finished difference Result 924 states and 1367 transitions. [2022-02-21 04:24:24,878 INFO L276 IsEmpty]: Start isEmpty. Operand 924 states and 1367 transitions. [2022-02-21 04:24:24,879 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:24,879 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:24,880 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:24,880 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:24,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 924 states, 924 states have (on average 1.4794372294372293) internal successors, (1367), 923 states have internal predecessors, (1367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 924 states to 924 states and 1367 transitions. [2022-02-21 04:24:24,900 INFO L704 BuchiCegarLoop]: Abstraction has 924 states and 1367 transitions. [2022-02-21 04:24:24,900 INFO L587 BuchiCegarLoop]: Abstraction has 924 states and 1367 transitions. [2022-02-21 04:24:24,900 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:24:24,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 924 states and 1367 transitions. [2022-02-21 04:24:24,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 811 [2022-02-21 04:24:24,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:24,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:24,903 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:24,903 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:24,904 INFO L791 eck$LassoCheckResult]: Stem: 32186#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 32187#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 32429#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31601#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31602#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 31873#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31874#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32371#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32362#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31941#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31942#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32167#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32168#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32023#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32024#L838 assume !(0 == ~M_E~0); 32174#L838-2 assume !(0 == ~T1_E~0); 31563#L843-1 assume !(0 == ~T2_E~0); 31564#L848-1 assume !(0 == ~T3_E~0); 31683#L853-1 assume !(0 == ~T4_E~0); 32011#L858-1 assume !(0 == ~T5_E~0); 31512#L863-1 assume !(0 == ~T6_E~0); 31513#L868-1 assume !(0 == ~T7_E~0); 32403#L873-1 assume !(0 == ~T8_E~0); 32401#L878-1 assume !(0 == ~E_1~0); 32390#L883-1 assume !(0 == ~E_2~0); 32391#L888-1 assume !(0 == ~E_3~0); 32139#L893-1 assume !(0 == ~E_4~0); 32140#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 32415#L903-1 assume !(0 == ~E_6~0); 32389#L908-1 assume !(0 == ~E_7~0); 32265#L913-1 assume !(0 == ~E_8~0); 31577#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31578#L402 assume !(1 == ~m_pc~0); 31790#L402-2 is_master_triggered_~__retres1~0#1 := 0; 31704#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31705#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31947#L1035 assume !(0 != activate_threads_~tmp~1#1); 31948#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32000#L421 assume 1 == ~t1_pc~0; 32385#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32407#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31992#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31993#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 32052#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32412#L440 assume 1 == ~t2_pc~0; 31547#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31548#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31714#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32423#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 32277#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31905#L459 assume !(1 == ~t3_pc~0); 31906#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32384#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32209#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31698#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31699#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31708#L478 assume 1 == ~t4_pc~0; 31709#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32143#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32370#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31879#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 31624#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31625#L497 assume !(1 == ~t5_pc~0); 31669#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 31670#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31961#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31962#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 32378#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32379#L516 assume 1 == ~t6_pc~0; 32432#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32164#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32165#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31753#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 31754#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32155#L535 assume !(1 == ~t7_pc~0); 32156#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 32225#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32226#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32254#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 32245#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32246#L554 assume 1 == ~t8_pc~0; 32195#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31539#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32295#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31844#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 31845#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31523#L931 assume !(1 == ~M_E~0); 31524#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32398#L936-1 assume !(1 == ~T2_E~0); 32421#L941-1 assume !(1 == ~T3_E~0); 32001#L946-1 assume !(1 == ~T4_E~0); 32002#L951-1 assume !(1 == ~T5_E~0); 31768#L956-1 assume !(1 == ~T6_E~0); 31769#L961-1 assume !(1 == ~T7_E~0); 32141#L966-1 assume !(1 == ~T8_E~0); 32142#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 32248#L976-1 assume !(1 == ~E_2~0); 32217#L981-1 assume !(1 == ~E_3~0); 32006#L986-1 assume !(1 == ~E_4~0); 31798#L991-1 assume !(1 == ~E_5~0); 31799#L996-1 assume !(1 == ~E_6~0); 32408#L1001-1 assume !(1 == ~E_7~0); 32184#L1006-1 assume !(1 == ~E_8~0); 32185#L1011-1 assume { :end_inline_reset_delta_events } true; 31586#L1272-2 [2022-02-21 04:24:24,904 INFO L793 eck$LassoCheckResult]: Loop: 31586#L1272-2 assume !false; 31587#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31588#L813 assume !false; 31589#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32335#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 31591#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 32137#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 32145#L696 assume !(0 != eval_~tmp~0#1); 32188#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32189#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32312#L838-3 assume !(0 == ~M_E~0); 32230#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32231#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32093#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32094#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32138#L858-3 assume !(0 == ~T5_E~0); 32204#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32197#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32198#L873-3 assume !(0 == ~T8_E~0); 31821#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31550#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31551#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31552#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31553#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32027#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32336#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32040#L913-3 assume !(0 == ~E_8~0); 31593#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31594#L402-27 assume 1 == ~m_pc~0; 31540#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31541#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32030#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32031#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32349#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32350#L421-27 assume !(1 == ~t1_pc~0); 31813#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 31814#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32063#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32064#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32409#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32158#L440-27 assume !(1 == ~t2_pc~0); 32160#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 32331#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31897#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31898#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32072#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31801#L459-27 assume !(1 == ~t3_pc~0); 31802#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 32220#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31865#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31866#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32154#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32402#L478-27 assume 1 == ~t4_pc~0; 32424#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31792#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32166#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32300#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32301#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32337#L497-27 assume 1 == ~t5_pc~0; 32338#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31830#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31831#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31774#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31775#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32032#L516-27 assume 1 == ~t6_pc~0; 32033#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31887#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31888#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32035#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32175#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31964#L535-27 assume 1 == ~t7_pc~0; 31965#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32281#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32310#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32311#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31918#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31919#L554-27 assume 1 == ~t8_pc~0; 32115#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31568#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31713#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32051#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 31818#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31819#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31694#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31695#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31915#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32047#L946-3 assume !(1 == ~T4_E~0); 31836#L951-3 assume !(1 == ~T5_E~0); 31837#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32116#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31925#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31926#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32163#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 31584#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31585#L986-3 assume !(1 == ~E_4~0); 31575#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31576#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32235#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31903#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31904#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 31617#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 31619#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 31933#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 31934#L1291 assume !(0 == start_simulation_~tmp~3#1); 32113#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 32019#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 31514#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 31515#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 32319#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31983#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31984#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 32200#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 31586#L1272-2 [2022-02-21 04:24:24,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:24,904 INFO L85 PathProgramCache]: Analyzing trace with hash 623392352, now seen corresponding path program 1 times [2022-02-21 04:24:24,904 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:24,905 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439043713] [2022-02-21 04:24:24,905 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:24,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:24,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,933 INFO L290 TraceCheckUtils]: 0: Hoare triple {34285#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,933 INFO L290 TraceCheckUtils]: 1: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,934 INFO L290 TraceCheckUtils]: 2: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,934 INFO L290 TraceCheckUtils]: 3: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,934 INFO L290 TraceCheckUtils]: 4: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,934 INFO L290 TraceCheckUtils]: 5: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,935 INFO L290 TraceCheckUtils]: 6: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,935 INFO L290 TraceCheckUtils]: 7: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,936 INFO L290 TraceCheckUtils]: 8: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,936 INFO L290 TraceCheckUtils]: 9: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,936 INFO L290 TraceCheckUtils]: 10: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,936 INFO L290 TraceCheckUtils]: 11: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,937 INFO L290 TraceCheckUtils]: 12: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,937 INFO L290 TraceCheckUtils]: 13: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,937 INFO L290 TraceCheckUtils]: 14: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume !(0 == ~M_E~0); {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,937 INFO L290 TraceCheckUtils]: 15: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume !(0 == ~T1_E~0); {34287#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:24,938 INFO L290 TraceCheckUtils]: 16: Hoare triple {34287#(= ~T2_E~0 ~E_5~0)} assume !(0 == ~T2_E~0); {34288#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:24,938 INFO L290 TraceCheckUtils]: 17: Hoare triple {34288#(not (= ~E_5~0 0))} assume !(0 == ~T3_E~0); {34288#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:24,938 INFO L290 TraceCheckUtils]: 18: Hoare triple {34288#(not (= ~E_5~0 0))} assume !(0 == ~T4_E~0); {34288#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:24,938 INFO L290 TraceCheckUtils]: 19: Hoare triple {34288#(not (= ~E_5~0 0))} assume !(0 == ~T5_E~0); {34288#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:24,939 INFO L290 TraceCheckUtils]: 20: Hoare triple {34288#(not (= ~E_5~0 0))} assume !(0 == ~T6_E~0); {34288#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:24,939 INFO L290 TraceCheckUtils]: 21: Hoare triple {34288#(not (= ~E_5~0 0))} assume !(0 == ~T7_E~0); {34288#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:24,939 INFO L290 TraceCheckUtils]: 22: Hoare triple {34288#(not (= ~E_5~0 0))} assume !(0 == ~T8_E~0); {34288#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:24,940 INFO L290 TraceCheckUtils]: 23: Hoare triple {34288#(not (= ~E_5~0 0))} assume !(0 == ~E_1~0); {34288#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:24,940 INFO L290 TraceCheckUtils]: 24: Hoare triple {34288#(not (= ~E_5~0 0))} assume !(0 == ~E_2~0); {34288#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:24,940 INFO L290 TraceCheckUtils]: 25: Hoare triple {34288#(not (= ~E_5~0 0))} assume !(0 == ~E_3~0); {34288#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:24,940 INFO L290 TraceCheckUtils]: 26: Hoare triple {34288#(not (= ~E_5~0 0))} assume !(0 == ~E_4~0); {34288#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:24,941 INFO L290 TraceCheckUtils]: 27: Hoare triple {34288#(not (= ~E_5~0 0))} assume 0 == ~E_5~0;~E_5~0 := 1; {34286#false} is VALID [2022-02-21 04:24:24,941 INFO L290 TraceCheckUtils]: 28: Hoare triple {34286#false} assume !(0 == ~E_6~0); {34286#false} is VALID [2022-02-21 04:24:24,941 INFO L290 TraceCheckUtils]: 29: Hoare triple {34286#false} assume !(0 == ~E_7~0); {34286#false} is VALID [2022-02-21 04:24:24,941 INFO L290 TraceCheckUtils]: 30: Hoare triple {34286#false} assume !(0 == ~E_8~0); {34286#false} is VALID [2022-02-21 04:24:24,941 INFO L290 TraceCheckUtils]: 31: Hoare triple {34286#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34286#false} is VALID [2022-02-21 04:24:24,941 INFO L290 TraceCheckUtils]: 32: Hoare triple {34286#false} assume !(1 == ~m_pc~0); {34286#false} is VALID [2022-02-21 04:24:24,941 INFO L290 TraceCheckUtils]: 33: Hoare triple {34286#false} is_master_triggered_~__retres1~0#1 := 0; {34286#false} is VALID [2022-02-21 04:24:24,941 INFO L290 TraceCheckUtils]: 34: Hoare triple {34286#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34286#false} is VALID [2022-02-21 04:24:24,941 INFO L290 TraceCheckUtils]: 35: Hoare triple {34286#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {34286#false} is VALID [2022-02-21 04:24:24,942 INFO L290 TraceCheckUtils]: 36: Hoare triple {34286#false} assume !(0 != activate_threads_~tmp~1#1); {34286#false} is VALID [2022-02-21 04:24:24,942 INFO L290 TraceCheckUtils]: 37: Hoare triple {34286#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34286#false} is VALID [2022-02-21 04:24:24,942 INFO L290 TraceCheckUtils]: 38: Hoare triple {34286#false} assume 1 == ~t1_pc~0; {34286#false} is VALID [2022-02-21 04:24:24,942 INFO L290 TraceCheckUtils]: 39: Hoare triple {34286#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {34286#false} is VALID [2022-02-21 04:24:24,942 INFO L290 TraceCheckUtils]: 40: Hoare triple {34286#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34286#false} is VALID [2022-02-21 04:24:24,942 INFO L290 TraceCheckUtils]: 41: Hoare triple {34286#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {34286#false} is VALID [2022-02-21 04:24:24,942 INFO L290 TraceCheckUtils]: 42: Hoare triple {34286#false} assume !(0 != activate_threads_~tmp___0~0#1); {34286#false} is VALID [2022-02-21 04:24:24,942 INFO L290 TraceCheckUtils]: 43: Hoare triple {34286#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34286#false} is VALID [2022-02-21 04:24:24,942 INFO L290 TraceCheckUtils]: 44: Hoare triple {34286#false} assume 1 == ~t2_pc~0; {34286#false} is VALID [2022-02-21 04:24:24,943 INFO L290 TraceCheckUtils]: 45: Hoare triple {34286#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34286#false} is VALID [2022-02-21 04:24:24,943 INFO L290 TraceCheckUtils]: 46: Hoare triple {34286#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34286#false} is VALID [2022-02-21 04:24:24,943 INFO L290 TraceCheckUtils]: 47: Hoare triple {34286#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {34286#false} is VALID [2022-02-21 04:24:24,943 INFO L290 TraceCheckUtils]: 48: Hoare triple {34286#false} assume !(0 != activate_threads_~tmp___1~0#1); {34286#false} is VALID [2022-02-21 04:24:24,943 INFO L290 TraceCheckUtils]: 49: Hoare triple {34286#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34286#false} is VALID [2022-02-21 04:24:24,943 INFO L290 TraceCheckUtils]: 50: Hoare triple {34286#false} assume !(1 == ~t3_pc~0); {34286#false} is VALID [2022-02-21 04:24:24,943 INFO L290 TraceCheckUtils]: 51: Hoare triple {34286#false} is_transmit3_triggered_~__retres1~3#1 := 0; {34286#false} is VALID [2022-02-21 04:24:24,943 INFO L290 TraceCheckUtils]: 52: Hoare triple {34286#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34286#false} is VALID [2022-02-21 04:24:24,944 INFO L290 TraceCheckUtils]: 53: Hoare triple {34286#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {34286#false} is VALID [2022-02-21 04:24:24,944 INFO L290 TraceCheckUtils]: 54: Hoare triple {34286#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34286#false} is VALID [2022-02-21 04:24:24,944 INFO L290 TraceCheckUtils]: 55: Hoare triple {34286#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34286#false} is VALID [2022-02-21 04:24:24,944 INFO L290 TraceCheckUtils]: 56: Hoare triple {34286#false} assume 1 == ~t4_pc~0; {34286#false} is VALID [2022-02-21 04:24:24,944 INFO L290 TraceCheckUtils]: 57: Hoare triple {34286#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34286#false} is VALID [2022-02-21 04:24:24,944 INFO L290 TraceCheckUtils]: 58: Hoare triple {34286#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34286#false} is VALID [2022-02-21 04:24:24,944 INFO L290 TraceCheckUtils]: 59: Hoare triple {34286#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {34286#false} is VALID [2022-02-21 04:24:24,944 INFO L290 TraceCheckUtils]: 60: Hoare triple {34286#false} assume !(0 != activate_threads_~tmp___3~0#1); {34286#false} is VALID [2022-02-21 04:24:24,944 INFO L290 TraceCheckUtils]: 61: Hoare triple {34286#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34286#false} is VALID [2022-02-21 04:24:24,945 INFO L290 TraceCheckUtils]: 62: Hoare triple {34286#false} assume !(1 == ~t5_pc~0); {34286#false} is VALID [2022-02-21 04:24:24,945 INFO L290 TraceCheckUtils]: 63: Hoare triple {34286#false} is_transmit5_triggered_~__retres1~5#1 := 0; {34286#false} is VALID [2022-02-21 04:24:24,945 INFO L290 TraceCheckUtils]: 64: Hoare triple {34286#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34286#false} is VALID [2022-02-21 04:24:24,945 INFO L290 TraceCheckUtils]: 65: Hoare triple {34286#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {34286#false} is VALID [2022-02-21 04:24:24,945 INFO L290 TraceCheckUtils]: 66: Hoare triple {34286#false} assume !(0 != activate_threads_~tmp___4~0#1); {34286#false} is VALID [2022-02-21 04:24:24,945 INFO L290 TraceCheckUtils]: 67: Hoare triple {34286#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34286#false} is VALID [2022-02-21 04:24:24,945 INFO L290 TraceCheckUtils]: 68: Hoare triple {34286#false} assume 1 == ~t6_pc~0; {34286#false} is VALID [2022-02-21 04:24:24,945 INFO L290 TraceCheckUtils]: 69: Hoare triple {34286#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {34286#false} is VALID [2022-02-21 04:24:24,945 INFO L290 TraceCheckUtils]: 70: Hoare triple {34286#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34286#false} is VALID [2022-02-21 04:24:24,946 INFO L290 TraceCheckUtils]: 71: Hoare triple {34286#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34286#false} is VALID [2022-02-21 04:24:24,946 INFO L290 TraceCheckUtils]: 72: Hoare triple {34286#false} assume !(0 != activate_threads_~tmp___5~0#1); {34286#false} is VALID [2022-02-21 04:24:24,946 INFO L290 TraceCheckUtils]: 73: Hoare triple {34286#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34286#false} is VALID [2022-02-21 04:24:24,946 INFO L290 TraceCheckUtils]: 74: Hoare triple {34286#false} assume !(1 == ~t7_pc~0); {34286#false} is VALID [2022-02-21 04:24:24,946 INFO L290 TraceCheckUtils]: 75: Hoare triple {34286#false} is_transmit7_triggered_~__retres1~7#1 := 0; {34286#false} is VALID [2022-02-21 04:24:24,946 INFO L290 TraceCheckUtils]: 76: Hoare triple {34286#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34286#false} is VALID [2022-02-21 04:24:24,946 INFO L290 TraceCheckUtils]: 77: Hoare triple {34286#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34286#false} is VALID [2022-02-21 04:24:24,946 INFO L290 TraceCheckUtils]: 78: Hoare triple {34286#false} assume !(0 != activate_threads_~tmp___6~0#1); {34286#false} is VALID [2022-02-21 04:24:24,946 INFO L290 TraceCheckUtils]: 79: Hoare triple {34286#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34286#false} is VALID [2022-02-21 04:24:24,947 INFO L290 TraceCheckUtils]: 80: Hoare triple {34286#false} assume 1 == ~t8_pc~0; {34286#false} is VALID [2022-02-21 04:24:24,947 INFO L290 TraceCheckUtils]: 81: Hoare triple {34286#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {34286#false} is VALID [2022-02-21 04:24:24,947 INFO L290 TraceCheckUtils]: 82: Hoare triple {34286#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34286#false} is VALID [2022-02-21 04:24:24,947 INFO L290 TraceCheckUtils]: 83: Hoare triple {34286#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34286#false} is VALID [2022-02-21 04:24:24,947 INFO L290 TraceCheckUtils]: 84: Hoare triple {34286#false} assume !(0 != activate_threads_~tmp___7~0#1); {34286#false} is VALID [2022-02-21 04:24:24,947 INFO L290 TraceCheckUtils]: 85: Hoare triple {34286#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34286#false} is VALID [2022-02-21 04:24:24,947 INFO L290 TraceCheckUtils]: 86: Hoare triple {34286#false} assume !(1 == ~M_E~0); {34286#false} is VALID [2022-02-21 04:24:24,947 INFO L290 TraceCheckUtils]: 87: Hoare triple {34286#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {34286#false} is VALID [2022-02-21 04:24:24,947 INFO L290 TraceCheckUtils]: 88: Hoare triple {34286#false} assume !(1 == ~T2_E~0); {34286#false} is VALID [2022-02-21 04:24:24,948 INFO L290 TraceCheckUtils]: 89: Hoare triple {34286#false} assume !(1 == ~T3_E~0); {34286#false} is VALID [2022-02-21 04:24:24,948 INFO L290 TraceCheckUtils]: 90: Hoare triple {34286#false} assume !(1 == ~T4_E~0); {34286#false} is VALID [2022-02-21 04:24:24,948 INFO L290 TraceCheckUtils]: 91: Hoare triple {34286#false} assume !(1 == ~T5_E~0); {34286#false} is VALID [2022-02-21 04:24:24,948 INFO L290 TraceCheckUtils]: 92: Hoare triple {34286#false} assume !(1 == ~T6_E~0); {34286#false} is VALID [2022-02-21 04:24:24,948 INFO L290 TraceCheckUtils]: 93: Hoare triple {34286#false} assume !(1 == ~T7_E~0); {34286#false} is VALID [2022-02-21 04:24:24,948 INFO L290 TraceCheckUtils]: 94: Hoare triple {34286#false} assume !(1 == ~T8_E~0); {34286#false} is VALID [2022-02-21 04:24:24,948 INFO L290 TraceCheckUtils]: 95: Hoare triple {34286#false} assume 1 == ~E_1~0;~E_1~0 := 2; {34286#false} is VALID [2022-02-21 04:24:24,948 INFO L290 TraceCheckUtils]: 96: Hoare triple {34286#false} assume !(1 == ~E_2~0); {34286#false} is VALID [2022-02-21 04:24:24,948 INFO L290 TraceCheckUtils]: 97: Hoare triple {34286#false} assume !(1 == ~E_3~0); {34286#false} is VALID [2022-02-21 04:24:24,949 INFO L290 TraceCheckUtils]: 98: Hoare triple {34286#false} assume !(1 == ~E_4~0); {34286#false} is VALID [2022-02-21 04:24:24,949 INFO L290 TraceCheckUtils]: 99: Hoare triple {34286#false} assume !(1 == ~E_5~0); {34286#false} is VALID [2022-02-21 04:24:24,949 INFO L290 TraceCheckUtils]: 100: Hoare triple {34286#false} assume !(1 == ~E_6~0); {34286#false} is VALID [2022-02-21 04:24:24,949 INFO L290 TraceCheckUtils]: 101: Hoare triple {34286#false} assume !(1 == ~E_7~0); {34286#false} is VALID [2022-02-21 04:24:24,949 INFO L290 TraceCheckUtils]: 102: Hoare triple {34286#false} assume !(1 == ~E_8~0); {34286#false} is VALID [2022-02-21 04:24:24,949 INFO L290 TraceCheckUtils]: 103: Hoare triple {34286#false} assume { :end_inline_reset_delta_events } true; {34286#false} is VALID [2022-02-21 04:24:24,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,950 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,950 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439043713] [2022-02-21 04:24:24,950 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1439043713] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,950 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,950 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:24,950 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1207365387] [2022-02-21 04:24:24,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,951 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:24,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:24,951 INFO L85 PathProgramCache]: Analyzing trace with hash -5807806, now seen corresponding path program 1 times [2022-02-21 04:24:24,951 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:24,951 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276868846] [2022-02-21 04:24:24,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:24,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:24,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,972 INFO L290 TraceCheckUtils]: 0: Hoare triple {34289#true} assume !false; {34289#true} is VALID [2022-02-21 04:24:24,973 INFO L290 TraceCheckUtils]: 1: Hoare triple {34289#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {34289#true} is VALID [2022-02-21 04:24:24,973 INFO L290 TraceCheckUtils]: 2: Hoare triple {34289#true} assume !false; {34289#true} is VALID [2022-02-21 04:24:24,973 INFO L290 TraceCheckUtils]: 3: Hoare triple {34289#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {34289#true} is VALID [2022-02-21 04:24:24,973 INFO L290 TraceCheckUtils]: 4: Hoare triple {34289#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {34289#true} is VALID [2022-02-21 04:24:24,973 INFO L290 TraceCheckUtils]: 5: Hoare triple {34289#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {34289#true} is VALID [2022-02-21 04:24:24,973 INFO L290 TraceCheckUtils]: 6: Hoare triple {34289#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {34289#true} is VALID [2022-02-21 04:24:24,973 INFO L290 TraceCheckUtils]: 7: Hoare triple {34289#true} assume !(0 != eval_~tmp~0#1); {34289#true} is VALID [2022-02-21 04:24:24,973 INFO L290 TraceCheckUtils]: 8: Hoare triple {34289#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {34289#true} is VALID [2022-02-21 04:24:24,974 INFO L290 TraceCheckUtils]: 9: Hoare triple {34289#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {34289#true} is VALID [2022-02-21 04:24:24,974 INFO L290 TraceCheckUtils]: 10: Hoare triple {34289#true} assume !(0 == ~M_E~0); {34289#true} is VALID [2022-02-21 04:24:24,974 INFO L290 TraceCheckUtils]: 11: Hoare triple {34289#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {34289#true} is VALID [2022-02-21 04:24:24,974 INFO L290 TraceCheckUtils]: 12: Hoare triple {34289#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {34289#true} is VALID [2022-02-21 04:24:24,974 INFO L290 TraceCheckUtils]: 13: Hoare triple {34289#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {34289#true} is VALID [2022-02-21 04:24:24,974 INFO L290 TraceCheckUtils]: 14: Hoare triple {34289#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,975 INFO L290 TraceCheckUtils]: 15: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T5_E~0); {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,975 INFO L290 TraceCheckUtils]: 16: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,975 INFO L290 TraceCheckUtils]: 17: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,975 INFO L290 TraceCheckUtils]: 18: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,976 INFO L290 TraceCheckUtils]: 19: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,976 INFO L290 TraceCheckUtils]: 20: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,976 INFO L290 TraceCheckUtils]: 21: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,976 INFO L290 TraceCheckUtils]: 22: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,977 INFO L290 TraceCheckUtils]: 23: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,977 INFO L290 TraceCheckUtils]: 24: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,977 INFO L290 TraceCheckUtils]: 25: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,977 INFO L290 TraceCheckUtils]: 26: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,978 INFO L290 TraceCheckUtils]: 27: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,978 INFO L290 TraceCheckUtils]: 28: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~m_pc~0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,978 INFO L290 TraceCheckUtils]: 29: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,979 INFO L290 TraceCheckUtils]: 30: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,979 INFO L290 TraceCheckUtils]: 31: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,979 INFO L290 TraceCheckUtils]: 32: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,979 INFO L290 TraceCheckUtils]: 33: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,980 INFO L290 TraceCheckUtils]: 34: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t1_pc~0); {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,980 INFO L290 TraceCheckUtils]: 35: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,980 INFO L290 TraceCheckUtils]: 36: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,980 INFO L290 TraceCheckUtils]: 37: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,981 INFO L290 TraceCheckUtils]: 38: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,981 INFO L290 TraceCheckUtils]: 39: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,981 INFO L290 TraceCheckUtils]: 40: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t2_pc~0); {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,981 INFO L290 TraceCheckUtils]: 41: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,982 INFO L290 TraceCheckUtils]: 42: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,982 INFO L290 TraceCheckUtils]: 43: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,982 INFO L290 TraceCheckUtils]: 44: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,982 INFO L290 TraceCheckUtils]: 45: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,983 INFO L290 TraceCheckUtils]: 46: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t3_pc~0); {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,983 INFO L290 TraceCheckUtils]: 47: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,983 INFO L290 TraceCheckUtils]: 48: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,983 INFO L290 TraceCheckUtils]: 49: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,984 INFO L290 TraceCheckUtils]: 50: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,984 INFO L290 TraceCheckUtils]: 51: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,984 INFO L290 TraceCheckUtils]: 52: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t4_pc~0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,985 INFO L290 TraceCheckUtils]: 53: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,985 INFO L290 TraceCheckUtils]: 54: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,985 INFO L290 TraceCheckUtils]: 55: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,985 INFO L290 TraceCheckUtils]: 56: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,986 INFO L290 TraceCheckUtils]: 57: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,986 INFO L290 TraceCheckUtils]: 58: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t5_pc~0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,986 INFO L290 TraceCheckUtils]: 59: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,986 INFO L290 TraceCheckUtils]: 60: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,987 INFO L290 TraceCheckUtils]: 61: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,987 INFO L290 TraceCheckUtils]: 62: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,987 INFO L290 TraceCheckUtils]: 63: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,987 INFO L290 TraceCheckUtils]: 64: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t6_pc~0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,988 INFO L290 TraceCheckUtils]: 65: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,988 INFO L290 TraceCheckUtils]: 66: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,988 INFO L290 TraceCheckUtils]: 67: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,988 INFO L290 TraceCheckUtils]: 68: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,989 INFO L290 TraceCheckUtils]: 69: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,989 INFO L290 TraceCheckUtils]: 70: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t7_pc~0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,989 INFO L290 TraceCheckUtils]: 71: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,989 INFO L290 TraceCheckUtils]: 72: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,990 INFO L290 TraceCheckUtils]: 73: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,990 INFO L290 TraceCheckUtils]: 74: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,990 INFO L290 TraceCheckUtils]: 75: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,990 INFO L290 TraceCheckUtils]: 76: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t8_pc~0; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,991 INFO L290 TraceCheckUtils]: 77: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,991 INFO L290 TraceCheckUtils]: 78: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,991 INFO L290 TraceCheckUtils]: 79: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,992 INFO L290 TraceCheckUtils]: 80: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,992 INFO L290 TraceCheckUtils]: 81: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,992 INFO L290 TraceCheckUtils]: 82: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,992 INFO L290 TraceCheckUtils]: 83: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,993 INFO L290 TraceCheckUtils]: 84: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,993 INFO L290 TraceCheckUtils]: 85: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34291#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:24,993 INFO L290 TraceCheckUtils]: 86: Hoare triple {34291#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {34290#false} is VALID [2022-02-21 04:24:24,993 INFO L290 TraceCheckUtils]: 87: Hoare triple {34290#false} assume !(1 == ~T5_E~0); {34290#false} is VALID [2022-02-21 04:24:24,993 INFO L290 TraceCheckUtils]: 88: Hoare triple {34290#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {34290#false} is VALID [2022-02-21 04:24:24,993 INFO L290 TraceCheckUtils]: 89: Hoare triple {34290#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {34290#false} is VALID [2022-02-21 04:24:24,994 INFO L290 TraceCheckUtils]: 90: Hoare triple {34290#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {34290#false} is VALID [2022-02-21 04:24:24,994 INFO L290 TraceCheckUtils]: 91: Hoare triple {34290#false} assume 1 == ~E_1~0;~E_1~0 := 2; {34290#false} is VALID [2022-02-21 04:24:24,994 INFO L290 TraceCheckUtils]: 92: Hoare triple {34290#false} assume 1 == ~E_2~0;~E_2~0 := 2; {34290#false} is VALID [2022-02-21 04:24:24,994 INFO L290 TraceCheckUtils]: 93: Hoare triple {34290#false} assume 1 == ~E_3~0;~E_3~0 := 2; {34290#false} is VALID [2022-02-21 04:24:24,994 INFO L290 TraceCheckUtils]: 94: Hoare triple {34290#false} assume !(1 == ~E_4~0); {34290#false} is VALID [2022-02-21 04:24:24,994 INFO L290 TraceCheckUtils]: 95: Hoare triple {34290#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34290#false} is VALID [2022-02-21 04:24:24,994 INFO L290 TraceCheckUtils]: 96: Hoare triple {34290#false} assume 1 == ~E_6~0;~E_6~0 := 2; {34290#false} is VALID [2022-02-21 04:24:24,994 INFO L290 TraceCheckUtils]: 97: Hoare triple {34290#false} assume 1 == ~E_7~0;~E_7~0 := 2; {34290#false} is VALID [2022-02-21 04:24:24,994 INFO L290 TraceCheckUtils]: 98: Hoare triple {34290#false} assume 1 == ~E_8~0;~E_8~0 := 2; {34290#false} is VALID [2022-02-21 04:24:24,995 INFO L290 TraceCheckUtils]: 99: Hoare triple {34290#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {34290#false} is VALID [2022-02-21 04:24:24,995 INFO L290 TraceCheckUtils]: 100: Hoare triple {34290#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {34290#false} is VALID [2022-02-21 04:24:24,995 INFO L290 TraceCheckUtils]: 101: Hoare triple {34290#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {34290#false} is VALID [2022-02-21 04:24:24,995 INFO L290 TraceCheckUtils]: 102: Hoare triple {34290#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {34290#false} is VALID [2022-02-21 04:24:24,995 INFO L290 TraceCheckUtils]: 103: Hoare triple {34290#false} assume !(0 == start_simulation_~tmp~3#1); {34290#false} is VALID [2022-02-21 04:24:24,995 INFO L290 TraceCheckUtils]: 104: Hoare triple {34290#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {34290#false} is VALID [2022-02-21 04:24:24,995 INFO L290 TraceCheckUtils]: 105: Hoare triple {34290#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {34290#false} is VALID [2022-02-21 04:24:24,995 INFO L290 TraceCheckUtils]: 106: Hoare triple {34290#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {34290#false} is VALID [2022-02-21 04:24:24,995 INFO L290 TraceCheckUtils]: 107: Hoare triple {34290#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {34290#false} is VALID [2022-02-21 04:24:24,996 INFO L290 TraceCheckUtils]: 108: Hoare triple {34290#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {34290#false} is VALID [2022-02-21 04:24:24,996 INFO L290 TraceCheckUtils]: 109: Hoare triple {34290#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {34290#false} is VALID [2022-02-21 04:24:24,996 INFO L290 TraceCheckUtils]: 110: Hoare triple {34290#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {34290#false} is VALID [2022-02-21 04:24:24,996 INFO L290 TraceCheckUtils]: 111: Hoare triple {34290#false} assume !(0 != start_simulation_~tmp___0~1#1); {34290#false} is VALID [2022-02-21 04:24:24,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,996 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,997 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276868846] [2022-02-21 04:24:24,997 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276868846] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,997 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,997 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:24,997 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132652474] [2022-02-21 04:24:24,997 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,997 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:24,998 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:24,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:24,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:24,998 INFO L87 Difference]: Start difference. First operand 924 states and 1367 transitions. cyclomatic complexity: 444 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,671 INFO L93 Difference]: Finished difference Result 1686 states and 2493 transitions. [2022-02-21 04:24:26,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:26,672 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,726 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:26,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1686 states and 2493 transitions. [2022-02-21 04:24:26,788 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1557 [2022-02-21 04:24:26,851 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1686 states to 1686 states and 2493 transitions. [2022-02-21 04:24:26,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1686 [2022-02-21 04:24:26,852 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1686 [2022-02-21 04:24:26,852 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1686 states and 2493 transitions. [2022-02-21 04:24:26,853 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:26,854 INFO L681 BuchiCegarLoop]: Abstraction has 1686 states and 2493 transitions. [2022-02-21 04:24:26,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1686 states and 2493 transitions. [2022-02-21 04:24:26,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1686 to 1685. [2022-02-21 04:24:26,869 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:26,871 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1686 states and 2493 transitions. Second operand has 1685 states, 1685 states have (on average 1.4789317507418398) internal successors, (2492), 1684 states have internal predecessors, (2492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,872 INFO L74 IsIncluded]: Start isIncluded. First operand 1686 states and 2493 transitions. Second operand has 1685 states, 1685 states have (on average 1.4789317507418398) internal successors, (2492), 1684 states have internal predecessors, (2492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,874 INFO L87 Difference]: Start difference. First operand 1686 states and 2493 transitions. Second operand has 1685 states, 1685 states have (on average 1.4789317507418398) internal successors, (2492), 1684 states have internal predecessors, (2492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,937 INFO L93 Difference]: Finished difference Result 1686 states and 2493 transitions. [2022-02-21 04:24:26,937 INFO L276 IsEmpty]: Start isEmpty. Operand 1686 states and 2493 transitions. [2022-02-21 04:24:26,939 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:26,939 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:26,941 INFO L74 IsIncluded]: Start isIncluded. First operand has 1685 states, 1685 states have (on average 1.4789317507418398) internal successors, (2492), 1684 states have internal predecessors, (2492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1686 states and 2493 transitions. [2022-02-21 04:24:26,942 INFO L87 Difference]: Start difference. First operand has 1685 states, 1685 states have (on average 1.4789317507418398) internal successors, (2492), 1684 states have internal predecessors, (2492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1686 states and 2493 transitions. [2022-02-21 04:24:27,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:27,003 INFO L93 Difference]: Finished difference Result 1686 states and 2493 transitions. [2022-02-21 04:24:27,003 INFO L276 IsEmpty]: Start isEmpty. Operand 1686 states and 2493 transitions. [2022-02-21 04:24:27,005 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:27,005 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:27,005 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:27,005 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:27,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1685 states, 1685 states have (on average 1.4789317507418398) internal successors, (2492), 1684 states have internal predecessors, (2492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1685 states to 1685 states and 2492 transitions. [2022-02-21 04:24:27,072 INFO L704 BuchiCegarLoop]: Abstraction has 1685 states and 2492 transitions. [2022-02-21 04:24:27,073 INFO L587 BuchiCegarLoop]: Abstraction has 1685 states and 2492 transitions. [2022-02-21 04:24:27,073 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:24:27,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1685 states and 2492 transitions. [2022-02-21 04:24:27,076 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1557 [2022-02-21 04:24:27,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:27,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:27,077 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:27,077 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:27,077 INFO L791 eck$LassoCheckResult]: Stem: 36664#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 36665#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 36947#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36071#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36072#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 36344#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36345#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36876#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36863#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36412#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36413#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36643#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36644#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36494#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36495#L838 assume !(0 == ~M_E~0); 36650#L838-2 assume !(0 == ~T1_E~0); 36033#L843-1 assume !(0 == ~T2_E~0); 36034#L848-1 assume !(0 == ~T3_E~0); 36154#L853-1 assume !(0 == ~T4_E~0); 36480#L858-1 assume !(0 == ~T5_E~0); 35980#L863-1 assume !(0 == ~T6_E~0); 35981#L868-1 assume !(0 == ~T7_E~0); 36916#L873-1 assume !(0 == ~T8_E~0); 36914#L878-1 assume !(0 == ~E_1~0); 36899#L883-1 assume !(0 == ~E_2~0); 36900#L888-1 assume !(0 == ~E_3~0); 36614#L893-1 assume !(0 == ~E_4~0); 36615#L898-1 assume !(0 == ~E_5~0); 36931#L903-1 assume !(0 == ~E_6~0); 36898#L908-1 assume !(0 == ~E_7~0); 36748#L913-1 assume !(0 == ~E_8~0); 36047#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36048#L402 assume !(1 == ~m_pc~0); 36257#L402-2 is_master_triggered_~__retres1~0#1 := 0; 36175#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36176#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 36418#L1035 assume !(0 != activate_threads_~tmp~1#1); 36419#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36471#L421 assume 1 == ~t1_pc~0; 36894#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36918#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36463#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 36464#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 36522#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36926#L440 assume 1 == ~t2_pc~0; 36017#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36018#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36185#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36940#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 36765#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36372#L459 assume !(1 == ~t3_pc~0); 36373#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 36890#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36688#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36169#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36170#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36179#L478 assume 1 == ~t4_pc~0; 36180#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36619#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36875#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36350#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 36092#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36093#L497 assume !(1 == ~t5_pc~0); 36139#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 36140#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36432#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36433#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 36882#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36883#L516 assume 1 == ~t6_pc~0; 36953#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36641#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36642#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36224#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 36225#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36632#L535 assume !(1 == ~t7_pc~0); 36633#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 36707#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36708#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36739#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 36729#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36730#L554 assume 1 == ~t8_pc~0; 36672#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36009#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36785#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36312#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 36313#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35993#L931 assume !(1 == ~M_E~0); 35994#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36909#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36937#L941-1 assume !(1 == ~T3_E~0); 37432#L946-1 assume !(1 == ~T4_E~0); 36891#L951-1 assume !(1 == ~T5_E~0); 36239#L956-1 assume !(1 == ~T6_E~0); 36240#L961-1 assume !(1 == ~T7_E~0); 36616#L966-1 assume !(1 == ~T8_E~0); 36617#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 36732#L976-1 assume !(1 == ~E_2~0); 36699#L981-1 assume !(1 == ~E_3~0); 36477#L986-1 assume !(1 == ~E_4~0); 36269#L991-1 assume !(1 == ~E_5~0); 36270#L996-1 assume !(1 == ~E_6~0); 36922#L1001-1 assume !(1 == ~E_7~0); 36662#L1006-1 assume !(1 == ~E_8~0); 36663#L1011-1 assume { :end_inline_reset_delta_events } true; 36974#L1272-2 [2022-02-21 04:24:27,077 INFO L793 eck$LassoCheckResult]: Loop: 36974#L1272-2 assume !false; 36654#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36058#L813 assume !false; 36059#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 36966#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 36610#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 36611#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 36840#L696 assume !(0 != eval_~tmp~0#1); 36666#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36667#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36868#L838-3 assume !(0 == ~M_E~0); 36869#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36955#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36956#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37664#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37663#L858-3 assume !(0 == ~T5_E~0); 37662#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37661#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37660#L873-3 assume !(0 == ~T8_E~0); 37659#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37658#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37657#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37656#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37655#L898-3 assume !(0 == ~E_5~0); 37654#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37653#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37652#L913-3 assume !(0 == ~E_8~0); 37651#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37650#L402-27 assume 1 == ~m_pc~0; 37648#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37647#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37646#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37645#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37644#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37643#L421-27 assume 1 == ~t1_pc~0; 37641#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37640#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37639#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 37638#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37637#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37636#L440-27 assume 1 == ~t2_pc~0; 37634#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37633#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37632#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37631#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37630#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37629#L459-27 assume !(1 == ~t3_pc~0); 37627#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 37626#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37625#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37624#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37623#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37622#L478-27 assume 1 == ~t4_pc~0; 37620#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37619#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37618#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37617#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37616#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37615#L497-27 assume !(1 == ~t5_pc~0); 37613#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 37612#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37611#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37610#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37609#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37608#L516-27 assume 1 == ~t6_pc~0; 36558#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36358#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36359#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36506#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36652#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36435#L535-27 assume 1 == ~t7_pc~0; 36436#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36769#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36803#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36804#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36389#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36390#L554-27 assume !(1 == ~t8_pc~0); 36037#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 36038#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36184#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36523#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 36289#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36290#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36165#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36166#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36386#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36518#L946-3 assume !(1 == ~T4_E~0); 36307#L951-3 assume !(1 == ~T5_E~0); 36308#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36590#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36396#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36397#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36640#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36054#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36055#L986-3 assume !(1 == ~E_4~0); 36045#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36046#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36718#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 36377#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36378#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 36087#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 36089#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 36404#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 36405#L1291 assume !(0 == start_simulation_~tmp~3#1); 36587#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 36490#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 35984#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 35985#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 36811#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36987#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36678#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 36679#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 36974#L1272-2 [2022-02-21 04:24:27,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:27,078 INFO L85 PathProgramCache]: Analyzing trace with hash 1671526308, now seen corresponding path program 1 times [2022-02-21 04:24:27,078 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:27,078 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720208223] [2022-02-21 04:24:27,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:27,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:27,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:27,105 INFO L290 TraceCheckUtils]: 0: Hoare triple {41040#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,106 INFO L290 TraceCheckUtils]: 1: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,106 INFO L290 TraceCheckUtils]: 2: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,107 INFO L290 TraceCheckUtils]: 3: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,107 INFO L290 TraceCheckUtils]: 4: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,107 INFO L290 TraceCheckUtils]: 5: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,107 INFO L290 TraceCheckUtils]: 6: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,108 INFO L290 TraceCheckUtils]: 7: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,108 INFO L290 TraceCheckUtils]: 8: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,108 INFO L290 TraceCheckUtils]: 9: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,109 INFO L290 TraceCheckUtils]: 10: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,109 INFO L290 TraceCheckUtils]: 11: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,109 INFO L290 TraceCheckUtils]: 12: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,110 INFO L290 TraceCheckUtils]: 13: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,110 INFO L290 TraceCheckUtils]: 14: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,110 INFO L290 TraceCheckUtils]: 15: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,110 INFO L290 TraceCheckUtils]: 16: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,111 INFO L290 TraceCheckUtils]: 17: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,111 INFO L290 TraceCheckUtils]: 18: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,111 INFO L290 TraceCheckUtils]: 19: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T5_E~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,112 INFO L290 TraceCheckUtils]: 20: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T6_E~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,112 INFO L290 TraceCheckUtils]: 21: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T7_E~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,112 INFO L290 TraceCheckUtils]: 22: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T8_E~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,112 INFO L290 TraceCheckUtils]: 23: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,113 INFO L290 TraceCheckUtils]: 24: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,113 INFO L290 TraceCheckUtils]: 25: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,113 INFO L290 TraceCheckUtils]: 26: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,114 INFO L290 TraceCheckUtils]: 27: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_5~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,114 INFO L290 TraceCheckUtils]: 28: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_6~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,114 INFO L290 TraceCheckUtils]: 29: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_7~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,114 INFO L290 TraceCheckUtils]: 30: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_8~0); {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,115 INFO L290 TraceCheckUtils]: 31: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {41042#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:27,115 INFO L290 TraceCheckUtils]: 32: Hoare triple {41042#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {41043#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:27,115 INFO L290 TraceCheckUtils]: 33: Hoare triple {41043#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {41043#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:27,116 INFO L290 TraceCheckUtils]: 34: Hoare triple {41043#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {41043#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:27,116 INFO L290 TraceCheckUtils]: 35: Hoare triple {41043#(not (= ~t1_pc~0 1))} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {41043#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:27,116 INFO L290 TraceCheckUtils]: 36: Hoare triple {41043#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {41043#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:27,116 INFO L290 TraceCheckUtils]: 37: Hoare triple {41043#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {41043#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:27,117 INFO L290 TraceCheckUtils]: 38: Hoare triple {41043#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {41041#false} is VALID [2022-02-21 04:24:27,117 INFO L290 TraceCheckUtils]: 39: Hoare triple {41041#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {41041#false} is VALID [2022-02-21 04:24:27,117 INFO L290 TraceCheckUtils]: 40: Hoare triple {41041#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {41041#false} is VALID [2022-02-21 04:24:27,117 INFO L290 TraceCheckUtils]: 41: Hoare triple {41041#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {41041#false} is VALID [2022-02-21 04:24:27,117 INFO L290 TraceCheckUtils]: 42: Hoare triple {41041#false} assume !(0 != activate_threads_~tmp___0~0#1); {41041#false} is VALID [2022-02-21 04:24:27,117 INFO L290 TraceCheckUtils]: 43: Hoare triple {41041#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {41041#false} is VALID [2022-02-21 04:24:27,117 INFO L290 TraceCheckUtils]: 44: Hoare triple {41041#false} assume 1 == ~t2_pc~0; {41041#false} is VALID [2022-02-21 04:24:27,117 INFO L290 TraceCheckUtils]: 45: Hoare triple {41041#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {41041#false} is VALID [2022-02-21 04:24:27,118 INFO L290 TraceCheckUtils]: 46: Hoare triple {41041#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {41041#false} is VALID [2022-02-21 04:24:27,118 INFO L290 TraceCheckUtils]: 47: Hoare triple {41041#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {41041#false} is VALID [2022-02-21 04:24:27,118 INFO L290 TraceCheckUtils]: 48: Hoare triple {41041#false} assume !(0 != activate_threads_~tmp___1~0#1); {41041#false} is VALID [2022-02-21 04:24:27,118 INFO L290 TraceCheckUtils]: 49: Hoare triple {41041#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {41041#false} is VALID [2022-02-21 04:24:27,118 INFO L290 TraceCheckUtils]: 50: Hoare triple {41041#false} assume !(1 == ~t3_pc~0); {41041#false} is VALID [2022-02-21 04:24:27,118 INFO L290 TraceCheckUtils]: 51: Hoare triple {41041#false} is_transmit3_triggered_~__retres1~3#1 := 0; {41041#false} is VALID [2022-02-21 04:24:27,118 INFO L290 TraceCheckUtils]: 52: Hoare triple {41041#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {41041#false} is VALID [2022-02-21 04:24:27,118 INFO L290 TraceCheckUtils]: 53: Hoare triple {41041#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {41041#false} is VALID [2022-02-21 04:24:27,118 INFO L290 TraceCheckUtils]: 54: Hoare triple {41041#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {41041#false} is VALID [2022-02-21 04:24:27,119 INFO L290 TraceCheckUtils]: 55: Hoare triple {41041#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {41041#false} is VALID [2022-02-21 04:24:27,119 INFO L290 TraceCheckUtils]: 56: Hoare triple {41041#false} assume 1 == ~t4_pc~0; {41041#false} is VALID [2022-02-21 04:24:27,119 INFO L290 TraceCheckUtils]: 57: Hoare triple {41041#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {41041#false} is VALID [2022-02-21 04:24:27,119 INFO L290 TraceCheckUtils]: 58: Hoare triple {41041#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {41041#false} is VALID [2022-02-21 04:24:27,119 INFO L290 TraceCheckUtils]: 59: Hoare triple {41041#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {41041#false} is VALID [2022-02-21 04:24:27,119 INFO L290 TraceCheckUtils]: 60: Hoare triple {41041#false} assume !(0 != activate_threads_~tmp___3~0#1); {41041#false} is VALID [2022-02-21 04:24:27,119 INFO L290 TraceCheckUtils]: 61: Hoare triple {41041#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {41041#false} is VALID [2022-02-21 04:24:27,119 INFO L290 TraceCheckUtils]: 62: Hoare triple {41041#false} assume !(1 == ~t5_pc~0); {41041#false} is VALID [2022-02-21 04:24:27,119 INFO L290 TraceCheckUtils]: 63: Hoare triple {41041#false} is_transmit5_triggered_~__retres1~5#1 := 0; {41041#false} is VALID [2022-02-21 04:24:27,120 INFO L290 TraceCheckUtils]: 64: Hoare triple {41041#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {41041#false} is VALID [2022-02-21 04:24:27,120 INFO L290 TraceCheckUtils]: 65: Hoare triple {41041#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {41041#false} is VALID [2022-02-21 04:24:27,120 INFO L290 TraceCheckUtils]: 66: Hoare triple {41041#false} assume !(0 != activate_threads_~tmp___4~0#1); {41041#false} is VALID [2022-02-21 04:24:27,120 INFO L290 TraceCheckUtils]: 67: Hoare triple {41041#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {41041#false} is VALID [2022-02-21 04:24:27,120 INFO L290 TraceCheckUtils]: 68: Hoare triple {41041#false} assume 1 == ~t6_pc~0; {41041#false} is VALID [2022-02-21 04:24:27,120 INFO L290 TraceCheckUtils]: 69: Hoare triple {41041#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {41041#false} is VALID [2022-02-21 04:24:27,120 INFO L290 TraceCheckUtils]: 70: Hoare triple {41041#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {41041#false} is VALID [2022-02-21 04:24:27,120 INFO L290 TraceCheckUtils]: 71: Hoare triple {41041#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {41041#false} is VALID [2022-02-21 04:24:27,120 INFO L290 TraceCheckUtils]: 72: Hoare triple {41041#false} assume !(0 != activate_threads_~tmp___5~0#1); {41041#false} is VALID [2022-02-21 04:24:27,121 INFO L290 TraceCheckUtils]: 73: Hoare triple {41041#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {41041#false} is VALID [2022-02-21 04:24:27,121 INFO L290 TraceCheckUtils]: 74: Hoare triple {41041#false} assume !(1 == ~t7_pc~0); {41041#false} is VALID [2022-02-21 04:24:27,121 INFO L290 TraceCheckUtils]: 75: Hoare triple {41041#false} is_transmit7_triggered_~__retres1~7#1 := 0; {41041#false} is VALID [2022-02-21 04:24:27,121 INFO L290 TraceCheckUtils]: 76: Hoare triple {41041#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {41041#false} is VALID [2022-02-21 04:24:27,121 INFO L290 TraceCheckUtils]: 77: Hoare triple {41041#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {41041#false} is VALID [2022-02-21 04:24:27,121 INFO L290 TraceCheckUtils]: 78: Hoare triple {41041#false} assume !(0 != activate_threads_~tmp___6~0#1); {41041#false} is VALID [2022-02-21 04:24:27,121 INFO L290 TraceCheckUtils]: 79: Hoare triple {41041#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {41041#false} is VALID [2022-02-21 04:24:27,121 INFO L290 TraceCheckUtils]: 80: Hoare triple {41041#false} assume 1 == ~t8_pc~0; {41041#false} is VALID [2022-02-21 04:24:27,121 INFO L290 TraceCheckUtils]: 81: Hoare triple {41041#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {41041#false} is VALID [2022-02-21 04:24:27,122 INFO L290 TraceCheckUtils]: 82: Hoare triple {41041#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {41041#false} is VALID [2022-02-21 04:24:27,122 INFO L290 TraceCheckUtils]: 83: Hoare triple {41041#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {41041#false} is VALID [2022-02-21 04:24:27,122 INFO L290 TraceCheckUtils]: 84: Hoare triple {41041#false} assume !(0 != activate_threads_~tmp___7~0#1); {41041#false} is VALID [2022-02-21 04:24:27,122 INFO L290 TraceCheckUtils]: 85: Hoare triple {41041#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {41041#false} is VALID [2022-02-21 04:24:27,122 INFO L290 TraceCheckUtils]: 86: Hoare triple {41041#false} assume !(1 == ~M_E~0); {41041#false} is VALID [2022-02-21 04:24:27,122 INFO L290 TraceCheckUtils]: 87: Hoare triple {41041#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {41041#false} is VALID [2022-02-21 04:24:27,122 INFO L290 TraceCheckUtils]: 88: Hoare triple {41041#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {41041#false} is VALID [2022-02-21 04:24:27,122 INFO L290 TraceCheckUtils]: 89: Hoare triple {41041#false} assume !(1 == ~T3_E~0); {41041#false} is VALID [2022-02-21 04:24:27,122 INFO L290 TraceCheckUtils]: 90: Hoare triple {41041#false} assume !(1 == ~T4_E~0); {41041#false} is VALID [2022-02-21 04:24:27,122 INFO L290 TraceCheckUtils]: 91: Hoare triple {41041#false} assume !(1 == ~T5_E~0); {41041#false} is VALID [2022-02-21 04:24:27,123 INFO L290 TraceCheckUtils]: 92: Hoare triple {41041#false} assume !(1 == ~T6_E~0); {41041#false} is VALID [2022-02-21 04:24:27,123 INFO L290 TraceCheckUtils]: 93: Hoare triple {41041#false} assume !(1 == ~T7_E~0); {41041#false} is VALID [2022-02-21 04:24:27,123 INFO L290 TraceCheckUtils]: 94: Hoare triple {41041#false} assume !(1 == ~T8_E~0); {41041#false} is VALID [2022-02-21 04:24:27,123 INFO L290 TraceCheckUtils]: 95: Hoare triple {41041#false} assume 1 == ~E_1~0;~E_1~0 := 2; {41041#false} is VALID [2022-02-21 04:24:27,123 INFO L290 TraceCheckUtils]: 96: Hoare triple {41041#false} assume !(1 == ~E_2~0); {41041#false} is VALID [2022-02-21 04:24:27,123 INFO L290 TraceCheckUtils]: 97: Hoare triple {41041#false} assume !(1 == ~E_3~0); {41041#false} is VALID [2022-02-21 04:24:27,123 INFO L290 TraceCheckUtils]: 98: Hoare triple {41041#false} assume !(1 == ~E_4~0); {41041#false} is VALID [2022-02-21 04:24:27,123 INFO L290 TraceCheckUtils]: 99: Hoare triple {41041#false} assume !(1 == ~E_5~0); {41041#false} is VALID [2022-02-21 04:24:27,123 INFO L290 TraceCheckUtils]: 100: Hoare triple {41041#false} assume !(1 == ~E_6~0); {41041#false} is VALID [2022-02-21 04:24:27,124 INFO L290 TraceCheckUtils]: 101: Hoare triple {41041#false} assume !(1 == ~E_7~0); {41041#false} is VALID [2022-02-21 04:24:27,124 INFO L290 TraceCheckUtils]: 102: Hoare triple {41041#false} assume !(1 == ~E_8~0); {41041#false} is VALID [2022-02-21 04:24:27,124 INFO L290 TraceCheckUtils]: 103: Hoare triple {41041#false} assume { :end_inline_reset_delta_events } true; {41041#false} is VALID [2022-02-21 04:24:27,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:27,124 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:27,124 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720208223] [2022-02-21 04:24:27,124 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1720208223] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:27,125 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:27,125 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:27,125 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753593052] [2022-02-21 04:24:27,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:27,125 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:27,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:27,126 INFO L85 PathProgramCache]: Analyzing trace with hash -675988540, now seen corresponding path program 1 times [2022-02-21 04:24:27,126 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:27,126 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548181892] [2022-02-21 04:24:27,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:27,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:27,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:27,152 INFO L290 TraceCheckUtils]: 0: Hoare triple {41044#true} assume !false; {41044#true} is VALID [2022-02-21 04:24:27,152 INFO L290 TraceCheckUtils]: 1: Hoare triple {41044#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {41044#true} is VALID [2022-02-21 04:24:27,152 INFO L290 TraceCheckUtils]: 2: Hoare triple {41044#true} assume !false; {41044#true} is VALID [2022-02-21 04:24:27,152 INFO L290 TraceCheckUtils]: 3: Hoare triple {41044#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {41044#true} is VALID [2022-02-21 04:24:27,152 INFO L290 TraceCheckUtils]: 4: Hoare triple {41044#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {41044#true} is VALID [2022-02-21 04:24:27,152 INFO L290 TraceCheckUtils]: 5: Hoare triple {41044#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {41044#true} is VALID [2022-02-21 04:24:27,152 INFO L290 TraceCheckUtils]: 6: Hoare triple {41044#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {41044#true} is VALID [2022-02-21 04:24:27,152 INFO L290 TraceCheckUtils]: 7: Hoare triple {41044#true} assume !(0 != eval_~tmp~0#1); {41044#true} is VALID [2022-02-21 04:24:27,153 INFO L290 TraceCheckUtils]: 8: Hoare triple {41044#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {41044#true} is VALID [2022-02-21 04:24:27,153 INFO L290 TraceCheckUtils]: 9: Hoare triple {41044#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {41044#true} is VALID [2022-02-21 04:24:27,153 INFO L290 TraceCheckUtils]: 10: Hoare triple {41044#true} assume !(0 == ~M_E~0); {41044#true} is VALID [2022-02-21 04:24:27,153 INFO L290 TraceCheckUtils]: 11: Hoare triple {41044#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {41044#true} is VALID [2022-02-21 04:24:27,153 INFO L290 TraceCheckUtils]: 12: Hoare triple {41044#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {41044#true} is VALID [2022-02-21 04:24:27,153 INFO L290 TraceCheckUtils]: 13: Hoare triple {41044#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {41044#true} is VALID [2022-02-21 04:24:27,153 INFO L290 TraceCheckUtils]: 14: Hoare triple {41044#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,154 INFO L290 TraceCheckUtils]: 15: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T5_E~0); {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,154 INFO L290 TraceCheckUtils]: 16: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,154 INFO L290 TraceCheckUtils]: 17: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,154 INFO L290 TraceCheckUtils]: 18: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,155 INFO L290 TraceCheckUtils]: 19: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,155 INFO L290 TraceCheckUtils]: 20: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,155 INFO L290 TraceCheckUtils]: 21: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,156 INFO L290 TraceCheckUtils]: 22: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,156 INFO L290 TraceCheckUtils]: 23: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_5~0); {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,156 INFO L290 TraceCheckUtils]: 24: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,156 INFO L290 TraceCheckUtils]: 25: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,157 INFO L290 TraceCheckUtils]: 26: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,157 INFO L290 TraceCheckUtils]: 27: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,157 INFO L290 TraceCheckUtils]: 28: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~m_pc~0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,157 INFO L290 TraceCheckUtils]: 29: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,158 INFO L290 TraceCheckUtils]: 30: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,158 INFO L290 TraceCheckUtils]: 31: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,159 INFO L290 TraceCheckUtils]: 32: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,159 INFO L290 TraceCheckUtils]: 33: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,159 INFO L290 TraceCheckUtils]: 34: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t1_pc~0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,159 INFO L290 TraceCheckUtils]: 35: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,160 INFO L290 TraceCheckUtils]: 36: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,160 INFO L290 TraceCheckUtils]: 37: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,160 INFO L290 TraceCheckUtils]: 38: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,161 INFO L290 TraceCheckUtils]: 39: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,161 INFO L290 TraceCheckUtils]: 40: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t2_pc~0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,161 INFO L290 TraceCheckUtils]: 41: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,161 INFO L290 TraceCheckUtils]: 42: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,162 INFO L290 TraceCheckUtils]: 43: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,162 INFO L290 TraceCheckUtils]: 44: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,162 INFO L290 TraceCheckUtils]: 45: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,162 INFO L290 TraceCheckUtils]: 46: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t3_pc~0); {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,163 INFO L290 TraceCheckUtils]: 47: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,163 INFO L290 TraceCheckUtils]: 48: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,163 INFO L290 TraceCheckUtils]: 49: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,163 INFO L290 TraceCheckUtils]: 50: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,164 INFO L290 TraceCheckUtils]: 51: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,164 INFO L290 TraceCheckUtils]: 52: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t4_pc~0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,164 INFO L290 TraceCheckUtils]: 53: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,164 INFO L290 TraceCheckUtils]: 54: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,165 INFO L290 TraceCheckUtils]: 55: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,183 INFO L290 TraceCheckUtils]: 56: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,184 INFO L290 TraceCheckUtils]: 57: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,184 INFO L290 TraceCheckUtils]: 58: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t5_pc~0); {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,184 INFO L290 TraceCheckUtils]: 59: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,185 INFO L290 TraceCheckUtils]: 60: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,185 INFO L290 TraceCheckUtils]: 61: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,185 INFO L290 TraceCheckUtils]: 62: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,185 INFO L290 TraceCheckUtils]: 63: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,186 INFO L290 TraceCheckUtils]: 64: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t6_pc~0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,186 INFO L290 TraceCheckUtils]: 65: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,186 INFO L290 TraceCheckUtils]: 66: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,187 INFO L290 TraceCheckUtils]: 67: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,187 INFO L290 TraceCheckUtils]: 68: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,187 INFO L290 TraceCheckUtils]: 69: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,187 INFO L290 TraceCheckUtils]: 70: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t7_pc~0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,188 INFO L290 TraceCheckUtils]: 71: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,188 INFO L290 TraceCheckUtils]: 72: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,188 INFO L290 TraceCheckUtils]: 73: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,189 INFO L290 TraceCheckUtils]: 74: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,189 INFO L290 TraceCheckUtils]: 75: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,189 INFO L290 TraceCheckUtils]: 76: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t8_pc~0); {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,189 INFO L290 TraceCheckUtils]: 77: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,190 INFO L290 TraceCheckUtils]: 78: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,190 INFO L290 TraceCheckUtils]: 79: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,190 INFO L290 TraceCheckUtils]: 80: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,191 INFO L290 TraceCheckUtils]: 81: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,191 INFO L290 TraceCheckUtils]: 82: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,191 INFO L290 TraceCheckUtils]: 83: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,191 INFO L290 TraceCheckUtils]: 84: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,192 INFO L290 TraceCheckUtils]: 85: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {41046#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:27,192 INFO L290 TraceCheckUtils]: 86: Hoare triple {41046#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {41045#false} is VALID [2022-02-21 04:24:27,192 INFO L290 TraceCheckUtils]: 87: Hoare triple {41045#false} assume !(1 == ~T5_E~0); {41045#false} is VALID [2022-02-21 04:24:27,192 INFO L290 TraceCheckUtils]: 88: Hoare triple {41045#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {41045#false} is VALID [2022-02-21 04:24:27,192 INFO L290 TraceCheckUtils]: 89: Hoare triple {41045#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {41045#false} is VALID [2022-02-21 04:24:27,192 INFO L290 TraceCheckUtils]: 90: Hoare triple {41045#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {41045#false} is VALID [2022-02-21 04:24:27,193 INFO L290 TraceCheckUtils]: 91: Hoare triple {41045#false} assume 1 == ~E_1~0;~E_1~0 := 2; {41045#false} is VALID [2022-02-21 04:24:27,193 INFO L290 TraceCheckUtils]: 92: Hoare triple {41045#false} assume 1 == ~E_2~0;~E_2~0 := 2; {41045#false} is VALID [2022-02-21 04:24:27,193 INFO L290 TraceCheckUtils]: 93: Hoare triple {41045#false} assume 1 == ~E_3~0;~E_3~0 := 2; {41045#false} is VALID [2022-02-21 04:24:27,193 INFO L290 TraceCheckUtils]: 94: Hoare triple {41045#false} assume !(1 == ~E_4~0); {41045#false} is VALID [2022-02-21 04:24:27,193 INFO L290 TraceCheckUtils]: 95: Hoare triple {41045#false} assume 1 == ~E_5~0;~E_5~0 := 2; {41045#false} is VALID [2022-02-21 04:24:27,193 INFO L290 TraceCheckUtils]: 96: Hoare triple {41045#false} assume 1 == ~E_6~0;~E_6~0 := 2; {41045#false} is VALID [2022-02-21 04:24:27,193 INFO L290 TraceCheckUtils]: 97: Hoare triple {41045#false} assume 1 == ~E_7~0;~E_7~0 := 2; {41045#false} is VALID [2022-02-21 04:24:27,193 INFO L290 TraceCheckUtils]: 98: Hoare triple {41045#false} assume 1 == ~E_8~0;~E_8~0 := 2; {41045#false} is VALID [2022-02-21 04:24:27,193 INFO L290 TraceCheckUtils]: 99: Hoare triple {41045#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {41045#false} is VALID [2022-02-21 04:24:27,194 INFO L290 TraceCheckUtils]: 100: Hoare triple {41045#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {41045#false} is VALID [2022-02-21 04:24:27,194 INFO L290 TraceCheckUtils]: 101: Hoare triple {41045#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {41045#false} is VALID [2022-02-21 04:24:27,194 INFO L290 TraceCheckUtils]: 102: Hoare triple {41045#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {41045#false} is VALID [2022-02-21 04:24:27,194 INFO L290 TraceCheckUtils]: 103: Hoare triple {41045#false} assume !(0 == start_simulation_~tmp~3#1); {41045#false} is VALID [2022-02-21 04:24:27,194 INFO L290 TraceCheckUtils]: 104: Hoare triple {41045#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {41045#false} is VALID [2022-02-21 04:24:27,194 INFO L290 TraceCheckUtils]: 105: Hoare triple {41045#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {41045#false} is VALID [2022-02-21 04:24:27,194 INFO L290 TraceCheckUtils]: 106: Hoare triple {41045#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {41045#false} is VALID [2022-02-21 04:24:27,194 INFO L290 TraceCheckUtils]: 107: Hoare triple {41045#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {41045#false} is VALID [2022-02-21 04:24:27,194 INFO L290 TraceCheckUtils]: 108: Hoare triple {41045#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {41045#false} is VALID [2022-02-21 04:24:27,195 INFO L290 TraceCheckUtils]: 109: Hoare triple {41045#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {41045#false} is VALID [2022-02-21 04:24:27,195 INFO L290 TraceCheckUtils]: 110: Hoare triple {41045#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {41045#false} is VALID [2022-02-21 04:24:27,195 INFO L290 TraceCheckUtils]: 111: Hoare triple {41045#false} assume !(0 != start_simulation_~tmp___0~1#1); {41045#false} is VALID [2022-02-21 04:24:27,195 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:27,195 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:27,195 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1548181892] [2022-02-21 04:24:27,195 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1548181892] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:27,196 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:27,196 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:27,196 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1931745147] [2022-02-21 04:24:27,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:27,196 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:27,196 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:27,197 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:27,197 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:27,197 INFO L87 Difference]: Start difference. First operand 1685 states and 2492 transitions. cyclomatic complexity: 809 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:29,485 INFO L93 Difference]: Finished difference Result 4590 states and 6693 transitions. [2022-02-21 04:24:29,485 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:29,486 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,554 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:29,555 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4590 states and 6693 transitions. [2022-02-21 04:24:29,968 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4320 [2022-02-21 04:24:30,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4590 states to 4590 states and 6693 transitions. [2022-02-21 04:24:30,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4590 [2022-02-21 04:24:30,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4590 [2022-02-21 04:24:30,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4590 states and 6693 transitions. [2022-02-21 04:24:30,412 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:30,412 INFO L681 BuchiCegarLoop]: Abstraction has 4590 states and 6693 transitions. [2022-02-21 04:24:30,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4590 states and 6693 transitions. [2022-02-21 04:24:30,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4590 to 4342. [2022-02-21 04:24:30,454 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:30,459 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4590 states and 6693 transitions. Second operand has 4342 states, 4342 states have (on average 1.4631506218332566) internal successors, (6353), 4341 states have internal predecessors, (6353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,463 INFO L74 IsIncluded]: Start isIncluded. First operand 4590 states and 6693 transitions. Second operand has 4342 states, 4342 states have (on average 1.4631506218332566) internal successors, (6353), 4341 states have internal predecessors, (6353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,467 INFO L87 Difference]: Start difference. First operand 4590 states and 6693 transitions. Second operand has 4342 states, 4342 states have (on average 1.4631506218332566) internal successors, (6353), 4341 states have internal predecessors, (6353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,889 INFO L93 Difference]: Finished difference Result 4590 states and 6693 transitions. [2022-02-21 04:24:30,889 INFO L276 IsEmpty]: Start isEmpty. Operand 4590 states and 6693 transitions. [2022-02-21 04:24:30,893 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:30,893 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:30,898 INFO L74 IsIncluded]: Start isIncluded. First operand has 4342 states, 4342 states have (on average 1.4631506218332566) internal successors, (6353), 4341 states have internal predecessors, (6353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4590 states and 6693 transitions. [2022-02-21 04:24:30,903 INFO L87 Difference]: Start difference. First operand has 4342 states, 4342 states have (on average 1.4631506218332566) internal successors, (6353), 4341 states have internal predecessors, (6353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4590 states and 6693 transitions. [2022-02-21 04:24:31,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:31,344 INFO L93 Difference]: Finished difference Result 4590 states and 6693 transitions. [2022-02-21 04:24:31,344 INFO L276 IsEmpty]: Start isEmpty. Operand 4590 states and 6693 transitions. [2022-02-21 04:24:31,348 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:31,348 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:31,348 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:31,348 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:31,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4342 states, 4342 states have (on average 1.4631506218332566) internal successors, (6353), 4341 states have internal predecessors, (6353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4342 states to 4342 states and 6353 transitions. [2022-02-21 04:24:31,771 INFO L704 BuchiCegarLoop]: Abstraction has 4342 states and 6353 transitions. [2022-02-21 04:24:31,771 INFO L587 BuchiCegarLoop]: Abstraction has 4342 states and 6353 transitions. [2022-02-21 04:24:31,771 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:24:31,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4342 states and 6353 transitions. [2022-02-21 04:24:31,779 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4206 [2022-02-21 04:24:31,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:31,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:31,780 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:31,780 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:31,781 INFO L791 eck$LassoCheckResult]: Stem: 46365#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 46366#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 46769#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45733#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45734#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 46006#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46007#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46627#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46612#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46081#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46082#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46339#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46340#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46170#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46171#L838 assume !(0 == ~M_E~0); 46349#L838-2 assume !(0 == ~T1_E~0); 45694#L843-1 assume !(0 == ~T2_E~0); 45695#L848-1 assume !(0 == ~T3_E~0); 45814#L853-1 assume !(0 == ~T4_E~0); 46156#L858-1 assume !(0 == ~T5_E~0); 45639#L863-1 assume !(0 == ~T6_E~0); 45640#L868-1 assume !(0 == ~T7_E~0); 46702#L873-1 assume !(0 == ~T8_E~0); 46694#L878-1 assume !(0 == ~E_1~0); 46662#L883-1 assume !(0 == ~E_2~0); 46663#L888-1 assume !(0 == ~E_3~0); 46306#L893-1 assume !(0 == ~E_4~0); 46307#L898-1 assume !(0 == ~E_5~0); 46732#L903-1 assume !(0 == ~E_6~0); 46661#L908-1 assume !(0 == ~E_7~0); 46463#L913-1 assume !(0 == ~E_8~0); 45708#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45709#L402 assume !(1 == ~m_pc~0); 46132#L402-2 is_master_triggered_~__retres1~0#1 := 0; 45835#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45836#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46087#L1035 assume !(0 != activate_threads_~tmp~1#1); 46088#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46147#L421 assume !(1 == ~t1_pc~0); 46655#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46703#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46135#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46136#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 46203#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46720#L440 assume 1 == ~t2_pc~0; 45678#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45679#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45846#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46749#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 46485#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46036#L459 assume !(1 == ~t3_pc~0); 46037#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46652#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46396#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45829#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45830#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45839#L478 assume 1 == ~t4_pc~0; 45840#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46311#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46626#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46012#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 45753#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45754#L497 assume !(1 == ~t5_pc~0); 45800#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 45801#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46101#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46102#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 46640#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46641#L516 assume 1 == ~t6_pc~0; 46784#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46337#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46338#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45885#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 45886#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46328#L535 assume !(1 == ~t7_pc~0); 46329#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 46416#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46417#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46452#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 46441#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46442#L554 assume 1 == ~t8_pc~0; 46375#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45668#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46510#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45972#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 45973#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45652#L931 assume !(1 == ~M_E~0); 45653#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46683#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46745#L941-1 assume !(1 == ~T3_E~0); 49331#L946-1 assume !(1 == ~T4_E~0); 49330#L951-1 assume !(1 == ~T5_E~0); 49329#L956-1 assume !(1 == ~T6_E~0); 49328#L961-1 assume !(1 == ~T7_E~0); 49327#L966-1 assume !(1 == ~T8_E~0); 49326#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 49325#L976-1 assume !(1 == ~E_2~0); 49324#L981-1 assume !(1 == ~E_3~0); 49323#L986-1 assume !(1 == ~E_4~0); 49322#L991-1 assume !(1 == ~E_5~0); 45931#L996-1 assume !(1 == ~E_6~0); 49321#L1001-1 assume !(1 == ~E_7~0); 49320#L1006-1 assume !(1 == ~E_8~0); 49319#L1011-1 assume { :end_inline_reset_delta_events } true; 49317#L1272-2 [2022-02-21 04:24:31,793 INFO L793 eck$LassoCheckResult]: Loop: 49317#L1272-2 assume !false; 49312#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49308#L813 assume !false; 46570#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 46571#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 49299#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 49298#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46581#L696 assume !(0 != eval_~tmp~0#1); 46367#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46368#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46530#L838-3 assume !(0 == ~M_E~0); 46421#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46422#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46253#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46254#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46310#L858-3 assume !(0 == ~T5_E~0); 46392#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46379#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46380#L873-3 assume !(0 == ~T8_E~0); 48050#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48046#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48047#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48004#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48005#L898-3 assume !(0 == ~E_5~0); 48000#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 48001#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 47996#L913-3 assume !(0 == ~E_8~0); 47997#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47990#L402-27 assume !(1 == ~m_pc~0); 47991#L402-29 is_master_triggered_~__retres1~0#1 := 0; 47983#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47984#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 47977#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47978#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47971#L421-27 assume !(1 == ~t1_pc~0); 47972#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 47967#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47968#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46709#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46710#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46788#L440-27 assume 1 == ~t2_pc~0; 49414#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46808#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46809#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49410#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46347#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45934#L459-27 assume 1 == ~t3_pc~0; 45936#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46760#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46761#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46326#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46327#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46785#L478-27 assume 1 == ~t4_pc~0; 46755#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45924#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49399#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46517#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46518#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46573#L497-27 assume !(1 == ~t5_pc~0); 46574#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 49395#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46248#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46249#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46628#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46180#L516-27 assume 1 == ~t6_pc~0; 46181#L517-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46243#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46183#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46184#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46707#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46105#L535-27 assume 1 == ~t7_pc~0; 46106#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49384#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46534#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46535#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46756#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46717#L554-27 assume !(1 == ~t8_pc~0); 46718#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 45844#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45845#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46204#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 45949#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45950#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45825#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45826#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46052#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46490#L946-3 assume !(1 == ~T4_E~0); 45967#L951-3 assume !(1 == ~T5_E~0); 45968#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46279#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46065#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46066#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46336#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45716#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45717#L986-3 assume !(1 == ~E_4~0); 45706#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45707#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46577#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46042#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46043#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 45748#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 45750#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 46073#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 46074#L1291 assume !(0 == start_simulation_~tmp~3#1); 46276#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 46166#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 45643#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 45644#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 49334#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49333#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49332#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 49318#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 49317#L1272-2 [2022-02-21 04:24:31,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:31,793 INFO L85 PathProgramCache]: Analyzing trace with hash 493551747, now seen corresponding path program 1 times [2022-02-21 04:24:31,794 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:31,794 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050303216] [2022-02-21 04:24:31,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:31,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:31,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:31,818 INFO L290 TraceCheckUtils]: 0: Hoare triple {59164#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,819 INFO L290 TraceCheckUtils]: 1: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,819 INFO L290 TraceCheckUtils]: 2: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,819 INFO L290 TraceCheckUtils]: 3: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,819 INFO L290 TraceCheckUtils]: 4: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,820 INFO L290 TraceCheckUtils]: 5: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,820 INFO L290 TraceCheckUtils]: 6: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,820 INFO L290 TraceCheckUtils]: 7: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,820 INFO L290 TraceCheckUtils]: 8: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,821 INFO L290 TraceCheckUtils]: 9: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,821 INFO L290 TraceCheckUtils]: 10: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,821 INFO L290 TraceCheckUtils]: 11: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,821 INFO L290 TraceCheckUtils]: 12: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,822 INFO L290 TraceCheckUtils]: 13: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,822 INFO L290 TraceCheckUtils]: 14: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~M_E~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,822 INFO L290 TraceCheckUtils]: 15: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T1_E~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,823 INFO L290 TraceCheckUtils]: 16: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T2_E~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,823 INFO L290 TraceCheckUtils]: 17: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T3_E~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,823 INFO L290 TraceCheckUtils]: 18: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T4_E~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,823 INFO L290 TraceCheckUtils]: 19: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T5_E~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,824 INFO L290 TraceCheckUtils]: 20: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T6_E~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,824 INFO L290 TraceCheckUtils]: 21: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T7_E~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,824 INFO L290 TraceCheckUtils]: 22: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T8_E~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,825 INFO L290 TraceCheckUtils]: 23: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_1~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,825 INFO L290 TraceCheckUtils]: 24: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_2~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,825 INFO L290 TraceCheckUtils]: 25: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_3~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,825 INFO L290 TraceCheckUtils]: 26: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_4~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,826 INFO L290 TraceCheckUtils]: 27: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_5~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,826 INFO L290 TraceCheckUtils]: 28: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_6~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,826 INFO L290 TraceCheckUtils]: 29: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_7~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,826 INFO L290 TraceCheckUtils]: 30: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_8~0); {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,827 INFO L290 TraceCheckUtils]: 31: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {59166#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:24:31,827 INFO L290 TraceCheckUtils]: 32: Hoare triple {59166#(= ~m_pc~0 ~t2_pc~0)} assume !(1 == ~m_pc~0); {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,827 INFO L290 TraceCheckUtils]: 33: Hoare triple {59167#(not (= ~t2_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,828 INFO L290 TraceCheckUtils]: 34: Hoare triple {59167#(not (= ~t2_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,828 INFO L290 TraceCheckUtils]: 35: Hoare triple {59167#(not (= ~t2_pc~0 1))} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,828 INFO L290 TraceCheckUtils]: 36: Hoare triple {59167#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,828 INFO L290 TraceCheckUtils]: 37: Hoare triple {59167#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,829 INFO L290 TraceCheckUtils]: 38: Hoare triple {59167#(not (= ~t2_pc~0 1))} assume !(1 == ~t1_pc~0); {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,829 INFO L290 TraceCheckUtils]: 39: Hoare triple {59167#(not (= ~t2_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,829 INFO L290 TraceCheckUtils]: 40: Hoare triple {59167#(not (= ~t2_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,829 INFO L290 TraceCheckUtils]: 41: Hoare triple {59167#(not (= ~t2_pc~0 1))} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 42: Hoare triple {59167#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 43: Hoare triple {59167#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {59167#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 44: Hoare triple {59167#(not (= ~t2_pc~0 1))} assume 1 == ~t2_pc~0; {59165#false} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 45: Hoare triple {59165#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {59165#false} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 46: Hoare triple {59165#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {59165#false} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 47: Hoare triple {59165#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {59165#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 48: Hoare triple {59165#false} assume !(0 != activate_threads_~tmp___1~0#1); {59165#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 49: Hoare triple {59165#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {59165#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 50: Hoare triple {59165#false} assume !(1 == ~t3_pc~0); {59165#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 51: Hoare triple {59165#false} is_transmit3_triggered_~__retres1~3#1 := 0; {59165#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 52: Hoare triple {59165#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {59165#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 53: Hoare triple {59165#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {59165#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 54: Hoare triple {59165#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {59165#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 55: Hoare triple {59165#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {59165#false} is VALID [2022-02-21 04:24:31,832 INFO L290 TraceCheckUtils]: 56: Hoare triple {59165#false} assume 1 == ~t4_pc~0; {59165#false} is VALID [2022-02-21 04:24:31,832 INFO L290 TraceCheckUtils]: 57: Hoare triple {59165#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {59165#false} is VALID [2022-02-21 04:24:31,832 INFO L290 TraceCheckUtils]: 58: Hoare triple {59165#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {59165#false} is VALID [2022-02-21 04:24:31,832 INFO L290 TraceCheckUtils]: 59: Hoare triple {59165#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {59165#false} is VALID [2022-02-21 04:24:31,832 INFO L290 TraceCheckUtils]: 60: Hoare triple {59165#false} assume !(0 != activate_threads_~tmp___3~0#1); {59165#false} is VALID [2022-02-21 04:24:31,832 INFO L290 TraceCheckUtils]: 61: Hoare triple {59165#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {59165#false} is VALID [2022-02-21 04:24:31,832 INFO L290 TraceCheckUtils]: 62: Hoare triple {59165#false} assume !(1 == ~t5_pc~0); {59165#false} is VALID [2022-02-21 04:24:31,832 INFO L290 TraceCheckUtils]: 63: Hoare triple {59165#false} is_transmit5_triggered_~__retres1~5#1 := 0; {59165#false} is VALID [2022-02-21 04:24:31,832 INFO L290 TraceCheckUtils]: 64: Hoare triple {59165#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {59165#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 65: Hoare triple {59165#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {59165#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 66: Hoare triple {59165#false} assume !(0 != activate_threads_~tmp___4~0#1); {59165#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 67: Hoare triple {59165#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {59165#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 68: Hoare triple {59165#false} assume 1 == ~t6_pc~0; {59165#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 69: Hoare triple {59165#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {59165#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 70: Hoare triple {59165#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {59165#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 71: Hoare triple {59165#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {59165#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 72: Hoare triple {59165#false} assume !(0 != activate_threads_~tmp___5~0#1); {59165#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 73: Hoare triple {59165#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {59165#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 74: Hoare triple {59165#false} assume !(1 == ~t7_pc~0); {59165#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 75: Hoare triple {59165#false} is_transmit7_triggered_~__retres1~7#1 := 0; {59165#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 76: Hoare triple {59165#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {59165#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 77: Hoare triple {59165#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {59165#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 78: Hoare triple {59165#false} assume !(0 != activate_threads_~tmp___6~0#1); {59165#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 79: Hoare triple {59165#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {59165#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 80: Hoare triple {59165#false} assume 1 == ~t8_pc~0; {59165#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 81: Hoare triple {59165#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {59165#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 82: Hoare triple {59165#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {59165#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 83: Hoare triple {59165#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {59165#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 84: Hoare triple {59165#false} assume !(0 != activate_threads_~tmp___7~0#1); {59165#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 85: Hoare triple {59165#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {59165#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 86: Hoare triple {59165#false} assume !(1 == ~M_E~0); {59165#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 87: Hoare triple {59165#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {59165#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 88: Hoare triple {59165#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {59165#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 89: Hoare triple {59165#false} assume !(1 == ~T3_E~0); {59165#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 90: Hoare triple {59165#false} assume !(1 == ~T4_E~0); {59165#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 91: Hoare triple {59165#false} assume !(1 == ~T5_E~0); {59165#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 92: Hoare triple {59165#false} assume !(1 == ~T6_E~0); {59165#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 93: Hoare triple {59165#false} assume !(1 == ~T7_E~0); {59165#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 94: Hoare triple {59165#false} assume !(1 == ~T8_E~0); {59165#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 95: Hoare triple {59165#false} assume 1 == ~E_1~0;~E_1~0 := 2; {59165#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 96: Hoare triple {59165#false} assume !(1 == ~E_2~0); {59165#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 97: Hoare triple {59165#false} assume !(1 == ~E_3~0); {59165#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 98: Hoare triple {59165#false} assume !(1 == ~E_4~0); {59165#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 99: Hoare triple {59165#false} assume !(1 == ~E_5~0); {59165#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 100: Hoare triple {59165#false} assume !(1 == ~E_6~0); {59165#false} is VALID [2022-02-21 04:24:31,837 INFO L290 TraceCheckUtils]: 101: Hoare triple {59165#false} assume !(1 == ~E_7~0); {59165#false} is VALID [2022-02-21 04:24:31,837 INFO L290 TraceCheckUtils]: 102: Hoare triple {59165#false} assume !(1 == ~E_8~0); {59165#false} is VALID [2022-02-21 04:24:31,837 INFO L290 TraceCheckUtils]: 103: Hoare triple {59165#false} assume { :end_inline_reset_delta_events } true; {59165#false} is VALID [2022-02-21 04:24:31,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:31,837 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:31,837 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050303216] [2022-02-21 04:24:31,837 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050303216] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:31,839 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:31,839 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:31,840 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1651610577] [2022-02-21 04:24:31,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:31,841 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:31,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:31,841 INFO L85 PathProgramCache]: Analyzing trace with hash -1230072733, now seen corresponding path program 1 times [2022-02-21 04:24:31,841 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:31,841 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360246760] [2022-02-21 04:24:31,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:31,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:31,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:31,864 INFO L290 TraceCheckUtils]: 0: Hoare triple {59168#true} assume !false; {59168#true} is VALID [2022-02-21 04:24:31,864 INFO L290 TraceCheckUtils]: 1: Hoare triple {59168#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {59168#true} is VALID [2022-02-21 04:24:31,864 INFO L290 TraceCheckUtils]: 2: Hoare triple {59168#true} assume !false; {59168#true} is VALID [2022-02-21 04:24:31,864 INFO L290 TraceCheckUtils]: 3: Hoare triple {59168#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {59168#true} is VALID [2022-02-21 04:24:31,864 INFO L290 TraceCheckUtils]: 4: Hoare triple {59168#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {59168#true} is VALID [2022-02-21 04:24:31,864 INFO L290 TraceCheckUtils]: 5: Hoare triple {59168#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {59168#true} is VALID [2022-02-21 04:24:31,865 INFO L290 TraceCheckUtils]: 6: Hoare triple {59168#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {59168#true} is VALID [2022-02-21 04:24:31,865 INFO L290 TraceCheckUtils]: 7: Hoare triple {59168#true} assume !(0 != eval_~tmp~0#1); {59168#true} is VALID [2022-02-21 04:24:31,865 INFO L290 TraceCheckUtils]: 8: Hoare triple {59168#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {59168#true} is VALID [2022-02-21 04:24:31,865 INFO L290 TraceCheckUtils]: 9: Hoare triple {59168#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {59168#true} is VALID [2022-02-21 04:24:31,865 INFO L290 TraceCheckUtils]: 10: Hoare triple {59168#true} assume !(0 == ~M_E~0); {59168#true} is VALID [2022-02-21 04:24:31,865 INFO L290 TraceCheckUtils]: 11: Hoare triple {59168#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {59168#true} is VALID [2022-02-21 04:24:31,866 INFO L290 TraceCheckUtils]: 12: Hoare triple {59168#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {59168#true} is VALID [2022-02-21 04:24:31,866 INFO L290 TraceCheckUtils]: 13: Hoare triple {59168#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {59168#true} is VALID [2022-02-21 04:24:31,866 INFO L290 TraceCheckUtils]: 14: Hoare triple {59168#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,867 INFO L290 TraceCheckUtils]: 15: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T5_E~0); {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,867 INFO L290 TraceCheckUtils]: 16: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,867 INFO L290 TraceCheckUtils]: 17: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,867 INFO L290 TraceCheckUtils]: 18: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,868 INFO L290 TraceCheckUtils]: 19: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,868 INFO L290 TraceCheckUtils]: 20: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,868 INFO L290 TraceCheckUtils]: 21: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,868 INFO L290 TraceCheckUtils]: 22: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,869 INFO L290 TraceCheckUtils]: 23: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_5~0); {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,869 INFO L290 TraceCheckUtils]: 24: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,869 INFO L290 TraceCheckUtils]: 25: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,869 INFO L290 TraceCheckUtils]: 26: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,870 INFO L290 TraceCheckUtils]: 27: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,870 INFO L290 TraceCheckUtils]: 28: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~m_pc~0); {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,870 INFO L290 TraceCheckUtils]: 29: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,870 INFO L290 TraceCheckUtils]: 30: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,871 INFO L290 TraceCheckUtils]: 31: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,871 INFO L290 TraceCheckUtils]: 32: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,871 INFO L290 TraceCheckUtils]: 33: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,871 INFO L290 TraceCheckUtils]: 34: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t1_pc~0); {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,872 INFO L290 TraceCheckUtils]: 35: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,872 INFO L290 TraceCheckUtils]: 36: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,872 INFO L290 TraceCheckUtils]: 37: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,872 INFO L290 TraceCheckUtils]: 38: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,872 INFO L290 TraceCheckUtils]: 39: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,873 INFO L290 TraceCheckUtils]: 40: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t2_pc~0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,873 INFO L290 TraceCheckUtils]: 41: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,873 INFO L290 TraceCheckUtils]: 42: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,873 INFO L290 TraceCheckUtils]: 43: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,874 INFO L290 TraceCheckUtils]: 44: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,874 INFO L290 TraceCheckUtils]: 45: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,874 INFO L290 TraceCheckUtils]: 46: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t3_pc~0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,874 INFO L290 TraceCheckUtils]: 47: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,875 INFO L290 TraceCheckUtils]: 48: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,875 INFO L290 TraceCheckUtils]: 49: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,875 INFO L290 TraceCheckUtils]: 50: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,875 INFO L290 TraceCheckUtils]: 51: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,876 INFO L290 TraceCheckUtils]: 52: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t4_pc~0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,876 INFO L290 TraceCheckUtils]: 53: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,876 INFO L290 TraceCheckUtils]: 54: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,876 INFO L290 TraceCheckUtils]: 55: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,877 INFO L290 TraceCheckUtils]: 56: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,877 INFO L290 TraceCheckUtils]: 57: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,877 INFO L290 TraceCheckUtils]: 58: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t5_pc~0); {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,877 INFO L290 TraceCheckUtils]: 59: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,878 INFO L290 TraceCheckUtils]: 60: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,878 INFO L290 TraceCheckUtils]: 61: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,878 INFO L290 TraceCheckUtils]: 62: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,878 INFO L290 TraceCheckUtils]: 63: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,879 INFO L290 TraceCheckUtils]: 64: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t6_pc~0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,879 INFO L290 TraceCheckUtils]: 65: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,879 INFO L290 TraceCheckUtils]: 66: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,879 INFO L290 TraceCheckUtils]: 67: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,880 INFO L290 TraceCheckUtils]: 68: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,880 INFO L290 TraceCheckUtils]: 69: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,880 INFO L290 TraceCheckUtils]: 70: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t7_pc~0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,880 INFO L290 TraceCheckUtils]: 71: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,881 INFO L290 TraceCheckUtils]: 72: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,881 INFO L290 TraceCheckUtils]: 73: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,881 INFO L290 TraceCheckUtils]: 74: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,881 INFO L290 TraceCheckUtils]: 75: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,882 INFO L290 TraceCheckUtils]: 76: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t8_pc~0); {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,882 INFO L290 TraceCheckUtils]: 77: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,882 INFO L290 TraceCheckUtils]: 78: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,882 INFO L290 TraceCheckUtils]: 79: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,883 INFO L290 TraceCheckUtils]: 80: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,883 INFO L290 TraceCheckUtils]: 81: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,883 INFO L290 TraceCheckUtils]: 82: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,883 INFO L290 TraceCheckUtils]: 83: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,884 INFO L290 TraceCheckUtils]: 84: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,884 INFO L290 TraceCheckUtils]: 85: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {59170#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:31,884 INFO L290 TraceCheckUtils]: 86: Hoare triple {59170#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {59169#false} is VALID [2022-02-21 04:24:31,884 INFO L290 TraceCheckUtils]: 87: Hoare triple {59169#false} assume !(1 == ~T5_E~0); {59169#false} is VALID [2022-02-21 04:24:31,884 INFO L290 TraceCheckUtils]: 88: Hoare triple {59169#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {59169#false} is VALID [2022-02-21 04:24:31,884 INFO L290 TraceCheckUtils]: 89: Hoare triple {59169#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {59169#false} is VALID [2022-02-21 04:24:31,885 INFO L290 TraceCheckUtils]: 90: Hoare triple {59169#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {59169#false} is VALID [2022-02-21 04:24:31,885 INFO L290 TraceCheckUtils]: 91: Hoare triple {59169#false} assume 1 == ~E_1~0;~E_1~0 := 2; {59169#false} is VALID [2022-02-21 04:24:31,885 INFO L290 TraceCheckUtils]: 92: Hoare triple {59169#false} assume 1 == ~E_2~0;~E_2~0 := 2; {59169#false} is VALID [2022-02-21 04:24:31,885 INFO L290 TraceCheckUtils]: 93: Hoare triple {59169#false} assume 1 == ~E_3~0;~E_3~0 := 2; {59169#false} is VALID [2022-02-21 04:24:31,885 INFO L290 TraceCheckUtils]: 94: Hoare triple {59169#false} assume !(1 == ~E_4~0); {59169#false} is VALID [2022-02-21 04:24:31,885 INFO L290 TraceCheckUtils]: 95: Hoare triple {59169#false} assume 1 == ~E_5~0;~E_5~0 := 2; {59169#false} is VALID [2022-02-21 04:24:31,885 INFO L290 TraceCheckUtils]: 96: Hoare triple {59169#false} assume 1 == ~E_6~0;~E_6~0 := 2; {59169#false} is VALID [2022-02-21 04:24:31,885 INFO L290 TraceCheckUtils]: 97: Hoare triple {59169#false} assume 1 == ~E_7~0;~E_7~0 := 2; {59169#false} is VALID [2022-02-21 04:24:31,885 INFO L290 TraceCheckUtils]: 98: Hoare triple {59169#false} assume 1 == ~E_8~0;~E_8~0 := 2; {59169#false} is VALID [2022-02-21 04:24:31,886 INFO L290 TraceCheckUtils]: 99: Hoare triple {59169#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {59169#false} is VALID [2022-02-21 04:24:31,886 INFO L290 TraceCheckUtils]: 100: Hoare triple {59169#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {59169#false} is VALID [2022-02-21 04:24:31,886 INFO L290 TraceCheckUtils]: 101: Hoare triple {59169#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {59169#false} is VALID [2022-02-21 04:24:31,886 INFO L290 TraceCheckUtils]: 102: Hoare triple {59169#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {59169#false} is VALID [2022-02-21 04:24:31,886 INFO L290 TraceCheckUtils]: 103: Hoare triple {59169#false} assume !(0 == start_simulation_~tmp~3#1); {59169#false} is VALID [2022-02-21 04:24:31,886 INFO L290 TraceCheckUtils]: 104: Hoare triple {59169#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {59169#false} is VALID [2022-02-21 04:24:31,886 INFO L290 TraceCheckUtils]: 105: Hoare triple {59169#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {59169#false} is VALID [2022-02-21 04:24:31,886 INFO L290 TraceCheckUtils]: 106: Hoare triple {59169#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {59169#false} is VALID [2022-02-21 04:24:31,886 INFO L290 TraceCheckUtils]: 107: Hoare triple {59169#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {59169#false} is VALID [2022-02-21 04:24:31,887 INFO L290 TraceCheckUtils]: 108: Hoare triple {59169#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {59169#false} is VALID [2022-02-21 04:24:31,887 INFO L290 TraceCheckUtils]: 109: Hoare triple {59169#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {59169#false} is VALID [2022-02-21 04:24:31,887 INFO L290 TraceCheckUtils]: 110: Hoare triple {59169#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {59169#false} is VALID [2022-02-21 04:24:31,887 INFO L290 TraceCheckUtils]: 111: Hoare triple {59169#false} assume !(0 != start_simulation_~tmp___0~1#1); {59169#false} is VALID [2022-02-21 04:24:31,887 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:31,887 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:31,888 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360246760] [2022-02-21 04:24:31,888 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1360246760] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:31,888 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:31,888 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:31,888 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1490621223] [2022-02-21 04:24:31,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:31,888 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:31,889 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:31,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:31,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:31,889 INFO L87 Difference]: Start difference. First operand 4342 states and 6353 transitions. cyclomatic complexity: 2015 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:36,761 INFO L93 Difference]: Finished difference Result 12155 states and 17606 transitions. [2022-02-21 04:24:36,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:36,761 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,816 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:36,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12155 states and 17606 transitions. [2022-02-21 04:24:39,895 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11706 [2022-02-21 04:24:42,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12155 states to 12155 states and 17606 transitions. [2022-02-21 04:24:42,807 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12155 [2022-02-21 04:24:42,810 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12155 [2022-02-21 04:24:42,810 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12155 states and 17606 transitions. [2022-02-21 04:24:42,815 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:42,816 INFO L681 BuchiCegarLoop]: Abstraction has 12155 states and 17606 transitions. [2022-02-21 04:24:42,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12155 states and 17606 transitions. [2022-02-21 04:24:42,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12155 to 11561. [2022-02-21 04:24:42,950 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:42,963 INFO L82 GeneralOperation]: Start isEquivalent. First operand 12155 states and 17606 transitions. Second operand has 11561 states, 11561 states have (on average 1.4531614912204827) internal successors, (16800), 11560 states have internal predecessors, (16800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,976 INFO L74 IsIncluded]: Start isIncluded. First operand 12155 states and 17606 transitions. Second operand has 11561 states, 11561 states have (on average 1.4531614912204827) internal successors, (16800), 11560 states have internal predecessors, (16800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,990 INFO L87 Difference]: Start difference. First operand 12155 states and 17606 transitions. Second operand has 11561 states, 11561 states have (on average 1.4531614912204827) internal successors, (16800), 11560 states have internal predecessors, (16800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:46,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:46,066 INFO L93 Difference]: Finished difference Result 12155 states and 17606 transitions. [2022-02-21 04:24:46,066 INFO L276 IsEmpty]: Start isEmpty. Operand 12155 states and 17606 transitions. [2022-02-21 04:24:46,076 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:46,076 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:46,089 INFO L74 IsIncluded]: Start isIncluded. First operand has 11561 states, 11561 states have (on average 1.4531614912204827) internal successors, (16800), 11560 states have internal predecessors, (16800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 12155 states and 17606 transitions. [2022-02-21 04:24:46,102 INFO L87 Difference]: Start difference. First operand has 11561 states, 11561 states have (on average 1.4531614912204827) internal successors, (16800), 11560 states have internal predecessors, (16800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 12155 states and 17606 transitions. [2022-02-21 04:24:48,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:48,992 INFO L93 Difference]: Finished difference Result 12155 states and 17606 transitions. [2022-02-21 04:24:48,992 INFO L276 IsEmpty]: Start isEmpty. Operand 12155 states and 17606 transitions. [2022-02-21 04:24:49,001 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:49,001 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:49,001 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:49,001 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:49,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11561 states, 11561 states have (on average 1.4531614912204827) internal successors, (16800), 11560 states have internal predecessors, (16800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11561 states to 11561 states and 16800 transitions. [2022-02-21 04:24:51,978 INFO L704 BuchiCegarLoop]: Abstraction has 11561 states and 16800 transitions. [2022-02-21 04:24:51,978 INFO L587 BuchiCegarLoop]: Abstraction has 11561 states and 16800 transitions. [2022-02-21 04:24:51,978 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:24:51,978 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11561 states and 16800 transitions. [2022-02-21 04:24:51,999 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11406 [2022-02-21 04:24:51,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:51,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:52,000 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:52,000 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:52,000 INFO L791 eck$LassoCheckResult]: Stem: 72034#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 72035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 72374#L1235 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 71419#L574 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 71420#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 71690#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 71691#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 72274#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 72258#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71764#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 71765#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 72010#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 72011#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 71850#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 71851#L838 assume !(0 == ~M_E~0); 72018#L838-2 assume !(0 == ~T1_E~0); 71380#L843-1 assume !(0 == ~T2_E~0); 71381#L848-1 assume !(0 == ~T3_E~0); 71500#L853-1 assume !(0 == ~T4_E~0); 71836#L858-1 assume !(0 == ~T5_E~0); 71328#L863-1 assume !(0 == ~T6_E~0); 71329#L868-1 assume !(0 == ~T7_E~0); 72328#L873-1 assume !(0 == ~T8_E~0); 72324#L878-1 assume !(0 == ~E_1~0); 72302#L883-1 assume !(0 == ~E_2~0); 72303#L888-1 assume !(0 == ~E_3~0); 71981#L893-1 assume !(0 == ~E_4~0); 71982#L898-1 assume !(0 == ~E_5~0); 72350#L903-1 assume !(0 == ~E_6~0); 72301#L908-1 assume !(0 == ~E_7~0); 72128#L913-1 assume !(0 == ~E_8~0); 71395#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71396#L402 assume !(1 == ~m_pc~0); 71813#L402-2 is_master_triggered_~__retres1~0#1 := 0; 71522#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71523#L414 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 71770#L1035 assume !(0 != activate_threads_~tmp~1#1); 71771#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71825#L421 assume !(1 == ~t1_pc~0); 72294#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 72331#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71816#L433 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 71817#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 71884#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72341#L440 assume !(1 == ~t2_pc~0); 72393#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 71532#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71533#L452 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 72362#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 72146#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71723#L459 assume !(1 == ~t3_pc~0); 71724#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 72288#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72061#L471 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 71515#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 71516#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71526#L478 assume 1 == ~t4_pc~0; 71527#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 71985#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 72273#L490 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 71696#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 71441#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71442#L497 assume !(1 == ~t5_pc~0); 71486#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 71487#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71784#L509 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 71785#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 72282#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72283#L516 assume 1 == ~t6_pc~0; 72385#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 72007#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 72008#L528 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71571#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 71572#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 71999#L535 assume !(1 == ~t7_pc~0); 72000#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 72081#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72082#L547 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72116#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 72104#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 72105#L554 assume 1 == ~t8_pc~0; 72043#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 71357#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 72168#L566 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71662#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 71663#L1099-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71341#L931 assume !(1 == ~M_E~0); 71342#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 72316#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 72359#L941-1 assume !(1 == ~T3_E~0); 72392#L946-1 assume !(1 == ~T4_E~0); 72290#L951-1 assume !(1 == ~T5_E~0); 72291#L956-1 assume !(1 == ~T6_E~0); 72386#L961-1 assume !(1 == ~T7_E~0); 72387#L966-1 assume !(1 == ~T8_E~0); 72109#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 72110#L976-1 assume !(1 == ~E_2~0); 72072#L981-1 assume !(1 == ~E_3~0); 72073#L986-1 assume !(1 == ~E_4~0); 71617#L991-1 assume !(1 == ~E_5~0); 71618#L996-1 assume !(1 == ~E_6~0); 72336#L1001-1 assume !(1 == ~E_7~0); 72337#L1006-1 assume !(1 == ~E_8~0); 72292#L1011-1 assume { :end_inline_reset_delta_events } true; 72293#L1272-2 [2022-02-21 04:24:52,000 INFO L793 eck$LassoCheckResult]: Loop: 72293#L1272-2 assume !false; 82110#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 71404#L813 assume !false; 71405#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 72389#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 71409#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 71976#L682 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 71987#L696 assume !(0 != eval_~tmp~0#1); 72233#L828 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82773#L574-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82765#L838-3 assume !(0 == ~M_E~0); 82764#L838-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 82762#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 82763#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 71979#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 71980#L858-3 assume !(0 == ~T5_E~0); 72056#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 72057#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 72069#L873-3 assume !(0 == ~T8_E~0); 72070#L878-3 assume 0 == ~E_1~0;~E_1~0 := 1; 71367#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 71368#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 71369#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 71370#L898-3 assume !(0 == ~E_5~0); 72225#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 72226#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 82836#L913-3 assume !(0 == ~E_8~0); 71411#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71412#L402-27 assume !(1 == ~m_pc~0); 71876#L402-29 is_master_triggered_~__retres1~0#1 := 0; 71877#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71863#L414-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 71864#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72243#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72244#L421-27 assume !(1 == ~t1_pc~0); 71630#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 71631#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71897#L433-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 71898#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 72338#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72002#L440-27 assume !(1 == ~t2_pc~0); 72003#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 72396#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72397#L452-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 71906#L1051-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 71907#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71620#L459-27 assume !(1 == ~t3_pc~0); 71621#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 72076#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81333#L471-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 81334#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81329#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81330#L478-27 assume 1 == ~t4_pc~0; 81323#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 81324#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81319#L490-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81320#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81315#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81316#L497-27 assume !(1 == ~t5_pc~0); 81309#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 81310#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81305#L509-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81306#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 81301#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81302#L516-27 assume !(1 == ~t6_pc~0); 81297#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 81296#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81289#L528-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81290#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 81283#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81284#L535-27 assume !(1 == ~t7_pc~0); 81275#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 81276#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81269#L547-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81270#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 81141#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81142#L554-27 assume 1 == ~t8_pc~0; 81133#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 81134#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 81127#L566-9 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81128#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 81120#L1099-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81121#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 81114#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 81115#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 81109#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 81110#L946-3 assume !(1 == ~T4_E~0); 81103#L951-3 assume !(1 == ~T5_E~0); 81104#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 81098#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 81099#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 81092#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 81093#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81086#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81087#L986-3 assume !(1 == ~E_4~0); 81080#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81081#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 81075#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 81076#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 81069#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 81070#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 82138#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 82137#L682-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 82135#L1291 assume !(0 == start_simulation_~tmp~3#1); 82133#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 82117#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 82116#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 82115#L682-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 82114#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 82113#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82112#L1254 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 82111#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 72293#L1272-2 [2022-02-21 04:24:52,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:52,001 INFO L85 PathProgramCache]: Analyzing trace with hash -1412932446, now seen corresponding path program 1 times [2022-02-21 04:24:52,001 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:52,001 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226354835] [2022-02-21 04:24:52,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:52,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:52,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:52,035 INFO L290 TraceCheckUtils]: 0: Hoare triple {107202#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; {107202#true} is VALID [2022-02-21 04:24:52,036 INFO L290 TraceCheckUtils]: 1: Hoare triple {107202#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; {107202#true} is VALID [2022-02-21 04:24:52,036 INFO L290 TraceCheckUtils]: 2: Hoare triple {107202#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {107202#true} is VALID [2022-02-21 04:24:52,036 INFO L290 TraceCheckUtils]: 3: Hoare triple {107202#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {107202#true} is VALID [2022-02-21 04:24:52,036 INFO L290 TraceCheckUtils]: 4: Hoare triple {107202#true} assume 1 == ~m_i~0;~m_st~0 := 0; {107202#true} is VALID [2022-02-21 04:24:52,036 INFO L290 TraceCheckUtils]: 5: Hoare triple {107202#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {107202#true} is VALID [2022-02-21 04:24:52,036 INFO L290 TraceCheckUtils]: 6: Hoare triple {107202#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {107202#true} is VALID [2022-02-21 04:24:52,036 INFO L290 TraceCheckUtils]: 7: Hoare triple {107202#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {107202#true} is VALID [2022-02-21 04:24:52,036 INFO L290 TraceCheckUtils]: 8: Hoare triple {107202#true} assume 1 == ~t4_i~0;~t4_st~0 := 0; {107202#true} is VALID [2022-02-21 04:24:52,036 INFO L290 TraceCheckUtils]: 9: Hoare triple {107202#true} assume 1 == ~t5_i~0;~t5_st~0 := 0; {107202#true} is VALID [2022-02-21 04:24:52,037 INFO L290 TraceCheckUtils]: 10: Hoare triple {107202#true} assume 1 == ~t6_i~0;~t6_st~0 := 0; {107202#true} is VALID [2022-02-21 04:24:52,037 INFO L290 TraceCheckUtils]: 11: Hoare triple {107202#true} assume 1 == ~t7_i~0;~t7_st~0 := 0; {107202#true} is VALID [2022-02-21 04:24:52,037 INFO L290 TraceCheckUtils]: 12: Hoare triple {107202#true} assume 1 == ~t8_i~0;~t8_st~0 := 0; {107202#true} is VALID [2022-02-21 04:24:52,037 INFO L290 TraceCheckUtils]: 13: Hoare triple {107202#true} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {107202#true} is VALID [2022-02-21 04:24:52,037 INFO L290 TraceCheckUtils]: 14: Hoare triple {107202#true} assume !(0 == ~M_E~0); {107202#true} is VALID [2022-02-21 04:24:52,037 INFO L290 TraceCheckUtils]: 15: Hoare triple {107202#true} assume !(0 == ~T1_E~0); {107202#true} is VALID [2022-02-21 04:24:52,037 INFO L290 TraceCheckUtils]: 16: Hoare triple {107202#true} assume !(0 == ~T2_E~0); {107202#true} is VALID [2022-02-21 04:24:52,037 INFO L290 TraceCheckUtils]: 17: Hoare triple {107202#true} assume !(0 == ~T3_E~0); {107202#true} is VALID [2022-02-21 04:24:52,037 INFO L290 TraceCheckUtils]: 18: Hoare triple {107202#true} assume !(0 == ~T4_E~0); {107202#true} is VALID [2022-02-21 04:24:52,038 INFO L290 TraceCheckUtils]: 19: Hoare triple {107202#true} assume !(0 == ~T5_E~0); {107202#true} is VALID [2022-02-21 04:24:52,038 INFO L290 TraceCheckUtils]: 20: Hoare triple {107202#true} assume !(0 == ~T6_E~0); {107202#true} is VALID [2022-02-21 04:24:52,038 INFO L290 TraceCheckUtils]: 21: Hoare triple {107202#true} assume !(0 == ~T7_E~0); {107202#true} is VALID [2022-02-21 04:24:52,038 INFO L290 TraceCheckUtils]: 22: Hoare triple {107202#true} assume !(0 == ~T8_E~0); {107202#true} is VALID [2022-02-21 04:24:52,038 INFO L290 TraceCheckUtils]: 23: Hoare triple {107202#true} assume !(0 == ~E_1~0); {107202#true} is VALID [2022-02-21 04:24:52,038 INFO L290 TraceCheckUtils]: 24: Hoare triple {107202#true} assume !(0 == ~E_2~0); {107202#true} is VALID [2022-02-21 04:24:52,038 INFO L290 TraceCheckUtils]: 25: Hoare triple {107202#true} assume !(0 == ~E_3~0); {107202#true} is VALID [2022-02-21 04:24:52,038 INFO L290 TraceCheckUtils]: 26: Hoare triple {107202#true} assume !(0 == ~E_4~0); {107202#true} is VALID [2022-02-21 04:24:52,038 INFO L290 TraceCheckUtils]: 27: Hoare triple {107202#true} assume !(0 == ~E_5~0); {107202#true} is VALID [2022-02-21 04:24:52,039 INFO L290 TraceCheckUtils]: 28: Hoare triple {107202#true} assume !(0 == ~E_6~0); {107202#true} is VALID [2022-02-21 04:24:52,039 INFO L290 TraceCheckUtils]: 29: Hoare triple {107202#true} assume !(0 == ~E_7~0); {107202#true} is VALID [2022-02-21 04:24:52,039 INFO L290 TraceCheckUtils]: 30: Hoare triple {107202#true} assume !(0 == ~E_8~0); {107202#true} is VALID [2022-02-21 04:24:52,039 INFO L290 TraceCheckUtils]: 31: Hoare triple {107202#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {107202#true} is VALID [2022-02-21 04:24:52,039 INFO L290 TraceCheckUtils]: 32: Hoare triple {107202#true} assume !(1 == ~m_pc~0); {107202#true} is VALID [2022-02-21 04:24:52,039 INFO L290 TraceCheckUtils]: 33: Hoare triple {107202#true} is_master_triggered_~__retres1~0#1 := 0; {107202#true} is VALID [2022-02-21 04:24:52,039 INFO L290 TraceCheckUtils]: 34: Hoare triple {107202#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {107202#true} is VALID [2022-02-21 04:24:52,039 INFO L290 TraceCheckUtils]: 35: Hoare triple {107202#true} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {107202#true} is VALID [2022-02-21 04:24:52,039 INFO L290 TraceCheckUtils]: 36: Hoare triple {107202#true} assume !(0 != activate_threads_~tmp~1#1); {107202#true} is VALID [2022-02-21 04:24:52,040 INFO L290 TraceCheckUtils]: 37: Hoare triple {107202#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {107202#true} is VALID [2022-02-21 04:24:52,040 INFO L290 TraceCheckUtils]: 38: Hoare triple {107202#true} assume !(1 == ~t1_pc~0); {107202#true} is VALID [2022-02-21 04:24:52,040 INFO L290 TraceCheckUtils]: 39: Hoare triple {107202#true} is_transmit1_triggered_~__retres1~1#1 := 0; {107202#true} is VALID [2022-02-21 04:24:52,040 INFO L290 TraceCheckUtils]: 40: Hoare triple {107202#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {107202#true} is VALID [2022-02-21 04:24:52,040 INFO L290 TraceCheckUtils]: 41: Hoare triple {107202#true} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {107202#true} is VALID [2022-02-21 04:24:52,040 INFO L290 TraceCheckUtils]: 42: Hoare triple {107202#true} assume !(0 != activate_threads_~tmp___0~0#1); {107202#true} is VALID [2022-02-21 04:24:52,040 INFO L290 TraceCheckUtils]: 43: Hoare triple {107202#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {107202#true} is VALID [2022-02-21 04:24:52,040 INFO L290 TraceCheckUtils]: 44: Hoare triple {107202#true} assume !(1 == ~t2_pc~0); {107202#true} is VALID [2022-02-21 04:24:52,040 INFO L290 TraceCheckUtils]: 45: Hoare triple {107202#true} is_transmit2_triggered_~__retres1~2#1 := 0; {107202#true} is VALID [2022-02-21 04:24:52,041 INFO L290 TraceCheckUtils]: 46: Hoare triple {107202#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {107202#true} is VALID [2022-02-21 04:24:52,041 INFO L290 TraceCheckUtils]: 47: Hoare triple {107202#true} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {107202#true} is VALID [2022-02-21 04:24:52,041 INFO L290 TraceCheckUtils]: 48: Hoare triple {107202#true} assume !(0 != activate_threads_~tmp___1~0#1); {107202#true} is VALID [2022-02-21 04:24:52,041 INFO L290 TraceCheckUtils]: 49: Hoare triple {107202#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {107202#true} is VALID [2022-02-21 04:24:52,041 INFO L290 TraceCheckUtils]: 50: Hoare triple {107202#true} assume !(1 == ~t3_pc~0); {107202#true} is VALID [2022-02-21 04:24:52,041 INFO L290 TraceCheckUtils]: 51: Hoare triple {107202#true} is_transmit3_triggered_~__retres1~3#1 := 0; {107204#(= |ULTIMATE.start_is_transmit3_triggered_~__retres1~3#1| 0)} is VALID [2022-02-21 04:24:52,042 INFO L290 TraceCheckUtils]: 52: Hoare triple {107204#(= |ULTIMATE.start_is_transmit3_triggered_~__retres1~3#1| 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {107205#(= |ULTIMATE.start_is_transmit3_triggered_#res#1| 0)} is VALID [2022-02-21 04:24:52,042 INFO L290 TraceCheckUtils]: 53: Hoare triple {107205#(= |ULTIMATE.start_is_transmit3_triggered_#res#1| 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {107206#(= |ULTIMATE.start_activate_threads_~tmp___2~0#1| 0)} is VALID [2022-02-21 04:24:52,042 INFO L290 TraceCheckUtils]: 54: Hoare triple {107206#(= |ULTIMATE.start_activate_threads_~tmp___2~0#1| 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {107203#false} is VALID [2022-02-21 04:24:52,042 INFO L290 TraceCheckUtils]: 55: Hoare triple {107203#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {107203#false} is VALID [2022-02-21 04:24:52,042 INFO L290 TraceCheckUtils]: 56: Hoare triple {107203#false} assume 1 == ~t4_pc~0; {107203#false} is VALID [2022-02-21 04:24:52,043 INFO L290 TraceCheckUtils]: 57: Hoare triple {107203#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {107203#false} is VALID [2022-02-21 04:24:52,043 INFO L290 TraceCheckUtils]: 58: Hoare triple {107203#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {107203#false} is VALID [2022-02-21 04:24:52,043 INFO L290 TraceCheckUtils]: 59: Hoare triple {107203#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {107203#false} is VALID [2022-02-21 04:24:52,043 INFO L290 TraceCheckUtils]: 60: Hoare triple {107203#false} assume !(0 != activate_threads_~tmp___3~0#1); {107203#false} is VALID [2022-02-21 04:24:52,043 INFO L290 TraceCheckUtils]: 61: Hoare triple {107203#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {107203#false} is VALID [2022-02-21 04:24:52,043 INFO L290 TraceCheckUtils]: 62: Hoare triple {107203#false} assume !(1 == ~t5_pc~0); {107203#false} is VALID [2022-02-21 04:24:52,043 INFO L290 TraceCheckUtils]: 63: Hoare triple {107203#false} is_transmit5_triggered_~__retres1~5#1 := 0; {107203#false} is VALID [2022-02-21 04:24:52,043 INFO L290 TraceCheckUtils]: 64: Hoare triple {107203#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {107203#false} is VALID [2022-02-21 04:24:52,044 INFO L290 TraceCheckUtils]: 65: Hoare triple {107203#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {107203#false} is VALID [2022-02-21 04:24:52,044 INFO L290 TraceCheckUtils]: 66: Hoare triple {107203#false} assume !(0 != activate_threads_~tmp___4~0#1); {107203#false} is VALID [2022-02-21 04:24:52,044 INFO L290 TraceCheckUtils]: 67: Hoare triple {107203#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {107203#false} is VALID [2022-02-21 04:24:52,044 INFO L290 TraceCheckUtils]: 68: Hoare triple {107203#false} assume 1 == ~t6_pc~0; {107203#false} is VALID [2022-02-21 04:24:52,044 INFO L290 TraceCheckUtils]: 69: Hoare triple {107203#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {107203#false} is VALID [2022-02-21 04:24:52,044 INFO L290 TraceCheckUtils]: 70: Hoare triple {107203#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {107203#false} is VALID [2022-02-21 04:24:52,044 INFO L290 TraceCheckUtils]: 71: Hoare triple {107203#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {107203#false} is VALID [2022-02-21 04:24:52,044 INFO L290 TraceCheckUtils]: 72: Hoare triple {107203#false} assume !(0 != activate_threads_~tmp___5~0#1); {107203#false} is VALID [2022-02-21 04:24:52,044 INFO L290 TraceCheckUtils]: 73: Hoare triple {107203#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {107203#false} is VALID [2022-02-21 04:24:52,044 INFO L290 TraceCheckUtils]: 74: Hoare triple {107203#false} assume !(1 == ~t7_pc~0); {107203#false} is VALID [2022-02-21 04:24:52,045 INFO L290 TraceCheckUtils]: 75: Hoare triple {107203#false} is_transmit7_triggered_~__retres1~7#1 := 0; {107203#false} is VALID [2022-02-21 04:24:52,045 INFO L290 TraceCheckUtils]: 76: Hoare triple {107203#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {107203#false} is VALID [2022-02-21 04:24:52,045 INFO L290 TraceCheckUtils]: 77: Hoare triple {107203#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {107203#false} is VALID [2022-02-21 04:24:52,045 INFO L290 TraceCheckUtils]: 78: Hoare triple {107203#false} assume !(0 != activate_threads_~tmp___6~0#1); {107203#false} is VALID [2022-02-21 04:24:52,045 INFO L290 TraceCheckUtils]: 79: Hoare triple {107203#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {107203#false} is VALID [2022-02-21 04:24:52,045 INFO L290 TraceCheckUtils]: 80: Hoare triple {107203#false} assume 1 == ~t8_pc~0; {107203#false} is VALID [2022-02-21 04:24:52,045 INFO L290 TraceCheckUtils]: 81: Hoare triple {107203#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {107203#false} is VALID [2022-02-21 04:24:52,045 INFO L290 TraceCheckUtils]: 82: Hoare triple {107203#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {107203#false} is VALID [2022-02-21 04:24:52,045 INFO L290 TraceCheckUtils]: 83: Hoare triple {107203#false} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {107203#false} is VALID [2022-02-21 04:24:52,046 INFO L290 TraceCheckUtils]: 84: Hoare triple {107203#false} assume !(0 != activate_threads_~tmp___7~0#1); {107203#false} is VALID [2022-02-21 04:24:52,046 INFO L290 TraceCheckUtils]: 85: Hoare triple {107203#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {107203#false} is VALID [2022-02-21 04:24:52,046 INFO L290 TraceCheckUtils]: 86: Hoare triple {107203#false} assume !(1 == ~M_E~0); {107203#false} is VALID [2022-02-21 04:24:52,046 INFO L290 TraceCheckUtils]: 87: Hoare triple {107203#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {107203#false} is VALID [2022-02-21 04:24:52,046 INFO L290 TraceCheckUtils]: 88: Hoare triple {107203#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {107203#false} is VALID [2022-02-21 04:24:52,046 INFO L290 TraceCheckUtils]: 89: Hoare triple {107203#false} assume !(1 == ~T3_E~0); {107203#false} is VALID [2022-02-21 04:24:52,046 INFO L290 TraceCheckUtils]: 90: Hoare triple {107203#false} assume !(1 == ~T4_E~0); {107203#false} is VALID [2022-02-21 04:24:52,046 INFO L290 TraceCheckUtils]: 91: Hoare triple {107203#false} assume !(1 == ~T5_E~0); {107203#false} is VALID [2022-02-21 04:24:52,046 INFO L290 TraceCheckUtils]: 92: Hoare triple {107203#false} assume !(1 == ~T6_E~0); {107203#false} is VALID [2022-02-21 04:24:52,047 INFO L290 TraceCheckUtils]: 93: Hoare triple {107203#false} assume !(1 == ~T7_E~0); {107203#false} is VALID [2022-02-21 04:24:52,047 INFO L290 TraceCheckUtils]: 94: Hoare triple {107203#false} assume !(1 == ~T8_E~0); {107203#false} is VALID [2022-02-21 04:24:52,047 INFO L290 TraceCheckUtils]: 95: Hoare triple {107203#false} assume 1 == ~E_1~0;~E_1~0 := 2; {107203#false} is VALID [2022-02-21 04:24:52,047 INFO L290 TraceCheckUtils]: 96: Hoare triple {107203#false} assume !(1 == ~E_2~0); {107203#false} is VALID [2022-02-21 04:24:52,047 INFO L290 TraceCheckUtils]: 97: Hoare triple {107203#false} assume !(1 == ~E_3~0); {107203#false} is VALID [2022-02-21 04:24:52,047 INFO L290 TraceCheckUtils]: 98: Hoare triple {107203#false} assume !(1 == ~E_4~0); {107203#false} is VALID [2022-02-21 04:24:52,047 INFO L290 TraceCheckUtils]: 99: Hoare triple {107203#false} assume !(1 == ~E_5~0); {107203#false} is VALID [2022-02-21 04:24:52,047 INFO L290 TraceCheckUtils]: 100: Hoare triple {107203#false} assume !(1 == ~E_6~0); {107203#false} is VALID [2022-02-21 04:24:52,047 INFO L290 TraceCheckUtils]: 101: Hoare triple {107203#false} assume !(1 == ~E_7~0); {107203#false} is VALID [2022-02-21 04:24:52,048 INFO L290 TraceCheckUtils]: 102: Hoare triple {107203#false} assume !(1 == ~E_8~0); {107203#false} is VALID [2022-02-21 04:24:52,048 INFO L290 TraceCheckUtils]: 103: Hoare triple {107203#false} assume { :end_inline_reset_delta_events } true; {107203#false} is VALID [2022-02-21 04:24:52,048 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:52,048 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:52,048 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226354835] [2022-02-21 04:24:52,048 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226354835] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:52,048 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:52,049 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:24:52,049 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1444018992] [2022-02-21 04:24:52,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:52,049 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:52,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:52,049 INFO L85 PathProgramCache]: Analyzing trace with hash -1851325888, now seen corresponding path program 1 times [2022-02-21 04:24:52,050 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:52,050 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902038645] [2022-02-21 04:24:52,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:52,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:52,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:52,069 INFO L290 TraceCheckUtils]: 0: Hoare triple {107207#true} assume !false; {107207#true} is VALID [2022-02-21 04:24:52,069 INFO L290 TraceCheckUtils]: 1: Hoare triple {107207#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {107207#true} is VALID [2022-02-21 04:24:52,069 INFO L290 TraceCheckUtils]: 2: Hoare triple {107207#true} assume !false; {107207#true} is VALID [2022-02-21 04:24:52,070 INFO L290 TraceCheckUtils]: 3: Hoare triple {107207#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {107207#true} is VALID [2022-02-21 04:24:52,070 INFO L290 TraceCheckUtils]: 4: Hoare triple {107207#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {107207#true} is VALID [2022-02-21 04:24:52,070 INFO L290 TraceCheckUtils]: 5: Hoare triple {107207#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {107207#true} is VALID [2022-02-21 04:24:52,070 INFO L290 TraceCheckUtils]: 6: Hoare triple {107207#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {107207#true} is VALID [2022-02-21 04:24:52,070 INFO L290 TraceCheckUtils]: 7: Hoare triple {107207#true} assume !(0 != eval_~tmp~0#1); {107207#true} is VALID [2022-02-21 04:24:52,070 INFO L290 TraceCheckUtils]: 8: Hoare triple {107207#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {107207#true} is VALID [2022-02-21 04:24:52,070 INFO L290 TraceCheckUtils]: 9: Hoare triple {107207#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {107207#true} is VALID [2022-02-21 04:24:52,070 INFO L290 TraceCheckUtils]: 10: Hoare triple {107207#true} assume !(0 == ~M_E~0); {107207#true} is VALID [2022-02-21 04:24:52,071 INFO L290 TraceCheckUtils]: 11: Hoare triple {107207#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {107207#true} is VALID [2022-02-21 04:24:52,071 INFO L290 TraceCheckUtils]: 12: Hoare triple {107207#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {107207#true} is VALID [2022-02-21 04:24:52,071 INFO L290 TraceCheckUtils]: 13: Hoare triple {107207#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {107207#true} is VALID [2022-02-21 04:24:52,071 INFO L290 TraceCheckUtils]: 14: Hoare triple {107207#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,071 INFO L290 TraceCheckUtils]: 15: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T5_E~0); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,072 INFO L290 TraceCheckUtils]: 16: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,072 INFO L290 TraceCheckUtils]: 17: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,072 INFO L290 TraceCheckUtils]: 18: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~T8_E~0); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,072 INFO L290 TraceCheckUtils]: 19: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,073 INFO L290 TraceCheckUtils]: 20: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,073 INFO L290 TraceCheckUtils]: 21: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,073 INFO L290 TraceCheckUtils]: 22: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,073 INFO L290 TraceCheckUtils]: 23: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_5~0); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,074 INFO L290 TraceCheckUtils]: 24: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,074 INFO L290 TraceCheckUtils]: 25: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,074 INFO L290 TraceCheckUtils]: 26: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 == ~E_8~0); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,074 INFO L290 TraceCheckUtils]: 27: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,075 INFO L290 TraceCheckUtils]: 28: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~m_pc~0); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,075 INFO L290 TraceCheckUtils]: 29: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,075 INFO L290 TraceCheckUtils]: 30: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,075 INFO L290 TraceCheckUtils]: 31: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,076 INFO L290 TraceCheckUtils]: 32: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,076 INFO L290 TraceCheckUtils]: 33: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,076 INFO L290 TraceCheckUtils]: 34: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t1_pc~0); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,076 INFO L290 TraceCheckUtils]: 35: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,077 INFO L290 TraceCheckUtils]: 36: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,077 INFO L290 TraceCheckUtils]: 37: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,077 INFO L290 TraceCheckUtils]: 38: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,077 INFO L290 TraceCheckUtils]: 39: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,077 INFO L290 TraceCheckUtils]: 40: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t2_pc~0); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,078 INFO L290 TraceCheckUtils]: 41: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,078 INFO L290 TraceCheckUtils]: 42: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,078 INFO L290 TraceCheckUtils]: 43: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,078 INFO L290 TraceCheckUtils]: 44: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,079 INFO L290 TraceCheckUtils]: 45: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,079 INFO L290 TraceCheckUtils]: 46: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t3_pc~0); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,079 INFO L290 TraceCheckUtils]: 47: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,079 INFO L290 TraceCheckUtils]: 48: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,080 INFO L290 TraceCheckUtils]: 49: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,080 INFO L290 TraceCheckUtils]: 50: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,080 INFO L290 TraceCheckUtils]: 51: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,080 INFO L290 TraceCheckUtils]: 52: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t4_pc~0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,081 INFO L290 TraceCheckUtils]: 53: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,081 INFO L290 TraceCheckUtils]: 54: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,081 INFO L290 TraceCheckUtils]: 55: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,081 INFO L290 TraceCheckUtils]: 56: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,082 INFO L290 TraceCheckUtils]: 57: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,082 INFO L290 TraceCheckUtils]: 58: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t5_pc~0); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,082 INFO L290 TraceCheckUtils]: 59: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,082 INFO L290 TraceCheckUtils]: 60: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,083 INFO L290 TraceCheckUtils]: 61: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,083 INFO L290 TraceCheckUtils]: 62: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,083 INFO L290 TraceCheckUtils]: 63: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,084 INFO L290 TraceCheckUtils]: 64: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t6_pc~0); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,084 INFO L290 TraceCheckUtils]: 65: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,084 INFO L290 TraceCheckUtils]: 66: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,084 INFO L290 TraceCheckUtils]: 67: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,085 INFO L290 TraceCheckUtils]: 68: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,085 INFO L290 TraceCheckUtils]: 69: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,085 INFO L290 TraceCheckUtils]: 70: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~t7_pc~0); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,085 INFO L290 TraceCheckUtils]: 71: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,086 INFO L290 TraceCheckUtils]: 72: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,086 INFO L290 TraceCheckUtils]: 73: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,086 INFO L290 TraceCheckUtils]: 74: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,086 INFO L290 TraceCheckUtils]: 75: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,087 INFO L290 TraceCheckUtils]: 76: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~t8_pc~0; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,087 INFO L290 TraceCheckUtils]: 77: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,087 INFO L290 TraceCheckUtils]: 78: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,087 INFO L290 TraceCheckUtils]: 79: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,087 INFO L290 TraceCheckUtils]: 80: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,088 INFO L290 TraceCheckUtils]: 81: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,088 INFO L290 TraceCheckUtils]: 82: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,088 INFO L290 TraceCheckUtils]: 83: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,088 INFO L290 TraceCheckUtils]: 84: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,089 INFO L290 TraceCheckUtils]: 85: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {107209#(= (+ (- 1) ~T4_E~0) 0)} is VALID [2022-02-21 04:24:52,089 INFO L290 TraceCheckUtils]: 86: Hoare triple {107209#(= (+ (- 1) ~T4_E~0) 0)} assume !(1 == ~T4_E~0); {107208#false} is VALID [2022-02-21 04:24:52,089 INFO L290 TraceCheckUtils]: 87: Hoare triple {107208#false} assume !(1 == ~T5_E~0); {107208#false} is VALID [2022-02-21 04:24:52,089 INFO L290 TraceCheckUtils]: 88: Hoare triple {107208#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {107208#false} is VALID [2022-02-21 04:24:52,089 INFO L290 TraceCheckUtils]: 89: Hoare triple {107208#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {107208#false} is VALID [2022-02-21 04:24:52,089 INFO L290 TraceCheckUtils]: 90: Hoare triple {107208#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {107208#false} is VALID [2022-02-21 04:24:52,090 INFO L290 TraceCheckUtils]: 91: Hoare triple {107208#false} assume 1 == ~E_1~0;~E_1~0 := 2; {107208#false} is VALID [2022-02-21 04:24:52,090 INFO L290 TraceCheckUtils]: 92: Hoare triple {107208#false} assume 1 == ~E_2~0;~E_2~0 := 2; {107208#false} is VALID [2022-02-21 04:24:52,090 INFO L290 TraceCheckUtils]: 93: Hoare triple {107208#false} assume 1 == ~E_3~0;~E_3~0 := 2; {107208#false} is VALID [2022-02-21 04:24:52,090 INFO L290 TraceCheckUtils]: 94: Hoare triple {107208#false} assume !(1 == ~E_4~0); {107208#false} is VALID [2022-02-21 04:24:52,090 INFO L290 TraceCheckUtils]: 95: Hoare triple {107208#false} assume 1 == ~E_5~0;~E_5~0 := 2; {107208#false} is VALID [2022-02-21 04:24:52,090 INFO L290 TraceCheckUtils]: 96: Hoare triple {107208#false} assume 1 == ~E_6~0;~E_6~0 := 2; {107208#false} is VALID [2022-02-21 04:24:52,090 INFO L290 TraceCheckUtils]: 97: Hoare triple {107208#false} assume 1 == ~E_7~0;~E_7~0 := 2; {107208#false} is VALID [2022-02-21 04:24:52,090 INFO L290 TraceCheckUtils]: 98: Hoare triple {107208#false} assume 1 == ~E_8~0;~E_8~0 := 2; {107208#false} is VALID [2022-02-21 04:24:52,090 INFO L290 TraceCheckUtils]: 99: Hoare triple {107208#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {107208#false} is VALID [2022-02-21 04:24:52,091 INFO L290 TraceCheckUtils]: 100: Hoare triple {107208#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {107208#false} is VALID [2022-02-21 04:24:52,091 INFO L290 TraceCheckUtils]: 101: Hoare triple {107208#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {107208#false} is VALID [2022-02-21 04:24:52,091 INFO L290 TraceCheckUtils]: 102: Hoare triple {107208#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {107208#false} is VALID [2022-02-21 04:24:52,091 INFO L290 TraceCheckUtils]: 103: Hoare triple {107208#false} assume !(0 == start_simulation_~tmp~3#1); {107208#false} is VALID [2022-02-21 04:24:52,091 INFO L290 TraceCheckUtils]: 104: Hoare triple {107208#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; {107208#false} is VALID [2022-02-21 04:24:52,091 INFO L290 TraceCheckUtils]: 105: Hoare triple {107208#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; {107208#false} is VALID [2022-02-21 04:24:52,091 INFO L290 TraceCheckUtils]: 106: Hoare triple {107208#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; {107208#false} is VALID [2022-02-21 04:24:52,091 INFO L290 TraceCheckUtils]: 107: Hoare triple {107208#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {107208#false} is VALID [2022-02-21 04:24:52,091 INFO L290 TraceCheckUtils]: 108: Hoare triple {107208#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {107208#false} is VALID [2022-02-21 04:24:52,092 INFO L290 TraceCheckUtils]: 109: Hoare triple {107208#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {107208#false} is VALID [2022-02-21 04:24:52,092 INFO L290 TraceCheckUtils]: 110: Hoare triple {107208#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {107208#false} is VALID [2022-02-21 04:24:52,092 INFO L290 TraceCheckUtils]: 111: Hoare triple {107208#false} assume !(0 != start_simulation_~tmp___0~1#1); {107208#false} is VALID [2022-02-21 04:24:52,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:52,092 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:52,092 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902038645] [2022-02-21 04:24:52,093 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902038645] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:52,093 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:52,093 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:52,093 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753354554] [2022-02-21 04:24:52,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:52,093 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:52,093 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:52,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:24:52,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:24:52,094 INFO L87 Difference]: Start difference. First operand 11561 states and 16800 transitions. cyclomatic complexity: 5247 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:18,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:18,243 INFO L93 Difference]: Finished difference Result 30699 states and 44801 transitions. [2022-02-21 04:25:18,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:25:18,243 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:18,297 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 104 edges. 104 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:18,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30699 states and 44801 transitions.