./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.09.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.09.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:24:13,754 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:24:13,757 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:24:13,791 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:24:13,792 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:24:13,795 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:24:13,796 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:24:13,798 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:24:13,800 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:24:13,803 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:24:13,804 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:24:13,805 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:24:13,805 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:24:13,807 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:24:13,808 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:24:13,811 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:24:13,812 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:24:13,812 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:24:13,815 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:24:13,820 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:24:13,821 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:24:13,822 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:24:13,824 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:24:13,824 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:24:13,829 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:24:13,830 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:24:13,830 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:24:13,832 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:24:13,832 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:24:13,833 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:24:13,833 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:24:13,834 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:24:13,835 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:24:13,836 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:24:13,837 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:24:13,837 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:24:13,838 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:24:13,838 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:24:13,838 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:24:13,839 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:24:13,839 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:24:13,840 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:24:13,872 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:24:13,872 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:24:13,873 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:24:13,873 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:24:13,874 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:24:13,874 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:24:13,874 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:24:13,875 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:24:13,875 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:24:13,875 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:24:13,875 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:24:13,876 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:24:13,876 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:24:13,876 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:24:13,876 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:24:13,876 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:24:13,876 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:24:13,877 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:24:13,877 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:24:13,877 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:24:13,877 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:24:13,877 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:24:13,877 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:24:13,877 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:24:13,879 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:24:13,879 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:24:13,879 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:24:13,879 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:24:13,879 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:24:13,880 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:24:13,880 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:24:13,881 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:24:13,881 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 [2022-02-21 04:24:14,094 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:24:14,110 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:24:14,112 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:24:14,113 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:24:14,113 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:24:14,114 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.09.cil.c [2022-02-21 04:24:14,168 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fb130496c/c406fce0561d48608919382169a9bfac/FLAG6175fb899 [2022-02-21 04:24:14,595 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:14,596 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.09.cil.c [2022-02-21 04:24:14,611 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fb130496c/c406fce0561d48608919382169a9bfac/FLAG6175fb899 [2022-02-21 04:24:14,626 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fb130496c/c406fce0561d48608919382169a9bfac [2022-02-21 04:24:14,628 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:14,630 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:14,632 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:14,632 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:14,635 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:14,636 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,637 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6a19da94 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:14, skipping insertion in model container [2022-02-21 04:24:14,637 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:14" (1/1) ... [2022-02-21 04:24:14,643 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:14,684 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:14,840 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.09.cil.c[706,719] [2022-02-21 04:24:14,937 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:14,945 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:14,953 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.09.cil.c[706,719] [2022-02-21 04:24:14,997 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:15,010 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:15,011 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15 WrapperNode [2022-02-21 04:24:15,011 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:15,012 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:15,017 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:15,018 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:15,023 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15" (1/1) ... [2022-02-21 04:24:15,037 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15" (1/1) ... [2022-02-21 04:24:15,130 INFO L137 Inliner]: procedures = 46, calls = 57, calls flagged for inlining = 52, calls inlined = 170, statements flattened = 2581 [2022-02-21 04:24:15,131 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:15,132 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:15,132 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:15,132 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:15,138 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15" (1/1) ... [2022-02-21 04:24:15,138 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15" (1/1) ... [2022-02-21 04:24:15,149 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15" (1/1) ... [2022-02-21 04:24:15,149 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15" (1/1) ... [2022-02-21 04:24:15,194 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15" (1/1) ... [2022-02-21 04:24:15,226 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15" (1/1) ... [2022-02-21 04:24:15,230 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15" (1/1) ... [2022-02-21 04:24:15,240 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:15,240 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:15,241 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:15,241 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:15,242 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15" (1/1) ... [2022-02-21 04:24:15,246 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:15,253 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:15,263 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:15,280 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:15,304 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:15,304 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:15,304 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:15,304 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:15,438 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:15,440 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:16,732 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:16,750 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:16,751 INFO L299 CfgBuilder]: Removed 13 assume(true) statements. [2022-02-21 04:24:16,753 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:16 BoogieIcfgContainer [2022-02-21 04:24:16,753 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:16,754 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:16,754 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:16,757 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:16,757 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:16,757 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:14" (1/3) ... [2022-02-21 04:24:16,758 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@28e9a5a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:16, skipping insertion in model container [2022-02-21 04:24:16,758 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:16,758 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:15" (2/3) ... [2022-02-21 04:24:16,759 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@28e9a5a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:16, skipping insertion in model container [2022-02-21 04:24:16,759 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:16,759 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:16" (3/3) ... [2022-02-21 04:24:16,760 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.09.cil.c [2022-02-21 04:24:16,812 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:16,812 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:16,812 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:16,812 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:16,812 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:16,812 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:16,812 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:16,812 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:16,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,011 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 972 [2022-02-21 04:24:17,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:17,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:17,020 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,020 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,020 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:17,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:17,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 972 [2022-02-21 04:24:17,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:17,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:17,088 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,088 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:17,093 INFO L791 eck$LassoCheckResult]: Stem: 531#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 999#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 220#L1359true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1059#L634true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 721#L641true assume !(1 == ~m_i~0);~m_st~0 := 2; 769#L641-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 695#L646-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 483#L651-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 972#L656-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 327#L661-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 930#L666-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 849#L671-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 673#L676-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 374#L681-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 224#L686-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1090#L922true assume !(0 == ~M_E~0); 1027#L922-2true assume !(0 == ~T1_E~0); 1047#L927-1true assume !(0 == ~T2_E~0); 539#L932-1true assume !(0 == ~T3_E~0); 428#L937-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 482#L942-1true assume !(0 == ~T5_E~0); 725#L947-1true assume !(0 == ~T6_E~0); 543#L952-1true assume !(0 == ~T7_E~0); 620#L957-1true assume !(0 == ~T8_E~0); 969#L962-1true assume !(0 == ~T9_E~0); 409#L967-1true assume !(0 == ~E_1~0); 936#L972-1true assume !(0 == ~E_2~0); 704#L977-1true assume 0 == ~E_3~0;~E_3~0 := 1; 1038#L982-1true assume !(0 == ~E_4~0); 105#L987-1true assume !(0 == ~E_5~0); 109#L992-1true assume !(0 == ~E_6~0); 356#L997-1true assume !(0 == ~E_7~0); 880#L1002-1true assume !(0 == ~E_8~0); 346#L1007-1true assume !(0 == ~E_9~0); 8#L1012-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 872#L443true assume !(1 == ~m_pc~0); 557#L443-2true is_master_triggered_~__retres1~0#1 := 0; 548#L454true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 962#L455true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 190#L1140true assume !(0 != activate_threads_~tmp~1#1); 63#L1140-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 896#L462true assume 1 == ~t1_pc~0; 450#L463true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 942#L473true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48#L474true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 568#L1148true assume !(0 != activate_threads_~tmp___0~0#1); 315#L1148-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 980#L481true assume !(1 == ~t2_pc~0); 774#L481-2true is_transmit2_triggered_~__retres1~2#1 := 0; 529#L492true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 426#L493true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 237#L1156true assume !(0 != activate_threads_~tmp___1~0#1); 299#L1156-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1082#L500true assume 1 == ~t3_pc~0; 462#L501true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 738#L511true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 688#L512true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 765#L1164true assume !(0 != activate_threads_~tmp___2~0#1); 9#L1164-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 750#L519true assume 1 == ~t4_pc~0; 156#L520true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 298#L530true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 578#L531true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 210#L1172true assume !(0 != activate_threads_~tmp___3~0#1); 504#L1172-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90#L538true assume !(1 == ~t5_pc~0); 827#L538-2true is_transmit5_triggered_~__retres1~5#1 := 0; 43#L549true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 954#L550true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 178#L1180true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 602#L1180-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1103#L557true assume 1 == ~t6_pc~0; 401#L558true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 809#L568true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 146#L569true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 211#L1188true assume !(0 != activate_threads_~tmp___5~0#1); 931#L1188-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1052#L576true assume !(1 == ~t7_pc~0); 303#L576-2true is_transmit7_triggered_~__retres1~7#1 := 0; 400#L587true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 349#L588true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1048#L1196true assume !(0 != activate_threads_~tmp___6~0#1); 657#L1196-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 258#L595true assume 1 == ~t8_pc~0; 1002#L596true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 689#L606true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 845#L607true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 506#L1204true assume !(0 != activate_threads_~tmp___7~0#1); 934#L1204-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 153#L614true assume !(1 == ~t9_pc~0); 451#L614-2true is_transmit9_triggered_~__retres1~9#1 := 0; 101#L625true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 195#L626true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 671#L1212true assume !(0 != activate_threads_~tmp___8~0#1); 238#L1212-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 415#L1025true assume !(1 == ~M_E~0); 461#L1025-2true assume !(1 == ~T1_E~0); 595#L1030-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 745#L1035-1true assume !(1 == ~T3_E~0); 234#L1040-1true assume !(1 == ~T4_E~0); 729#L1045-1true assume !(1 == ~T5_E~0); 184#L1050-1true assume !(1 == ~T6_E~0); 293#L1055-1true assume !(1 == ~T7_E~0); 94#L1060-1true assume !(1 == ~T8_E~0); 125#L1065-1true assume !(1 == ~T9_E~0); 949#L1070-1true assume 1 == ~E_1~0;~E_1~0 := 2; 544#L1075-1true assume !(1 == ~E_2~0); 1086#L1080-1true assume !(1 == ~E_3~0); 536#L1085-1true assume !(1 == ~E_4~0); 839#L1090-1true assume !(1 == ~E_5~0); 967#L1095-1true assume !(1 == ~E_6~0); 576#L1100-1true assume !(1 == ~E_7~0); 583#L1105-1true assume !(1 == ~E_8~0); 82#L1110-1true assume 1 == ~E_9~0;~E_9~0 := 2; 265#L1115-1true assume { :end_inline_reset_delta_events } true; 206#L1396-2true [2022-02-21 04:24:17,095 INFO L793 eck$LassoCheckResult]: Loop: 206#L1396-2true assume !false; 950#L1397true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 966#L897true assume false; 786#L912true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51#L634-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 342#L922-3true assume 0 == ~M_E~0;~M_E~0 := 1; 971#L922-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 174#L927-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 278#L932-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 534#L937-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 77#L942-3true assume !(0 == ~T5_E~0); 624#L947-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 279#L952-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 811#L957-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 833#L962-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 633#L967-3true assume 0 == ~E_1~0;~E_1~0 := 1; 855#L972-3true assume 0 == ~E_2~0;~E_2~0 := 1; 538#L977-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1089#L982-3true assume !(0 == ~E_4~0); 1061#L987-3true assume 0 == ~E_5~0;~E_5~0 := 1; 244#L992-3true assume 0 == ~E_6~0;~E_6~0 := 1; 360#L997-3true assume 0 == ~E_7~0;~E_7~0 := 1; 242#L1002-3true assume 0 == ~E_8~0;~E_8~0 := 1; 494#L1007-3true assume 0 == ~E_9~0;~E_9~0 := 1; 95#L1012-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272#L443-30true assume 1 == ~m_pc~0; 111#L444-10true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 262#L454-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 884#L455-10true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 946#L1140-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 711#L1140-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 332#L462-30true assume !(1 == ~t1_pc~0); 801#L462-32true is_transmit1_triggered_~__retres1~1#1 := 0; 701#L473-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 686#L474-10true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 741#L1148-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1067#L1148-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 323#L481-30true assume 1 == ~t2_pc~0; 157#L482-10true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 666#L492-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 185#L493-10true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 141#L1156-30true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 302#L1156-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 552#L500-30true assume !(1 == ~t3_pc~0); 1068#L500-32true is_transmit3_triggered_~__retres1~3#1 := 0; 362#L511-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194#L512-10true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1026#L1164-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 291#L1164-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 638#L519-30true assume 1 == ~t4_pc~0; 586#L520-10true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 404#L530-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30#L531-10true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 411#L1172-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 519#L1172-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 926#L538-30true assume !(1 == ~t5_pc~0); 865#L538-32true is_transmit5_triggered_~__retres1~5#1 := 0; 281#L549-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 257#L550-10true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 661#L1180-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 138#L1180-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 144#L557-30true assume !(1 == ~t6_pc~0); 368#L557-32true is_transmit6_triggered_~__retres1~6#1 := 0; 389#L568-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 430#L569-10true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1045#L1188-30true assume !(0 != activate_threads_~tmp___5~0#1); 152#L1188-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 511#L576-30true assume !(1 == ~t7_pc~0); 42#L576-32true is_transmit7_triggered_~__retres1~7#1 := 0; 384#L587-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1074#L588-10true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 836#L1196-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 235#L1196-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 215#L595-30true assume !(1 == ~t8_pc~0); 756#L595-32true is_transmit8_triggered_~__retres1~8#1 := 0; 181#L606-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47#L607-10true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 837#L1204-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1093#L1204-32true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 939#L614-30true assume 1 == ~t9_pc~0; 183#L615-10true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 640#L625-10true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 255#L626-10true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96#L1212-30true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 618#L1212-32true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 495#L1025-3true assume 1 == ~M_E~0;~M_E~0 := 2; 317#L1025-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 464#L1030-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 856#L1035-3true assume !(1 == ~T3_E~0); 1018#L1040-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1040#L1045-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 846#L1050-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 687#L1055-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 46#L1060-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 720#L1065-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 713#L1070-3true assume 1 == ~E_1~0;~E_1~0 := 2; 522#L1075-3true assume !(1 == ~E_2~0); 857#L1080-3true assume 1 == ~E_3~0;~E_3~0 := 2; 940#L1085-3true assume 1 == ~E_4~0;~E_4~0 := 2; 698#L1090-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1006#L1095-3true assume 1 == ~E_6~0;~E_6~0 := 2; 728#L1100-3true assume 1 == ~E_7~0;~E_7~0 := 2; 915#L1105-3true assume 1 == ~E_8~0;~E_8~0 := 2; 119#L1110-3true assume 1 == ~E_9~0;~E_9~0 := 2; 777#L1115-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 753#L699-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 122#L751-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 50#L752-1true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 710#L1415true assume !(0 == start_simulation_~tmp~3#1); 408#L1415-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 970#L699-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 413#L751-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 598#L752-2true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1077#L1370true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1062#L1377true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 458#L1378true start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 161#L1428true assume !(0 != start_simulation_~tmp___0~1#1); 206#L1396-2true [2022-02-21 04:24:17,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,104 INFO L85 PathProgramCache]: Analyzing trace with hash 1400170149, now seen corresponding path program 1 times [2022-02-21 04:24:17,110 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,111 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249158965] [2022-02-21 04:24:17,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,285 INFO L290 TraceCheckUtils]: 0: Hoare triple {1105#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {1105#true} is VALID [2022-02-21 04:24:17,286 INFO L290 TraceCheckUtils]: 1: Hoare triple {1105#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {1107#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:17,287 INFO L290 TraceCheckUtils]: 2: Hoare triple {1107#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1107#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:17,288 INFO L290 TraceCheckUtils]: 3: Hoare triple {1107#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1107#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:17,288 INFO L290 TraceCheckUtils]: 4: Hoare triple {1107#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1106#false} is VALID [2022-02-21 04:24:17,289 INFO L290 TraceCheckUtils]: 5: Hoare triple {1106#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1106#false} is VALID [2022-02-21 04:24:17,289 INFO L290 TraceCheckUtils]: 6: Hoare triple {1106#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1106#false} is VALID [2022-02-21 04:24:17,289 INFO L290 TraceCheckUtils]: 7: Hoare triple {1106#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1106#false} is VALID [2022-02-21 04:24:17,290 INFO L290 TraceCheckUtils]: 8: Hoare triple {1106#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1106#false} is VALID [2022-02-21 04:24:17,290 INFO L290 TraceCheckUtils]: 9: Hoare triple {1106#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1106#false} is VALID [2022-02-21 04:24:17,290 INFO L290 TraceCheckUtils]: 10: Hoare triple {1106#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1106#false} is VALID [2022-02-21 04:24:17,290 INFO L290 TraceCheckUtils]: 11: Hoare triple {1106#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1106#false} is VALID [2022-02-21 04:24:17,291 INFO L290 TraceCheckUtils]: 12: Hoare triple {1106#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1106#false} is VALID [2022-02-21 04:24:17,291 INFO L290 TraceCheckUtils]: 13: Hoare triple {1106#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {1106#false} is VALID [2022-02-21 04:24:17,291 INFO L290 TraceCheckUtils]: 14: Hoare triple {1106#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1106#false} is VALID [2022-02-21 04:24:17,291 INFO L290 TraceCheckUtils]: 15: Hoare triple {1106#false} assume !(0 == ~M_E~0); {1106#false} is VALID [2022-02-21 04:24:17,291 INFO L290 TraceCheckUtils]: 16: Hoare triple {1106#false} assume !(0 == ~T1_E~0); {1106#false} is VALID [2022-02-21 04:24:17,291 INFO L290 TraceCheckUtils]: 17: Hoare triple {1106#false} assume !(0 == ~T2_E~0); {1106#false} is VALID [2022-02-21 04:24:17,292 INFO L290 TraceCheckUtils]: 18: Hoare triple {1106#false} assume !(0 == ~T3_E~0); {1106#false} is VALID [2022-02-21 04:24:17,292 INFO L290 TraceCheckUtils]: 19: Hoare triple {1106#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1106#false} is VALID [2022-02-21 04:24:17,292 INFO L290 TraceCheckUtils]: 20: Hoare triple {1106#false} assume !(0 == ~T5_E~0); {1106#false} is VALID [2022-02-21 04:24:17,292 INFO L290 TraceCheckUtils]: 21: Hoare triple {1106#false} assume !(0 == ~T6_E~0); {1106#false} is VALID [2022-02-21 04:24:17,293 INFO L290 TraceCheckUtils]: 22: Hoare triple {1106#false} assume !(0 == ~T7_E~0); {1106#false} is VALID [2022-02-21 04:24:17,293 INFO L290 TraceCheckUtils]: 23: Hoare triple {1106#false} assume !(0 == ~T8_E~0); {1106#false} is VALID [2022-02-21 04:24:17,294 INFO L290 TraceCheckUtils]: 24: Hoare triple {1106#false} assume !(0 == ~T9_E~0); {1106#false} is VALID [2022-02-21 04:24:17,294 INFO L290 TraceCheckUtils]: 25: Hoare triple {1106#false} assume !(0 == ~E_1~0); {1106#false} is VALID [2022-02-21 04:24:17,294 INFO L290 TraceCheckUtils]: 26: Hoare triple {1106#false} assume !(0 == ~E_2~0); {1106#false} is VALID [2022-02-21 04:24:17,294 INFO L290 TraceCheckUtils]: 27: Hoare triple {1106#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1106#false} is VALID [2022-02-21 04:24:17,295 INFO L290 TraceCheckUtils]: 28: Hoare triple {1106#false} assume !(0 == ~E_4~0); {1106#false} is VALID [2022-02-21 04:24:17,295 INFO L290 TraceCheckUtils]: 29: Hoare triple {1106#false} assume !(0 == ~E_5~0); {1106#false} is VALID [2022-02-21 04:24:17,295 INFO L290 TraceCheckUtils]: 30: Hoare triple {1106#false} assume !(0 == ~E_6~0); {1106#false} is VALID [2022-02-21 04:24:17,295 INFO L290 TraceCheckUtils]: 31: Hoare triple {1106#false} assume !(0 == ~E_7~0); {1106#false} is VALID [2022-02-21 04:24:17,295 INFO L290 TraceCheckUtils]: 32: Hoare triple {1106#false} assume !(0 == ~E_8~0); {1106#false} is VALID [2022-02-21 04:24:17,296 INFO L290 TraceCheckUtils]: 33: Hoare triple {1106#false} assume !(0 == ~E_9~0); {1106#false} is VALID [2022-02-21 04:24:17,296 INFO L290 TraceCheckUtils]: 34: Hoare triple {1106#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1106#false} is VALID [2022-02-21 04:24:17,296 INFO L290 TraceCheckUtils]: 35: Hoare triple {1106#false} assume !(1 == ~m_pc~0); {1106#false} is VALID [2022-02-21 04:24:17,296 INFO L290 TraceCheckUtils]: 36: Hoare triple {1106#false} is_master_triggered_~__retres1~0#1 := 0; {1106#false} is VALID [2022-02-21 04:24:17,296 INFO L290 TraceCheckUtils]: 37: Hoare triple {1106#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1106#false} is VALID [2022-02-21 04:24:17,297 INFO L290 TraceCheckUtils]: 38: Hoare triple {1106#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {1106#false} is VALID [2022-02-21 04:24:17,297 INFO L290 TraceCheckUtils]: 39: Hoare triple {1106#false} assume !(0 != activate_threads_~tmp~1#1); {1106#false} is VALID [2022-02-21 04:24:17,297 INFO L290 TraceCheckUtils]: 40: Hoare triple {1106#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1106#false} is VALID [2022-02-21 04:24:17,297 INFO L290 TraceCheckUtils]: 41: Hoare triple {1106#false} assume 1 == ~t1_pc~0; {1106#false} is VALID [2022-02-21 04:24:17,298 INFO L290 TraceCheckUtils]: 42: Hoare triple {1106#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1106#false} is VALID [2022-02-21 04:24:17,298 INFO L290 TraceCheckUtils]: 43: Hoare triple {1106#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1106#false} is VALID [2022-02-21 04:24:17,298 INFO L290 TraceCheckUtils]: 44: Hoare triple {1106#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {1106#false} is VALID [2022-02-21 04:24:17,299 INFO L290 TraceCheckUtils]: 45: Hoare triple {1106#false} assume !(0 != activate_threads_~tmp___0~0#1); {1106#false} is VALID [2022-02-21 04:24:17,299 INFO L290 TraceCheckUtils]: 46: Hoare triple {1106#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1106#false} is VALID [2022-02-21 04:24:17,299 INFO L290 TraceCheckUtils]: 47: Hoare triple {1106#false} assume !(1 == ~t2_pc~0); {1106#false} is VALID [2022-02-21 04:24:17,299 INFO L290 TraceCheckUtils]: 48: Hoare triple {1106#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1106#false} is VALID [2022-02-21 04:24:17,299 INFO L290 TraceCheckUtils]: 49: Hoare triple {1106#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1106#false} is VALID [2022-02-21 04:24:17,301 INFO L290 TraceCheckUtils]: 50: Hoare triple {1106#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1106#false} is VALID [2022-02-21 04:24:17,302 INFO L290 TraceCheckUtils]: 51: Hoare triple {1106#false} assume !(0 != activate_threads_~tmp___1~0#1); {1106#false} is VALID [2022-02-21 04:24:17,302 INFO L290 TraceCheckUtils]: 52: Hoare triple {1106#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1106#false} is VALID [2022-02-21 04:24:17,302 INFO L290 TraceCheckUtils]: 53: Hoare triple {1106#false} assume 1 == ~t3_pc~0; {1106#false} is VALID [2022-02-21 04:24:17,303 INFO L290 TraceCheckUtils]: 54: Hoare triple {1106#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1106#false} is VALID [2022-02-21 04:24:17,304 INFO L290 TraceCheckUtils]: 55: Hoare triple {1106#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1106#false} is VALID [2022-02-21 04:24:17,305 INFO L290 TraceCheckUtils]: 56: Hoare triple {1106#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1106#false} is VALID [2022-02-21 04:24:17,305 INFO L290 TraceCheckUtils]: 57: Hoare triple {1106#false} assume !(0 != activate_threads_~tmp___2~0#1); {1106#false} is VALID [2022-02-21 04:24:17,305 INFO L290 TraceCheckUtils]: 58: Hoare triple {1106#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1106#false} is VALID [2022-02-21 04:24:17,305 INFO L290 TraceCheckUtils]: 59: Hoare triple {1106#false} assume 1 == ~t4_pc~0; {1106#false} is VALID [2022-02-21 04:24:17,305 INFO L290 TraceCheckUtils]: 60: Hoare triple {1106#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1106#false} is VALID [2022-02-21 04:24:17,306 INFO L290 TraceCheckUtils]: 61: Hoare triple {1106#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1106#false} is VALID [2022-02-21 04:24:17,306 INFO L290 TraceCheckUtils]: 62: Hoare triple {1106#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1106#false} is VALID [2022-02-21 04:24:17,307 INFO L290 TraceCheckUtils]: 63: Hoare triple {1106#false} assume !(0 != activate_threads_~tmp___3~0#1); {1106#false} is VALID [2022-02-21 04:24:17,307 INFO L290 TraceCheckUtils]: 64: Hoare triple {1106#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1106#false} is VALID [2022-02-21 04:24:17,309 INFO L290 TraceCheckUtils]: 65: Hoare triple {1106#false} assume !(1 == ~t5_pc~0); {1106#false} is VALID [2022-02-21 04:24:17,309 INFO L290 TraceCheckUtils]: 66: Hoare triple {1106#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1106#false} is VALID [2022-02-21 04:24:17,310 INFO L290 TraceCheckUtils]: 67: Hoare triple {1106#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1106#false} is VALID [2022-02-21 04:24:17,310 INFO L290 TraceCheckUtils]: 68: Hoare triple {1106#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1106#false} is VALID [2022-02-21 04:24:17,310 INFO L290 TraceCheckUtils]: 69: Hoare triple {1106#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1106#false} is VALID [2022-02-21 04:24:17,311 INFO L290 TraceCheckUtils]: 70: Hoare triple {1106#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1106#false} is VALID [2022-02-21 04:24:17,311 INFO L290 TraceCheckUtils]: 71: Hoare triple {1106#false} assume 1 == ~t6_pc~0; {1106#false} is VALID [2022-02-21 04:24:17,311 INFO L290 TraceCheckUtils]: 72: Hoare triple {1106#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {1106#false} is VALID [2022-02-21 04:24:17,311 INFO L290 TraceCheckUtils]: 73: Hoare triple {1106#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1106#false} is VALID [2022-02-21 04:24:17,314 INFO L290 TraceCheckUtils]: 74: Hoare triple {1106#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1106#false} is VALID [2022-02-21 04:24:17,314 INFO L290 TraceCheckUtils]: 75: Hoare triple {1106#false} assume !(0 != activate_threads_~tmp___5~0#1); {1106#false} is VALID [2022-02-21 04:24:17,314 INFO L290 TraceCheckUtils]: 76: Hoare triple {1106#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1106#false} is VALID [2022-02-21 04:24:17,314 INFO L290 TraceCheckUtils]: 77: Hoare triple {1106#false} assume !(1 == ~t7_pc~0); {1106#false} is VALID [2022-02-21 04:24:17,315 INFO L290 TraceCheckUtils]: 78: Hoare triple {1106#false} is_transmit7_triggered_~__retres1~7#1 := 0; {1106#false} is VALID [2022-02-21 04:24:17,315 INFO L290 TraceCheckUtils]: 79: Hoare triple {1106#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1106#false} is VALID [2022-02-21 04:24:17,315 INFO L290 TraceCheckUtils]: 80: Hoare triple {1106#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1106#false} is VALID [2022-02-21 04:24:17,315 INFO L290 TraceCheckUtils]: 81: Hoare triple {1106#false} assume !(0 != activate_threads_~tmp___6~0#1); {1106#false} is VALID [2022-02-21 04:24:17,315 INFO L290 TraceCheckUtils]: 82: Hoare triple {1106#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1106#false} is VALID [2022-02-21 04:24:17,315 INFO L290 TraceCheckUtils]: 83: Hoare triple {1106#false} assume 1 == ~t8_pc~0; {1106#false} is VALID [2022-02-21 04:24:17,316 INFO L290 TraceCheckUtils]: 84: Hoare triple {1106#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1106#false} is VALID [2022-02-21 04:24:17,316 INFO L290 TraceCheckUtils]: 85: Hoare triple {1106#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1106#false} is VALID [2022-02-21 04:24:17,316 INFO L290 TraceCheckUtils]: 86: Hoare triple {1106#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1106#false} is VALID [2022-02-21 04:24:17,316 INFO L290 TraceCheckUtils]: 87: Hoare triple {1106#false} assume !(0 != activate_threads_~tmp___7~0#1); {1106#false} is VALID [2022-02-21 04:24:17,316 INFO L290 TraceCheckUtils]: 88: Hoare triple {1106#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1106#false} is VALID [2022-02-21 04:24:17,317 INFO L290 TraceCheckUtils]: 89: Hoare triple {1106#false} assume !(1 == ~t9_pc~0); {1106#false} is VALID [2022-02-21 04:24:17,317 INFO L290 TraceCheckUtils]: 90: Hoare triple {1106#false} is_transmit9_triggered_~__retres1~9#1 := 0; {1106#false} is VALID [2022-02-21 04:24:17,317 INFO L290 TraceCheckUtils]: 91: Hoare triple {1106#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1106#false} is VALID [2022-02-21 04:24:17,317 INFO L290 TraceCheckUtils]: 92: Hoare triple {1106#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1106#false} is VALID [2022-02-21 04:24:17,317 INFO L290 TraceCheckUtils]: 93: Hoare triple {1106#false} assume !(0 != activate_threads_~tmp___8~0#1); {1106#false} is VALID [2022-02-21 04:24:17,317 INFO L290 TraceCheckUtils]: 94: Hoare triple {1106#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1106#false} is VALID [2022-02-21 04:24:17,318 INFO L290 TraceCheckUtils]: 95: Hoare triple {1106#false} assume !(1 == ~M_E~0); {1106#false} is VALID [2022-02-21 04:24:17,318 INFO L290 TraceCheckUtils]: 96: Hoare triple {1106#false} assume !(1 == ~T1_E~0); {1106#false} is VALID [2022-02-21 04:24:17,318 INFO L290 TraceCheckUtils]: 97: Hoare triple {1106#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1106#false} is VALID [2022-02-21 04:24:17,318 INFO L290 TraceCheckUtils]: 98: Hoare triple {1106#false} assume !(1 == ~T3_E~0); {1106#false} is VALID [2022-02-21 04:24:17,318 INFO L290 TraceCheckUtils]: 99: Hoare triple {1106#false} assume !(1 == ~T4_E~0); {1106#false} is VALID [2022-02-21 04:24:17,318 INFO L290 TraceCheckUtils]: 100: Hoare triple {1106#false} assume !(1 == ~T5_E~0); {1106#false} is VALID [2022-02-21 04:24:17,319 INFO L290 TraceCheckUtils]: 101: Hoare triple {1106#false} assume !(1 == ~T6_E~0); {1106#false} is VALID [2022-02-21 04:24:17,319 INFO L290 TraceCheckUtils]: 102: Hoare triple {1106#false} assume !(1 == ~T7_E~0); {1106#false} is VALID [2022-02-21 04:24:17,326 INFO L290 TraceCheckUtils]: 103: Hoare triple {1106#false} assume !(1 == ~T8_E~0); {1106#false} is VALID [2022-02-21 04:24:17,327 INFO L290 TraceCheckUtils]: 104: Hoare triple {1106#false} assume !(1 == ~T9_E~0); {1106#false} is VALID [2022-02-21 04:24:17,327 INFO L290 TraceCheckUtils]: 105: Hoare triple {1106#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1106#false} is VALID [2022-02-21 04:24:17,329 INFO L290 TraceCheckUtils]: 106: Hoare triple {1106#false} assume !(1 == ~E_2~0); {1106#false} is VALID [2022-02-21 04:24:17,329 INFO L290 TraceCheckUtils]: 107: Hoare triple {1106#false} assume !(1 == ~E_3~0); {1106#false} is VALID [2022-02-21 04:24:17,330 INFO L290 TraceCheckUtils]: 108: Hoare triple {1106#false} assume !(1 == ~E_4~0); {1106#false} is VALID [2022-02-21 04:24:17,330 INFO L290 TraceCheckUtils]: 109: Hoare triple {1106#false} assume !(1 == ~E_5~0); {1106#false} is VALID [2022-02-21 04:24:17,330 INFO L290 TraceCheckUtils]: 110: Hoare triple {1106#false} assume !(1 == ~E_6~0); {1106#false} is VALID [2022-02-21 04:24:17,330 INFO L290 TraceCheckUtils]: 111: Hoare triple {1106#false} assume !(1 == ~E_7~0); {1106#false} is VALID [2022-02-21 04:24:17,330 INFO L290 TraceCheckUtils]: 112: Hoare triple {1106#false} assume !(1 == ~E_8~0); {1106#false} is VALID [2022-02-21 04:24:17,331 INFO L290 TraceCheckUtils]: 113: Hoare triple {1106#false} assume 1 == ~E_9~0;~E_9~0 := 2; {1106#false} is VALID [2022-02-21 04:24:17,331 INFO L290 TraceCheckUtils]: 114: Hoare triple {1106#false} assume { :end_inline_reset_delta_events } true; {1106#false} is VALID [2022-02-21 04:24:17,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,333 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,333 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249158965] [2022-02-21 04:24:17,334 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249158965] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,335 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,335 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:17,336 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209385858] [2022-02-21 04:24:17,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,339 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:17,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:17,341 INFO L85 PathProgramCache]: Analyzing trace with hash -2065415498, now seen corresponding path program 1 times [2022-02-21 04:24:17,341 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:17,341 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046862436] [2022-02-21 04:24:17,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:17,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:17,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:17,378 INFO L290 TraceCheckUtils]: 0: Hoare triple {1108#true} assume !false; {1108#true} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 1: Hoare triple {1108#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1108#true} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 2: Hoare triple {1108#true} assume false; {1109#false} is VALID [2022-02-21 04:24:17,379 INFO L290 TraceCheckUtils]: 3: Hoare triple {1109#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1109#false} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 4: Hoare triple {1109#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1109#false} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 5: Hoare triple {1109#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 6: Hoare triple {1109#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 7: Hoare triple {1109#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 8: Hoare triple {1109#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 9: Hoare triple {1109#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 10: Hoare triple {1109#false} assume !(0 == ~T5_E~0); {1109#false} is VALID [2022-02-21 04:24:17,380 INFO L290 TraceCheckUtils]: 11: Hoare triple {1109#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 12: Hoare triple {1109#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 13: Hoare triple {1109#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 14: Hoare triple {1109#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 15: Hoare triple {1109#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 16: Hoare triple {1109#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 17: Hoare triple {1109#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 18: Hoare triple {1109#false} assume !(0 == ~E_4~0); {1109#false} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 19: Hoare triple {1109#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 20: Hoare triple {1109#false} assume 0 == ~E_6~0;~E_6~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,381 INFO L290 TraceCheckUtils]: 21: Hoare triple {1109#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 22: Hoare triple {1109#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 23: Hoare triple {1109#false} assume 0 == ~E_9~0;~E_9~0 := 1; {1109#false} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 24: Hoare triple {1109#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1109#false} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 25: Hoare triple {1109#false} assume 1 == ~m_pc~0; {1109#false} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 26: Hoare triple {1109#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {1109#false} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 27: Hoare triple {1109#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1109#false} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 28: Hoare triple {1109#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {1109#false} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 29: Hoare triple {1109#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1109#false} is VALID [2022-02-21 04:24:17,382 INFO L290 TraceCheckUtils]: 30: Hoare triple {1109#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1109#false} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 31: Hoare triple {1109#false} assume !(1 == ~t1_pc~0); {1109#false} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 32: Hoare triple {1109#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1109#false} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 33: Hoare triple {1109#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1109#false} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 34: Hoare triple {1109#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {1109#false} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 35: Hoare triple {1109#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1109#false} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 36: Hoare triple {1109#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1109#false} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 37: Hoare triple {1109#false} assume 1 == ~t2_pc~0; {1109#false} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 38: Hoare triple {1109#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1109#false} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 39: Hoare triple {1109#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1109#false} is VALID [2022-02-21 04:24:17,383 INFO L290 TraceCheckUtils]: 40: Hoare triple {1109#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1109#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 41: Hoare triple {1109#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1109#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 42: Hoare triple {1109#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1109#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 43: Hoare triple {1109#false} assume !(1 == ~t3_pc~0); {1109#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 44: Hoare triple {1109#false} is_transmit3_triggered_~__retres1~3#1 := 0; {1109#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 45: Hoare triple {1109#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1109#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 46: Hoare triple {1109#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1109#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 47: Hoare triple {1109#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1109#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 48: Hoare triple {1109#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1109#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 49: Hoare triple {1109#false} assume 1 == ~t4_pc~0; {1109#false} is VALID [2022-02-21 04:24:17,384 INFO L290 TraceCheckUtils]: 50: Hoare triple {1109#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1109#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 51: Hoare triple {1109#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1109#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 52: Hoare triple {1109#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1109#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 53: Hoare triple {1109#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1109#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 54: Hoare triple {1109#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1109#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 55: Hoare triple {1109#false} assume !(1 == ~t5_pc~0); {1109#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 56: Hoare triple {1109#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1109#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 57: Hoare triple {1109#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1109#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 58: Hoare triple {1109#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1109#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 59: Hoare triple {1109#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1109#false} is VALID [2022-02-21 04:24:17,385 INFO L290 TraceCheckUtils]: 60: Hoare triple {1109#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1109#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 61: Hoare triple {1109#false} assume !(1 == ~t6_pc~0); {1109#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 62: Hoare triple {1109#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1109#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 63: Hoare triple {1109#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1109#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 64: Hoare triple {1109#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1109#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 65: Hoare triple {1109#false} assume !(0 != activate_threads_~tmp___5~0#1); {1109#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 66: Hoare triple {1109#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1109#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 67: Hoare triple {1109#false} assume !(1 == ~t7_pc~0); {1109#false} is VALID [2022-02-21 04:24:17,386 INFO L290 TraceCheckUtils]: 68: Hoare triple {1109#false} is_transmit7_triggered_~__retres1~7#1 := 0; {1109#false} is VALID [2022-02-21 04:24:17,387 INFO L290 TraceCheckUtils]: 69: Hoare triple {1109#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1109#false} is VALID [2022-02-21 04:24:17,387 INFO L290 TraceCheckUtils]: 70: Hoare triple {1109#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1109#false} is VALID [2022-02-21 04:24:17,387 INFO L290 TraceCheckUtils]: 71: Hoare triple {1109#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {1109#false} is VALID [2022-02-21 04:24:17,387 INFO L290 TraceCheckUtils]: 72: Hoare triple {1109#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1109#false} is VALID [2022-02-21 04:24:17,387 INFO L290 TraceCheckUtils]: 73: Hoare triple {1109#false} assume !(1 == ~t8_pc~0); {1109#false} is VALID [2022-02-21 04:24:17,389 INFO L290 TraceCheckUtils]: 74: Hoare triple {1109#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1109#false} is VALID [2022-02-21 04:24:17,389 INFO L290 TraceCheckUtils]: 75: Hoare triple {1109#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1109#false} is VALID [2022-02-21 04:24:17,389 INFO L290 TraceCheckUtils]: 76: Hoare triple {1109#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1109#false} is VALID [2022-02-21 04:24:17,389 INFO L290 TraceCheckUtils]: 77: Hoare triple {1109#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1109#false} is VALID [2022-02-21 04:24:17,389 INFO L290 TraceCheckUtils]: 78: Hoare triple {1109#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1109#false} is VALID [2022-02-21 04:24:17,389 INFO L290 TraceCheckUtils]: 79: Hoare triple {1109#false} assume 1 == ~t9_pc~0; {1109#false} is VALID [2022-02-21 04:24:17,390 INFO L290 TraceCheckUtils]: 80: Hoare triple {1109#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1109#false} is VALID [2022-02-21 04:24:17,390 INFO L290 TraceCheckUtils]: 81: Hoare triple {1109#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1109#false} is VALID [2022-02-21 04:24:17,390 INFO L290 TraceCheckUtils]: 82: Hoare triple {1109#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1109#false} is VALID [2022-02-21 04:24:17,390 INFO L290 TraceCheckUtils]: 83: Hoare triple {1109#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {1109#false} is VALID [2022-02-21 04:24:17,391 INFO L290 TraceCheckUtils]: 84: Hoare triple {1109#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1109#false} is VALID [2022-02-21 04:24:17,391 INFO L290 TraceCheckUtils]: 85: Hoare triple {1109#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,391 INFO L290 TraceCheckUtils]: 86: Hoare triple {1109#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,391 INFO L290 TraceCheckUtils]: 87: Hoare triple {1109#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,392 INFO L290 TraceCheckUtils]: 88: Hoare triple {1109#false} assume !(1 == ~T3_E~0); {1109#false} is VALID [2022-02-21 04:24:17,392 INFO L290 TraceCheckUtils]: 89: Hoare triple {1109#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,395 INFO L290 TraceCheckUtils]: 90: Hoare triple {1109#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,395 INFO L290 TraceCheckUtils]: 91: Hoare triple {1109#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,395 INFO L290 TraceCheckUtils]: 92: Hoare triple {1109#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,395 INFO L290 TraceCheckUtils]: 93: Hoare triple {1109#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,396 INFO L290 TraceCheckUtils]: 94: Hoare triple {1109#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,396 INFO L290 TraceCheckUtils]: 95: Hoare triple {1109#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,396 INFO L290 TraceCheckUtils]: 96: Hoare triple {1109#false} assume !(1 == ~E_2~0); {1109#false} is VALID [2022-02-21 04:24:17,396 INFO L290 TraceCheckUtils]: 97: Hoare triple {1109#false} assume 1 == ~E_3~0;~E_3~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,396 INFO L290 TraceCheckUtils]: 98: Hoare triple {1109#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 99: Hoare triple {1109#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 100: Hoare triple {1109#false} assume 1 == ~E_6~0;~E_6~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 101: Hoare triple {1109#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 102: Hoare triple {1109#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 103: Hoare triple {1109#false} assume 1 == ~E_9~0;~E_9~0 := 2; {1109#false} is VALID [2022-02-21 04:24:17,397 INFO L290 TraceCheckUtils]: 104: Hoare triple {1109#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {1109#false} is VALID [2022-02-21 04:24:17,398 INFO L290 TraceCheckUtils]: 105: Hoare triple {1109#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {1109#false} is VALID [2022-02-21 04:24:17,398 INFO L290 TraceCheckUtils]: 106: Hoare triple {1109#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {1109#false} is VALID [2022-02-21 04:24:17,398 INFO L290 TraceCheckUtils]: 107: Hoare triple {1109#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {1109#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 108: Hoare triple {1109#false} assume !(0 == start_simulation_~tmp~3#1); {1109#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 109: Hoare triple {1109#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {1109#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 110: Hoare triple {1109#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {1109#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 111: Hoare triple {1109#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {1109#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 112: Hoare triple {1109#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {1109#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 113: Hoare triple {1109#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1109#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 114: Hoare triple {1109#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1109#false} is VALID [2022-02-21 04:24:17,412 INFO L290 TraceCheckUtils]: 115: Hoare triple {1109#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {1109#false} is VALID [2022-02-21 04:24:17,413 INFO L290 TraceCheckUtils]: 116: Hoare triple {1109#false} assume !(0 != start_simulation_~tmp___0~1#1); {1109#false} is VALID [2022-02-21 04:24:17,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:17,413 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:17,414 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2046862436] [2022-02-21 04:24:17,414 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2046862436] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:17,414 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:17,414 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:17,414 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330520087] [2022-02-21 04:24:17,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:17,415 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:17,416 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:17,433 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:17,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:17,437 INFO L87 Difference]: Start difference. First operand has 1101 states, 1100 states have (on average 1.5136363636363637) internal successors, (1665), 1100 states have internal predecessors, (1665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,508 INFO L93 Difference]: Finished difference Result 1100 states and 1636 transitions. [2022-02-21 04:24:18,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:18,510 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,587 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:18,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1100 states and 1636 transitions. [2022-02-21 04:24:18,638 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:18,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1100 states to 1094 states and 1630 transitions. [2022-02-21 04:24:18,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-02-21 04:24:18,697 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-02-21 04:24:18,698 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1630 transitions. [2022-02-21 04:24:18,704 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:18,704 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2022-02-21 04:24:18,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1630 transitions. [2022-02-21 04:24:18,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-02-21 04:24:18,756 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:18,759 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1094 states and 1630 transitions. Second operand has 1094 states, 1094 states have (on average 1.489945155393053) internal successors, (1630), 1093 states have internal predecessors, (1630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,761 INFO L74 IsIncluded]: Start isIncluded. First operand 1094 states and 1630 transitions. Second operand has 1094 states, 1094 states have (on average 1.489945155393053) internal successors, (1630), 1093 states have internal predecessors, (1630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,765 INFO L87 Difference]: Start difference. First operand 1094 states and 1630 transitions. Second operand has 1094 states, 1094 states have (on average 1.489945155393053) internal successors, (1630), 1093 states have internal predecessors, (1630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,808 INFO L93 Difference]: Finished difference Result 1094 states and 1630 transitions. [2022-02-21 04:24:18,809 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1630 transitions. [2022-02-21 04:24:18,816 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:18,816 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:18,818 INFO L74 IsIncluded]: Start isIncluded. First operand has 1094 states, 1094 states have (on average 1.489945155393053) internal successors, (1630), 1093 states have internal predecessors, (1630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1630 transitions. [2022-02-21 04:24:18,819 INFO L87 Difference]: Start difference. First operand has 1094 states, 1094 states have (on average 1.489945155393053) internal successors, (1630), 1093 states have internal predecessors, (1630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1630 transitions. [2022-02-21 04:24:18,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:18,850 INFO L93 Difference]: Finished difference Result 1094 states and 1630 transitions. [2022-02-21 04:24:18,850 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1630 transitions. [2022-02-21 04:24:18,852 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:18,852 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:18,852 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:18,852 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:18,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.489945155393053) internal successors, (1630), 1093 states have internal predecessors, (1630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:18,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1630 transitions. [2022-02-21 04:24:18,885 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2022-02-21 04:24:18,885 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1630 transitions. [2022-02-21 04:24:18,885 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:18,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1630 transitions. [2022-02-21 04:24:18,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:18,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:18,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:18,891 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:18,891 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:18,891 INFO L791 eck$LassoCheckResult]: Stem: 3047#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 3048#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2648#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2649#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3195#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3196#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3178#L646-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2998#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2999#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2815#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2816#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3255#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3162#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2870#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2654#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2655#L922 assume !(0 == ~M_E~0); 3300#L922-2 assume !(0 == ~T1_E~0); 3301#L927-1 assume !(0 == ~T2_E~0); 3055#L932-1 assume !(0 == ~T3_E~0); 2940#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2941#L942-1 assume !(0 == ~T5_E~0); 2997#L947-1 assume !(0 == ~T6_E~0); 3059#L952-1 assume !(0 == ~T7_E~0); 3060#L957-1 assume !(0 == ~T8_E~0); 3120#L962-1 assume !(0 == ~T9_E~0); 2916#L967-1 assume !(0 == ~E_1~0); 2917#L972-1 assume !(0 == ~E_2~0); 3183#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3184#L982-1 assume !(0 == ~E_4~0); 2424#L987-1 assume !(0 == ~E_5~0); 2425#L992-1 assume !(0 == ~E_6~0); 2433#L997-1 assume !(0 == ~E_7~0); 2847#L1002-1 assume !(0 == ~E_8~0); 2834#L1007-1 assume !(0 == ~E_9~0); 2222#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2223#L443 assume !(1 == ~m_pc~0); 3075#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3066#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3067#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2588#L1140 assume !(0 != activate_threads_~tmp~1#1); 2337#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2338#L462 assume 1 == ~t1_pc~0; 2966#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2933#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2308#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2309#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2796#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2797#L481 assume !(1 == ~t2_pc~0); 2583#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2582#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2937#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2676#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2677#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2769#L500 assume 1 == ~t3_pc~0; 2979#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2980#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3170#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3171#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2224#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2225#L519 assume 1 == ~t4_pc~0; 2523#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2524#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2768#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2628#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2629#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2391#L538 assume !(1 == ~t5_pc~0); 2392#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2298#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2299#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2567#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2568#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3105#L557 assume 1 == ~t6_pc~0; 2904#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2605#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2505#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2506#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2630#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3283#L576 assume !(1 == ~t7_pc~0); 2592#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2593#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2837#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2838#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3154#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2713#L595 assume 1 == ~t8_pc~0; 2714#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3172#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3173#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3022#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3023#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2516#L614 assume !(1 == ~t9_pc~0); 2517#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2416#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2417#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2596#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2678#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2679#L1025 assume !(1 == ~M_E~0); 2925#L1025-2 assume !(1 == ~T1_E~0); 2978#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3100#L1035-1 assume !(1 == ~T3_E~0); 2672#L1040-1 assume !(1 == ~T4_E~0); 2673#L1045-1 assume !(1 == ~T5_E~0); 2578#L1050-1 assume !(1 == ~T6_E~0); 2579#L1055-1 assume !(1 == ~T7_E~0); 2400#L1060-1 assume !(1 == ~T8_E~0); 2401#L1065-1 assume !(1 == ~T9_E~0); 2464#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3061#L1075-1 assume !(1 == ~E_2~0); 3062#L1080-1 assume !(1 == ~E_3~0); 3050#L1085-1 assume !(1 == ~E_4~0); 3051#L1090-1 assume !(1 == ~E_5~0); 3250#L1095-1 assume !(1 == ~E_6~0); 3084#L1100-1 assume !(1 == ~E_7~0); 3085#L1105-1 assume !(1 == ~E_8~0); 2373#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 2374#L1115-1 assume { :end_inline_reset_delta_events } true; 2535#L1396-2 [2022-02-21 04:24:18,892 INFO L793 eck$LassoCheckResult]: Loop: 2535#L1396-2 assume !false; 2618#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2647#L897 assume !false; 3290#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3197#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2245#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2246#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3245#L766 assume !(0 != eval_~tmp~0#1); 3231#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2315#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2316#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2830#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2559#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2560#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2738#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2365#L942-3 assume !(0 == ~T5_E~0); 2366#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2739#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2740#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3241#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3132#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3133#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3053#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3054#L982-3 assume !(0 == ~E_4~0); 3302#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2689#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2690#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2684#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2685#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2402#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2403#L443-30 assume 1 == ~m_pc~0; 2436#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2437#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2720#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3268#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3187#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2820#L462-30 assume 1 == ~t1_pc~0; 2664#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2666#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3168#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3169#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3209#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2807#L481-30 assume !(1 == ~t2_pc~0); 2528#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2527#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2580#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2493#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2494#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2774#L500-30 assume 1 == ~t3_pc~0; 2531#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2532#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2594#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2595#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2757#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2758#L519-30 assume 1 == ~t4_pc~0; 3093#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2909#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2271#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2272#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2921#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3034#L538-30 assume 1 == ~t5_pc~0; 2412#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2413#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2711#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2712#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2489#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2490#L557-30 assume 1 == ~t6_pc~0; 2210#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2211#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2888#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2948#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2514#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2515#L576-30 assume 1 == ~t7_pc~0; 3027#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2297#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2882#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3248#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2674#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2637#L595-30 assume !(1 == ~t8_pc~0); 2638#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2569#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2306#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2307#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3249#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3285#L614-30 assume !(1 == ~t9_pc~0); 2576#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2575#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2710#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2404#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2405#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3013#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2798#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2799#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2983#L1035-3 assume !(1 == ~T3_E~0); 3258#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3298#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3254#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3167#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2304#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2305#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3189#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3035#L1075-3 assume !(1 == ~E_2~0); 3036#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3259#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3180#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3181#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3200#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3201#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2452#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2453#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3212#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2321#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2310#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2311#L1415 assume !(0 == start_simulation_~tmp~3#1); 2912#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2913#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2361#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2923#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 3102#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3303#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2971#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2534#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2535#L1396-2 [2022-02-21 04:24:18,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:18,893 INFO L85 PathProgramCache]: Analyzing trace with hash -1247434205, now seen corresponding path program 1 times [2022-02-21 04:24:18,893 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:18,893 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138807131] [2022-02-21 04:24:18,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:18,893 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:18,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:18,947 INFO L290 TraceCheckUtils]: 0: Hoare triple {5495#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {5495#true} is VALID [2022-02-21 04:24:18,948 INFO L290 TraceCheckUtils]: 1: Hoare triple {5495#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {5497#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:18,948 INFO L290 TraceCheckUtils]: 2: Hoare triple {5497#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {5497#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:18,948 INFO L290 TraceCheckUtils]: 3: Hoare triple {5497#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {5497#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:18,949 INFO L290 TraceCheckUtils]: 4: Hoare triple {5497#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {5497#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:18,949 INFO L290 TraceCheckUtils]: 5: Hoare triple {5497#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {5497#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:18,952 INFO L290 TraceCheckUtils]: 6: Hoare triple {5497#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {5496#false} is VALID [2022-02-21 04:24:18,952 INFO L290 TraceCheckUtils]: 7: Hoare triple {5496#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {5496#false} is VALID [2022-02-21 04:24:18,952 INFO L290 TraceCheckUtils]: 8: Hoare triple {5496#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {5496#false} is VALID [2022-02-21 04:24:18,953 INFO L290 TraceCheckUtils]: 9: Hoare triple {5496#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {5496#false} is VALID [2022-02-21 04:24:18,956 INFO L290 TraceCheckUtils]: 10: Hoare triple {5496#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {5496#false} is VALID [2022-02-21 04:24:18,957 INFO L290 TraceCheckUtils]: 11: Hoare triple {5496#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {5496#false} is VALID [2022-02-21 04:24:18,957 INFO L290 TraceCheckUtils]: 12: Hoare triple {5496#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {5496#false} is VALID [2022-02-21 04:24:18,957 INFO L290 TraceCheckUtils]: 13: Hoare triple {5496#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {5496#false} is VALID [2022-02-21 04:24:18,959 INFO L290 TraceCheckUtils]: 14: Hoare triple {5496#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {5496#false} is VALID [2022-02-21 04:24:18,959 INFO L290 TraceCheckUtils]: 15: Hoare triple {5496#false} assume !(0 == ~M_E~0); {5496#false} is VALID [2022-02-21 04:24:18,961 INFO L290 TraceCheckUtils]: 16: Hoare triple {5496#false} assume !(0 == ~T1_E~0); {5496#false} is VALID [2022-02-21 04:24:18,962 INFO L290 TraceCheckUtils]: 17: Hoare triple {5496#false} assume !(0 == ~T2_E~0); {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 18: Hoare triple {5496#false} assume !(0 == ~T3_E~0); {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 19: Hoare triple {5496#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 20: Hoare triple {5496#false} assume !(0 == ~T5_E~0); {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 21: Hoare triple {5496#false} assume !(0 == ~T6_E~0); {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 22: Hoare triple {5496#false} assume !(0 == ~T7_E~0); {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 23: Hoare triple {5496#false} assume !(0 == ~T8_E~0); {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 24: Hoare triple {5496#false} assume !(0 == ~T9_E~0); {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 25: Hoare triple {5496#false} assume !(0 == ~E_1~0); {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 26: Hoare triple {5496#false} assume !(0 == ~E_2~0); {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 27: Hoare triple {5496#false} assume 0 == ~E_3~0;~E_3~0 := 1; {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 28: Hoare triple {5496#false} assume !(0 == ~E_4~0); {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 29: Hoare triple {5496#false} assume !(0 == ~E_5~0); {5496#false} is VALID [2022-02-21 04:24:18,964 INFO L290 TraceCheckUtils]: 30: Hoare triple {5496#false} assume !(0 == ~E_6~0); {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 31: Hoare triple {5496#false} assume !(0 == ~E_7~0); {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 32: Hoare triple {5496#false} assume !(0 == ~E_8~0); {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 33: Hoare triple {5496#false} assume !(0 == ~E_9~0); {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 34: Hoare triple {5496#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 35: Hoare triple {5496#false} assume !(1 == ~m_pc~0); {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 36: Hoare triple {5496#false} is_master_triggered_~__retres1~0#1 := 0; {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 37: Hoare triple {5496#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 38: Hoare triple {5496#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 39: Hoare triple {5496#false} assume !(0 != activate_threads_~tmp~1#1); {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 40: Hoare triple {5496#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 41: Hoare triple {5496#false} assume 1 == ~t1_pc~0; {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 42: Hoare triple {5496#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {5496#false} is VALID [2022-02-21 04:24:18,965 INFO L290 TraceCheckUtils]: 43: Hoare triple {5496#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 44: Hoare triple {5496#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 45: Hoare triple {5496#false} assume !(0 != activate_threads_~tmp___0~0#1); {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 46: Hoare triple {5496#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 47: Hoare triple {5496#false} assume !(1 == ~t2_pc~0); {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 48: Hoare triple {5496#false} is_transmit2_triggered_~__retres1~2#1 := 0; {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 49: Hoare triple {5496#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 50: Hoare triple {5496#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 51: Hoare triple {5496#false} assume !(0 != activate_threads_~tmp___1~0#1); {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 52: Hoare triple {5496#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 53: Hoare triple {5496#false} assume 1 == ~t3_pc~0; {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 54: Hoare triple {5496#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 55: Hoare triple {5496#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 56: Hoare triple {5496#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 57: Hoare triple {5496#false} assume !(0 != activate_threads_~tmp___2~0#1); {5496#false} is VALID [2022-02-21 04:24:18,966 INFO L290 TraceCheckUtils]: 58: Hoare triple {5496#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5496#false} is VALID [2022-02-21 04:24:18,967 INFO L290 TraceCheckUtils]: 59: Hoare triple {5496#false} assume 1 == ~t4_pc~0; {5496#false} is VALID [2022-02-21 04:24:18,967 INFO L290 TraceCheckUtils]: 60: Hoare triple {5496#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {5496#false} is VALID [2022-02-21 04:24:18,967 INFO L290 TraceCheckUtils]: 61: Hoare triple {5496#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5496#false} is VALID [2022-02-21 04:24:18,967 INFO L290 TraceCheckUtils]: 62: Hoare triple {5496#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {5496#false} is VALID [2022-02-21 04:24:18,967 INFO L290 TraceCheckUtils]: 63: Hoare triple {5496#false} assume !(0 != activate_threads_~tmp___3~0#1); {5496#false} is VALID [2022-02-21 04:24:18,967 INFO L290 TraceCheckUtils]: 64: Hoare triple {5496#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {5496#false} is VALID [2022-02-21 04:24:18,967 INFO L290 TraceCheckUtils]: 65: Hoare triple {5496#false} assume !(1 == ~t5_pc~0); {5496#false} is VALID [2022-02-21 04:24:18,967 INFO L290 TraceCheckUtils]: 66: Hoare triple {5496#false} is_transmit5_triggered_~__retres1~5#1 := 0; {5496#false} is VALID [2022-02-21 04:24:18,967 INFO L290 TraceCheckUtils]: 67: Hoare triple {5496#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {5496#false} is VALID [2022-02-21 04:24:18,967 INFO L290 TraceCheckUtils]: 68: Hoare triple {5496#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {5496#false} is VALID [2022-02-21 04:24:18,968 INFO L290 TraceCheckUtils]: 69: Hoare triple {5496#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {5496#false} is VALID [2022-02-21 04:24:18,968 INFO L290 TraceCheckUtils]: 70: Hoare triple {5496#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {5496#false} is VALID [2022-02-21 04:24:18,968 INFO L290 TraceCheckUtils]: 71: Hoare triple {5496#false} assume 1 == ~t6_pc~0; {5496#false} is VALID [2022-02-21 04:24:18,968 INFO L290 TraceCheckUtils]: 72: Hoare triple {5496#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {5496#false} is VALID [2022-02-21 04:24:18,968 INFO L290 TraceCheckUtils]: 73: Hoare triple {5496#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {5496#false} is VALID [2022-02-21 04:24:18,968 INFO L290 TraceCheckUtils]: 74: Hoare triple {5496#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {5496#false} is VALID [2022-02-21 04:24:18,968 INFO L290 TraceCheckUtils]: 75: Hoare triple {5496#false} assume !(0 != activate_threads_~tmp___5~0#1); {5496#false} is VALID [2022-02-21 04:24:18,968 INFO L290 TraceCheckUtils]: 76: Hoare triple {5496#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {5496#false} is VALID [2022-02-21 04:24:18,969 INFO L290 TraceCheckUtils]: 77: Hoare triple {5496#false} assume !(1 == ~t7_pc~0); {5496#false} is VALID [2022-02-21 04:24:18,969 INFO L290 TraceCheckUtils]: 78: Hoare triple {5496#false} is_transmit7_triggered_~__retres1~7#1 := 0; {5496#false} is VALID [2022-02-21 04:24:18,969 INFO L290 TraceCheckUtils]: 79: Hoare triple {5496#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {5496#false} is VALID [2022-02-21 04:24:18,969 INFO L290 TraceCheckUtils]: 80: Hoare triple {5496#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {5496#false} is VALID [2022-02-21 04:24:18,969 INFO L290 TraceCheckUtils]: 81: Hoare triple {5496#false} assume !(0 != activate_threads_~tmp___6~0#1); {5496#false} is VALID [2022-02-21 04:24:18,969 INFO L290 TraceCheckUtils]: 82: Hoare triple {5496#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {5496#false} is VALID [2022-02-21 04:24:18,969 INFO L290 TraceCheckUtils]: 83: Hoare triple {5496#false} assume 1 == ~t8_pc~0; {5496#false} is VALID [2022-02-21 04:24:18,969 INFO L290 TraceCheckUtils]: 84: Hoare triple {5496#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {5496#false} is VALID [2022-02-21 04:24:18,970 INFO L290 TraceCheckUtils]: 85: Hoare triple {5496#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {5496#false} is VALID [2022-02-21 04:24:18,970 INFO L290 TraceCheckUtils]: 86: Hoare triple {5496#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {5496#false} is VALID [2022-02-21 04:24:18,970 INFO L290 TraceCheckUtils]: 87: Hoare triple {5496#false} assume !(0 != activate_threads_~tmp___7~0#1); {5496#false} is VALID [2022-02-21 04:24:18,970 INFO L290 TraceCheckUtils]: 88: Hoare triple {5496#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {5496#false} is VALID [2022-02-21 04:24:18,970 INFO L290 TraceCheckUtils]: 89: Hoare triple {5496#false} assume !(1 == ~t9_pc~0); {5496#false} is VALID [2022-02-21 04:24:18,970 INFO L290 TraceCheckUtils]: 90: Hoare triple {5496#false} is_transmit9_triggered_~__retres1~9#1 := 0; {5496#false} is VALID [2022-02-21 04:24:18,970 INFO L290 TraceCheckUtils]: 91: Hoare triple {5496#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {5496#false} is VALID [2022-02-21 04:24:18,970 INFO L290 TraceCheckUtils]: 92: Hoare triple {5496#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {5496#false} is VALID [2022-02-21 04:24:18,971 INFO L290 TraceCheckUtils]: 93: Hoare triple {5496#false} assume !(0 != activate_threads_~tmp___8~0#1); {5496#false} is VALID [2022-02-21 04:24:18,971 INFO L290 TraceCheckUtils]: 94: Hoare triple {5496#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5496#false} is VALID [2022-02-21 04:24:18,971 INFO L290 TraceCheckUtils]: 95: Hoare triple {5496#false} assume !(1 == ~M_E~0); {5496#false} is VALID [2022-02-21 04:24:18,972 INFO L290 TraceCheckUtils]: 96: Hoare triple {5496#false} assume !(1 == ~T1_E~0); {5496#false} is VALID [2022-02-21 04:24:18,973 INFO L290 TraceCheckUtils]: 97: Hoare triple {5496#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {5496#false} is VALID [2022-02-21 04:24:18,973 INFO L290 TraceCheckUtils]: 98: Hoare triple {5496#false} assume !(1 == ~T3_E~0); {5496#false} is VALID [2022-02-21 04:24:18,973 INFO L290 TraceCheckUtils]: 99: Hoare triple {5496#false} assume !(1 == ~T4_E~0); {5496#false} is VALID [2022-02-21 04:24:18,973 INFO L290 TraceCheckUtils]: 100: Hoare triple {5496#false} assume !(1 == ~T5_E~0); {5496#false} is VALID [2022-02-21 04:24:18,973 INFO L290 TraceCheckUtils]: 101: Hoare triple {5496#false} assume !(1 == ~T6_E~0); {5496#false} is VALID [2022-02-21 04:24:18,973 INFO L290 TraceCheckUtils]: 102: Hoare triple {5496#false} assume !(1 == ~T7_E~0); {5496#false} is VALID [2022-02-21 04:24:18,973 INFO L290 TraceCheckUtils]: 103: Hoare triple {5496#false} assume !(1 == ~T8_E~0); {5496#false} is VALID [2022-02-21 04:24:18,974 INFO L290 TraceCheckUtils]: 104: Hoare triple {5496#false} assume !(1 == ~T9_E~0); {5496#false} is VALID [2022-02-21 04:24:18,974 INFO L290 TraceCheckUtils]: 105: Hoare triple {5496#false} assume 1 == ~E_1~0;~E_1~0 := 2; {5496#false} is VALID [2022-02-21 04:24:18,974 INFO L290 TraceCheckUtils]: 106: Hoare triple {5496#false} assume !(1 == ~E_2~0); {5496#false} is VALID [2022-02-21 04:24:18,974 INFO L290 TraceCheckUtils]: 107: Hoare triple {5496#false} assume !(1 == ~E_3~0); {5496#false} is VALID [2022-02-21 04:24:18,974 INFO L290 TraceCheckUtils]: 108: Hoare triple {5496#false} assume !(1 == ~E_4~0); {5496#false} is VALID [2022-02-21 04:24:18,974 INFO L290 TraceCheckUtils]: 109: Hoare triple {5496#false} assume !(1 == ~E_5~0); {5496#false} is VALID [2022-02-21 04:24:18,974 INFO L290 TraceCheckUtils]: 110: Hoare triple {5496#false} assume !(1 == ~E_6~0); {5496#false} is VALID [2022-02-21 04:24:18,974 INFO L290 TraceCheckUtils]: 111: Hoare triple {5496#false} assume !(1 == ~E_7~0); {5496#false} is VALID [2022-02-21 04:24:18,975 INFO L290 TraceCheckUtils]: 112: Hoare triple {5496#false} assume !(1 == ~E_8~0); {5496#false} is VALID [2022-02-21 04:24:18,975 INFO L290 TraceCheckUtils]: 113: Hoare triple {5496#false} assume 1 == ~E_9~0;~E_9~0 := 2; {5496#false} is VALID [2022-02-21 04:24:18,975 INFO L290 TraceCheckUtils]: 114: Hoare triple {5496#false} assume { :end_inline_reset_delta_events } true; {5496#false} is VALID [2022-02-21 04:24:18,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:18,977 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:18,977 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2138807131] [2022-02-21 04:24:18,977 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2138807131] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:18,977 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:18,978 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:18,978 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [494057704] [2022-02-21 04:24:18,978 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:18,978 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:18,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:18,980 INFO L85 PathProgramCache]: Analyzing trace with hash -1392985774, now seen corresponding path program 1 times [2022-02-21 04:24:18,980 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:18,980 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304501957] [2022-02-21 04:24:18,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:18,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:19,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:19,081 INFO L290 TraceCheckUtils]: 0: Hoare triple {5498#true} assume !false; {5498#true} is VALID [2022-02-21 04:24:19,081 INFO L290 TraceCheckUtils]: 1: Hoare triple {5498#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {5498#true} is VALID [2022-02-21 04:24:19,081 INFO L290 TraceCheckUtils]: 2: Hoare triple {5498#true} assume !false; {5498#true} is VALID [2022-02-21 04:24:19,081 INFO L290 TraceCheckUtils]: 3: Hoare triple {5498#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {5498#true} is VALID [2022-02-21 04:24:19,081 INFO L290 TraceCheckUtils]: 4: Hoare triple {5498#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {5498#true} is VALID [2022-02-21 04:24:19,082 INFO L290 TraceCheckUtils]: 5: Hoare triple {5498#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {5498#true} is VALID [2022-02-21 04:24:19,082 INFO L290 TraceCheckUtils]: 6: Hoare triple {5498#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {5498#true} is VALID [2022-02-21 04:24:19,082 INFO L290 TraceCheckUtils]: 7: Hoare triple {5498#true} assume !(0 != eval_~tmp~0#1); {5498#true} is VALID [2022-02-21 04:24:19,082 INFO L290 TraceCheckUtils]: 8: Hoare triple {5498#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {5498#true} is VALID [2022-02-21 04:24:19,082 INFO L290 TraceCheckUtils]: 9: Hoare triple {5498#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {5498#true} is VALID [2022-02-21 04:24:19,082 INFO L290 TraceCheckUtils]: 10: Hoare triple {5498#true} assume 0 == ~M_E~0;~M_E~0 := 1; {5498#true} is VALID [2022-02-21 04:24:19,082 INFO L290 TraceCheckUtils]: 11: Hoare triple {5498#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {5498#true} is VALID [2022-02-21 04:24:19,082 INFO L290 TraceCheckUtils]: 12: Hoare triple {5498#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {5498#true} is VALID [2022-02-21 04:24:19,091 INFO L290 TraceCheckUtils]: 13: Hoare triple {5498#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,092 INFO L290 TraceCheckUtils]: 14: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,092 INFO L290 TraceCheckUtils]: 15: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T5_E~0); {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,092 INFO L290 TraceCheckUtils]: 16: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,093 INFO L290 TraceCheckUtils]: 17: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,093 INFO L290 TraceCheckUtils]: 18: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,093 INFO L290 TraceCheckUtils]: 19: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,094 INFO L290 TraceCheckUtils]: 20: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,094 INFO L290 TraceCheckUtils]: 21: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,094 INFO L290 TraceCheckUtils]: 22: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,095 INFO L290 TraceCheckUtils]: 23: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_4~0); {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,096 INFO L290 TraceCheckUtils]: 24: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,096 INFO L290 TraceCheckUtils]: 25: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,097 INFO L290 TraceCheckUtils]: 26: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,097 INFO L290 TraceCheckUtils]: 27: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,097 INFO L290 TraceCheckUtils]: 28: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,097 INFO L290 TraceCheckUtils]: 29: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,098 INFO L290 TraceCheckUtils]: 30: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~m_pc~0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,098 INFO L290 TraceCheckUtils]: 31: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,098 INFO L290 TraceCheckUtils]: 32: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,099 INFO L290 TraceCheckUtils]: 33: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,099 INFO L290 TraceCheckUtils]: 34: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,105 INFO L290 TraceCheckUtils]: 35: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,107 INFO L290 TraceCheckUtils]: 36: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t1_pc~0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,107 INFO L290 TraceCheckUtils]: 37: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,108 INFO L290 TraceCheckUtils]: 38: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,108 INFO L290 TraceCheckUtils]: 39: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,108 INFO L290 TraceCheckUtils]: 40: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,108 INFO L290 TraceCheckUtils]: 41: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,109 INFO L290 TraceCheckUtils]: 42: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t2_pc~0); {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,109 INFO L290 TraceCheckUtils]: 43: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,109 INFO L290 TraceCheckUtils]: 44: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,110 INFO L290 TraceCheckUtils]: 45: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,110 INFO L290 TraceCheckUtils]: 46: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,111 INFO L290 TraceCheckUtils]: 47: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,111 INFO L290 TraceCheckUtils]: 48: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t3_pc~0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,111 INFO L290 TraceCheckUtils]: 49: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,111 INFO L290 TraceCheckUtils]: 50: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,112 INFO L290 TraceCheckUtils]: 51: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,112 INFO L290 TraceCheckUtils]: 52: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,112 INFO L290 TraceCheckUtils]: 53: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,113 INFO L290 TraceCheckUtils]: 54: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t4_pc~0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,113 INFO L290 TraceCheckUtils]: 55: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,113 INFO L290 TraceCheckUtils]: 56: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,113 INFO L290 TraceCheckUtils]: 57: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,114 INFO L290 TraceCheckUtils]: 58: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,114 INFO L290 TraceCheckUtils]: 59: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,114 INFO L290 TraceCheckUtils]: 60: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t5_pc~0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,114 INFO L290 TraceCheckUtils]: 61: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,115 INFO L290 TraceCheckUtils]: 62: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,115 INFO L290 TraceCheckUtils]: 63: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,115 INFO L290 TraceCheckUtils]: 64: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,116 INFO L290 TraceCheckUtils]: 65: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,116 INFO L290 TraceCheckUtils]: 66: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t6_pc~0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,116 INFO L290 TraceCheckUtils]: 67: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,116 INFO L290 TraceCheckUtils]: 68: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,117 INFO L290 TraceCheckUtils]: 69: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,117 INFO L290 TraceCheckUtils]: 70: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,117 INFO L290 TraceCheckUtils]: 71: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,117 INFO L290 TraceCheckUtils]: 72: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t7_pc~0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,118 INFO L290 TraceCheckUtils]: 73: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,118 INFO L290 TraceCheckUtils]: 74: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,118 INFO L290 TraceCheckUtils]: 75: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,118 INFO L290 TraceCheckUtils]: 76: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,119 INFO L290 TraceCheckUtils]: 77: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,119 INFO L290 TraceCheckUtils]: 78: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t8_pc~0); {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,119 INFO L290 TraceCheckUtils]: 79: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,120 INFO L290 TraceCheckUtils]: 80: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,120 INFO L290 TraceCheckUtils]: 81: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,120 INFO L290 TraceCheckUtils]: 82: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,120 INFO L290 TraceCheckUtils]: 83: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,121 INFO L290 TraceCheckUtils]: 84: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t9_pc~0); {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,121 INFO L290 TraceCheckUtils]: 85: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,121 INFO L290 TraceCheckUtils]: 86: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,121 INFO L290 TraceCheckUtils]: 87: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,122 INFO L290 TraceCheckUtils]: 88: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,122 INFO L290 TraceCheckUtils]: 89: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,122 INFO L290 TraceCheckUtils]: 90: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,123 INFO L290 TraceCheckUtils]: 91: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,123 INFO L290 TraceCheckUtils]: 92: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {5500#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:19,123 INFO L290 TraceCheckUtils]: 93: Hoare triple {5500#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~T3_E~0); {5499#false} is VALID [2022-02-21 04:24:19,123 INFO L290 TraceCheckUtils]: 94: Hoare triple {5499#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,123 INFO L290 TraceCheckUtils]: 95: Hoare triple {5499#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,124 INFO L290 TraceCheckUtils]: 96: Hoare triple {5499#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,124 INFO L290 TraceCheckUtils]: 97: Hoare triple {5499#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,124 INFO L290 TraceCheckUtils]: 98: Hoare triple {5499#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,124 INFO L290 TraceCheckUtils]: 99: Hoare triple {5499#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,124 INFO L290 TraceCheckUtils]: 100: Hoare triple {5499#false} assume 1 == ~E_1~0;~E_1~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,124 INFO L290 TraceCheckUtils]: 101: Hoare triple {5499#false} assume !(1 == ~E_2~0); {5499#false} is VALID [2022-02-21 04:24:19,124 INFO L290 TraceCheckUtils]: 102: Hoare triple {5499#false} assume 1 == ~E_3~0;~E_3~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,124 INFO L290 TraceCheckUtils]: 103: Hoare triple {5499#false} assume 1 == ~E_4~0;~E_4~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,125 INFO L290 TraceCheckUtils]: 104: Hoare triple {5499#false} assume 1 == ~E_5~0;~E_5~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,125 INFO L290 TraceCheckUtils]: 105: Hoare triple {5499#false} assume 1 == ~E_6~0;~E_6~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,125 INFO L290 TraceCheckUtils]: 106: Hoare triple {5499#false} assume 1 == ~E_7~0;~E_7~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,125 INFO L290 TraceCheckUtils]: 107: Hoare triple {5499#false} assume 1 == ~E_8~0;~E_8~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,125 INFO L290 TraceCheckUtils]: 108: Hoare triple {5499#false} assume 1 == ~E_9~0;~E_9~0 := 2; {5499#false} is VALID [2022-02-21 04:24:19,125 INFO L290 TraceCheckUtils]: 109: Hoare triple {5499#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {5499#false} is VALID [2022-02-21 04:24:19,126 INFO L290 TraceCheckUtils]: 110: Hoare triple {5499#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {5499#false} is VALID [2022-02-21 04:24:19,126 INFO L290 TraceCheckUtils]: 111: Hoare triple {5499#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {5499#false} is VALID [2022-02-21 04:24:19,126 INFO L290 TraceCheckUtils]: 112: Hoare triple {5499#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {5499#false} is VALID [2022-02-21 04:24:19,126 INFO L290 TraceCheckUtils]: 113: Hoare triple {5499#false} assume !(0 == start_simulation_~tmp~3#1); {5499#false} is VALID [2022-02-21 04:24:19,126 INFO L290 TraceCheckUtils]: 114: Hoare triple {5499#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {5499#false} is VALID [2022-02-21 04:24:19,126 INFO L290 TraceCheckUtils]: 115: Hoare triple {5499#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {5499#false} is VALID [2022-02-21 04:24:19,126 INFO L290 TraceCheckUtils]: 116: Hoare triple {5499#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {5499#false} is VALID [2022-02-21 04:24:19,126 INFO L290 TraceCheckUtils]: 117: Hoare triple {5499#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {5499#false} is VALID [2022-02-21 04:24:19,127 INFO L290 TraceCheckUtils]: 118: Hoare triple {5499#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {5499#false} is VALID [2022-02-21 04:24:19,127 INFO L290 TraceCheckUtils]: 119: Hoare triple {5499#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {5499#false} is VALID [2022-02-21 04:24:19,127 INFO L290 TraceCheckUtils]: 120: Hoare triple {5499#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {5499#false} is VALID [2022-02-21 04:24:19,127 INFO L290 TraceCheckUtils]: 121: Hoare triple {5499#false} assume !(0 != start_simulation_~tmp___0~1#1); {5499#false} is VALID [2022-02-21 04:24:19,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:19,129 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:19,130 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1304501957] [2022-02-21 04:24:19,130 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1304501957] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:19,130 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:19,131 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:19,131 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [394147420] [2022-02-21 04:24:19,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:19,131 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:19,131 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:19,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:19,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:19,132 INFO L87 Difference]: Start difference. First operand 1094 states and 1630 transitions. cyclomatic complexity: 537 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:19,949 INFO L93 Difference]: Finished difference Result 1094 states and 1629 transitions. [2022-02-21 04:24:19,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:19,949 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,010 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:20,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1629 transitions. [2022-02-21 04:24:20,042 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:20,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1629 transitions. [2022-02-21 04:24:20,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-02-21 04:24:20,073 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-02-21 04:24:20,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1629 transitions. [2022-02-21 04:24:20,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:20,074 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2022-02-21 04:24:20,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1629 transitions. [2022-02-21 04:24:20,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-02-21 04:24:20,089 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:20,092 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1094 states and 1629 transitions. Second operand has 1094 states, 1094 states have (on average 1.4890310786106034) internal successors, (1629), 1093 states have internal predecessors, (1629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,093 INFO L74 IsIncluded]: Start isIncluded. First operand 1094 states and 1629 transitions. Second operand has 1094 states, 1094 states have (on average 1.4890310786106034) internal successors, (1629), 1093 states have internal predecessors, (1629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,095 INFO L87 Difference]: Start difference. First operand 1094 states and 1629 transitions. Second operand has 1094 states, 1094 states have (on average 1.4890310786106034) internal successors, (1629), 1093 states have internal predecessors, (1629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,126 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,126 INFO L93 Difference]: Finished difference Result 1094 states and 1629 transitions. [2022-02-21 04:24:20,126 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1629 transitions. [2022-02-21 04:24:20,128 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:20,128 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:20,131 INFO L74 IsIncluded]: Start isIncluded. First operand has 1094 states, 1094 states have (on average 1.4890310786106034) internal successors, (1629), 1093 states have internal predecessors, (1629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1629 transitions. [2022-02-21 04:24:20,132 INFO L87 Difference]: Start difference. First operand has 1094 states, 1094 states have (on average 1.4890310786106034) internal successors, (1629), 1093 states have internal predecessors, (1629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1629 transitions. [2022-02-21 04:24:20,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:20,163 INFO L93 Difference]: Finished difference Result 1094 states and 1629 transitions. [2022-02-21 04:24:20,163 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1629 transitions. [2022-02-21 04:24:20,165 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:20,165 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:20,165 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:20,165 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:20,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4890310786106034) internal successors, (1629), 1093 states have internal predecessors, (1629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:20,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1629 transitions. [2022-02-21 04:24:20,195 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2022-02-21 04:24:20,195 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1629 transitions. [2022-02-21 04:24:20,196 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:20,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1629 transitions. [2022-02-21 04:24:20,199 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:20,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:20,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:20,200 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:20,201 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:20,201 INFO L791 eck$LassoCheckResult]: Stem: 7432#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 7433#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7033#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7034#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7580#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 7581#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7563#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7383#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7384#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7200#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7201#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7641#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7547#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7255#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7039#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7040#L922 assume !(0 == ~M_E~0); 7685#L922-2 assume !(0 == ~T1_E~0); 7686#L927-1 assume !(0 == ~T2_E~0); 7440#L932-1 assume !(0 == ~T3_E~0); 7325#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7326#L942-1 assume !(0 == ~T5_E~0); 7382#L947-1 assume !(0 == ~T6_E~0); 7444#L952-1 assume !(0 == ~T7_E~0); 7445#L957-1 assume !(0 == ~T8_E~0); 7507#L962-1 assume !(0 == ~T9_E~0); 7301#L967-1 assume !(0 == ~E_1~0); 7302#L972-1 assume !(0 == ~E_2~0); 7568#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 7569#L982-1 assume !(0 == ~E_4~0); 6809#L987-1 assume !(0 == ~E_5~0); 6810#L992-1 assume !(0 == ~E_6~0); 6818#L997-1 assume !(0 == ~E_7~0); 7234#L1002-1 assume !(0 == ~E_8~0); 7219#L1007-1 assume !(0 == ~E_9~0); 6607#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6608#L443 assume !(1 == ~m_pc~0); 7460#L443-2 is_master_triggered_~__retres1~0#1 := 0; 7451#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7452#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6973#L1140 assume !(0 != activate_threads_~tmp~1#1); 6722#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6723#L462 assume 1 == ~t1_pc~0; 7351#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7319#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6693#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6694#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 7181#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7182#L481 assume !(1 == ~t2_pc~0); 6968#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6967#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7322#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7061#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 7062#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7156#L500 assume 1 == ~t3_pc~0; 7364#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7365#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7555#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7556#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 6609#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6610#L519 assume 1 == ~t4_pc~0; 6908#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6909#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7153#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7015#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 7016#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6776#L538 assume !(1 == ~t5_pc~0); 6777#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6683#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6684#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6952#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6953#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7492#L557 assume 1 == ~t6_pc~0; 7289#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6990#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6892#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6893#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 7017#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7668#L576 assume !(1 == ~t7_pc~0); 6977#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6978#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7222#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7223#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 7539#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7098#L595 assume 1 == ~t8_pc~0; 7099#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7557#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7558#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7407#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 7408#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6901#L614 assume !(1 == ~t9_pc~0); 6902#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6801#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6802#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6981#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 7063#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7064#L1025 assume !(1 == ~M_E~0); 7310#L1025-2 assume !(1 == ~T1_E~0); 7363#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7485#L1035-1 assume !(1 == ~T3_E~0); 7058#L1040-1 assume !(1 == ~T4_E~0); 7059#L1045-1 assume !(1 == ~T5_E~0); 6963#L1050-1 assume !(1 == ~T6_E~0); 6964#L1055-1 assume !(1 == ~T7_E~0); 6785#L1060-1 assume !(1 == ~T8_E~0); 6786#L1065-1 assume !(1 == ~T9_E~0); 6849#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7446#L1075-1 assume !(1 == ~E_2~0); 7447#L1080-1 assume !(1 == ~E_3~0); 7435#L1085-1 assume !(1 == ~E_4~0); 7436#L1090-1 assume !(1 == ~E_5~0); 7635#L1095-1 assume !(1 == ~E_6~0); 7469#L1100-1 assume !(1 == ~E_7~0); 7470#L1105-1 assume !(1 == ~E_8~0); 6758#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 6759#L1115-1 assume { :end_inline_reset_delta_events } true; 6920#L1396-2 [2022-02-21 04:24:20,201 INFO L793 eck$LassoCheckResult]: Loop: 6920#L1396-2 assume !false; 7003#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7032#L897 assume !false; 7675#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7582#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6632#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6633#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7630#L766 assume !(0 != eval_~tmp~0#1); 7616#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6700#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6701#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7217#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6944#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6945#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7123#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6750#L942-3 assume !(0 == ~T5_E~0); 6751#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7124#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7125#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7626#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7517#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7518#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7438#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7439#L982-3 assume !(0 == ~E_4~0); 7687#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7074#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7075#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7072#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7073#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6787#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6788#L443-30 assume 1 == ~m_pc~0; 6821#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6822#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7105#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7653#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7572#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7205#L462-30 assume 1 == ~t1_pc~0; 7050#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7052#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7553#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7554#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7594#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7192#L481-30 assume !(1 == ~t2_pc~0); 6913#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 6912#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6965#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6881#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6882#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7159#L500-30 assume 1 == ~t3_pc~0; 6916#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6917#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6979#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6980#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7142#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7143#L519-30 assume !(1 == ~t4_pc~0); 7317#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 7294#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6656#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6657#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7306#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7419#L538-30 assume 1 == ~t5_pc~0; 6797#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6798#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7096#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7097#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6874#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6875#L557-30 assume 1 == ~t6_pc~0; 6595#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6596#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7273#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7327#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 6899#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6900#L576-30 assume 1 == ~t7_pc~0; 7412#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6680#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7266#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7633#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7057#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7022#L595-30 assume 1 == ~t8_pc~0; 7024#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6956#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6691#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6692#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7634#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7670#L614-30 assume !(1 == ~t9_pc~0); 6961#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 6960#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7095#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6789#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6790#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7398#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7183#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7184#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7368#L1035-3 assume !(1 == ~T3_E~0); 7643#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7683#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7639#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7552#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6689#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6690#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7574#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7420#L1075-3 assume !(1 == ~E_2~0); 7421#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7644#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7565#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7566#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7585#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7586#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6837#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6838#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7598#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6706#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6695#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 6696#L1415 assume !(0 == start_simulation_~tmp~3#1); 7298#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7299#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6746#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 7308#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 7487#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7688#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7358#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6919#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 6920#L1396-2 [2022-02-21 04:24:20,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:20,202 INFO L85 PathProgramCache]: Analyzing trace with hash -208849631, now seen corresponding path program 1 times [2022-02-21 04:24:20,202 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:20,202 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276390339] [2022-02-21 04:24:20,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:20,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:20,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:20,243 INFO L290 TraceCheckUtils]: 0: Hoare triple {9880#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {9880#true} is VALID [2022-02-21 04:24:20,259 INFO L290 TraceCheckUtils]: 1: Hoare triple {9880#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {9882#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:20,260 INFO L290 TraceCheckUtils]: 2: Hoare triple {9882#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {9882#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:20,260 INFO L290 TraceCheckUtils]: 3: Hoare triple {9882#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {9882#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:20,260 INFO L290 TraceCheckUtils]: 4: Hoare triple {9882#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {9882#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:20,261 INFO L290 TraceCheckUtils]: 5: Hoare triple {9882#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {9882#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:20,261 INFO L290 TraceCheckUtils]: 6: Hoare triple {9882#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {9882#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:20,261 INFO L290 TraceCheckUtils]: 7: Hoare triple {9882#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {9881#false} is VALID [2022-02-21 04:24:20,261 INFO L290 TraceCheckUtils]: 8: Hoare triple {9881#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {9881#false} is VALID [2022-02-21 04:24:20,261 INFO L290 TraceCheckUtils]: 9: Hoare triple {9881#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {9881#false} is VALID [2022-02-21 04:24:20,262 INFO L290 TraceCheckUtils]: 10: Hoare triple {9881#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {9881#false} is VALID [2022-02-21 04:24:20,262 INFO L290 TraceCheckUtils]: 11: Hoare triple {9881#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {9881#false} is VALID [2022-02-21 04:24:20,262 INFO L290 TraceCheckUtils]: 12: Hoare triple {9881#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {9881#false} is VALID [2022-02-21 04:24:20,262 INFO L290 TraceCheckUtils]: 13: Hoare triple {9881#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {9881#false} is VALID [2022-02-21 04:24:20,263 INFO L290 TraceCheckUtils]: 14: Hoare triple {9881#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {9881#false} is VALID [2022-02-21 04:24:20,263 INFO L290 TraceCheckUtils]: 15: Hoare triple {9881#false} assume !(0 == ~M_E~0); {9881#false} is VALID [2022-02-21 04:24:20,263 INFO L290 TraceCheckUtils]: 16: Hoare triple {9881#false} assume !(0 == ~T1_E~0); {9881#false} is VALID [2022-02-21 04:24:20,263 INFO L290 TraceCheckUtils]: 17: Hoare triple {9881#false} assume !(0 == ~T2_E~0); {9881#false} is VALID [2022-02-21 04:24:20,263 INFO L290 TraceCheckUtils]: 18: Hoare triple {9881#false} assume !(0 == ~T3_E~0); {9881#false} is VALID [2022-02-21 04:24:20,264 INFO L290 TraceCheckUtils]: 19: Hoare triple {9881#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {9881#false} is VALID [2022-02-21 04:24:20,264 INFO L290 TraceCheckUtils]: 20: Hoare triple {9881#false} assume !(0 == ~T5_E~0); {9881#false} is VALID [2022-02-21 04:24:20,264 INFO L290 TraceCheckUtils]: 21: Hoare triple {9881#false} assume !(0 == ~T6_E~0); {9881#false} is VALID [2022-02-21 04:24:20,264 INFO L290 TraceCheckUtils]: 22: Hoare triple {9881#false} assume !(0 == ~T7_E~0); {9881#false} is VALID [2022-02-21 04:24:20,264 INFO L290 TraceCheckUtils]: 23: Hoare triple {9881#false} assume !(0 == ~T8_E~0); {9881#false} is VALID [2022-02-21 04:24:20,264 INFO L290 TraceCheckUtils]: 24: Hoare triple {9881#false} assume !(0 == ~T9_E~0); {9881#false} is VALID [2022-02-21 04:24:20,264 INFO L290 TraceCheckUtils]: 25: Hoare triple {9881#false} assume !(0 == ~E_1~0); {9881#false} is VALID [2022-02-21 04:24:20,264 INFO L290 TraceCheckUtils]: 26: Hoare triple {9881#false} assume !(0 == ~E_2~0); {9881#false} is VALID [2022-02-21 04:24:20,264 INFO L290 TraceCheckUtils]: 27: Hoare triple {9881#false} assume 0 == ~E_3~0;~E_3~0 := 1; {9881#false} is VALID [2022-02-21 04:24:20,265 INFO L290 TraceCheckUtils]: 28: Hoare triple {9881#false} assume !(0 == ~E_4~0); {9881#false} is VALID [2022-02-21 04:24:20,265 INFO L290 TraceCheckUtils]: 29: Hoare triple {9881#false} assume !(0 == ~E_5~0); {9881#false} is VALID [2022-02-21 04:24:20,265 INFO L290 TraceCheckUtils]: 30: Hoare triple {9881#false} assume !(0 == ~E_6~0); {9881#false} is VALID [2022-02-21 04:24:20,265 INFO L290 TraceCheckUtils]: 31: Hoare triple {9881#false} assume !(0 == ~E_7~0); {9881#false} is VALID [2022-02-21 04:24:20,265 INFO L290 TraceCheckUtils]: 32: Hoare triple {9881#false} assume !(0 == ~E_8~0); {9881#false} is VALID [2022-02-21 04:24:20,265 INFO L290 TraceCheckUtils]: 33: Hoare triple {9881#false} assume !(0 == ~E_9~0); {9881#false} is VALID [2022-02-21 04:24:20,265 INFO L290 TraceCheckUtils]: 34: Hoare triple {9881#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {9881#false} is VALID [2022-02-21 04:24:20,265 INFO L290 TraceCheckUtils]: 35: Hoare triple {9881#false} assume !(1 == ~m_pc~0); {9881#false} is VALID [2022-02-21 04:24:20,266 INFO L290 TraceCheckUtils]: 36: Hoare triple {9881#false} is_master_triggered_~__retres1~0#1 := 0; {9881#false} is VALID [2022-02-21 04:24:20,266 INFO L290 TraceCheckUtils]: 37: Hoare triple {9881#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {9881#false} is VALID [2022-02-21 04:24:20,266 INFO L290 TraceCheckUtils]: 38: Hoare triple {9881#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {9881#false} is VALID [2022-02-21 04:24:20,266 INFO L290 TraceCheckUtils]: 39: Hoare triple {9881#false} assume !(0 != activate_threads_~tmp~1#1); {9881#false} is VALID [2022-02-21 04:24:20,266 INFO L290 TraceCheckUtils]: 40: Hoare triple {9881#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {9881#false} is VALID [2022-02-21 04:24:20,266 INFO L290 TraceCheckUtils]: 41: Hoare triple {9881#false} assume 1 == ~t1_pc~0; {9881#false} is VALID [2022-02-21 04:24:20,266 INFO L290 TraceCheckUtils]: 42: Hoare triple {9881#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {9881#false} is VALID [2022-02-21 04:24:20,266 INFO L290 TraceCheckUtils]: 43: Hoare triple {9881#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {9881#false} is VALID [2022-02-21 04:24:20,266 INFO L290 TraceCheckUtils]: 44: Hoare triple {9881#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {9881#false} is VALID [2022-02-21 04:24:20,267 INFO L290 TraceCheckUtils]: 45: Hoare triple {9881#false} assume !(0 != activate_threads_~tmp___0~0#1); {9881#false} is VALID [2022-02-21 04:24:20,267 INFO L290 TraceCheckUtils]: 46: Hoare triple {9881#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {9881#false} is VALID [2022-02-21 04:24:20,267 INFO L290 TraceCheckUtils]: 47: Hoare triple {9881#false} assume !(1 == ~t2_pc~0); {9881#false} is VALID [2022-02-21 04:24:20,267 INFO L290 TraceCheckUtils]: 48: Hoare triple {9881#false} is_transmit2_triggered_~__retres1~2#1 := 0; {9881#false} is VALID [2022-02-21 04:24:20,267 INFO L290 TraceCheckUtils]: 49: Hoare triple {9881#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {9881#false} is VALID [2022-02-21 04:24:20,267 INFO L290 TraceCheckUtils]: 50: Hoare triple {9881#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {9881#false} is VALID [2022-02-21 04:24:20,267 INFO L290 TraceCheckUtils]: 51: Hoare triple {9881#false} assume !(0 != activate_threads_~tmp___1~0#1); {9881#false} is VALID [2022-02-21 04:24:20,267 INFO L290 TraceCheckUtils]: 52: Hoare triple {9881#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {9881#false} is VALID [2022-02-21 04:24:20,267 INFO L290 TraceCheckUtils]: 53: Hoare triple {9881#false} assume 1 == ~t3_pc~0; {9881#false} is VALID [2022-02-21 04:24:20,268 INFO L290 TraceCheckUtils]: 54: Hoare triple {9881#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {9881#false} is VALID [2022-02-21 04:24:20,268 INFO L290 TraceCheckUtils]: 55: Hoare triple {9881#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {9881#false} is VALID [2022-02-21 04:24:20,268 INFO L290 TraceCheckUtils]: 56: Hoare triple {9881#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {9881#false} is VALID [2022-02-21 04:24:20,268 INFO L290 TraceCheckUtils]: 57: Hoare triple {9881#false} assume !(0 != activate_threads_~tmp___2~0#1); {9881#false} is VALID [2022-02-21 04:24:20,268 INFO L290 TraceCheckUtils]: 58: Hoare triple {9881#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {9881#false} is VALID [2022-02-21 04:24:20,268 INFO L290 TraceCheckUtils]: 59: Hoare triple {9881#false} assume 1 == ~t4_pc~0; {9881#false} is VALID [2022-02-21 04:24:20,268 INFO L290 TraceCheckUtils]: 60: Hoare triple {9881#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {9881#false} is VALID [2022-02-21 04:24:20,268 INFO L290 TraceCheckUtils]: 61: Hoare triple {9881#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {9881#false} is VALID [2022-02-21 04:24:20,268 INFO L290 TraceCheckUtils]: 62: Hoare triple {9881#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {9881#false} is VALID [2022-02-21 04:24:20,269 INFO L290 TraceCheckUtils]: 63: Hoare triple {9881#false} assume !(0 != activate_threads_~tmp___3~0#1); {9881#false} is VALID [2022-02-21 04:24:20,269 INFO L290 TraceCheckUtils]: 64: Hoare triple {9881#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {9881#false} is VALID [2022-02-21 04:24:20,269 INFO L290 TraceCheckUtils]: 65: Hoare triple {9881#false} assume !(1 == ~t5_pc~0); {9881#false} is VALID [2022-02-21 04:24:20,269 INFO L290 TraceCheckUtils]: 66: Hoare triple {9881#false} is_transmit5_triggered_~__retres1~5#1 := 0; {9881#false} is VALID [2022-02-21 04:24:20,269 INFO L290 TraceCheckUtils]: 67: Hoare triple {9881#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {9881#false} is VALID [2022-02-21 04:24:20,269 INFO L290 TraceCheckUtils]: 68: Hoare triple {9881#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {9881#false} is VALID [2022-02-21 04:24:20,269 INFO L290 TraceCheckUtils]: 69: Hoare triple {9881#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {9881#false} is VALID [2022-02-21 04:24:20,269 INFO L290 TraceCheckUtils]: 70: Hoare triple {9881#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {9881#false} is VALID [2022-02-21 04:24:20,270 INFO L290 TraceCheckUtils]: 71: Hoare triple {9881#false} assume 1 == ~t6_pc~0; {9881#false} is VALID [2022-02-21 04:24:20,270 INFO L290 TraceCheckUtils]: 72: Hoare triple {9881#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {9881#false} is VALID [2022-02-21 04:24:20,270 INFO L290 TraceCheckUtils]: 73: Hoare triple {9881#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {9881#false} is VALID [2022-02-21 04:24:20,270 INFO L290 TraceCheckUtils]: 74: Hoare triple {9881#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {9881#false} is VALID [2022-02-21 04:24:20,270 INFO L290 TraceCheckUtils]: 75: Hoare triple {9881#false} assume !(0 != activate_threads_~tmp___5~0#1); {9881#false} is VALID [2022-02-21 04:24:20,270 INFO L290 TraceCheckUtils]: 76: Hoare triple {9881#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {9881#false} is VALID [2022-02-21 04:24:20,270 INFO L290 TraceCheckUtils]: 77: Hoare triple {9881#false} assume !(1 == ~t7_pc~0); {9881#false} is VALID [2022-02-21 04:24:20,270 INFO L290 TraceCheckUtils]: 78: Hoare triple {9881#false} is_transmit7_triggered_~__retres1~7#1 := 0; {9881#false} is VALID [2022-02-21 04:24:20,270 INFO L290 TraceCheckUtils]: 79: Hoare triple {9881#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {9881#false} is VALID [2022-02-21 04:24:20,271 INFO L290 TraceCheckUtils]: 80: Hoare triple {9881#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {9881#false} is VALID [2022-02-21 04:24:20,271 INFO L290 TraceCheckUtils]: 81: Hoare triple {9881#false} assume !(0 != activate_threads_~tmp___6~0#1); {9881#false} is VALID [2022-02-21 04:24:20,271 INFO L290 TraceCheckUtils]: 82: Hoare triple {9881#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {9881#false} is VALID [2022-02-21 04:24:20,271 INFO L290 TraceCheckUtils]: 83: Hoare triple {9881#false} assume 1 == ~t8_pc~0; {9881#false} is VALID [2022-02-21 04:24:20,271 INFO L290 TraceCheckUtils]: 84: Hoare triple {9881#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {9881#false} is VALID [2022-02-21 04:24:20,271 INFO L290 TraceCheckUtils]: 85: Hoare triple {9881#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {9881#false} is VALID [2022-02-21 04:24:20,271 INFO L290 TraceCheckUtils]: 86: Hoare triple {9881#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {9881#false} is VALID [2022-02-21 04:24:20,271 INFO L290 TraceCheckUtils]: 87: Hoare triple {9881#false} assume !(0 != activate_threads_~tmp___7~0#1); {9881#false} is VALID [2022-02-21 04:24:20,271 INFO L290 TraceCheckUtils]: 88: Hoare triple {9881#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {9881#false} is VALID [2022-02-21 04:24:20,272 INFO L290 TraceCheckUtils]: 89: Hoare triple {9881#false} assume !(1 == ~t9_pc~0); {9881#false} is VALID [2022-02-21 04:24:20,272 INFO L290 TraceCheckUtils]: 90: Hoare triple {9881#false} is_transmit9_triggered_~__retres1~9#1 := 0; {9881#false} is VALID [2022-02-21 04:24:20,272 INFO L290 TraceCheckUtils]: 91: Hoare triple {9881#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {9881#false} is VALID [2022-02-21 04:24:20,272 INFO L290 TraceCheckUtils]: 92: Hoare triple {9881#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {9881#false} is VALID [2022-02-21 04:24:20,272 INFO L290 TraceCheckUtils]: 93: Hoare triple {9881#false} assume !(0 != activate_threads_~tmp___8~0#1); {9881#false} is VALID [2022-02-21 04:24:20,272 INFO L290 TraceCheckUtils]: 94: Hoare triple {9881#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {9881#false} is VALID [2022-02-21 04:24:20,272 INFO L290 TraceCheckUtils]: 95: Hoare triple {9881#false} assume !(1 == ~M_E~0); {9881#false} is VALID [2022-02-21 04:24:20,272 INFO L290 TraceCheckUtils]: 96: Hoare triple {9881#false} assume !(1 == ~T1_E~0); {9881#false} is VALID [2022-02-21 04:24:20,272 INFO L290 TraceCheckUtils]: 97: Hoare triple {9881#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {9881#false} is VALID [2022-02-21 04:24:20,273 INFO L290 TraceCheckUtils]: 98: Hoare triple {9881#false} assume !(1 == ~T3_E~0); {9881#false} is VALID [2022-02-21 04:24:20,273 INFO L290 TraceCheckUtils]: 99: Hoare triple {9881#false} assume !(1 == ~T4_E~0); {9881#false} is VALID [2022-02-21 04:24:20,273 INFO L290 TraceCheckUtils]: 100: Hoare triple {9881#false} assume !(1 == ~T5_E~0); {9881#false} is VALID [2022-02-21 04:24:20,273 INFO L290 TraceCheckUtils]: 101: Hoare triple {9881#false} assume !(1 == ~T6_E~0); {9881#false} is VALID [2022-02-21 04:24:20,273 INFO L290 TraceCheckUtils]: 102: Hoare triple {9881#false} assume !(1 == ~T7_E~0); {9881#false} is VALID [2022-02-21 04:24:20,273 INFO L290 TraceCheckUtils]: 103: Hoare triple {9881#false} assume !(1 == ~T8_E~0); {9881#false} is VALID [2022-02-21 04:24:20,273 INFO L290 TraceCheckUtils]: 104: Hoare triple {9881#false} assume !(1 == ~T9_E~0); {9881#false} is VALID [2022-02-21 04:24:20,273 INFO L290 TraceCheckUtils]: 105: Hoare triple {9881#false} assume 1 == ~E_1~0;~E_1~0 := 2; {9881#false} is VALID [2022-02-21 04:24:20,273 INFO L290 TraceCheckUtils]: 106: Hoare triple {9881#false} assume !(1 == ~E_2~0); {9881#false} is VALID [2022-02-21 04:24:20,274 INFO L290 TraceCheckUtils]: 107: Hoare triple {9881#false} assume !(1 == ~E_3~0); {9881#false} is VALID [2022-02-21 04:24:20,274 INFO L290 TraceCheckUtils]: 108: Hoare triple {9881#false} assume !(1 == ~E_4~0); {9881#false} is VALID [2022-02-21 04:24:20,274 INFO L290 TraceCheckUtils]: 109: Hoare triple {9881#false} assume !(1 == ~E_5~0); {9881#false} is VALID [2022-02-21 04:24:20,274 INFO L290 TraceCheckUtils]: 110: Hoare triple {9881#false} assume !(1 == ~E_6~0); {9881#false} is VALID [2022-02-21 04:24:20,274 INFO L290 TraceCheckUtils]: 111: Hoare triple {9881#false} assume !(1 == ~E_7~0); {9881#false} is VALID [2022-02-21 04:24:20,274 INFO L290 TraceCheckUtils]: 112: Hoare triple {9881#false} assume !(1 == ~E_8~0); {9881#false} is VALID [2022-02-21 04:24:20,274 INFO L290 TraceCheckUtils]: 113: Hoare triple {9881#false} assume 1 == ~E_9~0;~E_9~0 := 2; {9881#false} is VALID [2022-02-21 04:24:20,274 INFO L290 TraceCheckUtils]: 114: Hoare triple {9881#false} assume { :end_inline_reset_delta_events } true; {9881#false} is VALID [2022-02-21 04:24:20,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:20,275 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:20,275 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276390339] [2022-02-21 04:24:20,275 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276390339] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:20,276 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:20,276 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:20,276 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845183894] [2022-02-21 04:24:20,276 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:20,276 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:20,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:20,277 INFO L85 PathProgramCache]: Analyzing trace with hash 1719929938, now seen corresponding path program 1 times [2022-02-21 04:24:20,277 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:20,277 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588951402] [2022-02-21 04:24:20,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:20,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:20,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:20,329 INFO L290 TraceCheckUtils]: 0: Hoare triple {9883#true} assume !false; {9883#true} is VALID [2022-02-21 04:24:20,329 INFO L290 TraceCheckUtils]: 1: Hoare triple {9883#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {9883#true} is VALID [2022-02-21 04:24:20,329 INFO L290 TraceCheckUtils]: 2: Hoare triple {9883#true} assume !false; {9883#true} is VALID [2022-02-21 04:24:20,330 INFO L290 TraceCheckUtils]: 3: Hoare triple {9883#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {9883#true} is VALID [2022-02-21 04:24:20,330 INFO L290 TraceCheckUtils]: 4: Hoare triple {9883#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {9883#true} is VALID [2022-02-21 04:24:20,330 INFO L290 TraceCheckUtils]: 5: Hoare triple {9883#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {9883#true} is VALID [2022-02-21 04:24:20,330 INFO L290 TraceCheckUtils]: 6: Hoare triple {9883#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {9883#true} is VALID [2022-02-21 04:24:20,330 INFO L290 TraceCheckUtils]: 7: Hoare triple {9883#true} assume !(0 != eval_~tmp~0#1); {9883#true} is VALID [2022-02-21 04:24:20,330 INFO L290 TraceCheckUtils]: 8: Hoare triple {9883#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {9883#true} is VALID [2022-02-21 04:24:20,330 INFO L290 TraceCheckUtils]: 9: Hoare triple {9883#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {9883#true} is VALID [2022-02-21 04:24:20,330 INFO L290 TraceCheckUtils]: 10: Hoare triple {9883#true} assume 0 == ~M_E~0;~M_E~0 := 1; {9883#true} is VALID [2022-02-21 04:24:20,331 INFO L290 TraceCheckUtils]: 11: Hoare triple {9883#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {9883#true} is VALID [2022-02-21 04:24:20,331 INFO L290 TraceCheckUtils]: 12: Hoare triple {9883#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {9883#true} is VALID [2022-02-21 04:24:20,331 INFO L290 TraceCheckUtils]: 13: Hoare triple {9883#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,331 INFO L290 TraceCheckUtils]: 14: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,332 INFO L290 TraceCheckUtils]: 15: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T5_E~0); {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,332 INFO L290 TraceCheckUtils]: 16: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,332 INFO L290 TraceCheckUtils]: 17: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,332 INFO L290 TraceCheckUtils]: 18: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,333 INFO L290 TraceCheckUtils]: 19: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,333 INFO L290 TraceCheckUtils]: 20: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,333 INFO L290 TraceCheckUtils]: 21: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,334 INFO L290 TraceCheckUtils]: 22: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,334 INFO L290 TraceCheckUtils]: 23: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_4~0); {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,334 INFO L290 TraceCheckUtils]: 24: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,334 INFO L290 TraceCheckUtils]: 25: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,335 INFO L290 TraceCheckUtils]: 26: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,335 INFO L290 TraceCheckUtils]: 27: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,335 INFO L290 TraceCheckUtils]: 28: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,336 INFO L290 TraceCheckUtils]: 29: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,336 INFO L290 TraceCheckUtils]: 30: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~m_pc~0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,336 INFO L290 TraceCheckUtils]: 31: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,336 INFO L290 TraceCheckUtils]: 32: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,337 INFO L290 TraceCheckUtils]: 33: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,337 INFO L290 TraceCheckUtils]: 34: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,337 INFO L290 TraceCheckUtils]: 35: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,337 INFO L290 TraceCheckUtils]: 36: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t1_pc~0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,338 INFO L290 TraceCheckUtils]: 37: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,338 INFO L290 TraceCheckUtils]: 38: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,338 INFO L290 TraceCheckUtils]: 39: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,339 INFO L290 TraceCheckUtils]: 40: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,339 INFO L290 TraceCheckUtils]: 41: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,339 INFO L290 TraceCheckUtils]: 42: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t2_pc~0); {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,339 INFO L290 TraceCheckUtils]: 43: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,340 INFO L290 TraceCheckUtils]: 44: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,340 INFO L290 TraceCheckUtils]: 45: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,340 INFO L290 TraceCheckUtils]: 46: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,341 INFO L290 TraceCheckUtils]: 47: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,341 INFO L290 TraceCheckUtils]: 48: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t3_pc~0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,341 INFO L290 TraceCheckUtils]: 49: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,341 INFO L290 TraceCheckUtils]: 50: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,342 INFO L290 TraceCheckUtils]: 51: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,342 INFO L290 TraceCheckUtils]: 52: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,342 INFO L290 TraceCheckUtils]: 53: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,342 INFO L290 TraceCheckUtils]: 54: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t4_pc~0); {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,343 INFO L290 TraceCheckUtils]: 55: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,343 INFO L290 TraceCheckUtils]: 56: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,343 INFO L290 TraceCheckUtils]: 57: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,344 INFO L290 TraceCheckUtils]: 58: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,344 INFO L290 TraceCheckUtils]: 59: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,344 INFO L290 TraceCheckUtils]: 60: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t5_pc~0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,344 INFO L290 TraceCheckUtils]: 61: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,345 INFO L290 TraceCheckUtils]: 62: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,345 INFO L290 TraceCheckUtils]: 63: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,345 INFO L290 TraceCheckUtils]: 64: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,346 INFO L290 TraceCheckUtils]: 65: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,346 INFO L290 TraceCheckUtils]: 66: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t6_pc~0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,346 INFO L290 TraceCheckUtils]: 67: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,346 INFO L290 TraceCheckUtils]: 68: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,347 INFO L290 TraceCheckUtils]: 69: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,347 INFO L290 TraceCheckUtils]: 70: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,347 INFO L290 TraceCheckUtils]: 71: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,347 INFO L290 TraceCheckUtils]: 72: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t7_pc~0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,348 INFO L290 TraceCheckUtils]: 73: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,348 INFO L290 TraceCheckUtils]: 74: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,348 INFO L290 TraceCheckUtils]: 75: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,349 INFO L290 TraceCheckUtils]: 76: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,349 INFO L290 TraceCheckUtils]: 77: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,349 INFO L290 TraceCheckUtils]: 78: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t8_pc~0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,349 INFO L290 TraceCheckUtils]: 79: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,350 INFO L290 TraceCheckUtils]: 80: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,350 INFO L290 TraceCheckUtils]: 81: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,350 INFO L290 TraceCheckUtils]: 82: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,350 INFO L290 TraceCheckUtils]: 83: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,351 INFO L290 TraceCheckUtils]: 84: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t9_pc~0); {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,351 INFO L290 TraceCheckUtils]: 85: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,351 INFO L290 TraceCheckUtils]: 86: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,351 INFO L290 TraceCheckUtils]: 87: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,352 INFO L290 TraceCheckUtils]: 88: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,352 INFO L290 TraceCheckUtils]: 89: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,352 INFO L290 TraceCheckUtils]: 90: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,353 INFO L290 TraceCheckUtils]: 91: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,353 INFO L290 TraceCheckUtils]: 92: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {9885#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:20,353 INFO L290 TraceCheckUtils]: 93: Hoare triple {9885#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~T3_E~0); {9884#false} is VALID [2022-02-21 04:24:20,353 INFO L290 TraceCheckUtils]: 94: Hoare triple {9884#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,353 INFO L290 TraceCheckUtils]: 95: Hoare triple {9884#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,354 INFO L290 TraceCheckUtils]: 96: Hoare triple {9884#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,354 INFO L290 TraceCheckUtils]: 97: Hoare triple {9884#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,354 INFO L290 TraceCheckUtils]: 98: Hoare triple {9884#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,354 INFO L290 TraceCheckUtils]: 99: Hoare triple {9884#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,354 INFO L290 TraceCheckUtils]: 100: Hoare triple {9884#false} assume 1 == ~E_1~0;~E_1~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,354 INFO L290 TraceCheckUtils]: 101: Hoare triple {9884#false} assume !(1 == ~E_2~0); {9884#false} is VALID [2022-02-21 04:24:20,354 INFO L290 TraceCheckUtils]: 102: Hoare triple {9884#false} assume 1 == ~E_3~0;~E_3~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,354 INFO L290 TraceCheckUtils]: 103: Hoare triple {9884#false} assume 1 == ~E_4~0;~E_4~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,354 INFO L290 TraceCheckUtils]: 104: Hoare triple {9884#false} assume 1 == ~E_5~0;~E_5~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,355 INFO L290 TraceCheckUtils]: 105: Hoare triple {9884#false} assume 1 == ~E_6~0;~E_6~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,355 INFO L290 TraceCheckUtils]: 106: Hoare triple {9884#false} assume 1 == ~E_7~0;~E_7~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,355 INFO L290 TraceCheckUtils]: 107: Hoare triple {9884#false} assume 1 == ~E_8~0;~E_8~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,355 INFO L290 TraceCheckUtils]: 108: Hoare triple {9884#false} assume 1 == ~E_9~0;~E_9~0 := 2; {9884#false} is VALID [2022-02-21 04:24:20,355 INFO L290 TraceCheckUtils]: 109: Hoare triple {9884#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {9884#false} is VALID [2022-02-21 04:24:20,355 INFO L290 TraceCheckUtils]: 110: Hoare triple {9884#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {9884#false} is VALID [2022-02-21 04:24:20,355 INFO L290 TraceCheckUtils]: 111: Hoare triple {9884#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {9884#false} is VALID [2022-02-21 04:24:20,355 INFO L290 TraceCheckUtils]: 112: Hoare triple {9884#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {9884#false} is VALID [2022-02-21 04:24:20,356 INFO L290 TraceCheckUtils]: 113: Hoare triple {9884#false} assume !(0 == start_simulation_~tmp~3#1); {9884#false} is VALID [2022-02-21 04:24:20,356 INFO L290 TraceCheckUtils]: 114: Hoare triple {9884#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {9884#false} is VALID [2022-02-21 04:24:20,356 INFO L290 TraceCheckUtils]: 115: Hoare triple {9884#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {9884#false} is VALID [2022-02-21 04:24:20,356 INFO L290 TraceCheckUtils]: 116: Hoare triple {9884#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {9884#false} is VALID [2022-02-21 04:24:20,356 INFO L290 TraceCheckUtils]: 117: Hoare triple {9884#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {9884#false} is VALID [2022-02-21 04:24:20,356 INFO L290 TraceCheckUtils]: 118: Hoare triple {9884#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {9884#false} is VALID [2022-02-21 04:24:20,356 INFO L290 TraceCheckUtils]: 119: Hoare triple {9884#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {9884#false} is VALID [2022-02-21 04:24:20,356 INFO L290 TraceCheckUtils]: 120: Hoare triple {9884#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {9884#false} is VALID [2022-02-21 04:24:20,357 INFO L290 TraceCheckUtils]: 121: Hoare triple {9884#false} assume !(0 != start_simulation_~tmp___0~1#1); {9884#false} is VALID [2022-02-21 04:24:20,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:20,357 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:20,358 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588951402] [2022-02-21 04:24:20,358 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588951402] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:20,358 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:20,358 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:20,358 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2028343251] [2022-02-21 04:24:20,359 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:20,359 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:20,359 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:20,360 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:20,360 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:20,360 INFO L87 Difference]: Start difference. First operand 1094 states and 1629 transitions. cyclomatic complexity: 536 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:21,180 INFO L93 Difference]: Finished difference Result 1094 states and 1628 transitions. [2022-02-21 04:24:21,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:21,181 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,258 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:21,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1628 transitions. [2022-02-21 04:24:21,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:21,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1628 transitions. [2022-02-21 04:24:21,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-02-21 04:24:21,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-02-21 04:24:21,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1628 transitions. [2022-02-21 04:24:21,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:21,353 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2022-02-21 04:24:21,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1628 transitions. [2022-02-21 04:24:21,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-02-21 04:24:21,366 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:21,369 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1094 states and 1628 transitions. Second operand has 1094 states, 1094 states have (on average 1.4881170018281535) internal successors, (1628), 1093 states have internal predecessors, (1628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,370 INFO L74 IsIncluded]: Start isIncluded. First operand 1094 states and 1628 transitions. Second operand has 1094 states, 1094 states have (on average 1.4881170018281535) internal successors, (1628), 1093 states have internal predecessors, (1628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,372 INFO L87 Difference]: Start difference. First operand 1094 states and 1628 transitions. Second operand has 1094 states, 1094 states have (on average 1.4881170018281535) internal successors, (1628), 1093 states have internal predecessors, (1628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:21,403 INFO L93 Difference]: Finished difference Result 1094 states and 1628 transitions. [2022-02-21 04:24:21,403 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1628 transitions. [2022-02-21 04:24:21,405 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:21,405 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:21,408 INFO L74 IsIncluded]: Start isIncluded. First operand has 1094 states, 1094 states have (on average 1.4881170018281535) internal successors, (1628), 1093 states have internal predecessors, (1628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1628 transitions. [2022-02-21 04:24:21,409 INFO L87 Difference]: Start difference. First operand has 1094 states, 1094 states have (on average 1.4881170018281535) internal successors, (1628), 1093 states have internal predecessors, (1628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1628 transitions. [2022-02-21 04:24:21,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:21,441 INFO L93 Difference]: Finished difference Result 1094 states and 1628 transitions. [2022-02-21 04:24:21,441 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1628 transitions. [2022-02-21 04:24:21,443 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:21,443 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:21,443 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:21,443 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:21,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4881170018281535) internal successors, (1628), 1093 states have internal predecessors, (1628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1628 transitions. [2022-02-21 04:24:21,477 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2022-02-21 04:24:21,477 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1628 transitions. [2022-02-21 04:24:21,478 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:21,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1628 transitions. [2022-02-21 04:24:21,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:21,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:21,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:21,484 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:21,484 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:21,485 INFO L791 eck$LassoCheckResult]: Stem: 11817#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 11818#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 11418#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11419#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11965#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 11966#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11948#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11768#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11769#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11585#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11586#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12026#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11932#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11640#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11424#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11425#L922 assume !(0 == ~M_E~0); 12070#L922-2 assume !(0 == ~T1_E~0); 12071#L927-1 assume !(0 == ~T2_E~0); 11825#L932-1 assume !(0 == ~T3_E~0); 11710#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11711#L942-1 assume !(0 == ~T5_E~0); 11767#L947-1 assume !(0 == ~T6_E~0); 11829#L952-1 assume !(0 == ~T7_E~0); 11830#L957-1 assume !(0 == ~T8_E~0); 11892#L962-1 assume !(0 == ~T9_E~0); 11686#L967-1 assume !(0 == ~E_1~0); 11687#L972-1 assume !(0 == ~E_2~0); 11953#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 11954#L982-1 assume !(0 == ~E_4~0); 11194#L987-1 assume !(0 == ~E_5~0); 11195#L992-1 assume !(0 == ~E_6~0); 11203#L997-1 assume !(0 == ~E_7~0); 11619#L1002-1 assume !(0 == ~E_8~0); 11605#L1007-1 assume !(0 == ~E_9~0); 10992#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10993#L443 assume !(1 == ~m_pc~0); 11845#L443-2 is_master_triggered_~__retres1~0#1 := 0; 11836#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11837#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11358#L1140 assume !(0 != activate_threads_~tmp~1#1); 11107#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11108#L462 assume 1 == ~t1_pc~0; 11736#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11706#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11078#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11079#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 11566#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11567#L481 assume !(1 == ~t2_pc~0); 11353#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11352#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11707#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11446#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 11447#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11541#L500 assume 1 == ~t3_pc~0; 11749#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11750#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11940#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11941#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 10997#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10998#L519 assume 1 == ~t4_pc~0; 11296#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11297#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11538#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11400#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 11401#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11161#L538 assume !(1 == ~t5_pc~0); 11162#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11068#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11069#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11337#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11338#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11877#L557 assume 1 == ~t6_pc~0; 11674#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11375#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11277#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11278#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 11402#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12053#L576 assume !(1 == ~t7_pc~0); 11362#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11363#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11607#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11608#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 11924#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11485#L595 assume 1 == ~t8_pc~0; 11486#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11942#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11943#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11792#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 11793#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11286#L614 assume !(1 == ~t9_pc~0); 11287#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11186#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11187#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11366#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 11448#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11449#L1025 assume !(1 == ~M_E~0); 11695#L1025-2 assume !(1 == ~T1_E~0); 11748#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11871#L1035-1 assume !(1 == ~T3_E~0); 11443#L1040-1 assume !(1 == ~T4_E~0); 11444#L1045-1 assume !(1 == ~T5_E~0); 11348#L1050-1 assume !(1 == ~T6_E~0); 11349#L1055-1 assume !(1 == ~T7_E~0); 11170#L1060-1 assume !(1 == ~T8_E~0); 11171#L1065-1 assume !(1 == ~T9_E~0); 11234#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11831#L1075-1 assume !(1 == ~E_2~0); 11832#L1080-1 assume !(1 == ~E_3~0); 11820#L1085-1 assume !(1 == ~E_4~0); 11821#L1090-1 assume !(1 == ~E_5~0); 12020#L1095-1 assume !(1 == ~E_6~0); 11854#L1100-1 assume !(1 == ~E_7~0); 11855#L1105-1 assume !(1 == ~E_8~0); 11143#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 11144#L1115-1 assume { :end_inline_reset_delta_events } true; 11305#L1396-2 [2022-02-21 04:24:21,485 INFO L793 eck$LassoCheckResult]: Loop: 11305#L1396-2 assume !false; 11391#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11417#L897 assume !false; 12060#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11967#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11017#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11018#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12015#L766 assume !(0 != eval_~tmp~0#1); 12001#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11085#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11086#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11602#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11329#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11330#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11508#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11135#L942-3 assume !(0 == ~T5_E~0); 11136#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11509#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11510#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12011#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11902#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11903#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11823#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11824#L982-3 assume !(0 == ~E_4~0); 12072#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11459#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11460#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11454#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11455#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11172#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11173#L443-30 assume 1 == ~m_pc~0; 11206#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11207#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11490#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12038#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11957#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11590#L462-30 assume 1 == ~t1_pc~0; 11434#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11436#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11937#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11938#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11979#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11577#L481-30 assume 1 == ~t2_pc~0; 11293#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11294#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11350#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11263#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11264#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11544#L500-30 assume 1 == ~t3_pc~0; 11301#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11302#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11364#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11365#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11527#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11528#L519-30 assume 1 == ~t4_pc~0; 11863#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11679#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11041#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11042#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11691#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11804#L538-30 assume !(1 == ~t5_pc~0); 11184#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 11183#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11481#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11482#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11259#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11260#L557-30 assume 1 == ~t6_pc~0; 10980#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10981#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11658#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11712#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 11284#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11285#L576-30 assume 1 == ~t7_pc~0; 11797#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11067#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11652#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12018#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11442#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11407#L595-30 assume !(1 == ~t8_pc~0); 11408#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 11343#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11076#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11077#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12019#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12055#L614-30 assume 1 == ~t9_pc~0; 11345#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11346#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11480#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11174#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11175#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11783#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11568#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11569#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11753#L1035-3 assume !(1 == ~T3_E~0); 12028#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12068#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12024#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11939#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11074#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11075#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11959#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11805#L1075-3 assume !(1 == ~E_2~0); 11806#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12029#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11950#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11951#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11970#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11971#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11222#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11223#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11983#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11091#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11080#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 11081#L1415 assume !(0 == start_simulation_~tmp~3#1); 11684#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11685#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11131#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11693#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 11872#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12073#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11743#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 11304#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 11305#L1396-2 [2022-02-21 04:24:21,486 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:21,486 INFO L85 PathProgramCache]: Analyzing trace with hash 1764315747, now seen corresponding path program 1 times [2022-02-21 04:24:21,486 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:21,486 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004627299] [2022-02-21 04:24:21,487 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:21,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:21,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:21,510 INFO L290 TraceCheckUtils]: 0: Hoare triple {14265#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {14265#true} is VALID [2022-02-21 04:24:21,510 INFO L290 TraceCheckUtils]: 1: Hoare triple {14265#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {14267#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:21,511 INFO L290 TraceCheckUtils]: 2: Hoare triple {14267#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {14267#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:21,511 INFO L290 TraceCheckUtils]: 3: Hoare triple {14267#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {14267#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:21,511 INFO L290 TraceCheckUtils]: 4: Hoare triple {14267#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {14267#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:21,511 INFO L290 TraceCheckUtils]: 5: Hoare triple {14267#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {14267#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:21,512 INFO L290 TraceCheckUtils]: 6: Hoare triple {14267#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {14267#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:21,512 INFO L290 TraceCheckUtils]: 7: Hoare triple {14267#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {14267#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:21,512 INFO L290 TraceCheckUtils]: 8: Hoare triple {14267#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {14266#false} is VALID [2022-02-21 04:24:21,512 INFO L290 TraceCheckUtils]: 9: Hoare triple {14266#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {14266#false} is VALID [2022-02-21 04:24:21,513 INFO L290 TraceCheckUtils]: 10: Hoare triple {14266#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {14266#false} is VALID [2022-02-21 04:24:21,513 INFO L290 TraceCheckUtils]: 11: Hoare triple {14266#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {14266#false} is VALID [2022-02-21 04:24:21,513 INFO L290 TraceCheckUtils]: 12: Hoare triple {14266#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {14266#false} is VALID [2022-02-21 04:24:21,513 INFO L290 TraceCheckUtils]: 13: Hoare triple {14266#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {14266#false} is VALID [2022-02-21 04:24:21,513 INFO L290 TraceCheckUtils]: 14: Hoare triple {14266#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {14266#false} is VALID [2022-02-21 04:24:21,513 INFO L290 TraceCheckUtils]: 15: Hoare triple {14266#false} assume !(0 == ~M_E~0); {14266#false} is VALID [2022-02-21 04:24:21,513 INFO L290 TraceCheckUtils]: 16: Hoare triple {14266#false} assume !(0 == ~T1_E~0); {14266#false} is VALID [2022-02-21 04:24:21,513 INFO L290 TraceCheckUtils]: 17: Hoare triple {14266#false} assume !(0 == ~T2_E~0); {14266#false} is VALID [2022-02-21 04:24:21,513 INFO L290 TraceCheckUtils]: 18: Hoare triple {14266#false} assume !(0 == ~T3_E~0); {14266#false} is VALID [2022-02-21 04:24:21,514 INFO L290 TraceCheckUtils]: 19: Hoare triple {14266#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {14266#false} is VALID [2022-02-21 04:24:21,514 INFO L290 TraceCheckUtils]: 20: Hoare triple {14266#false} assume !(0 == ~T5_E~0); {14266#false} is VALID [2022-02-21 04:24:21,514 INFO L290 TraceCheckUtils]: 21: Hoare triple {14266#false} assume !(0 == ~T6_E~0); {14266#false} is VALID [2022-02-21 04:24:21,514 INFO L290 TraceCheckUtils]: 22: Hoare triple {14266#false} assume !(0 == ~T7_E~0); {14266#false} is VALID [2022-02-21 04:24:21,514 INFO L290 TraceCheckUtils]: 23: Hoare triple {14266#false} assume !(0 == ~T8_E~0); {14266#false} is VALID [2022-02-21 04:24:21,514 INFO L290 TraceCheckUtils]: 24: Hoare triple {14266#false} assume !(0 == ~T9_E~0); {14266#false} is VALID [2022-02-21 04:24:21,514 INFO L290 TraceCheckUtils]: 25: Hoare triple {14266#false} assume !(0 == ~E_1~0); {14266#false} is VALID [2022-02-21 04:24:21,514 INFO L290 TraceCheckUtils]: 26: Hoare triple {14266#false} assume !(0 == ~E_2~0); {14266#false} is VALID [2022-02-21 04:24:21,515 INFO L290 TraceCheckUtils]: 27: Hoare triple {14266#false} assume 0 == ~E_3~0;~E_3~0 := 1; {14266#false} is VALID [2022-02-21 04:24:21,515 INFO L290 TraceCheckUtils]: 28: Hoare triple {14266#false} assume !(0 == ~E_4~0); {14266#false} is VALID [2022-02-21 04:24:21,515 INFO L290 TraceCheckUtils]: 29: Hoare triple {14266#false} assume !(0 == ~E_5~0); {14266#false} is VALID [2022-02-21 04:24:21,515 INFO L290 TraceCheckUtils]: 30: Hoare triple {14266#false} assume !(0 == ~E_6~0); {14266#false} is VALID [2022-02-21 04:24:21,515 INFO L290 TraceCheckUtils]: 31: Hoare triple {14266#false} assume !(0 == ~E_7~0); {14266#false} is VALID [2022-02-21 04:24:21,515 INFO L290 TraceCheckUtils]: 32: Hoare triple {14266#false} assume !(0 == ~E_8~0); {14266#false} is VALID [2022-02-21 04:24:21,515 INFO L290 TraceCheckUtils]: 33: Hoare triple {14266#false} assume !(0 == ~E_9~0); {14266#false} is VALID [2022-02-21 04:24:21,515 INFO L290 TraceCheckUtils]: 34: Hoare triple {14266#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14266#false} is VALID [2022-02-21 04:24:21,515 INFO L290 TraceCheckUtils]: 35: Hoare triple {14266#false} assume !(1 == ~m_pc~0); {14266#false} is VALID [2022-02-21 04:24:21,516 INFO L290 TraceCheckUtils]: 36: Hoare triple {14266#false} is_master_triggered_~__retres1~0#1 := 0; {14266#false} is VALID [2022-02-21 04:24:21,516 INFO L290 TraceCheckUtils]: 37: Hoare triple {14266#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14266#false} is VALID [2022-02-21 04:24:21,516 INFO L290 TraceCheckUtils]: 38: Hoare triple {14266#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {14266#false} is VALID [2022-02-21 04:24:21,516 INFO L290 TraceCheckUtils]: 39: Hoare triple {14266#false} assume !(0 != activate_threads_~tmp~1#1); {14266#false} is VALID [2022-02-21 04:24:21,516 INFO L290 TraceCheckUtils]: 40: Hoare triple {14266#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14266#false} is VALID [2022-02-21 04:24:21,516 INFO L290 TraceCheckUtils]: 41: Hoare triple {14266#false} assume 1 == ~t1_pc~0; {14266#false} is VALID [2022-02-21 04:24:21,516 INFO L290 TraceCheckUtils]: 42: Hoare triple {14266#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {14266#false} is VALID [2022-02-21 04:24:21,516 INFO L290 TraceCheckUtils]: 43: Hoare triple {14266#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14266#false} is VALID [2022-02-21 04:24:21,517 INFO L290 TraceCheckUtils]: 44: Hoare triple {14266#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {14266#false} is VALID [2022-02-21 04:24:21,517 INFO L290 TraceCheckUtils]: 45: Hoare triple {14266#false} assume !(0 != activate_threads_~tmp___0~0#1); {14266#false} is VALID [2022-02-21 04:24:21,517 INFO L290 TraceCheckUtils]: 46: Hoare triple {14266#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14266#false} is VALID [2022-02-21 04:24:21,517 INFO L290 TraceCheckUtils]: 47: Hoare triple {14266#false} assume !(1 == ~t2_pc~0); {14266#false} is VALID [2022-02-21 04:24:21,517 INFO L290 TraceCheckUtils]: 48: Hoare triple {14266#false} is_transmit2_triggered_~__retres1~2#1 := 0; {14266#false} is VALID [2022-02-21 04:24:21,517 INFO L290 TraceCheckUtils]: 49: Hoare triple {14266#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14266#false} is VALID [2022-02-21 04:24:21,517 INFO L290 TraceCheckUtils]: 50: Hoare triple {14266#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {14266#false} is VALID [2022-02-21 04:24:21,517 INFO L290 TraceCheckUtils]: 51: Hoare triple {14266#false} assume !(0 != activate_threads_~tmp___1~0#1); {14266#false} is VALID [2022-02-21 04:24:21,517 INFO L290 TraceCheckUtils]: 52: Hoare triple {14266#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14266#false} is VALID [2022-02-21 04:24:21,518 INFO L290 TraceCheckUtils]: 53: Hoare triple {14266#false} assume 1 == ~t3_pc~0; {14266#false} is VALID [2022-02-21 04:24:21,518 INFO L290 TraceCheckUtils]: 54: Hoare triple {14266#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {14266#false} is VALID [2022-02-21 04:24:21,518 INFO L290 TraceCheckUtils]: 55: Hoare triple {14266#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14266#false} is VALID [2022-02-21 04:24:21,518 INFO L290 TraceCheckUtils]: 56: Hoare triple {14266#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {14266#false} is VALID [2022-02-21 04:24:21,518 INFO L290 TraceCheckUtils]: 57: Hoare triple {14266#false} assume !(0 != activate_threads_~tmp___2~0#1); {14266#false} is VALID [2022-02-21 04:24:21,518 INFO L290 TraceCheckUtils]: 58: Hoare triple {14266#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14266#false} is VALID [2022-02-21 04:24:21,518 INFO L290 TraceCheckUtils]: 59: Hoare triple {14266#false} assume 1 == ~t4_pc~0; {14266#false} is VALID [2022-02-21 04:24:21,518 INFO L290 TraceCheckUtils]: 60: Hoare triple {14266#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {14266#false} is VALID [2022-02-21 04:24:21,519 INFO L290 TraceCheckUtils]: 61: Hoare triple {14266#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14266#false} is VALID [2022-02-21 04:24:21,519 INFO L290 TraceCheckUtils]: 62: Hoare triple {14266#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {14266#false} is VALID [2022-02-21 04:24:21,519 INFO L290 TraceCheckUtils]: 63: Hoare triple {14266#false} assume !(0 != activate_threads_~tmp___3~0#1); {14266#false} is VALID [2022-02-21 04:24:21,519 INFO L290 TraceCheckUtils]: 64: Hoare triple {14266#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14266#false} is VALID [2022-02-21 04:24:21,519 INFO L290 TraceCheckUtils]: 65: Hoare triple {14266#false} assume !(1 == ~t5_pc~0); {14266#false} is VALID [2022-02-21 04:24:21,519 INFO L290 TraceCheckUtils]: 66: Hoare triple {14266#false} is_transmit5_triggered_~__retres1~5#1 := 0; {14266#false} is VALID [2022-02-21 04:24:21,519 INFO L290 TraceCheckUtils]: 67: Hoare triple {14266#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14266#false} is VALID [2022-02-21 04:24:21,519 INFO L290 TraceCheckUtils]: 68: Hoare triple {14266#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {14266#false} is VALID [2022-02-21 04:24:21,520 INFO L290 TraceCheckUtils]: 69: Hoare triple {14266#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {14266#false} is VALID [2022-02-21 04:24:21,520 INFO L290 TraceCheckUtils]: 70: Hoare triple {14266#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {14266#false} is VALID [2022-02-21 04:24:21,520 INFO L290 TraceCheckUtils]: 71: Hoare triple {14266#false} assume 1 == ~t6_pc~0; {14266#false} is VALID [2022-02-21 04:24:21,520 INFO L290 TraceCheckUtils]: 72: Hoare triple {14266#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {14266#false} is VALID [2022-02-21 04:24:21,520 INFO L290 TraceCheckUtils]: 73: Hoare triple {14266#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {14266#false} is VALID [2022-02-21 04:24:21,520 INFO L290 TraceCheckUtils]: 74: Hoare triple {14266#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {14266#false} is VALID [2022-02-21 04:24:21,520 INFO L290 TraceCheckUtils]: 75: Hoare triple {14266#false} assume !(0 != activate_threads_~tmp___5~0#1); {14266#false} is VALID [2022-02-21 04:24:21,520 INFO L290 TraceCheckUtils]: 76: Hoare triple {14266#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {14266#false} is VALID [2022-02-21 04:24:21,520 INFO L290 TraceCheckUtils]: 77: Hoare triple {14266#false} assume !(1 == ~t7_pc~0); {14266#false} is VALID [2022-02-21 04:24:21,521 INFO L290 TraceCheckUtils]: 78: Hoare triple {14266#false} is_transmit7_triggered_~__retres1~7#1 := 0; {14266#false} is VALID [2022-02-21 04:24:21,521 INFO L290 TraceCheckUtils]: 79: Hoare triple {14266#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {14266#false} is VALID [2022-02-21 04:24:21,521 INFO L290 TraceCheckUtils]: 80: Hoare triple {14266#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {14266#false} is VALID [2022-02-21 04:24:21,521 INFO L290 TraceCheckUtils]: 81: Hoare triple {14266#false} assume !(0 != activate_threads_~tmp___6~0#1); {14266#false} is VALID [2022-02-21 04:24:21,521 INFO L290 TraceCheckUtils]: 82: Hoare triple {14266#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {14266#false} is VALID [2022-02-21 04:24:21,521 INFO L290 TraceCheckUtils]: 83: Hoare triple {14266#false} assume 1 == ~t8_pc~0; {14266#false} is VALID [2022-02-21 04:24:21,521 INFO L290 TraceCheckUtils]: 84: Hoare triple {14266#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {14266#false} is VALID [2022-02-21 04:24:21,522 INFO L290 TraceCheckUtils]: 85: Hoare triple {14266#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {14266#false} is VALID [2022-02-21 04:24:21,522 INFO L290 TraceCheckUtils]: 86: Hoare triple {14266#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {14266#false} is VALID [2022-02-21 04:24:21,522 INFO L290 TraceCheckUtils]: 87: Hoare triple {14266#false} assume !(0 != activate_threads_~tmp___7~0#1); {14266#false} is VALID [2022-02-21 04:24:21,522 INFO L290 TraceCheckUtils]: 88: Hoare triple {14266#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {14266#false} is VALID [2022-02-21 04:24:21,522 INFO L290 TraceCheckUtils]: 89: Hoare triple {14266#false} assume !(1 == ~t9_pc~0); {14266#false} is VALID [2022-02-21 04:24:21,522 INFO L290 TraceCheckUtils]: 90: Hoare triple {14266#false} is_transmit9_triggered_~__retres1~9#1 := 0; {14266#false} is VALID [2022-02-21 04:24:21,522 INFO L290 TraceCheckUtils]: 91: Hoare triple {14266#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {14266#false} is VALID [2022-02-21 04:24:21,522 INFO L290 TraceCheckUtils]: 92: Hoare triple {14266#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {14266#false} is VALID [2022-02-21 04:24:21,522 INFO L290 TraceCheckUtils]: 93: Hoare triple {14266#false} assume !(0 != activate_threads_~tmp___8~0#1); {14266#false} is VALID [2022-02-21 04:24:21,523 INFO L290 TraceCheckUtils]: 94: Hoare triple {14266#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14266#false} is VALID [2022-02-21 04:24:21,523 INFO L290 TraceCheckUtils]: 95: Hoare triple {14266#false} assume !(1 == ~M_E~0); {14266#false} is VALID [2022-02-21 04:24:21,523 INFO L290 TraceCheckUtils]: 96: Hoare triple {14266#false} assume !(1 == ~T1_E~0); {14266#false} is VALID [2022-02-21 04:24:21,523 INFO L290 TraceCheckUtils]: 97: Hoare triple {14266#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {14266#false} is VALID [2022-02-21 04:24:21,524 INFO L290 TraceCheckUtils]: 98: Hoare triple {14266#false} assume !(1 == ~T3_E~0); {14266#false} is VALID [2022-02-21 04:24:21,524 INFO L290 TraceCheckUtils]: 99: Hoare triple {14266#false} assume !(1 == ~T4_E~0); {14266#false} is VALID [2022-02-21 04:24:21,524 INFO L290 TraceCheckUtils]: 100: Hoare triple {14266#false} assume !(1 == ~T5_E~0); {14266#false} is VALID [2022-02-21 04:24:21,524 INFO L290 TraceCheckUtils]: 101: Hoare triple {14266#false} assume !(1 == ~T6_E~0); {14266#false} is VALID [2022-02-21 04:24:21,524 INFO L290 TraceCheckUtils]: 102: Hoare triple {14266#false} assume !(1 == ~T7_E~0); {14266#false} is VALID [2022-02-21 04:24:21,524 INFO L290 TraceCheckUtils]: 103: Hoare triple {14266#false} assume !(1 == ~T8_E~0); {14266#false} is VALID [2022-02-21 04:24:21,524 INFO L290 TraceCheckUtils]: 104: Hoare triple {14266#false} assume !(1 == ~T9_E~0); {14266#false} is VALID [2022-02-21 04:24:21,524 INFO L290 TraceCheckUtils]: 105: Hoare triple {14266#false} assume 1 == ~E_1~0;~E_1~0 := 2; {14266#false} is VALID [2022-02-21 04:24:21,525 INFO L290 TraceCheckUtils]: 106: Hoare triple {14266#false} assume !(1 == ~E_2~0); {14266#false} is VALID [2022-02-21 04:24:21,525 INFO L290 TraceCheckUtils]: 107: Hoare triple {14266#false} assume !(1 == ~E_3~0); {14266#false} is VALID [2022-02-21 04:24:21,525 INFO L290 TraceCheckUtils]: 108: Hoare triple {14266#false} assume !(1 == ~E_4~0); {14266#false} is VALID [2022-02-21 04:24:21,525 INFO L290 TraceCheckUtils]: 109: Hoare triple {14266#false} assume !(1 == ~E_5~0); {14266#false} is VALID [2022-02-21 04:24:21,525 INFO L290 TraceCheckUtils]: 110: Hoare triple {14266#false} assume !(1 == ~E_6~0); {14266#false} is VALID [2022-02-21 04:24:21,525 INFO L290 TraceCheckUtils]: 111: Hoare triple {14266#false} assume !(1 == ~E_7~0); {14266#false} is VALID [2022-02-21 04:24:21,525 INFO L290 TraceCheckUtils]: 112: Hoare triple {14266#false} assume !(1 == ~E_8~0); {14266#false} is VALID [2022-02-21 04:24:21,529 INFO L290 TraceCheckUtils]: 113: Hoare triple {14266#false} assume 1 == ~E_9~0;~E_9~0 := 2; {14266#false} is VALID [2022-02-21 04:24:21,529 INFO L290 TraceCheckUtils]: 114: Hoare triple {14266#false} assume { :end_inline_reset_delta_events } true; {14266#false} is VALID [2022-02-21 04:24:21,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:21,529 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:21,530 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2004627299] [2022-02-21 04:24:21,530 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2004627299] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:21,530 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:21,530 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:21,530 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590387867] [2022-02-21 04:24:21,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:21,531 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:21,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:21,532 INFO L85 PathProgramCache]: Analyzing trace with hash -1113508429, now seen corresponding path program 1 times [2022-02-21 04:24:21,532 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:21,532 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033434703] [2022-02-21 04:24:21,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:21,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:21,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:21,586 INFO L290 TraceCheckUtils]: 0: Hoare triple {14268#true} assume !false; {14268#true} is VALID [2022-02-21 04:24:21,587 INFO L290 TraceCheckUtils]: 1: Hoare triple {14268#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {14268#true} is VALID [2022-02-21 04:24:21,587 INFO L290 TraceCheckUtils]: 2: Hoare triple {14268#true} assume !false; {14268#true} is VALID [2022-02-21 04:24:21,587 INFO L290 TraceCheckUtils]: 3: Hoare triple {14268#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {14268#true} is VALID [2022-02-21 04:24:21,593 INFO L290 TraceCheckUtils]: 4: Hoare triple {14268#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {14268#true} is VALID [2022-02-21 04:24:21,593 INFO L290 TraceCheckUtils]: 5: Hoare triple {14268#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {14268#true} is VALID [2022-02-21 04:24:21,593 INFO L290 TraceCheckUtils]: 6: Hoare triple {14268#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {14268#true} is VALID [2022-02-21 04:24:21,594 INFO L290 TraceCheckUtils]: 7: Hoare triple {14268#true} assume !(0 != eval_~tmp~0#1); {14268#true} is VALID [2022-02-21 04:24:21,594 INFO L290 TraceCheckUtils]: 8: Hoare triple {14268#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {14268#true} is VALID [2022-02-21 04:24:21,594 INFO L290 TraceCheckUtils]: 9: Hoare triple {14268#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {14268#true} is VALID [2022-02-21 04:24:21,594 INFO L290 TraceCheckUtils]: 10: Hoare triple {14268#true} assume 0 == ~M_E~0;~M_E~0 := 1; {14268#true} is VALID [2022-02-21 04:24:21,594 INFO L290 TraceCheckUtils]: 11: Hoare triple {14268#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {14268#true} is VALID [2022-02-21 04:24:21,594 INFO L290 TraceCheckUtils]: 12: Hoare triple {14268#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {14268#true} is VALID [2022-02-21 04:24:21,595 INFO L290 TraceCheckUtils]: 13: Hoare triple {14268#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,595 INFO L290 TraceCheckUtils]: 14: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,595 INFO L290 TraceCheckUtils]: 15: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T5_E~0); {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,596 INFO L290 TraceCheckUtils]: 16: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,596 INFO L290 TraceCheckUtils]: 17: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,596 INFO L290 TraceCheckUtils]: 18: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,596 INFO L290 TraceCheckUtils]: 19: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,597 INFO L290 TraceCheckUtils]: 20: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,597 INFO L290 TraceCheckUtils]: 21: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,597 INFO L290 TraceCheckUtils]: 22: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,598 INFO L290 TraceCheckUtils]: 23: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_4~0); {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,598 INFO L290 TraceCheckUtils]: 24: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,598 INFO L290 TraceCheckUtils]: 25: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,598 INFO L290 TraceCheckUtils]: 26: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,599 INFO L290 TraceCheckUtils]: 27: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,599 INFO L290 TraceCheckUtils]: 28: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,599 INFO L290 TraceCheckUtils]: 29: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,600 INFO L290 TraceCheckUtils]: 30: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~m_pc~0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,600 INFO L290 TraceCheckUtils]: 31: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,600 INFO L290 TraceCheckUtils]: 32: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,600 INFO L290 TraceCheckUtils]: 33: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,601 INFO L290 TraceCheckUtils]: 34: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,601 INFO L290 TraceCheckUtils]: 35: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,601 INFO L290 TraceCheckUtils]: 36: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t1_pc~0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,601 INFO L290 TraceCheckUtils]: 37: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,602 INFO L290 TraceCheckUtils]: 38: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,602 INFO L290 TraceCheckUtils]: 39: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,602 INFO L290 TraceCheckUtils]: 40: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,602 INFO L290 TraceCheckUtils]: 41: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,603 INFO L290 TraceCheckUtils]: 42: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t2_pc~0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,603 INFO L290 TraceCheckUtils]: 43: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,603 INFO L290 TraceCheckUtils]: 44: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,604 INFO L290 TraceCheckUtils]: 45: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,604 INFO L290 TraceCheckUtils]: 46: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,604 INFO L290 TraceCheckUtils]: 47: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,604 INFO L290 TraceCheckUtils]: 48: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t3_pc~0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,605 INFO L290 TraceCheckUtils]: 49: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,605 INFO L290 TraceCheckUtils]: 50: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,605 INFO L290 TraceCheckUtils]: 51: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,605 INFO L290 TraceCheckUtils]: 52: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,606 INFO L290 TraceCheckUtils]: 53: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,606 INFO L290 TraceCheckUtils]: 54: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t4_pc~0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,606 INFO L290 TraceCheckUtils]: 55: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,607 INFO L290 TraceCheckUtils]: 56: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,607 INFO L290 TraceCheckUtils]: 57: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,607 INFO L290 TraceCheckUtils]: 58: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,607 INFO L290 TraceCheckUtils]: 59: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,608 INFO L290 TraceCheckUtils]: 60: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t5_pc~0); {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,608 INFO L290 TraceCheckUtils]: 61: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,608 INFO L290 TraceCheckUtils]: 62: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,609 INFO L290 TraceCheckUtils]: 63: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,609 INFO L290 TraceCheckUtils]: 64: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,609 INFO L290 TraceCheckUtils]: 65: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,609 INFO L290 TraceCheckUtils]: 66: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t6_pc~0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,610 INFO L290 TraceCheckUtils]: 67: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,610 INFO L290 TraceCheckUtils]: 68: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,610 INFO L290 TraceCheckUtils]: 69: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,610 INFO L290 TraceCheckUtils]: 70: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,611 INFO L290 TraceCheckUtils]: 71: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,611 INFO L290 TraceCheckUtils]: 72: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t7_pc~0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,611 INFO L290 TraceCheckUtils]: 73: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,612 INFO L290 TraceCheckUtils]: 74: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,612 INFO L290 TraceCheckUtils]: 75: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,612 INFO L290 TraceCheckUtils]: 76: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,612 INFO L290 TraceCheckUtils]: 77: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,613 INFO L290 TraceCheckUtils]: 78: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t8_pc~0); {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,613 INFO L290 TraceCheckUtils]: 79: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,613 INFO L290 TraceCheckUtils]: 80: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,613 INFO L290 TraceCheckUtils]: 81: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,614 INFO L290 TraceCheckUtils]: 82: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,614 INFO L290 TraceCheckUtils]: 83: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,614 INFO L290 TraceCheckUtils]: 84: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t9_pc~0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,615 INFO L290 TraceCheckUtils]: 85: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,615 INFO L290 TraceCheckUtils]: 86: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,615 INFO L290 TraceCheckUtils]: 87: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,615 INFO L290 TraceCheckUtils]: 88: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,616 INFO L290 TraceCheckUtils]: 89: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,616 INFO L290 TraceCheckUtils]: 90: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,616 INFO L290 TraceCheckUtils]: 91: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,616 INFO L290 TraceCheckUtils]: 92: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {14270#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:21,617 INFO L290 TraceCheckUtils]: 93: Hoare triple {14270#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~T3_E~0); {14269#false} is VALID [2022-02-21 04:24:21,617 INFO L290 TraceCheckUtils]: 94: Hoare triple {14269#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,617 INFO L290 TraceCheckUtils]: 95: Hoare triple {14269#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,617 INFO L290 TraceCheckUtils]: 96: Hoare triple {14269#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,617 INFO L290 TraceCheckUtils]: 97: Hoare triple {14269#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,617 INFO L290 TraceCheckUtils]: 98: Hoare triple {14269#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,617 INFO L290 TraceCheckUtils]: 99: Hoare triple {14269#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,618 INFO L290 TraceCheckUtils]: 100: Hoare triple {14269#false} assume 1 == ~E_1~0;~E_1~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,618 INFO L290 TraceCheckUtils]: 101: Hoare triple {14269#false} assume !(1 == ~E_2~0); {14269#false} is VALID [2022-02-21 04:24:21,618 INFO L290 TraceCheckUtils]: 102: Hoare triple {14269#false} assume 1 == ~E_3~0;~E_3~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,618 INFO L290 TraceCheckUtils]: 103: Hoare triple {14269#false} assume 1 == ~E_4~0;~E_4~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,618 INFO L290 TraceCheckUtils]: 104: Hoare triple {14269#false} assume 1 == ~E_5~0;~E_5~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,618 INFO L290 TraceCheckUtils]: 105: Hoare triple {14269#false} assume 1 == ~E_6~0;~E_6~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,618 INFO L290 TraceCheckUtils]: 106: Hoare triple {14269#false} assume 1 == ~E_7~0;~E_7~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,618 INFO L290 TraceCheckUtils]: 107: Hoare triple {14269#false} assume 1 == ~E_8~0;~E_8~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,618 INFO L290 TraceCheckUtils]: 108: Hoare triple {14269#false} assume 1 == ~E_9~0;~E_9~0 := 2; {14269#false} is VALID [2022-02-21 04:24:21,619 INFO L290 TraceCheckUtils]: 109: Hoare triple {14269#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {14269#false} is VALID [2022-02-21 04:24:21,619 INFO L290 TraceCheckUtils]: 110: Hoare triple {14269#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {14269#false} is VALID [2022-02-21 04:24:21,619 INFO L290 TraceCheckUtils]: 111: Hoare triple {14269#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {14269#false} is VALID [2022-02-21 04:24:21,619 INFO L290 TraceCheckUtils]: 112: Hoare triple {14269#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {14269#false} is VALID [2022-02-21 04:24:21,619 INFO L290 TraceCheckUtils]: 113: Hoare triple {14269#false} assume !(0 == start_simulation_~tmp~3#1); {14269#false} is VALID [2022-02-21 04:24:21,619 INFO L290 TraceCheckUtils]: 114: Hoare triple {14269#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {14269#false} is VALID [2022-02-21 04:24:21,619 INFO L290 TraceCheckUtils]: 115: Hoare triple {14269#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {14269#false} is VALID [2022-02-21 04:24:21,619 INFO L290 TraceCheckUtils]: 116: Hoare triple {14269#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {14269#false} is VALID [2022-02-21 04:24:21,619 INFO L290 TraceCheckUtils]: 117: Hoare triple {14269#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {14269#false} is VALID [2022-02-21 04:24:21,620 INFO L290 TraceCheckUtils]: 118: Hoare triple {14269#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {14269#false} is VALID [2022-02-21 04:24:21,620 INFO L290 TraceCheckUtils]: 119: Hoare triple {14269#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {14269#false} is VALID [2022-02-21 04:24:21,620 INFO L290 TraceCheckUtils]: 120: Hoare triple {14269#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {14269#false} is VALID [2022-02-21 04:24:21,620 INFO L290 TraceCheckUtils]: 121: Hoare triple {14269#false} assume !(0 != start_simulation_~tmp___0~1#1); {14269#false} is VALID [2022-02-21 04:24:21,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:21,621 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:21,621 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2033434703] [2022-02-21 04:24:21,621 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2033434703] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:21,621 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:21,621 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:21,621 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885924785] [2022-02-21 04:24:21,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:21,622 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:21,622 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:21,622 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:21,622 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:21,623 INFO L87 Difference]: Start difference. First operand 1094 states and 1628 transitions. cyclomatic complexity: 535 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,427 INFO L93 Difference]: Finished difference Result 1094 states and 1627 transitions. [2022-02-21 04:24:22,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:22,428 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,499 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:22,500 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1627 transitions. [2022-02-21 04:24:22,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:22,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1627 transitions. [2022-02-21 04:24:22,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-02-21 04:24:22,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-02-21 04:24:22,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1627 transitions. [2022-02-21 04:24:22,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:22,568 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2022-02-21 04:24:22,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1627 transitions. [2022-02-21 04:24:22,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-02-21 04:24:22,578 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:22,580 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1094 states and 1627 transitions. Second operand has 1094 states, 1094 states have (on average 1.487202925045704) internal successors, (1627), 1093 states have internal predecessors, (1627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,581 INFO L74 IsIncluded]: Start isIncluded. First operand 1094 states and 1627 transitions. Second operand has 1094 states, 1094 states have (on average 1.487202925045704) internal successors, (1627), 1093 states have internal predecessors, (1627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,582 INFO L87 Difference]: Start difference. First operand 1094 states and 1627 transitions. Second operand has 1094 states, 1094 states have (on average 1.487202925045704) internal successors, (1627), 1093 states have internal predecessors, (1627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,613 INFO L93 Difference]: Finished difference Result 1094 states and 1627 transitions. [2022-02-21 04:24:22,613 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1627 transitions. [2022-02-21 04:24:22,614 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:22,614 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:22,617 INFO L74 IsIncluded]: Start isIncluded. First operand has 1094 states, 1094 states have (on average 1.487202925045704) internal successors, (1627), 1093 states have internal predecessors, (1627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1627 transitions. [2022-02-21 04:24:22,618 INFO L87 Difference]: Start difference. First operand has 1094 states, 1094 states have (on average 1.487202925045704) internal successors, (1627), 1093 states have internal predecessors, (1627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1627 transitions. [2022-02-21 04:24:22,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,652 INFO L93 Difference]: Finished difference Result 1094 states and 1627 transitions. [2022-02-21 04:24:22,652 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1627 transitions. [2022-02-21 04:24:22,653 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:22,653 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:22,654 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:22,654 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:22,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.487202925045704) internal successors, (1627), 1093 states have internal predecessors, (1627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1627 transitions. [2022-02-21 04:24:22,685 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2022-02-21 04:24:22,685 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1627 transitions. [2022-02-21 04:24:22,685 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:22,685 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1627 transitions. [2022-02-21 04:24:22,688 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:22,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:22,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:22,707 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,707 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,707 INFO L791 eck$LassoCheckResult]: Stem: 16202#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 16203#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 15803#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15804#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16350#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 16351#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16334#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16153#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16154#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15970#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15971#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16411#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16317#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16025#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15809#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15810#L922 assume !(0 == ~M_E~0); 16455#L922-2 assume !(0 == ~T1_E~0); 16456#L927-1 assume !(0 == ~T2_E~0); 16210#L932-1 assume !(0 == ~T3_E~0); 16095#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16096#L942-1 assume !(0 == ~T5_E~0); 16152#L947-1 assume !(0 == ~T6_E~0); 16214#L952-1 assume !(0 == ~T7_E~0); 16215#L957-1 assume !(0 == ~T8_E~0); 16278#L962-1 assume !(0 == ~T9_E~0); 16074#L967-1 assume !(0 == ~E_1~0); 16075#L972-1 assume !(0 == ~E_2~0); 16338#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16339#L982-1 assume !(0 == ~E_4~0); 15581#L987-1 assume !(0 == ~E_5~0); 15582#L992-1 assume !(0 == ~E_6~0); 15588#L997-1 assume !(0 == ~E_7~0); 16004#L1002-1 assume !(0 == ~E_8~0); 15990#L1007-1 assume !(0 == ~E_9~0); 15377#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15378#L443 assume !(1 == ~m_pc~0); 16230#L443-2 is_master_triggered_~__retres1~0#1 := 0; 16221#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16222#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15743#L1140 assume !(0 != activate_threads_~tmp~1#1); 15492#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15493#L462 assume 1 == ~t1_pc~0; 16121#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16091#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15463#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15464#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 15951#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15952#L481 assume !(1 == ~t2_pc~0); 15738#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15737#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16092#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15831#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 15832#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15926#L500 assume 1 == ~t3_pc~0; 16134#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16135#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16325#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16326#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 15382#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15383#L519 assume 1 == ~t4_pc~0; 15681#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15682#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15923#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15783#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 15784#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15546#L538 assume !(1 == ~t5_pc~0); 15547#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15453#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15454#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15722#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15723#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16260#L557 assume 1 == ~t6_pc~0; 16059#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15760#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15657#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15658#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 15785#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16438#L576 assume !(1 == ~t7_pc~0); 15747#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15748#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15992#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15993#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 16309#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15868#L595 assume 1 == ~t8_pc~0; 15869#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16327#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16328#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16177#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 16178#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15671#L614 assume !(1 == ~t9_pc~0); 15672#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15570#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15571#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15751#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 15833#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15834#L1025 assume !(1 == ~M_E~0); 16080#L1025-2 assume !(1 == ~T1_E~0); 16133#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16255#L1035-1 assume !(1 == ~T3_E~0); 15827#L1040-1 assume !(1 == ~T4_E~0); 15828#L1045-1 assume !(1 == ~T5_E~0); 15733#L1050-1 assume !(1 == ~T6_E~0); 15734#L1055-1 assume !(1 == ~T7_E~0); 15555#L1060-1 assume !(1 == ~T8_E~0); 15556#L1065-1 assume !(1 == ~T9_E~0); 15619#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16216#L1075-1 assume !(1 == ~E_2~0); 16217#L1080-1 assume !(1 == ~E_3~0); 16205#L1085-1 assume !(1 == ~E_4~0); 16206#L1090-1 assume !(1 == ~E_5~0); 16405#L1095-1 assume !(1 == ~E_6~0); 16239#L1100-1 assume !(1 == ~E_7~0); 16240#L1105-1 assume !(1 == ~E_8~0); 15528#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 15529#L1115-1 assume { :end_inline_reset_delta_events } true; 15692#L1396-2 [2022-02-21 04:24:22,708 INFO L793 eck$LassoCheckResult]: Loop: 15692#L1396-2 assume !false; 15773#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15802#L897 assume !false; 16445#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16352#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15400#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15401#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16400#L766 assume !(0 != eval_~tmp~0#1); 16386#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15470#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15471#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15984#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15714#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15715#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15893#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15520#L942-3 assume !(0 == ~T5_E~0); 15521#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15894#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15895#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16396#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16287#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16288#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16208#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16209#L982-3 assume !(0 == ~E_4~0); 16457#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15844#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15845#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15839#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15840#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15557#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15558#L443-30 assume 1 == ~m_pc~0; 15591#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15592#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15875#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16423#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16342#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15975#L462-30 assume 1 == ~t1_pc~0; 15819#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15821#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16322#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16323#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16364#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15962#L481-30 assume !(1 == ~t2_pc~0); 15680#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 15679#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15735#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15648#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15649#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15929#L500-30 assume 1 == ~t3_pc~0; 15686#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15687#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15749#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15750#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15912#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15913#L519-30 assume 1 == ~t4_pc~0; 16248#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16064#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15426#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15427#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16076#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16189#L538-30 assume !(1 == ~t5_pc~0); 15569#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 15568#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15866#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15867#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15644#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15645#L557-30 assume 1 == ~t6_pc~0; 15365#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15366#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16043#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16100#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 15669#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15670#L576-30 assume 1 == ~t7_pc~0; 16182#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15452#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16037#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16403#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15829#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15792#L595-30 assume !(1 == ~t8_pc~0); 15793#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 15728#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15461#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15462#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16404#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16440#L614-30 assume 1 == ~t9_pc~0; 15730#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15731#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15865#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15559#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15560#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16168#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15953#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15954#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16138#L1035-3 assume !(1 == ~T3_E~0); 16413#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16453#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16409#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16324#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15459#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15460#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16344#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16190#L1075-3 assume !(1 == ~E_2~0); 16191#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16414#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16335#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16336#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16355#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16356#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15607#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15608#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16369#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15476#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15468#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 15469#L1415 assume !(0 == start_simulation_~tmp~3#1); 16069#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16070#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15516#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 16078#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 16257#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16458#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16128#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 15691#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 15692#L1396-2 [2022-02-21 04:24:22,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:22,708 INFO L85 PathProgramCache]: Analyzing trace with hash -388791071, now seen corresponding path program 1 times [2022-02-21 04:24:22,709 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:22,709 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067434358] [2022-02-21 04:24:22,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:22,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:22,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:22,728 INFO L290 TraceCheckUtils]: 0: Hoare triple {18650#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {18650#true} is VALID [2022-02-21 04:24:22,728 INFO L290 TraceCheckUtils]: 1: Hoare triple {18650#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {18652#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:22,729 INFO L290 TraceCheckUtils]: 2: Hoare triple {18652#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {18652#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:22,729 INFO L290 TraceCheckUtils]: 3: Hoare triple {18652#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {18652#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:22,729 INFO L290 TraceCheckUtils]: 4: Hoare triple {18652#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {18652#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:22,729 INFO L290 TraceCheckUtils]: 5: Hoare triple {18652#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {18652#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:22,730 INFO L290 TraceCheckUtils]: 6: Hoare triple {18652#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {18652#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:22,730 INFO L290 TraceCheckUtils]: 7: Hoare triple {18652#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {18652#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:22,730 INFO L290 TraceCheckUtils]: 8: Hoare triple {18652#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {18652#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:22,731 INFO L290 TraceCheckUtils]: 9: Hoare triple {18652#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {18651#false} is VALID [2022-02-21 04:24:22,731 INFO L290 TraceCheckUtils]: 10: Hoare triple {18651#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {18651#false} is VALID [2022-02-21 04:24:22,731 INFO L290 TraceCheckUtils]: 11: Hoare triple {18651#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {18651#false} is VALID [2022-02-21 04:24:22,731 INFO L290 TraceCheckUtils]: 12: Hoare triple {18651#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {18651#false} is VALID [2022-02-21 04:24:22,731 INFO L290 TraceCheckUtils]: 13: Hoare triple {18651#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {18651#false} is VALID [2022-02-21 04:24:22,731 INFO L290 TraceCheckUtils]: 14: Hoare triple {18651#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {18651#false} is VALID [2022-02-21 04:24:22,731 INFO L290 TraceCheckUtils]: 15: Hoare triple {18651#false} assume !(0 == ~M_E~0); {18651#false} is VALID [2022-02-21 04:24:22,732 INFO L290 TraceCheckUtils]: 16: Hoare triple {18651#false} assume !(0 == ~T1_E~0); {18651#false} is VALID [2022-02-21 04:24:22,732 INFO L290 TraceCheckUtils]: 17: Hoare triple {18651#false} assume !(0 == ~T2_E~0); {18651#false} is VALID [2022-02-21 04:24:22,732 INFO L290 TraceCheckUtils]: 18: Hoare triple {18651#false} assume !(0 == ~T3_E~0); {18651#false} is VALID [2022-02-21 04:24:22,732 INFO L290 TraceCheckUtils]: 19: Hoare triple {18651#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {18651#false} is VALID [2022-02-21 04:24:22,732 INFO L290 TraceCheckUtils]: 20: Hoare triple {18651#false} assume !(0 == ~T5_E~0); {18651#false} is VALID [2022-02-21 04:24:22,732 INFO L290 TraceCheckUtils]: 21: Hoare triple {18651#false} assume !(0 == ~T6_E~0); {18651#false} is VALID [2022-02-21 04:24:22,732 INFO L290 TraceCheckUtils]: 22: Hoare triple {18651#false} assume !(0 == ~T7_E~0); {18651#false} is VALID [2022-02-21 04:24:22,732 INFO L290 TraceCheckUtils]: 23: Hoare triple {18651#false} assume !(0 == ~T8_E~0); {18651#false} is VALID [2022-02-21 04:24:22,733 INFO L290 TraceCheckUtils]: 24: Hoare triple {18651#false} assume !(0 == ~T9_E~0); {18651#false} is VALID [2022-02-21 04:24:22,733 INFO L290 TraceCheckUtils]: 25: Hoare triple {18651#false} assume !(0 == ~E_1~0); {18651#false} is VALID [2022-02-21 04:24:22,733 INFO L290 TraceCheckUtils]: 26: Hoare triple {18651#false} assume !(0 == ~E_2~0); {18651#false} is VALID [2022-02-21 04:24:22,733 INFO L290 TraceCheckUtils]: 27: Hoare triple {18651#false} assume 0 == ~E_3~0;~E_3~0 := 1; {18651#false} is VALID [2022-02-21 04:24:22,733 INFO L290 TraceCheckUtils]: 28: Hoare triple {18651#false} assume !(0 == ~E_4~0); {18651#false} is VALID [2022-02-21 04:24:22,733 INFO L290 TraceCheckUtils]: 29: Hoare triple {18651#false} assume !(0 == ~E_5~0); {18651#false} is VALID [2022-02-21 04:24:22,733 INFO L290 TraceCheckUtils]: 30: Hoare triple {18651#false} assume !(0 == ~E_6~0); {18651#false} is VALID [2022-02-21 04:24:22,733 INFO L290 TraceCheckUtils]: 31: Hoare triple {18651#false} assume !(0 == ~E_7~0); {18651#false} is VALID [2022-02-21 04:24:22,734 INFO L290 TraceCheckUtils]: 32: Hoare triple {18651#false} assume !(0 == ~E_8~0); {18651#false} is VALID [2022-02-21 04:24:22,734 INFO L290 TraceCheckUtils]: 33: Hoare triple {18651#false} assume !(0 == ~E_9~0); {18651#false} is VALID [2022-02-21 04:24:22,734 INFO L290 TraceCheckUtils]: 34: Hoare triple {18651#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18651#false} is VALID [2022-02-21 04:24:22,734 INFO L290 TraceCheckUtils]: 35: Hoare triple {18651#false} assume !(1 == ~m_pc~0); {18651#false} is VALID [2022-02-21 04:24:22,734 INFO L290 TraceCheckUtils]: 36: Hoare triple {18651#false} is_master_triggered_~__retres1~0#1 := 0; {18651#false} is VALID [2022-02-21 04:24:22,734 INFO L290 TraceCheckUtils]: 37: Hoare triple {18651#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18651#false} is VALID [2022-02-21 04:24:22,734 INFO L290 TraceCheckUtils]: 38: Hoare triple {18651#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {18651#false} is VALID [2022-02-21 04:24:22,734 INFO L290 TraceCheckUtils]: 39: Hoare triple {18651#false} assume !(0 != activate_threads_~tmp~1#1); {18651#false} is VALID [2022-02-21 04:24:22,735 INFO L290 TraceCheckUtils]: 40: Hoare triple {18651#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18651#false} is VALID [2022-02-21 04:24:22,735 INFO L290 TraceCheckUtils]: 41: Hoare triple {18651#false} assume 1 == ~t1_pc~0; {18651#false} is VALID [2022-02-21 04:24:22,735 INFO L290 TraceCheckUtils]: 42: Hoare triple {18651#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {18651#false} is VALID [2022-02-21 04:24:22,735 INFO L290 TraceCheckUtils]: 43: Hoare triple {18651#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18651#false} is VALID [2022-02-21 04:24:22,735 INFO L290 TraceCheckUtils]: 44: Hoare triple {18651#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {18651#false} is VALID [2022-02-21 04:24:22,735 INFO L290 TraceCheckUtils]: 45: Hoare triple {18651#false} assume !(0 != activate_threads_~tmp___0~0#1); {18651#false} is VALID [2022-02-21 04:24:22,735 INFO L290 TraceCheckUtils]: 46: Hoare triple {18651#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18651#false} is VALID [2022-02-21 04:24:22,735 INFO L290 TraceCheckUtils]: 47: Hoare triple {18651#false} assume !(1 == ~t2_pc~0); {18651#false} is VALID [2022-02-21 04:24:22,736 INFO L290 TraceCheckUtils]: 48: Hoare triple {18651#false} is_transmit2_triggered_~__retres1~2#1 := 0; {18651#false} is VALID [2022-02-21 04:24:22,736 INFO L290 TraceCheckUtils]: 49: Hoare triple {18651#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18651#false} is VALID [2022-02-21 04:24:22,736 INFO L290 TraceCheckUtils]: 50: Hoare triple {18651#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {18651#false} is VALID [2022-02-21 04:24:22,736 INFO L290 TraceCheckUtils]: 51: Hoare triple {18651#false} assume !(0 != activate_threads_~tmp___1~0#1); {18651#false} is VALID [2022-02-21 04:24:22,736 INFO L290 TraceCheckUtils]: 52: Hoare triple {18651#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18651#false} is VALID [2022-02-21 04:24:22,736 INFO L290 TraceCheckUtils]: 53: Hoare triple {18651#false} assume 1 == ~t3_pc~0; {18651#false} is VALID [2022-02-21 04:24:22,736 INFO L290 TraceCheckUtils]: 54: Hoare triple {18651#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {18651#false} is VALID [2022-02-21 04:24:22,736 INFO L290 TraceCheckUtils]: 55: Hoare triple {18651#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18651#false} is VALID [2022-02-21 04:24:22,737 INFO L290 TraceCheckUtils]: 56: Hoare triple {18651#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {18651#false} is VALID [2022-02-21 04:24:22,737 INFO L290 TraceCheckUtils]: 57: Hoare triple {18651#false} assume !(0 != activate_threads_~tmp___2~0#1); {18651#false} is VALID [2022-02-21 04:24:22,737 INFO L290 TraceCheckUtils]: 58: Hoare triple {18651#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {18651#false} is VALID [2022-02-21 04:24:22,737 INFO L290 TraceCheckUtils]: 59: Hoare triple {18651#false} assume 1 == ~t4_pc~0; {18651#false} is VALID [2022-02-21 04:24:22,737 INFO L290 TraceCheckUtils]: 60: Hoare triple {18651#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {18651#false} is VALID [2022-02-21 04:24:22,737 INFO L290 TraceCheckUtils]: 61: Hoare triple {18651#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {18651#false} is VALID [2022-02-21 04:24:22,737 INFO L290 TraceCheckUtils]: 62: Hoare triple {18651#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {18651#false} is VALID [2022-02-21 04:24:22,737 INFO L290 TraceCheckUtils]: 63: Hoare triple {18651#false} assume !(0 != activate_threads_~tmp___3~0#1); {18651#false} is VALID [2022-02-21 04:24:22,738 INFO L290 TraceCheckUtils]: 64: Hoare triple {18651#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {18651#false} is VALID [2022-02-21 04:24:22,738 INFO L290 TraceCheckUtils]: 65: Hoare triple {18651#false} assume !(1 == ~t5_pc~0); {18651#false} is VALID [2022-02-21 04:24:22,738 INFO L290 TraceCheckUtils]: 66: Hoare triple {18651#false} is_transmit5_triggered_~__retres1~5#1 := 0; {18651#false} is VALID [2022-02-21 04:24:22,738 INFO L290 TraceCheckUtils]: 67: Hoare triple {18651#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {18651#false} is VALID [2022-02-21 04:24:22,738 INFO L290 TraceCheckUtils]: 68: Hoare triple {18651#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {18651#false} is VALID [2022-02-21 04:24:22,738 INFO L290 TraceCheckUtils]: 69: Hoare triple {18651#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {18651#false} is VALID [2022-02-21 04:24:22,738 INFO L290 TraceCheckUtils]: 70: Hoare triple {18651#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {18651#false} is VALID [2022-02-21 04:24:22,738 INFO L290 TraceCheckUtils]: 71: Hoare triple {18651#false} assume 1 == ~t6_pc~0; {18651#false} is VALID [2022-02-21 04:24:22,739 INFO L290 TraceCheckUtils]: 72: Hoare triple {18651#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {18651#false} is VALID [2022-02-21 04:24:22,739 INFO L290 TraceCheckUtils]: 73: Hoare triple {18651#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {18651#false} is VALID [2022-02-21 04:24:22,739 INFO L290 TraceCheckUtils]: 74: Hoare triple {18651#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {18651#false} is VALID [2022-02-21 04:24:22,739 INFO L290 TraceCheckUtils]: 75: Hoare triple {18651#false} assume !(0 != activate_threads_~tmp___5~0#1); {18651#false} is VALID [2022-02-21 04:24:22,739 INFO L290 TraceCheckUtils]: 76: Hoare triple {18651#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {18651#false} is VALID [2022-02-21 04:24:22,739 INFO L290 TraceCheckUtils]: 77: Hoare triple {18651#false} assume !(1 == ~t7_pc~0); {18651#false} is VALID [2022-02-21 04:24:22,739 INFO L290 TraceCheckUtils]: 78: Hoare triple {18651#false} is_transmit7_triggered_~__retres1~7#1 := 0; {18651#false} is VALID [2022-02-21 04:24:22,740 INFO L290 TraceCheckUtils]: 79: Hoare triple {18651#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {18651#false} is VALID [2022-02-21 04:24:22,740 INFO L290 TraceCheckUtils]: 80: Hoare triple {18651#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {18651#false} is VALID [2022-02-21 04:24:22,740 INFO L290 TraceCheckUtils]: 81: Hoare triple {18651#false} assume !(0 != activate_threads_~tmp___6~0#1); {18651#false} is VALID [2022-02-21 04:24:22,740 INFO L290 TraceCheckUtils]: 82: Hoare triple {18651#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {18651#false} is VALID [2022-02-21 04:24:22,740 INFO L290 TraceCheckUtils]: 83: Hoare triple {18651#false} assume 1 == ~t8_pc~0; {18651#false} is VALID [2022-02-21 04:24:22,740 INFO L290 TraceCheckUtils]: 84: Hoare triple {18651#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {18651#false} is VALID [2022-02-21 04:24:22,740 INFO L290 TraceCheckUtils]: 85: Hoare triple {18651#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {18651#false} is VALID [2022-02-21 04:24:22,740 INFO L290 TraceCheckUtils]: 86: Hoare triple {18651#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {18651#false} is VALID [2022-02-21 04:24:22,741 INFO L290 TraceCheckUtils]: 87: Hoare triple {18651#false} assume !(0 != activate_threads_~tmp___7~0#1); {18651#false} is VALID [2022-02-21 04:24:22,741 INFO L290 TraceCheckUtils]: 88: Hoare triple {18651#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {18651#false} is VALID [2022-02-21 04:24:22,741 INFO L290 TraceCheckUtils]: 89: Hoare triple {18651#false} assume !(1 == ~t9_pc~0); {18651#false} is VALID [2022-02-21 04:24:22,741 INFO L290 TraceCheckUtils]: 90: Hoare triple {18651#false} is_transmit9_triggered_~__retres1~9#1 := 0; {18651#false} is VALID [2022-02-21 04:24:22,741 INFO L290 TraceCheckUtils]: 91: Hoare triple {18651#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {18651#false} is VALID [2022-02-21 04:24:22,741 INFO L290 TraceCheckUtils]: 92: Hoare triple {18651#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {18651#false} is VALID [2022-02-21 04:24:22,741 INFO L290 TraceCheckUtils]: 93: Hoare triple {18651#false} assume !(0 != activate_threads_~tmp___8~0#1); {18651#false} is VALID [2022-02-21 04:24:22,741 INFO L290 TraceCheckUtils]: 94: Hoare triple {18651#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18651#false} is VALID [2022-02-21 04:24:22,742 INFO L290 TraceCheckUtils]: 95: Hoare triple {18651#false} assume !(1 == ~M_E~0); {18651#false} is VALID [2022-02-21 04:24:22,742 INFO L290 TraceCheckUtils]: 96: Hoare triple {18651#false} assume !(1 == ~T1_E~0); {18651#false} is VALID [2022-02-21 04:24:22,742 INFO L290 TraceCheckUtils]: 97: Hoare triple {18651#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {18651#false} is VALID [2022-02-21 04:24:22,742 INFO L290 TraceCheckUtils]: 98: Hoare triple {18651#false} assume !(1 == ~T3_E~0); {18651#false} is VALID [2022-02-21 04:24:22,742 INFO L290 TraceCheckUtils]: 99: Hoare triple {18651#false} assume !(1 == ~T4_E~0); {18651#false} is VALID [2022-02-21 04:24:22,742 INFO L290 TraceCheckUtils]: 100: Hoare triple {18651#false} assume !(1 == ~T5_E~0); {18651#false} is VALID [2022-02-21 04:24:22,742 INFO L290 TraceCheckUtils]: 101: Hoare triple {18651#false} assume !(1 == ~T6_E~0); {18651#false} is VALID [2022-02-21 04:24:22,742 INFO L290 TraceCheckUtils]: 102: Hoare triple {18651#false} assume !(1 == ~T7_E~0); {18651#false} is VALID [2022-02-21 04:24:22,743 INFO L290 TraceCheckUtils]: 103: Hoare triple {18651#false} assume !(1 == ~T8_E~0); {18651#false} is VALID [2022-02-21 04:24:22,743 INFO L290 TraceCheckUtils]: 104: Hoare triple {18651#false} assume !(1 == ~T9_E~0); {18651#false} is VALID [2022-02-21 04:24:22,743 INFO L290 TraceCheckUtils]: 105: Hoare triple {18651#false} assume 1 == ~E_1~0;~E_1~0 := 2; {18651#false} is VALID [2022-02-21 04:24:22,743 INFO L290 TraceCheckUtils]: 106: Hoare triple {18651#false} assume !(1 == ~E_2~0); {18651#false} is VALID [2022-02-21 04:24:22,743 INFO L290 TraceCheckUtils]: 107: Hoare triple {18651#false} assume !(1 == ~E_3~0); {18651#false} is VALID [2022-02-21 04:24:22,743 INFO L290 TraceCheckUtils]: 108: Hoare triple {18651#false} assume !(1 == ~E_4~0); {18651#false} is VALID [2022-02-21 04:24:22,743 INFO L290 TraceCheckUtils]: 109: Hoare triple {18651#false} assume !(1 == ~E_5~0); {18651#false} is VALID [2022-02-21 04:24:22,743 INFO L290 TraceCheckUtils]: 110: Hoare triple {18651#false} assume !(1 == ~E_6~0); {18651#false} is VALID [2022-02-21 04:24:22,744 INFO L290 TraceCheckUtils]: 111: Hoare triple {18651#false} assume !(1 == ~E_7~0); {18651#false} is VALID [2022-02-21 04:24:22,744 INFO L290 TraceCheckUtils]: 112: Hoare triple {18651#false} assume !(1 == ~E_8~0); {18651#false} is VALID [2022-02-21 04:24:22,744 INFO L290 TraceCheckUtils]: 113: Hoare triple {18651#false} assume 1 == ~E_9~0;~E_9~0 := 2; {18651#false} is VALID [2022-02-21 04:24:22,744 INFO L290 TraceCheckUtils]: 114: Hoare triple {18651#false} assume { :end_inline_reset_delta_events } true; {18651#false} is VALID [2022-02-21 04:24:22,744 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:22,745 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:22,745 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067434358] [2022-02-21 04:24:22,745 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067434358] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:22,745 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:22,745 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:22,745 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714789964] [2022-02-21 04:24:22,745 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:22,746 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:22,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:22,746 INFO L85 PathProgramCache]: Analyzing trace with hash -96580526, now seen corresponding path program 1 times [2022-02-21 04:24:22,746 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:22,746 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108126118] [2022-02-21 04:24:22,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:22,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:22,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:22,773 INFO L290 TraceCheckUtils]: 0: Hoare triple {18653#true} assume !false; {18653#true} is VALID [2022-02-21 04:24:22,773 INFO L290 TraceCheckUtils]: 1: Hoare triple {18653#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {18653#true} is VALID [2022-02-21 04:24:22,773 INFO L290 TraceCheckUtils]: 2: Hoare triple {18653#true} assume !false; {18653#true} is VALID [2022-02-21 04:24:22,773 INFO L290 TraceCheckUtils]: 3: Hoare triple {18653#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {18653#true} is VALID [2022-02-21 04:24:22,773 INFO L290 TraceCheckUtils]: 4: Hoare triple {18653#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {18653#true} is VALID [2022-02-21 04:24:22,774 INFO L290 TraceCheckUtils]: 5: Hoare triple {18653#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {18653#true} is VALID [2022-02-21 04:24:22,774 INFO L290 TraceCheckUtils]: 6: Hoare triple {18653#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {18653#true} is VALID [2022-02-21 04:24:22,774 INFO L290 TraceCheckUtils]: 7: Hoare triple {18653#true} assume !(0 != eval_~tmp~0#1); {18653#true} is VALID [2022-02-21 04:24:22,774 INFO L290 TraceCheckUtils]: 8: Hoare triple {18653#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {18653#true} is VALID [2022-02-21 04:24:22,774 INFO L290 TraceCheckUtils]: 9: Hoare triple {18653#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {18653#true} is VALID [2022-02-21 04:24:22,774 INFO L290 TraceCheckUtils]: 10: Hoare triple {18653#true} assume 0 == ~M_E~0;~M_E~0 := 1; {18653#true} is VALID [2022-02-21 04:24:22,774 INFO L290 TraceCheckUtils]: 11: Hoare triple {18653#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {18653#true} is VALID [2022-02-21 04:24:22,774 INFO L290 TraceCheckUtils]: 12: Hoare triple {18653#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {18653#true} is VALID [2022-02-21 04:24:22,775 INFO L290 TraceCheckUtils]: 13: Hoare triple {18653#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,775 INFO L290 TraceCheckUtils]: 14: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,775 INFO L290 TraceCheckUtils]: 15: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T5_E~0); {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,776 INFO L290 TraceCheckUtils]: 16: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,776 INFO L290 TraceCheckUtils]: 17: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,776 INFO L290 TraceCheckUtils]: 18: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,776 INFO L290 TraceCheckUtils]: 19: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,777 INFO L290 TraceCheckUtils]: 20: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,777 INFO L290 TraceCheckUtils]: 21: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,777 INFO L290 TraceCheckUtils]: 22: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,778 INFO L290 TraceCheckUtils]: 23: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_4~0); {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,778 INFO L290 TraceCheckUtils]: 24: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,778 INFO L290 TraceCheckUtils]: 25: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,778 INFO L290 TraceCheckUtils]: 26: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,779 INFO L290 TraceCheckUtils]: 27: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,779 INFO L290 TraceCheckUtils]: 28: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,779 INFO L290 TraceCheckUtils]: 29: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,780 INFO L290 TraceCheckUtils]: 30: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~m_pc~0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,780 INFO L290 TraceCheckUtils]: 31: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,780 INFO L290 TraceCheckUtils]: 32: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,780 INFO L290 TraceCheckUtils]: 33: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,781 INFO L290 TraceCheckUtils]: 34: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,781 INFO L290 TraceCheckUtils]: 35: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,781 INFO L290 TraceCheckUtils]: 36: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t1_pc~0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,781 INFO L290 TraceCheckUtils]: 37: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,782 INFO L290 TraceCheckUtils]: 38: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,782 INFO L290 TraceCheckUtils]: 39: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,782 INFO L290 TraceCheckUtils]: 40: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,783 INFO L290 TraceCheckUtils]: 41: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,783 INFO L290 TraceCheckUtils]: 42: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t2_pc~0); {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,783 INFO L290 TraceCheckUtils]: 43: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,783 INFO L290 TraceCheckUtils]: 44: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,784 INFO L290 TraceCheckUtils]: 45: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,784 INFO L290 TraceCheckUtils]: 46: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,784 INFO L290 TraceCheckUtils]: 47: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,784 INFO L290 TraceCheckUtils]: 48: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t3_pc~0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,785 INFO L290 TraceCheckUtils]: 49: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,785 INFO L290 TraceCheckUtils]: 50: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,785 INFO L290 TraceCheckUtils]: 51: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,786 INFO L290 TraceCheckUtils]: 52: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,786 INFO L290 TraceCheckUtils]: 53: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,786 INFO L290 TraceCheckUtils]: 54: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t4_pc~0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,786 INFO L290 TraceCheckUtils]: 55: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,787 INFO L290 TraceCheckUtils]: 56: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,787 INFO L290 TraceCheckUtils]: 57: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,787 INFO L290 TraceCheckUtils]: 58: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,788 INFO L290 TraceCheckUtils]: 59: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,788 INFO L290 TraceCheckUtils]: 60: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t5_pc~0); {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,788 INFO L290 TraceCheckUtils]: 61: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,788 INFO L290 TraceCheckUtils]: 62: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,789 INFO L290 TraceCheckUtils]: 63: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,789 INFO L290 TraceCheckUtils]: 64: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,789 INFO L290 TraceCheckUtils]: 65: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,789 INFO L290 TraceCheckUtils]: 66: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t6_pc~0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,790 INFO L290 TraceCheckUtils]: 67: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,790 INFO L290 TraceCheckUtils]: 68: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,790 INFO L290 TraceCheckUtils]: 69: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,791 INFO L290 TraceCheckUtils]: 70: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,791 INFO L290 TraceCheckUtils]: 71: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,791 INFO L290 TraceCheckUtils]: 72: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t7_pc~0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,791 INFO L290 TraceCheckUtils]: 73: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,792 INFO L290 TraceCheckUtils]: 74: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,792 INFO L290 TraceCheckUtils]: 75: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,792 INFO L290 TraceCheckUtils]: 76: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,792 INFO L290 TraceCheckUtils]: 77: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,793 INFO L290 TraceCheckUtils]: 78: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t8_pc~0); {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,793 INFO L290 TraceCheckUtils]: 79: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,793 INFO L290 TraceCheckUtils]: 80: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,794 INFO L290 TraceCheckUtils]: 81: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,794 INFO L290 TraceCheckUtils]: 82: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,794 INFO L290 TraceCheckUtils]: 83: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,794 INFO L290 TraceCheckUtils]: 84: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t9_pc~0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,795 INFO L290 TraceCheckUtils]: 85: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,795 INFO L290 TraceCheckUtils]: 86: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,795 INFO L290 TraceCheckUtils]: 87: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,795 INFO L290 TraceCheckUtils]: 88: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,796 INFO L290 TraceCheckUtils]: 89: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,796 INFO L290 TraceCheckUtils]: 90: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,796 INFO L290 TraceCheckUtils]: 91: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,797 INFO L290 TraceCheckUtils]: 92: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {18655#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:22,797 INFO L290 TraceCheckUtils]: 93: Hoare triple {18655#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~T3_E~0); {18654#false} is VALID [2022-02-21 04:24:22,797 INFO L290 TraceCheckUtils]: 94: Hoare triple {18654#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,797 INFO L290 TraceCheckUtils]: 95: Hoare triple {18654#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,797 INFO L290 TraceCheckUtils]: 96: Hoare triple {18654#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,797 INFO L290 TraceCheckUtils]: 97: Hoare triple {18654#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,797 INFO L290 TraceCheckUtils]: 98: Hoare triple {18654#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,798 INFO L290 TraceCheckUtils]: 99: Hoare triple {18654#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,798 INFO L290 TraceCheckUtils]: 100: Hoare triple {18654#false} assume 1 == ~E_1~0;~E_1~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,798 INFO L290 TraceCheckUtils]: 101: Hoare triple {18654#false} assume !(1 == ~E_2~0); {18654#false} is VALID [2022-02-21 04:24:22,798 INFO L290 TraceCheckUtils]: 102: Hoare triple {18654#false} assume 1 == ~E_3~0;~E_3~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,798 INFO L290 TraceCheckUtils]: 103: Hoare triple {18654#false} assume 1 == ~E_4~0;~E_4~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,798 INFO L290 TraceCheckUtils]: 104: Hoare triple {18654#false} assume 1 == ~E_5~0;~E_5~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,798 INFO L290 TraceCheckUtils]: 105: Hoare triple {18654#false} assume 1 == ~E_6~0;~E_6~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,798 INFO L290 TraceCheckUtils]: 106: Hoare triple {18654#false} assume 1 == ~E_7~0;~E_7~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,799 INFO L290 TraceCheckUtils]: 107: Hoare triple {18654#false} assume 1 == ~E_8~0;~E_8~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,799 INFO L290 TraceCheckUtils]: 108: Hoare triple {18654#false} assume 1 == ~E_9~0;~E_9~0 := 2; {18654#false} is VALID [2022-02-21 04:24:22,799 INFO L290 TraceCheckUtils]: 109: Hoare triple {18654#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {18654#false} is VALID [2022-02-21 04:24:22,799 INFO L290 TraceCheckUtils]: 110: Hoare triple {18654#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {18654#false} is VALID [2022-02-21 04:24:22,799 INFO L290 TraceCheckUtils]: 111: Hoare triple {18654#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {18654#false} is VALID [2022-02-21 04:24:22,799 INFO L290 TraceCheckUtils]: 112: Hoare triple {18654#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {18654#false} is VALID [2022-02-21 04:24:22,799 INFO L290 TraceCheckUtils]: 113: Hoare triple {18654#false} assume !(0 == start_simulation_~tmp~3#1); {18654#false} is VALID [2022-02-21 04:24:22,800 INFO L290 TraceCheckUtils]: 114: Hoare triple {18654#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {18654#false} is VALID [2022-02-21 04:24:22,800 INFO L290 TraceCheckUtils]: 115: Hoare triple {18654#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {18654#false} is VALID [2022-02-21 04:24:22,800 INFO L290 TraceCheckUtils]: 116: Hoare triple {18654#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {18654#false} is VALID [2022-02-21 04:24:22,800 INFO L290 TraceCheckUtils]: 117: Hoare triple {18654#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {18654#false} is VALID [2022-02-21 04:24:22,800 INFO L290 TraceCheckUtils]: 118: Hoare triple {18654#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {18654#false} is VALID [2022-02-21 04:24:22,800 INFO L290 TraceCheckUtils]: 119: Hoare triple {18654#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {18654#false} is VALID [2022-02-21 04:24:22,800 INFO L290 TraceCheckUtils]: 120: Hoare triple {18654#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {18654#false} is VALID [2022-02-21 04:24:22,800 INFO L290 TraceCheckUtils]: 121: Hoare triple {18654#false} assume !(0 != start_simulation_~tmp___0~1#1); {18654#false} is VALID [2022-02-21 04:24:22,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:22,801 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:22,801 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [108126118] [2022-02-21 04:24:22,801 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [108126118] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:22,802 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:22,802 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:22,802 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [578260302] [2022-02-21 04:24:22,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:22,802 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:22,802 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:22,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:22,803 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:22,804 INFO L87 Difference]: Start difference. First operand 1094 states and 1627 transitions. cyclomatic complexity: 534 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,722 INFO L93 Difference]: Finished difference Result 1094 states and 1626 transitions. [2022-02-21 04:24:23,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:23,722 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,785 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:23,787 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1626 transitions. [2022-02-21 04:24:23,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:23,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1626 transitions. [2022-02-21 04:24:23,851 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-02-21 04:24:23,851 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-02-21 04:24:23,852 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1626 transitions. [2022-02-21 04:24:23,853 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:23,853 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2022-02-21 04:24:23,854 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1626 transitions. [2022-02-21 04:24:23,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-02-21 04:24:23,864 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:23,866 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1094 states and 1626 transitions. Second operand has 1094 states, 1094 states have (on average 1.4862888482632541) internal successors, (1626), 1093 states have internal predecessors, (1626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,868 INFO L74 IsIncluded]: Start isIncluded. First operand 1094 states and 1626 transitions. Second operand has 1094 states, 1094 states have (on average 1.4862888482632541) internal successors, (1626), 1093 states have internal predecessors, (1626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,869 INFO L87 Difference]: Start difference. First operand 1094 states and 1626 transitions. Second operand has 1094 states, 1094 states have (on average 1.4862888482632541) internal successors, (1626), 1093 states have internal predecessors, (1626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,901 INFO L93 Difference]: Finished difference Result 1094 states and 1626 transitions. [2022-02-21 04:24:23,901 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1626 transitions. [2022-02-21 04:24:23,902 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:23,902 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:23,904 INFO L74 IsIncluded]: Start isIncluded. First operand has 1094 states, 1094 states have (on average 1.4862888482632541) internal successors, (1626), 1093 states have internal predecessors, (1626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1626 transitions. [2022-02-21 04:24:23,905 INFO L87 Difference]: Start difference. First operand has 1094 states, 1094 states have (on average 1.4862888482632541) internal successors, (1626), 1093 states have internal predecessors, (1626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1626 transitions. [2022-02-21 04:24:23,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,941 INFO L93 Difference]: Finished difference Result 1094 states and 1626 transitions. [2022-02-21 04:24:23,941 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1626 transitions. [2022-02-21 04:24:23,943 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:23,943 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:23,943 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:23,943 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:23,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4862888482632541) internal successors, (1626), 1093 states have internal predecessors, (1626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1626 transitions. [2022-02-21 04:24:23,979 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2022-02-21 04:24:23,980 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1626 transitions. [2022-02-21 04:24:23,980 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:23,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1626 transitions. [2022-02-21 04:24:23,983 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:23,983 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:23,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:23,984 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,985 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,985 INFO L791 eck$LassoCheckResult]: Stem: 20586#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 20587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 20188#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20189#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20735#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 20736#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20718#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20538#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20539#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20354#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20355#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20795#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20701#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20410#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20194#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20195#L922 assume !(0 == ~M_E~0); 20840#L922-2 assume !(0 == ~T1_E~0); 20841#L927-1 assume !(0 == ~T2_E~0); 20595#L932-1 assume !(0 == ~T3_E~0); 20480#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20481#L942-1 assume !(0 == ~T5_E~0); 20537#L947-1 assume !(0 == ~T6_E~0); 20599#L952-1 assume !(0 == ~T7_E~0); 20600#L957-1 assume !(0 == ~T8_E~0); 20660#L962-1 assume !(0 == ~T9_E~0); 20456#L967-1 assume !(0 == ~E_1~0); 20457#L972-1 assume !(0 == ~E_2~0); 20723#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20724#L982-1 assume !(0 == ~E_4~0); 19964#L987-1 assume !(0 == ~E_5~0); 19965#L992-1 assume !(0 == ~E_6~0); 19973#L997-1 assume !(0 == ~E_7~0); 20387#L1002-1 assume !(0 == ~E_8~0); 20374#L1007-1 assume !(0 == ~E_9~0); 19762#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19763#L443 assume !(1 == ~m_pc~0); 20615#L443-2 is_master_triggered_~__retres1~0#1 := 0; 20606#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20607#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20128#L1140 assume !(0 != activate_threads_~tmp~1#1); 19877#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19878#L462 assume 1 == ~t1_pc~0; 20506#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20473#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19848#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19849#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 20335#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20336#L481 assume !(1 == ~t2_pc~0); 20123#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20122#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20477#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20216#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 20217#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20309#L500 assume 1 == ~t3_pc~0; 20519#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20520#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20710#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20711#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 19764#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19765#L519 assume 1 == ~t4_pc~0; 20063#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20064#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20308#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20168#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 20169#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19931#L538 assume !(1 == ~t5_pc~0); 19932#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 19838#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19839#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20107#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20108#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20645#L557 assume 1 == ~t6_pc~0; 20444#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20145#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20042#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20043#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 20170#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20823#L576 assume !(1 == ~t7_pc~0); 20132#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20133#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20377#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20378#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 20694#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20253#L595 assume 1 == ~t8_pc~0; 20254#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20712#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20713#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20562#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 20563#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20056#L614 assume !(1 == ~t9_pc~0); 20057#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 19955#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19956#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20136#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 20218#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20219#L1025 assume !(1 == ~M_E~0); 20465#L1025-2 assume !(1 == ~T1_E~0); 20518#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20640#L1035-1 assume !(1 == ~T3_E~0); 20212#L1040-1 assume !(1 == ~T4_E~0); 20213#L1045-1 assume !(1 == ~T5_E~0); 20118#L1050-1 assume !(1 == ~T6_E~0); 20119#L1055-1 assume !(1 == ~T7_E~0); 19940#L1060-1 assume !(1 == ~T8_E~0); 19941#L1065-1 assume !(1 == ~T9_E~0); 20004#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20601#L1075-1 assume !(1 == ~E_2~0); 20602#L1080-1 assume !(1 == ~E_3~0); 20590#L1085-1 assume !(1 == ~E_4~0); 20591#L1090-1 assume !(1 == ~E_5~0); 20790#L1095-1 assume !(1 == ~E_6~0); 20624#L1100-1 assume !(1 == ~E_7~0); 20625#L1105-1 assume !(1 == ~E_8~0); 19913#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 19914#L1115-1 assume { :end_inline_reset_delta_events } true; 20077#L1396-2 [2022-02-21 04:24:23,985 INFO L793 eck$LassoCheckResult]: Loop: 20077#L1396-2 assume !false; 20158#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20187#L897 assume !false; 20830#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20737#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19785#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19786#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20785#L766 assume !(0 != eval_~tmp~0#1); 20771#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19855#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19856#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20369#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20099#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20100#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20278#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19905#L942-3 assume !(0 == ~T5_E~0); 19906#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20279#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20280#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20781#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20672#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20673#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20593#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20594#L982-3 assume !(0 == ~E_4~0); 20842#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20229#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20230#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20224#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20225#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19942#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19943#L443-30 assume 1 == ~m_pc~0; 19976#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19977#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20260#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20808#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20727#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20360#L462-30 assume 1 == ~t1_pc~0; 20204#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20206#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20707#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20708#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20749#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20347#L481-30 assume 1 == ~t2_pc~0; 20066#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20067#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20120#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20033#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20034#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20314#L500-30 assume 1 == ~t3_pc~0; 20071#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20072#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20134#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20135#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20297#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20298#L519-30 assume 1 == ~t4_pc~0; 20633#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20449#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19811#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19812#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20461#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20574#L538-30 assume 1 == ~t5_pc~0; 19952#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19953#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20251#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20252#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20029#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20030#L557-30 assume 1 == ~t6_pc~0; 19750#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19751#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20428#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20485#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 20054#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20055#L576-30 assume 1 == ~t7_pc~0; 20567#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19837#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20422#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20788#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20214#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20177#L595-30 assume !(1 == ~t8_pc~0); 20178#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 20113#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19846#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19847#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20789#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20825#L614-30 assume 1 == ~t9_pc~0; 20115#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20116#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20250#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19944#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19945#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20553#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20338#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20339#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20523#L1035-3 assume !(1 == ~T3_E~0); 20798#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20838#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20794#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20709#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19844#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19845#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 20729#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20575#L1075-3 assume !(1 == ~E_2~0); 20576#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20799#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20720#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20721#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20740#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20741#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19992#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19993#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20754#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19861#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 19853#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 19854#L1415 assume !(0 == start_simulation_~tmp~3#1); 20454#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20455#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19901#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 20463#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 20642#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20843#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20513#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 20076#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 20077#L1396-2 [2022-02-21 04:24:23,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:23,986 INFO L85 PathProgramCache]: Analyzing trace with hash 234490531, now seen corresponding path program 1 times [2022-02-21 04:24:23,986 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:23,986 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1732116685] [2022-02-21 04:24:23,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:23,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:23,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,009 INFO L290 TraceCheckUtils]: 0: Hoare triple {23035#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {23035#true} is VALID [2022-02-21 04:24:24,010 INFO L290 TraceCheckUtils]: 1: Hoare triple {23035#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {23037#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:24,010 INFO L290 TraceCheckUtils]: 2: Hoare triple {23037#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {23037#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:24,010 INFO L290 TraceCheckUtils]: 3: Hoare triple {23037#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {23037#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:24,010 INFO L290 TraceCheckUtils]: 4: Hoare triple {23037#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {23037#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:24,011 INFO L290 TraceCheckUtils]: 5: Hoare triple {23037#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {23037#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:24,011 INFO L290 TraceCheckUtils]: 6: Hoare triple {23037#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {23037#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:24,036 INFO L290 TraceCheckUtils]: 7: Hoare triple {23037#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {23037#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:24,036 INFO L290 TraceCheckUtils]: 8: Hoare triple {23037#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {23037#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:24,037 INFO L290 TraceCheckUtils]: 9: Hoare triple {23037#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {23037#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:24,037 INFO L290 TraceCheckUtils]: 10: Hoare triple {23037#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {23036#false} is VALID [2022-02-21 04:24:24,037 INFO L290 TraceCheckUtils]: 11: Hoare triple {23036#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {23036#false} is VALID [2022-02-21 04:24:24,037 INFO L290 TraceCheckUtils]: 12: Hoare triple {23036#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {23036#false} is VALID [2022-02-21 04:24:24,037 INFO L290 TraceCheckUtils]: 13: Hoare triple {23036#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {23036#false} is VALID [2022-02-21 04:24:24,037 INFO L290 TraceCheckUtils]: 14: Hoare triple {23036#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {23036#false} is VALID [2022-02-21 04:24:24,037 INFO L290 TraceCheckUtils]: 15: Hoare triple {23036#false} assume !(0 == ~M_E~0); {23036#false} is VALID [2022-02-21 04:24:24,037 INFO L290 TraceCheckUtils]: 16: Hoare triple {23036#false} assume !(0 == ~T1_E~0); {23036#false} is VALID [2022-02-21 04:24:24,037 INFO L290 TraceCheckUtils]: 17: Hoare triple {23036#false} assume !(0 == ~T2_E~0); {23036#false} is VALID [2022-02-21 04:24:24,037 INFO L290 TraceCheckUtils]: 18: Hoare triple {23036#false} assume !(0 == ~T3_E~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 19: Hoare triple {23036#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 20: Hoare triple {23036#false} assume !(0 == ~T5_E~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 21: Hoare triple {23036#false} assume !(0 == ~T6_E~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 22: Hoare triple {23036#false} assume !(0 == ~T7_E~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 23: Hoare triple {23036#false} assume !(0 == ~T8_E~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 24: Hoare triple {23036#false} assume !(0 == ~T9_E~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 25: Hoare triple {23036#false} assume !(0 == ~E_1~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 26: Hoare triple {23036#false} assume !(0 == ~E_2~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 27: Hoare triple {23036#false} assume 0 == ~E_3~0;~E_3~0 := 1; {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 28: Hoare triple {23036#false} assume !(0 == ~E_4~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 29: Hoare triple {23036#false} assume !(0 == ~E_5~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 30: Hoare triple {23036#false} assume !(0 == ~E_6~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 31: Hoare triple {23036#false} assume !(0 == ~E_7~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 32: Hoare triple {23036#false} assume !(0 == ~E_8~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 33: Hoare triple {23036#false} assume !(0 == ~E_9~0); {23036#false} is VALID [2022-02-21 04:24:24,038 INFO L290 TraceCheckUtils]: 34: Hoare triple {23036#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 35: Hoare triple {23036#false} assume !(1 == ~m_pc~0); {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 36: Hoare triple {23036#false} is_master_triggered_~__retres1~0#1 := 0; {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 37: Hoare triple {23036#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 38: Hoare triple {23036#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 39: Hoare triple {23036#false} assume !(0 != activate_threads_~tmp~1#1); {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 40: Hoare triple {23036#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 41: Hoare triple {23036#false} assume 1 == ~t1_pc~0; {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 42: Hoare triple {23036#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 43: Hoare triple {23036#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 44: Hoare triple {23036#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 45: Hoare triple {23036#false} assume !(0 != activate_threads_~tmp___0~0#1); {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 46: Hoare triple {23036#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23036#false} is VALID [2022-02-21 04:24:24,039 INFO L290 TraceCheckUtils]: 47: Hoare triple {23036#false} assume !(1 == ~t2_pc~0); {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 48: Hoare triple {23036#false} is_transmit2_triggered_~__retres1~2#1 := 0; {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 49: Hoare triple {23036#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 50: Hoare triple {23036#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 51: Hoare triple {23036#false} assume !(0 != activate_threads_~tmp___1~0#1); {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 52: Hoare triple {23036#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 53: Hoare triple {23036#false} assume 1 == ~t3_pc~0; {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 54: Hoare triple {23036#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 55: Hoare triple {23036#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 56: Hoare triple {23036#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 57: Hoare triple {23036#false} assume !(0 != activate_threads_~tmp___2~0#1); {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 58: Hoare triple {23036#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23036#false} is VALID [2022-02-21 04:24:24,040 INFO L290 TraceCheckUtils]: 59: Hoare triple {23036#false} assume 1 == ~t4_pc~0; {23036#false} is VALID [2022-02-21 04:24:24,041 INFO L290 TraceCheckUtils]: 60: Hoare triple {23036#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {23036#false} is VALID [2022-02-21 04:24:24,041 INFO L290 TraceCheckUtils]: 61: Hoare triple {23036#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23036#false} is VALID [2022-02-21 04:24:24,041 INFO L290 TraceCheckUtils]: 62: Hoare triple {23036#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {23036#false} is VALID [2022-02-21 04:24:24,041 INFO L290 TraceCheckUtils]: 63: Hoare triple {23036#false} assume !(0 != activate_threads_~tmp___3~0#1); {23036#false} is VALID [2022-02-21 04:24:24,041 INFO L290 TraceCheckUtils]: 64: Hoare triple {23036#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23036#false} is VALID [2022-02-21 04:24:24,041 INFO L290 TraceCheckUtils]: 65: Hoare triple {23036#false} assume !(1 == ~t5_pc~0); {23036#false} is VALID [2022-02-21 04:24:24,041 INFO L290 TraceCheckUtils]: 66: Hoare triple {23036#false} is_transmit5_triggered_~__retres1~5#1 := 0; {23036#false} is VALID [2022-02-21 04:24:24,041 INFO L290 TraceCheckUtils]: 67: Hoare triple {23036#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 68: Hoare triple {23036#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 69: Hoare triple {23036#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 70: Hoare triple {23036#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 71: Hoare triple {23036#false} assume 1 == ~t6_pc~0; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 72: Hoare triple {23036#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 73: Hoare triple {23036#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 74: Hoare triple {23036#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 75: Hoare triple {23036#false} assume !(0 != activate_threads_~tmp___5~0#1); {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 76: Hoare triple {23036#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 77: Hoare triple {23036#false} assume !(1 == ~t7_pc~0); {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 78: Hoare triple {23036#false} is_transmit7_triggered_~__retres1~7#1 := 0; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 79: Hoare triple {23036#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 80: Hoare triple {23036#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 81: Hoare triple {23036#false} assume !(0 != activate_threads_~tmp___6~0#1); {23036#false} is VALID [2022-02-21 04:24:24,043 INFO L290 TraceCheckUtils]: 82: Hoare triple {23036#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 83: Hoare triple {23036#false} assume 1 == ~t8_pc~0; {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 84: Hoare triple {23036#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 85: Hoare triple {23036#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 86: Hoare triple {23036#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 87: Hoare triple {23036#false} assume !(0 != activate_threads_~tmp___7~0#1); {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 88: Hoare triple {23036#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 89: Hoare triple {23036#false} assume !(1 == ~t9_pc~0); {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 90: Hoare triple {23036#false} is_transmit9_triggered_~__retres1~9#1 := 0; {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 91: Hoare triple {23036#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 92: Hoare triple {23036#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 93: Hoare triple {23036#false} assume !(0 != activate_threads_~tmp___8~0#1); {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 94: Hoare triple {23036#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 95: Hoare triple {23036#false} assume !(1 == ~M_E~0); {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 96: Hoare triple {23036#false} assume !(1 == ~T1_E~0); {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 97: Hoare triple {23036#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 98: Hoare triple {23036#false} assume !(1 == ~T3_E~0); {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 99: Hoare triple {23036#false} assume !(1 == ~T4_E~0); {23036#false} is VALID [2022-02-21 04:24:24,044 INFO L290 TraceCheckUtils]: 100: Hoare triple {23036#false} assume !(1 == ~T5_E~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 101: Hoare triple {23036#false} assume !(1 == ~T6_E~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 102: Hoare triple {23036#false} assume !(1 == ~T7_E~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 103: Hoare triple {23036#false} assume !(1 == ~T8_E~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 104: Hoare triple {23036#false} assume !(1 == ~T9_E~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 105: Hoare triple {23036#false} assume 1 == ~E_1~0;~E_1~0 := 2; {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 106: Hoare triple {23036#false} assume !(1 == ~E_2~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 107: Hoare triple {23036#false} assume !(1 == ~E_3~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 108: Hoare triple {23036#false} assume !(1 == ~E_4~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 109: Hoare triple {23036#false} assume !(1 == ~E_5~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 110: Hoare triple {23036#false} assume !(1 == ~E_6~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 111: Hoare triple {23036#false} assume !(1 == ~E_7~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 112: Hoare triple {23036#false} assume !(1 == ~E_8~0); {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 113: Hoare triple {23036#false} assume 1 == ~E_9~0;~E_9~0 := 2; {23036#false} is VALID [2022-02-21 04:24:24,045 INFO L290 TraceCheckUtils]: 114: Hoare triple {23036#false} assume { :end_inline_reset_delta_events } true; {23036#false} is VALID [2022-02-21 04:24:24,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,046 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,046 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1732116685] [2022-02-21 04:24:24,046 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1732116685] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,046 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,046 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:24,046 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2115806064] [2022-02-21 04:24:24,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,046 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:24,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:24,047 INFO L85 PathProgramCache]: Analyzing trace with hash 1361732948, now seen corresponding path program 1 times [2022-02-21 04:24:24,047 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:24,047 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841575875] [2022-02-21 04:24:24,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:24,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:24,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,087 INFO L290 TraceCheckUtils]: 0: Hoare triple {23038#true} assume !false; {23038#true} is VALID [2022-02-21 04:24:24,088 INFO L290 TraceCheckUtils]: 1: Hoare triple {23038#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {23038#true} is VALID [2022-02-21 04:24:24,088 INFO L290 TraceCheckUtils]: 2: Hoare triple {23038#true} assume !false; {23038#true} is VALID [2022-02-21 04:24:24,088 INFO L290 TraceCheckUtils]: 3: Hoare triple {23038#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {23038#true} is VALID [2022-02-21 04:24:24,088 INFO L290 TraceCheckUtils]: 4: Hoare triple {23038#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {23038#true} is VALID [2022-02-21 04:24:24,088 INFO L290 TraceCheckUtils]: 5: Hoare triple {23038#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {23038#true} is VALID [2022-02-21 04:24:24,089 INFO L290 TraceCheckUtils]: 6: Hoare triple {23038#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {23038#true} is VALID [2022-02-21 04:24:24,089 INFO L290 TraceCheckUtils]: 7: Hoare triple {23038#true} assume !(0 != eval_~tmp~0#1); {23038#true} is VALID [2022-02-21 04:24:24,089 INFO L290 TraceCheckUtils]: 8: Hoare triple {23038#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {23038#true} is VALID [2022-02-21 04:24:24,089 INFO L290 TraceCheckUtils]: 9: Hoare triple {23038#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {23038#true} is VALID [2022-02-21 04:24:24,089 INFO L290 TraceCheckUtils]: 10: Hoare triple {23038#true} assume 0 == ~M_E~0;~M_E~0 := 1; {23038#true} is VALID [2022-02-21 04:24:24,089 INFO L290 TraceCheckUtils]: 11: Hoare triple {23038#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {23038#true} is VALID [2022-02-21 04:24:24,089 INFO L290 TraceCheckUtils]: 12: Hoare triple {23038#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {23038#true} is VALID [2022-02-21 04:24:24,090 INFO L290 TraceCheckUtils]: 13: Hoare triple {23038#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,090 INFO L290 TraceCheckUtils]: 14: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,090 INFO L290 TraceCheckUtils]: 15: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T5_E~0); {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,090 INFO L290 TraceCheckUtils]: 16: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,091 INFO L290 TraceCheckUtils]: 17: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,091 INFO L290 TraceCheckUtils]: 18: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,091 INFO L290 TraceCheckUtils]: 19: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,092 INFO L290 TraceCheckUtils]: 20: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,092 INFO L290 TraceCheckUtils]: 21: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,092 INFO L290 TraceCheckUtils]: 22: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,092 INFO L290 TraceCheckUtils]: 23: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_4~0); {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,093 INFO L290 TraceCheckUtils]: 24: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,093 INFO L290 TraceCheckUtils]: 25: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,093 INFO L290 TraceCheckUtils]: 26: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,093 INFO L290 TraceCheckUtils]: 27: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,094 INFO L290 TraceCheckUtils]: 28: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,094 INFO L290 TraceCheckUtils]: 29: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,094 INFO L290 TraceCheckUtils]: 30: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~m_pc~0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,095 INFO L290 TraceCheckUtils]: 31: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,095 INFO L290 TraceCheckUtils]: 32: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,095 INFO L290 TraceCheckUtils]: 33: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,095 INFO L290 TraceCheckUtils]: 34: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,096 INFO L290 TraceCheckUtils]: 35: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,096 INFO L290 TraceCheckUtils]: 36: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t1_pc~0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,096 INFO L290 TraceCheckUtils]: 37: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,097 INFO L290 TraceCheckUtils]: 38: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,097 INFO L290 TraceCheckUtils]: 39: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,097 INFO L290 TraceCheckUtils]: 40: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,097 INFO L290 TraceCheckUtils]: 41: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,098 INFO L290 TraceCheckUtils]: 42: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t2_pc~0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,098 INFO L290 TraceCheckUtils]: 43: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,098 INFO L290 TraceCheckUtils]: 44: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,098 INFO L290 TraceCheckUtils]: 45: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,099 INFO L290 TraceCheckUtils]: 46: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,099 INFO L290 TraceCheckUtils]: 47: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,099 INFO L290 TraceCheckUtils]: 48: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t3_pc~0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,099 INFO L290 TraceCheckUtils]: 49: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 50: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 51: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,100 INFO L290 TraceCheckUtils]: 52: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,101 INFO L290 TraceCheckUtils]: 53: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,101 INFO L290 TraceCheckUtils]: 54: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t4_pc~0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,101 INFO L290 TraceCheckUtils]: 55: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,101 INFO L290 TraceCheckUtils]: 56: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,102 INFO L290 TraceCheckUtils]: 57: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,102 INFO L290 TraceCheckUtils]: 58: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,102 INFO L290 TraceCheckUtils]: 59: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,102 INFO L290 TraceCheckUtils]: 60: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t5_pc~0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,103 INFO L290 TraceCheckUtils]: 61: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,103 INFO L290 TraceCheckUtils]: 62: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,103 INFO L290 TraceCheckUtils]: 63: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,103 INFO L290 TraceCheckUtils]: 64: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,104 INFO L290 TraceCheckUtils]: 65: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,104 INFO L290 TraceCheckUtils]: 66: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t6_pc~0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,104 INFO L290 TraceCheckUtils]: 67: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,105 INFO L290 TraceCheckUtils]: 68: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,105 INFO L290 TraceCheckUtils]: 69: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,105 INFO L290 TraceCheckUtils]: 70: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,105 INFO L290 TraceCheckUtils]: 71: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,106 INFO L290 TraceCheckUtils]: 72: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t7_pc~0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,106 INFO L290 TraceCheckUtils]: 73: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,106 INFO L290 TraceCheckUtils]: 74: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,107 INFO L290 TraceCheckUtils]: 75: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,107 INFO L290 TraceCheckUtils]: 76: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,107 INFO L290 TraceCheckUtils]: 77: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,108 INFO L290 TraceCheckUtils]: 78: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t8_pc~0); {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,108 INFO L290 TraceCheckUtils]: 79: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,108 INFO L290 TraceCheckUtils]: 80: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,109 INFO L290 TraceCheckUtils]: 81: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,109 INFO L290 TraceCheckUtils]: 82: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,109 INFO L290 TraceCheckUtils]: 83: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,110 INFO L290 TraceCheckUtils]: 84: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t9_pc~0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,110 INFO L290 TraceCheckUtils]: 85: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,110 INFO L290 TraceCheckUtils]: 86: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,111 INFO L290 TraceCheckUtils]: 87: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,111 INFO L290 TraceCheckUtils]: 88: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,111 INFO L290 TraceCheckUtils]: 89: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,112 INFO L290 TraceCheckUtils]: 90: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,112 INFO L290 TraceCheckUtils]: 91: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,112 INFO L290 TraceCheckUtils]: 92: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {23040#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:24,113 INFO L290 TraceCheckUtils]: 93: Hoare triple {23040#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~T3_E~0); {23039#false} is VALID [2022-02-21 04:24:24,113 INFO L290 TraceCheckUtils]: 94: Hoare triple {23039#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,113 INFO L290 TraceCheckUtils]: 95: Hoare triple {23039#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,113 INFO L290 TraceCheckUtils]: 96: Hoare triple {23039#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,113 INFO L290 TraceCheckUtils]: 97: Hoare triple {23039#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,113 INFO L290 TraceCheckUtils]: 98: Hoare triple {23039#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,113 INFO L290 TraceCheckUtils]: 99: Hoare triple {23039#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 100: Hoare triple {23039#false} assume 1 == ~E_1~0;~E_1~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 101: Hoare triple {23039#false} assume !(1 == ~E_2~0); {23039#false} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 102: Hoare triple {23039#false} assume 1 == ~E_3~0;~E_3~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 103: Hoare triple {23039#false} assume 1 == ~E_4~0;~E_4~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 104: Hoare triple {23039#false} assume 1 == ~E_5~0;~E_5~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 105: Hoare triple {23039#false} assume 1 == ~E_6~0;~E_6~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 106: Hoare triple {23039#false} assume 1 == ~E_7~0;~E_7~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,114 INFO L290 TraceCheckUtils]: 107: Hoare triple {23039#false} assume 1 == ~E_8~0;~E_8~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 108: Hoare triple {23039#false} assume 1 == ~E_9~0;~E_9~0 := 2; {23039#false} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 109: Hoare triple {23039#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {23039#false} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 110: Hoare triple {23039#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {23039#false} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 111: Hoare triple {23039#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {23039#false} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 112: Hoare triple {23039#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {23039#false} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 113: Hoare triple {23039#false} assume !(0 == start_simulation_~tmp~3#1); {23039#false} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 114: Hoare triple {23039#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {23039#false} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 115: Hoare triple {23039#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {23039#false} is VALID [2022-02-21 04:24:24,115 INFO L290 TraceCheckUtils]: 116: Hoare triple {23039#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {23039#false} is VALID [2022-02-21 04:24:24,116 INFO L290 TraceCheckUtils]: 117: Hoare triple {23039#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {23039#false} is VALID [2022-02-21 04:24:24,116 INFO L290 TraceCheckUtils]: 118: Hoare triple {23039#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {23039#false} is VALID [2022-02-21 04:24:24,116 INFO L290 TraceCheckUtils]: 119: Hoare triple {23039#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {23039#false} is VALID [2022-02-21 04:24:24,116 INFO L290 TraceCheckUtils]: 120: Hoare triple {23039#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {23039#false} is VALID [2022-02-21 04:24:24,116 INFO L290 TraceCheckUtils]: 121: Hoare triple {23039#false} assume !(0 != start_simulation_~tmp___0~1#1); {23039#false} is VALID [2022-02-21 04:24:24,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,117 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,117 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841575875] [2022-02-21 04:24:24,117 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841575875] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,117 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,117 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:24,117 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795975906] [2022-02-21 04:24:24,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,118 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:24,118 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:24,119 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:24,119 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:24,119 INFO L87 Difference]: Start difference. First operand 1094 states and 1626 transitions. cyclomatic complexity: 533 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,911 INFO L93 Difference]: Finished difference Result 1094 states and 1625 transitions. [2022-02-21 04:24:24,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:24,912 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,971 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:24,972 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1625 transitions. [2022-02-21 04:24:25,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:25,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1625 transitions. [2022-02-21 04:24:25,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-02-21 04:24:25,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-02-21 04:24:25,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1625 transitions. [2022-02-21 04:24:25,045 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:25,045 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2022-02-21 04:24:25,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1625 transitions. [2022-02-21 04:24:25,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-02-21 04:24:25,055 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:25,057 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1094 states and 1625 transitions. Second operand has 1094 states, 1094 states have (on average 1.4853747714808043) internal successors, (1625), 1093 states have internal predecessors, (1625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,058 INFO L74 IsIncluded]: Start isIncluded. First operand 1094 states and 1625 transitions. Second operand has 1094 states, 1094 states have (on average 1.4853747714808043) internal successors, (1625), 1093 states have internal predecessors, (1625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,059 INFO L87 Difference]: Start difference. First operand 1094 states and 1625 transitions. Second operand has 1094 states, 1094 states have (on average 1.4853747714808043) internal successors, (1625), 1093 states have internal predecessors, (1625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:25,089 INFO L93 Difference]: Finished difference Result 1094 states and 1625 transitions. [2022-02-21 04:24:25,089 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1625 transitions. [2022-02-21 04:24:25,091 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:25,091 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:25,093 INFO L74 IsIncluded]: Start isIncluded. First operand has 1094 states, 1094 states have (on average 1.4853747714808043) internal successors, (1625), 1093 states have internal predecessors, (1625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1625 transitions. [2022-02-21 04:24:25,095 INFO L87 Difference]: Start difference. First operand has 1094 states, 1094 states have (on average 1.4853747714808043) internal successors, (1625), 1093 states have internal predecessors, (1625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1625 transitions. [2022-02-21 04:24:25,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:25,128 INFO L93 Difference]: Finished difference Result 1094 states and 1625 transitions. [2022-02-21 04:24:25,128 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1625 transitions. [2022-02-21 04:24:25,129 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:25,129 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:25,129 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:25,129 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:25,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4853747714808043) internal successors, (1625), 1093 states have internal predecessors, (1625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1625 transitions. [2022-02-21 04:24:25,163 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2022-02-21 04:24:25,163 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1625 transitions. [2022-02-21 04:24:25,163 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:25,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1625 transitions. [2022-02-21 04:24:25,167 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:25,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:25,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:25,169 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:25,169 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:25,169 INFO L791 eck$LassoCheckResult]: Stem: 24971#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 24972#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 24573#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24574#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25120#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 25121#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25103#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24923#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24924#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24739#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24740#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25180#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25086#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24795#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24579#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24580#L922 assume !(0 == ~M_E~0); 25225#L922-2 assume !(0 == ~T1_E~0); 25226#L927-1 assume !(0 == ~T2_E~0); 24980#L932-1 assume !(0 == ~T3_E~0); 24865#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24866#L942-1 assume !(0 == ~T5_E~0); 24922#L947-1 assume !(0 == ~T6_E~0); 24984#L952-1 assume !(0 == ~T7_E~0); 24985#L957-1 assume !(0 == ~T8_E~0); 25045#L962-1 assume !(0 == ~T9_E~0); 24841#L967-1 assume !(0 == ~E_1~0); 24842#L972-1 assume !(0 == ~E_2~0); 25108#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 25109#L982-1 assume !(0 == ~E_4~0); 24349#L987-1 assume !(0 == ~E_5~0); 24350#L992-1 assume !(0 == ~E_6~0); 24358#L997-1 assume !(0 == ~E_7~0); 24772#L1002-1 assume !(0 == ~E_8~0); 24759#L1007-1 assume !(0 == ~E_9~0); 24147#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24148#L443 assume !(1 == ~m_pc~0); 25000#L443-2 is_master_triggered_~__retres1~0#1 := 0; 24991#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24992#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24513#L1140 assume !(0 != activate_threads_~tmp~1#1); 24262#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24263#L462 assume 1 == ~t1_pc~0; 24891#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24858#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24233#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24234#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 24720#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24721#L481 assume !(1 == ~t2_pc~0); 24508#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24507#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24862#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24601#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 24602#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24694#L500 assume 1 == ~t3_pc~0; 24904#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24905#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25095#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25096#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 24149#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24150#L519 assume 1 == ~t4_pc~0; 24448#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24449#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24693#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24553#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 24554#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24316#L538 assume !(1 == ~t5_pc~0); 24317#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24223#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24224#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24492#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24493#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25030#L557 assume 1 == ~t6_pc~0; 24829#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24530#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24427#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24428#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 24555#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25208#L576 assume !(1 == ~t7_pc~0); 24517#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24518#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24762#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24763#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 25079#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24638#L595 assume 1 == ~t8_pc~0; 24639#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25097#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25098#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24947#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 24948#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24441#L614 assume !(1 == ~t9_pc~0); 24442#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24340#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24341#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24521#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 24603#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24604#L1025 assume !(1 == ~M_E~0); 24850#L1025-2 assume !(1 == ~T1_E~0); 24903#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25025#L1035-1 assume !(1 == ~T3_E~0); 24597#L1040-1 assume !(1 == ~T4_E~0); 24598#L1045-1 assume !(1 == ~T5_E~0); 24503#L1050-1 assume !(1 == ~T6_E~0); 24504#L1055-1 assume !(1 == ~T7_E~0); 24325#L1060-1 assume !(1 == ~T8_E~0); 24326#L1065-1 assume !(1 == ~T9_E~0); 24389#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 24986#L1075-1 assume !(1 == ~E_2~0); 24987#L1080-1 assume !(1 == ~E_3~0); 24975#L1085-1 assume !(1 == ~E_4~0); 24976#L1090-1 assume !(1 == ~E_5~0); 25175#L1095-1 assume !(1 == ~E_6~0); 25009#L1100-1 assume !(1 == ~E_7~0); 25010#L1105-1 assume !(1 == ~E_8~0); 24298#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 24299#L1115-1 assume { :end_inline_reset_delta_events } true; 24462#L1396-2 [2022-02-21 04:24:25,170 INFO L793 eck$LassoCheckResult]: Loop: 24462#L1396-2 assume !false; 24543#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24572#L897 assume !false; 25215#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 25122#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 24170#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 24171#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25170#L766 assume !(0 != eval_~tmp~0#1); 25156#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24240#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24241#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24754#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24484#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24485#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24663#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24290#L942-3 assume !(0 == ~T5_E~0); 24291#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24664#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24665#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25166#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25057#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25058#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24978#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24979#L982-3 assume !(0 == ~E_4~0); 25227#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24614#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24615#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24609#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 24610#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24327#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24328#L443-30 assume 1 == ~m_pc~0; 24361#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24362#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24645#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25193#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25112#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24745#L462-30 assume 1 == ~t1_pc~0; 24589#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24591#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25092#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25093#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25134#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24732#L481-30 assume 1 == ~t2_pc~0; 24451#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24452#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24505#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24418#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24419#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24699#L500-30 assume 1 == ~t3_pc~0; 24456#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24457#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24519#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24520#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24682#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24683#L519-30 assume 1 == ~t4_pc~0; 25018#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24834#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24196#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24197#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24846#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24959#L538-30 assume 1 == ~t5_pc~0; 24337#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24338#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24636#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24637#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24414#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24415#L557-30 assume 1 == ~t6_pc~0; 24135#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24136#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24813#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24870#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 24439#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24440#L576-30 assume 1 == ~t7_pc~0; 24952#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24222#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24807#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25173#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24599#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24562#L595-30 assume !(1 == ~t8_pc~0); 24563#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 24498#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24231#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24232#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25174#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25210#L614-30 assume 1 == ~t9_pc~0; 24500#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24501#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24635#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24329#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24330#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24938#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24723#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24724#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24908#L1035-3 assume !(1 == ~T3_E~0); 25183#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25223#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25179#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25094#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24229#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24230#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25114#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24960#L1075-3 assume !(1 == ~E_2~0); 24961#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25184#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25105#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25106#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25125#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25126#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24377#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24378#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 25139#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 24246#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 24238#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 24239#L1415 assume !(0 == start_simulation_~tmp~3#1); 24839#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 24840#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 24286#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 24848#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 25027#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25228#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24898#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 24461#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 24462#L1396-2 [2022-02-21 04:24:25,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:25,170 INFO L85 PathProgramCache]: Analyzing trace with hash 116049057, now seen corresponding path program 1 times [2022-02-21 04:24:25,170 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:25,171 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485219356] [2022-02-21 04:24:25,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:25,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:25,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:25,189 INFO L290 TraceCheckUtils]: 0: Hoare triple {27420#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {27420#true} is VALID [2022-02-21 04:24:25,190 INFO L290 TraceCheckUtils]: 1: Hoare triple {27420#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {27422#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:25,190 INFO L290 TraceCheckUtils]: 2: Hoare triple {27422#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {27422#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:25,191 INFO L290 TraceCheckUtils]: 3: Hoare triple {27422#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {27422#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:25,191 INFO L290 TraceCheckUtils]: 4: Hoare triple {27422#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {27422#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:25,203 INFO L290 TraceCheckUtils]: 5: Hoare triple {27422#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {27422#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:25,203 INFO L290 TraceCheckUtils]: 6: Hoare triple {27422#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {27422#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:25,203 INFO L290 TraceCheckUtils]: 7: Hoare triple {27422#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {27422#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:25,204 INFO L290 TraceCheckUtils]: 8: Hoare triple {27422#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {27422#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:25,204 INFO L290 TraceCheckUtils]: 9: Hoare triple {27422#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {27422#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:25,204 INFO L290 TraceCheckUtils]: 10: Hoare triple {27422#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {27422#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 11: Hoare triple {27422#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {27421#false} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 12: Hoare triple {27421#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {27421#false} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 13: Hoare triple {27421#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {27421#false} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 14: Hoare triple {27421#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {27421#false} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 15: Hoare triple {27421#false} assume !(0 == ~M_E~0); {27421#false} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 16: Hoare triple {27421#false} assume !(0 == ~T1_E~0); {27421#false} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 17: Hoare triple {27421#false} assume !(0 == ~T2_E~0); {27421#false} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 18: Hoare triple {27421#false} assume !(0 == ~T3_E~0); {27421#false} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 19: Hoare triple {27421#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {27421#false} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 20: Hoare triple {27421#false} assume !(0 == ~T5_E~0); {27421#false} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 21: Hoare triple {27421#false} assume !(0 == ~T6_E~0); {27421#false} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 22: Hoare triple {27421#false} assume !(0 == ~T7_E~0); {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 23: Hoare triple {27421#false} assume !(0 == ~T8_E~0); {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 24: Hoare triple {27421#false} assume !(0 == ~T9_E~0); {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 25: Hoare triple {27421#false} assume !(0 == ~E_1~0); {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 26: Hoare triple {27421#false} assume !(0 == ~E_2~0); {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 27: Hoare triple {27421#false} assume 0 == ~E_3~0;~E_3~0 := 1; {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 28: Hoare triple {27421#false} assume !(0 == ~E_4~0); {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 29: Hoare triple {27421#false} assume !(0 == ~E_5~0); {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 30: Hoare triple {27421#false} assume !(0 == ~E_6~0); {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 31: Hoare triple {27421#false} assume !(0 == ~E_7~0); {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 32: Hoare triple {27421#false} assume !(0 == ~E_8~0); {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 33: Hoare triple {27421#false} assume !(0 == ~E_9~0); {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 34: Hoare triple {27421#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {27421#false} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 35: Hoare triple {27421#false} assume !(1 == ~m_pc~0); {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 36: Hoare triple {27421#false} is_master_triggered_~__retres1~0#1 := 0; {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 37: Hoare triple {27421#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 38: Hoare triple {27421#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 39: Hoare triple {27421#false} assume !(0 != activate_threads_~tmp~1#1); {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 40: Hoare triple {27421#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 41: Hoare triple {27421#false} assume 1 == ~t1_pc~0; {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 42: Hoare triple {27421#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 43: Hoare triple {27421#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 44: Hoare triple {27421#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 45: Hoare triple {27421#false} assume !(0 != activate_threads_~tmp___0~0#1); {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 46: Hoare triple {27421#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {27421#false} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 47: Hoare triple {27421#false} assume !(1 == ~t2_pc~0); {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 48: Hoare triple {27421#false} is_transmit2_triggered_~__retres1~2#1 := 0; {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 49: Hoare triple {27421#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 50: Hoare triple {27421#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 51: Hoare triple {27421#false} assume !(0 != activate_threads_~tmp___1~0#1); {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 52: Hoare triple {27421#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 53: Hoare triple {27421#false} assume 1 == ~t3_pc~0; {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 54: Hoare triple {27421#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 55: Hoare triple {27421#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 56: Hoare triple {27421#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 57: Hoare triple {27421#false} assume !(0 != activate_threads_~tmp___2~0#1); {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 58: Hoare triple {27421#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 59: Hoare triple {27421#false} assume 1 == ~t4_pc~0; {27421#false} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 60: Hoare triple {27421#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 61: Hoare triple {27421#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 62: Hoare triple {27421#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 63: Hoare triple {27421#false} assume !(0 != activate_threads_~tmp___3~0#1); {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 64: Hoare triple {27421#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 65: Hoare triple {27421#false} assume !(1 == ~t5_pc~0); {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 66: Hoare triple {27421#false} is_transmit5_triggered_~__retres1~5#1 := 0; {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 67: Hoare triple {27421#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 68: Hoare triple {27421#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 69: Hoare triple {27421#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 70: Hoare triple {27421#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 71: Hoare triple {27421#false} assume 1 == ~t6_pc~0; {27421#false} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 72: Hoare triple {27421#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 73: Hoare triple {27421#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 74: Hoare triple {27421#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 75: Hoare triple {27421#false} assume !(0 != activate_threads_~tmp___5~0#1); {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 76: Hoare triple {27421#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 77: Hoare triple {27421#false} assume !(1 == ~t7_pc~0); {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 78: Hoare triple {27421#false} is_transmit7_triggered_~__retres1~7#1 := 0; {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 79: Hoare triple {27421#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 80: Hoare triple {27421#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 81: Hoare triple {27421#false} assume !(0 != activate_threads_~tmp___6~0#1); {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 82: Hoare triple {27421#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 83: Hoare triple {27421#false} assume 1 == ~t8_pc~0; {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 84: Hoare triple {27421#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {27421#false} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 85: Hoare triple {27421#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 86: Hoare triple {27421#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 87: Hoare triple {27421#false} assume !(0 != activate_threads_~tmp___7~0#1); {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 88: Hoare triple {27421#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 89: Hoare triple {27421#false} assume !(1 == ~t9_pc~0); {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 90: Hoare triple {27421#false} is_transmit9_triggered_~__retres1~9#1 := 0; {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 91: Hoare triple {27421#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 92: Hoare triple {27421#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 93: Hoare triple {27421#false} assume !(0 != activate_threads_~tmp___8~0#1); {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 94: Hoare triple {27421#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 95: Hoare triple {27421#false} assume !(1 == ~M_E~0); {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 96: Hoare triple {27421#false} assume !(1 == ~T1_E~0); {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 97: Hoare triple {27421#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {27421#false} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 98: Hoare triple {27421#false} assume !(1 == ~T3_E~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 99: Hoare triple {27421#false} assume !(1 == ~T4_E~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 100: Hoare triple {27421#false} assume !(1 == ~T5_E~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 101: Hoare triple {27421#false} assume !(1 == ~T6_E~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 102: Hoare triple {27421#false} assume !(1 == ~T7_E~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 103: Hoare triple {27421#false} assume !(1 == ~T8_E~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 104: Hoare triple {27421#false} assume !(1 == ~T9_E~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 105: Hoare triple {27421#false} assume 1 == ~E_1~0;~E_1~0 := 2; {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 106: Hoare triple {27421#false} assume !(1 == ~E_2~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 107: Hoare triple {27421#false} assume !(1 == ~E_3~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 108: Hoare triple {27421#false} assume !(1 == ~E_4~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 109: Hoare triple {27421#false} assume !(1 == ~E_5~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 110: Hoare triple {27421#false} assume !(1 == ~E_6~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 111: Hoare triple {27421#false} assume !(1 == ~E_7~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 112: Hoare triple {27421#false} assume !(1 == ~E_8~0); {27421#false} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 113: Hoare triple {27421#false} assume 1 == ~E_9~0;~E_9~0 := 2; {27421#false} is VALID [2022-02-21 04:24:25,213 INFO L290 TraceCheckUtils]: 114: Hoare triple {27421#false} assume { :end_inline_reset_delta_events } true; {27421#false} is VALID [2022-02-21 04:24:25,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:25,213 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:25,213 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485219356] [2022-02-21 04:24:25,213 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485219356] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:25,213 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:25,213 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:25,213 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592421901] [2022-02-21 04:24:25,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:25,214 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:25,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:25,214 INFO L85 PathProgramCache]: Analyzing trace with hash 1361732948, now seen corresponding path program 2 times [2022-02-21 04:24:25,214 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:25,215 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740303380] [2022-02-21 04:24:25,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:25,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:25,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:25,243 INFO L290 TraceCheckUtils]: 0: Hoare triple {27423#true} assume !false; {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 1: Hoare triple {27423#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 2: Hoare triple {27423#true} assume !false; {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 3: Hoare triple {27423#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 4: Hoare triple {27423#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 5: Hoare triple {27423#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 6: Hoare triple {27423#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 7: Hoare triple {27423#true} assume !(0 != eval_~tmp~0#1); {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 8: Hoare triple {27423#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 9: Hoare triple {27423#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 10: Hoare triple {27423#true} assume 0 == ~M_E~0;~M_E~0 := 1; {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 11: Hoare triple {27423#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {27423#true} is VALID [2022-02-21 04:24:25,244 INFO L290 TraceCheckUtils]: 12: Hoare triple {27423#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {27423#true} is VALID [2022-02-21 04:24:25,245 INFO L290 TraceCheckUtils]: 13: Hoare triple {27423#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,245 INFO L290 TraceCheckUtils]: 14: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,245 INFO L290 TraceCheckUtils]: 15: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T5_E~0); {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,245 INFO L290 TraceCheckUtils]: 16: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,246 INFO L290 TraceCheckUtils]: 17: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,246 INFO L290 TraceCheckUtils]: 18: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,246 INFO L290 TraceCheckUtils]: 19: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,246 INFO L290 TraceCheckUtils]: 20: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,247 INFO L290 TraceCheckUtils]: 21: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,247 INFO L290 TraceCheckUtils]: 22: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,247 INFO L290 TraceCheckUtils]: 23: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_4~0); {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,247 INFO L290 TraceCheckUtils]: 24: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,248 INFO L290 TraceCheckUtils]: 25: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,248 INFO L290 TraceCheckUtils]: 26: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,248 INFO L290 TraceCheckUtils]: 27: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,248 INFO L290 TraceCheckUtils]: 28: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,249 INFO L290 TraceCheckUtils]: 29: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,249 INFO L290 TraceCheckUtils]: 30: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~m_pc~0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,249 INFO L290 TraceCheckUtils]: 31: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,249 INFO L290 TraceCheckUtils]: 32: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,250 INFO L290 TraceCheckUtils]: 33: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,250 INFO L290 TraceCheckUtils]: 34: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,250 INFO L290 TraceCheckUtils]: 35: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,250 INFO L290 TraceCheckUtils]: 36: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t1_pc~0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,251 INFO L290 TraceCheckUtils]: 37: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,251 INFO L290 TraceCheckUtils]: 38: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,251 INFO L290 TraceCheckUtils]: 39: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,251 INFO L290 TraceCheckUtils]: 40: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,252 INFO L290 TraceCheckUtils]: 41: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,252 INFO L290 TraceCheckUtils]: 42: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t2_pc~0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,252 INFO L290 TraceCheckUtils]: 43: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,252 INFO L290 TraceCheckUtils]: 44: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,253 INFO L290 TraceCheckUtils]: 45: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,253 INFO L290 TraceCheckUtils]: 46: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,253 INFO L290 TraceCheckUtils]: 47: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,253 INFO L290 TraceCheckUtils]: 48: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t3_pc~0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,254 INFO L290 TraceCheckUtils]: 49: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,254 INFO L290 TraceCheckUtils]: 50: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,254 INFO L290 TraceCheckUtils]: 51: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,254 INFO L290 TraceCheckUtils]: 52: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,255 INFO L290 TraceCheckUtils]: 53: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,255 INFO L290 TraceCheckUtils]: 54: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t4_pc~0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,255 INFO L290 TraceCheckUtils]: 55: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,256 INFO L290 TraceCheckUtils]: 56: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,256 INFO L290 TraceCheckUtils]: 57: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,256 INFO L290 TraceCheckUtils]: 58: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,256 INFO L290 TraceCheckUtils]: 59: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,257 INFO L290 TraceCheckUtils]: 60: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t5_pc~0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,257 INFO L290 TraceCheckUtils]: 61: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,257 INFO L290 TraceCheckUtils]: 62: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,257 INFO L290 TraceCheckUtils]: 63: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,258 INFO L290 TraceCheckUtils]: 64: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,258 INFO L290 TraceCheckUtils]: 65: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,258 INFO L290 TraceCheckUtils]: 66: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t6_pc~0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,258 INFO L290 TraceCheckUtils]: 67: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,259 INFO L290 TraceCheckUtils]: 68: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,259 INFO L290 TraceCheckUtils]: 69: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,259 INFO L290 TraceCheckUtils]: 70: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,259 INFO L290 TraceCheckUtils]: 71: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,260 INFO L290 TraceCheckUtils]: 72: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t7_pc~0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,260 INFO L290 TraceCheckUtils]: 73: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,260 INFO L290 TraceCheckUtils]: 74: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,260 INFO L290 TraceCheckUtils]: 75: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,261 INFO L290 TraceCheckUtils]: 76: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,261 INFO L290 TraceCheckUtils]: 77: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,261 INFO L290 TraceCheckUtils]: 78: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t8_pc~0); {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,261 INFO L290 TraceCheckUtils]: 79: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,262 INFO L290 TraceCheckUtils]: 80: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,262 INFO L290 TraceCheckUtils]: 81: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,262 INFO L290 TraceCheckUtils]: 82: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,262 INFO L290 TraceCheckUtils]: 83: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,263 INFO L290 TraceCheckUtils]: 84: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t9_pc~0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,263 INFO L290 TraceCheckUtils]: 85: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,263 INFO L290 TraceCheckUtils]: 86: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,263 INFO L290 TraceCheckUtils]: 87: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,264 INFO L290 TraceCheckUtils]: 88: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,264 INFO L290 TraceCheckUtils]: 89: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,264 INFO L290 TraceCheckUtils]: 90: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,265 INFO L290 TraceCheckUtils]: 91: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,265 INFO L290 TraceCheckUtils]: 92: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {27425#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:25,265 INFO L290 TraceCheckUtils]: 93: Hoare triple {27425#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~T3_E~0); {27424#false} is VALID [2022-02-21 04:24:25,265 INFO L290 TraceCheckUtils]: 94: Hoare triple {27424#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,265 INFO L290 TraceCheckUtils]: 95: Hoare triple {27424#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,265 INFO L290 TraceCheckUtils]: 96: Hoare triple {27424#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,265 INFO L290 TraceCheckUtils]: 97: Hoare triple {27424#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,265 INFO L290 TraceCheckUtils]: 98: Hoare triple {27424#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,265 INFO L290 TraceCheckUtils]: 99: Hoare triple {27424#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,265 INFO L290 TraceCheckUtils]: 100: Hoare triple {27424#false} assume 1 == ~E_1~0;~E_1~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,266 INFO L290 TraceCheckUtils]: 101: Hoare triple {27424#false} assume !(1 == ~E_2~0); {27424#false} is VALID [2022-02-21 04:24:25,266 INFO L290 TraceCheckUtils]: 102: Hoare triple {27424#false} assume 1 == ~E_3~0;~E_3~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,266 INFO L290 TraceCheckUtils]: 103: Hoare triple {27424#false} assume 1 == ~E_4~0;~E_4~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,266 INFO L290 TraceCheckUtils]: 104: Hoare triple {27424#false} assume 1 == ~E_5~0;~E_5~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,266 INFO L290 TraceCheckUtils]: 105: Hoare triple {27424#false} assume 1 == ~E_6~0;~E_6~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,266 INFO L290 TraceCheckUtils]: 106: Hoare triple {27424#false} assume 1 == ~E_7~0;~E_7~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,266 INFO L290 TraceCheckUtils]: 107: Hoare triple {27424#false} assume 1 == ~E_8~0;~E_8~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,266 INFO L290 TraceCheckUtils]: 108: Hoare triple {27424#false} assume 1 == ~E_9~0;~E_9~0 := 2; {27424#false} is VALID [2022-02-21 04:24:25,266 INFO L290 TraceCheckUtils]: 109: Hoare triple {27424#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {27424#false} is VALID [2022-02-21 04:24:25,266 INFO L290 TraceCheckUtils]: 110: Hoare triple {27424#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {27424#false} is VALID [2022-02-21 04:24:25,284 INFO L290 TraceCheckUtils]: 111: Hoare triple {27424#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {27424#false} is VALID [2022-02-21 04:24:25,284 INFO L290 TraceCheckUtils]: 112: Hoare triple {27424#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {27424#false} is VALID [2022-02-21 04:24:25,284 INFO L290 TraceCheckUtils]: 113: Hoare triple {27424#false} assume !(0 == start_simulation_~tmp~3#1); {27424#false} is VALID [2022-02-21 04:24:25,284 INFO L290 TraceCheckUtils]: 114: Hoare triple {27424#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {27424#false} is VALID [2022-02-21 04:24:25,284 INFO L290 TraceCheckUtils]: 115: Hoare triple {27424#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {27424#false} is VALID [2022-02-21 04:24:25,284 INFO L290 TraceCheckUtils]: 116: Hoare triple {27424#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {27424#false} is VALID [2022-02-21 04:24:25,284 INFO L290 TraceCheckUtils]: 117: Hoare triple {27424#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {27424#false} is VALID [2022-02-21 04:24:25,284 INFO L290 TraceCheckUtils]: 118: Hoare triple {27424#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {27424#false} is VALID [2022-02-21 04:24:25,284 INFO L290 TraceCheckUtils]: 119: Hoare triple {27424#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {27424#false} is VALID [2022-02-21 04:24:25,285 INFO L290 TraceCheckUtils]: 120: Hoare triple {27424#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {27424#false} is VALID [2022-02-21 04:24:25,285 INFO L290 TraceCheckUtils]: 121: Hoare triple {27424#false} assume !(0 != start_simulation_~tmp___0~1#1); {27424#false} is VALID [2022-02-21 04:24:25,285 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:25,285 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:25,285 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740303380] [2022-02-21 04:24:25,285 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740303380] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:25,285 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:25,285 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:25,285 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285199879] [2022-02-21 04:24:25,286 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:25,286 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:25,286 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:25,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:25,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:25,286 INFO L87 Difference]: Start difference. First operand 1094 states and 1625 transitions. cyclomatic complexity: 532 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,045 INFO L93 Difference]: Finished difference Result 1094 states and 1624 transitions. [2022-02-21 04:24:26,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:26,046 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,110 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:26,112 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1624 transitions. [2022-02-21 04:24:26,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:26,174 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1624 transitions. [2022-02-21 04:24:26,174 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-02-21 04:24:26,175 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-02-21 04:24:26,175 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1624 transitions. [2022-02-21 04:24:26,176 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:26,176 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2022-02-21 04:24:26,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1624 transitions. [2022-02-21 04:24:26,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-02-21 04:24:26,187 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:26,188 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1094 states and 1624 transitions. Second operand has 1094 states, 1094 states have (on average 1.4844606946983547) internal successors, (1624), 1093 states have internal predecessors, (1624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,189 INFO L74 IsIncluded]: Start isIncluded. First operand 1094 states and 1624 transitions. Second operand has 1094 states, 1094 states have (on average 1.4844606946983547) internal successors, (1624), 1093 states have internal predecessors, (1624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,190 INFO L87 Difference]: Start difference. First operand 1094 states and 1624 transitions. Second operand has 1094 states, 1094 states have (on average 1.4844606946983547) internal successors, (1624), 1093 states have internal predecessors, (1624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,218 INFO L93 Difference]: Finished difference Result 1094 states and 1624 transitions. [2022-02-21 04:24:26,218 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1624 transitions. [2022-02-21 04:24:26,220 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:26,220 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:26,221 INFO L74 IsIncluded]: Start isIncluded. First operand has 1094 states, 1094 states have (on average 1.4844606946983547) internal successors, (1624), 1093 states have internal predecessors, (1624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1624 transitions. [2022-02-21 04:24:26,222 INFO L87 Difference]: Start difference. First operand has 1094 states, 1094 states have (on average 1.4844606946983547) internal successors, (1624), 1093 states have internal predecessors, (1624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1624 transitions. [2022-02-21 04:24:26,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,252 INFO L93 Difference]: Finished difference Result 1094 states and 1624 transitions. [2022-02-21 04:24:26,252 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1624 transitions. [2022-02-21 04:24:26,253 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:26,254 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:26,254 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:26,254 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:26,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.4844606946983547) internal successors, (1624), 1093 states have internal predecessors, (1624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1624 transitions. [2022-02-21 04:24:26,286 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2022-02-21 04:24:26,286 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1624 transitions. [2022-02-21 04:24:26,286 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:26,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1624 transitions. [2022-02-21 04:24:26,289 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:26,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:26,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:26,290 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:26,291 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:26,291 INFO L791 eck$LassoCheckResult]: Stem: 29356#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 29357#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 28958#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28959#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29505#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 29506#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29488#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29308#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29309#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29124#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29125#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29565#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29471#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29180#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28964#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28965#L922 assume !(0 == ~M_E~0); 29610#L922-2 assume !(0 == ~T1_E~0); 29611#L927-1 assume !(0 == ~T2_E~0); 29365#L932-1 assume !(0 == ~T3_E~0); 29250#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29251#L942-1 assume !(0 == ~T5_E~0); 29307#L947-1 assume !(0 == ~T6_E~0); 29369#L952-1 assume !(0 == ~T7_E~0); 29370#L957-1 assume !(0 == ~T8_E~0); 29430#L962-1 assume !(0 == ~T9_E~0); 29226#L967-1 assume !(0 == ~E_1~0); 29227#L972-1 assume !(0 == ~E_2~0); 29493#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 29494#L982-1 assume !(0 == ~E_4~0); 28734#L987-1 assume !(0 == ~E_5~0); 28735#L992-1 assume !(0 == ~E_6~0); 28743#L997-1 assume !(0 == ~E_7~0); 29157#L1002-1 assume !(0 == ~E_8~0); 29144#L1007-1 assume !(0 == ~E_9~0); 28532#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28533#L443 assume !(1 == ~m_pc~0); 29385#L443-2 is_master_triggered_~__retres1~0#1 := 0; 29376#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29377#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28898#L1140 assume !(0 != activate_threads_~tmp~1#1); 28647#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28648#L462 assume 1 == ~t1_pc~0; 29276#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29243#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28618#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28619#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 29105#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29106#L481 assume !(1 == ~t2_pc~0); 28893#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28892#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29247#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28986#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 28987#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29079#L500 assume 1 == ~t3_pc~0; 29289#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29290#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29480#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29481#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 28534#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28535#L519 assume 1 == ~t4_pc~0; 28833#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28834#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29078#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28938#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 28939#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28701#L538 assume !(1 == ~t5_pc~0); 28702#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28608#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28609#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28877#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28878#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29415#L557 assume 1 == ~t6_pc~0; 29214#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28915#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28812#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28813#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 28940#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29593#L576 assume !(1 == ~t7_pc~0); 28902#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28903#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29147#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29148#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 29464#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29023#L595 assume 1 == ~t8_pc~0; 29024#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29482#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29483#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29332#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 29333#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28826#L614 assume !(1 == ~t9_pc~0); 28827#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 28725#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28726#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28906#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 28988#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28989#L1025 assume !(1 == ~M_E~0); 29235#L1025-2 assume !(1 == ~T1_E~0); 29288#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29410#L1035-1 assume !(1 == ~T3_E~0); 28982#L1040-1 assume !(1 == ~T4_E~0); 28983#L1045-1 assume !(1 == ~T5_E~0); 28888#L1050-1 assume !(1 == ~T6_E~0); 28889#L1055-1 assume !(1 == ~T7_E~0); 28710#L1060-1 assume !(1 == ~T8_E~0); 28711#L1065-1 assume !(1 == ~T9_E~0); 28774#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 29371#L1075-1 assume !(1 == ~E_2~0); 29372#L1080-1 assume !(1 == ~E_3~0); 29360#L1085-1 assume !(1 == ~E_4~0); 29361#L1090-1 assume !(1 == ~E_5~0); 29560#L1095-1 assume !(1 == ~E_6~0); 29394#L1100-1 assume !(1 == ~E_7~0); 29395#L1105-1 assume !(1 == ~E_8~0); 28683#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 28684#L1115-1 assume { :end_inline_reset_delta_events } true; 28847#L1396-2 [2022-02-21 04:24:26,291 INFO L793 eck$LassoCheckResult]: Loop: 28847#L1396-2 assume !false; 28928#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28957#L897 assume !false; 29600#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 29507#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28555#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28556#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 29555#L766 assume !(0 != eval_~tmp~0#1); 29541#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28625#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28626#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29139#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28869#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28870#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29048#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28675#L942-3 assume !(0 == ~T5_E~0); 28676#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29049#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29050#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29551#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29442#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29443#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29363#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29364#L982-3 assume !(0 == ~E_4~0); 29612#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28999#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29000#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28994#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28995#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28712#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28713#L443-30 assume 1 == ~m_pc~0; 28746#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28747#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29030#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 29578#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29497#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29130#L462-30 assume 1 == ~t1_pc~0; 28974#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28976#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29477#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29478#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29519#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29117#L481-30 assume 1 == ~t2_pc~0; 28836#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28837#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28890#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28803#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28804#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29084#L500-30 assume 1 == ~t3_pc~0; 28841#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28842#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28904#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28905#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29067#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29068#L519-30 assume 1 == ~t4_pc~0; 29403#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29219#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28581#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28582#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29231#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29344#L538-30 assume 1 == ~t5_pc~0; 28722#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28723#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29021#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29022#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28799#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28800#L557-30 assume 1 == ~t6_pc~0; 28520#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28521#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29198#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29255#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 28824#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28825#L576-30 assume 1 == ~t7_pc~0; 29337#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28607#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29192#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29558#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28984#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28947#L595-30 assume !(1 == ~t8_pc~0); 28948#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 28883#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28616#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28617#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29559#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29595#L614-30 assume 1 == ~t9_pc~0; 28885#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28886#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29020#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28714#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28715#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29323#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29108#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29109#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29293#L1035-3 assume !(1 == ~T3_E~0); 29568#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29608#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29564#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29479#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28614#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28615#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29499#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29345#L1075-3 assume !(1 == ~E_2~0); 29346#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29569#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29490#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29491#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29510#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29511#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28762#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28763#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 29524#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28631#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28623#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 28624#L1415 assume !(0 == start_simulation_~tmp~3#1); 29224#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 29225#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28671#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 29233#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 29412#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29613#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29283#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 28846#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 28847#L1396-2 [2022-02-21 04:24:26,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:26,292 INFO L85 PathProgramCache]: Analyzing trace with hash -1273244957, now seen corresponding path program 1 times [2022-02-21 04:24:26,292 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:26,292 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1498251301] [2022-02-21 04:24:26,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:26,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:26,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:26,338 INFO L290 TraceCheckUtils]: 0: Hoare triple {31805#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {31805#true} is VALID [2022-02-21 04:24:26,339 INFO L290 TraceCheckUtils]: 1: Hoare triple {31805#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {31807#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:26,339 INFO L290 TraceCheckUtils]: 2: Hoare triple {31807#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {31807#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:26,339 INFO L290 TraceCheckUtils]: 3: Hoare triple {31807#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {31807#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:26,340 INFO L290 TraceCheckUtils]: 4: Hoare triple {31807#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {31807#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:26,340 INFO L290 TraceCheckUtils]: 5: Hoare triple {31807#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {31807#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:26,340 INFO L290 TraceCheckUtils]: 6: Hoare triple {31807#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {31807#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:26,340 INFO L290 TraceCheckUtils]: 7: Hoare triple {31807#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {31807#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:26,341 INFO L290 TraceCheckUtils]: 8: Hoare triple {31807#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {31807#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:26,341 INFO L290 TraceCheckUtils]: 9: Hoare triple {31807#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {31807#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:26,341 INFO L290 TraceCheckUtils]: 10: Hoare triple {31807#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {31807#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:26,341 INFO L290 TraceCheckUtils]: 11: Hoare triple {31807#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {31807#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 12: Hoare triple {31807#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 13: Hoare triple {31806#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 14: Hoare triple {31806#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 15: Hoare triple {31806#false} assume !(0 == ~M_E~0); {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 16: Hoare triple {31806#false} assume !(0 == ~T1_E~0); {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 17: Hoare triple {31806#false} assume !(0 == ~T2_E~0); {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 18: Hoare triple {31806#false} assume !(0 == ~T3_E~0); {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 19: Hoare triple {31806#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 20: Hoare triple {31806#false} assume !(0 == ~T5_E~0); {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 21: Hoare triple {31806#false} assume !(0 == ~T6_E~0); {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 22: Hoare triple {31806#false} assume !(0 == ~T7_E~0); {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 23: Hoare triple {31806#false} assume !(0 == ~T8_E~0); {31806#false} is VALID [2022-02-21 04:24:26,342 INFO L290 TraceCheckUtils]: 24: Hoare triple {31806#false} assume !(0 == ~T9_E~0); {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 25: Hoare triple {31806#false} assume !(0 == ~E_1~0); {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 26: Hoare triple {31806#false} assume !(0 == ~E_2~0); {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 27: Hoare triple {31806#false} assume 0 == ~E_3~0;~E_3~0 := 1; {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 28: Hoare triple {31806#false} assume !(0 == ~E_4~0); {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 29: Hoare triple {31806#false} assume !(0 == ~E_5~0); {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 30: Hoare triple {31806#false} assume !(0 == ~E_6~0); {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 31: Hoare triple {31806#false} assume !(0 == ~E_7~0); {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 32: Hoare triple {31806#false} assume !(0 == ~E_8~0); {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 33: Hoare triple {31806#false} assume !(0 == ~E_9~0); {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 34: Hoare triple {31806#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 35: Hoare triple {31806#false} assume !(1 == ~m_pc~0); {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 36: Hoare triple {31806#false} is_master_triggered_~__retres1~0#1 := 0; {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 37: Hoare triple {31806#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 38: Hoare triple {31806#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 39: Hoare triple {31806#false} assume !(0 != activate_threads_~tmp~1#1); {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 40: Hoare triple {31806#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {31806#false} is VALID [2022-02-21 04:24:26,343 INFO L290 TraceCheckUtils]: 41: Hoare triple {31806#false} assume 1 == ~t1_pc~0; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 42: Hoare triple {31806#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 43: Hoare triple {31806#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 44: Hoare triple {31806#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 45: Hoare triple {31806#false} assume !(0 != activate_threads_~tmp___0~0#1); {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 46: Hoare triple {31806#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 47: Hoare triple {31806#false} assume !(1 == ~t2_pc~0); {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 48: Hoare triple {31806#false} is_transmit2_triggered_~__retres1~2#1 := 0; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 49: Hoare triple {31806#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 50: Hoare triple {31806#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 51: Hoare triple {31806#false} assume !(0 != activate_threads_~tmp___1~0#1); {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 52: Hoare triple {31806#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 53: Hoare triple {31806#false} assume 1 == ~t3_pc~0; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 54: Hoare triple {31806#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 55: Hoare triple {31806#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 56: Hoare triple {31806#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {31806#false} is VALID [2022-02-21 04:24:26,344 INFO L290 TraceCheckUtils]: 57: Hoare triple {31806#false} assume !(0 != activate_threads_~tmp___2~0#1); {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 58: Hoare triple {31806#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 59: Hoare triple {31806#false} assume 1 == ~t4_pc~0; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 60: Hoare triple {31806#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 61: Hoare triple {31806#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 62: Hoare triple {31806#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 63: Hoare triple {31806#false} assume !(0 != activate_threads_~tmp___3~0#1); {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 64: Hoare triple {31806#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 65: Hoare triple {31806#false} assume !(1 == ~t5_pc~0); {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 66: Hoare triple {31806#false} is_transmit5_triggered_~__retres1~5#1 := 0; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 67: Hoare triple {31806#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 68: Hoare triple {31806#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 69: Hoare triple {31806#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 70: Hoare triple {31806#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 71: Hoare triple {31806#false} assume 1 == ~t6_pc~0; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 72: Hoare triple {31806#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 73: Hoare triple {31806#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {31806#false} is VALID [2022-02-21 04:24:26,345 INFO L290 TraceCheckUtils]: 74: Hoare triple {31806#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 75: Hoare triple {31806#false} assume !(0 != activate_threads_~tmp___5~0#1); {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 76: Hoare triple {31806#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 77: Hoare triple {31806#false} assume !(1 == ~t7_pc~0); {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 78: Hoare triple {31806#false} is_transmit7_triggered_~__retres1~7#1 := 0; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 79: Hoare triple {31806#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 80: Hoare triple {31806#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 81: Hoare triple {31806#false} assume !(0 != activate_threads_~tmp___6~0#1); {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 82: Hoare triple {31806#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 83: Hoare triple {31806#false} assume 1 == ~t8_pc~0; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 84: Hoare triple {31806#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 85: Hoare triple {31806#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 86: Hoare triple {31806#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 87: Hoare triple {31806#false} assume !(0 != activate_threads_~tmp___7~0#1); {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 88: Hoare triple {31806#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 89: Hoare triple {31806#false} assume !(1 == ~t9_pc~0); {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 90: Hoare triple {31806#false} is_transmit9_triggered_~__retres1~9#1 := 0; {31806#false} is VALID [2022-02-21 04:24:26,346 INFO L290 TraceCheckUtils]: 91: Hoare triple {31806#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 92: Hoare triple {31806#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 93: Hoare triple {31806#false} assume !(0 != activate_threads_~tmp___8~0#1); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 94: Hoare triple {31806#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 95: Hoare triple {31806#false} assume !(1 == ~M_E~0); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 96: Hoare triple {31806#false} assume !(1 == ~T1_E~0); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 97: Hoare triple {31806#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 98: Hoare triple {31806#false} assume !(1 == ~T3_E~0); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 99: Hoare triple {31806#false} assume !(1 == ~T4_E~0); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 100: Hoare triple {31806#false} assume !(1 == ~T5_E~0); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 101: Hoare triple {31806#false} assume !(1 == ~T6_E~0); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 102: Hoare triple {31806#false} assume !(1 == ~T7_E~0); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 103: Hoare triple {31806#false} assume !(1 == ~T8_E~0); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 104: Hoare triple {31806#false} assume !(1 == ~T9_E~0); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 105: Hoare triple {31806#false} assume 1 == ~E_1~0;~E_1~0 := 2; {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 106: Hoare triple {31806#false} assume !(1 == ~E_2~0); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 107: Hoare triple {31806#false} assume !(1 == ~E_3~0); {31806#false} is VALID [2022-02-21 04:24:26,347 INFO L290 TraceCheckUtils]: 108: Hoare triple {31806#false} assume !(1 == ~E_4~0); {31806#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 109: Hoare triple {31806#false} assume !(1 == ~E_5~0); {31806#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 110: Hoare triple {31806#false} assume !(1 == ~E_6~0); {31806#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 111: Hoare triple {31806#false} assume !(1 == ~E_7~0); {31806#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 112: Hoare triple {31806#false} assume !(1 == ~E_8~0); {31806#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 113: Hoare triple {31806#false} assume 1 == ~E_9~0;~E_9~0 := 2; {31806#false} is VALID [2022-02-21 04:24:26,348 INFO L290 TraceCheckUtils]: 114: Hoare triple {31806#false} assume { :end_inline_reset_delta_events } true; {31806#false} is VALID [2022-02-21 04:24:26,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:26,348 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:26,348 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1498251301] [2022-02-21 04:24:26,348 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1498251301] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:26,348 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:26,349 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:26,349 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1357324708] [2022-02-21 04:24:26,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:26,349 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:26,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:26,349 INFO L85 PathProgramCache]: Analyzing trace with hash 1361732948, now seen corresponding path program 3 times [2022-02-21 04:24:26,350 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:26,350 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127384003] [2022-02-21 04:24:26,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:26,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:26,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:26,374 INFO L290 TraceCheckUtils]: 0: Hoare triple {31808#true} assume !false; {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 1: Hoare triple {31808#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 2: Hoare triple {31808#true} assume !false; {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 3: Hoare triple {31808#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 4: Hoare triple {31808#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 5: Hoare triple {31808#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 6: Hoare triple {31808#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 7: Hoare triple {31808#true} assume !(0 != eval_~tmp~0#1); {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 8: Hoare triple {31808#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 9: Hoare triple {31808#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 10: Hoare triple {31808#true} assume 0 == ~M_E~0;~M_E~0 := 1; {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 11: Hoare triple {31808#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {31808#true} is VALID [2022-02-21 04:24:26,375 INFO L290 TraceCheckUtils]: 12: Hoare triple {31808#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {31808#true} is VALID [2022-02-21 04:24:26,376 INFO L290 TraceCheckUtils]: 13: Hoare triple {31808#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,376 INFO L290 TraceCheckUtils]: 14: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,376 INFO L290 TraceCheckUtils]: 15: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T5_E~0); {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,376 INFO L290 TraceCheckUtils]: 16: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,377 INFO L290 TraceCheckUtils]: 17: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,377 INFO L290 TraceCheckUtils]: 18: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,377 INFO L290 TraceCheckUtils]: 19: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,377 INFO L290 TraceCheckUtils]: 20: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,377 INFO L290 TraceCheckUtils]: 21: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,378 INFO L290 TraceCheckUtils]: 22: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,378 INFO L290 TraceCheckUtils]: 23: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_4~0); {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,378 INFO L290 TraceCheckUtils]: 24: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,378 INFO L290 TraceCheckUtils]: 25: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,379 INFO L290 TraceCheckUtils]: 26: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,379 INFO L290 TraceCheckUtils]: 27: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,379 INFO L290 TraceCheckUtils]: 28: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,379 INFO L290 TraceCheckUtils]: 29: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,380 INFO L290 TraceCheckUtils]: 30: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~m_pc~0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,380 INFO L290 TraceCheckUtils]: 31: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,380 INFO L290 TraceCheckUtils]: 32: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,380 INFO L290 TraceCheckUtils]: 33: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,381 INFO L290 TraceCheckUtils]: 34: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,381 INFO L290 TraceCheckUtils]: 35: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,381 INFO L290 TraceCheckUtils]: 36: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t1_pc~0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,381 INFO L290 TraceCheckUtils]: 37: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,381 INFO L290 TraceCheckUtils]: 38: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,382 INFO L290 TraceCheckUtils]: 39: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,382 INFO L290 TraceCheckUtils]: 40: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,382 INFO L290 TraceCheckUtils]: 41: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,383 INFO L290 TraceCheckUtils]: 42: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t2_pc~0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,383 INFO L290 TraceCheckUtils]: 43: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,383 INFO L290 TraceCheckUtils]: 44: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,383 INFO L290 TraceCheckUtils]: 45: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,383 INFO L290 TraceCheckUtils]: 46: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,384 INFO L290 TraceCheckUtils]: 47: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,384 INFO L290 TraceCheckUtils]: 48: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t3_pc~0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,384 INFO L290 TraceCheckUtils]: 49: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,384 INFO L290 TraceCheckUtils]: 50: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,385 INFO L290 TraceCheckUtils]: 51: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,385 INFO L290 TraceCheckUtils]: 52: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,385 INFO L290 TraceCheckUtils]: 53: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,385 INFO L290 TraceCheckUtils]: 54: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t4_pc~0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,386 INFO L290 TraceCheckUtils]: 55: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,386 INFO L290 TraceCheckUtils]: 56: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,386 INFO L290 TraceCheckUtils]: 57: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,386 INFO L290 TraceCheckUtils]: 58: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,387 INFO L290 TraceCheckUtils]: 59: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,387 INFO L290 TraceCheckUtils]: 60: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t5_pc~0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,387 INFO L290 TraceCheckUtils]: 61: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,387 INFO L290 TraceCheckUtils]: 62: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,388 INFO L290 TraceCheckUtils]: 63: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,388 INFO L290 TraceCheckUtils]: 64: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,388 INFO L290 TraceCheckUtils]: 65: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,388 INFO L290 TraceCheckUtils]: 66: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t6_pc~0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,389 INFO L290 TraceCheckUtils]: 67: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,389 INFO L290 TraceCheckUtils]: 68: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,389 INFO L290 TraceCheckUtils]: 69: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,389 INFO L290 TraceCheckUtils]: 70: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,389 INFO L290 TraceCheckUtils]: 71: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,390 INFO L290 TraceCheckUtils]: 72: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t7_pc~0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,390 INFO L290 TraceCheckUtils]: 73: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,390 INFO L290 TraceCheckUtils]: 74: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,390 INFO L290 TraceCheckUtils]: 75: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,391 INFO L290 TraceCheckUtils]: 76: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,391 INFO L290 TraceCheckUtils]: 77: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,391 INFO L290 TraceCheckUtils]: 78: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t8_pc~0); {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,391 INFO L290 TraceCheckUtils]: 79: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,392 INFO L290 TraceCheckUtils]: 80: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,392 INFO L290 TraceCheckUtils]: 81: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,392 INFO L290 TraceCheckUtils]: 82: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,392 INFO L290 TraceCheckUtils]: 83: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,393 INFO L290 TraceCheckUtils]: 84: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t9_pc~0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,393 INFO L290 TraceCheckUtils]: 85: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,393 INFO L290 TraceCheckUtils]: 86: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,393 INFO L290 TraceCheckUtils]: 87: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,394 INFO L290 TraceCheckUtils]: 88: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,394 INFO L290 TraceCheckUtils]: 89: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,394 INFO L290 TraceCheckUtils]: 90: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,394 INFO L290 TraceCheckUtils]: 91: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 92: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {31810#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 93: Hoare triple {31810#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~T3_E~0); {31809#false} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 94: Hoare triple {31809#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 95: Hoare triple {31809#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 96: Hoare triple {31809#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 97: Hoare triple {31809#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 98: Hoare triple {31809#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 99: Hoare triple {31809#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 100: Hoare triple {31809#false} assume 1 == ~E_1~0;~E_1~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 101: Hoare triple {31809#false} assume !(1 == ~E_2~0); {31809#false} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 102: Hoare triple {31809#false} assume 1 == ~E_3~0;~E_3~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,395 INFO L290 TraceCheckUtils]: 103: Hoare triple {31809#false} assume 1 == ~E_4~0;~E_4~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 104: Hoare triple {31809#false} assume 1 == ~E_5~0;~E_5~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 105: Hoare triple {31809#false} assume 1 == ~E_6~0;~E_6~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 106: Hoare triple {31809#false} assume 1 == ~E_7~0;~E_7~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 107: Hoare triple {31809#false} assume 1 == ~E_8~0;~E_8~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 108: Hoare triple {31809#false} assume 1 == ~E_9~0;~E_9~0 := 2; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 109: Hoare triple {31809#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 110: Hoare triple {31809#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 111: Hoare triple {31809#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 112: Hoare triple {31809#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 113: Hoare triple {31809#false} assume !(0 == start_simulation_~tmp~3#1); {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 114: Hoare triple {31809#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 115: Hoare triple {31809#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 116: Hoare triple {31809#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 117: Hoare triple {31809#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {31809#false} is VALID [2022-02-21 04:24:26,396 INFO L290 TraceCheckUtils]: 118: Hoare triple {31809#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {31809#false} is VALID [2022-02-21 04:24:26,397 INFO L290 TraceCheckUtils]: 119: Hoare triple {31809#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {31809#false} is VALID [2022-02-21 04:24:26,397 INFO L290 TraceCheckUtils]: 120: Hoare triple {31809#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {31809#false} is VALID [2022-02-21 04:24:26,397 INFO L290 TraceCheckUtils]: 121: Hoare triple {31809#false} assume !(0 != start_simulation_~tmp___0~1#1); {31809#false} is VALID [2022-02-21 04:24:26,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:26,397 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:26,397 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127384003] [2022-02-21 04:24:26,397 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2127384003] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:26,398 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:26,398 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:26,398 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180358535] [2022-02-21 04:24:26,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:26,398 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:26,398 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:26,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:26,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:26,399 INFO L87 Difference]: Start difference. First operand 1094 states and 1624 transitions. cyclomatic complexity: 531 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:27,137 INFO L93 Difference]: Finished difference Result 1094 states and 1623 transitions. [2022-02-21 04:24:27,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:27,137 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,200 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:27,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1623 transitions. [2022-02-21 04:24:27,235 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:27,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1623 transitions. [2022-02-21 04:24:27,270 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2022-02-21 04:24:27,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2022-02-21 04:24:27,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1623 transitions. [2022-02-21 04:24:27,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:27,272 INFO L681 BuchiCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2022-02-21 04:24:27,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1623 transitions. [2022-02-21 04:24:27,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1094. [2022-02-21 04:24:27,283 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:27,285 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1094 states and 1623 transitions. Second operand has 1094 states, 1094 states have (on average 1.483546617915905) internal successors, (1623), 1093 states have internal predecessors, (1623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,286 INFO L74 IsIncluded]: Start isIncluded. First operand 1094 states and 1623 transitions. Second operand has 1094 states, 1094 states have (on average 1.483546617915905) internal successors, (1623), 1093 states have internal predecessors, (1623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,287 INFO L87 Difference]: Start difference. First operand 1094 states and 1623 transitions. Second operand has 1094 states, 1094 states have (on average 1.483546617915905) internal successors, (1623), 1093 states have internal predecessors, (1623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:27,320 INFO L93 Difference]: Finished difference Result 1094 states and 1623 transitions. [2022-02-21 04:24:27,320 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1623 transitions. [2022-02-21 04:24:27,321 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:27,321 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:27,323 INFO L74 IsIncluded]: Start isIncluded. First operand has 1094 states, 1094 states have (on average 1.483546617915905) internal successors, (1623), 1093 states have internal predecessors, (1623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1623 transitions. [2022-02-21 04:24:27,323 INFO L87 Difference]: Start difference. First operand has 1094 states, 1094 states have (on average 1.483546617915905) internal successors, (1623), 1093 states have internal predecessors, (1623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1094 states and 1623 transitions. [2022-02-21 04:24:27,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:27,352 INFO L93 Difference]: Finished difference Result 1094 states and 1623 transitions. [2022-02-21 04:24:27,352 INFO L276 IsEmpty]: Start isEmpty. Operand 1094 states and 1623 transitions. [2022-02-21 04:24:27,354 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:27,354 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:27,354 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:27,354 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:27,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1094 states, 1094 states have (on average 1.483546617915905) internal successors, (1623), 1093 states have internal predecessors, (1623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1094 states to 1094 states and 1623 transitions. [2022-02-21 04:24:27,383 INFO L704 BuchiCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2022-02-21 04:24:27,384 INFO L587 BuchiCegarLoop]: Abstraction has 1094 states and 1623 transitions. [2022-02-21 04:24:27,384 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:27,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1094 states and 1623 transitions. [2022-02-21 04:24:27,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 969 [2022-02-21 04:24:27,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:27,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:27,388 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:27,388 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:27,389 INFO L791 eck$LassoCheckResult]: Stem: 33742#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 33743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 33343#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33344#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33890#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 33891#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33873#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33693#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33694#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33510#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33511#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33950#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33857#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33565#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33349#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33350#L922 assume !(0 == ~M_E~0); 33995#L922-2 assume !(0 == ~T1_E~0); 33996#L927-1 assume !(0 == ~T2_E~0); 33750#L932-1 assume !(0 == ~T3_E~0); 33635#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33636#L942-1 assume !(0 == ~T5_E~0); 33692#L947-1 assume !(0 == ~T6_E~0); 33754#L952-1 assume !(0 == ~T7_E~0); 33755#L957-1 assume !(0 == ~T8_E~0); 33815#L962-1 assume !(0 == ~T9_E~0); 33611#L967-1 assume !(0 == ~E_1~0); 33612#L972-1 assume !(0 == ~E_2~0); 33878#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 33879#L982-1 assume !(0 == ~E_4~0); 33119#L987-1 assume !(0 == ~E_5~0); 33120#L992-1 assume !(0 == ~E_6~0); 33128#L997-1 assume !(0 == ~E_7~0); 33542#L1002-1 assume !(0 == ~E_8~0); 33529#L1007-1 assume !(0 == ~E_9~0); 32917#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32918#L443 assume !(1 == ~m_pc~0); 33770#L443-2 is_master_triggered_~__retres1~0#1 := 0; 33761#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33762#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33283#L1140 assume !(0 != activate_threads_~tmp~1#1); 33032#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33033#L462 assume 1 == ~t1_pc~0; 33661#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33628#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33003#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33004#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 33491#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33492#L481 assume !(1 == ~t2_pc~0); 33278#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33277#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33632#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33371#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 33372#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33464#L500 assume 1 == ~t3_pc~0; 33674#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33675#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33865#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33866#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 32919#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32920#L519 assume 1 == ~t4_pc~0; 33218#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33219#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33463#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33323#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 33324#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33086#L538 assume !(1 == ~t5_pc~0); 33087#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 32993#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32994#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33262#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33263#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33800#L557 assume 1 == ~t6_pc~0; 33599#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33300#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33200#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33201#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 33325#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33978#L576 assume !(1 == ~t7_pc~0); 33287#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33288#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33532#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33533#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 33849#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33408#L595 assume 1 == ~t8_pc~0; 33409#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33867#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33868#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33717#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 33718#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33211#L614 assume !(1 == ~t9_pc~0); 33212#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 33111#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33112#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33291#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 33373#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33374#L1025 assume !(1 == ~M_E~0); 33620#L1025-2 assume !(1 == ~T1_E~0); 33673#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33795#L1035-1 assume !(1 == ~T3_E~0); 33367#L1040-1 assume !(1 == ~T4_E~0); 33368#L1045-1 assume !(1 == ~T5_E~0); 33273#L1050-1 assume !(1 == ~T6_E~0); 33274#L1055-1 assume !(1 == ~T7_E~0); 33095#L1060-1 assume !(1 == ~T8_E~0); 33096#L1065-1 assume !(1 == ~T9_E~0); 33159#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 33756#L1075-1 assume !(1 == ~E_2~0); 33757#L1080-1 assume !(1 == ~E_3~0); 33745#L1085-1 assume !(1 == ~E_4~0); 33746#L1090-1 assume !(1 == ~E_5~0); 33945#L1095-1 assume !(1 == ~E_6~0); 33779#L1100-1 assume !(1 == ~E_7~0); 33780#L1105-1 assume !(1 == ~E_8~0); 33068#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 33069#L1115-1 assume { :end_inline_reset_delta_events } true; 33230#L1396-2 [2022-02-21 04:24:27,389 INFO L793 eck$LassoCheckResult]: Loop: 33230#L1396-2 assume !false; 33313#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33342#L897 assume !false; 33985#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33892#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 32940#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 32941#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33940#L766 assume !(0 != eval_~tmp~0#1); 33926#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33010#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33011#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33525#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33254#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33255#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33433#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33060#L942-3 assume !(0 == ~T5_E~0); 33061#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33434#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33435#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33936#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33827#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33828#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33748#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33749#L982-3 assume !(0 == ~E_4~0); 33997#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33384#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33385#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33379#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33380#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33097#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33098#L443-30 assume 1 == ~m_pc~0; 33131#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33132#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33415#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33963#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33882#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33515#L462-30 assume !(1 == ~t1_pc~0); 33360#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 33361#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33863#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33864#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33904#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33502#L481-30 assume 1 == ~t2_pc~0; 33221#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33222#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33275#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33188#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33189#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33469#L500-30 assume 1 == ~t3_pc~0; 33226#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33227#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33289#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33290#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33452#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33453#L519-30 assume 1 == ~t4_pc~0; 33788#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33604#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32966#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32967#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33616#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33729#L538-30 assume 1 == ~t5_pc~0; 33107#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33108#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33406#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33407#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33184#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33185#L557-30 assume 1 == ~t6_pc~0; 32905#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32906#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33583#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33643#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 33209#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33210#L576-30 assume 1 == ~t7_pc~0; 33722#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32992#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33577#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33943#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33369#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33332#L595-30 assume !(1 == ~t8_pc~0); 33333#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 33268#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33001#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33002#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33944#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33980#L614-30 assume 1 == ~t9_pc~0; 33270#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33271#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33405#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33099#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33100#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33708#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33493#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33494#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33678#L1035-3 assume !(1 == ~T3_E~0); 33953#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33993#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33949#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33862#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32999#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33000#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33884#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33730#L1075-3 assume !(1 == ~E_2~0); 33731#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33954#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33875#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33876#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33895#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33896#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33147#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33148#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33907#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 33016#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33005#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 33006#L1415 assume !(0 == start_simulation_~tmp~3#1); 33607#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33608#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 33056#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33618#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 33797#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33998#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33666#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 33229#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 33230#L1396-2 [2022-02-21 04:24:27,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:27,389 INFO L85 PathProgramCache]: Analyzing trace with hash 760149089, now seen corresponding path program 1 times [2022-02-21 04:24:27,390 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:27,390 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [491535886] [2022-02-21 04:24:27,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:27,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:27,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:27,416 INFO L290 TraceCheckUtils]: 0: Hoare triple {36190#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,417 INFO L290 TraceCheckUtils]: 1: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,417 INFO L290 TraceCheckUtils]: 2: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,417 INFO L290 TraceCheckUtils]: 3: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,418 INFO L290 TraceCheckUtils]: 4: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,418 INFO L290 TraceCheckUtils]: 5: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,418 INFO L290 TraceCheckUtils]: 6: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,418 INFO L290 TraceCheckUtils]: 7: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,419 INFO L290 TraceCheckUtils]: 8: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,419 INFO L290 TraceCheckUtils]: 9: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,419 INFO L290 TraceCheckUtils]: 10: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,419 INFO L290 TraceCheckUtils]: 11: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,420 INFO L290 TraceCheckUtils]: 12: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,420 INFO L290 TraceCheckUtils]: 13: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,420 INFO L290 TraceCheckUtils]: 14: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,420 INFO L290 TraceCheckUtils]: 15: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume !(0 == ~M_E~0); {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,421 INFO L290 TraceCheckUtils]: 16: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume !(0 == ~T1_E~0); {36192#(= ~T2_E~0 ~T4_E~0)} is VALID [2022-02-21 04:24:27,421 INFO L290 TraceCheckUtils]: 17: Hoare triple {36192#(= ~T2_E~0 ~T4_E~0)} assume !(0 == ~T2_E~0); {36193#(not (= ~T4_E~0 0))} is VALID [2022-02-21 04:24:27,421 INFO L290 TraceCheckUtils]: 18: Hoare triple {36193#(not (= ~T4_E~0 0))} assume !(0 == ~T3_E~0); {36193#(not (= ~T4_E~0 0))} is VALID [2022-02-21 04:24:27,422 INFO L290 TraceCheckUtils]: 19: Hoare triple {36193#(not (= ~T4_E~0 0))} assume 0 == ~T4_E~0;~T4_E~0 := 1; {36191#false} is VALID [2022-02-21 04:24:27,422 INFO L290 TraceCheckUtils]: 20: Hoare triple {36191#false} assume !(0 == ~T5_E~0); {36191#false} is VALID [2022-02-21 04:24:27,422 INFO L290 TraceCheckUtils]: 21: Hoare triple {36191#false} assume !(0 == ~T6_E~0); {36191#false} is VALID [2022-02-21 04:24:27,422 INFO L290 TraceCheckUtils]: 22: Hoare triple {36191#false} assume !(0 == ~T7_E~0); {36191#false} is VALID [2022-02-21 04:24:27,422 INFO L290 TraceCheckUtils]: 23: Hoare triple {36191#false} assume !(0 == ~T8_E~0); {36191#false} is VALID [2022-02-21 04:24:27,422 INFO L290 TraceCheckUtils]: 24: Hoare triple {36191#false} assume !(0 == ~T9_E~0); {36191#false} is VALID [2022-02-21 04:24:27,422 INFO L290 TraceCheckUtils]: 25: Hoare triple {36191#false} assume !(0 == ~E_1~0); {36191#false} is VALID [2022-02-21 04:24:27,422 INFO L290 TraceCheckUtils]: 26: Hoare triple {36191#false} assume !(0 == ~E_2~0); {36191#false} is VALID [2022-02-21 04:24:27,423 INFO L290 TraceCheckUtils]: 27: Hoare triple {36191#false} assume 0 == ~E_3~0;~E_3~0 := 1; {36191#false} is VALID [2022-02-21 04:24:27,423 INFO L290 TraceCheckUtils]: 28: Hoare triple {36191#false} assume !(0 == ~E_4~0); {36191#false} is VALID [2022-02-21 04:24:27,423 INFO L290 TraceCheckUtils]: 29: Hoare triple {36191#false} assume !(0 == ~E_5~0); {36191#false} is VALID [2022-02-21 04:24:27,423 INFO L290 TraceCheckUtils]: 30: Hoare triple {36191#false} assume !(0 == ~E_6~0); {36191#false} is VALID [2022-02-21 04:24:27,423 INFO L290 TraceCheckUtils]: 31: Hoare triple {36191#false} assume !(0 == ~E_7~0); {36191#false} is VALID [2022-02-21 04:24:27,423 INFO L290 TraceCheckUtils]: 32: Hoare triple {36191#false} assume !(0 == ~E_8~0); {36191#false} is VALID [2022-02-21 04:24:27,423 INFO L290 TraceCheckUtils]: 33: Hoare triple {36191#false} assume !(0 == ~E_9~0); {36191#false} is VALID [2022-02-21 04:24:27,423 INFO L290 TraceCheckUtils]: 34: Hoare triple {36191#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {36191#false} is VALID [2022-02-21 04:24:27,423 INFO L290 TraceCheckUtils]: 35: Hoare triple {36191#false} assume !(1 == ~m_pc~0); {36191#false} is VALID [2022-02-21 04:24:27,424 INFO L290 TraceCheckUtils]: 36: Hoare triple {36191#false} is_master_triggered_~__retres1~0#1 := 0; {36191#false} is VALID [2022-02-21 04:24:27,424 INFO L290 TraceCheckUtils]: 37: Hoare triple {36191#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {36191#false} is VALID [2022-02-21 04:24:27,424 INFO L290 TraceCheckUtils]: 38: Hoare triple {36191#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {36191#false} is VALID [2022-02-21 04:24:27,424 INFO L290 TraceCheckUtils]: 39: Hoare triple {36191#false} assume !(0 != activate_threads_~tmp~1#1); {36191#false} is VALID [2022-02-21 04:24:27,424 INFO L290 TraceCheckUtils]: 40: Hoare triple {36191#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {36191#false} is VALID [2022-02-21 04:24:27,424 INFO L290 TraceCheckUtils]: 41: Hoare triple {36191#false} assume 1 == ~t1_pc~0; {36191#false} is VALID [2022-02-21 04:24:27,424 INFO L290 TraceCheckUtils]: 42: Hoare triple {36191#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {36191#false} is VALID [2022-02-21 04:24:27,424 INFO L290 TraceCheckUtils]: 43: Hoare triple {36191#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {36191#false} is VALID [2022-02-21 04:24:27,424 INFO L290 TraceCheckUtils]: 44: Hoare triple {36191#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {36191#false} is VALID [2022-02-21 04:24:27,425 INFO L290 TraceCheckUtils]: 45: Hoare triple {36191#false} assume !(0 != activate_threads_~tmp___0~0#1); {36191#false} is VALID [2022-02-21 04:24:27,425 INFO L290 TraceCheckUtils]: 46: Hoare triple {36191#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {36191#false} is VALID [2022-02-21 04:24:27,425 INFO L290 TraceCheckUtils]: 47: Hoare triple {36191#false} assume !(1 == ~t2_pc~0); {36191#false} is VALID [2022-02-21 04:24:27,425 INFO L290 TraceCheckUtils]: 48: Hoare triple {36191#false} is_transmit2_triggered_~__retres1~2#1 := 0; {36191#false} is VALID [2022-02-21 04:24:27,425 INFO L290 TraceCheckUtils]: 49: Hoare triple {36191#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {36191#false} is VALID [2022-02-21 04:24:27,425 INFO L290 TraceCheckUtils]: 50: Hoare triple {36191#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {36191#false} is VALID [2022-02-21 04:24:27,425 INFO L290 TraceCheckUtils]: 51: Hoare triple {36191#false} assume !(0 != activate_threads_~tmp___1~0#1); {36191#false} is VALID [2022-02-21 04:24:27,425 INFO L290 TraceCheckUtils]: 52: Hoare triple {36191#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {36191#false} is VALID [2022-02-21 04:24:27,426 INFO L290 TraceCheckUtils]: 53: Hoare triple {36191#false} assume 1 == ~t3_pc~0; {36191#false} is VALID [2022-02-21 04:24:27,426 INFO L290 TraceCheckUtils]: 54: Hoare triple {36191#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {36191#false} is VALID [2022-02-21 04:24:27,426 INFO L290 TraceCheckUtils]: 55: Hoare triple {36191#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {36191#false} is VALID [2022-02-21 04:24:27,426 INFO L290 TraceCheckUtils]: 56: Hoare triple {36191#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {36191#false} is VALID [2022-02-21 04:24:27,426 INFO L290 TraceCheckUtils]: 57: Hoare triple {36191#false} assume !(0 != activate_threads_~tmp___2~0#1); {36191#false} is VALID [2022-02-21 04:24:27,426 INFO L290 TraceCheckUtils]: 58: Hoare triple {36191#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {36191#false} is VALID [2022-02-21 04:24:27,426 INFO L290 TraceCheckUtils]: 59: Hoare triple {36191#false} assume 1 == ~t4_pc~0; {36191#false} is VALID [2022-02-21 04:24:27,426 INFO L290 TraceCheckUtils]: 60: Hoare triple {36191#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {36191#false} is VALID [2022-02-21 04:24:27,426 INFO L290 TraceCheckUtils]: 61: Hoare triple {36191#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {36191#false} is VALID [2022-02-21 04:24:27,427 INFO L290 TraceCheckUtils]: 62: Hoare triple {36191#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {36191#false} is VALID [2022-02-21 04:24:27,427 INFO L290 TraceCheckUtils]: 63: Hoare triple {36191#false} assume !(0 != activate_threads_~tmp___3~0#1); {36191#false} is VALID [2022-02-21 04:24:27,427 INFO L290 TraceCheckUtils]: 64: Hoare triple {36191#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {36191#false} is VALID [2022-02-21 04:24:27,427 INFO L290 TraceCheckUtils]: 65: Hoare triple {36191#false} assume !(1 == ~t5_pc~0); {36191#false} is VALID [2022-02-21 04:24:27,427 INFO L290 TraceCheckUtils]: 66: Hoare triple {36191#false} is_transmit5_triggered_~__retres1~5#1 := 0; {36191#false} is VALID [2022-02-21 04:24:27,427 INFO L290 TraceCheckUtils]: 67: Hoare triple {36191#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {36191#false} is VALID [2022-02-21 04:24:27,427 INFO L290 TraceCheckUtils]: 68: Hoare triple {36191#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {36191#false} is VALID [2022-02-21 04:24:27,427 INFO L290 TraceCheckUtils]: 69: Hoare triple {36191#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {36191#false} is VALID [2022-02-21 04:24:27,427 INFO L290 TraceCheckUtils]: 70: Hoare triple {36191#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {36191#false} is VALID [2022-02-21 04:24:27,428 INFO L290 TraceCheckUtils]: 71: Hoare triple {36191#false} assume 1 == ~t6_pc~0; {36191#false} is VALID [2022-02-21 04:24:27,428 INFO L290 TraceCheckUtils]: 72: Hoare triple {36191#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {36191#false} is VALID [2022-02-21 04:24:27,428 INFO L290 TraceCheckUtils]: 73: Hoare triple {36191#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {36191#false} is VALID [2022-02-21 04:24:27,428 INFO L290 TraceCheckUtils]: 74: Hoare triple {36191#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {36191#false} is VALID [2022-02-21 04:24:27,428 INFO L290 TraceCheckUtils]: 75: Hoare triple {36191#false} assume !(0 != activate_threads_~tmp___5~0#1); {36191#false} is VALID [2022-02-21 04:24:27,428 INFO L290 TraceCheckUtils]: 76: Hoare triple {36191#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {36191#false} is VALID [2022-02-21 04:24:27,428 INFO L290 TraceCheckUtils]: 77: Hoare triple {36191#false} assume !(1 == ~t7_pc~0); {36191#false} is VALID [2022-02-21 04:24:27,428 INFO L290 TraceCheckUtils]: 78: Hoare triple {36191#false} is_transmit7_triggered_~__retres1~7#1 := 0; {36191#false} is VALID [2022-02-21 04:24:27,428 INFO L290 TraceCheckUtils]: 79: Hoare triple {36191#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {36191#false} is VALID [2022-02-21 04:24:27,429 INFO L290 TraceCheckUtils]: 80: Hoare triple {36191#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {36191#false} is VALID [2022-02-21 04:24:27,429 INFO L290 TraceCheckUtils]: 81: Hoare triple {36191#false} assume !(0 != activate_threads_~tmp___6~0#1); {36191#false} is VALID [2022-02-21 04:24:27,429 INFO L290 TraceCheckUtils]: 82: Hoare triple {36191#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {36191#false} is VALID [2022-02-21 04:24:27,429 INFO L290 TraceCheckUtils]: 83: Hoare triple {36191#false} assume 1 == ~t8_pc~0; {36191#false} is VALID [2022-02-21 04:24:27,430 INFO L290 TraceCheckUtils]: 84: Hoare triple {36191#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {36191#false} is VALID [2022-02-21 04:24:27,431 INFO L290 TraceCheckUtils]: 85: Hoare triple {36191#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {36191#false} is VALID [2022-02-21 04:24:27,431 INFO L290 TraceCheckUtils]: 86: Hoare triple {36191#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {36191#false} is VALID [2022-02-21 04:24:27,431 INFO L290 TraceCheckUtils]: 87: Hoare triple {36191#false} assume !(0 != activate_threads_~tmp___7~0#1); {36191#false} is VALID [2022-02-21 04:24:27,431 INFO L290 TraceCheckUtils]: 88: Hoare triple {36191#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {36191#false} is VALID [2022-02-21 04:24:27,431 INFO L290 TraceCheckUtils]: 89: Hoare triple {36191#false} assume !(1 == ~t9_pc~0); {36191#false} is VALID [2022-02-21 04:24:27,431 INFO L290 TraceCheckUtils]: 90: Hoare triple {36191#false} is_transmit9_triggered_~__retres1~9#1 := 0; {36191#false} is VALID [2022-02-21 04:24:27,431 INFO L290 TraceCheckUtils]: 91: Hoare triple {36191#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {36191#false} is VALID [2022-02-21 04:24:27,431 INFO L290 TraceCheckUtils]: 92: Hoare triple {36191#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {36191#false} is VALID [2022-02-21 04:24:27,431 INFO L290 TraceCheckUtils]: 93: Hoare triple {36191#false} assume !(0 != activate_threads_~tmp___8~0#1); {36191#false} is VALID [2022-02-21 04:24:27,432 INFO L290 TraceCheckUtils]: 94: Hoare triple {36191#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {36191#false} is VALID [2022-02-21 04:24:27,432 INFO L290 TraceCheckUtils]: 95: Hoare triple {36191#false} assume !(1 == ~M_E~0); {36191#false} is VALID [2022-02-21 04:24:27,432 INFO L290 TraceCheckUtils]: 96: Hoare triple {36191#false} assume !(1 == ~T1_E~0); {36191#false} is VALID [2022-02-21 04:24:27,432 INFO L290 TraceCheckUtils]: 97: Hoare triple {36191#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {36191#false} is VALID [2022-02-21 04:24:27,432 INFO L290 TraceCheckUtils]: 98: Hoare triple {36191#false} assume !(1 == ~T3_E~0); {36191#false} is VALID [2022-02-21 04:24:27,432 INFO L290 TraceCheckUtils]: 99: Hoare triple {36191#false} assume !(1 == ~T4_E~0); {36191#false} is VALID [2022-02-21 04:24:27,432 INFO L290 TraceCheckUtils]: 100: Hoare triple {36191#false} assume !(1 == ~T5_E~0); {36191#false} is VALID [2022-02-21 04:24:27,432 INFO L290 TraceCheckUtils]: 101: Hoare triple {36191#false} assume !(1 == ~T6_E~0); {36191#false} is VALID [2022-02-21 04:24:27,432 INFO L290 TraceCheckUtils]: 102: Hoare triple {36191#false} assume !(1 == ~T7_E~0); {36191#false} is VALID [2022-02-21 04:24:27,433 INFO L290 TraceCheckUtils]: 103: Hoare triple {36191#false} assume !(1 == ~T8_E~0); {36191#false} is VALID [2022-02-21 04:24:27,433 INFO L290 TraceCheckUtils]: 104: Hoare triple {36191#false} assume !(1 == ~T9_E~0); {36191#false} is VALID [2022-02-21 04:24:27,433 INFO L290 TraceCheckUtils]: 105: Hoare triple {36191#false} assume 1 == ~E_1~0;~E_1~0 := 2; {36191#false} is VALID [2022-02-21 04:24:27,433 INFO L290 TraceCheckUtils]: 106: Hoare triple {36191#false} assume !(1 == ~E_2~0); {36191#false} is VALID [2022-02-21 04:24:27,433 INFO L290 TraceCheckUtils]: 107: Hoare triple {36191#false} assume !(1 == ~E_3~0); {36191#false} is VALID [2022-02-21 04:24:27,433 INFO L290 TraceCheckUtils]: 108: Hoare triple {36191#false} assume !(1 == ~E_4~0); {36191#false} is VALID [2022-02-21 04:24:27,433 INFO L290 TraceCheckUtils]: 109: Hoare triple {36191#false} assume !(1 == ~E_5~0); {36191#false} is VALID [2022-02-21 04:24:27,433 INFO L290 TraceCheckUtils]: 110: Hoare triple {36191#false} assume !(1 == ~E_6~0); {36191#false} is VALID [2022-02-21 04:24:27,434 INFO L290 TraceCheckUtils]: 111: Hoare triple {36191#false} assume !(1 == ~E_7~0); {36191#false} is VALID [2022-02-21 04:24:27,434 INFO L290 TraceCheckUtils]: 112: Hoare triple {36191#false} assume !(1 == ~E_8~0); {36191#false} is VALID [2022-02-21 04:24:27,434 INFO L290 TraceCheckUtils]: 113: Hoare triple {36191#false} assume 1 == ~E_9~0;~E_9~0 := 2; {36191#false} is VALID [2022-02-21 04:24:27,434 INFO L290 TraceCheckUtils]: 114: Hoare triple {36191#false} assume { :end_inline_reset_delta_events } true; {36191#false} is VALID [2022-02-21 04:24:27,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:27,434 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:27,435 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [491535886] [2022-02-21 04:24:27,435 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [491535886] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:27,435 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:27,435 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:27,435 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [926009285] [2022-02-21 04:24:27,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:27,436 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:27,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:27,436 INFO L85 PathProgramCache]: Analyzing trace with hash -2011313997, now seen corresponding path program 1 times [2022-02-21 04:24:27,436 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:27,436 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289989884] [2022-02-21 04:24:27,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:27,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:27,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:27,475 INFO L290 TraceCheckUtils]: 0: Hoare triple {36194#true} assume !false; {36194#true} is VALID [2022-02-21 04:24:27,476 INFO L290 TraceCheckUtils]: 1: Hoare triple {36194#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {36194#true} is VALID [2022-02-21 04:24:27,476 INFO L290 TraceCheckUtils]: 2: Hoare triple {36194#true} assume !false; {36194#true} is VALID [2022-02-21 04:24:27,476 INFO L290 TraceCheckUtils]: 3: Hoare triple {36194#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {36194#true} is VALID [2022-02-21 04:24:27,476 INFO L290 TraceCheckUtils]: 4: Hoare triple {36194#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {36194#true} is VALID [2022-02-21 04:24:27,476 INFO L290 TraceCheckUtils]: 5: Hoare triple {36194#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {36194#true} is VALID [2022-02-21 04:24:27,476 INFO L290 TraceCheckUtils]: 6: Hoare triple {36194#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {36194#true} is VALID [2022-02-21 04:24:27,476 INFO L290 TraceCheckUtils]: 7: Hoare triple {36194#true} assume !(0 != eval_~tmp~0#1); {36194#true} is VALID [2022-02-21 04:24:27,477 INFO L290 TraceCheckUtils]: 8: Hoare triple {36194#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {36194#true} is VALID [2022-02-21 04:24:27,477 INFO L290 TraceCheckUtils]: 9: Hoare triple {36194#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {36194#true} is VALID [2022-02-21 04:24:27,477 INFO L290 TraceCheckUtils]: 10: Hoare triple {36194#true} assume 0 == ~M_E~0;~M_E~0 := 1; {36194#true} is VALID [2022-02-21 04:24:27,477 INFO L290 TraceCheckUtils]: 11: Hoare triple {36194#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {36194#true} is VALID [2022-02-21 04:24:27,477 INFO L290 TraceCheckUtils]: 12: Hoare triple {36194#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {36194#true} is VALID [2022-02-21 04:24:27,477 INFO L290 TraceCheckUtils]: 13: Hoare triple {36194#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,478 INFO L290 TraceCheckUtils]: 14: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,478 INFO L290 TraceCheckUtils]: 15: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T5_E~0); {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,478 INFO L290 TraceCheckUtils]: 16: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,478 INFO L290 TraceCheckUtils]: 17: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,479 INFO L290 TraceCheckUtils]: 18: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,479 INFO L290 TraceCheckUtils]: 19: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,479 INFO L290 TraceCheckUtils]: 20: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,479 INFO L290 TraceCheckUtils]: 21: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,480 INFO L290 TraceCheckUtils]: 22: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,480 INFO L290 TraceCheckUtils]: 23: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_4~0); {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,480 INFO L290 TraceCheckUtils]: 24: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,480 INFO L290 TraceCheckUtils]: 25: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,481 INFO L290 TraceCheckUtils]: 26: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,481 INFO L290 TraceCheckUtils]: 27: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,481 INFO L290 TraceCheckUtils]: 28: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,482 INFO L290 TraceCheckUtils]: 29: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,482 INFO L290 TraceCheckUtils]: 30: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~m_pc~0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,482 INFO L290 TraceCheckUtils]: 31: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,482 INFO L290 TraceCheckUtils]: 32: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,483 INFO L290 TraceCheckUtils]: 33: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,483 INFO L290 TraceCheckUtils]: 34: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,483 INFO L290 TraceCheckUtils]: 35: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,483 INFO L290 TraceCheckUtils]: 36: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t1_pc~0); {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,484 INFO L290 TraceCheckUtils]: 37: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,484 INFO L290 TraceCheckUtils]: 38: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,484 INFO L290 TraceCheckUtils]: 39: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,484 INFO L290 TraceCheckUtils]: 40: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,485 INFO L290 TraceCheckUtils]: 41: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,485 INFO L290 TraceCheckUtils]: 42: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t2_pc~0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,485 INFO L290 TraceCheckUtils]: 43: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,485 INFO L290 TraceCheckUtils]: 44: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,486 INFO L290 TraceCheckUtils]: 45: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,486 INFO L290 TraceCheckUtils]: 46: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,486 INFO L290 TraceCheckUtils]: 47: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,487 INFO L290 TraceCheckUtils]: 48: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t3_pc~0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,487 INFO L290 TraceCheckUtils]: 49: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,487 INFO L290 TraceCheckUtils]: 50: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,487 INFO L290 TraceCheckUtils]: 51: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,488 INFO L290 TraceCheckUtils]: 52: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,488 INFO L290 TraceCheckUtils]: 53: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,488 INFO L290 TraceCheckUtils]: 54: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t4_pc~0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,488 INFO L290 TraceCheckUtils]: 55: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,489 INFO L290 TraceCheckUtils]: 56: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,489 INFO L290 TraceCheckUtils]: 57: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,489 INFO L290 TraceCheckUtils]: 58: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,489 INFO L290 TraceCheckUtils]: 59: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,490 INFO L290 TraceCheckUtils]: 60: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t5_pc~0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,490 INFO L290 TraceCheckUtils]: 61: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,490 INFO L290 TraceCheckUtils]: 62: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,490 INFO L290 TraceCheckUtils]: 63: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,491 INFO L290 TraceCheckUtils]: 64: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,491 INFO L290 TraceCheckUtils]: 65: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,491 INFO L290 TraceCheckUtils]: 66: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t6_pc~0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,491 INFO L290 TraceCheckUtils]: 67: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,492 INFO L290 TraceCheckUtils]: 68: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,492 INFO L290 TraceCheckUtils]: 69: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,492 INFO L290 TraceCheckUtils]: 70: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,492 INFO L290 TraceCheckUtils]: 71: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,493 INFO L290 TraceCheckUtils]: 72: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t7_pc~0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,493 INFO L290 TraceCheckUtils]: 73: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,493 INFO L290 TraceCheckUtils]: 74: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,493 INFO L290 TraceCheckUtils]: 75: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,494 INFO L290 TraceCheckUtils]: 76: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,494 INFO L290 TraceCheckUtils]: 77: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,494 INFO L290 TraceCheckUtils]: 78: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t8_pc~0); {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,494 INFO L290 TraceCheckUtils]: 79: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,495 INFO L290 TraceCheckUtils]: 80: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,495 INFO L290 TraceCheckUtils]: 81: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,495 INFO L290 TraceCheckUtils]: 82: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,495 INFO L290 TraceCheckUtils]: 83: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,496 INFO L290 TraceCheckUtils]: 84: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t9_pc~0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,496 INFO L290 TraceCheckUtils]: 85: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,496 INFO L290 TraceCheckUtils]: 86: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,496 INFO L290 TraceCheckUtils]: 87: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,497 INFO L290 TraceCheckUtils]: 88: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,497 INFO L290 TraceCheckUtils]: 89: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,497 INFO L290 TraceCheckUtils]: 90: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,497 INFO L290 TraceCheckUtils]: 91: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,498 INFO L290 TraceCheckUtils]: 92: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {36196#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:27,498 INFO L290 TraceCheckUtils]: 93: Hoare triple {36196#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~T3_E~0); {36195#false} is VALID [2022-02-21 04:24:27,498 INFO L290 TraceCheckUtils]: 94: Hoare triple {36195#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,498 INFO L290 TraceCheckUtils]: 95: Hoare triple {36195#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,498 INFO L290 TraceCheckUtils]: 96: Hoare triple {36195#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,498 INFO L290 TraceCheckUtils]: 97: Hoare triple {36195#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,499 INFO L290 TraceCheckUtils]: 98: Hoare triple {36195#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,499 INFO L290 TraceCheckUtils]: 99: Hoare triple {36195#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,499 INFO L290 TraceCheckUtils]: 100: Hoare triple {36195#false} assume 1 == ~E_1~0;~E_1~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,499 INFO L290 TraceCheckUtils]: 101: Hoare triple {36195#false} assume !(1 == ~E_2~0); {36195#false} is VALID [2022-02-21 04:24:27,499 INFO L290 TraceCheckUtils]: 102: Hoare triple {36195#false} assume 1 == ~E_3~0;~E_3~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,499 INFO L290 TraceCheckUtils]: 103: Hoare triple {36195#false} assume 1 == ~E_4~0;~E_4~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,499 INFO L290 TraceCheckUtils]: 104: Hoare triple {36195#false} assume 1 == ~E_5~0;~E_5~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,499 INFO L290 TraceCheckUtils]: 105: Hoare triple {36195#false} assume 1 == ~E_6~0;~E_6~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,500 INFO L290 TraceCheckUtils]: 106: Hoare triple {36195#false} assume 1 == ~E_7~0;~E_7~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,500 INFO L290 TraceCheckUtils]: 107: Hoare triple {36195#false} assume 1 == ~E_8~0;~E_8~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,500 INFO L290 TraceCheckUtils]: 108: Hoare triple {36195#false} assume 1 == ~E_9~0;~E_9~0 := 2; {36195#false} is VALID [2022-02-21 04:24:27,500 INFO L290 TraceCheckUtils]: 109: Hoare triple {36195#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {36195#false} is VALID [2022-02-21 04:24:27,500 INFO L290 TraceCheckUtils]: 110: Hoare triple {36195#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {36195#false} is VALID [2022-02-21 04:24:27,500 INFO L290 TraceCheckUtils]: 111: Hoare triple {36195#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {36195#false} is VALID [2022-02-21 04:24:27,500 INFO L290 TraceCheckUtils]: 112: Hoare triple {36195#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {36195#false} is VALID [2022-02-21 04:24:27,500 INFO L290 TraceCheckUtils]: 113: Hoare triple {36195#false} assume !(0 == start_simulation_~tmp~3#1); {36195#false} is VALID [2022-02-21 04:24:27,501 INFO L290 TraceCheckUtils]: 114: Hoare triple {36195#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {36195#false} is VALID [2022-02-21 04:24:27,501 INFO L290 TraceCheckUtils]: 115: Hoare triple {36195#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {36195#false} is VALID [2022-02-21 04:24:27,501 INFO L290 TraceCheckUtils]: 116: Hoare triple {36195#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {36195#false} is VALID [2022-02-21 04:24:27,501 INFO L290 TraceCheckUtils]: 117: Hoare triple {36195#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {36195#false} is VALID [2022-02-21 04:24:27,501 INFO L290 TraceCheckUtils]: 118: Hoare triple {36195#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {36195#false} is VALID [2022-02-21 04:24:27,501 INFO L290 TraceCheckUtils]: 119: Hoare triple {36195#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {36195#false} is VALID [2022-02-21 04:24:27,501 INFO L290 TraceCheckUtils]: 120: Hoare triple {36195#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {36195#false} is VALID [2022-02-21 04:24:27,501 INFO L290 TraceCheckUtils]: 121: Hoare triple {36195#false} assume !(0 != start_simulation_~tmp___0~1#1); {36195#false} is VALID [2022-02-21 04:24:27,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:27,502 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:27,502 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289989884] [2022-02-21 04:24:27,502 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289989884] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:27,502 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:27,502 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:27,502 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [86448719] [2022-02-21 04:24:27,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:27,503 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:27,503 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:27,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:27,504 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:27,504 INFO L87 Difference]: Start difference. First operand 1094 states and 1623 transitions. cyclomatic complexity: 530 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:29,526 INFO L93 Difference]: Finished difference Result 2080 states and 3079 transitions. [2022-02-21 04:24:29,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:29,526 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,608 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:29,608 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2080 states and 3079 transitions. [2022-02-21 04:24:29,720 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1938 [2022-02-21 04:24:29,832 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2080 states to 2080 states and 3079 transitions. [2022-02-21 04:24:29,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2080 [2022-02-21 04:24:29,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2080 [2022-02-21 04:24:29,834 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2080 states and 3079 transitions. [2022-02-21 04:24:29,836 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:29,836 INFO L681 BuchiCegarLoop]: Abstraction has 2080 states and 3079 transitions. [2022-02-21 04:24:29,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2080 states and 3079 transitions. [2022-02-21 04:24:29,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2080 to 2080. [2022-02-21 04:24:29,859 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:29,861 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2080 states and 3079 transitions. Second operand has 2080 states, 2080 states have (on average 1.4802884615384615) internal successors, (3079), 2079 states have internal predecessors, (3079), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,862 INFO L74 IsIncluded]: Start isIncluded. First operand 2080 states and 3079 transitions. Second operand has 2080 states, 2080 states have (on average 1.4802884615384615) internal successors, (3079), 2079 states have internal predecessors, (3079), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,863 INFO L87 Difference]: Start difference. First operand 2080 states and 3079 transitions. Second operand has 2080 states, 2080 states have (on average 1.4802884615384615) internal successors, (3079), 2079 states have internal predecessors, (3079), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:29,967 INFO L93 Difference]: Finished difference Result 2080 states and 3079 transitions. [2022-02-21 04:24:29,967 INFO L276 IsEmpty]: Start isEmpty. Operand 2080 states and 3079 transitions. [2022-02-21 04:24:29,969 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:29,969 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:29,972 INFO L74 IsIncluded]: Start isIncluded. First operand has 2080 states, 2080 states have (on average 1.4802884615384615) internal successors, (3079), 2079 states have internal predecessors, (3079), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2080 states and 3079 transitions. [2022-02-21 04:24:29,973 INFO L87 Difference]: Start difference. First operand has 2080 states, 2080 states have (on average 1.4802884615384615) internal successors, (3079), 2079 states have internal predecessors, (3079), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2080 states and 3079 transitions. [2022-02-21 04:24:30,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,096 INFO L93 Difference]: Finished difference Result 2080 states and 3079 transitions. [2022-02-21 04:24:30,096 INFO L276 IsEmpty]: Start isEmpty. Operand 2080 states and 3079 transitions. [2022-02-21 04:24:30,098 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:30,098 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:30,098 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:30,098 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:30,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2080 states, 2080 states have (on average 1.4802884615384615) internal successors, (3079), 2079 states have internal predecessors, (3079), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2080 states to 2080 states and 3079 transitions. [2022-02-21 04:24:30,193 INFO L704 BuchiCegarLoop]: Abstraction has 2080 states and 3079 transitions. [2022-02-21 04:24:30,193 INFO L587 BuchiCegarLoop]: Abstraction has 2080 states and 3079 transitions. [2022-02-21 04:24:30,193 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:24:30,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2080 states and 3079 transitions. [2022-02-21 04:24:30,196 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1938 [2022-02-21 04:24:30,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:30,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:30,197 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:30,197 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:30,198 INFO L791 eck$LassoCheckResult]: Stem: 39132#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 39133#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 38718#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38719#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39295#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 39296#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39273#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39080#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39081#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38886#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38887#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39361#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39256#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38943#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38724#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38725#L922 assume !(0 == ~M_E~0); 39426#L922-2 assume !(0 == ~T1_E~0); 39427#L927-1 assume !(0 == ~T2_E~0); 39140#L932-1 assume !(0 == ~T3_E~0); 39017#L937-1 assume !(0 == ~T4_E~0); 39018#L942-1 assume !(0 == ~T5_E~0); 39079#L947-1 assume !(0 == ~T6_E~0); 39144#L952-1 assume !(0 == ~T7_E~0); 39145#L957-1 assume !(0 == ~T8_E~0); 39214#L962-1 assume !(0 == ~T9_E~0); 38991#L967-1 assume !(0 == ~E_1~0); 38992#L972-1 assume !(0 == ~E_2~0); 39278#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 39279#L982-1 assume !(0 == ~E_4~0); 38493#L987-1 assume !(0 == ~E_5~0); 38494#L992-1 assume !(0 == ~E_6~0); 38502#L997-1 assume !(0 == ~E_7~0); 38922#L1002-1 assume !(0 == ~E_8~0); 38907#L1007-1 assume !(0 == ~E_9~0); 38291#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38292#L443 assume !(1 == ~m_pc~0); 39160#L443-2 is_master_triggered_~__retres1~0#1 := 0; 39151#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39152#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 38658#L1140 assume !(0 != activate_threads_~tmp~1#1); 38406#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38407#L462 assume 1 == ~t1_pc~0; 39043#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39013#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38377#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38378#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 38867#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38868#L481 assume !(1 == ~t2_pc~0); 38653#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38652#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39014#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38746#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 38747#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38842#L500 assume 1 == ~t3_pc~0; 39056#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39057#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39265#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39266#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 38296#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38297#L519 assume 1 == ~t4_pc~0; 38596#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38597#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38839#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38700#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 38701#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38460#L538 assume !(1 == ~t5_pc~0); 38461#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 38367#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38368#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38637#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38638#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39197#L557 assume 1 == ~t6_pc~0; 38978#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38675#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38577#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38578#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 38702#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39397#L576 assume !(1 == ~t7_pc~0); 38662#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 38663#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38909#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38910#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 39248#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38786#L595 assume 1 == ~t8_pc~0; 38787#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39267#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39268#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39106#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 39107#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38586#L614 assume !(1 == ~t9_pc~0); 38587#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 38485#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38486#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38666#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 38748#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38749#L1025 assume !(1 == ~M_E~0); 39002#L1025-2 assume !(1 == ~T1_E~0); 39055#L1030-1 assume !(1 == ~T2_E~0); 39189#L1035-1 assume !(1 == ~T3_E~0); 39585#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38744#L1045-1 assume !(1 == ~T5_E~0); 38648#L1050-1 assume !(1 == ~T6_E~0); 38649#L1055-1 assume !(1 == ~T7_E~0); 38469#L1060-1 assume !(1 == ~T8_E~0); 38470#L1065-1 assume !(1 == ~T9_E~0); 38534#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 39146#L1075-1 assume !(1 == ~E_2~0); 39147#L1080-1 assume !(1 == ~E_3~0); 39135#L1085-1 assume !(1 == ~E_4~0); 39136#L1090-1 assume !(1 == ~E_5~0); 39355#L1095-1 assume !(1 == ~E_6~0); 39408#L1100-1 assume !(1 == ~E_7~0); 39180#L1105-1 assume !(1 == ~E_8~0); 38442#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 38443#L1115-1 assume { :end_inline_reset_delta_events } true; 38605#L1396-2 [2022-02-21 04:24:30,198 INFO L793 eck$LassoCheckResult]: Loop: 38605#L1396-2 assume !false; 38691#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39406#L897 assume !false; 39407#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 39431#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 39439#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 39377#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 39378#L766 assume !(0 != eval_~tmp~0#1); 39334#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38384#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38385#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39410#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39411#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39437#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39964#L937-3 assume !(0 == ~T4_E~0); 39963#L942-3 assume !(0 == ~T5_E~0); 39962#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39961#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39960#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39959#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39958#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 39957#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39956#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39955#L982-3 assume !(0 == ~E_4~0); 39954#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39953#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39952#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 39951#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 39950#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39949#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39948#L443-30 assume 1 == ~m_pc~0; 39946#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39945#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39944#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39943#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39942#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39941#L462-30 assume !(1 == ~t1_pc~0); 39939#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 39938#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39937#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39936#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39935#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39934#L481-30 assume 1 == ~t2_pc~0; 39932#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39931#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39930#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39929#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39928#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39927#L500-30 assume !(1 == ~t3_pc~0); 39925#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 39924#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39923#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39922#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39921#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39920#L519-30 assume 1 == ~t4_pc~0; 39918#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39917#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39916#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39915#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39914#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39913#L538-30 assume !(1 == ~t5_pc~0); 39911#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 39910#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39909#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39908#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39907#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39906#L557-30 assume 1 == ~t6_pc~0; 39904#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39903#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39902#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39901#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 39900#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39899#L576-30 assume 1 == ~t7_pc~0; 39897#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39896#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39895#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39894#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39893#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39892#L595-30 assume 1 == ~t8_pc~0; 39890#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39889#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39888#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39887#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39886#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39885#L614-30 assume 1 == ~t9_pc~0; 39883#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 39882#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39881#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39880#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39879#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39878#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39877#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39876#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39060#L1035-3 assume !(1 == ~T3_E~0); 39875#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39421#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39874#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39873#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39872#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39294#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39287#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39120#L1075-3 assume !(1 == ~E_2~0); 39121#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39364#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39275#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 39276#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 39300#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 39301#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38521#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38522#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 39314#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 38390#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 39794#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 39793#L1415 assume !(0 == start_simulation_~tmp~3#1); 38989#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 38990#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 39476#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 39191#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 39192#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39435#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39050#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 38604#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 38605#L1396-2 [2022-02-21 04:24:30,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:30,199 INFO L85 PathProgramCache]: Analyzing trace with hash -1269658465, now seen corresponding path program 1 times [2022-02-21 04:24:30,199 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:30,199 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214251269] [2022-02-21 04:24:30,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:30,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:30,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:30,218 INFO L290 TraceCheckUtils]: 0: Hoare triple {44522#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,219 INFO L290 TraceCheckUtils]: 1: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,219 INFO L290 TraceCheckUtils]: 2: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,234 INFO L290 TraceCheckUtils]: 3: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,234 INFO L290 TraceCheckUtils]: 4: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,234 INFO L290 TraceCheckUtils]: 5: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,235 INFO L290 TraceCheckUtils]: 6: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,235 INFO L290 TraceCheckUtils]: 7: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,235 INFO L290 TraceCheckUtils]: 8: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,235 INFO L290 TraceCheckUtils]: 9: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,236 INFO L290 TraceCheckUtils]: 10: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,236 INFO L290 TraceCheckUtils]: 11: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,236 INFO L290 TraceCheckUtils]: 12: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,237 INFO L290 TraceCheckUtils]: 13: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,237 INFO L290 TraceCheckUtils]: 14: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,237 INFO L290 TraceCheckUtils]: 15: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~M_E~0); {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,237 INFO L290 TraceCheckUtils]: 16: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T1_E~0); {44524#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:24:30,238 INFO L290 TraceCheckUtils]: 17: Hoare triple {44524#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T2_E~0); {44525#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:30,238 INFO L290 TraceCheckUtils]: 18: Hoare triple {44525#(not (= ~E_3~0 0))} assume !(0 == ~T3_E~0); {44525#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:30,238 INFO L290 TraceCheckUtils]: 19: Hoare triple {44525#(not (= ~E_3~0 0))} assume !(0 == ~T4_E~0); {44525#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:30,238 INFO L290 TraceCheckUtils]: 20: Hoare triple {44525#(not (= ~E_3~0 0))} assume !(0 == ~T5_E~0); {44525#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:30,239 INFO L290 TraceCheckUtils]: 21: Hoare triple {44525#(not (= ~E_3~0 0))} assume !(0 == ~T6_E~0); {44525#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:30,239 INFO L290 TraceCheckUtils]: 22: Hoare triple {44525#(not (= ~E_3~0 0))} assume !(0 == ~T7_E~0); {44525#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:30,239 INFO L290 TraceCheckUtils]: 23: Hoare triple {44525#(not (= ~E_3~0 0))} assume !(0 == ~T8_E~0); {44525#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:30,239 INFO L290 TraceCheckUtils]: 24: Hoare triple {44525#(not (= ~E_3~0 0))} assume !(0 == ~T9_E~0); {44525#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:30,240 INFO L290 TraceCheckUtils]: 25: Hoare triple {44525#(not (= ~E_3~0 0))} assume !(0 == ~E_1~0); {44525#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:30,240 INFO L290 TraceCheckUtils]: 26: Hoare triple {44525#(not (= ~E_3~0 0))} assume !(0 == ~E_2~0); {44525#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:24:30,240 INFO L290 TraceCheckUtils]: 27: Hoare triple {44525#(not (= ~E_3~0 0))} assume 0 == ~E_3~0;~E_3~0 := 1; {44523#false} is VALID [2022-02-21 04:24:30,240 INFO L290 TraceCheckUtils]: 28: Hoare triple {44523#false} assume !(0 == ~E_4~0); {44523#false} is VALID [2022-02-21 04:24:30,240 INFO L290 TraceCheckUtils]: 29: Hoare triple {44523#false} assume !(0 == ~E_5~0); {44523#false} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 30: Hoare triple {44523#false} assume !(0 == ~E_6~0); {44523#false} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 31: Hoare triple {44523#false} assume !(0 == ~E_7~0); {44523#false} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 32: Hoare triple {44523#false} assume !(0 == ~E_8~0); {44523#false} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 33: Hoare triple {44523#false} assume !(0 == ~E_9~0); {44523#false} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 34: Hoare triple {44523#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {44523#false} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 35: Hoare triple {44523#false} assume !(1 == ~m_pc~0); {44523#false} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 36: Hoare triple {44523#false} is_master_triggered_~__retres1~0#1 := 0; {44523#false} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 37: Hoare triple {44523#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {44523#false} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 38: Hoare triple {44523#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {44523#false} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 39: Hoare triple {44523#false} assume !(0 != activate_threads_~tmp~1#1); {44523#false} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 40: Hoare triple {44523#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {44523#false} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 41: Hoare triple {44523#false} assume 1 == ~t1_pc~0; {44523#false} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 42: Hoare triple {44523#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {44523#false} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 43: Hoare triple {44523#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {44523#false} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 44: Hoare triple {44523#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {44523#false} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 45: Hoare triple {44523#false} assume !(0 != activate_threads_~tmp___0~0#1); {44523#false} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 46: Hoare triple {44523#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {44523#false} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 47: Hoare triple {44523#false} assume !(1 == ~t2_pc~0); {44523#false} is VALID [2022-02-21 04:24:30,243 INFO L290 TraceCheckUtils]: 48: Hoare triple {44523#false} is_transmit2_triggered_~__retres1~2#1 := 0; {44523#false} is VALID [2022-02-21 04:24:30,243 INFO L290 TraceCheckUtils]: 49: Hoare triple {44523#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {44523#false} is VALID [2022-02-21 04:24:30,243 INFO L290 TraceCheckUtils]: 50: Hoare triple {44523#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {44523#false} is VALID [2022-02-21 04:24:30,243 INFO L290 TraceCheckUtils]: 51: Hoare triple {44523#false} assume !(0 != activate_threads_~tmp___1~0#1); {44523#false} is VALID [2022-02-21 04:24:30,243 INFO L290 TraceCheckUtils]: 52: Hoare triple {44523#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {44523#false} is VALID [2022-02-21 04:24:30,243 INFO L290 TraceCheckUtils]: 53: Hoare triple {44523#false} assume 1 == ~t3_pc~0; {44523#false} is VALID [2022-02-21 04:24:30,243 INFO L290 TraceCheckUtils]: 54: Hoare triple {44523#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {44523#false} is VALID [2022-02-21 04:24:30,243 INFO L290 TraceCheckUtils]: 55: Hoare triple {44523#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {44523#false} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 56: Hoare triple {44523#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {44523#false} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 57: Hoare triple {44523#false} assume !(0 != activate_threads_~tmp___2~0#1); {44523#false} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 58: Hoare triple {44523#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {44523#false} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 59: Hoare triple {44523#false} assume 1 == ~t4_pc~0; {44523#false} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 60: Hoare triple {44523#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {44523#false} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 61: Hoare triple {44523#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {44523#false} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 62: Hoare triple {44523#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {44523#false} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 63: Hoare triple {44523#false} assume !(0 != activate_threads_~tmp___3~0#1); {44523#false} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 64: Hoare triple {44523#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {44523#false} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 65: Hoare triple {44523#false} assume !(1 == ~t5_pc~0); {44523#false} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 66: Hoare triple {44523#false} is_transmit5_triggered_~__retres1~5#1 := 0; {44523#false} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 67: Hoare triple {44523#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {44523#false} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 68: Hoare triple {44523#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {44523#false} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 69: Hoare triple {44523#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {44523#false} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 70: Hoare triple {44523#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {44523#false} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 71: Hoare triple {44523#false} assume 1 == ~t6_pc~0; {44523#false} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 72: Hoare triple {44523#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {44523#false} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 73: Hoare triple {44523#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {44523#false} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 74: Hoare triple {44523#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {44523#false} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 75: Hoare triple {44523#false} assume !(0 != activate_threads_~tmp___5~0#1); {44523#false} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 76: Hoare triple {44523#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {44523#false} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 77: Hoare triple {44523#false} assume !(1 == ~t7_pc~0); {44523#false} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 78: Hoare triple {44523#false} is_transmit7_triggered_~__retres1~7#1 := 0; {44523#false} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 79: Hoare triple {44523#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {44523#false} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 80: Hoare triple {44523#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {44523#false} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 81: Hoare triple {44523#false} assume !(0 != activate_threads_~tmp___6~0#1); {44523#false} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 82: Hoare triple {44523#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {44523#false} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 83: Hoare triple {44523#false} assume 1 == ~t8_pc~0; {44523#false} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 84: Hoare triple {44523#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {44523#false} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 85: Hoare triple {44523#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {44523#false} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 86: Hoare triple {44523#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {44523#false} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 87: Hoare triple {44523#false} assume !(0 != activate_threads_~tmp___7~0#1); {44523#false} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 88: Hoare triple {44523#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {44523#false} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 89: Hoare triple {44523#false} assume !(1 == ~t9_pc~0); {44523#false} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 90: Hoare triple {44523#false} is_transmit9_triggered_~__retres1~9#1 := 0; {44523#false} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 91: Hoare triple {44523#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {44523#false} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 92: Hoare triple {44523#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {44523#false} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 93: Hoare triple {44523#false} assume !(0 != activate_threads_~tmp___8~0#1); {44523#false} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 94: Hoare triple {44523#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {44523#false} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 95: Hoare triple {44523#false} assume !(1 == ~M_E~0); {44523#false} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 96: Hoare triple {44523#false} assume !(1 == ~T1_E~0); {44523#false} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 97: Hoare triple {44523#false} assume !(1 == ~T2_E~0); {44523#false} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 98: Hoare triple {44523#false} assume !(1 == ~T3_E~0); {44523#false} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 99: Hoare triple {44523#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {44523#false} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 100: Hoare triple {44523#false} assume !(1 == ~T5_E~0); {44523#false} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 101: Hoare triple {44523#false} assume !(1 == ~T6_E~0); {44523#false} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 102: Hoare triple {44523#false} assume !(1 == ~T7_E~0); {44523#false} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 103: Hoare triple {44523#false} assume !(1 == ~T8_E~0); {44523#false} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 104: Hoare triple {44523#false} assume !(1 == ~T9_E~0); {44523#false} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 105: Hoare triple {44523#false} assume 1 == ~E_1~0;~E_1~0 := 2; {44523#false} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 106: Hoare triple {44523#false} assume !(1 == ~E_2~0); {44523#false} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 107: Hoare triple {44523#false} assume !(1 == ~E_3~0); {44523#false} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 108: Hoare triple {44523#false} assume !(1 == ~E_4~0); {44523#false} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 109: Hoare triple {44523#false} assume !(1 == ~E_5~0); {44523#false} is VALID [2022-02-21 04:24:30,250 INFO L290 TraceCheckUtils]: 110: Hoare triple {44523#false} assume !(1 == ~E_6~0); {44523#false} is VALID [2022-02-21 04:24:30,250 INFO L290 TraceCheckUtils]: 111: Hoare triple {44523#false} assume !(1 == ~E_7~0); {44523#false} is VALID [2022-02-21 04:24:30,250 INFO L290 TraceCheckUtils]: 112: Hoare triple {44523#false} assume !(1 == ~E_8~0); {44523#false} is VALID [2022-02-21 04:24:30,250 INFO L290 TraceCheckUtils]: 113: Hoare triple {44523#false} assume 1 == ~E_9~0;~E_9~0 := 2; {44523#false} is VALID [2022-02-21 04:24:30,250 INFO L290 TraceCheckUtils]: 114: Hoare triple {44523#false} assume { :end_inline_reset_delta_events } true; {44523#false} is VALID [2022-02-21 04:24:30,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:30,251 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:30,251 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [214251269] [2022-02-21 04:24:30,251 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [214251269] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:30,251 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:30,251 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:30,251 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824466782] [2022-02-21 04:24:30,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:30,252 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:30,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:30,253 INFO L85 PathProgramCache]: Analyzing trace with hash 777468816, now seen corresponding path program 1 times [2022-02-21 04:24:30,253 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:30,253 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1191648253] [2022-02-21 04:24:30,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:30,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:30,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:30,280 INFO L290 TraceCheckUtils]: 0: Hoare triple {44526#true} assume !false; {44526#true} is VALID [2022-02-21 04:24:30,280 INFO L290 TraceCheckUtils]: 1: Hoare triple {44526#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {44526#true} is VALID [2022-02-21 04:24:30,280 INFO L290 TraceCheckUtils]: 2: Hoare triple {44526#true} assume !false; {44526#true} is VALID [2022-02-21 04:24:30,280 INFO L290 TraceCheckUtils]: 3: Hoare triple {44526#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {44526#true} is VALID [2022-02-21 04:24:30,280 INFO L290 TraceCheckUtils]: 4: Hoare triple {44526#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {44526#true} is VALID [2022-02-21 04:24:30,280 INFO L290 TraceCheckUtils]: 5: Hoare triple {44526#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {44526#true} is VALID [2022-02-21 04:24:30,281 INFO L290 TraceCheckUtils]: 6: Hoare triple {44526#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {44526#true} is VALID [2022-02-21 04:24:30,281 INFO L290 TraceCheckUtils]: 7: Hoare triple {44526#true} assume !(0 != eval_~tmp~0#1); {44526#true} is VALID [2022-02-21 04:24:30,281 INFO L290 TraceCheckUtils]: 8: Hoare triple {44526#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {44526#true} is VALID [2022-02-21 04:24:30,281 INFO L290 TraceCheckUtils]: 9: Hoare triple {44526#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {44526#true} is VALID [2022-02-21 04:24:30,281 INFO L290 TraceCheckUtils]: 10: Hoare triple {44526#true} assume 0 == ~M_E~0;~M_E~0 := 1; {44526#true} is VALID [2022-02-21 04:24:30,281 INFO L290 TraceCheckUtils]: 11: Hoare triple {44526#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {44526#true} is VALID [2022-02-21 04:24:30,281 INFO L290 TraceCheckUtils]: 12: Hoare triple {44526#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {44526#true} is VALID [2022-02-21 04:24:30,282 INFO L290 TraceCheckUtils]: 13: Hoare triple {44526#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,282 INFO L290 TraceCheckUtils]: 14: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T4_E~0); {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,282 INFO L290 TraceCheckUtils]: 15: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T5_E~0); {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,282 INFO L290 TraceCheckUtils]: 16: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,283 INFO L290 TraceCheckUtils]: 17: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,283 INFO L290 TraceCheckUtils]: 18: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,283 INFO L290 TraceCheckUtils]: 19: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,283 INFO L290 TraceCheckUtils]: 20: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,284 INFO L290 TraceCheckUtils]: 21: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,284 INFO L290 TraceCheckUtils]: 22: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,284 INFO L290 TraceCheckUtils]: 23: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_4~0); {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,284 INFO L290 TraceCheckUtils]: 24: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,285 INFO L290 TraceCheckUtils]: 25: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,285 INFO L290 TraceCheckUtils]: 26: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,285 INFO L290 TraceCheckUtils]: 27: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,285 INFO L290 TraceCheckUtils]: 28: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,286 INFO L290 TraceCheckUtils]: 29: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,286 INFO L290 TraceCheckUtils]: 30: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~m_pc~0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,286 INFO L290 TraceCheckUtils]: 31: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,286 INFO L290 TraceCheckUtils]: 32: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,287 INFO L290 TraceCheckUtils]: 33: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,287 INFO L290 TraceCheckUtils]: 34: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,287 INFO L290 TraceCheckUtils]: 35: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,287 INFO L290 TraceCheckUtils]: 36: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t1_pc~0); {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,288 INFO L290 TraceCheckUtils]: 37: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,288 INFO L290 TraceCheckUtils]: 38: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,288 INFO L290 TraceCheckUtils]: 39: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,288 INFO L290 TraceCheckUtils]: 40: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,289 INFO L290 TraceCheckUtils]: 41: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,289 INFO L290 TraceCheckUtils]: 42: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t2_pc~0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,289 INFO L290 TraceCheckUtils]: 43: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,289 INFO L290 TraceCheckUtils]: 44: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,290 INFO L290 TraceCheckUtils]: 45: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,290 INFO L290 TraceCheckUtils]: 46: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,290 INFO L290 TraceCheckUtils]: 47: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,294 INFO L290 TraceCheckUtils]: 48: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t3_pc~0); {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,295 INFO L290 TraceCheckUtils]: 49: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,295 INFO L290 TraceCheckUtils]: 50: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,295 INFO L290 TraceCheckUtils]: 51: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,296 INFO L290 TraceCheckUtils]: 52: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,296 INFO L290 TraceCheckUtils]: 53: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,296 INFO L290 TraceCheckUtils]: 54: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t4_pc~0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,296 INFO L290 TraceCheckUtils]: 55: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,297 INFO L290 TraceCheckUtils]: 56: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,297 INFO L290 TraceCheckUtils]: 57: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,297 INFO L290 TraceCheckUtils]: 58: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,297 INFO L290 TraceCheckUtils]: 59: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,298 INFO L290 TraceCheckUtils]: 60: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t5_pc~0); {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,298 INFO L290 TraceCheckUtils]: 61: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,298 INFO L290 TraceCheckUtils]: 62: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,298 INFO L290 TraceCheckUtils]: 63: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,299 INFO L290 TraceCheckUtils]: 64: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,299 INFO L290 TraceCheckUtils]: 65: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,299 INFO L290 TraceCheckUtils]: 66: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t6_pc~0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,299 INFO L290 TraceCheckUtils]: 67: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,299 INFO L290 TraceCheckUtils]: 68: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,300 INFO L290 TraceCheckUtils]: 69: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,300 INFO L290 TraceCheckUtils]: 70: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,300 INFO L290 TraceCheckUtils]: 71: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,300 INFO L290 TraceCheckUtils]: 72: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t7_pc~0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,301 INFO L290 TraceCheckUtils]: 73: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,301 INFO L290 TraceCheckUtils]: 74: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,301 INFO L290 TraceCheckUtils]: 75: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,302 INFO L290 TraceCheckUtils]: 76: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,302 INFO L290 TraceCheckUtils]: 77: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,302 INFO L290 TraceCheckUtils]: 78: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t8_pc~0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,302 INFO L290 TraceCheckUtils]: 79: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,303 INFO L290 TraceCheckUtils]: 80: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,303 INFO L290 TraceCheckUtils]: 81: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,303 INFO L290 TraceCheckUtils]: 82: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,303 INFO L290 TraceCheckUtils]: 83: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,304 INFO L290 TraceCheckUtils]: 84: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t9_pc~0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,304 INFO L290 TraceCheckUtils]: 85: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,304 INFO L290 TraceCheckUtils]: 86: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,304 INFO L290 TraceCheckUtils]: 87: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,305 INFO L290 TraceCheckUtils]: 88: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,305 INFO L290 TraceCheckUtils]: 89: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,305 INFO L290 TraceCheckUtils]: 90: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,305 INFO L290 TraceCheckUtils]: 91: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,306 INFO L290 TraceCheckUtils]: 92: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {44528#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:30,306 INFO L290 TraceCheckUtils]: 93: Hoare triple {44528#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~T3_E~0); {44527#false} is VALID [2022-02-21 04:24:30,306 INFO L290 TraceCheckUtils]: 94: Hoare triple {44527#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,306 INFO L290 TraceCheckUtils]: 95: Hoare triple {44527#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,306 INFO L290 TraceCheckUtils]: 96: Hoare triple {44527#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,306 INFO L290 TraceCheckUtils]: 97: Hoare triple {44527#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,306 INFO L290 TraceCheckUtils]: 98: Hoare triple {44527#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,306 INFO L290 TraceCheckUtils]: 99: Hoare triple {44527#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,307 INFO L290 TraceCheckUtils]: 100: Hoare triple {44527#false} assume 1 == ~E_1~0;~E_1~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,307 INFO L290 TraceCheckUtils]: 101: Hoare triple {44527#false} assume !(1 == ~E_2~0); {44527#false} is VALID [2022-02-21 04:24:30,307 INFO L290 TraceCheckUtils]: 102: Hoare triple {44527#false} assume 1 == ~E_3~0;~E_3~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,307 INFO L290 TraceCheckUtils]: 103: Hoare triple {44527#false} assume 1 == ~E_4~0;~E_4~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,307 INFO L290 TraceCheckUtils]: 104: Hoare triple {44527#false} assume 1 == ~E_5~0;~E_5~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,307 INFO L290 TraceCheckUtils]: 105: Hoare triple {44527#false} assume 1 == ~E_6~0;~E_6~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,307 INFO L290 TraceCheckUtils]: 106: Hoare triple {44527#false} assume 1 == ~E_7~0;~E_7~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,307 INFO L290 TraceCheckUtils]: 107: Hoare triple {44527#false} assume 1 == ~E_8~0;~E_8~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,308 INFO L290 TraceCheckUtils]: 108: Hoare triple {44527#false} assume 1 == ~E_9~0;~E_9~0 := 2; {44527#false} is VALID [2022-02-21 04:24:30,308 INFO L290 TraceCheckUtils]: 109: Hoare triple {44527#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {44527#false} is VALID [2022-02-21 04:24:30,308 INFO L290 TraceCheckUtils]: 110: Hoare triple {44527#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {44527#false} is VALID [2022-02-21 04:24:30,308 INFO L290 TraceCheckUtils]: 111: Hoare triple {44527#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {44527#false} is VALID [2022-02-21 04:24:30,308 INFO L290 TraceCheckUtils]: 112: Hoare triple {44527#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {44527#false} is VALID [2022-02-21 04:24:30,308 INFO L290 TraceCheckUtils]: 113: Hoare triple {44527#false} assume !(0 == start_simulation_~tmp~3#1); {44527#false} is VALID [2022-02-21 04:24:30,308 INFO L290 TraceCheckUtils]: 114: Hoare triple {44527#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {44527#false} is VALID [2022-02-21 04:24:30,308 INFO L290 TraceCheckUtils]: 115: Hoare triple {44527#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {44527#false} is VALID [2022-02-21 04:24:30,308 INFO L290 TraceCheckUtils]: 116: Hoare triple {44527#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {44527#false} is VALID [2022-02-21 04:24:30,309 INFO L290 TraceCheckUtils]: 117: Hoare triple {44527#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {44527#false} is VALID [2022-02-21 04:24:30,309 INFO L290 TraceCheckUtils]: 118: Hoare triple {44527#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {44527#false} is VALID [2022-02-21 04:24:30,309 INFO L290 TraceCheckUtils]: 119: Hoare triple {44527#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {44527#false} is VALID [2022-02-21 04:24:30,309 INFO L290 TraceCheckUtils]: 120: Hoare triple {44527#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {44527#false} is VALID [2022-02-21 04:24:30,309 INFO L290 TraceCheckUtils]: 121: Hoare triple {44527#false} assume !(0 != start_simulation_~tmp___0~1#1); {44527#false} is VALID [2022-02-21 04:24:30,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:30,310 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:30,310 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1191648253] [2022-02-21 04:24:30,310 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1191648253] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:30,310 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:30,310 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:30,310 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945904917] [2022-02-21 04:24:30,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:30,311 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:30,311 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:30,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:30,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:30,311 INFO L87 Difference]: Start difference. First operand 2080 states and 3079 transitions. cyclomatic complexity: 1001 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:32,510 INFO L93 Difference]: Finished difference Result 3898 states and 5766 transitions. [2022-02-21 04:24:32,510 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:32,511 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,587 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:32,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3898 states and 5766 transitions. [2022-02-21 04:24:32,938 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3732 [2022-02-21 04:24:33,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3898 states to 3898 states and 5766 transitions. [2022-02-21 04:24:33,298 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3898 [2022-02-21 04:24:33,299 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3898 [2022-02-21 04:24:33,299 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3898 states and 5766 transitions. [2022-02-21 04:24:33,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:33,302 INFO L681 BuchiCegarLoop]: Abstraction has 3898 states and 5766 transitions. [2022-02-21 04:24:33,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3898 states and 5766 transitions. [2022-02-21 04:24:33,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3898 to 3896. [2022-02-21 04:24:33,344 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:33,349 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3898 states and 5766 transitions. Second operand has 3896 states, 3896 states have (on average 1.4794661190965093) internal successors, (5764), 3895 states have internal predecessors, (5764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,353 INFO L74 IsIncluded]: Start isIncluded. First operand 3898 states and 5766 transitions. Second operand has 3896 states, 3896 states have (on average 1.4794661190965093) internal successors, (5764), 3895 states have internal predecessors, (5764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,357 INFO L87 Difference]: Start difference. First operand 3898 states and 5766 transitions. Second operand has 3896 states, 3896 states have (on average 1.4794661190965093) internal successors, (5764), 3895 states have internal predecessors, (5764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:33,707 INFO L93 Difference]: Finished difference Result 3898 states and 5766 transitions. [2022-02-21 04:24:33,708 INFO L276 IsEmpty]: Start isEmpty. Operand 3898 states and 5766 transitions. [2022-02-21 04:24:33,710 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:33,710 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:33,715 INFO L74 IsIncluded]: Start isIncluded. First operand has 3896 states, 3896 states have (on average 1.4794661190965093) internal successors, (5764), 3895 states have internal predecessors, (5764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3898 states and 5766 transitions. [2022-02-21 04:24:33,717 INFO L87 Difference]: Start difference. First operand has 3896 states, 3896 states have (on average 1.4794661190965093) internal successors, (5764), 3895 states have internal predecessors, (5764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3898 states and 5766 transitions. [2022-02-21 04:24:34,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:34,054 INFO L93 Difference]: Finished difference Result 3898 states and 5766 transitions. [2022-02-21 04:24:34,055 INFO L276 IsEmpty]: Start isEmpty. Operand 3898 states and 5766 transitions. [2022-02-21 04:24:34,059 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:34,059 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:34,059 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:34,059 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:34,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3896 states, 3896 states have (on average 1.4794661190965093) internal successors, (5764), 3895 states have internal predecessors, (5764), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3896 states to 3896 states and 5764 transitions. [2022-02-21 04:24:34,436 INFO L704 BuchiCegarLoop]: Abstraction has 3896 states and 5764 transitions. [2022-02-21 04:24:34,436 INFO L587 BuchiCegarLoop]: Abstraction has 3896 states and 5764 transitions. [2022-02-21 04:24:34,436 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:24:34,436 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3896 states and 5764 transitions. [2022-02-21 04:24:34,445 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3732 [2022-02-21 04:24:34,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:34,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:34,447 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:34,447 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:34,447 INFO L791 eck$LassoCheckResult]: Stem: 49278#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 49279#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 48869#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48870#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49436#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 49437#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49417#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49227#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49228#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49038#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49039#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49504#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49399#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49094#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48876#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48877#L922 assume !(0 == ~M_E~0); 49569#L922-2 assume !(0 == ~T1_E~0); 49570#L927-1 assume !(0 == ~T2_E~0); 49287#L932-1 assume !(0 == ~T3_E~0); 49166#L937-1 assume !(0 == ~T4_E~0); 49167#L942-1 assume !(0 == ~T5_E~0); 49226#L947-1 assume !(0 == ~T6_E~0); 49291#L952-1 assume !(0 == ~T7_E~0); 49292#L957-1 assume !(0 == ~T8_E~0); 49356#L962-1 assume !(0 == ~T9_E~0); 49142#L967-1 assume !(0 == ~E_1~0); 49143#L972-1 assume !(0 == ~E_2~0); 49422#L977-1 assume !(0 == ~E_3~0); 49423#L982-1 assume !(0 == ~E_4~0); 48643#L987-1 assume !(0 == ~E_5~0); 48644#L992-1 assume !(0 == ~E_6~0); 48652#L997-1 assume !(0 == ~E_7~0); 49071#L1002-1 assume !(0 == ~E_8~0); 49058#L1007-1 assume !(0 == ~E_9~0); 48441#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48442#L443 assume !(1 == ~m_pc~0); 49307#L443-2 is_master_triggered_~__retres1~0#1 := 0; 49298#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49299#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48808#L1140 assume !(0 != activate_threads_~tmp~1#1); 48556#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48557#L462 assume 1 == ~t1_pc~0; 49192#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49159#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48527#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48528#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 49019#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49020#L481 assume !(1 == ~t2_pc~0); 48803#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48802#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49163#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48899#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 48900#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48993#L500 assume 1 == ~t3_pc~0; 49206#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49207#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49409#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49410#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 48443#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48444#L519 assume 1 == ~t4_pc~0; 48743#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48744#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48992#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48849#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 48850#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48610#L538 assume !(1 == ~t5_pc~0); 48611#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48517#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48518#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48787#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48788#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49338#L557 assume 1 == ~t6_pc~0; 49130#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48826#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48722#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48723#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 48851#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49537#L576 assume !(1 == ~t7_pc~0); 48812#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 48813#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49061#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49062#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 49391#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48936#L595 assume 1 == ~t8_pc~0; 48937#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49411#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49412#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49252#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 49253#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48736#L614 assume !(1 == ~t9_pc~0); 48737#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 48634#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48635#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48816#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 48901#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48902#L1025 assume !(1 == ~M_E~0); 49151#L1025-2 assume !(1 == ~T1_E~0); 49205#L1030-1 assume !(1 == ~T2_E~0); 49332#L1035-1 assume !(1 == ~T3_E~0); 48894#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48895#L1045-1 assume !(1 == ~T5_E~0); 48798#L1050-1 assume !(1 == ~T6_E~0); 48799#L1055-1 assume !(1 == ~T7_E~0); 48619#L1060-1 assume !(1 == ~T8_E~0); 48620#L1065-1 assume !(1 == ~T9_E~0); 48683#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 49293#L1075-1 assume !(1 == ~E_2~0); 49294#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 49697#L1085-1 assume !(1 == ~E_4~0); 49670#L1090-1 assume !(1 == ~E_5~0); 49668#L1095-1 assume !(1 == ~E_6~0); 49653#L1100-1 assume !(1 == ~E_7~0); 49638#L1105-1 assume !(1 == ~E_8~0); 49627#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 49618#L1115-1 assume { :end_inline_reset_delta_events } true; 49611#L1396-2 [2022-02-21 04:24:34,448 INFO L793 eck$LassoCheckResult]: Loop: 49611#L1396-2 assume !false; 49605#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49600#L897 assume !false; 49599#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 49598#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 49588#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 49587#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49585#L766 assume !(0 != eval_~tmp~0#1); 49584#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49583#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49582#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49581#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49579#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49580#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51309#L937-3 assume !(0 == ~T4_E~0); 51307#L942-3 assume !(0 == ~T5_E~0); 51306#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51302#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51227#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51217#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 51209#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 51010#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51005#L977-3 assume !(0 == ~E_3~0); 51003#L982-3 assume !(0 == ~E_4~0); 51001#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51000#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50999#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50997#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50995#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50993#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50992#L443-30 assume 1 == ~m_pc~0; 50990#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50988#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50986#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50983#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50981#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50898#L462-30 assume !(1 == ~t1_pc~0); 50704#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 50702#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50701#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50697#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50695#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50693#L481-30 assume 1 == ~t2_pc~0; 50678#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50676#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50625#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50581#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50579#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50576#L500-30 assume !(1 == ~t3_pc~0); 50573#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 50571#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50569#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50567#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50565#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50530#L519-30 assume 1 == ~t4_pc~0; 50525#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50523#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50475#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50473#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50471#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50428#L538-30 assume !(1 == ~t5_pc~0); 50424#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 50422#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50420#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50418#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 50385#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50383#L557-30 assume 1 == ~t6_pc~0; 50380#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50341#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50303#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50300#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 50261#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50260#L576-30 assume 1 == ~t7_pc~0; 50193#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50191#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50189#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50188#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50187#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50186#L595-30 assume 1 == ~t8_pc~0; 50184#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50183#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50181#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50178#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50137#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50134#L614-30 assume 1 == ~t9_pc~0; 50131#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50129#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50127#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50126#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50124#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49242#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49022#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49023#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49211#L1035-3 assume !(1 == ~T3_E~0); 50024#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49564#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50019#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50017#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50015#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 50013#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50011#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50009#L1075-3 assume !(1 == ~E_2~0); 49963#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49959#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49958#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49956#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49921#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49919#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49917#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 49857#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 49814#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 49812#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 49810#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 49772#L1415 assume !(0 == start_simulation_~tmp~3#1); 49736#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 49706#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 49671#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 49669#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 49654#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49639#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49628#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 49619#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 49611#L1396-2 [2022-02-21 04:24:34,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:34,448 INFO L85 PathProgramCache]: Analyzing trace with hash -1455005537, now seen corresponding path program 1 times [2022-02-21 04:24:34,448 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:34,449 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [451403562] [2022-02-21 04:24:34,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:34,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:34,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:34,475 INFO L290 TraceCheckUtils]: 0: Hoare triple {60124#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,475 INFO L290 TraceCheckUtils]: 1: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,476 INFO L290 TraceCheckUtils]: 2: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,476 INFO L290 TraceCheckUtils]: 3: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,476 INFO L290 TraceCheckUtils]: 4: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,477 INFO L290 TraceCheckUtils]: 5: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,477 INFO L290 TraceCheckUtils]: 6: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,477 INFO L290 TraceCheckUtils]: 7: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,477 INFO L290 TraceCheckUtils]: 8: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,478 INFO L290 TraceCheckUtils]: 9: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,478 INFO L290 TraceCheckUtils]: 10: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,478 INFO L290 TraceCheckUtils]: 11: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,479 INFO L290 TraceCheckUtils]: 12: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,479 INFO L290 TraceCheckUtils]: 13: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,479 INFO L290 TraceCheckUtils]: 14: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,480 INFO L290 TraceCheckUtils]: 15: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,480 INFO L290 TraceCheckUtils]: 16: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,480 INFO L290 TraceCheckUtils]: 17: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,481 INFO L290 TraceCheckUtils]: 18: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,481 INFO L290 TraceCheckUtils]: 19: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,481 INFO L290 TraceCheckUtils]: 20: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T5_E~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,481 INFO L290 TraceCheckUtils]: 21: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T6_E~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,482 INFO L290 TraceCheckUtils]: 22: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T7_E~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,482 INFO L290 TraceCheckUtils]: 23: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T8_E~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,482 INFO L290 TraceCheckUtils]: 24: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T9_E~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,483 INFO L290 TraceCheckUtils]: 25: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,483 INFO L290 TraceCheckUtils]: 26: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,483 INFO L290 TraceCheckUtils]: 27: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,484 INFO L290 TraceCheckUtils]: 28: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,484 INFO L290 TraceCheckUtils]: 29: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_5~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,484 INFO L290 TraceCheckUtils]: 30: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_6~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,484 INFO L290 TraceCheckUtils]: 31: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_7~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,485 INFO L290 TraceCheckUtils]: 32: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_8~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,485 INFO L290 TraceCheckUtils]: 33: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_9~0); {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,485 INFO L290 TraceCheckUtils]: 34: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {60126#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:34,486 INFO L290 TraceCheckUtils]: 35: Hoare triple {60126#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {60127#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:34,486 INFO L290 TraceCheckUtils]: 36: Hoare triple {60127#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {60127#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:34,486 INFO L290 TraceCheckUtils]: 37: Hoare triple {60127#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {60127#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:34,486 INFO L290 TraceCheckUtils]: 38: Hoare triple {60127#(not (= ~t1_pc~0 1))} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {60127#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:34,487 INFO L290 TraceCheckUtils]: 39: Hoare triple {60127#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {60127#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:34,487 INFO L290 TraceCheckUtils]: 40: Hoare triple {60127#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {60127#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:34,487 INFO L290 TraceCheckUtils]: 41: Hoare triple {60127#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {60125#false} is VALID [2022-02-21 04:24:34,487 INFO L290 TraceCheckUtils]: 42: Hoare triple {60125#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {60125#false} is VALID [2022-02-21 04:24:34,487 INFO L290 TraceCheckUtils]: 43: Hoare triple {60125#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {60125#false} is VALID [2022-02-21 04:24:34,488 INFO L290 TraceCheckUtils]: 44: Hoare triple {60125#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {60125#false} is VALID [2022-02-21 04:24:34,488 INFO L290 TraceCheckUtils]: 45: Hoare triple {60125#false} assume !(0 != activate_threads_~tmp___0~0#1); {60125#false} is VALID [2022-02-21 04:24:34,488 INFO L290 TraceCheckUtils]: 46: Hoare triple {60125#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {60125#false} is VALID [2022-02-21 04:24:34,488 INFO L290 TraceCheckUtils]: 47: Hoare triple {60125#false} assume !(1 == ~t2_pc~0); {60125#false} is VALID [2022-02-21 04:24:34,488 INFO L290 TraceCheckUtils]: 48: Hoare triple {60125#false} is_transmit2_triggered_~__retres1~2#1 := 0; {60125#false} is VALID [2022-02-21 04:24:34,504 INFO L290 TraceCheckUtils]: 49: Hoare triple {60125#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {60125#false} is VALID [2022-02-21 04:24:34,504 INFO L290 TraceCheckUtils]: 50: Hoare triple {60125#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {60125#false} is VALID [2022-02-21 04:24:34,504 INFO L290 TraceCheckUtils]: 51: Hoare triple {60125#false} assume !(0 != activate_threads_~tmp___1~0#1); {60125#false} is VALID [2022-02-21 04:24:34,504 INFO L290 TraceCheckUtils]: 52: Hoare triple {60125#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {60125#false} is VALID [2022-02-21 04:24:34,504 INFO L290 TraceCheckUtils]: 53: Hoare triple {60125#false} assume 1 == ~t3_pc~0; {60125#false} is VALID [2022-02-21 04:24:34,504 INFO L290 TraceCheckUtils]: 54: Hoare triple {60125#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {60125#false} is VALID [2022-02-21 04:24:34,504 INFO L290 TraceCheckUtils]: 55: Hoare triple {60125#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {60125#false} is VALID [2022-02-21 04:24:34,504 INFO L290 TraceCheckUtils]: 56: Hoare triple {60125#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {60125#false} is VALID [2022-02-21 04:24:34,505 INFO L290 TraceCheckUtils]: 57: Hoare triple {60125#false} assume !(0 != activate_threads_~tmp___2~0#1); {60125#false} is VALID [2022-02-21 04:24:34,505 INFO L290 TraceCheckUtils]: 58: Hoare triple {60125#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {60125#false} is VALID [2022-02-21 04:24:34,505 INFO L290 TraceCheckUtils]: 59: Hoare triple {60125#false} assume 1 == ~t4_pc~0; {60125#false} is VALID [2022-02-21 04:24:34,505 INFO L290 TraceCheckUtils]: 60: Hoare triple {60125#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {60125#false} is VALID [2022-02-21 04:24:34,505 INFO L290 TraceCheckUtils]: 61: Hoare triple {60125#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {60125#false} is VALID [2022-02-21 04:24:34,505 INFO L290 TraceCheckUtils]: 62: Hoare triple {60125#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {60125#false} is VALID [2022-02-21 04:24:34,505 INFO L290 TraceCheckUtils]: 63: Hoare triple {60125#false} assume !(0 != activate_threads_~tmp___3~0#1); {60125#false} is VALID [2022-02-21 04:24:34,505 INFO L290 TraceCheckUtils]: 64: Hoare triple {60125#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {60125#false} is VALID [2022-02-21 04:24:34,506 INFO L290 TraceCheckUtils]: 65: Hoare triple {60125#false} assume !(1 == ~t5_pc~0); {60125#false} is VALID [2022-02-21 04:24:34,506 INFO L290 TraceCheckUtils]: 66: Hoare triple {60125#false} is_transmit5_triggered_~__retres1~5#1 := 0; {60125#false} is VALID [2022-02-21 04:24:34,506 INFO L290 TraceCheckUtils]: 67: Hoare triple {60125#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {60125#false} is VALID [2022-02-21 04:24:34,506 INFO L290 TraceCheckUtils]: 68: Hoare triple {60125#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {60125#false} is VALID [2022-02-21 04:24:34,506 INFO L290 TraceCheckUtils]: 69: Hoare triple {60125#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {60125#false} is VALID [2022-02-21 04:24:34,506 INFO L290 TraceCheckUtils]: 70: Hoare triple {60125#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {60125#false} is VALID [2022-02-21 04:24:34,506 INFO L290 TraceCheckUtils]: 71: Hoare triple {60125#false} assume 1 == ~t6_pc~0; {60125#false} is VALID [2022-02-21 04:24:34,506 INFO L290 TraceCheckUtils]: 72: Hoare triple {60125#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {60125#false} is VALID [2022-02-21 04:24:34,507 INFO L290 TraceCheckUtils]: 73: Hoare triple {60125#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {60125#false} is VALID [2022-02-21 04:24:34,507 INFO L290 TraceCheckUtils]: 74: Hoare triple {60125#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {60125#false} is VALID [2022-02-21 04:24:34,507 INFO L290 TraceCheckUtils]: 75: Hoare triple {60125#false} assume !(0 != activate_threads_~tmp___5~0#1); {60125#false} is VALID [2022-02-21 04:24:34,507 INFO L290 TraceCheckUtils]: 76: Hoare triple {60125#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {60125#false} is VALID [2022-02-21 04:24:34,507 INFO L290 TraceCheckUtils]: 77: Hoare triple {60125#false} assume !(1 == ~t7_pc~0); {60125#false} is VALID [2022-02-21 04:24:34,507 INFO L290 TraceCheckUtils]: 78: Hoare triple {60125#false} is_transmit7_triggered_~__retres1~7#1 := 0; {60125#false} is VALID [2022-02-21 04:24:34,507 INFO L290 TraceCheckUtils]: 79: Hoare triple {60125#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {60125#false} is VALID [2022-02-21 04:24:34,507 INFO L290 TraceCheckUtils]: 80: Hoare triple {60125#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {60125#false} is VALID [2022-02-21 04:24:34,508 INFO L290 TraceCheckUtils]: 81: Hoare triple {60125#false} assume !(0 != activate_threads_~tmp___6~0#1); {60125#false} is VALID [2022-02-21 04:24:34,508 INFO L290 TraceCheckUtils]: 82: Hoare triple {60125#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {60125#false} is VALID [2022-02-21 04:24:34,508 INFO L290 TraceCheckUtils]: 83: Hoare triple {60125#false} assume 1 == ~t8_pc~0; {60125#false} is VALID [2022-02-21 04:24:34,508 INFO L290 TraceCheckUtils]: 84: Hoare triple {60125#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {60125#false} is VALID [2022-02-21 04:24:34,508 INFO L290 TraceCheckUtils]: 85: Hoare triple {60125#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {60125#false} is VALID [2022-02-21 04:24:34,508 INFO L290 TraceCheckUtils]: 86: Hoare triple {60125#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {60125#false} is VALID [2022-02-21 04:24:34,508 INFO L290 TraceCheckUtils]: 87: Hoare triple {60125#false} assume !(0 != activate_threads_~tmp___7~0#1); {60125#false} is VALID [2022-02-21 04:24:34,508 INFO L290 TraceCheckUtils]: 88: Hoare triple {60125#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {60125#false} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 89: Hoare triple {60125#false} assume !(1 == ~t9_pc~0); {60125#false} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 90: Hoare triple {60125#false} is_transmit9_triggered_~__retres1~9#1 := 0; {60125#false} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 91: Hoare triple {60125#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {60125#false} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 92: Hoare triple {60125#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {60125#false} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 93: Hoare triple {60125#false} assume !(0 != activate_threads_~tmp___8~0#1); {60125#false} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 94: Hoare triple {60125#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {60125#false} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 95: Hoare triple {60125#false} assume !(1 == ~M_E~0); {60125#false} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 96: Hoare triple {60125#false} assume !(1 == ~T1_E~0); {60125#false} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 97: Hoare triple {60125#false} assume !(1 == ~T2_E~0); {60125#false} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 98: Hoare triple {60125#false} assume !(1 == ~T3_E~0); {60125#false} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 99: Hoare triple {60125#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {60125#false} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 100: Hoare triple {60125#false} assume !(1 == ~T5_E~0); {60125#false} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 101: Hoare triple {60125#false} assume !(1 == ~T6_E~0); {60125#false} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 102: Hoare triple {60125#false} assume !(1 == ~T7_E~0); {60125#false} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 103: Hoare triple {60125#false} assume !(1 == ~T8_E~0); {60125#false} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 104: Hoare triple {60125#false} assume !(1 == ~T9_E~0); {60125#false} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 105: Hoare triple {60125#false} assume 1 == ~E_1~0;~E_1~0 := 2; {60125#false} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 106: Hoare triple {60125#false} assume !(1 == ~E_2~0); {60125#false} is VALID [2022-02-21 04:24:34,511 INFO L290 TraceCheckUtils]: 107: Hoare triple {60125#false} assume 1 == ~E_3~0;~E_3~0 := 2; {60125#false} is VALID [2022-02-21 04:24:34,511 INFO L290 TraceCheckUtils]: 108: Hoare triple {60125#false} assume !(1 == ~E_4~0); {60125#false} is VALID [2022-02-21 04:24:34,511 INFO L290 TraceCheckUtils]: 109: Hoare triple {60125#false} assume !(1 == ~E_5~0); {60125#false} is VALID [2022-02-21 04:24:34,511 INFO L290 TraceCheckUtils]: 110: Hoare triple {60125#false} assume !(1 == ~E_6~0); {60125#false} is VALID [2022-02-21 04:24:34,511 INFO L290 TraceCheckUtils]: 111: Hoare triple {60125#false} assume !(1 == ~E_7~0); {60125#false} is VALID [2022-02-21 04:24:34,511 INFO L290 TraceCheckUtils]: 112: Hoare triple {60125#false} assume !(1 == ~E_8~0); {60125#false} is VALID [2022-02-21 04:24:34,511 INFO L290 TraceCheckUtils]: 113: Hoare triple {60125#false} assume 1 == ~E_9~0;~E_9~0 := 2; {60125#false} is VALID [2022-02-21 04:24:34,511 INFO L290 TraceCheckUtils]: 114: Hoare triple {60125#false} assume { :end_inline_reset_delta_events } true; {60125#false} is VALID [2022-02-21 04:24:34,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:34,512 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:34,512 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [451403562] [2022-02-21 04:24:34,512 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [451403562] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:34,512 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:34,512 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:34,513 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1616803988] [2022-02-21 04:24:34,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:34,513 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:34,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:34,513 INFO L85 PathProgramCache]: Analyzing trace with hash -1620001714, now seen corresponding path program 1 times [2022-02-21 04:24:34,514 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:34,514 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902028584] [2022-02-21 04:24:34,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:34,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:34,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:34,543 INFO L290 TraceCheckUtils]: 0: Hoare triple {60128#true} assume !false; {60128#true} is VALID [2022-02-21 04:24:34,544 INFO L290 TraceCheckUtils]: 1: Hoare triple {60128#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {60128#true} is VALID [2022-02-21 04:24:34,544 INFO L290 TraceCheckUtils]: 2: Hoare triple {60128#true} assume !false; {60128#true} is VALID [2022-02-21 04:24:34,544 INFO L290 TraceCheckUtils]: 3: Hoare triple {60128#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {60128#true} is VALID [2022-02-21 04:24:34,544 INFO L290 TraceCheckUtils]: 4: Hoare triple {60128#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {60128#true} is VALID [2022-02-21 04:24:34,544 INFO L290 TraceCheckUtils]: 5: Hoare triple {60128#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {60128#true} is VALID [2022-02-21 04:24:34,544 INFO L290 TraceCheckUtils]: 6: Hoare triple {60128#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {60128#true} is VALID [2022-02-21 04:24:34,544 INFO L290 TraceCheckUtils]: 7: Hoare triple {60128#true} assume !(0 != eval_~tmp~0#1); {60128#true} is VALID [2022-02-21 04:24:34,544 INFO L290 TraceCheckUtils]: 8: Hoare triple {60128#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {60128#true} is VALID [2022-02-21 04:24:34,545 INFO L290 TraceCheckUtils]: 9: Hoare triple {60128#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {60128#true} is VALID [2022-02-21 04:24:34,545 INFO L290 TraceCheckUtils]: 10: Hoare triple {60128#true} assume 0 == ~M_E~0;~M_E~0 := 1; {60128#true} is VALID [2022-02-21 04:24:34,545 INFO L290 TraceCheckUtils]: 11: Hoare triple {60128#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {60128#true} is VALID [2022-02-21 04:24:34,545 INFO L290 TraceCheckUtils]: 12: Hoare triple {60128#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {60128#true} is VALID [2022-02-21 04:24:34,545 INFO L290 TraceCheckUtils]: 13: Hoare triple {60128#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,545 INFO L290 TraceCheckUtils]: 14: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T4_E~0); {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,546 INFO L290 TraceCheckUtils]: 15: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T5_E~0); {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,546 INFO L290 TraceCheckUtils]: 16: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,546 INFO L290 TraceCheckUtils]: 17: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,546 INFO L290 TraceCheckUtils]: 18: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,547 INFO L290 TraceCheckUtils]: 19: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,547 INFO L290 TraceCheckUtils]: 20: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,547 INFO L290 TraceCheckUtils]: 21: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,548 INFO L290 TraceCheckUtils]: 22: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_3~0); {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,548 INFO L290 TraceCheckUtils]: 23: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_4~0); {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,548 INFO L290 TraceCheckUtils]: 24: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,548 INFO L290 TraceCheckUtils]: 25: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,549 INFO L290 TraceCheckUtils]: 26: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,549 INFO L290 TraceCheckUtils]: 27: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,549 INFO L290 TraceCheckUtils]: 28: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,549 INFO L290 TraceCheckUtils]: 29: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,550 INFO L290 TraceCheckUtils]: 30: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~m_pc~0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,550 INFO L290 TraceCheckUtils]: 31: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,550 INFO L290 TraceCheckUtils]: 32: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,550 INFO L290 TraceCheckUtils]: 33: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,551 INFO L290 TraceCheckUtils]: 34: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,551 INFO L290 TraceCheckUtils]: 35: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,551 INFO L290 TraceCheckUtils]: 36: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t1_pc~0); {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,551 INFO L290 TraceCheckUtils]: 37: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,552 INFO L290 TraceCheckUtils]: 38: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,552 INFO L290 TraceCheckUtils]: 39: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,552 INFO L290 TraceCheckUtils]: 40: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,552 INFO L290 TraceCheckUtils]: 41: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,553 INFO L290 TraceCheckUtils]: 42: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t2_pc~0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,553 INFO L290 TraceCheckUtils]: 43: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,553 INFO L290 TraceCheckUtils]: 44: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,553 INFO L290 TraceCheckUtils]: 45: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,554 INFO L290 TraceCheckUtils]: 46: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,554 INFO L290 TraceCheckUtils]: 47: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,554 INFO L290 TraceCheckUtils]: 48: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t3_pc~0); {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,554 INFO L290 TraceCheckUtils]: 49: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,555 INFO L290 TraceCheckUtils]: 50: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,555 INFO L290 TraceCheckUtils]: 51: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,555 INFO L290 TraceCheckUtils]: 52: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,556 INFO L290 TraceCheckUtils]: 53: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,556 INFO L290 TraceCheckUtils]: 54: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t4_pc~0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,556 INFO L290 TraceCheckUtils]: 55: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,556 INFO L290 TraceCheckUtils]: 56: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,557 INFO L290 TraceCheckUtils]: 57: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,557 INFO L290 TraceCheckUtils]: 58: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,557 INFO L290 TraceCheckUtils]: 59: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,557 INFO L290 TraceCheckUtils]: 60: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t5_pc~0); {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,558 INFO L290 TraceCheckUtils]: 61: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,558 INFO L290 TraceCheckUtils]: 62: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,558 INFO L290 TraceCheckUtils]: 63: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,558 INFO L290 TraceCheckUtils]: 64: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,559 INFO L290 TraceCheckUtils]: 65: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,559 INFO L290 TraceCheckUtils]: 66: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t6_pc~0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,559 INFO L290 TraceCheckUtils]: 67: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,559 INFO L290 TraceCheckUtils]: 68: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,560 INFO L290 TraceCheckUtils]: 69: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,560 INFO L290 TraceCheckUtils]: 70: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,560 INFO L290 TraceCheckUtils]: 71: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,560 INFO L290 TraceCheckUtils]: 72: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t7_pc~0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,561 INFO L290 TraceCheckUtils]: 73: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,561 INFO L290 TraceCheckUtils]: 74: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,561 INFO L290 TraceCheckUtils]: 75: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,561 INFO L290 TraceCheckUtils]: 76: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,562 INFO L290 TraceCheckUtils]: 77: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,562 INFO L290 TraceCheckUtils]: 78: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t8_pc~0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,562 INFO L290 TraceCheckUtils]: 79: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,562 INFO L290 TraceCheckUtils]: 80: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,563 INFO L290 TraceCheckUtils]: 81: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,563 INFO L290 TraceCheckUtils]: 82: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,563 INFO L290 TraceCheckUtils]: 83: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,563 INFO L290 TraceCheckUtils]: 84: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t9_pc~0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,564 INFO L290 TraceCheckUtils]: 85: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,564 INFO L290 TraceCheckUtils]: 86: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,564 INFO L290 TraceCheckUtils]: 87: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,565 INFO L290 TraceCheckUtils]: 88: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,565 INFO L290 TraceCheckUtils]: 89: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,565 INFO L290 TraceCheckUtils]: 90: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,565 INFO L290 TraceCheckUtils]: 91: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,566 INFO L290 TraceCheckUtils]: 92: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {60130#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:34,566 INFO L290 TraceCheckUtils]: 93: Hoare triple {60130#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~T3_E~0); {60129#false} is VALID [2022-02-21 04:24:34,566 INFO L290 TraceCheckUtils]: 94: Hoare triple {60129#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,566 INFO L290 TraceCheckUtils]: 95: Hoare triple {60129#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,566 INFO L290 TraceCheckUtils]: 96: Hoare triple {60129#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,566 INFO L290 TraceCheckUtils]: 97: Hoare triple {60129#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,566 INFO L290 TraceCheckUtils]: 98: Hoare triple {60129#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,567 INFO L290 TraceCheckUtils]: 99: Hoare triple {60129#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,567 INFO L290 TraceCheckUtils]: 100: Hoare triple {60129#false} assume 1 == ~E_1~0;~E_1~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,567 INFO L290 TraceCheckUtils]: 101: Hoare triple {60129#false} assume !(1 == ~E_2~0); {60129#false} is VALID [2022-02-21 04:24:34,567 INFO L290 TraceCheckUtils]: 102: Hoare triple {60129#false} assume 1 == ~E_3~0;~E_3~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,567 INFO L290 TraceCheckUtils]: 103: Hoare triple {60129#false} assume 1 == ~E_4~0;~E_4~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,567 INFO L290 TraceCheckUtils]: 104: Hoare triple {60129#false} assume 1 == ~E_5~0;~E_5~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,567 INFO L290 TraceCheckUtils]: 105: Hoare triple {60129#false} assume 1 == ~E_6~0;~E_6~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,567 INFO L290 TraceCheckUtils]: 106: Hoare triple {60129#false} assume 1 == ~E_7~0;~E_7~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,567 INFO L290 TraceCheckUtils]: 107: Hoare triple {60129#false} assume 1 == ~E_8~0;~E_8~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,568 INFO L290 TraceCheckUtils]: 108: Hoare triple {60129#false} assume 1 == ~E_9~0;~E_9~0 := 2; {60129#false} is VALID [2022-02-21 04:24:34,568 INFO L290 TraceCheckUtils]: 109: Hoare triple {60129#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {60129#false} is VALID [2022-02-21 04:24:34,568 INFO L290 TraceCheckUtils]: 110: Hoare triple {60129#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {60129#false} is VALID [2022-02-21 04:24:34,568 INFO L290 TraceCheckUtils]: 111: Hoare triple {60129#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {60129#false} is VALID [2022-02-21 04:24:34,568 INFO L290 TraceCheckUtils]: 112: Hoare triple {60129#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {60129#false} is VALID [2022-02-21 04:24:34,568 INFO L290 TraceCheckUtils]: 113: Hoare triple {60129#false} assume !(0 == start_simulation_~tmp~3#1); {60129#false} is VALID [2022-02-21 04:24:34,568 INFO L290 TraceCheckUtils]: 114: Hoare triple {60129#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {60129#false} is VALID [2022-02-21 04:24:34,568 INFO L290 TraceCheckUtils]: 115: Hoare triple {60129#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {60129#false} is VALID [2022-02-21 04:24:34,568 INFO L290 TraceCheckUtils]: 116: Hoare triple {60129#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {60129#false} is VALID [2022-02-21 04:24:34,569 INFO L290 TraceCheckUtils]: 117: Hoare triple {60129#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {60129#false} is VALID [2022-02-21 04:24:34,569 INFO L290 TraceCheckUtils]: 118: Hoare triple {60129#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {60129#false} is VALID [2022-02-21 04:24:34,569 INFO L290 TraceCheckUtils]: 119: Hoare triple {60129#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {60129#false} is VALID [2022-02-21 04:24:34,569 INFO L290 TraceCheckUtils]: 120: Hoare triple {60129#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {60129#false} is VALID [2022-02-21 04:24:34,569 INFO L290 TraceCheckUtils]: 121: Hoare triple {60129#false} assume !(0 != start_simulation_~tmp___0~1#1); {60129#false} is VALID [2022-02-21 04:24:34,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:34,570 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:34,570 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902028584] [2022-02-21 04:24:34,570 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902028584] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:34,570 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:34,570 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:34,570 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355896555] [2022-02-21 04:24:34,570 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:34,571 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:34,571 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:34,571 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:34,571 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:34,571 INFO L87 Difference]: Start difference. First operand 3896 states and 5764 transitions. cyclomatic complexity: 1872 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:39,501 INFO L93 Difference]: Finished difference Result 10904 states and 15918 transitions. [2022-02-21 04:24:39,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:39,501 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,565 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:39,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10904 states and 15918 transitions. [2022-02-21 04:24:42,269 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10426 [2022-02-21 04:24:44,936 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10904 states to 10904 states and 15918 transitions. [2022-02-21 04:24:44,936 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10904 [2022-02-21 04:24:44,940 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10904 [2022-02-21 04:24:44,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10904 states and 15918 transitions. [2022-02-21 04:24:44,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:44,947 INFO L681 BuchiCegarLoop]: Abstraction has 10904 states and 15918 transitions. [2022-02-21 04:24:44,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10904 states and 15918 transitions. [2022-02-21 04:24:45,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10904 to 10352. [2022-02-21 04:24:45,069 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:45,081 INFO L82 GeneralOperation]: Start isEquivalent. First operand 10904 states and 15918 transitions. Second operand has 10352 states, 10352 states have (on average 1.464258114374034) internal successors, (15158), 10351 states have internal predecessors, (15158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,092 INFO L74 IsIncluded]: Start isIncluded. First operand 10904 states and 15918 transitions. Second operand has 10352 states, 10352 states have (on average 1.464258114374034) internal successors, (15158), 10351 states have internal predecessors, (15158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,103 INFO L87 Difference]: Start difference. First operand 10904 states and 15918 transitions. Second operand has 10352 states, 10352 states have (on average 1.464258114374034) internal successors, (15158), 10351 states have internal predecessors, (15158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:47,798 INFO L93 Difference]: Finished difference Result 10904 states and 15918 transitions. [2022-02-21 04:24:47,798 INFO L276 IsEmpty]: Start isEmpty. Operand 10904 states and 15918 transitions. [2022-02-21 04:24:47,808 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:47,808 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:47,819 INFO L74 IsIncluded]: Start isIncluded. First operand has 10352 states, 10352 states have (on average 1.464258114374034) internal successors, (15158), 10351 states have internal predecessors, (15158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 10904 states and 15918 transitions. [2022-02-21 04:24:47,828 INFO L87 Difference]: Start difference. First operand has 10352 states, 10352 states have (on average 1.464258114374034) internal successors, (15158), 10351 states have internal predecessors, (15158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 10904 states and 15918 transitions. [2022-02-21 04:24:50,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:50,640 INFO L93 Difference]: Finished difference Result 10904 states and 15918 transitions. [2022-02-21 04:24:50,640 INFO L276 IsEmpty]: Start isEmpty. Operand 10904 states and 15918 transitions. [2022-02-21 04:24:50,650 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:50,650 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:50,650 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:50,650 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:50,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10352 states, 10352 states have (on average 1.464258114374034) internal successors, (15158), 10351 states have internal predecessors, (15158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:53,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10352 states to 10352 states and 15158 transitions. [2022-02-21 04:24:53,574 INFO L704 BuchiCegarLoop]: Abstraction has 10352 states and 15158 transitions. [2022-02-21 04:24:53,574 INFO L587 BuchiCegarLoop]: Abstraction has 10352 states and 15158 transitions. [2022-02-21 04:24:53,574 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:24:53,574 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10352 states and 15158 transitions. [2022-02-21 04:24:53,612 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10170 [2022-02-21 04:24:53,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:53,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:53,614 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:53,614 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:53,614 INFO L791 eck$LassoCheckResult]: Stem: 71929#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 71930#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 71486#L1359 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 71487#L634 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 72135#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 72136#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 72107#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 71873#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 71874#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71667#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 71668#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 72232#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 72082#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 71731#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 71493#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 71494#L922 assume !(0 == ~M_E~0); 72323#L922-2 assume !(0 == ~T1_E~0); 72324#L927-1 assume !(0 == ~T2_E~0); 71939#L932-1 assume !(0 == ~T3_E~0); 71811#L937-1 assume !(0 == ~T4_E~0); 71812#L942-1 assume !(0 == ~T5_E~0); 71872#L947-1 assume !(0 == ~T6_E~0); 71943#L952-1 assume !(0 == ~T7_E~0); 71944#L957-1 assume !(0 == ~T8_E~0); 72025#L962-1 assume !(0 == ~T9_E~0); 71788#L967-1 assume !(0 == ~E_1~0); 71789#L972-1 assume !(0 == ~E_2~0); 72114#L977-1 assume !(0 == ~E_3~0); 72115#L982-1 assume !(0 == ~E_4~0); 71255#L987-1 assume !(0 == ~E_5~0); 71256#L992-1 assume !(0 == ~E_6~0); 71262#L997-1 assume !(0 == ~E_7~0); 71708#L1002-1 assume !(0 == ~E_8~0); 71692#L1007-1 assume !(0 == ~E_9~0); 71049#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71050#L443 assume !(1 == ~m_pc~0); 71961#L443-2 is_master_triggered_~__retres1~0#1 := 0; 71949#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71950#L455 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 71425#L1140 assume !(0 != activate_threads_~tmp~1#1); 71164#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71165#L462 assume !(1 == ~t1_pc~0); 71803#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 71804#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71135#L474 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 71136#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 71647#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71648#L481 assume !(1 == ~t2_pc~0); 71419#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 71418#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71808#L493 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 71518#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 71519#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71621#L500 assume 1 == ~t3_pc~0; 71851#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 71852#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72097#L512 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 72098#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 71051#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71052#L519 assume 1 == ~t4_pc~0; 71358#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 71359#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71618#L531 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 71468#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 71469#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71220#L538 assume !(1 == ~t5_pc~0); 71221#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 71125#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71126#L550 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71402#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 71403#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72008#L557 assume 1 == ~t6_pc~0; 71772#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 71443#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 71339#L569 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 71340#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 71470#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72279#L576 assume !(1 == ~t7_pc~0); 71429#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 71430#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71695#L588 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71696#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 72068#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 71557#L595 assume 1 == ~t8_pc~0; 71558#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 72099#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 72100#L607 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 71903#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 71904#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 71348#L614 assume !(1 == ~t9_pc~0); 71349#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 71245#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 71246#L626 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 71433#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 71520#L1212-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71521#L1025 assume !(1 == ~M_E~0); 71795#L1025-2 assume !(1 == ~T1_E~0); 71850#L1030-1 assume !(1 == ~T2_E~0); 71998#L1035-1 assume !(1 == ~T3_E~0); 78054#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 72143#L1045-1 assume !(1 == ~T5_E~0); 71414#L1050-1 assume !(1 == ~T6_E~0); 71415#L1055-1 assume !(1 == ~T7_E~0); 71229#L1060-1 assume !(1 == ~T8_E~0); 71230#L1065-1 assume !(1 == ~T9_E~0); 71293#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 71945#L1075-1 assume !(1 == ~E_2~0); 71946#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 72339#L1085-1 assume !(1 == ~E_4~0); 80411#L1090-1 assume !(1 == ~E_5~0); 80409#L1095-1 assume !(1 == ~E_6~0); 80408#L1100-1 assume !(1 == ~E_7~0); 80407#L1105-1 assume !(1 == ~E_8~0); 80387#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 80381#L1115-1 assume { :end_inline_reset_delta_events } true; 80375#L1396-2 [2022-02-21 04:24:53,615 INFO L793 eck$LassoCheckResult]: Loop: 80375#L1396-2 assume !false; 72288#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 71483#L897 assume !false; 72295#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 72328#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 71074#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 71075#L752 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 72209#L766 assume !(0 != eval_~tmp~0#1); 72211#L912 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 80355#L634-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 80354#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 80353#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 80352#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 71584#L932-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 71585#L937-3 assume !(0 == ~T4_E~0); 71931#L942-3 assume !(0 == ~T5_E~0); 80799#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 80798#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 72205#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 72206#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 72037#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 72038#L972-3 assume 0 == ~E_2~0;~E_2~0 := 1; 71937#L977-3 assume !(0 == ~E_3~0); 71938#L982-3 assume !(0 == ~E_4~0); 72331#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71533#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 71534#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 71531#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 71532#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 71231#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71232#L443-30 assume !(1 == ~m_pc~0); 71579#L443-32 is_master_triggered_~__retres1~0#1 := 0; 71564#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71565#L455-10 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 72250#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72120#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71675#L462-30 assume !(1 == ~t1_pc~0); 71676#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 72111#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72095#L474-10 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 72096#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 72154#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71659#L481-30 assume 1 == ~t2_pc~0; 71355#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 71356#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71416#L493-10 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 71327#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 71328#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71624#L500-30 assume 1 == ~t3_pc~0; 71364#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 71365#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71431#L512-10 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 71432#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 71606#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71607#L519-30 assume 1 == ~t4_pc~0; 71992#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 71777#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71098#L531-10 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 71099#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 71791#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71916#L538-30 assume 1 == ~t5_pc~0; 72275#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 80731#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80729#L550-10 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72070#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 72071#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 71331#L557-30 assume 1 == ~t6_pc~0; 71037#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 71038#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80717#L569-10 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 80714#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 71346#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 71347#L576-30 assume 1 == ~t7_pc~0; 71908#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 71119#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72335#L588-10 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 72336#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 80697#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 80693#L595-30 assume 1 == ~t8_pc~0; 80691#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 80690#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 80688#L607-10 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 72216#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 72217#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 80681#L614-30 assume !(1 == ~t9_pc~0); 80679#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 80675#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 80673#L626-10 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 80670#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 80668#L1212-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 80657#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 71649#L1025-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 71650#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 71855#L1035-3 assume !(1 == ~T3_E~0); 80648#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76079#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 72226#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 72227#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 80643#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 72133#L1065-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 72134#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 71917#L1075-3 assume !(1 == ~E_2~0); 71918#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 72238#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 80635#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 80632#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 80630#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 80628#L1105-3 assume 1 == ~E_8~0;~E_8~0 := 2; 80627#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 80626#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 80615#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 80614#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 80613#L752-1 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 80611#L1415 assume !(0 == start_simulation_~tmp~3#1); 80609#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 72296#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 71188#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 71792#L752-2 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 72001#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 72332#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 71844#L1378 start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 71845#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 80375#L1396-2 [2022-02-21 04:24:53,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:53,615 INFO L85 PathProgramCache]: Analyzing trace with hash 212114046, now seen corresponding path program 1 times [2022-02-21 04:24:53,616 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:53,616 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930852635] [2022-02-21 04:24:53,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:53,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:53,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:53,642 INFO L290 TraceCheckUtils]: 0: Hoare triple {103200#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,643 INFO L290 TraceCheckUtils]: 1: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,643 INFO L290 TraceCheckUtils]: 2: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,643 INFO L290 TraceCheckUtils]: 3: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,644 INFO L290 TraceCheckUtils]: 4: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,644 INFO L290 TraceCheckUtils]: 5: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,644 INFO L290 TraceCheckUtils]: 6: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,645 INFO L290 TraceCheckUtils]: 7: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,645 INFO L290 TraceCheckUtils]: 8: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,645 INFO L290 TraceCheckUtils]: 9: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,646 INFO L290 TraceCheckUtils]: 10: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,646 INFO L290 TraceCheckUtils]: 11: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,646 INFO L290 TraceCheckUtils]: 12: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,647 INFO L290 TraceCheckUtils]: 13: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,647 INFO L290 TraceCheckUtils]: 14: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,647 INFO L290 TraceCheckUtils]: 15: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~M_E~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,648 INFO L290 TraceCheckUtils]: 16: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T1_E~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,648 INFO L290 TraceCheckUtils]: 17: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T2_E~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,648 INFO L290 TraceCheckUtils]: 18: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T3_E~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,649 INFO L290 TraceCheckUtils]: 19: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T4_E~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,649 INFO L290 TraceCheckUtils]: 20: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T5_E~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,649 INFO L290 TraceCheckUtils]: 21: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T6_E~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,650 INFO L290 TraceCheckUtils]: 22: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T7_E~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,650 INFO L290 TraceCheckUtils]: 23: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T8_E~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,650 INFO L290 TraceCheckUtils]: 24: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T9_E~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,651 INFO L290 TraceCheckUtils]: 25: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_1~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,651 INFO L290 TraceCheckUtils]: 26: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_2~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,651 INFO L290 TraceCheckUtils]: 27: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_3~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,652 INFO L290 TraceCheckUtils]: 28: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_4~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,652 INFO L290 TraceCheckUtils]: 29: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_5~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,652 INFO L290 TraceCheckUtils]: 30: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_6~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,653 INFO L290 TraceCheckUtils]: 31: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_7~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,653 INFO L290 TraceCheckUtils]: 32: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_8~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,653 INFO L290 TraceCheckUtils]: 33: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_9~0); {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,653 INFO L290 TraceCheckUtils]: 34: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {103202#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:24:53,654 INFO L290 TraceCheckUtils]: 35: Hoare triple {103202#(= ~m_pc~0 ~t3_pc~0)} assume !(1 == ~m_pc~0); {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,654 INFO L290 TraceCheckUtils]: 36: Hoare triple {103203#(not (= ~t3_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,654 INFO L290 TraceCheckUtils]: 37: Hoare triple {103203#(not (= ~t3_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,655 INFO L290 TraceCheckUtils]: 38: Hoare triple {103203#(not (= ~t3_pc~0 1))} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,655 INFO L290 TraceCheckUtils]: 39: Hoare triple {103203#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,655 INFO L290 TraceCheckUtils]: 40: Hoare triple {103203#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,655 INFO L290 TraceCheckUtils]: 41: Hoare triple {103203#(not (= ~t3_pc~0 1))} assume !(1 == ~t1_pc~0); {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,656 INFO L290 TraceCheckUtils]: 42: Hoare triple {103203#(not (= ~t3_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,656 INFO L290 TraceCheckUtils]: 43: Hoare triple {103203#(not (= ~t3_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,656 INFO L290 TraceCheckUtils]: 44: Hoare triple {103203#(not (= ~t3_pc~0 1))} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,657 INFO L290 TraceCheckUtils]: 45: Hoare triple {103203#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,657 INFO L290 TraceCheckUtils]: 46: Hoare triple {103203#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,657 INFO L290 TraceCheckUtils]: 47: Hoare triple {103203#(not (= ~t3_pc~0 1))} assume !(1 == ~t2_pc~0); {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,657 INFO L290 TraceCheckUtils]: 48: Hoare triple {103203#(not (= ~t3_pc~0 1))} is_transmit2_triggered_~__retres1~2#1 := 0; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,658 INFO L290 TraceCheckUtils]: 49: Hoare triple {103203#(not (= ~t3_pc~0 1))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,658 INFO L290 TraceCheckUtils]: 50: Hoare triple {103203#(not (= ~t3_pc~0 1))} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,658 INFO L290 TraceCheckUtils]: 51: Hoare triple {103203#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___1~0#1); {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,658 INFO L290 TraceCheckUtils]: 52: Hoare triple {103203#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {103203#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:24:53,659 INFO L290 TraceCheckUtils]: 53: Hoare triple {103203#(not (= ~t3_pc~0 1))} assume 1 == ~t3_pc~0; {103201#false} is VALID [2022-02-21 04:24:53,659 INFO L290 TraceCheckUtils]: 54: Hoare triple {103201#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {103201#false} is VALID [2022-02-21 04:24:53,659 INFO L290 TraceCheckUtils]: 55: Hoare triple {103201#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {103201#false} is VALID [2022-02-21 04:24:53,659 INFO L290 TraceCheckUtils]: 56: Hoare triple {103201#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {103201#false} is VALID [2022-02-21 04:24:53,659 INFO L290 TraceCheckUtils]: 57: Hoare triple {103201#false} assume !(0 != activate_threads_~tmp___2~0#1); {103201#false} is VALID [2022-02-21 04:24:53,659 INFO L290 TraceCheckUtils]: 58: Hoare triple {103201#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {103201#false} is VALID [2022-02-21 04:24:53,660 INFO L290 TraceCheckUtils]: 59: Hoare triple {103201#false} assume 1 == ~t4_pc~0; {103201#false} is VALID [2022-02-21 04:24:53,660 INFO L290 TraceCheckUtils]: 60: Hoare triple {103201#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {103201#false} is VALID [2022-02-21 04:24:53,660 INFO L290 TraceCheckUtils]: 61: Hoare triple {103201#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {103201#false} is VALID [2022-02-21 04:24:53,660 INFO L290 TraceCheckUtils]: 62: Hoare triple {103201#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {103201#false} is VALID [2022-02-21 04:24:53,660 INFO L290 TraceCheckUtils]: 63: Hoare triple {103201#false} assume !(0 != activate_threads_~tmp___3~0#1); {103201#false} is VALID [2022-02-21 04:24:53,660 INFO L290 TraceCheckUtils]: 64: Hoare triple {103201#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {103201#false} is VALID [2022-02-21 04:24:53,660 INFO L290 TraceCheckUtils]: 65: Hoare triple {103201#false} assume !(1 == ~t5_pc~0); {103201#false} is VALID [2022-02-21 04:24:53,660 INFO L290 TraceCheckUtils]: 66: Hoare triple {103201#false} is_transmit5_triggered_~__retres1~5#1 := 0; {103201#false} is VALID [2022-02-21 04:24:53,661 INFO L290 TraceCheckUtils]: 67: Hoare triple {103201#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {103201#false} is VALID [2022-02-21 04:24:53,661 INFO L290 TraceCheckUtils]: 68: Hoare triple {103201#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {103201#false} is VALID [2022-02-21 04:24:53,661 INFO L290 TraceCheckUtils]: 69: Hoare triple {103201#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {103201#false} is VALID [2022-02-21 04:24:53,661 INFO L290 TraceCheckUtils]: 70: Hoare triple {103201#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {103201#false} is VALID [2022-02-21 04:24:53,661 INFO L290 TraceCheckUtils]: 71: Hoare triple {103201#false} assume 1 == ~t6_pc~0; {103201#false} is VALID [2022-02-21 04:24:53,661 INFO L290 TraceCheckUtils]: 72: Hoare triple {103201#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {103201#false} is VALID [2022-02-21 04:24:53,661 INFO L290 TraceCheckUtils]: 73: Hoare triple {103201#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {103201#false} is VALID [2022-02-21 04:24:53,661 INFO L290 TraceCheckUtils]: 74: Hoare triple {103201#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {103201#false} is VALID [2022-02-21 04:24:53,662 INFO L290 TraceCheckUtils]: 75: Hoare triple {103201#false} assume !(0 != activate_threads_~tmp___5~0#1); {103201#false} is VALID [2022-02-21 04:24:53,662 INFO L290 TraceCheckUtils]: 76: Hoare triple {103201#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {103201#false} is VALID [2022-02-21 04:24:53,662 INFO L290 TraceCheckUtils]: 77: Hoare triple {103201#false} assume !(1 == ~t7_pc~0); {103201#false} is VALID [2022-02-21 04:24:53,662 INFO L290 TraceCheckUtils]: 78: Hoare triple {103201#false} is_transmit7_triggered_~__retres1~7#1 := 0; {103201#false} is VALID [2022-02-21 04:24:53,662 INFO L290 TraceCheckUtils]: 79: Hoare triple {103201#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {103201#false} is VALID [2022-02-21 04:24:53,662 INFO L290 TraceCheckUtils]: 80: Hoare triple {103201#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {103201#false} is VALID [2022-02-21 04:24:53,662 INFO L290 TraceCheckUtils]: 81: Hoare triple {103201#false} assume !(0 != activate_threads_~tmp___6~0#1); {103201#false} is VALID [2022-02-21 04:24:53,662 INFO L290 TraceCheckUtils]: 82: Hoare triple {103201#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {103201#false} is VALID [2022-02-21 04:24:53,663 INFO L290 TraceCheckUtils]: 83: Hoare triple {103201#false} assume 1 == ~t8_pc~0; {103201#false} is VALID [2022-02-21 04:24:53,663 INFO L290 TraceCheckUtils]: 84: Hoare triple {103201#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {103201#false} is VALID [2022-02-21 04:24:53,663 INFO L290 TraceCheckUtils]: 85: Hoare triple {103201#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {103201#false} is VALID [2022-02-21 04:24:53,663 INFO L290 TraceCheckUtils]: 86: Hoare triple {103201#false} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {103201#false} is VALID [2022-02-21 04:24:53,663 INFO L290 TraceCheckUtils]: 87: Hoare triple {103201#false} assume !(0 != activate_threads_~tmp___7~0#1); {103201#false} is VALID [2022-02-21 04:24:53,663 INFO L290 TraceCheckUtils]: 88: Hoare triple {103201#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {103201#false} is VALID [2022-02-21 04:24:53,663 INFO L290 TraceCheckUtils]: 89: Hoare triple {103201#false} assume !(1 == ~t9_pc~0); {103201#false} is VALID [2022-02-21 04:24:53,663 INFO L290 TraceCheckUtils]: 90: Hoare triple {103201#false} is_transmit9_triggered_~__retres1~9#1 := 0; {103201#false} is VALID [2022-02-21 04:24:53,664 INFO L290 TraceCheckUtils]: 91: Hoare triple {103201#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {103201#false} is VALID [2022-02-21 04:24:53,664 INFO L290 TraceCheckUtils]: 92: Hoare triple {103201#false} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {103201#false} is VALID [2022-02-21 04:24:53,664 INFO L290 TraceCheckUtils]: 93: Hoare triple {103201#false} assume !(0 != activate_threads_~tmp___8~0#1); {103201#false} is VALID [2022-02-21 04:24:53,664 INFO L290 TraceCheckUtils]: 94: Hoare triple {103201#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {103201#false} is VALID [2022-02-21 04:24:53,664 INFO L290 TraceCheckUtils]: 95: Hoare triple {103201#false} assume !(1 == ~M_E~0); {103201#false} is VALID [2022-02-21 04:24:53,664 INFO L290 TraceCheckUtils]: 96: Hoare triple {103201#false} assume !(1 == ~T1_E~0); {103201#false} is VALID [2022-02-21 04:24:53,664 INFO L290 TraceCheckUtils]: 97: Hoare triple {103201#false} assume !(1 == ~T2_E~0); {103201#false} is VALID [2022-02-21 04:24:53,664 INFO L290 TraceCheckUtils]: 98: Hoare triple {103201#false} assume !(1 == ~T3_E~0); {103201#false} is VALID [2022-02-21 04:24:53,665 INFO L290 TraceCheckUtils]: 99: Hoare triple {103201#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {103201#false} is VALID [2022-02-21 04:24:53,665 INFO L290 TraceCheckUtils]: 100: Hoare triple {103201#false} assume !(1 == ~T5_E~0); {103201#false} is VALID [2022-02-21 04:24:53,665 INFO L290 TraceCheckUtils]: 101: Hoare triple {103201#false} assume !(1 == ~T6_E~0); {103201#false} is VALID [2022-02-21 04:24:53,665 INFO L290 TraceCheckUtils]: 102: Hoare triple {103201#false} assume !(1 == ~T7_E~0); {103201#false} is VALID [2022-02-21 04:24:53,665 INFO L290 TraceCheckUtils]: 103: Hoare triple {103201#false} assume !(1 == ~T8_E~0); {103201#false} is VALID [2022-02-21 04:24:53,665 INFO L290 TraceCheckUtils]: 104: Hoare triple {103201#false} assume !(1 == ~T9_E~0); {103201#false} is VALID [2022-02-21 04:24:53,665 INFO L290 TraceCheckUtils]: 105: Hoare triple {103201#false} assume 1 == ~E_1~0;~E_1~0 := 2; {103201#false} is VALID [2022-02-21 04:24:53,665 INFO L290 TraceCheckUtils]: 106: Hoare triple {103201#false} assume !(1 == ~E_2~0); {103201#false} is VALID [2022-02-21 04:24:53,666 INFO L290 TraceCheckUtils]: 107: Hoare triple {103201#false} assume 1 == ~E_3~0;~E_3~0 := 2; {103201#false} is VALID [2022-02-21 04:24:53,666 INFO L290 TraceCheckUtils]: 108: Hoare triple {103201#false} assume !(1 == ~E_4~0); {103201#false} is VALID [2022-02-21 04:24:53,666 INFO L290 TraceCheckUtils]: 109: Hoare triple {103201#false} assume !(1 == ~E_5~0); {103201#false} is VALID [2022-02-21 04:24:53,666 INFO L290 TraceCheckUtils]: 110: Hoare triple {103201#false} assume !(1 == ~E_6~0); {103201#false} is VALID [2022-02-21 04:24:53,666 INFO L290 TraceCheckUtils]: 111: Hoare triple {103201#false} assume !(1 == ~E_7~0); {103201#false} is VALID [2022-02-21 04:24:53,666 INFO L290 TraceCheckUtils]: 112: Hoare triple {103201#false} assume !(1 == ~E_8~0); {103201#false} is VALID [2022-02-21 04:24:53,666 INFO L290 TraceCheckUtils]: 113: Hoare triple {103201#false} assume 1 == ~E_9~0;~E_9~0 := 2; {103201#false} is VALID [2022-02-21 04:24:53,666 INFO L290 TraceCheckUtils]: 114: Hoare triple {103201#false} assume { :end_inline_reset_delta_events } true; {103201#false} is VALID [2022-02-21 04:24:53,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:53,667 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:53,667 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930852635] [2022-02-21 04:24:53,667 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930852635] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:53,667 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:53,668 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:53,668 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1797526018] [2022-02-21 04:24:53,668 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:53,668 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:53,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:53,669 INFO L85 PathProgramCache]: Analyzing trace with hash -1915089010, now seen corresponding path program 1 times [2022-02-21 04:24:53,669 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:53,669 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372942124] [2022-02-21 04:24:53,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:53,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:53,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:53,691 INFO L290 TraceCheckUtils]: 0: Hoare triple {103204#true} assume !false; {103204#true} is VALID [2022-02-21 04:24:53,691 INFO L290 TraceCheckUtils]: 1: Hoare triple {103204#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {103204#true} is VALID [2022-02-21 04:24:53,691 INFO L290 TraceCheckUtils]: 2: Hoare triple {103204#true} assume !false; {103204#true} is VALID [2022-02-21 04:24:53,691 INFO L290 TraceCheckUtils]: 3: Hoare triple {103204#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {103204#true} is VALID [2022-02-21 04:24:53,692 INFO L290 TraceCheckUtils]: 4: Hoare triple {103204#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {103204#true} is VALID [2022-02-21 04:24:53,692 INFO L290 TraceCheckUtils]: 5: Hoare triple {103204#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {103204#true} is VALID [2022-02-21 04:24:53,692 INFO L290 TraceCheckUtils]: 6: Hoare triple {103204#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {103204#true} is VALID [2022-02-21 04:24:53,692 INFO L290 TraceCheckUtils]: 7: Hoare triple {103204#true} assume !(0 != eval_~tmp~0#1); {103204#true} is VALID [2022-02-21 04:24:53,692 INFO L290 TraceCheckUtils]: 8: Hoare triple {103204#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {103204#true} is VALID [2022-02-21 04:24:53,692 INFO L290 TraceCheckUtils]: 9: Hoare triple {103204#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {103204#true} is VALID [2022-02-21 04:24:53,692 INFO L290 TraceCheckUtils]: 10: Hoare triple {103204#true} assume 0 == ~M_E~0;~M_E~0 := 1; {103204#true} is VALID [2022-02-21 04:24:53,692 INFO L290 TraceCheckUtils]: 11: Hoare triple {103204#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {103204#true} is VALID [2022-02-21 04:24:53,693 INFO L290 TraceCheckUtils]: 12: Hoare triple {103204#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {103204#true} is VALID [2022-02-21 04:24:53,693 INFO L290 TraceCheckUtils]: 13: Hoare triple {103204#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,693 INFO L290 TraceCheckUtils]: 14: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T4_E~0); {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,693 INFO L290 TraceCheckUtils]: 15: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~T5_E~0); {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,694 INFO L290 TraceCheckUtils]: 16: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,694 INFO L290 TraceCheckUtils]: 17: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,694 INFO L290 TraceCheckUtils]: 18: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,695 INFO L290 TraceCheckUtils]: 19: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,695 INFO L290 TraceCheckUtils]: 20: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,695 INFO L290 TraceCheckUtils]: 21: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,695 INFO L290 TraceCheckUtils]: 22: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_3~0); {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,696 INFO L290 TraceCheckUtils]: 23: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 == ~E_4~0); {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,696 INFO L290 TraceCheckUtils]: 24: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,696 INFO L290 TraceCheckUtils]: 25: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,696 INFO L290 TraceCheckUtils]: 26: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,697 INFO L290 TraceCheckUtils]: 27: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,697 INFO L290 TraceCheckUtils]: 28: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,697 INFO L290 TraceCheckUtils]: 29: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,698 INFO L290 TraceCheckUtils]: 30: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~m_pc~0); {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,698 INFO L290 TraceCheckUtils]: 31: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,698 INFO L290 TraceCheckUtils]: 32: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,698 INFO L290 TraceCheckUtils]: 33: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,699 INFO L290 TraceCheckUtils]: 34: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,699 INFO L290 TraceCheckUtils]: 35: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,699 INFO L290 TraceCheckUtils]: 36: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t1_pc~0); {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,699 INFO L290 TraceCheckUtils]: 37: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,700 INFO L290 TraceCheckUtils]: 38: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,700 INFO L290 TraceCheckUtils]: 39: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,700 INFO L290 TraceCheckUtils]: 40: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,701 INFO L290 TraceCheckUtils]: 41: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,701 INFO L290 TraceCheckUtils]: 42: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t2_pc~0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,701 INFO L290 TraceCheckUtils]: 43: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,701 INFO L290 TraceCheckUtils]: 44: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,702 INFO L290 TraceCheckUtils]: 45: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,702 INFO L290 TraceCheckUtils]: 46: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,702 INFO L290 TraceCheckUtils]: 47: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,703 INFO L290 TraceCheckUtils]: 48: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t3_pc~0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,703 INFO L290 TraceCheckUtils]: 49: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,703 INFO L290 TraceCheckUtils]: 50: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,703 INFO L290 TraceCheckUtils]: 51: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,704 INFO L290 TraceCheckUtils]: 52: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,704 INFO L290 TraceCheckUtils]: 53: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,704 INFO L290 TraceCheckUtils]: 54: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t4_pc~0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,705 INFO L290 TraceCheckUtils]: 55: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,705 INFO L290 TraceCheckUtils]: 56: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,705 INFO L290 TraceCheckUtils]: 57: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,705 INFO L290 TraceCheckUtils]: 58: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,706 INFO L290 TraceCheckUtils]: 59: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,706 INFO L290 TraceCheckUtils]: 60: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t5_pc~0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,706 INFO L290 TraceCheckUtils]: 61: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,707 INFO L290 TraceCheckUtils]: 62: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,707 INFO L290 TraceCheckUtils]: 63: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,707 INFO L290 TraceCheckUtils]: 64: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,707 INFO L290 TraceCheckUtils]: 65: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,708 INFO L290 TraceCheckUtils]: 66: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t6_pc~0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,708 INFO L290 TraceCheckUtils]: 67: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,708 INFO L290 TraceCheckUtils]: 68: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,708 INFO L290 TraceCheckUtils]: 69: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,709 INFO L290 TraceCheckUtils]: 70: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume !(0 != activate_threads_~tmp___5~0#1); {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,709 INFO L290 TraceCheckUtils]: 71: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,709 INFO L290 TraceCheckUtils]: 72: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t7_pc~0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,710 INFO L290 TraceCheckUtils]: 73: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,710 INFO L290 TraceCheckUtils]: 74: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,710 INFO L290 TraceCheckUtils]: 75: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,710 INFO L290 TraceCheckUtils]: 76: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,711 INFO L290 TraceCheckUtils]: 77: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,711 INFO L290 TraceCheckUtils]: 78: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~t8_pc~0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,711 INFO L290 TraceCheckUtils]: 79: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,711 INFO L290 TraceCheckUtils]: 80: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,712 INFO L290 TraceCheckUtils]: 81: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,712 INFO L290 TraceCheckUtils]: 82: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,712 INFO L290 TraceCheckUtils]: 83: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,712 INFO L290 TraceCheckUtils]: 84: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~t9_pc~0); {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,713 INFO L290 TraceCheckUtils]: 85: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,713 INFO L290 TraceCheckUtils]: 86: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,713 INFO L290 TraceCheckUtils]: 87: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,714 INFO L290 TraceCheckUtils]: 88: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,714 INFO L290 TraceCheckUtils]: 89: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,714 INFO L290 TraceCheckUtils]: 90: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,714 INFO L290 TraceCheckUtils]: 91: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,715 INFO L290 TraceCheckUtils]: 92: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {103206#(= (+ (- 1) ~T3_E~0) 0)} is VALID [2022-02-21 04:24:53,715 INFO L290 TraceCheckUtils]: 93: Hoare triple {103206#(= (+ (- 1) ~T3_E~0) 0)} assume !(1 == ~T3_E~0); {103205#false} is VALID [2022-02-21 04:24:53,715 INFO L290 TraceCheckUtils]: 94: Hoare triple {103205#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,715 INFO L290 TraceCheckUtils]: 95: Hoare triple {103205#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,715 INFO L290 TraceCheckUtils]: 96: Hoare triple {103205#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,715 INFO L290 TraceCheckUtils]: 97: Hoare triple {103205#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,716 INFO L290 TraceCheckUtils]: 98: Hoare triple {103205#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,716 INFO L290 TraceCheckUtils]: 99: Hoare triple {103205#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,716 INFO L290 TraceCheckUtils]: 100: Hoare triple {103205#false} assume 1 == ~E_1~0;~E_1~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,716 INFO L290 TraceCheckUtils]: 101: Hoare triple {103205#false} assume !(1 == ~E_2~0); {103205#false} is VALID [2022-02-21 04:24:53,716 INFO L290 TraceCheckUtils]: 102: Hoare triple {103205#false} assume 1 == ~E_3~0;~E_3~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,716 INFO L290 TraceCheckUtils]: 103: Hoare triple {103205#false} assume 1 == ~E_4~0;~E_4~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,716 INFO L290 TraceCheckUtils]: 104: Hoare triple {103205#false} assume 1 == ~E_5~0;~E_5~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,716 INFO L290 TraceCheckUtils]: 105: Hoare triple {103205#false} assume 1 == ~E_6~0;~E_6~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,717 INFO L290 TraceCheckUtils]: 106: Hoare triple {103205#false} assume 1 == ~E_7~0;~E_7~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,717 INFO L290 TraceCheckUtils]: 107: Hoare triple {103205#false} assume 1 == ~E_8~0;~E_8~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,717 INFO L290 TraceCheckUtils]: 108: Hoare triple {103205#false} assume 1 == ~E_9~0;~E_9~0 := 2; {103205#false} is VALID [2022-02-21 04:24:53,717 INFO L290 TraceCheckUtils]: 109: Hoare triple {103205#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {103205#false} is VALID [2022-02-21 04:24:53,717 INFO L290 TraceCheckUtils]: 110: Hoare triple {103205#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {103205#false} is VALID [2022-02-21 04:24:53,717 INFO L290 TraceCheckUtils]: 111: Hoare triple {103205#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {103205#false} is VALID [2022-02-21 04:24:53,717 INFO L290 TraceCheckUtils]: 112: Hoare triple {103205#false} start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; {103205#false} is VALID [2022-02-21 04:24:53,717 INFO L290 TraceCheckUtils]: 113: Hoare triple {103205#false} assume !(0 == start_simulation_~tmp~3#1); {103205#false} is VALID [2022-02-21 04:24:53,718 INFO L290 TraceCheckUtils]: 114: Hoare triple {103205#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; {103205#false} is VALID [2022-02-21 04:24:53,718 INFO L290 TraceCheckUtils]: 115: Hoare triple {103205#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; {103205#false} is VALID [2022-02-21 04:24:53,718 INFO L290 TraceCheckUtils]: 116: Hoare triple {103205#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; {103205#false} is VALID [2022-02-21 04:24:53,718 INFO L290 TraceCheckUtils]: 117: Hoare triple {103205#false} stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; {103205#false} is VALID [2022-02-21 04:24:53,718 INFO L290 TraceCheckUtils]: 118: Hoare triple {103205#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {103205#false} is VALID [2022-02-21 04:24:53,718 INFO L290 TraceCheckUtils]: 119: Hoare triple {103205#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {103205#false} is VALID [2022-02-21 04:24:53,718 INFO L290 TraceCheckUtils]: 120: Hoare triple {103205#false} start_simulation_#t~ret27#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; {103205#false} is VALID [2022-02-21 04:24:53,719 INFO L290 TraceCheckUtils]: 121: Hoare triple {103205#false} assume !(0 != start_simulation_~tmp___0~1#1); {103205#false} is VALID [2022-02-21 04:24:53,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:53,719 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:53,719 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372942124] [2022-02-21 04:24:53,719 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [372942124] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:53,720 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:53,720 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:53,720 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [813068721] [2022-02-21 04:24:53,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:53,720 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:53,720 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:53,721 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:53,721 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:53,721 INFO L87 Difference]: Start difference. First operand 10352 states and 15158 transitions. cyclomatic complexity: 4814 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:20,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:20,583 INFO L93 Difference]: Finished difference Result 29295 states and 42485 transitions. [2022-02-21 04:25:20,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:25:20,583 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:20,647 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 115 edges. 115 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:20,648 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29295 states and 42485 transitions.