./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.10.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.10.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:24:15,733 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:24:15,734 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:24:15,763 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:24:15,763 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:24:15,764 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:24:15,765 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:24:15,766 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:24:15,769 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:24:15,771 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:24:15,772 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:24:15,773 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:24:15,773 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:24:15,775 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:24:15,776 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:24:15,778 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:24:15,780 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:24:15,780 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:24:15,784 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:24:15,785 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:24:15,786 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:24:15,790 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:24:15,790 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:24:15,791 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:24:15,793 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:24:15,795 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:24:15,795 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:24:15,796 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:24:15,796 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:24:15,797 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:24:15,798 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:24:15,798 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:24:15,799 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:24:15,801 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:24:15,801 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:24:15,802 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:24:15,802 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:24:15,803 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:24:15,803 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:24:15,804 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:24:15,804 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:24:15,807 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:24:15,829 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:24:15,829 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:24:15,830 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:24:15,830 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:24:15,831 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:24:15,831 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:24:15,831 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:24:15,831 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:24:15,831 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:24:15,831 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:24:15,832 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:24:15,832 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:24:15,832 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:24:15,832 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:24:15,833 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:24:15,833 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:24:15,833 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:24:15,833 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:24:15,833 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:24:15,833 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:24:15,833 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:24:15,833 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:24:15,834 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:24:15,834 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:24:15,834 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:24:15,835 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:24:15,835 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:24:15,835 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:24:15,835 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:24:15,835 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:24:15,835 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:24:15,836 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:24:15,836 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 [2022-02-21 04:24:16,025 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:24:16,055 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:24:16,057 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:24:16,058 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:24:16,058 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:24:16,060 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.10.cil.c [2022-02-21 04:24:16,134 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/9f5a390f7/8b11406cf24c440da43f75f837deaef8/FLAG80e8e16e8 [2022-02-21 04:24:16,465 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:16,466 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.10.cil.c [2022-02-21 04:24:16,478 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/9f5a390f7/8b11406cf24c440da43f75f837deaef8/FLAG80e8e16e8 [2022-02-21 04:24:16,864 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/9f5a390f7/8b11406cf24c440da43f75f837deaef8 [2022-02-21 04:24:16,866 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:16,867 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:16,878 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:16,879 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:16,881 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:16,882 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:16" (1/1) ... [2022-02-21 04:24:16,883 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@ca21b19 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:16, skipping insertion in model container [2022-02-21 04:24:16,883 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:16" (1/1) ... [2022-02-21 04:24:16,887 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:16,911 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:17,047 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.10.cil.c[706,719] [2022-02-21 04:24:17,168 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:17,183 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:17,193 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.10.cil.c[706,719] [2022-02-21 04:24:17,272 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:17,286 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:17,287 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17 WrapperNode [2022-02-21 04:24:17,287 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:17,287 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:17,288 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:17,288 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:17,293 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17" (1/1) ... [2022-02-21 04:24:17,314 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17" (1/1) ... [2022-02-21 04:24:17,414 INFO L137 Inliner]: procedures = 48, calls = 60, calls flagged for inlining = 55, calls inlined = 196, statements flattened = 2994 [2022-02-21 04:24:17,415 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:17,416 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:17,416 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:17,416 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:17,422 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17" (1/1) ... [2022-02-21 04:24:17,422 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17" (1/1) ... [2022-02-21 04:24:17,429 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17" (1/1) ... [2022-02-21 04:24:17,429 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17" (1/1) ... [2022-02-21 04:24:17,470 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17" (1/1) ... [2022-02-21 04:24:17,530 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17" (1/1) ... [2022-02-21 04:24:17,533 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17" (1/1) ... [2022-02-21 04:24:17,539 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:17,579 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:17,580 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:17,580 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:17,581 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17" (1/1) ... [2022-02-21 04:24:17,586 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:17,593 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:17,617 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:17,649 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:17,685 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:17,685 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:17,685 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:17,685 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:17,864 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:17,866 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:19,286 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:19,297 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:19,297 INFO L299 CfgBuilder]: Removed 14 assume(true) statements. [2022-02-21 04:24:19,299 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:19 BoogieIcfgContainer [2022-02-21 04:24:19,299 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:19,300 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:19,300 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:19,302 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:19,303 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:19,303 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:16" (1/3) ... [2022-02-21 04:24:19,304 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1388bceb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:19, skipping insertion in model container [2022-02-21 04:24:19,304 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:19,304 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:17" (2/3) ... [2022-02-21 04:24:19,304 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1388bceb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:19, skipping insertion in model container [2022-02-21 04:24:19,305 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:19,305 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:19" (3/3) ... [2022-02-21 04:24:19,305 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.10.cil.c [2022-02-21 04:24:19,342 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:19,342 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:19,342 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:19,343 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:19,343 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:19,343 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:19,343 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:19,343 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:19,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,558 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1144 [2022-02-21 04:24:19,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:19,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:19,567 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:19,568 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:19,568 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:19,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:19,665 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1144 [2022-02-21 04:24:19,666 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:19,666 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:19,668 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:19,668 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:19,675 INFO L791 eck$LassoCheckResult]: Stem: 617#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 1166#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1096#L1483true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1051#L694true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1270#L701true assume !(1 == ~m_i~0);~m_st~0 := 2; 1144#L701-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1164#L706-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 284#L711-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 132#L716-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1186#L721-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 878#L726-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1069#L731-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 850#L736-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 924#L741-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1224#L746-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 159#L751-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 792#L1006true assume !(0 == ~M_E~0); 83#L1006-2true assume !(0 == ~T1_E~0); 978#L1011-1true assume !(0 == ~T2_E~0); 1017#L1016-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1169#L1021-1true assume !(0 == ~T4_E~0); 25#L1026-1true assume !(0 == ~T5_E~0); 1237#L1031-1true assume !(0 == ~T6_E~0); 562#L1036-1true assume !(0 == ~T7_E~0); 559#L1041-1true assume !(0 == ~T8_E~0); 896#L1046-1true assume !(0 == ~T9_E~0); 178#L1051-1true assume !(0 == ~T10_E~0); 702#L1056-1true assume 0 == ~E_1~0;~E_1~0 := 1; 748#L1061-1true assume !(0 == ~E_2~0); 134#L1066-1true assume !(0 == ~E_3~0); 1061#L1071-1true assume !(0 == ~E_4~0); 680#L1076-1true assume !(0 == ~E_5~0); 88#L1081-1true assume !(0 == ~E_6~0); 271#L1086-1true assume !(0 == ~E_7~0); 1075#L1091-1true assume !(0 == ~E_8~0); 951#L1096-1true assume 0 == ~E_9~0;~E_9~0 := 1; 1170#L1101-1true assume !(0 == ~E_10~0); 308#L1106-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1086#L484true assume !(1 == ~m_pc~0); 371#L484-2true is_master_triggered_~__retres1~0#1 := 0; 495#L495true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 879#L496true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 795#L1245true assume !(0 != activate_threads_~tmp~1#1); 1206#L1245-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 554#L503true assume 1 == ~t1_pc~0; 566#L504true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 734#L514true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 694#L515true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 384#L1253true assume !(0 != activate_threads_~tmp___0~0#1); 40#L1253-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 900#L522true assume !(1 == ~t2_pc~0); 522#L522-2true is_transmit2_triggered_~__retres1~2#1 := 0; 141#L533true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 424#L534true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 880#L1261true assume !(0 != activate_threads_~tmp___1~0#1); 1197#L1261-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1040#L541true assume 1 == ~t3_pc~0; 483#L542true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 825#L552true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 238#L553true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 591#L1269true assume !(0 != activate_threads_~tmp___2~0#1); 525#L1269-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 964#L560true assume !(1 == ~t4_pc~0); 1067#L560-2true is_transmit4_triggered_~__retres1~4#1 := 0; 463#L571true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 447#L572true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24#L1277true assume !(0 != activate_threads_~tmp___3~0#1); 888#L1277-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 166#L579true assume 1 == ~t5_pc~0; 3#L580true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55#L590true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 453#L591true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1015#L1285true assume !(0 != activate_threads_~tmp___4~0#1); 1090#L1285-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1263#L598true assume 1 == ~t6_pc~0; 220#L599true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 409#L609true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1185#L610true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 833#L1293true assume !(0 != activate_threads_~tmp___5~0#1); 598#L1293-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 548#L617true assume !(1 == ~t7_pc~0); 459#L617-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1180#L628true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 372#L629true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 902#L1301true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 327#L1301-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 595#L636true assume 1 == ~t8_pc~0; 445#L637true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 782#L647true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 309#L648true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 605#L1309true assume !(0 != activate_threads_~tmp___7~0#1); 415#L1309-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 684#L655true assume !(1 == ~t9_pc~0); 761#L655-2true is_transmit9_triggered_~__retres1~9#1 := 0; 1121#L666true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 196#L667true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1019#L1317true assume !(0 != activate_threads_~tmp___8~0#1); 618#L1317-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 961#L674true assume 1 == ~t10_pc~0; 78#L675true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1046#L685true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1203#L686true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1284#L1325true assume !(0 != activate_threads_~tmp___9~0#1); 408#L1325-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 890#L1119true assume !(1 == ~M_E~0); 123#L1119-2true assume !(1 == ~T1_E~0); 354#L1124-1true assume !(1 == ~T2_E~0); 36#L1129-1true assume !(1 == ~T3_E~0); 533#L1134-1true assume !(1 == ~T4_E~0); 197#L1139-1true assume !(1 == ~T5_E~0); 325#L1144-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1244#L1149-1true assume !(1 == ~T7_E~0); 120#L1154-1true assume !(1 == ~T8_E~0); 169#L1159-1true assume !(1 == ~T9_E~0); 1213#L1164-1true assume !(1 == ~T10_E~0); 426#L1169-1true assume !(1 == ~E_1~0); 347#L1174-1true assume !(1 == ~E_2~0); 227#L1179-1true assume !(1 == ~E_3~0); 162#L1184-1true assume 1 == ~E_4~0;~E_4~0 := 2; 193#L1189-1true assume !(1 == ~E_5~0); 260#L1194-1true assume !(1 == ~E_6~0); 1257#L1199-1true assume !(1 == ~E_7~0); 233#L1204-1true assume !(1 == ~E_8~0); 1119#L1209-1true assume !(1 == ~E_9~0); 615#L1214-1true assume !(1 == ~E_10~0); 1211#L1219-1true assume { :end_inline_reset_delta_events } true; 18#L1520-2true [2022-02-21 04:24:19,682 INFO L793 eck$LassoCheckResult]: Loop: 18#L1520-2true assume !false; 1267#L1521true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164#L981true assume !true; 322#L996true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1260#L694-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 321#L1006-3true assume 0 == ~M_E~0;~M_E~0 := 1; 959#L1006-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 731#L1011-3true assume !(0 == ~T2_E~0); 968#L1016-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 777#L1021-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 464#L1026-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1139#L1031-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 698#L1036-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1207#L1041-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 769#L1046-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1085#L1051-3true assume !(0 == ~T10_E~0); 699#L1056-3true assume 0 == ~E_1~0;~E_1~0 := 1; 175#L1061-3true assume 0 == ~E_2~0;~E_2~0 := 1; 177#L1066-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1227#L1071-3true assume 0 == ~E_4~0;~E_4~0 := 1; 992#L1076-3true assume 0 == ~E_5~0;~E_5~0 := 1; 67#L1081-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1140#L1086-3true assume 0 == ~E_7~0;~E_7~0 := 1; 91#L1091-3true assume !(0 == ~E_8~0); 1052#L1096-3true assume 0 == ~E_9~0;~E_9~0 := 1; 928#L1101-3true assume 0 == ~E_10~0;~E_10~0 := 1; 985#L1106-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 480#L484-33true assume 1 == ~m_pc~0; 1177#L485-11true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 418#L495-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 943#L496-11true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21#L1245-33true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 632#L1245-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 265#L503-33true assume !(1 == ~t1_pc~0); 895#L503-35true is_transmit1_triggered_~__retres1~1#1 := 0; 600#L514-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 530#L515-11true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 216#L1253-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 645#L1253-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 506#L522-33true assume 1 == ~t2_pc~0; 631#L523-11true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 85#L533-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 608#L534-11true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 804#L1261-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 521#L1261-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 875#L541-33true assume !(1 == ~t3_pc~0); 288#L541-35true is_transmit3_triggered_~__retres1~3#1 := 0; 20#L552-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 973#L553-11true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 500#L1269-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 932#L1269-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 693#L560-33true assume !(1 == ~t4_pc~0); 988#L560-35true is_transmit4_triggered_~__retres1~4#1 := 0; 57#L571-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189#L572-11true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1074#L1277-33true assume !(0 != activate_threads_~tmp___3~0#1); 672#L1277-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16#L579-33true assume 1 == ~t5_pc~0; 460#L580-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1033#L590-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1047#L591-11true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 549#L1285-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 569#L1285-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1035#L598-33true assume 1 == ~t6_pc~0; 1249#L599-11true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 278#L609-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 753#L610-11true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 192#L1293-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 901#L1293-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1155#L617-33true assume 1 == ~t7_pc~0; 918#L618-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 776#L628-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1002#L629-11true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1123#L1301-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 994#L1301-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50#L636-33true assume !(1 == ~t8_pc~0); 1010#L636-35true is_transmit8_triggered_~__retres1~8#1 := 0; 664#L647-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1165#L648-11true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1055#L1309-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 652#L1309-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1255#L655-33true assume 1 == ~t9_pc~0; 1171#L656-11true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 247#L666-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 487#L667-11true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 750#L1317-33true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1000#L1317-35true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 346#L674-33true assume !(1 == ~t10_pc~0); 1029#L674-35true is_transmit10_triggered_~__retres1~10#1 := 0; 1066#L685-11true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 202#L686-11true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 512#L1325-33true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1060#L1325-35true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1093#L1119-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1101#L1119-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1261#L1124-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1150#L1129-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 214#L1134-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 497#L1139-3true assume !(1 == ~T5_E~0); 342#L1144-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 450#L1149-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1248#L1154-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 708#L1159-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1230#L1164-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1005#L1169-3true assume 1 == ~E_1~0;~E_1~0 := 2; 277#L1174-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1083#L1179-3true assume !(1 == ~E_3~0); 835#L1184-3true assume 1 == ~E_4~0;~E_4~0 := 2; 80#L1189-3true assume 1 == ~E_5~0;~E_5~0 := 2; 840#L1194-3true assume 1 == ~E_6~0;~E_6~0 := 2; 244#L1199-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1266#L1204-3true assume 1 == ~E_8~0;~E_8~0 := 2; 438#L1209-3true assume 1 == ~E_9~0;~E_9~0 := 2; 27#L1214-3true assume 1 == ~E_10~0;~E_10~0 := 2; 937#L1219-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 607#L764-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 945#L821-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 254#L822-1true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 306#L1539true assume !(0 == start_simulation_~tmp~3#1); 501#L1539-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 428#L764-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 863#L821-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 386#L822-2true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 250#L1494true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 739#L1501true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 903#L1502true start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 307#L1552true assume !(0 != start_simulation_~tmp___0~1#1); 18#L1520-2true [2022-02-21 04:24:19,686 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:19,686 INFO L85 PathProgramCache]: Analyzing trace with hash 1310232617, now seen corresponding path program 1 times [2022-02-21 04:24:19,693 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:19,694 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1496310758] [2022-02-21 04:24:19,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:19,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:19,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:19,906 INFO L290 TraceCheckUtils]: 0: Hoare triple {1289#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {1289#true} is VALID [2022-02-21 04:24:19,907 INFO L290 TraceCheckUtils]: 1: Hoare triple {1289#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {1291#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:19,908 INFO L290 TraceCheckUtils]: 2: Hoare triple {1291#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1291#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:19,908 INFO L290 TraceCheckUtils]: 3: Hoare triple {1291#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1291#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:19,909 INFO L290 TraceCheckUtils]: 4: Hoare triple {1291#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1290#false} is VALID [2022-02-21 04:24:19,909 INFO L290 TraceCheckUtils]: 5: Hoare triple {1290#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1290#false} is VALID [2022-02-21 04:24:19,910 INFO L290 TraceCheckUtils]: 6: Hoare triple {1290#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1290#false} is VALID [2022-02-21 04:24:19,910 INFO L290 TraceCheckUtils]: 7: Hoare triple {1290#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1290#false} is VALID [2022-02-21 04:24:19,910 INFO L290 TraceCheckUtils]: 8: Hoare triple {1290#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1290#false} is VALID [2022-02-21 04:24:19,910 INFO L290 TraceCheckUtils]: 9: Hoare triple {1290#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1290#false} is VALID [2022-02-21 04:24:19,910 INFO L290 TraceCheckUtils]: 10: Hoare triple {1290#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1290#false} is VALID [2022-02-21 04:24:19,911 INFO L290 TraceCheckUtils]: 11: Hoare triple {1290#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1290#false} is VALID [2022-02-21 04:24:19,911 INFO L290 TraceCheckUtils]: 12: Hoare triple {1290#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1290#false} is VALID [2022-02-21 04:24:19,911 INFO L290 TraceCheckUtils]: 13: Hoare triple {1290#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {1290#false} is VALID [2022-02-21 04:24:19,911 INFO L290 TraceCheckUtils]: 14: Hoare triple {1290#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {1290#false} is VALID [2022-02-21 04:24:19,911 INFO L290 TraceCheckUtils]: 15: Hoare triple {1290#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1290#false} is VALID [2022-02-21 04:24:19,912 INFO L290 TraceCheckUtils]: 16: Hoare triple {1290#false} assume !(0 == ~M_E~0); {1290#false} is VALID [2022-02-21 04:24:19,912 INFO L290 TraceCheckUtils]: 17: Hoare triple {1290#false} assume !(0 == ~T1_E~0); {1290#false} is VALID [2022-02-21 04:24:19,912 INFO L290 TraceCheckUtils]: 18: Hoare triple {1290#false} assume !(0 == ~T2_E~0); {1290#false} is VALID [2022-02-21 04:24:19,912 INFO L290 TraceCheckUtils]: 19: Hoare triple {1290#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1290#false} is VALID [2022-02-21 04:24:19,912 INFO L290 TraceCheckUtils]: 20: Hoare triple {1290#false} assume !(0 == ~T4_E~0); {1290#false} is VALID [2022-02-21 04:24:19,913 INFO L290 TraceCheckUtils]: 21: Hoare triple {1290#false} assume !(0 == ~T5_E~0); {1290#false} is VALID [2022-02-21 04:24:19,913 INFO L290 TraceCheckUtils]: 22: Hoare triple {1290#false} assume !(0 == ~T6_E~0); {1290#false} is VALID [2022-02-21 04:24:19,913 INFO L290 TraceCheckUtils]: 23: Hoare triple {1290#false} assume !(0 == ~T7_E~0); {1290#false} is VALID [2022-02-21 04:24:19,914 INFO L290 TraceCheckUtils]: 24: Hoare triple {1290#false} assume !(0 == ~T8_E~0); {1290#false} is VALID [2022-02-21 04:24:19,914 INFO L290 TraceCheckUtils]: 25: Hoare triple {1290#false} assume !(0 == ~T9_E~0); {1290#false} is VALID [2022-02-21 04:24:19,914 INFO L290 TraceCheckUtils]: 26: Hoare triple {1290#false} assume !(0 == ~T10_E~0); {1290#false} is VALID [2022-02-21 04:24:19,914 INFO L290 TraceCheckUtils]: 27: Hoare triple {1290#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1290#false} is VALID [2022-02-21 04:24:19,914 INFO L290 TraceCheckUtils]: 28: Hoare triple {1290#false} assume !(0 == ~E_2~0); {1290#false} is VALID [2022-02-21 04:24:19,915 INFO L290 TraceCheckUtils]: 29: Hoare triple {1290#false} assume !(0 == ~E_3~0); {1290#false} is VALID [2022-02-21 04:24:19,915 INFO L290 TraceCheckUtils]: 30: Hoare triple {1290#false} assume !(0 == ~E_4~0); {1290#false} is VALID [2022-02-21 04:24:19,915 INFO L290 TraceCheckUtils]: 31: Hoare triple {1290#false} assume !(0 == ~E_5~0); {1290#false} is VALID [2022-02-21 04:24:19,915 INFO L290 TraceCheckUtils]: 32: Hoare triple {1290#false} assume !(0 == ~E_6~0); {1290#false} is VALID [2022-02-21 04:24:19,916 INFO L290 TraceCheckUtils]: 33: Hoare triple {1290#false} assume !(0 == ~E_7~0); {1290#false} is VALID [2022-02-21 04:24:19,916 INFO L290 TraceCheckUtils]: 34: Hoare triple {1290#false} assume !(0 == ~E_8~0); {1290#false} is VALID [2022-02-21 04:24:19,916 INFO L290 TraceCheckUtils]: 35: Hoare triple {1290#false} assume 0 == ~E_9~0;~E_9~0 := 1; {1290#false} is VALID [2022-02-21 04:24:19,916 INFO L290 TraceCheckUtils]: 36: Hoare triple {1290#false} assume !(0 == ~E_10~0); {1290#false} is VALID [2022-02-21 04:24:19,916 INFO L290 TraceCheckUtils]: 37: Hoare triple {1290#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1290#false} is VALID [2022-02-21 04:24:19,917 INFO L290 TraceCheckUtils]: 38: Hoare triple {1290#false} assume !(1 == ~m_pc~0); {1290#false} is VALID [2022-02-21 04:24:19,917 INFO L290 TraceCheckUtils]: 39: Hoare triple {1290#false} is_master_triggered_~__retres1~0#1 := 0; {1290#false} is VALID [2022-02-21 04:24:19,917 INFO L290 TraceCheckUtils]: 40: Hoare triple {1290#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1290#false} is VALID [2022-02-21 04:24:19,917 INFO L290 TraceCheckUtils]: 41: Hoare triple {1290#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {1290#false} is VALID [2022-02-21 04:24:19,918 INFO L290 TraceCheckUtils]: 42: Hoare triple {1290#false} assume !(0 != activate_threads_~tmp~1#1); {1290#false} is VALID [2022-02-21 04:24:19,918 INFO L290 TraceCheckUtils]: 43: Hoare triple {1290#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1290#false} is VALID [2022-02-21 04:24:19,918 INFO L290 TraceCheckUtils]: 44: Hoare triple {1290#false} assume 1 == ~t1_pc~0; {1290#false} is VALID [2022-02-21 04:24:19,919 INFO L290 TraceCheckUtils]: 45: Hoare triple {1290#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1290#false} is VALID [2022-02-21 04:24:19,919 INFO L290 TraceCheckUtils]: 46: Hoare triple {1290#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1290#false} is VALID [2022-02-21 04:24:19,919 INFO L290 TraceCheckUtils]: 47: Hoare triple {1290#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1290#false} is VALID [2022-02-21 04:24:19,919 INFO L290 TraceCheckUtils]: 48: Hoare triple {1290#false} assume !(0 != activate_threads_~tmp___0~0#1); {1290#false} is VALID [2022-02-21 04:24:19,922 INFO L290 TraceCheckUtils]: 49: Hoare triple {1290#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1290#false} is VALID [2022-02-21 04:24:19,922 INFO L290 TraceCheckUtils]: 50: Hoare triple {1290#false} assume !(1 == ~t2_pc~0); {1290#false} is VALID [2022-02-21 04:24:19,922 INFO L290 TraceCheckUtils]: 51: Hoare triple {1290#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1290#false} is VALID [2022-02-21 04:24:19,922 INFO L290 TraceCheckUtils]: 52: Hoare triple {1290#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1290#false} is VALID [2022-02-21 04:24:19,923 INFO L290 TraceCheckUtils]: 53: Hoare triple {1290#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1290#false} is VALID [2022-02-21 04:24:19,923 INFO L290 TraceCheckUtils]: 54: Hoare triple {1290#false} assume !(0 != activate_threads_~tmp___1~0#1); {1290#false} is VALID [2022-02-21 04:24:19,924 INFO L290 TraceCheckUtils]: 55: Hoare triple {1290#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1290#false} is VALID [2022-02-21 04:24:19,925 INFO L290 TraceCheckUtils]: 56: Hoare triple {1290#false} assume 1 == ~t3_pc~0; {1290#false} is VALID [2022-02-21 04:24:19,925 INFO L290 TraceCheckUtils]: 57: Hoare triple {1290#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1290#false} is VALID [2022-02-21 04:24:19,926 INFO L290 TraceCheckUtils]: 58: Hoare triple {1290#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1290#false} is VALID [2022-02-21 04:24:19,926 INFO L290 TraceCheckUtils]: 59: Hoare triple {1290#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1290#false} is VALID [2022-02-21 04:24:19,926 INFO L290 TraceCheckUtils]: 60: Hoare triple {1290#false} assume !(0 != activate_threads_~tmp___2~0#1); {1290#false} is VALID [2022-02-21 04:24:19,927 INFO L290 TraceCheckUtils]: 61: Hoare triple {1290#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1290#false} is VALID [2022-02-21 04:24:19,927 INFO L290 TraceCheckUtils]: 62: Hoare triple {1290#false} assume !(1 == ~t4_pc~0); {1290#false} is VALID [2022-02-21 04:24:19,927 INFO L290 TraceCheckUtils]: 63: Hoare triple {1290#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1290#false} is VALID [2022-02-21 04:24:19,928 INFO L290 TraceCheckUtils]: 64: Hoare triple {1290#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1290#false} is VALID [2022-02-21 04:24:19,929 INFO L290 TraceCheckUtils]: 65: Hoare triple {1290#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1290#false} is VALID [2022-02-21 04:24:19,930 INFO L290 TraceCheckUtils]: 66: Hoare triple {1290#false} assume !(0 != activate_threads_~tmp___3~0#1); {1290#false} is VALID [2022-02-21 04:24:19,930 INFO L290 TraceCheckUtils]: 67: Hoare triple {1290#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1290#false} is VALID [2022-02-21 04:24:19,930 INFO L290 TraceCheckUtils]: 68: Hoare triple {1290#false} assume 1 == ~t5_pc~0; {1290#false} is VALID [2022-02-21 04:24:19,930 INFO L290 TraceCheckUtils]: 69: Hoare triple {1290#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1290#false} is VALID [2022-02-21 04:24:19,931 INFO L290 TraceCheckUtils]: 70: Hoare triple {1290#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1290#false} is VALID [2022-02-21 04:24:19,931 INFO L290 TraceCheckUtils]: 71: Hoare triple {1290#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1290#false} is VALID [2022-02-21 04:24:19,931 INFO L290 TraceCheckUtils]: 72: Hoare triple {1290#false} assume !(0 != activate_threads_~tmp___4~0#1); {1290#false} is VALID [2022-02-21 04:24:19,931 INFO L290 TraceCheckUtils]: 73: Hoare triple {1290#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1290#false} is VALID [2022-02-21 04:24:19,935 INFO L290 TraceCheckUtils]: 74: Hoare triple {1290#false} assume 1 == ~t6_pc~0; {1290#false} is VALID [2022-02-21 04:24:19,936 INFO L290 TraceCheckUtils]: 75: Hoare triple {1290#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {1290#false} is VALID [2022-02-21 04:24:19,936 INFO L290 TraceCheckUtils]: 76: Hoare triple {1290#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1290#false} is VALID [2022-02-21 04:24:19,936 INFO L290 TraceCheckUtils]: 77: Hoare triple {1290#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1290#false} is VALID [2022-02-21 04:24:19,936 INFO L290 TraceCheckUtils]: 78: Hoare triple {1290#false} assume !(0 != activate_threads_~tmp___5~0#1); {1290#false} is VALID [2022-02-21 04:24:19,936 INFO L290 TraceCheckUtils]: 79: Hoare triple {1290#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1290#false} is VALID [2022-02-21 04:24:19,937 INFO L290 TraceCheckUtils]: 80: Hoare triple {1290#false} assume !(1 == ~t7_pc~0); {1290#false} is VALID [2022-02-21 04:24:19,937 INFO L290 TraceCheckUtils]: 81: Hoare triple {1290#false} is_transmit7_triggered_~__retres1~7#1 := 0; {1290#false} is VALID [2022-02-21 04:24:19,937 INFO L290 TraceCheckUtils]: 82: Hoare triple {1290#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1290#false} is VALID [2022-02-21 04:24:19,937 INFO L290 TraceCheckUtils]: 83: Hoare triple {1290#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1290#false} is VALID [2022-02-21 04:24:19,937 INFO L290 TraceCheckUtils]: 84: Hoare triple {1290#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {1290#false} is VALID [2022-02-21 04:24:19,938 INFO L290 TraceCheckUtils]: 85: Hoare triple {1290#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1290#false} is VALID [2022-02-21 04:24:19,938 INFO L290 TraceCheckUtils]: 86: Hoare triple {1290#false} assume 1 == ~t8_pc~0; {1290#false} is VALID [2022-02-21 04:24:19,938 INFO L290 TraceCheckUtils]: 87: Hoare triple {1290#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1290#false} is VALID [2022-02-21 04:24:19,938 INFO L290 TraceCheckUtils]: 88: Hoare triple {1290#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1290#false} is VALID [2022-02-21 04:24:19,938 INFO L290 TraceCheckUtils]: 89: Hoare triple {1290#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1290#false} is VALID [2022-02-21 04:24:19,938 INFO L290 TraceCheckUtils]: 90: Hoare triple {1290#false} assume !(0 != activate_threads_~tmp___7~0#1); {1290#false} is VALID [2022-02-21 04:24:19,939 INFO L290 TraceCheckUtils]: 91: Hoare triple {1290#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1290#false} is VALID [2022-02-21 04:24:19,939 INFO L290 TraceCheckUtils]: 92: Hoare triple {1290#false} assume !(1 == ~t9_pc~0); {1290#false} is VALID [2022-02-21 04:24:19,939 INFO L290 TraceCheckUtils]: 93: Hoare triple {1290#false} is_transmit9_triggered_~__retres1~9#1 := 0; {1290#false} is VALID [2022-02-21 04:24:19,939 INFO L290 TraceCheckUtils]: 94: Hoare triple {1290#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1290#false} is VALID [2022-02-21 04:24:19,940 INFO L290 TraceCheckUtils]: 95: Hoare triple {1290#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1290#false} is VALID [2022-02-21 04:24:19,940 INFO L290 TraceCheckUtils]: 96: Hoare triple {1290#false} assume !(0 != activate_threads_~tmp___8~0#1); {1290#false} is VALID [2022-02-21 04:24:19,940 INFO L290 TraceCheckUtils]: 97: Hoare triple {1290#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1290#false} is VALID [2022-02-21 04:24:19,940 INFO L290 TraceCheckUtils]: 98: Hoare triple {1290#false} assume 1 == ~t10_pc~0; {1290#false} is VALID [2022-02-21 04:24:19,940 INFO L290 TraceCheckUtils]: 99: Hoare triple {1290#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {1290#false} is VALID [2022-02-21 04:24:19,941 INFO L290 TraceCheckUtils]: 100: Hoare triple {1290#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1290#false} is VALID [2022-02-21 04:24:19,941 INFO L290 TraceCheckUtils]: 101: Hoare triple {1290#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1290#false} is VALID [2022-02-21 04:24:19,941 INFO L290 TraceCheckUtils]: 102: Hoare triple {1290#false} assume !(0 != activate_threads_~tmp___9~0#1); {1290#false} is VALID [2022-02-21 04:24:19,941 INFO L290 TraceCheckUtils]: 103: Hoare triple {1290#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1290#false} is VALID [2022-02-21 04:24:19,941 INFO L290 TraceCheckUtils]: 104: Hoare triple {1290#false} assume !(1 == ~M_E~0); {1290#false} is VALID [2022-02-21 04:24:19,943 INFO L290 TraceCheckUtils]: 105: Hoare triple {1290#false} assume !(1 == ~T1_E~0); {1290#false} is VALID [2022-02-21 04:24:19,943 INFO L290 TraceCheckUtils]: 106: Hoare triple {1290#false} assume !(1 == ~T2_E~0); {1290#false} is VALID [2022-02-21 04:24:19,944 INFO L290 TraceCheckUtils]: 107: Hoare triple {1290#false} assume !(1 == ~T3_E~0); {1290#false} is VALID [2022-02-21 04:24:19,944 INFO L290 TraceCheckUtils]: 108: Hoare triple {1290#false} assume !(1 == ~T4_E~0); {1290#false} is VALID [2022-02-21 04:24:19,944 INFO L290 TraceCheckUtils]: 109: Hoare triple {1290#false} assume !(1 == ~T5_E~0); {1290#false} is VALID [2022-02-21 04:24:19,944 INFO L290 TraceCheckUtils]: 110: Hoare triple {1290#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1290#false} is VALID [2022-02-21 04:24:19,944 INFO L290 TraceCheckUtils]: 111: Hoare triple {1290#false} assume !(1 == ~T7_E~0); {1290#false} is VALID [2022-02-21 04:24:19,944 INFO L290 TraceCheckUtils]: 112: Hoare triple {1290#false} assume !(1 == ~T8_E~0); {1290#false} is VALID [2022-02-21 04:24:19,945 INFO L290 TraceCheckUtils]: 113: Hoare triple {1290#false} assume !(1 == ~T9_E~0); {1290#false} is VALID [2022-02-21 04:24:19,945 INFO L290 TraceCheckUtils]: 114: Hoare triple {1290#false} assume !(1 == ~T10_E~0); {1290#false} is VALID [2022-02-21 04:24:19,945 INFO L290 TraceCheckUtils]: 115: Hoare triple {1290#false} assume !(1 == ~E_1~0); {1290#false} is VALID [2022-02-21 04:24:19,946 INFO L290 TraceCheckUtils]: 116: Hoare triple {1290#false} assume !(1 == ~E_2~0); {1290#false} is VALID [2022-02-21 04:24:19,947 INFO L290 TraceCheckUtils]: 117: Hoare triple {1290#false} assume !(1 == ~E_3~0); {1290#false} is VALID [2022-02-21 04:24:19,947 INFO L290 TraceCheckUtils]: 118: Hoare triple {1290#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1290#false} is VALID [2022-02-21 04:24:19,953 INFO L290 TraceCheckUtils]: 119: Hoare triple {1290#false} assume !(1 == ~E_5~0); {1290#false} is VALID [2022-02-21 04:24:19,954 INFO L290 TraceCheckUtils]: 120: Hoare triple {1290#false} assume !(1 == ~E_6~0); {1290#false} is VALID [2022-02-21 04:24:19,956 INFO L290 TraceCheckUtils]: 121: Hoare triple {1290#false} assume !(1 == ~E_7~0); {1290#false} is VALID [2022-02-21 04:24:19,956 INFO L290 TraceCheckUtils]: 122: Hoare triple {1290#false} assume !(1 == ~E_8~0); {1290#false} is VALID [2022-02-21 04:24:19,956 INFO L290 TraceCheckUtils]: 123: Hoare triple {1290#false} assume !(1 == ~E_9~0); {1290#false} is VALID [2022-02-21 04:24:19,956 INFO L290 TraceCheckUtils]: 124: Hoare triple {1290#false} assume !(1 == ~E_10~0); {1290#false} is VALID [2022-02-21 04:24:19,956 INFO L290 TraceCheckUtils]: 125: Hoare triple {1290#false} assume { :end_inline_reset_delta_events } true; {1290#false} is VALID [2022-02-21 04:24:19,958 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:19,958 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:19,958 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1496310758] [2022-02-21 04:24:19,959 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1496310758] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:19,959 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:19,960 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:19,962 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1866488120] [2022-02-21 04:24:19,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:19,966 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:19,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:19,968 INFO L85 PathProgramCache]: Analyzing trace with hash 1452797615, now seen corresponding path program 1 times [2022-02-21 04:24:19,968 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:19,968 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907609404] [2022-02-21 04:24:19,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:19,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:19,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:20,010 INFO L290 TraceCheckUtils]: 0: Hoare triple {1292#true} assume !false; {1292#true} is VALID [2022-02-21 04:24:20,011 INFO L290 TraceCheckUtils]: 1: Hoare triple {1292#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1292#true} is VALID [2022-02-21 04:24:20,011 INFO L290 TraceCheckUtils]: 2: Hoare triple {1292#true} assume !true; {1293#false} is VALID [2022-02-21 04:24:20,012 INFO L290 TraceCheckUtils]: 3: Hoare triple {1293#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1293#false} is VALID [2022-02-21 04:24:20,012 INFO L290 TraceCheckUtils]: 4: Hoare triple {1293#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1293#false} is VALID [2022-02-21 04:24:20,012 INFO L290 TraceCheckUtils]: 5: Hoare triple {1293#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,012 INFO L290 TraceCheckUtils]: 6: Hoare triple {1293#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,013 INFO L290 TraceCheckUtils]: 7: Hoare triple {1293#false} assume !(0 == ~T2_E~0); {1293#false} is VALID [2022-02-21 04:24:20,013 INFO L290 TraceCheckUtils]: 8: Hoare triple {1293#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,013 INFO L290 TraceCheckUtils]: 9: Hoare triple {1293#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,013 INFO L290 TraceCheckUtils]: 10: Hoare triple {1293#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,013 INFO L290 TraceCheckUtils]: 11: Hoare triple {1293#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,014 INFO L290 TraceCheckUtils]: 12: Hoare triple {1293#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,014 INFO L290 TraceCheckUtils]: 13: Hoare triple {1293#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,014 INFO L290 TraceCheckUtils]: 14: Hoare triple {1293#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,014 INFO L290 TraceCheckUtils]: 15: Hoare triple {1293#false} assume !(0 == ~T10_E~0); {1293#false} is VALID [2022-02-21 04:24:20,014 INFO L290 TraceCheckUtils]: 16: Hoare triple {1293#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,015 INFO L290 TraceCheckUtils]: 17: Hoare triple {1293#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,015 INFO L290 TraceCheckUtils]: 18: Hoare triple {1293#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,015 INFO L290 TraceCheckUtils]: 19: Hoare triple {1293#false} assume 0 == ~E_4~0;~E_4~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,015 INFO L290 TraceCheckUtils]: 20: Hoare triple {1293#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,016 INFO L290 TraceCheckUtils]: 21: Hoare triple {1293#false} assume 0 == ~E_6~0;~E_6~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,016 INFO L290 TraceCheckUtils]: 22: Hoare triple {1293#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,016 INFO L290 TraceCheckUtils]: 23: Hoare triple {1293#false} assume !(0 == ~E_8~0); {1293#false} is VALID [2022-02-21 04:24:20,016 INFO L290 TraceCheckUtils]: 24: Hoare triple {1293#false} assume 0 == ~E_9~0;~E_9~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,016 INFO L290 TraceCheckUtils]: 25: Hoare triple {1293#false} assume 0 == ~E_10~0;~E_10~0 := 1; {1293#false} is VALID [2022-02-21 04:24:20,017 INFO L290 TraceCheckUtils]: 26: Hoare triple {1293#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1293#false} is VALID [2022-02-21 04:24:20,017 INFO L290 TraceCheckUtils]: 27: Hoare triple {1293#false} assume 1 == ~m_pc~0; {1293#false} is VALID [2022-02-21 04:24:20,017 INFO L290 TraceCheckUtils]: 28: Hoare triple {1293#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {1293#false} is VALID [2022-02-21 04:24:20,017 INFO L290 TraceCheckUtils]: 29: Hoare triple {1293#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1293#false} is VALID [2022-02-21 04:24:20,017 INFO L290 TraceCheckUtils]: 30: Hoare triple {1293#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {1293#false} is VALID [2022-02-21 04:24:20,018 INFO L290 TraceCheckUtils]: 31: Hoare triple {1293#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1293#false} is VALID [2022-02-21 04:24:20,018 INFO L290 TraceCheckUtils]: 32: Hoare triple {1293#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1293#false} is VALID [2022-02-21 04:24:20,018 INFO L290 TraceCheckUtils]: 33: Hoare triple {1293#false} assume !(1 == ~t1_pc~0); {1293#false} is VALID [2022-02-21 04:24:20,018 INFO L290 TraceCheckUtils]: 34: Hoare triple {1293#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1293#false} is VALID [2022-02-21 04:24:20,019 INFO L290 TraceCheckUtils]: 35: Hoare triple {1293#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1293#false} is VALID [2022-02-21 04:24:20,019 INFO L290 TraceCheckUtils]: 36: Hoare triple {1293#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {1293#false} is VALID [2022-02-21 04:24:20,019 INFO L290 TraceCheckUtils]: 37: Hoare triple {1293#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1293#false} is VALID [2022-02-21 04:24:20,019 INFO L290 TraceCheckUtils]: 38: Hoare triple {1293#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1293#false} is VALID [2022-02-21 04:24:20,019 INFO L290 TraceCheckUtils]: 39: Hoare triple {1293#false} assume 1 == ~t2_pc~0; {1293#false} is VALID [2022-02-21 04:24:20,020 INFO L290 TraceCheckUtils]: 40: Hoare triple {1293#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1293#false} is VALID [2022-02-21 04:24:20,020 INFO L290 TraceCheckUtils]: 41: Hoare triple {1293#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1293#false} is VALID [2022-02-21 04:24:20,020 INFO L290 TraceCheckUtils]: 42: Hoare triple {1293#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1293#false} is VALID [2022-02-21 04:24:20,020 INFO L290 TraceCheckUtils]: 43: Hoare triple {1293#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1293#false} is VALID [2022-02-21 04:24:20,020 INFO L290 TraceCheckUtils]: 44: Hoare triple {1293#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1293#false} is VALID [2022-02-21 04:24:20,021 INFO L290 TraceCheckUtils]: 45: Hoare triple {1293#false} assume !(1 == ~t3_pc~0); {1293#false} is VALID [2022-02-21 04:24:20,021 INFO L290 TraceCheckUtils]: 46: Hoare triple {1293#false} is_transmit3_triggered_~__retres1~3#1 := 0; {1293#false} is VALID [2022-02-21 04:24:20,021 INFO L290 TraceCheckUtils]: 47: Hoare triple {1293#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1293#false} is VALID [2022-02-21 04:24:20,021 INFO L290 TraceCheckUtils]: 48: Hoare triple {1293#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1293#false} is VALID [2022-02-21 04:24:20,021 INFO L290 TraceCheckUtils]: 49: Hoare triple {1293#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1293#false} is VALID [2022-02-21 04:24:20,022 INFO L290 TraceCheckUtils]: 50: Hoare triple {1293#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1293#false} is VALID [2022-02-21 04:24:20,022 INFO L290 TraceCheckUtils]: 51: Hoare triple {1293#false} assume !(1 == ~t4_pc~0); {1293#false} is VALID [2022-02-21 04:24:20,022 INFO L290 TraceCheckUtils]: 52: Hoare triple {1293#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1293#false} is VALID [2022-02-21 04:24:20,022 INFO L290 TraceCheckUtils]: 53: Hoare triple {1293#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1293#false} is VALID [2022-02-21 04:24:20,022 INFO L290 TraceCheckUtils]: 54: Hoare triple {1293#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1293#false} is VALID [2022-02-21 04:24:20,023 INFO L290 TraceCheckUtils]: 55: Hoare triple {1293#false} assume !(0 != activate_threads_~tmp___3~0#1); {1293#false} is VALID [2022-02-21 04:24:20,023 INFO L290 TraceCheckUtils]: 56: Hoare triple {1293#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1293#false} is VALID [2022-02-21 04:24:20,023 INFO L290 TraceCheckUtils]: 57: Hoare triple {1293#false} assume 1 == ~t5_pc~0; {1293#false} is VALID [2022-02-21 04:24:20,023 INFO L290 TraceCheckUtils]: 58: Hoare triple {1293#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1293#false} is VALID [2022-02-21 04:24:20,023 INFO L290 TraceCheckUtils]: 59: Hoare triple {1293#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1293#false} is VALID [2022-02-21 04:24:20,024 INFO L290 TraceCheckUtils]: 60: Hoare triple {1293#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1293#false} is VALID [2022-02-21 04:24:20,024 INFO L290 TraceCheckUtils]: 61: Hoare triple {1293#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1293#false} is VALID [2022-02-21 04:24:20,024 INFO L290 TraceCheckUtils]: 62: Hoare triple {1293#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1293#false} is VALID [2022-02-21 04:24:20,024 INFO L290 TraceCheckUtils]: 63: Hoare triple {1293#false} assume 1 == ~t6_pc~0; {1293#false} is VALID [2022-02-21 04:24:20,024 INFO L290 TraceCheckUtils]: 64: Hoare triple {1293#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {1293#false} is VALID [2022-02-21 04:24:20,024 INFO L290 TraceCheckUtils]: 65: Hoare triple {1293#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1293#false} is VALID [2022-02-21 04:24:20,025 INFO L290 TraceCheckUtils]: 66: Hoare triple {1293#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1293#false} is VALID [2022-02-21 04:24:20,025 INFO L290 TraceCheckUtils]: 67: Hoare triple {1293#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1293#false} is VALID [2022-02-21 04:24:20,025 INFO L290 TraceCheckUtils]: 68: Hoare triple {1293#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1293#false} is VALID [2022-02-21 04:24:20,025 INFO L290 TraceCheckUtils]: 69: Hoare triple {1293#false} assume 1 == ~t7_pc~0; {1293#false} is VALID [2022-02-21 04:24:20,025 INFO L290 TraceCheckUtils]: 70: Hoare triple {1293#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1293#false} is VALID [2022-02-21 04:24:20,026 INFO L290 TraceCheckUtils]: 71: Hoare triple {1293#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1293#false} is VALID [2022-02-21 04:24:20,026 INFO L290 TraceCheckUtils]: 72: Hoare triple {1293#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1293#false} is VALID [2022-02-21 04:24:20,026 INFO L290 TraceCheckUtils]: 73: Hoare triple {1293#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {1293#false} is VALID [2022-02-21 04:24:20,026 INFO L290 TraceCheckUtils]: 74: Hoare triple {1293#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1293#false} is VALID [2022-02-21 04:24:20,026 INFO L290 TraceCheckUtils]: 75: Hoare triple {1293#false} assume !(1 == ~t8_pc~0); {1293#false} is VALID [2022-02-21 04:24:20,026 INFO L290 TraceCheckUtils]: 76: Hoare triple {1293#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1293#false} is VALID [2022-02-21 04:24:20,027 INFO L290 TraceCheckUtils]: 77: Hoare triple {1293#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1293#false} is VALID [2022-02-21 04:24:20,027 INFO L290 TraceCheckUtils]: 78: Hoare triple {1293#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1293#false} is VALID [2022-02-21 04:24:20,027 INFO L290 TraceCheckUtils]: 79: Hoare triple {1293#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1293#false} is VALID [2022-02-21 04:24:20,027 INFO L290 TraceCheckUtils]: 80: Hoare triple {1293#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1293#false} is VALID [2022-02-21 04:24:20,027 INFO L290 TraceCheckUtils]: 81: Hoare triple {1293#false} assume 1 == ~t9_pc~0; {1293#false} is VALID [2022-02-21 04:24:20,027 INFO L290 TraceCheckUtils]: 82: Hoare triple {1293#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1293#false} is VALID [2022-02-21 04:24:20,028 INFO L290 TraceCheckUtils]: 83: Hoare triple {1293#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1293#false} is VALID [2022-02-21 04:24:20,028 INFO L290 TraceCheckUtils]: 84: Hoare triple {1293#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1293#false} is VALID [2022-02-21 04:24:20,028 INFO L290 TraceCheckUtils]: 85: Hoare triple {1293#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {1293#false} is VALID [2022-02-21 04:24:20,028 INFO L290 TraceCheckUtils]: 86: Hoare triple {1293#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1293#false} is VALID [2022-02-21 04:24:20,028 INFO L290 TraceCheckUtils]: 87: Hoare triple {1293#false} assume !(1 == ~t10_pc~0); {1293#false} is VALID [2022-02-21 04:24:20,028 INFO L290 TraceCheckUtils]: 88: Hoare triple {1293#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1293#false} is VALID [2022-02-21 04:24:20,029 INFO L290 TraceCheckUtils]: 89: Hoare triple {1293#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1293#false} is VALID [2022-02-21 04:24:20,029 INFO L290 TraceCheckUtils]: 90: Hoare triple {1293#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1293#false} is VALID [2022-02-21 04:24:20,029 INFO L290 TraceCheckUtils]: 91: Hoare triple {1293#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {1293#false} is VALID [2022-02-21 04:24:20,029 INFO L290 TraceCheckUtils]: 92: Hoare triple {1293#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1293#false} is VALID [2022-02-21 04:24:20,029 INFO L290 TraceCheckUtils]: 93: Hoare triple {1293#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,029 INFO L290 TraceCheckUtils]: 94: Hoare triple {1293#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,030 INFO L290 TraceCheckUtils]: 95: Hoare triple {1293#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,030 INFO L290 TraceCheckUtils]: 96: Hoare triple {1293#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,030 INFO L290 TraceCheckUtils]: 97: Hoare triple {1293#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,030 INFO L290 TraceCheckUtils]: 98: Hoare triple {1293#false} assume !(1 == ~T5_E~0); {1293#false} is VALID [2022-02-21 04:24:20,030 INFO L290 TraceCheckUtils]: 99: Hoare triple {1293#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,030 INFO L290 TraceCheckUtils]: 100: Hoare triple {1293#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,031 INFO L290 TraceCheckUtils]: 101: Hoare triple {1293#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,031 INFO L290 TraceCheckUtils]: 102: Hoare triple {1293#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,031 INFO L290 TraceCheckUtils]: 103: Hoare triple {1293#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,031 INFO L290 TraceCheckUtils]: 104: Hoare triple {1293#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,031 INFO L290 TraceCheckUtils]: 105: Hoare triple {1293#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,031 INFO L290 TraceCheckUtils]: 106: Hoare triple {1293#false} assume !(1 == ~E_3~0); {1293#false} is VALID [2022-02-21 04:24:20,032 INFO L290 TraceCheckUtils]: 107: Hoare triple {1293#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,032 INFO L290 TraceCheckUtils]: 108: Hoare triple {1293#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,032 INFO L290 TraceCheckUtils]: 109: Hoare triple {1293#false} assume 1 == ~E_6~0;~E_6~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,032 INFO L290 TraceCheckUtils]: 110: Hoare triple {1293#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,032 INFO L290 TraceCheckUtils]: 111: Hoare triple {1293#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,032 INFO L290 TraceCheckUtils]: 112: Hoare triple {1293#false} assume 1 == ~E_9~0;~E_9~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,033 INFO L290 TraceCheckUtils]: 113: Hoare triple {1293#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1293#false} is VALID [2022-02-21 04:24:20,033 INFO L290 TraceCheckUtils]: 114: Hoare triple {1293#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {1293#false} is VALID [2022-02-21 04:24:20,033 INFO L290 TraceCheckUtils]: 115: Hoare triple {1293#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {1293#false} is VALID [2022-02-21 04:24:20,033 INFO L290 TraceCheckUtils]: 116: Hoare triple {1293#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {1293#false} is VALID [2022-02-21 04:24:20,033 INFO L290 TraceCheckUtils]: 117: Hoare triple {1293#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {1293#false} is VALID [2022-02-21 04:24:20,033 INFO L290 TraceCheckUtils]: 118: Hoare triple {1293#false} assume !(0 == start_simulation_~tmp~3#1); {1293#false} is VALID [2022-02-21 04:24:20,034 INFO L290 TraceCheckUtils]: 119: Hoare triple {1293#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {1293#false} is VALID [2022-02-21 04:24:20,034 INFO L290 TraceCheckUtils]: 120: Hoare triple {1293#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {1293#false} is VALID [2022-02-21 04:24:20,034 INFO L290 TraceCheckUtils]: 121: Hoare triple {1293#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {1293#false} is VALID [2022-02-21 04:24:20,034 INFO L290 TraceCheckUtils]: 122: Hoare triple {1293#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {1293#false} is VALID [2022-02-21 04:24:20,034 INFO L290 TraceCheckUtils]: 123: Hoare triple {1293#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1293#false} is VALID [2022-02-21 04:24:20,034 INFO L290 TraceCheckUtils]: 124: Hoare triple {1293#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1293#false} is VALID [2022-02-21 04:24:20,035 INFO L290 TraceCheckUtils]: 125: Hoare triple {1293#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {1293#false} is VALID [2022-02-21 04:24:20,035 INFO L290 TraceCheckUtils]: 126: Hoare triple {1293#false} assume !(0 != start_simulation_~tmp___0~1#1); {1293#false} is VALID [2022-02-21 04:24:20,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:20,036 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:20,036 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [907609404] [2022-02-21 04:24:20,036 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [907609404] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:20,036 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:20,036 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:20,037 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [272865338] [2022-02-21 04:24:20,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:20,038 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:20,039 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:20,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:20,058 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:20,062 INFO L87 Difference]: Start difference. First operand has 1285 states, 1284 states have (on average 1.5093457943925233) internal successors, (1938), 1284 states have internal predecessors, (1938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:21,480 INFO L93 Difference]: Finished difference Result 1284 states and 1907 transitions. [2022-02-21 04:24:21,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:21,481 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,577 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:21,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1284 states and 1907 transitions. [2022-02-21 04:24:21,815 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:21,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1284 states to 1278 states and 1901 transitions. [2022-02-21 04:24:21,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-02-21 04:24:21,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-02-21 04:24:21,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1901 transitions. [2022-02-21 04:24:21,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:21,869 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2022-02-21 04:24:21,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1901 transitions. [2022-02-21 04:24:21,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-02-21 04:24:21,914 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:21,917 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1278 states and 1901 transitions. Second operand has 1278 states, 1278 states have (on average 1.4874804381846636) internal successors, (1901), 1277 states have internal predecessors, (1901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,919 INFO L74 IsIncluded]: Start isIncluded. First operand 1278 states and 1901 transitions. Second operand has 1278 states, 1278 states have (on average 1.4874804381846636) internal successors, (1901), 1277 states have internal predecessors, (1901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,922 INFO L87 Difference]: Start difference. First operand 1278 states and 1901 transitions. Second operand has 1278 states, 1278 states have (on average 1.4874804381846636) internal successors, (1901), 1277 states have internal predecessors, (1901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:21,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:21,980 INFO L93 Difference]: Finished difference Result 1278 states and 1901 transitions. [2022-02-21 04:24:21,980 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1901 transitions. [2022-02-21 04:24:21,984 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:21,984 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:21,987 INFO L74 IsIncluded]: Start isIncluded. First operand has 1278 states, 1278 states have (on average 1.4874804381846636) internal successors, (1901), 1277 states have internal predecessors, (1901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1901 transitions. [2022-02-21 04:24:21,988 INFO L87 Difference]: Start difference. First operand has 1278 states, 1278 states have (on average 1.4874804381846636) internal successors, (1901), 1277 states have internal predecessors, (1901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1901 transitions. [2022-02-21 04:24:22,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:22,034 INFO L93 Difference]: Finished difference Result 1278 states and 1901 transitions. [2022-02-21 04:24:22,034 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1901 transitions. [2022-02-21 04:24:22,036 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:22,036 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:22,036 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:22,036 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:22,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4874804381846636) internal successors, (1901), 1277 states have internal predecessors, (1901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1901 transitions. [2022-02-21 04:24:22,080 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2022-02-21 04:24:22,080 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1901 transitions. [2022-02-21 04:24:22,080 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:22,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1901 transitions. [2022-02-21 04:24:22,084 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:22,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:22,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:22,087 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,087 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,087 INFO L791 eck$LassoCheckResult]: Stem: 3560#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 3561#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3835#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3823#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3824#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3844#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3845#L706-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3128#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2846#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2847#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3753#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3754#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3739#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3740#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3775#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2900#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2901#L1006 assume !(0 == ~M_E~0); 2749#L1006-2 assume !(0 == ~T1_E~0); 2750#L1011-1 assume !(0 == ~T2_E~0); 3797#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3812#L1021-1 assume !(0 == ~T4_E~0); 2631#L1026-1 assume !(0 == ~T5_E~0); 2632#L1031-1 assume !(0 == ~T6_E~0); 3505#L1036-1 assume !(0 == ~T7_E~0); 3501#L1041-1 assume !(0 == ~T8_E~0); 3502#L1046-1 assume !(0 == ~T9_E~0); 2931#L1051-1 assume !(0 == ~T10_E~0); 2932#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3634#L1061-1 assume !(0 == ~E_2~0); 2850#L1066-1 assume !(0 == ~E_3~0); 2851#L1071-1 assume !(0 == ~E_4~0); 3613#L1076-1 assume !(0 == ~E_5~0); 2760#L1081-1 assume !(0 == ~E_6~0); 2761#L1086-1 assume !(0 == ~E_7~0); 3103#L1091-1 assume !(0 == ~E_8~0); 3790#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 3791#L1101-1 assume !(0 == ~E_10~0); 3165#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3166#L484 assume !(1 == ~m_pc~0); 2809#L484-2 is_master_triggered_~__retres1~0#1 := 0; 2808#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3424#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3708#L1245 assume !(0 != activate_threads_~tmp~1#1); 3709#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3493#L503 assume 1 == ~t1_pc~0; 3494#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3511#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3626#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3279#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 2659#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2660#L522 assume !(1 == ~t2_pc~0); 3460#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2863#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2864#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3334#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3755#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3820#L541 assume 1 == ~t3_pc~0; 3409#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3225#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3040#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3041#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3463#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3464#L560 assume !(1 == ~t4_pc~0); 2743#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2742#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3368#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2627#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 2628#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2914#L579 assume 1 == ~t5_pc~0; 2578#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2579#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2687#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3371#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3811#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3832#L598 assume 1 == ~t6_pc~0; 3008#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3009#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3311#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3731#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3542#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3484#L617 assume !(1 == ~t7_pc~0); 2981#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2980#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3266#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3267#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3202#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3203#L636 assume 1 == ~t8_pc~0; 3365#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3366#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3167#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3168#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3318#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3319#L655 assume !(1 == ~t9_pc~0); 3348#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3349#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2960#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2961#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3562#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3563#L674 assume 1 == ~t10_pc~0; 2736#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2737#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3822#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3853#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3308#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3309#L1119 assume !(1 == ~M_E~0); 2832#L1119-2 assume !(1 == ~T1_E~0); 2833#L1124-1 assume !(1 == ~T2_E~0); 2651#L1129-1 assume !(1 == ~T3_E~0); 2652#L1134-1 assume !(1 == ~T4_E~0); 2965#L1139-1 assume !(1 == ~T5_E~0); 2966#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3198#L1149-1 assume !(1 == ~T7_E~0); 2827#L1154-1 assume !(1 == ~T8_E~0); 2828#L1159-1 assume !(1 == ~T9_E~0); 2915#L1164-1 assume !(1 == ~T10_E~0); 3337#L1169-1 assume !(1 == ~E_1~0); 3235#L1174-1 assume !(1 == ~E_2~0); 3022#L1179-1 assume !(1 == ~E_3~0); 2904#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2905#L1189-1 assume !(1 == ~E_5~0); 2958#L1194-1 assume !(1 == ~E_6~0); 3081#L1199-1 assume !(1 == ~E_7~0); 3032#L1204-1 assume !(1 == ~E_8~0); 3033#L1209-1 assume !(1 == ~E_9~0); 3556#L1214-1 assume !(1 == ~E_10~0); 3557#L1219-1 assume { :end_inline_reset_delta_events } true; 2615#L1520-2 [2022-02-21 04:24:22,088 INFO L793 eck$LassoCheckResult]: Loop: 2615#L1520-2 assume !false; 2616#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2719#L981 assume !false; 2911#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3583#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2601#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3701#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3751#L836 assume !(0 != eval_~tmp~0#1); 3193#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3194#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3189#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3190#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3660#L1011-3 assume !(0 == ~T2_E~0); 3661#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3700#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3383#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3384#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3628#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3629#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3691#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3692#L1051-3 assume !(0 == ~T10_E~0); 3630#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2928#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2929#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2930#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3801#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2713#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2714#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2768#L1091-3 assume !(0 == ~E_8~0); 2769#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3776#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3777#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3403#L484-33 assume 1 == ~m_pc~0; 3404#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3323#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3324#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2621#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2622#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3093#L503-33 assume !(1 == ~t1_pc~0); 3094#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3544#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3473#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3000#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3001#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3440#L522-33 assume 1 == ~t2_pc~0; 3441#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2756#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2757#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3550#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3458#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3459#L541-33 assume 1 == ~t3_pc~0; 2780#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2619#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2620#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3430#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3431#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3625#L560-33 assume 1 == ~t4_pc~0; 3330#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2691#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2692#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2948#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 3607#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2607#L579-33 assume 1 == ~t5_pc~0; 2608#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2856#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3816#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3485#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3486#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3510#L598-33 assume !(1 == ~t6_pc~0); 3283#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3114#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3115#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2955#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2956#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3765#L617-33 assume 1 == ~t7_pc~0; 3771#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2748#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3699#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3806#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3802#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2679#L636-33 assume !(1 == ~t8_pc~0); 2680#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3599#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3600#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3825#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3588#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3589#L655-33 assume 1 == ~t9_pc~0; 3849#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3055#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3056#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3414#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3678#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3234#L674-33 assume 1 == ~t10_pc~0; 3109#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3110#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2971#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2972#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3449#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3826#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3833#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3836#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3847#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2993#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2994#L1139-3 assume !(1 == ~T5_E~0); 3227#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3228#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3370#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3640#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3641#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3807#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3112#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3113#L1179-3 assume !(1 == ~E_3~0); 3732#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2739#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2740#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3053#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3054#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3357#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2633#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2634#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3547#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2716#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3070#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3071#L1539 assume !(0 == start_simulation_~tmp~3#1); 3163#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3339#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3146#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3278#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3062#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3063#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3667#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3164#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 2615#L1520-2 [2022-02-21 04:24:22,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:22,089 INFO L85 PathProgramCache]: Analyzing trace with hash -934325781, now seen corresponding path program 1 times [2022-02-21 04:24:22,089 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:22,089 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757500730] [2022-02-21 04:24:22,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:22,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:22,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:22,152 INFO L290 TraceCheckUtils]: 0: Hoare triple {6415#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {6415#true} is VALID [2022-02-21 04:24:22,152 INFO L290 TraceCheckUtils]: 1: Hoare triple {6415#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {6417#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:22,154 INFO L290 TraceCheckUtils]: 2: Hoare triple {6417#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {6417#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:22,155 INFO L290 TraceCheckUtils]: 3: Hoare triple {6417#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {6417#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:22,155 INFO L290 TraceCheckUtils]: 4: Hoare triple {6417#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {6417#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:22,156 INFO L290 TraceCheckUtils]: 5: Hoare triple {6417#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {6417#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:22,156 INFO L290 TraceCheckUtils]: 6: Hoare triple {6417#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {6416#false} is VALID [2022-02-21 04:24:22,156 INFO L290 TraceCheckUtils]: 7: Hoare triple {6416#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {6416#false} is VALID [2022-02-21 04:24:22,156 INFO L290 TraceCheckUtils]: 8: Hoare triple {6416#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {6416#false} is VALID [2022-02-21 04:24:22,156 INFO L290 TraceCheckUtils]: 9: Hoare triple {6416#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {6416#false} is VALID [2022-02-21 04:24:22,156 INFO L290 TraceCheckUtils]: 10: Hoare triple {6416#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {6416#false} is VALID [2022-02-21 04:24:22,156 INFO L290 TraceCheckUtils]: 11: Hoare triple {6416#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {6416#false} is VALID [2022-02-21 04:24:22,157 INFO L290 TraceCheckUtils]: 12: Hoare triple {6416#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {6416#false} is VALID [2022-02-21 04:24:22,157 INFO L290 TraceCheckUtils]: 13: Hoare triple {6416#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {6416#false} is VALID [2022-02-21 04:24:22,157 INFO L290 TraceCheckUtils]: 14: Hoare triple {6416#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {6416#false} is VALID [2022-02-21 04:24:22,157 INFO L290 TraceCheckUtils]: 15: Hoare triple {6416#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {6416#false} is VALID [2022-02-21 04:24:22,157 INFO L290 TraceCheckUtils]: 16: Hoare triple {6416#false} assume !(0 == ~M_E~0); {6416#false} is VALID [2022-02-21 04:24:22,157 INFO L290 TraceCheckUtils]: 17: Hoare triple {6416#false} assume !(0 == ~T1_E~0); {6416#false} is VALID [2022-02-21 04:24:22,157 INFO L290 TraceCheckUtils]: 18: Hoare triple {6416#false} assume !(0 == ~T2_E~0); {6416#false} is VALID [2022-02-21 04:24:22,158 INFO L290 TraceCheckUtils]: 19: Hoare triple {6416#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {6416#false} is VALID [2022-02-21 04:24:22,158 INFO L290 TraceCheckUtils]: 20: Hoare triple {6416#false} assume !(0 == ~T4_E~0); {6416#false} is VALID [2022-02-21 04:24:22,158 INFO L290 TraceCheckUtils]: 21: Hoare triple {6416#false} assume !(0 == ~T5_E~0); {6416#false} is VALID [2022-02-21 04:24:22,158 INFO L290 TraceCheckUtils]: 22: Hoare triple {6416#false} assume !(0 == ~T6_E~0); {6416#false} is VALID [2022-02-21 04:24:22,158 INFO L290 TraceCheckUtils]: 23: Hoare triple {6416#false} assume !(0 == ~T7_E~0); {6416#false} is VALID [2022-02-21 04:24:22,158 INFO L290 TraceCheckUtils]: 24: Hoare triple {6416#false} assume !(0 == ~T8_E~0); {6416#false} is VALID [2022-02-21 04:24:22,158 INFO L290 TraceCheckUtils]: 25: Hoare triple {6416#false} assume !(0 == ~T9_E~0); {6416#false} is VALID [2022-02-21 04:24:22,158 INFO L290 TraceCheckUtils]: 26: Hoare triple {6416#false} assume !(0 == ~T10_E~0); {6416#false} is VALID [2022-02-21 04:24:22,159 INFO L290 TraceCheckUtils]: 27: Hoare triple {6416#false} assume 0 == ~E_1~0;~E_1~0 := 1; {6416#false} is VALID [2022-02-21 04:24:22,161 INFO L290 TraceCheckUtils]: 28: Hoare triple {6416#false} assume !(0 == ~E_2~0); {6416#false} is VALID [2022-02-21 04:24:22,161 INFO L290 TraceCheckUtils]: 29: Hoare triple {6416#false} assume !(0 == ~E_3~0); {6416#false} is VALID [2022-02-21 04:24:22,162 INFO L290 TraceCheckUtils]: 30: Hoare triple {6416#false} assume !(0 == ~E_4~0); {6416#false} is VALID [2022-02-21 04:24:22,162 INFO L290 TraceCheckUtils]: 31: Hoare triple {6416#false} assume !(0 == ~E_5~0); {6416#false} is VALID [2022-02-21 04:24:22,162 INFO L290 TraceCheckUtils]: 32: Hoare triple {6416#false} assume !(0 == ~E_6~0); {6416#false} is VALID [2022-02-21 04:24:22,162 INFO L290 TraceCheckUtils]: 33: Hoare triple {6416#false} assume !(0 == ~E_7~0); {6416#false} is VALID [2022-02-21 04:24:22,162 INFO L290 TraceCheckUtils]: 34: Hoare triple {6416#false} assume !(0 == ~E_8~0); {6416#false} is VALID [2022-02-21 04:24:22,162 INFO L290 TraceCheckUtils]: 35: Hoare triple {6416#false} assume 0 == ~E_9~0;~E_9~0 := 1; {6416#false} is VALID [2022-02-21 04:24:22,162 INFO L290 TraceCheckUtils]: 36: Hoare triple {6416#false} assume !(0 == ~E_10~0); {6416#false} is VALID [2022-02-21 04:24:22,162 INFO L290 TraceCheckUtils]: 37: Hoare triple {6416#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6416#false} is VALID [2022-02-21 04:24:22,163 INFO L290 TraceCheckUtils]: 38: Hoare triple {6416#false} assume !(1 == ~m_pc~0); {6416#false} is VALID [2022-02-21 04:24:22,163 INFO L290 TraceCheckUtils]: 39: Hoare triple {6416#false} is_master_triggered_~__retres1~0#1 := 0; {6416#false} is VALID [2022-02-21 04:24:22,163 INFO L290 TraceCheckUtils]: 40: Hoare triple {6416#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6416#false} is VALID [2022-02-21 04:24:22,163 INFO L290 TraceCheckUtils]: 41: Hoare triple {6416#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {6416#false} is VALID [2022-02-21 04:24:22,163 INFO L290 TraceCheckUtils]: 42: Hoare triple {6416#false} assume !(0 != activate_threads_~tmp~1#1); {6416#false} is VALID [2022-02-21 04:24:22,163 INFO L290 TraceCheckUtils]: 43: Hoare triple {6416#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6416#false} is VALID [2022-02-21 04:24:22,163 INFO L290 TraceCheckUtils]: 44: Hoare triple {6416#false} assume 1 == ~t1_pc~0; {6416#false} is VALID [2022-02-21 04:24:22,164 INFO L290 TraceCheckUtils]: 45: Hoare triple {6416#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {6416#false} is VALID [2022-02-21 04:24:22,164 INFO L290 TraceCheckUtils]: 46: Hoare triple {6416#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6416#false} is VALID [2022-02-21 04:24:22,164 INFO L290 TraceCheckUtils]: 47: Hoare triple {6416#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {6416#false} is VALID [2022-02-21 04:24:22,164 INFO L290 TraceCheckUtils]: 48: Hoare triple {6416#false} assume !(0 != activate_threads_~tmp___0~0#1); {6416#false} is VALID [2022-02-21 04:24:22,164 INFO L290 TraceCheckUtils]: 49: Hoare triple {6416#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6416#false} is VALID [2022-02-21 04:24:22,164 INFO L290 TraceCheckUtils]: 50: Hoare triple {6416#false} assume !(1 == ~t2_pc~0); {6416#false} is VALID [2022-02-21 04:24:22,165 INFO L290 TraceCheckUtils]: 51: Hoare triple {6416#false} is_transmit2_triggered_~__retres1~2#1 := 0; {6416#false} is VALID [2022-02-21 04:24:22,165 INFO L290 TraceCheckUtils]: 52: Hoare triple {6416#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6416#false} is VALID [2022-02-21 04:24:22,165 INFO L290 TraceCheckUtils]: 53: Hoare triple {6416#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {6416#false} is VALID [2022-02-21 04:24:22,165 INFO L290 TraceCheckUtils]: 54: Hoare triple {6416#false} assume !(0 != activate_threads_~tmp___1~0#1); {6416#false} is VALID [2022-02-21 04:24:22,166 INFO L290 TraceCheckUtils]: 55: Hoare triple {6416#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6416#false} is VALID [2022-02-21 04:24:22,166 INFO L290 TraceCheckUtils]: 56: Hoare triple {6416#false} assume 1 == ~t3_pc~0; {6416#false} is VALID [2022-02-21 04:24:22,166 INFO L290 TraceCheckUtils]: 57: Hoare triple {6416#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6416#false} is VALID [2022-02-21 04:24:22,166 INFO L290 TraceCheckUtils]: 58: Hoare triple {6416#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6416#false} is VALID [2022-02-21 04:24:22,166 INFO L290 TraceCheckUtils]: 59: Hoare triple {6416#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {6416#false} is VALID [2022-02-21 04:24:22,166 INFO L290 TraceCheckUtils]: 60: Hoare triple {6416#false} assume !(0 != activate_threads_~tmp___2~0#1); {6416#false} is VALID [2022-02-21 04:24:22,166 INFO L290 TraceCheckUtils]: 61: Hoare triple {6416#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6416#false} is VALID [2022-02-21 04:24:22,167 INFO L290 TraceCheckUtils]: 62: Hoare triple {6416#false} assume !(1 == ~t4_pc~0); {6416#false} is VALID [2022-02-21 04:24:22,167 INFO L290 TraceCheckUtils]: 63: Hoare triple {6416#false} is_transmit4_triggered_~__retres1~4#1 := 0; {6416#false} is VALID [2022-02-21 04:24:22,167 INFO L290 TraceCheckUtils]: 64: Hoare triple {6416#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6416#false} is VALID [2022-02-21 04:24:22,167 INFO L290 TraceCheckUtils]: 65: Hoare triple {6416#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {6416#false} is VALID [2022-02-21 04:24:22,167 INFO L290 TraceCheckUtils]: 66: Hoare triple {6416#false} assume !(0 != activate_threads_~tmp___3~0#1); {6416#false} is VALID [2022-02-21 04:24:22,167 INFO L290 TraceCheckUtils]: 67: Hoare triple {6416#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6416#false} is VALID [2022-02-21 04:24:22,167 INFO L290 TraceCheckUtils]: 68: Hoare triple {6416#false} assume 1 == ~t5_pc~0; {6416#false} is VALID [2022-02-21 04:24:22,167 INFO L290 TraceCheckUtils]: 69: Hoare triple {6416#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {6416#false} is VALID [2022-02-21 04:24:22,168 INFO L290 TraceCheckUtils]: 70: Hoare triple {6416#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6416#false} is VALID [2022-02-21 04:24:22,168 INFO L290 TraceCheckUtils]: 71: Hoare triple {6416#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {6416#false} is VALID [2022-02-21 04:24:22,168 INFO L290 TraceCheckUtils]: 72: Hoare triple {6416#false} assume !(0 != activate_threads_~tmp___4~0#1); {6416#false} is VALID [2022-02-21 04:24:22,168 INFO L290 TraceCheckUtils]: 73: Hoare triple {6416#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {6416#false} is VALID [2022-02-21 04:24:22,168 INFO L290 TraceCheckUtils]: 74: Hoare triple {6416#false} assume 1 == ~t6_pc~0; {6416#false} is VALID [2022-02-21 04:24:22,168 INFO L290 TraceCheckUtils]: 75: Hoare triple {6416#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {6416#false} is VALID [2022-02-21 04:24:22,168 INFO L290 TraceCheckUtils]: 76: Hoare triple {6416#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {6416#false} is VALID [2022-02-21 04:24:22,168 INFO L290 TraceCheckUtils]: 77: Hoare triple {6416#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {6416#false} is VALID [2022-02-21 04:24:22,169 INFO L290 TraceCheckUtils]: 78: Hoare triple {6416#false} assume !(0 != activate_threads_~tmp___5~0#1); {6416#false} is VALID [2022-02-21 04:24:22,169 INFO L290 TraceCheckUtils]: 79: Hoare triple {6416#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {6416#false} is VALID [2022-02-21 04:24:22,169 INFO L290 TraceCheckUtils]: 80: Hoare triple {6416#false} assume !(1 == ~t7_pc~0); {6416#false} is VALID [2022-02-21 04:24:22,169 INFO L290 TraceCheckUtils]: 81: Hoare triple {6416#false} is_transmit7_triggered_~__retres1~7#1 := 0; {6416#false} is VALID [2022-02-21 04:24:22,169 INFO L290 TraceCheckUtils]: 82: Hoare triple {6416#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {6416#false} is VALID [2022-02-21 04:24:22,169 INFO L290 TraceCheckUtils]: 83: Hoare triple {6416#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {6416#false} is VALID [2022-02-21 04:24:22,169 INFO L290 TraceCheckUtils]: 84: Hoare triple {6416#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {6416#false} is VALID [2022-02-21 04:24:22,169 INFO L290 TraceCheckUtils]: 85: Hoare triple {6416#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {6416#false} is VALID [2022-02-21 04:24:22,170 INFO L290 TraceCheckUtils]: 86: Hoare triple {6416#false} assume 1 == ~t8_pc~0; {6416#false} is VALID [2022-02-21 04:24:22,174 INFO L290 TraceCheckUtils]: 87: Hoare triple {6416#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {6416#false} is VALID [2022-02-21 04:24:22,174 INFO L290 TraceCheckUtils]: 88: Hoare triple {6416#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {6416#false} is VALID [2022-02-21 04:24:22,174 INFO L290 TraceCheckUtils]: 89: Hoare triple {6416#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {6416#false} is VALID [2022-02-21 04:24:22,174 INFO L290 TraceCheckUtils]: 90: Hoare triple {6416#false} assume !(0 != activate_threads_~tmp___7~0#1); {6416#false} is VALID [2022-02-21 04:24:22,174 INFO L290 TraceCheckUtils]: 91: Hoare triple {6416#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {6416#false} is VALID [2022-02-21 04:24:22,175 INFO L290 TraceCheckUtils]: 92: Hoare triple {6416#false} assume !(1 == ~t9_pc~0); {6416#false} is VALID [2022-02-21 04:24:22,175 INFO L290 TraceCheckUtils]: 93: Hoare triple {6416#false} is_transmit9_triggered_~__retres1~9#1 := 0; {6416#false} is VALID [2022-02-21 04:24:22,175 INFO L290 TraceCheckUtils]: 94: Hoare triple {6416#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {6416#false} is VALID [2022-02-21 04:24:22,175 INFO L290 TraceCheckUtils]: 95: Hoare triple {6416#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {6416#false} is VALID [2022-02-21 04:24:22,175 INFO L290 TraceCheckUtils]: 96: Hoare triple {6416#false} assume !(0 != activate_threads_~tmp___8~0#1); {6416#false} is VALID [2022-02-21 04:24:22,175 INFO L290 TraceCheckUtils]: 97: Hoare triple {6416#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {6416#false} is VALID [2022-02-21 04:24:22,175 INFO L290 TraceCheckUtils]: 98: Hoare triple {6416#false} assume 1 == ~t10_pc~0; {6416#false} is VALID [2022-02-21 04:24:22,175 INFO L290 TraceCheckUtils]: 99: Hoare triple {6416#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {6416#false} is VALID [2022-02-21 04:24:22,176 INFO L290 TraceCheckUtils]: 100: Hoare triple {6416#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {6416#false} is VALID [2022-02-21 04:24:22,176 INFO L290 TraceCheckUtils]: 101: Hoare triple {6416#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {6416#false} is VALID [2022-02-21 04:24:22,176 INFO L290 TraceCheckUtils]: 102: Hoare triple {6416#false} assume !(0 != activate_threads_~tmp___9~0#1); {6416#false} is VALID [2022-02-21 04:24:22,176 INFO L290 TraceCheckUtils]: 103: Hoare triple {6416#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6416#false} is VALID [2022-02-21 04:24:22,176 INFO L290 TraceCheckUtils]: 104: Hoare triple {6416#false} assume !(1 == ~M_E~0); {6416#false} is VALID [2022-02-21 04:24:22,176 INFO L290 TraceCheckUtils]: 105: Hoare triple {6416#false} assume !(1 == ~T1_E~0); {6416#false} is VALID [2022-02-21 04:24:22,176 INFO L290 TraceCheckUtils]: 106: Hoare triple {6416#false} assume !(1 == ~T2_E~0); {6416#false} is VALID [2022-02-21 04:24:22,176 INFO L290 TraceCheckUtils]: 107: Hoare triple {6416#false} assume !(1 == ~T3_E~0); {6416#false} is VALID [2022-02-21 04:24:22,177 INFO L290 TraceCheckUtils]: 108: Hoare triple {6416#false} assume !(1 == ~T4_E~0); {6416#false} is VALID [2022-02-21 04:24:22,177 INFO L290 TraceCheckUtils]: 109: Hoare triple {6416#false} assume !(1 == ~T5_E~0); {6416#false} is VALID [2022-02-21 04:24:22,177 INFO L290 TraceCheckUtils]: 110: Hoare triple {6416#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {6416#false} is VALID [2022-02-21 04:24:22,177 INFO L290 TraceCheckUtils]: 111: Hoare triple {6416#false} assume !(1 == ~T7_E~0); {6416#false} is VALID [2022-02-21 04:24:22,177 INFO L290 TraceCheckUtils]: 112: Hoare triple {6416#false} assume !(1 == ~T8_E~0); {6416#false} is VALID [2022-02-21 04:24:22,177 INFO L290 TraceCheckUtils]: 113: Hoare triple {6416#false} assume !(1 == ~T9_E~0); {6416#false} is VALID [2022-02-21 04:24:22,177 INFO L290 TraceCheckUtils]: 114: Hoare triple {6416#false} assume !(1 == ~T10_E~0); {6416#false} is VALID [2022-02-21 04:24:22,178 INFO L290 TraceCheckUtils]: 115: Hoare triple {6416#false} assume !(1 == ~E_1~0); {6416#false} is VALID [2022-02-21 04:24:22,178 INFO L290 TraceCheckUtils]: 116: Hoare triple {6416#false} assume !(1 == ~E_2~0); {6416#false} is VALID [2022-02-21 04:24:22,178 INFO L290 TraceCheckUtils]: 117: Hoare triple {6416#false} assume !(1 == ~E_3~0); {6416#false} is VALID [2022-02-21 04:24:22,178 INFO L290 TraceCheckUtils]: 118: Hoare triple {6416#false} assume 1 == ~E_4~0;~E_4~0 := 2; {6416#false} is VALID [2022-02-21 04:24:22,178 INFO L290 TraceCheckUtils]: 119: Hoare triple {6416#false} assume !(1 == ~E_5~0); {6416#false} is VALID [2022-02-21 04:24:22,178 INFO L290 TraceCheckUtils]: 120: Hoare triple {6416#false} assume !(1 == ~E_6~0); {6416#false} is VALID [2022-02-21 04:24:22,181 INFO L290 TraceCheckUtils]: 121: Hoare triple {6416#false} assume !(1 == ~E_7~0); {6416#false} is VALID [2022-02-21 04:24:22,181 INFO L290 TraceCheckUtils]: 122: Hoare triple {6416#false} assume !(1 == ~E_8~0); {6416#false} is VALID [2022-02-21 04:24:22,187 INFO L290 TraceCheckUtils]: 123: Hoare triple {6416#false} assume !(1 == ~E_9~0); {6416#false} is VALID [2022-02-21 04:24:22,187 INFO L290 TraceCheckUtils]: 124: Hoare triple {6416#false} assume !(1 == ~E_10~0); {6416#false} is VALID [2022-02-21 04:24:22,188 INFO L290 TraceCheckUtils]: 125: Hoare triple {6416#false} assume { :end_inline_reset_delta_events } true; {6416#false} is VALID [2022-02-21 04:24:22,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:22,190 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:22,190 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757500730] [2022-02-21 04:24:22,190 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757500730] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:22,190 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:22,190 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:22,190 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [385329037] [2022-02-21 04:24:22,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:22,191 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:22,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:22,195 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 1 times [2022-02-21 04:24:22,195 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:22,195 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703498214] [2022-02-21 04:24:22,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:22,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:22,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:22,306 INFO L290 TraceCheckUtils]: 0: Hoare triple {6418#true} assume !false; {6418#true} is VALID [2022-02-21 04:24:22,306 INFO L290 TraceCheckUtils]: 1: Hoare triple {6418#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {6418#true} is VALID [2022-02-21 04:24:22,306 INFO L290 TraceCheckUtils]: 2: Hoare triple {6418#true} assume !false; {6418#true} is VALID [2022-02-21 04:24:22,307 INFO L290 TraceCheckUtils]: 3: Hoare triple {6418#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {6418#true} is VALID [2022-02-21 04:24:22,307 INFO L290 TraceCheckUtils]: 4: Hoare triple {6418#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {6418#true} is VALID [2022-02-21 04:24:22,307 INFO L290 TraceCheckUtils]: 5: Hoare triple {6418#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {6418#true} is VALID [2022-02-21 04:24:22,307 INFO L290 TraceCheckUtils]: 6: Hoare triple {6418#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {6418#true} is VALID [2022-02-21 04:24:22,307 INFO L290 TraceCheckUtils]: 7: Hoare triple {6418#true} assume !(0 != eval_~tmp~0#1); {6418#true} is VALID [2022-02-21 04:24:22,307 INFO L290 TraceCheckUtils]: 8: Hoare triple {6418#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {6418#true} is VALID [2022-02-21 04:24:22,307 INFO L290 TraceCheckUtils]: 9: Hoare triple {6418#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {6418#true} is VALID [2022-02-21 04:24:22,308 INFO L290 TraceCheckUtils]: 10: Hoare triple {6418#true} assume 0 == ~M_E~0;~M_E~0 := 1; {6418#true} is VALID [2022-02-21 04:24:22,308 INFO L290 TraceCheckUtils]: 11: Hoare triple {6418#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {6418#true} is VALID [2022-02-21 04:24:22,308 INFO L290 TraceCheckUtils]: 12: Hoare triple {6418#true} assume !(0 == ~T2_E~0); {6418#true} is VALID [2022-02-21 04:24:22,308 INFO L290 TraceCheckUtils]: 13: Hoare triple {6418#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {6418#true} is VALID [2022-02-21 04:24:22,308 INFO L290 TraceCheckUtils]: 14: Hoare triple {6418#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {6418#true} is VALID [2022-02-21 04:24:22,309 INFO L290 TraceCheckUtils]: 15: Hoare triple {6418#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,309 INFO L290 TraceCheckUtils]: 16: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,309 INFO L290 TraceCheckUtils]: 17: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,310 INFO L290 TraceCheckUtils]: 18: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,310 INFO L290 TraceCheckUtils]: 19: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,311 INFO L290 TraceCheckUtils]: 20: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,311 INFO L290 TraceCheckUtils]: 21: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,311 INFO L290 TraceCheckUtils]: 22: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,312 INFO L290 TraceCheckUtils]: 23: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,312 INFO L290 TraceCheckUtils]: 24: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,313 INFO L290 TraceCheckUtils]: 25: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,313 INFO L290 TraceCheckUtils]: 26: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,313 INFO L290 TraceCheckUtils]: 27: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,314 INFO L290 TraceCheckUtils]: 28: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,314 INFO L290 TraceCheckUtils]: 29: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,315 INFO L290 TraceCheckUtils]: 30: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,315 INFO L290 TraceCheckUtils]: 31: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,315 INFO L290 TraceCheckUtils]: 32: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,316 INFO L290 TraceCheckUtils]: 33: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,316 INFO L290 TraceCheckUtils]: 34: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,317 INFO L290 TraceCheckUtils]: 35: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,317 INFO L290 TraceCheckUtils]: 36: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,317 INFO L290 TraceCheckUtils]: 37: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,318 INFO L290 TraceCheckUtils]: 38: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,318 INFO L290 TraceCheckUtils]: 39: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,319 INFO L290 TraceCheckUtils]: 40: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,319 INFO L290 TraceCheckUtils]: 41: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,319 INFO L290 TraceCheckUtils]: 42: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,320 INFO L290 TraceCheckUtils]: 43: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,320 INFO L290 TraceCheckUtils]: 44: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,321 INFO L290 TraceCheckUtils]: 45: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,321 INFO L290 TraceCheckUtils]: 46: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,321 INFO L290 TraceCheckUtils]: 47: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,322 INFO L290 TraceCheckUtils]: 48: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,322 INFO L290 TraceCheckUtils]: 49: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,322 INFO L290 TraceCheckUtils]: 50: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,323 INFO L290 TraceCheckUtils]: 51: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,323 INFO L290 TraceCheckUtils]: 52: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 53: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 54: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,324 INFO L290 TraceCheckUtils]: 55: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,325 INFO L290 TraceCheckUtils]: 56: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,325 INFO L290 TraceCheckUtils]: 57: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,326 INFO L290 TraceCheckUtils]: 58: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,326 INFO L290 TraceCheckUtils]: 59: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,326 INFO L290 TraceCheckUtils]: 60: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,327 INFO L290 TraceCheckUtils]: 61: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,327 INFO L290 TraceCheckUtils]: 62: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,328 INFO L290 TraceCheckUtils]: 63: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,328 INFO L290 TraceCheckUtils]: 64: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,328 INFO L290 TraceCheckUtils]: 65: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,329 INFO L290 TraceCheckUtils]: 66: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,329 INFO L290 TraceCheckUtils]: 67: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,329 INFO L290 TraceCheckUtils]: 68: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,330 INFO L290 TraceCheckUtils]: 69: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,330 INFO L290 TraceCheckUtils]: 70: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,331 INFO L290 TraceCheckUtils]: 71: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,331 INFO L290 TraceCheckUtils]: 72: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,331 INFO L290 TraceCheckUtils]: 73: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,332 INFO L290 TraceCheckUtils]: 74: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,332 INFO L290 TraceCheckUtils]: 75: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,333 INFO L290 TraceCheckUtils]: 76: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,333 INFO L290 TraceCheckUtils]: 77: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,333 INFO L290 TraceCheckUtils]: 78: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,334 INFO L290 TraceCheckUtils]: 79: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,334 INFO L290 TraceCheckUtils]: 80: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,334 INFO L290 TraceCheckUtils]: 81: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,335 INFO L290 TraceCheckUtils]: 82: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,335 INFO L290 TraceCheckUtils]: 83: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,336 INFO L290 TraceCheckUtils]: 84: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,336 INFO L290 TraceCheckUtils]: 85: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,336 INFO L290 TraceCheckUtils]: 86: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,337 INFO L290 TraceCheckUtils]: 87: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,337 INFO L290 TraceCheckUtils]: 88: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,338 INFO L290 TraceCheckUtils]: 89: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,338 INFO L290 TraceCheckUtils]: 90: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,338 INFO L290 TraceCheckUtils]: 91: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,339 INFO L290 TraceCheckUtils]: 92: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,339 INFO L290 TraceCheckUtils]: 93: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,339 INFO L290 TraceCheckUtils]: 94: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,340 INFO L290 TraceCheckUtils]: 95: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,340 INFO L290 TraceCheckUtils]: 96: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,341 INFO L290 TraceCheckUtils]: 97: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,341 INFO L290 TraceCheckUtils]: 98: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,341 INFO L290 TraceCheckUtils]: 99: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,342 INFO L290 TraceCheckUtils]: 100: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,342 INFO L290 TraceCheckUtils]: 101: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,343 INFO L290 TraceCheckUtils]: 102: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {6420#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:22,343 INFO L290 TraceCheckUtils]: 103: Hoare triple {6420#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {6419#false} is VALID [2022-02-21 04:24:22,343 INFO L290 TraceCheckUtils]: 104: Hoare triple {6419#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,343 INFO L290 TraceCheckUtils]: 105: Hoare triple {6419#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,343 INFO L290 TraceCheckUtils]: 106: Hoare triple {6419#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,344 INFO L290 TraceCheckUtils]: 107: Hoare triple {6419#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,344 INFO L290 TraceCheckUtils]: 108: Hoare triple {6419#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,344 INFO L290 TraceCheckUtils]: 109: Hoare triple {6419#false} assume 1 == ~E_1~0;~E_1~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,344 INFO L290 TraceCheckUtils]: 110: Hoare triple {6419#false} assume 1 == ~E_2~0;~E_2~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,344 INFO L290 TraceCheckUtils]: 111: Hoare triple {6419#false} assume !(1 == ~E_3~0); {6419#false} is VALID [2022-02-21 04:24:22,344 INFO L290 TraceCheckUtils]: 112: Hoare triple {6419#false} assume 1 == ~E_4~0;~E_4~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,344 INFO L290 TraceCheckUtils]: 113: Hoare triple {6419#false} assume 1 == ~E_5~0;~E_5~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,345 INFO L290 TraceCheckUtils]: 114: Hoare triple {6419#false} assume 1 == ~E_6~0;~E_6~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,345 INFO L290 TraceCheckUtils]: 115: Hoare triple {6419#false} assume 1 == ~E_7~0;~E_7~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,345 INFO L290 TraceCheckUtils]: 116: Hoare triple {6419#false} assume 1 == ~E_8~0;~E_8~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,345 INFO L290 TraceCheckUtils]: 117: Hoare triple {6419#false} assume 1 == ~E_9~0;~E_9~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,345 INFO L290 TraceCheckUtils]: 118: Hoare triple {6419#false} assume 1 == ~E_10~0;~E_10~0 := 2; {6419#false} is VALID [2022-02-21 04:24:22,345 INFO L290 TraceCheckUtils]: 119: Hoare triple {6419#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {6419#false} is VALID [2022-02-21 04:24:22,345 INFO L290 TraceCheckUtils]: 120: Hoare triple {6419#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {6419#false} is VALID [2022-02-21 04:24:22,346 INFO L290 TraceCheckUtils]: 121: Hoare triple {6419#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {6419#false} is VALID [2022-02-21 04:24:22,346 INFO L290 TraceCheckUtils]: 122: Hoare triple {6419#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {6419#false} is VALID [2022-02-21 04:24:22,346 INFO L290 TraceCheckUtils]: 123: Hoare triple {6419#false} assume !(0 == start_simulation_~tmp~3#1); {6419#false} is VALID [2022-02-21 04:24:22,346 INFO L290 TraceCheckUtils]: 124: Hoare triple {6419#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {6419#false} is VALID [2022-02-21 04:24:22,346 INFO L290 TraceCheckUtils]: 125: Hoare triple {6419#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {6419#false} is VALID [2022-02-21 04:24:22,346 INFO L290 TraceCheckUtils]: 126: Hoare triple {6419#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {6419#false} is VALID [2022-02-21 04:24:22,346 INFO L290 TraceCheckUtils]: 127: Hoare triple {6419#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {6419#false} is VALID [2022-02-21 04:24:22,347 INFO L290 TraceCheckUtils]: 128: Hoare triple {6419#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {6419#false} is VALID [2022-02-21 04:24:22,347 INFO L290 TraceCheckUtils]: 129: Hoare triple {6419#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {6419#false} is VALID [2022-02-21 04:24:22,347 INFO L290 TraceCheckUtils]: 130: Hoare triple {6419#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {6419#false} is VALID [2022-02-21 04:24:22,347 INFO L290 TraceCheckUtils]: 131: Hoare triple {6419#false} assume !(0 != start_simulation_~tmp___0~1#1); {6419#false} is VALID [2022-02-21 04:24:22,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:22,348 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:22,348 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703498214] [2022-02-21 04:24:22,348 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1703498214] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:22,349 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:22,349 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:22,349 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528038078] [2022-02-21 04:24:22,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:22,349 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:22,350 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:22,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:22,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:22,351 INFO L87 Difference]: Start difference. First operand 1278 states and 1901 transitions. cyclomatic complexity: 624 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,274 INFO L93 Difference]: Finished difference Result 1278 states and 1900 transitions. [2022-02-21 04:24:23,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:23,275 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,356 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:23,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1900 transitions. [2022-02-21 04:24:23,399 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:23,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1900 transitions. [2022-02-21 04:24:23,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-02-21 04:24:23,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-02-21 04:24:23,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1900 transitions. [2022-02-21 04:24:23,470 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:23,470 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2022-02-21 04:24:23,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1900 transitions. [2022-02-21 04:24:23,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-02-21 04:24:23,487 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:23,489 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1278 states and 1900 transitions. Second operand has 1278 states, 1278 states have (on average 1.486697965571205) internal successors, (1900), 1277 states have internal predecessors, (1900), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,491 INFO L74 IsIncluded]: Start isIncluded. First operand 1278 states and 1900 transitions. Second operand has 1278 states, 1278 states have (on average 1.486697965571205) internal successors, (1900), 1277 states have internal predecessors, (1900), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,493 INFO L87 Difference]: Start difference. First operand 1278 states and 1900 transitions. Second operand has 1278 states, 1278 states have (on average 1.486697965571205) internal successors, (1900), 1277 states have internal predecessors, (1900), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,537 INFO L93 Difference]: Finished difference Result 1278 states and 1900 transitions. [2022-02-21 04:24:23,537 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1900 transitions. [2022-02-21 04:24:23,538 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:23,538 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:23,541 INFO L74 IsIncluded]: Start isIncluded. First operand has 1278 states, 1278 states have (on average 1.486697965571205) internal successors, (1900), 1277 states have internal predecessors, (1900), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1900 transitions. [2022-02-21 04:24:23,543 INFO L87 Difference]: Start difference. First operand has 1278 states, 1278 states have (on average 1.486697965571205) internal successors, (1900), 1277 states have internal predecessors, (1900), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1900 transitions. [2022-02-21 04:24:23,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,581 INFO L93 Difference]: Finished difference Result 1278 states and 1900 transitions. [2022-02-21 04:24:23,582 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1900 transitions. [2022-02-21 04:24:23,583 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:23,583 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:23,583 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:23,583 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:23,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.486697965571205) internal successors, (1900), 1277 states have internal predecessors, (1900), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1900 transitions. [2022-02-21 04:24:23,623 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2022-02-21 04:24:23,623 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1900 transitions. [2022-02-21 04:24:23,623 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:23,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1900 transitions. [2022-02-21 04:24:23,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:23,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:23,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:23,629 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,629 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,630 INFO L791 eck$LassoCheckResult]: Stem: 8680#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 8681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8956#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8944#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8945#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 8965#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8966#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8249#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7967#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7968#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8874#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8875#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8860#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8861#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8896#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8019#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8020#L1006 assume !(0 == ~M_E~0); 7870#L1006-2 assume !(0 == ~T1_E~0); 7871#L1011-1 assume !(0 == ~T2_E~0); 8918#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8933#L1021-1 assume !(0 == ~T4_E~0); 7750#L1026-1 assume !(0 == ~T5_E~0); 7751#L1031-1 assume !(0 == ~T6_E~0); 8626#L1036-1 assume !(0 == ~T7_E~0); 8622#L1041-1 assume !(0 == ~T8_E~0); 8623#L1046-1 assume !(0 == ~T9_E~0); 8052#L1051-1 assume !(0 == ~T10_E~0); 8053#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8755#L1061-1 assume !(0 == ~E_2~0); 7971#L1066-1 assume !(0 == ~E_3~0); 7972#L1071-1 assume !(0 == ~E_4~0); 8734#L1076-1 assume !(0 == ~E_5~0); 7881#L1081-1 assume !(0 == ~E_6~0); 7882#L1086-1 assume !(0 == ~E_7~0); 8224#L1091-1 assume !(0 == ~E_8~0); 8910#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8911#L1101-1 assume !(0 == ~E_10~0); 8286#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8287#L484 assume !(1 == ~m_pc~0); 7930#L484-2 is_master_triggered_~__retres1~0#1 := 0; 7929#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8545#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8829#L1245 assume !(0 != activate_threads_~tmp~1#1); 8830#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8614#L503 assume 1 == ~t1_pc~0; 8615#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8631#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8747#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8397#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 7780#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7781#L522 assume !(1 == ~t2_pc~0); 8581#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7984#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7985#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8455#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 8876#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8941#L541 assume 1 == ~t3_pc~0; 8530#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8346#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8161#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8162#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 8584#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8585#L560 assume !(1 == ~t4_pc~0); 7862#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7861#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8489#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7748#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 7749#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8033#L579 assume 1 == ~t5_pc~0; 7699#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7700#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7808#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8492#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 8931#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8953#L598 assume 1 == ~t6_pc~0; 8129#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8130#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8431#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8852#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 8663#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8605#L617 assume !(1 == ~t7_pc~0); 8102#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8101#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8387#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8388#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8323#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8324#L636 assume 1 == ~t8_pc~0; 8486#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8487#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8288#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8289#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 8439#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8440#L655 assume !(1 == ~t9_pc~0); 8467#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 8468#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8081#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8082#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 8682#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8683#L674 assume 1 == ~t10_pc~0; 7857#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7858#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8943#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8974#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 8429#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8430#L1119 assume !(1 == ~M_E~0); 7953#L1119-2 assume !(1 == ~T1_E~0); 7954#L1124-1 assume !(1 == ~T2_E~0); 7772#L1129-1 assume !(1 == ~T3_E~0); 7773#L1134-1 assume !(1 == ~T4_E~0); 8083#L1139-1 assume !(1 == ~T5_E~0); 8084#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8319#L1149-1 assume !(1 == ~T7_E~0); 7948#L1154-1 assume !(1 == ~T8_E~0); 7949#L1159-1 assume !(1 == ~T9_E~0); 8036#L1164-1 assume !(1 == ~T10_E~0); 8458#L1169-1 assume !(1 == ~E_1~0); 8356#L1174-1 assume !(1 == ~E_2~0); 8143#L1179-1 assume !(1 == ~E_3~0); 8025#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8026#L1189-1 assume !(1 == ~E_5~0); 8078#L1194-1 assume !(1 == ~E_6~0); 8202#L1199-1 assume !(1 == ~E_7~0); 8153#L1204-1 assume !(1 == ~E_8~0); 8154#L1209-1 assume !(1 == ~E_9~0); 8677#L1214-1 assume !(1 == ~E_10~0); 8678#L1219-1 assume { :end_inline_reset_delta_events } true; 7736#L1520-2 [2022-02-21 04:24:23,630 INFO L793 eck$LassoCheckResult]: Loop: 7736#L1520-2 assume !false; 7737#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7837#L981 assume !false; 8029#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8704#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7722#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8822#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8872#L836 assume !(0 != eval_~tmp~0#1); 8314#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8315#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8310#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8311#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8781#L1011-3 assume !(0 == ~T2_E~0); 8782#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8821#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8502#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8503#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8749#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8750#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8810#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8811#L1051-3 assume !(0 == ~T10_E~0); 8751#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8047#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8048#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8051#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8922#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7834#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7835#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7887#L1091-3 assume !(0 == ~E_8~0); 7888#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8897#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8898#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8524#L484-33 assume 1 == ~m_pc~0; 8525#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8444#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8445#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7742#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7743#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8211#L503-33 assume !(1 == ~t1_pc~0); 8212#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 8665#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8592#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8121#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8122#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8561#L522-33 assume 1 == ~t2_pc~0; 8562#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7875#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7876#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8670#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8579#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8580#L541-33 assume 1 == ~t3_pc~0; 7901#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7740#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7741#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8551#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8552#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8746#L560-33 assume 1 == ~t4_pc~0; 8451#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7812#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7813#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8071#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 8728#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7731#L579-33 assume 1 == ~t5_pc~0; 7732#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7978#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8937#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8606#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8607#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8635#L598-33 assume !(1 == ~t6_pc~0); 8409#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 8235#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8236#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8076#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8077#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8886#L617-33 assume 1 == ~t7_pc~0; 8892#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7869#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8820#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8927#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8923#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7800#L636-33 assume !(1 == ~t8_pc~0); 7801#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 8720#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8721#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8946#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8711#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8712#L655-33 assume 1 == ~t9_pc~0; 8970#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8178#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8179#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8535#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8799#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8355#L674-33 assume 1 == ~t10_pc~0; 8230#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8231#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8092#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8093#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8570#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8947#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8954#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8958#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8968#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8117#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8118#L1139-3 assume !(1 == ~T5_E~0); 8348#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8349#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8491#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8761#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8762#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8929#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8233#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8234#L1179-3 assume !(1 == ~E_3~0); 8853#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7863#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7864#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8174#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8175#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8478#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7754#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7755#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8669#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7840#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8191#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 8192#L1539 assume !(0 == start_simulation_~tmp~3#1); 8284#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8460#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8267#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8400#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 8183#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8184#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8788#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8285#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 7736#L1520-2 [2022-02-21 04:24:23,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:23,630 INFO L85 PathProgramCache]: Analyzing trace with hash 158309421, now seen corresponding path program 1 times [2022-02-21 04:24:23,631 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:23,631 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207008617] [2022-02-21 04:24:23,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:23,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:23,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:23,671 INFO L290 TraceCheckUtils]: 0: Hoare triple {11536#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {11536#true} is VALID [2022-02-21 04:24:23,671 INFO L290 TraceCheckUtils]: 1: Hoare triple {11536#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {11538#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:23,671 INFO L290 TraceCheckUtils]: 2: Hoare triple {11538#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {11538#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:23,672 INFO L290 TraceCheckUtils]: 3: Hoare triple {11538#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {11538#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:23,672 INFO L290 TraceCheckUtils]: 4: Hoare triple {11538#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {11538#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:23,672 INFO L290 TraceCheckUtils]: 5: Hoare triple {11538#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {11538#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:23,672 INFO L290 TraceCheckUtils]: 6: Hoare triple {11538#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {11538#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:23,673 INFO L290 TraceCheckUtils]: 7: Hoare triple {11538#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {11537#false} is VALID [2022-02-21 04:24:23,673 INFO L290 TraceCheckUtils]: 8: Hoare triple {11537#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {11537#false} is VALID [2022-02-21 04:24:23,673 INFO L290 TraceCheckUtils]: 9: Hoare triple {11537#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {11537#false} is VALID [2022-02-21 04:24:23,673 INFO L290 TraceCheckUtils]: 10: Hoare triple {11537#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {11537#false} is VALID [2022-02-21 04:24:23,673 INFO L290 TraceCheckUtils]: 11: Hoare triple {11537#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {11537#false} is VALID [2022-02-21 04:24:23,673 INFO L290 TraceCheckUtils]: 12: Hoare triple {11537#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {11537#false} is VALID [2022-02-21 04:24:23,673 INFO L290 TraceCheckUtils]: 13: Hoare triple {11537#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {11537#false} is VALID [2022-02-21 04:24:23,674 INFO L290 TraceCheckUtils]: 14: Hoare triple {11537#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {11537#false} is VALID [2022-02-21 04:24:23,674 INFO L290 TraceCheckUtils]: 15: Hoare triple {11537#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {11537#false} is VALID [2022-02-21 04:24:23,674 INFO L290 TraceCheckUtils]: 16: Hoare triple {11537#false} assume !(0 == ~M_E~0); {11537#false} is VALID [2022-02-21 04:24:23,674 INFO L290 TraceCheckUtils]: 17: Hoare triple {11537#false} assume !(0 == ~T1_E~0); {11537#false} is VALID [2022-02-21 04:24:23,674 INFO L290 TraceCheckUtils]: 18: Hoare triple {11537#false} assume !(0 == ~T2_E~0); {11537#false} is VALID [2022-02-21 04:24:23,674 INFO L290 TraceCheckUtils]: 19: Hoare triple {11537#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {11537#false} is VALID [2022-02-21 04:24:23,674 INFO L290 TraceCheckUtils]: 20: Hoare triple {11537#false} assume !(0 == ~T4_E~0); {11537#false} is VALID [2022-02-21 04:24:23,674 INFO L290 TraceCheckUtils]: 21: Hoare triple {11537#false} assume !(0 == ~T5_E~0); {11537#false} is VALID [2022-02-21 04:24:23,675 INFO L290 TraceCheckUtils]: 22: Hoare triple {11537#false} assume !(0 == ~T6_E~0); {11537#false} is VALID [2022-02-21 04:24:23,675 INFO L290 TraceCheckUtils]: 23: Hoare triple {11537#false} assume !(0 == ~T7_E~0); {11537#false} is VALID [2022-02-21 04:24:23,675 INFO L290 TraceCheckUtils]: 24: Hoare triple {11537#false} assume !(0 == ~T8_E~0); {11537#false} is VALID [2022-02-21 04:24:23,691 INFO L290 TraceCheckUtils]: 25: Hoare triple {11537#false} assume !(0 == ~T9_E~0); {11537#false} is VALID [2022-02-21 04:24:23,691 INFO L290 TraceCheckUtils]: 26: Hoare triple {11537#false} assume !(0 == ~T10_E~0); {11537#false} is VALID [2022-02-21 04:24:23,691 INFO L290 TraceCheckUtils]: 27: Hoare triple {11537#false} assume 0 == ~E_1~0;~E_1~0 := 1; {11537#false} is VALID [2022-02-21 04:24:23,691 INFO L290 TraceCheckUtils]: 28: Hoare triple {11537#false} assume !(0 == ~E_2~0); {11537#false} is VALID [2022-02-21 04:24:23,692 INFO L290 TraceCheckUtils]: 29: Hoare triple {11537#false} assume !(0 == ~E_3~0); {11537#false} is VALID [2022-02-21 04:24:23,692 INFO L290 TraceCheckUtils]: 30: Hoare triple {11537#false} assume !(0 == ~E_4~0); {11537#false} is VALID [2022-02-21 04:24:23,692 INFO L290 TraceCheckUtils]: 31: Hoare triple {11537#false} assume !(0 == ~E_5~0); {11537#false} is VALID [2022-02-21 04:24:23,692 INFO L290 TraceCheckUtils]: 32: Hoare triple {11537#false} assume !(0 == ~E_6~0); {11537#false} is VALID [2022-02-21 04:24:23,692 INFO L290 TraceCheckUtils]: 33: Hoare triple {11537#false} assume !(0 == ~E_7~0); {11537#false} is VALID [2022-02-21 04:24:23,692 INFO L290 TraceCheckUtils]: 34: Hoare triple {11537#false} assume !(0 == ~E_8~0); {11537#false} is VALID [2022-02-21 04:24:23,692 INFO L290 TraceCheckUtils]: 35: Hoare triple {11537#false} assume 0 == ~E_9~0;~E_9~0 := 1; {11537#false} is VALID [2022-02-21 04:24:23,692 INFO L290 TraceCheckUtils]: 36: Hoare triple {11537#false} assume !(0 == ~E_10~0); {11537#false} is VALID [2022-02-21 04:24:23,693 INFO L290 TraceCheckUtils]: 37: Hoare triple {11537#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {11537#false} is VALID [2022-02-21 04:24:23,693 INFO L290 TraceCheckUtils]: 38: Hoare triple {11537#false} assume !(1 == ~m_pc~0); {11537#false} is VALID [2022-02-21 04:24:23,693 INFO L290 TraceCheckUtils]: 39: Hoare triple {11537#false} is_master_triggered_~__retres1~0#1 := 0; {11537#false} is VALID [2022-02-21 04:24:23,693 INFO L290 TraceCheckUtils]: 40: Hoare triple {11537#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {11537#false} is VALID [2022-02-21 04:24:23,693 INFO L290 TraceCheckUtils]: 41: Hoare triple {11537#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {11537#false} is VALID [2022-02-21 04:24:23,693 INFO L290 TraceCheckUtils]: 42: Hoare triple {11537#false} assume !(0 != activate_threads_~tmp~1#1); {11537#false} is VALID [2022-02-21 04:24:23,693 INFO L290 TraceCheckUtils]: 43: Hoare triple {11537#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {11537#false} is VALID [2022-02-21 04:24:23,693 INFO L290 TraceCheckUtils]: 44: Hoare triple {11537#false} assume 1 == ~t1_pc~0; {11537#false} is VALID [2022-02-21 04:24:23,694 INFO L290 TraceCheckUtils]: 45: Hoare triple {11537#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {11537#false} is VALID [2022-02-21 04:24:23,694 INFO L290 TraceCheckUtils]: 46: Hoare triple {11537#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {11537#false} is VALID [2022-02-21 04:24:23,694 INFO L290 TraceCheckUtils]: 47: Hoare triple {11537#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {11537#false} is VALID [2022-02-21 04:24:23,694 INFO L290 TraceCheckUtils]: 48: Hoare triple {11537#false} assume !(0 != activate_threads_~tmp___0~0#1); {11537#false} is VALID [2022-02-21 04:24:23,694 INFO L290 TraceCheckUtils]: 49: Hoare triple {11537#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {11537#false} is VALID [2022-02-21 04:24:23,694 INFO L290 TraceCheckUtils]: 50: Hoare triple {11537#false} assume !(1 == ~t2_pc~0); {11537#false} is VALID [2022-02-21 04:24:23,694 INFO L290 TraceCheckUtils]: 51: Hoare triple {11537#false} is_transmit2_triggered_~__retres1~2#1 := 0; {11537#false} is VALID [2022-02-21 04:24:23,694 INFO L290 TraceCheckUtils]: 52: Hoare triple {11537#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {11537#false} is VALID [2022-02-21 04:24:23,694 INFO L290 TraceCheckUtils]: 53: Hoare triple {11537#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {11537#false} is VALID [2022-02-21 04:24:23,695 INFO L290 TraceCheckUtils]: 54: Hoare triple {11537#false} assume !(0 != activate_threads_~tmp___1~0#1); {11537#false} is VALID [2022-02-21 04:24:23,695 INFO L290 TraceCheckUtils]: 55: Hoare triple {11537#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {11537#false} is VALID [2022-02-21 04:24:23,695 INFO L290 TraceCheckUtils]: 56: Hoare triple {11537#false} assume 1 == ~t3_pc~0; {11537#false} is VALID [2022-02-21 04:24:23,695 INFO L290 TraceCheckUtils]: 57: Hoare triple {11537#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {11537#false} is VALID [2022-02-21 04:24:23,695 INFO L290 TraceCheckUtils]: 58: Hoare triple {11537#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {11537#false} is VALID [2022-02-21 04:24:23,695 INFO L290 TraceCheckUtils]: 59: Hoare triple {11537#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {11537#false} is VALID [2022-02-21 04:24:23,695 INFO L290 TraceCheckUtils]: 60: Hoare triple {11537#false} assume !(0 != activate_threads_~tmp___2~0#1); {11537#false} is VALID [2022-02-21 04:24:23,695 INFO L290 TraceCheckUtils]: 61: Hoare triple {11537#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {11537#false} is VALID [2022-02-21 04:24:23,695 INFO L290 TraceCheckUtils]: 62: Hoare triple {11537#false} assume !(1 == ~t4_pc~0); {11537#false} is VALID [2022-02-21 04:24:23,696 INFO L290 TraceCheckUtils]: 63: Hoare triple {11537#false} is_transmit4_triggered_~__retres1~4#1 := 0; {11537#false} is VALID [2022-02-21 04:24:23,696 INFO L290 TraceCheckUtils]: 64: Hoare triple {11537#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {11537#false} is VALID [2022-02-21 04:24:23,696 INFO L290 TraceCheckUtils]: 65: Hoare triple {11537#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {11537#false} is VALID [2022-02-21 04:24:23,696 INFO L290 TraceCheckUtils]: 66: Hoare triple {11537#false} assume !(0 != activate_threads_~tmp___3~0#1); {11537#false} is VALID [2022-02-21 04:24:23,696 INFO L290 TraceCheckUtils]: 67: Hoare triple {11537#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {11537#false} is VALID [2022-02-21 04:24:23,696 INFO L290 TraceCheckUtils]: 68: Hoare triple {11537#false} assume 1 == ~t5_pc~0; {11537#false} is VALID [2022-02-21 04:24:23,696 INFO L290 TraceCheckUtils]: 69: Hoare triple {11537#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {11537#false} is VALID [2022-02-21 04:24:23,696 INFO L290 TraceCheckUtils]: 70: Hoare triple {11537#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {11537#false} is VALID [2022-02-21 04:24:23,697 INFO L290 TraceCheckUtils]: 71: Hoare triple {11537#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {11537#false} is VALID [2022-02-21 04:24:23,697 INFO L290 TraceCheckUtils]: 72: Hoare triple {11537#false} assume !(0 != activate_threads_~tmp___4~0#1); {11537#false} is VALID [2022-02-21 04:24:23,697 INFO L290 TraceCheckUtils]: 73: Hoare triple {11537#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {11537#false} is VALID [2022-02-21 04:24:23,697 INFO L290 TraceCheckUtils]: 74: Hoare triple {11537#false} assume 1 == ~t6_pc~0; {11537#false} is VALID [2022-02-21 04:24:23,697 INFO L290 TraceCheckUtils]: 75: Hoare triple {11537#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {11537#false} is VALID [2022-02-21 04:24:23,697 INFO L290 TraceCheckUtils]: 76: Hoare triple {11537#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {11537#false} is VALID [2022-02-21 04:24:23,697 INFO L290 TraceCheckUtils]: 77: Hoare triple {11537#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {11537#false} is VALID [2022-02-21 04:24:23,697 INFO L290 TraceCheckUtils]: 78: Hoare triple {11537#false} assume !(0 != activate_threads_~tmp___5~0#1); {11537#false} is VALID [2022-02-21 04:24:23,697 INFO L290 TraceCheckUtils]: 79: Hoare triple {11537#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {11537#false} is VALID [2022-02-21 04:24:23,698 INFO L290 TraceCheckUtils]: 80: Hoare triple {11537#false} assume !(1 == ~t7_pc~0); {11537#false} is VALID [2022-02-21 04:24:23,698 INFO L290 TraceCheckUtils]: 81: Hoare triple {11537#false} is_transmit7_triggered_~__retres1~7#1 := 0; {11537#false} is VALID [2022-02-21 04:24:23,698 INFO L290 TraceCheckUtils]: 82: Hoare triple {11537#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {11537#false} is VALID [2022-02-21 04:24:23,698 INFO L290 TraceCheckUtils]: 83: Hoare triple {11537#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {11537#false} is VALID [2022-02-21 04:24:23,698 INFO L290 TraceCheckUtils]: 84: Hoare triple {11537#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {11537#false} is VALID [2022-02-21 04:24:23,698 INFO L290 TraceCheckUtils]: 85: Hoare triple {11537#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {11537#false} is VALID [2022-02-21 04:24:23,698 INFO L290 TraceCheckUtils]: 86: Hoare triple {11537#false} assume 1 == ~t8_pc~0; {11537#false} is VALID [2022-02-21 04:24:23,698 INFO L290 TraceCheckUtils]: 87: Hoare triple {11537#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {11537#false} is VALID [2022-02-21 04:24:23,699 INFO L290 TraceCheckUtils]: 88: Hoare triple {11537#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {11537#false} is VALID [2022-02-21 04:24:23,699 INFO L290 TraceCheckUtils]: 89: Hoare triple {11537#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {11537#false} is VALID [2022-02-21 04:24:23,699 INFO L290 TraceCheckUtils]: 90: Hoare triple {11537#false} assume !(0 != activate_threads_~tmp___7~0#1); {11537#false} is VALID [2022-02-21 04:24:23,699 INFO L290 TraceCheckUtils]: 91: Hoare triple {11537#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {11537#false} is VALID [2022-02-21 04:24:23,699 INFO L290 TraceCheckUtils]: 92: Hoare triple {11537#false} assume !(1 == ~t9_pc~0); {11537#false} is VALID [2022-02-21 04:24:23,699 INFO L290 TraceCheckUtils]: 93: Hoare triple {11537#false} is_transmit9_triggered_~__retres1~9#1 := 0; {11537#false} is VALID [2022-02-21 04:24:23,699 INFO L290 TraceCheckUtils]: 94: Hoare triple {11537#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {11537#false} is VALID [2022-02-21 04:24:23,699 INFO L290 TraceCheckUtils]: 95: Hoare triple {11537#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {11537#false} is VALID [2022-02-21 04:24:23,700 INFO L290 TraceCheckUtils]: 96: Hoare triple {11537#false} assume !(0 != activate_threads_~tmp___8~0#1); {11537#false} is VALID [2022-02-21 04:24:23,700 INFO L290 TraceCheckUtils]: 97: Hoare triple {11537#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {11537#false} is VALID [2022-02-21 04:24:23,700 INFO L290 TraceCheckUtils]: 98: Hoare triple {11537#false} assume 1 == ~t10_pc~0; {11537#false} is VALID [2022-02-21 04:24:23,700 INFO L290 TraceCheckUtils]: 99: Hoare triple {11537#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {11537#false} is VALID [2022-02-21 04:24:23,700 INFO L290 TraceCheckUtils]: 100: Hoare triple {11537#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {11537#false} is VALID [2022-02-21 04:24:23,700 INFO L290 TraceCheckUtils]: 101: Hoare triple {11537#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {11537#false} is VALID [2022-02-21 04:24:23,700 INFO L290 TraceCheckUtils]: 102: Hoare triple {11537#false} assume !(0 != activate_threads_~tmp___9~0#1); {11537#false} is VALID [2022-02-21 04:24:23,700 INFO L290 TraceCheckUtils]: 103: Hoare triple {11537#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {11537#false} is VALID [2022-02-21 04:24:23,700 INFO L290 TraceCheckUtils]: 104: Hoare triple {11537#false} assume !(1 == ~M_E~0); {11537#false} is VALID [2022-02-21 04:24:23,701 INFO L290 TraceCheckUtils]: 105: Hoare triple {11537#false} assume !(1 == ~T1_E~0); {11537#false} is VALID [2022-02-21 04:24:23,701 INFO L290 TraceCheckUtils]: 106: Hoare triple {11537#false} assume !(1 == ~T2_E~0); {11537#false} is VALID [2022-02-21 04:24:23,701 INFO L290 TraceCheckUtils]: 107: Hoare triple {11537#false} assume !(1 == ~T3_E~0); {11537#false} is VALID [2022-02-21 04:24:23,701 INFO L290 TraceCheckUtils]: 108: Hoare triple {11537#false} assume !(1 == ~T4_E~0); {11537#false} is VALID [2022-02-21 04:24:23,701 INFO L290 TraceCheckUtils]: 109: Hoare triple {11537#false} assume !(1 == ~T5_E~0); {11537#false} is VALID [2022-02-21 04:24:23,701 INFO L290 TraceCheckUtils]: 110: Hoare triple {11537#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {11537#false} is VALID [2022-02-21 04:24:23,701 INFO L290 TraceCheckUtils]: 111: Hoare triple {11537#false} assume !(1 == ~T7_E~0); {11537#false} is VALID [2022-02-21 04:24:23,701 INFO L290 TraceCheckUtils]: 112: Hoare triple {11537#false} assume !(1 == ~T8_E~0); {11537#false} is VALID [2022-02-21 04:24:23,701 INFO L290 TraceCheckUtils]: 113: Hoare triple {11537#false} assume !(1 == ~T9_E~0); {11537#false} is VALID [2022-02-21 04:24:23,702 INFO L290 TraceCheckUtils]: 114: Hoare triple {11537#false} assume !(1 == ~T10_E~0); {11537#false} is VALID [2022-02-21 04:24:23,702 INFO L290 TraceCheckUtils]: 115: Hoare triple {11537#false} assume !(1 == ~E_1~0); {11537#false} is VALID [2022-02-21 04:24:23,702 INFO L290 TraceCheckUtils]: 116: Hoare triple {11537#false} assume !(1 == ~E_2~0); {11537#false} is VALID [2022-02-21 04:24:23,702 INFO L290 TraceCheckUtils]: 117: Hoare triple {11537#false} assume !(1 == ~E_3~0); {11537#false} is VALID [2022-02-21 04:24:23,702 INFO L290 TraceCheckUtils]: 118: Hoare triple {11537#false} assume 1 == ~E_4~0;~E_4~0 := 2; {11537#false} is VALID [2022-02-21 04:24:23,702 INFO L290 TraceCheckUtils]: 119: Hoare triple {11537#false} assume !(1 == ~E_5~0); {11537#false} is VALID [2022-02-21 04:24:23,702 INFO L290 TraceCheckUtils]: 120: Hoare triple {11537#false} assume !(1 == ~E_6~0); {11537#false} is VALID [2022-02-21 04:24:23,702 INFO L290 TraceCheckUtils]: 121: Hoare triple {11537#false} assume !(1 == ~E_7~0); {11537#false} is VALID [2022-02-21 04:24:23,703 INFO L290 TraceCheckUtils]: 122: Hoare triple {11537#false} assume !(1 == ~E_8~0); {11537#false} is VALID [2022-02-21 04:24:23,703 INFO L290 TraceCheckUtils]: 123: Hoare triple {11537#false} assume !(1 == ~E_9~0); {11537#false} is VALID [2022-02-21 04:24:23,703 INFO L290 TraceCheckUtils]: 124: Hoare triple {11537#false} assume !(1 == ~E_10~0); {11537#false} is VALID [2022-02-21 04:24:23,703 INFO L290 TraceCheckUtils]: 125: Hoare triple {11537#false} assume { :end_inline_reset_delta_events } true; {11537#false} is VALID [2022-02-21 04:24:23,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:23,703 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:23,704 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207008617] [2022-02-21 04:24:23,704 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1207008617] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:23,704 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:23,704 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:23,704 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2125850427] [2022-02-21 04:24:23,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:23,705 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:23,705 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:23,705 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 2 times [2022-02-21 04:24:23,705 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:23,705 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1645745723] [2022-02-21 04:24:23,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:23,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:23,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:23,763 INFO L290 TraceCheckUtils]: 0: Hoare triple {11539#true} assume !false; {11539#true} is VALID [2022-02-21 04:24:23,763 INFO L290 TraceCheckUtils]: 1: Hoare triple {11539#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {11539#true} is VALID [2022-02-21 04:24:23,764 INFO L290 TraceCheckUtils]: 2: Hoare triple {11539#true} assume !false; {11539#true} is VALID [2022-02-21 04:24:23,764 INFO L290 TraceCheckUtils]: 3: Hoare triple {11539#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {11539#true} is VALID [2022-02-21 04:24:23,764 INFO L290 TraceCheckUtils]: 4: Hoare triple {11539#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {11539#true} is VALID [2022-02-21 04:24:23,764 INFO L290 TraceCheckUtils]: 5: Hoare triple {11539#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {11539#true} is VALID [2022-02-21 04:24:23,764 INFO L290 TraceCheckUtils]: 6: Hoare triple {11539#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {11539#true} is VALID [2022-02-21 04:24:23,764 INFO L290 TraceCheckUtils]: 7: Hoare triple {11539#true} assume !(0 != eval_~tmp~0#1); {11539#true} is VALID [2022-02-21 04:24:23,764 INFO L290 TraceCheckUtils]: 8: Hoare triple {11539#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {11539#true} is VALID [2022-02-21 04:24:23,764 INFO L290 TraceCheckUtils]: 9: Hoare triple {11539#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {11539#true} is VALID [2022-02-21 04:24:23,765 INFO L290 TraceCheckUtils]: 10: Hoare triple {11539#true} assume 0 == ~M_E~0;~M_E~0 := 1; {11539#true} is VALID [2022-02-21 04:24:23,765 INFO L290 TraceCheckUtils]: 11: Hoare triple {11539#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {11539#true} is VALID [2022-02-21 04:24:23,765 INFO L290 TraceCheckUtils]: 12: Hoare triple {11539#true} assume !(0 == ~T2_E~0); {11539#true} is VALID [2022-02-21 04:24:23,765 INFO L290 TraceCheckUtils]: 13: Hoare triple {11539#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {11539#true} is VALID [2022-02-21 04:24:23,765 INFO L290 TraceCheckUtils]: 14: Hoare triple {11539#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {11539#true} is VALID [2022-02-21 04:24:23,765 INFO L290 TraceCheckUtils]: 15: Hoare triple {11539#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,766 INFO L290 TraceCheckUtils]: 16: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,766 INFO L290 TraceCheckUtils]: 17: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,766 INFO L290 TraceCheckUtils]: 18: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,767 INFO L290 TraceCheckUtils]: 19: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,767 INFO L290 TraceCheckUtils]: 20: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,767 INFO L290 TraceCheckUtils]: 21: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,768 INFO L290 TraceCheckUtils]: 22: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,768 INFO L290 TraceCheckUtils]: 23: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,768 INFO L290 TraceCheckUtils]: 24: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,769 INFO L290 TraceCheckUtils]: 25: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,769 INFO L290 TraceCheckUtils]: 26: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,769 INFO L290 TraceCheckUtils]: 27: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,770 INFO L290 TraceCheckUtils]: 28: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,770 INFO L290 TraceCheckUtils]: 29: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,770 INFO L290 TraceCheckUtils]: 30: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,770 INFO L290 TraceCheckUtils]: 31: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,771 INFO L290 TraceCheckUtils]: 32: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,771 INFO L290 TraceCheckUtils]: 33: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,771 INFO L290 TraceCheckUtils]: 34: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,772 INFO L290 TraceCheckUtils]: 35: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,772 INFO L290 TraceCheckUtils]: 36: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,772 INFO L290 TraceCheckUtils]: 37: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,773 INFO L290 TraceCheckUtils]: 38: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,773 INFO L290 TraceCheckUtils]: 39: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,773 INFO L290 TraceCheckUtils]: 40: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,774 INFO L290 TraceCheckUtils]: 41: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,774 INFO L290 TraceCheckUtils]: 42: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,774 INFO L290 TraceCheckUtils]: 43: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,775 INFO L290 TraceCheckUtils]: 44: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,775 INFO L290 TraceCheckUtils]: 45: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,775 INFO L290 TraceCheckUtils]: 46: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,775 INFO L290 TraceCheckUtils]: 47: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,776 INFO L290 TraceCheckUtils]: 48: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,776 INFO L290 TraceCheckUtils]: 49: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,776 INFO L290 TraceCheckUtils]: 50: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,777 INFO L290 TraceCheckUtils]: 51: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,777 INFO L290 TraceCheckUtils]: 52: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,777 INFO L290 TraceCheckUtils]: 53: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,778 INFO L290 TraceCheckUtils]: 54: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,778 INFO L290 TraceCheckUtils]: 55: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,778 INFO L290 TraceCheckUtils]: 56: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,779 INFO L290 TraceCheckUtils]: 57: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,779 INFO L290 TraceCheckUtils]: 58: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,779 INFO L290 TraceCheckUtils]: 59: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,780 INFO L290 TraceCheckUtils]: 60: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,780 INFO L290 TraceCheckUtils]: 61: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,780 INFO L290 TraceCheckUtils]: 62: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,780 INFO L290 TraceCheckUtils]: 63: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,781 INFO L290 TraceCheckUtils]: 64: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,781 INFO L290 TraceCheckUtils]: 65: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,781 INFO L290 TraceCheckUtils]: 66: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,782 INFO L290 TraceCheckUtils]: 67: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,782 INFO L290 TraceCheckUtils]: 68: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,782 INFO L290 TraceCheckUtils]: 69: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,783 INFO L290 TraceCheckUtils]: 70: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,783 INFO L290 TraceCheckUtils]: 71: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,783 INFO L290 TraceCheckUtils]: 72: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,784 INFO L290 TraceCheckUtils]: 73: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,784 INFO L290 TraceCheckUtils]: 74: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,784 INFO L290 TraceCheckUtils]: 75: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,785 INFO L290 TraceCheckUtils]: 76: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,785 INFO L290 TraceCheckUtils]: 77: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,785 INFO L290 TraceCheckUtils]: 78: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,786 INFO L290 TraceCheckUtils]: 79: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,786 INFO L290 TraceCheckUtils]: 80: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,786 INFO L290 TraceCheckUtils]: 81: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,786 INFO L290 TraceCheckUtils]: 82: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,787 INFO L290 TraceCheckUtils]: 83: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,787 INFO L290 TraceCheckUtils]: 84: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,787 INFO L290 TraceCheckUtils]: 85: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,788 INFO L290 TraceCheckUtils]: 86: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,788 INFO L290 TraceCheckUtils]: 87: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,788 INFO L290 TraceCheckUtils]: 88: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,789 INFO L290 TraceCheckUtils]: 89: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,789 INFO L290 TraceCheckUtils]: 90: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,789 INFO L290 TraceCheckUtils]: 91: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,790 INFO L290 TraceCheckUtils]: 92: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,790 INFO L290 TraceCheckUtils]: 93: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,790 INFO L290 TraceCheckUtils]: 94: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,791 INFO L290 TraceCheckUtils]: 95: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,791 INFO L290 TraceCheckUtils]: 96: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,791 INFO L290 TraceCheckUtils]: 97: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,792 INFO L290 TraceCheckUtils]: 98: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,792 INFO L290 TraceCheckUtils]: 99: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,792 INFO L290 TraceCheckUtils]: 100: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,792 INFO L290 TraceCheckUtils]: 101: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,793 INFO L290 TraceCheckUtils]: 102: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {11541#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:23,793 INFO L290 TraceCheckUtils]: 103: Hoare triple {11541#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {11540#false} is VALID [2022-02-21 04:24:23,793 INFO L290 TraceCheckUtils]: 104: Hoare triple {11540#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,794 INFO L290 TraceCheckUtils]: 105: Hoare triple {11540#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,794 INFO L290 TraceCheckUtils]: 106: Hoare triple {11540#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,794 INFO L290 TraceCheckUtils]: 107: Hoare triple {11540#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,794 INFO L290 TraceCheckUtils]: 108: Hoare triple {11540#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,794 INFO L290 TraceCheckUtils]: 109: Hoare triple {11540#false} assume 1 == ~E_1~0;~E_1~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,794 INFO L290 TraceCheckUtils]: 110: Hoare triple {11540#false} assume 1 == ~E_2~0;~E_2~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,794 INFO L290 TraceCheckUtils]: 111: Hoare triple {11540#false} assume !(1 == ~E_3~0); {11540#false} is VALID [2022-02-21 04:24:23,795 INFO L290 TraceCheckUtils]: 112: Hoare triple {11540#false} assume 1 == ~E_4~0;~E_4~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,795 INFO L290 TraceCheckUtils]: 113: Hoare triple {11540#false} assume 1 == ~E_5~0;~E_5~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,795 INFO L290 TraceCheckUtils]: 114: Hoare triple {11540#false} assume 1 == ~E_6~0;~E_6~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,795 INFO L290 TraceCheckUtils]: 115: Hoare triple {11540#false} assume 1 == ~E_7~0;~E_7~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,795 INFO L290 TraceCheckUtils]: 116: Hoare triple {11540#false} assume 1 == ~E_8~0;~E_8~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,795 INFO L290 TraceCheckUtils]: 117: Hoare triple {11540#false} assume 1 == ~E_9~0;~E_9~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,795 INFO L290 TraceCheckUtils]: 118: Hoare triple {11540#false} assume 1 == ~E_10~0;~E_10~0 := 2; {11540#false} is VALID [2022-02-21 04:24:23,796 INFO L290 TraceCheckUtils]: 119: Hoare triple {11540#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {11540#false} is VALID [2022-02-21 04:24:23,796 INFO L290 TraceCheckUtils]: 120: Hoare triple {11540#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {11540#false} is VALID [2022-02-21 04:24:23,796 INFO L290 TraceCheckUtils]: 121: Hoare triple {11540#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {11540#false} is VALID [2022-02-21 04:24:23,796 INFO L290 TraceCheckUtils]: 122: Hoare triple {11540#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {11540#false} is VALID [2022-02-21 04:24:23,796 INFO L290 TraceCheckUtils]: 123: Hoare triple {11540#false} assume !(0 == start_simulation_~tmp~3#1); {11540#false} is VALID [2022-02-21 04:24:23,796 INFO L290 TraceCheckUtils]: 124: Hoare triple {11540#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {11540#false} is VALID [2022-02-21 04:24:23,796 INFO L290 TraceCheckUtils]: 125: Hoare triple {11540#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {11540#false} is VALID [2022-02-21 04:24:23,797 INFO L290 TraceCheckUtils]: 126: Hoare triple {11540#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {11540#false} is VALID [2022-02-21 04:24:23,797 INFO L290 TraceCheckUtils]: 127: Hoare triple {11540#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {11540#false} is VALID [2022-02-21 04:24:23,797 INFO L290 TraceCheckUtils]: 128: Hoare triple {11540#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {11540#false} is VALID [2022-02-21 04:24:23,797 INFO L290 TraceCheckUtils]: 129: Hoare triple {11540#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {11540#false} is VALID [2022-02-21 04:24:23,797 INFO L290 TraceCheckUtils]: 130: Hoare triple {11540#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {11540#false} is VALID [2022-02-21 04:24:23,797 INFO L290 TraceCheckUtils]: 131: Hoare triple {11540#false} assume !(0 != start_simulation_~tmp___0~1#1); {11540#false} is VALID [2022-02-21 04:24:23,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:23,798 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:23,798 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1645745723] [2022-02-21 04:24:23,798 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1645745723] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:23,798 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:23,798 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:23,799 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927202969] [2022-02-21 04:24:23,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:23,799 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:23,799 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:23,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:23,800 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:23,800 INFO L87 Difference]: Start difference. First operand 1278 states and 1900 transitions. cyclomatic complexity: 623 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,720 INFO L93 Difference]: Finished difference Result 1278 states and 1899 transitions. [2022-02-21 04:24:24,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:24,721 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,793 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:24,794 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1899 transitions. [2022-02-21 04:24:24,837 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:24,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1899 transitions. [2022-02-21 04:24:24,877 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-02-21 04:24:24,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-02-21 04:24:24,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1899 transitions. [2022-02-21 04:24:24,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:24,879 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2022-02-21 04:24:24,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1899 transitions. [2022-02-21 04:24:24,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-02-21 04:24:24,891 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:24,893 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1278 states and 1899 transitions. Second operand has 1278 states, 1278 states have (on average 1.4859154929577465) internal successors, (1899), 1277 states have internal predecessors, (1899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,895 INFO L74 IsIncluded]: Start isIncluded. First operand 1278 states and 1899 transitions. Second operand has 1278 states, 1278 states have (on average 1.4859154929577465) internal successors, (1899), 1277 states have internal predecessors, (1899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,897 INFO L87 Difference]: Start difference. First operand 1278 states and 1899 transitions. Second operand has 1278 states, 1278 states have (on average 1.4859154929577465) internal successors, (1899), 1277 states have internal predecessors, (1899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,949 INFO L93 Difference]: Finished difference Result 1278 states and 1899 transitions. [2022-02-21 04:24:24,949 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1899 transitions. [2022-02-21 04:24:24,952 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:24,952 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:24,957 INFO L74 IsIncluded]: Start isIncluded. First operand has 1278 states, 1278 states have (on average 1.4859154929577465) internal successors, (1899), 1277 states have internal predecessors, (1899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1899 transitions. [2022-02-21 04:24:24,960 INFO L87 Difference]: Start difference. First operand has 1278 states, 1278 states have (on average 1.4859154929577465) internal successors, (1899), 1277 states have internal predecessors, (1899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1899 transitions. [2022-02-21 04:24:25,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:25,000 INFO L93 Difference]: Finished difference Result 1278 states and 1899 transitions. [2022-02-21 04:24:25,001 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1899 transitions. [2022-02-21 04:24:25,002 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:25,002 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:25,002 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:25,003 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:25,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4859154929577465) internal successors, (1899), 1277 states have internal predecessors, (1899), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1899 transitions. [2022-02-21 04:24:25,052 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2022-02-21 04:24:25,052 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1899 transitions. [2022-02-21 04:24:25,052 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:25,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1899 transitions. [2022-02-21 04:24:25,056 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:25,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:25,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:25,058 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:25,058 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:25,058 INFO L791 eck$LassoCheckResult]: Stem: 13802#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 13803#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14077#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14065#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14066#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 14086#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14087#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13370#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13088#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13089#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13995#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13996#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13981#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13982#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14017#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13142#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13143#L1006 assume !(0 == ~M_E~0); 12991#L1006-2 assume !(0 == ~T1_E~0); 12992#L1011-1 assume !(0 == ~T2_E~0); 14039#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14054#L1021-1 assume !(0 == ~T4_E~0); 12873#L1026-1 assume !(0 == ~T5_E~0); 12874#L1031-1 assume !(0 == ~T6_E~0); 13747#L1036-1 assume !(0 == ~T7_E~0); 13743#L1041-1 assume !(0 == ~T8_E~0); 13744#L1046-1 assume !(0 == ~T9_E~0); 13173#L1051-1 assume !(0 == ~T10_E~0); 13174#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 13876#L1061-1 assume !(0 == ~E_2~0); 13092#L1066-1 assume !(0 == ~E_3~0); 13093#L1071-1 assume !(0 == ~E_4~0); 13855#L1076-1 assume !(0 == ~E_5~0); 13002#L1081-1 assume !(0 == ~E_6~0); 13003#L1086-1 assume !(0 == ~E_7~0); 13345#L1091-1 assume !(0 == ~E_8~0); 14032#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 14033#L1101-1 assume !(0 == ~E_10~0); 13407#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13408#L484 assume !(1 == ~m_pc~0); 13051#L484-2 is_master_triggered_~__retres1~0#1 := 0; 13050#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13666#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13950#L1245 assume !(0 != activate_threads_~tmp~1#1); 13951#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13735#L503 assume 1 == ~t1_pc~0; 13736#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13753#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13868#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13521#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 12901#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12902#L522 assume !(1 == ~t2_pc~0); 13702#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13105#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13106#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13576#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 13997#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14062#L541 assume 1 == ~t3_pc~0; 13651#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13467#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13282#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13283#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 13705#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13706#L560 assume !(1 == ~t4_pc~0); 12985#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12984#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13610#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12869#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 12870#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13156#L579 assume 1 == ~t5_pc~0; 12820#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12821#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12929#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13613#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 14053#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14074#L598 assume 1 == ~t6_pc~0; 13250#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13251#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13553#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13973#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 13784#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13726#L617 assume !(1 == ~t7_pc~0); 13223#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13222#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13508#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13509#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13444#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13445#L636 assume 1 == ~t8_pc~0; 13607#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13608#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13409#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13410#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 13560#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13561#L655 assume !(1 == ~t9_pc~0); 13590#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13591#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13202#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13203#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 13804#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13805#L674 assume 1 == ~t10_pc~0; 12978#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12979#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14064#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14095#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 13550#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13551#L1119 assume !(1 == ~M_E~0); 13074#L1119-2 assume !(1 == ~T1_E~0); 13075#L1124-1 assume !(1 == ~T2_E~0); 12893#L1129-1 assume !(1 == ~T3_E~0); 12894#L1134-1 assume !(1 == ~T4_E~0); 13207#L1139-1 assume !(1 == ~T5_E~0); 13208#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13440#L1149-1 assume !(1 == ~T7_E~0); 13069#L1154-1 assume !(1 == ~T8_E~0); 13070#L1159-1 assume !(1 == ~T9_E~0); 13157#L1164-1 assume !(1 == ~T10_E~0); 13579#L1169-1 assume !(1 == ~E_1~0); 13477#L1174-1 assume !(1 == ~E_2~0); 13264#L1179-1 assume !(1 == ~E_3~0); 13146#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 13147#L1189-1 assume !(1 == ~E_5~0); 13200#L1194-1 assume !(1 == ~E_6~0); 13323#L1199-1 assume !(1 == ~E_7~0); 13274#L1204-1 assume !(1 == ~E_8~0); 13275#L1209-1 assume !(1 == ~E_9~0); 13798#L1214-1 assume !(1 == ~E_10~0); 13799#L1219-1 assume { :end_inline_reset_delta_events } true; 12857#L1520-2 [2022-02-21 04:24:25,059 INFO L793 eck$LassoCheckResult]: Loop: 12857#L1520-2 assume !false; 12858#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12961#L981 assume !false; 13153#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13825#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12843#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13943#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13993#L836 assume !(0 != eval_~tmp~0#1); 13435#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13436#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13431#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13432#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13902#L1011-3 assume !(0 == ~T2_E~0); 13903#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13942#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13625#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13626#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13870#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13871#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13933#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13934#L1051-3 assume !(0 == ~T10_E~0); 13872#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13170#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13171#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13172#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14043#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12955#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12956#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13010#L1091-3 assume !(0 == ~E_8~0); 13011#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14018#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14019#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13645#L484-33 assume 1 == ~m_pc~0; 13646#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13565#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13566#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12863#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12864#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13335#L503-33 assume !(1 == ~t1_pc~0); 13336#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 13786#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13715#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13242#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13243#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13682#L522-33 assume 1 == ~t2_pc~0; 13683#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12998#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12999#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13792#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13700#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13701#L541-33 assume 1 == ~t3_pc~0; 13022#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12861#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12862#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13672#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13673#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13867#L560-33 assume 1 == ~t4_pc~0; 13572#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12933#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12934#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13190#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 13849#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12849#L579-33 assume 1 == ~t5_pc~0; 12850#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13098#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14058#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13727#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13728#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13752#L598-33 assume !(1 == ~t6_pc~0); 13525#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 13356#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13357#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13197#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13198#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14007#L617-33 assume 1 == ~t7_pc~0; 14013#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12990#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13941#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14048#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14044#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12921#L636-33 assume !(1 == ~t8_pc~0); 12922#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 13841#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13842#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14067#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13830#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13831#L655-33 assume 1 == ~t9_pc~0; 14091#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13297#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13298#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13656#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13920#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13476#L674-33 assume 1 == ~t10_pc~0; 13351#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13352#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13213#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13214#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13691#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14068#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14075#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14078#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14089#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13235#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13236#L1139-3 assume !(1 == ~T5_E~0); 13469#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13470#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13612#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13882#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13883#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14049#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13354#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13355#L1179-3 assume !(1 == ~E_3~0); 13974#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12981#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12982#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13295#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13296#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13599#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12875#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12876#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13789#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12958#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13312#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 13313#L1539 assume !(0 == start_simulation_~tmp~3#1); 13405#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13581#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13388#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13520#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 13304#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13305#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13909#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 13406#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 12857#L1520-2 [2022-02-21 04:24:25,059 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:25,059 INFO L85 PathProgramCache]: Analyzing trace with hash 1440481707, now seen corresponding path program 1 times [2022-02-21 04:24:25,060 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:25,060 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70597690] [2022-02-21 04:24:25,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:25,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:25,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:25,087 INFO L290 TraceCheckUtils]: 0: Hoare triple {16657#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {16657#true} is VALID [2022-02-21 04:24:25,088 INFO L290 TraceCheckUtils]: 1: Hoare triple {16657#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {16659#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:25,089 INFO L290 TraceCheckUtils]: 2: Hoare triple {16659#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {16659#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:25,089 INFO L290 TraceCheckUtils]: 3: Hoare triple {16659#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {16659#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:25,089 INFO L290 TraceCheckUtils]: 4: Hoare triple {16659#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {16659#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:25,090 INFO L290 TraceCheckUtils]: 5: Hoare triple {16659#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {16659#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:25,090 INFO L290 TraceCheckUtils]: 6: Hoare triple {16659#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {16659#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:25,090 INFO L290 TraceCheckUtils]: 7: Hoare triple {16659#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {16659#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:25,090 INFO L290 TraceCheckUtils]: 8: Hoare triple {16659#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {16658#false} is VALID [2022-02-21 04:24:25,090 INFO L290 TraceCheckUtils]: 9: Hoare triple {16658#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {16658#false} is VALID [2022-02-21 04:24:25,091 INFO L290 TraceCheckUtils]: 10: Hoare triple {16658#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {16658#false} is VALID [2022-02-21 04:24:25,091 INFO L290 TraceCheckUtils]: 11: Hoare triple {16658#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {16658#false} is VALID [2022-02-21 04:24:25,091 INFO L290 TraceCheckUtils]: 12: Hoare triple {16658#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {16658#false} is VALID [2022-02-21 04:24:25,091 INFO L290 TraceCheckUtils]: 13: Hoare triple {16658#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {16658#false} is VALID [2022-02-21 04:24:25,091 INFO L290 TraceCheckUtils]: 14: Hoare triple {16658#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {16658#false} is VALID [2022-02-21 04:24:25,091 INFO L290 TraceCheckUtils]: 15: Hoare triple {16658#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {16658#false} is VALID [2022-02-21 04:24:25,091 INFO L290 TraceCheckUtils]: 16: Hoare triple {16658#false} assume !(0 == ~M_E~0); {16658#false} is VALID [2022-02-21 04:24:25,091 INFO L290 TraceCheckUtils]: 17: Hoare triple {16658#false} assume !(0 == ~T1_E~0); {16658#false} is VALID [2022-02-21 04:24:25,092 INFO L290 TraceCheckUtils]: 18: Hoare triple {16658#false} assume !(0 == ~T2_E~0); {16658#false} is VALID [2022-02-21 04:24:25,092 INFO L290 TraceCheckUtils]: 19: Hoare triple {16658#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {16658#false} is VALID [2022-02-21 04:24:25,092 INFO L290 TraceCheckUtils]: 20: Hoare triple {16658#false} assume !(0 == ~T4_E~0); {16658#false} is VALID [2022-02-21 04:24:25,092 INFO L290 TraceCheckUtils]: 21: Hoare triple {16658#false} assume !(0 == ~T5_E~0); {16658#false} is VALID [2022-02-21 04:24:25,092 INFO L290 TraceCheckUtils]: 22: Hoare triple {16658#false} assume !(0 == ~T6_E~0); {16658#false} is VALID [2022-02-21 04:24:25,092 INFO L290 TraceCheckUtils]: 23: Hoare triple {16658#false} assume !(0 == ~T7_E~0); {16658#false} is VALID [2022-02-21 04:24:25,092 INFO L290 TraceCheckUtils]: 24: Hoare triple {16658#false} assume !(0 == ~T8_E~0); {16658#false} is VALID [2022-02-21 04:24:25,092 INFO L290 TraceCheckUtils]: 25: Hoare triple {16658#false} assume !(0 == ~T9_E~0); {16658#false} is VALID [2022-02-21 04:24:25,093 INFO L290 TraceCheckUtils]: 26: Hoare triple {16658#false} assume !(0 == ~T10_E~0); {16658#false} is VALID [2022-02-21 04:24:25,093 INFO L290 TraceCheckUtils]: 27: Hoare triple {16658#false} assume 0 == ~E_1~0;~E_1~0 := 1; {16658#false} is VALID [2022-02-21 04:24:25,093 INFO L290 TraceCheckUtils]: 28: Hoare triple {16658#false} assume !(0 == ~E_2~0); {16658#false} is VALID [2022-02-21 04:24:25,093 INFO L290 TraceCheckUtils]: 29: Hoare triple {16658#false} assume !(0 == ~E_3~0); {16658#false} is VALID [2022-02-21 04:24:25,093 INFO L290 TraceCheckUtils]: 30: Hoare triple {16658#false} assume !(0 == ~E_4~0); {16658#false} is VALID [2022-02-21 04:24:25,093 INFO L290 TraceCheckUtils]: 31: Hoare triple {16658#false} assume !(0 == ~E_5~0); {16658#false} is VALID [2022-02-21 04:24:25,093 INFO L290 TraceCheckUtils]: 32: Hoare triple {16658#false} assume !(0 == ~E_6~0); {16658#false} is VALID [2022-02-21 04:24:25,093 INFO L290 TraceCheckUtils]: 33: Hoare triple {16658#false} assume !(0 == ~E_7~0); {16658#false} is VALID [2022-02-21 04:24:25,093 INFO L290 TraceCheckUtils]: 34: Hoare triple {16658#false} assume !(0 == ~E_8~0); {16658#false} is VALID [2022-02-21 04:24:25,094 INFO L290 TraceCheckUtils]: 35: Hoare triple {16658#false} assume 0 == ~E_9~0;~E_9~0 := 1; {16658#false} is VALID [2022-02-21 04:24:25,094 INFO L290 TraceCheckUtils]: 36: Hoare triple {16658#false} assume !(0 == ~E_10~0); {16658#false} is VALID [2022-02-21 04:24:25,094 INFO L290 TraceCheckUtils]: 37: Hoare triple {16658#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16658#false} is VALID [2022-02-21 04:24:25,094 INFO L290 TraceCheckUtils]: 38: Hoare triple {16658#false} assume !(1 == ~m_pc~0); {16658#false} is VALID [2022-02-21 04:24:25,094 INFO L290 TraceCheckUtils]: 39: Hoare triple {16658#false} is_master_triggered_~__retres1~0#1 := 0; {16658#false} is VALID [2022-02-21 04:24:25,094 INFO L290 TraceCheckUtils]: 40: Hoare triple {16658#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16658#false} is VALID [2022-02-21 04:24:25,094 INFO L290 TraceCheckUtils]: 41: Hoare triple {16658#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {16658#false} is VALID [2022-02-21 04:24:25,094 INFO L290 TraceCheckUtils]: 42: Hoare triple {16658#false} assume !(0 != activate_threads_~tmp~1#1); {16658#false} is VALID [2022-02-21 04:24:25,095 INFO L290 TraceCheckUtils]: 43: Hoare triple {16658#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16658#false} is VALID [2022-02-21 04:24:25,095 INFO L290 TraceCheckUtils]: 44: Hoare triple {16658#false} assume 1 == ~t1_pc~0; {16658#false} is VALID [2022-02-21 04:24:25,095 INFO L290 TraceCheckUtils]: 45: Hoare triple {16658#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {16658#false} is VALID [2022-02-21 04:24:25,095 INFO L290 TraceCheckUtils]: 46: Hoare triple {16658#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16658#false} is VALID [2022-02-21 04:24:25,095 INFO L290 TraceCheckUtils]: 47: Hoare triple {16658#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {16658#false} is VALID [2022-02-21 04:24:25,095 INFO L290 TraceCheckUtils]: 48: Hoare triple {16658#false} assume !(0 != activate_threads_~tmp___0~0#1); {16658#false} is VALID [2022-02-21 04:24:25,102 INFO L290 TraceCheckUtils]: 49: Hoare triple {16658#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16658#false} is VALID [2022-02-21 04:24:25,102 INFO L290 TraceCheckUtils]: 50: Hoare triple {16658#false} assume !(1 == ~t2_pc~0); {16658#false} is VALID [2022-02-21 04:24:25,102 INFO L290 TraceCheckUtils]: 51: Hoare triple {16658#false} is_transmit2_triggered_~__retres1~2#1 := 0; {16658#false} is VALID [2022-02-21 04:24:25,102 INFO L290 TraceCheckUtils]: 52: Hoare triple {16658#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16658#false} is VALID [2022-02-21 04:24:25,102 INFO L290 TraceCheckUtils]: 53: Hoare triple {16658#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {16658#false} is VALID [2022-02-21 04:24:25,102 INFO L290 TraceCheckUtils]: 54: Hoare triple {16658#false} assume !(0 != activate_threads_~tmp___1~0#1); {16658#false} is VALID [2022-02-21 04:24:25,102 INFO L290 TraceCheckUtils]: 55: Hoare triple {16658#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16658#false} is VALID [2022-02-21 04:24:25,103 INFO L290 TraceCheckUtils]: 56: Hoare triple {16658#false} assume 1 == ~t3_pc~0; {16658#false} is VALID [2022-02-21 04:24:25,103 INFO L290 TraceCheckUtils]: 57: Hoare triple {16658#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {16658#false} is VALID [2022-02-21 04:24:25,103 INFO L290 TraceCheckUtils]: 58: Hoare triple {16658#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16658#false} is VALID [2022-02-21 04:24:25,103 INFO L290 TraceCheckUtils]: 59: Hoare triple {16658#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {16658#false} is VALID [2022-02-21 04:24:25,103 INFO L290 TraceCheckUtils]: 60: Hoare triple {16658#false} assume !(0 != activate_threads_~tmp___2~0#1); {16658#false} is VALID [2022-02-21 04:24:25,103 INFO L290 TraceCheckUtils]: 61: Hoare triple {16658#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16658#false} is VALID [2022-02-21 04:24:25,103 INFO L290 TraceCheckUtils]: 62: Hoare triple {16658#false} assume !(1 == ~t4_pc~0); {16658#false} is VALID [2022-02-21 04:24:25,103 INFO L290 TraceCheckUtils]: 63: Hoare triple {16658#false} is_transmit4_triggered_~__retres1~4#1 := 0; {16658#false} is VALID [2022-02-21 04:24:25,104 INFO L290 TraceCheckUtils]: 64: Hoare triple {16658#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16658#false} is VALID [2022-02-21 04:24:25,104 INFO L290 TraceCheckUtils]: 65: Hoare triple {16658#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {16658#false} is VALID [2022-02-21 04:24:25,104 INFO L290 TraceCheckUtils]: 66: Hoare triple {16658#false} assume !(0 != activate_threads_~tmp___3~0#1); {16658#false} is VALID [2022-02-21 04:24:25,104 INFO L290 TraceCheckUtils]: 67: Hoare triple {16658#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {16658#false} is VALID [2022-02-21 04:24:25,104 INFO L290 TraceCheckUtils]: 68: Hoare triple {16658#false} assume 1 == ~t5_pc~0; {16658#false} is VALID [2022-02-21 04:24:25,104 INFO L290 TraceCheckUtils]: 69: Hoare triple {16658#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {16658#false} is VALID [2022-02-21 04:24:25,104 INFO L290 TraceCheckUtils]: 70: Hoare triple {16658#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {16658#false} is VALID [2022-02-21 04:24:25,104 INFO L290 TraceCheckUtils]: 71: Hoare triple {16658#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {16658#false} is VALID [2022-02-21 04:24:25,105 INFO L290 TraceCheckUtils]: 72: Hoare triple {16658#false} assume !(0 != activate_threads_~tmp___4~0#1); {16658#false} is VALID [2022-02-21 04:24:25,105 INFO L290 TraceCheckUtils]: 73: Hoare triple {16658#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {16658#false} is VALID [2022-02-21 04:24:25,105 INFO L290 TraceCheckUtils]: 74: Hoare triple {16658#false} assume 1 == ~t6_pc~0; {16658#false} is VALID [2022-02-21 04:24:25,105 INFO L290 TraceCheckUtils]: 75: Hoare triple {16658#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {16658#false} is VALID [2022-02-21 04:24:25,105 INFO L290 TraceCheckUtils]: 76: Hoare triple {16658#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {16658#false} is VALID [2022-02-21 04:24:25,105 INFO L290 TraceCheckUtils]: 77: Hoare triple {16658#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {16658#false} is VALID [2022-02-21 04:24:25,105 INFO L290 TraceCheckUtils]: 78: Hoare triple {16658#false} assume !(0 != activate_threads_~tmp___5~0#1); {16658#false} is VALID [2022-02-21 04:24:25,105 INFO L290 TraceCheckUtils]: 79: Hoare triple {16658#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {16658#false} is VALID [2022-02-21 04:24:25,105 INFO L290 TraceCheckUtils]: 80: Hoare triple {16658#false} assume !(1 == ~t7_pc~0); {16658#false} is VALID [2022-02-21 04:24:25,106 INFO L290 TraceCheckUtils]: 81: Hoare triple {16658#false} is_transmit7_triggered_~__retres1~7#1 := 0; {16658#false} is VALID [2022-02-21 04:24:25,106 INFO L290 TraceCheckUtils]: 82: Hoare triple {16658#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {16658#false} is VALID [2022-02-21 04:24:25,106 INFO L290 TraceCheckUtils]: 83: Hoare triple {16658#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {16658#false} is VALID [2022-02-21 04:24:25,106 INFO L290 TraceCheckUtils]: 84: Hoare triple {16658#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {16658#false} is VALID [2022-02-21 04:24:25,106 INFO L290 TraceCheckUtils]: 85: Hoare triple {16658#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {16658#false} is VALID [2022-02-21 04:24:25,106 INFO L290 TraceCheckUtils]: 86: Hoare triple {16658#false} assume 1 == ~t8_pc~0; {16658#false} is VALID [2022-02-21 04:24:25,106 INFO L290 TraceCheckUtils]: 87: Hoare triple {16658#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {16658#false} is VALID [2022-02-21 04:24:25,106 INFO L290 TraceCheckUtils]: 88: Hoare triple {16658#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {16658#false} is VALID [2022-02-21 04:24:25,107 INFO L290 TraceCheckUtils]: 89: Hoare triple {16658#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {16658#false} is VALID [2022-02-21 04:24:25,107 INFO L290 TraceCheckUtils]: 90: Hoare triple {16658#false} assume !(0 != activate_threads_~tmp___7~0#1); {16658#false} is VALID [2022-02-21 04:24:25,107 INFO L290 TraceCheckUtils]: 91: Hoare triple {16658#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {16658#false} is VALID [2022-02-21 04:24:25,107 INFO L290 TraceCheckUtils]: 92: Hoare triple {16658#false} assume !(1 == ~t9_pc~0); {16658#false} is VALID [2022-02-21 04:24:25,107 INFO L290 TraceCheckUtils]: 93: Hoare triple {16658#false} is_transmit9_triggered_~__retres1~9#1 := 0; {16658#false} is VALID [2022-02-21 04:24:25,107 INFO L290 TraceCheckUtils]: 94: Hoare triple {16658#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {16658#false} is VALID [2022-02-21 04:24:25,107 INFO L290 TraceCheckUtils]: 95: Hoare triple {16658#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {16658#false} is VALID [2022-02-21 04:24:25,108 INFO L290 TraceCheckUtils]: 96: Hoare triple {16658#false} assume !(0 != activate_threads_~tmp___8~0#1); {16658#false} is VALID [2022-02-21 04:24:25,108 INFO L290 TraceCheckUtils]: 97: Hoare triple {16658#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {16658#false} is VALID [2022-02-21 04:24:25,108 INFO L290 TraceCheckUtils]: 98: Hoare triple {16658#false} assume 1 == ~t10_pc~0; {16658#false} is VALID [2022-02-21 04:24:25,108 INFO L290 TraceCheckUtils]: 99: Hoare triple {16658#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {16658#false} is VALID [2022-02-21 04:24:25,108 INFO L290 TraceCheckUtils]: 100: Hoare triple {16658#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {16658#false} is VALID [2022-02-21 04:24:25,108 INFO L290 TraceCheckUtils]: 101: Hoare triple {16658#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {16658#false} is VALID [2022-02-21 04:24:25,108 INFO L290 TraceCheckUtils]: 102: Hoare triple {16658#false} assume !(0 != activate_threads_~tmp___9~0#1); {16658#false} is VALID [2022-02-21 04:24:25,109 INFO L290 TraceCheckUtils]: 103: Hoare triple {16658#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16658#false} is VALID [2022-02-21 04:24:25,109 INFO L290 TraceCheckUtils]: 104: Hoare triple {16658#false} assume !(1 == ~M_E~0); {16658#false} is VALID [2022-02-21 04:24:25,109 INFO L290 TraceCheckUtils]: 105: Hoare triple {16658#false} assume !(1 == ~T1_E~0); {16658#false} is VALID [2022-02-21 04:24:25,109 INFO L290 TraceCheckUtils]: 106: Hoare triple {16658#false} assume !(1 == ~T2_E~0); {16658#false} is VALID [2022-02-21 04:24:25,109 INFO L290 TraceCheckUtils]: 107: Hoare triple {16658#false} assume !(1 == ~T3_E~0); {16658#false} is VALID [2022-02-21 04:24:25,109 INFO L290 TraceCheckUtils]: 108: Hoare triple {16658#false} assume !(1 == ~T4_E~0); {16658#false} is VALID [2022-02-21 04:24:25,109 INFO L290 TraceCheckUtils]: 109: Hoare triple {16658#false} assume !(1 == ~T5_E~0); {16658#false} is VALID [2022-02-21 04:24:25,110 INFO L290 TraceCheckUtils]: 110: Hoare triple {16658#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {16658#false} is VALID [2022-02-21 04:24:25,110 INFO L290 TraceCheckUtils]: 111: Hoare triple {16658#false} assume !(1 == ~T7_E~0); {16658#false} is VALID [2022-02-21 04:24:25,110 INFO L290 TraceCheckUtils]: 112: Hoare triple {16658#false} assume !(1 == ~T8_E~0); {16658#false} is VALID [2022-02-21 04:24:25,110 INFO L290 TraceCheckUtils]: 113: Hoare triple {16658#false} assume !(1 == ~T9_E~0); {16658#false} is VALID [2022-02-21 04:24:25,110 INFO L290 TraceCheckUtils]: 114: Hoare triple {16658#false} assume !(1 == ~T10_E~0); {16658#false} is VALID [2022-02-21 04:24:25,110 INFO L290 TraceCheckUtils]: 115: Hoare triple {16658#false} assume !(1 == ~E_1~0); {16658#false} is VALID [2022-02-21 04:24:25,111 INFO L290 TraceCheckUtils]: 116: Hoare triple {16658#false} assume !(1 == ~E_2~0); {16658#false} is VALID [2022-02-21 04:24:25,111 INFO L290 TraceCheckUtils]: 117: Hoare triple {16658#false} assume !(1 == ~E_3~0); {16658#false} is VALID [2022-02-21 04:24:25,111 INFO L290 TraceCheckUtils]: 118: Hoare triple {16658#false} assume 1 == ~E_4~0;~E_4~0 := 2; {16658#false} is VALID [2022-02-21 04:24:25,111 INFO L290 TraceCheckUtils]: 119: Hoare triple {16658#false} assume !(1 == ~E_5~0); {16658#false} is VALID [2022-02-21 04:24:25,111 INFO L290 TraceCheckUtils]: 120: Hoare triple {16658#false} assume !(1 == ~E_6~0); {16658#false} is VALID [2022-02-21 04:24:25,111 INFO L290 TraceCheckUtils]: 121: Hoare triple {16658#false} assume !(1 == ~E_7~0); {16658#false} is VALID [2022-02-21 04:24:25,111 INFO L290 TraceCheckUtils]: 122: Hoare triple {16658#false} assume !(1 == ~E_8~0); {16658#false} is VALID [2022-02-21 04:24:25,112 INFO L290 TraceCheckUtils]: 123: Hoare triple {16658#false} assume !(1 == ~E_9~0); {16658#false} is VALID [2022-02-21 04:24:25,112 INFO L290 TraceCheckUtils]: 124: Hoare triple {16658#false} assume !(1 == ~E_10~0); {16658#false} is VALID [2022-02-21 04:24:25,112 INFO L290 TraceCheckUtils]: 125: Hoare triple {16658#false} assume { :end_inline_reset_delta_events } true; {16658#false} is VALID [2022-02-21 04:24:25,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:25,112 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:25,113 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [70597690] [2022-02-21 04:24:25,114 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [70597690] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:25,114 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:25,114 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:25,114 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205729140] [2022-02-21 04:24:25,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:25,115 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:25,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:25,116 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 3 times [2022-02-21 04:24:25,116 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:25,118 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852830428] [2022-02-21 04:24:25,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:25,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:25,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:25,184 INFO L290 TraceCheckUtils]: 0: Hoare triple {16660#true} assume !false; {16660#true} is VALID [2022-02-21 04:24:25,184 INFO L290 TraceCheckUtils]: 1: Hoare triple {16660#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {16660#true} is VALID [2022-02-21 04:24:25,184 INFO L290 TraceCheckUtils]: 2: Hoare triple {16660#true} assume !false; {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 3: Hoare triple {16660#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 4: Hoare triple {16660#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 5: Hoare triple {16660#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 6: Hoare triple {16660#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 7: Hoare triple {16660#true} assume !(0 != eval_~tmp~0#1); {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 8: Hoare triple {16660#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 9: Hoare triple {16660#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 10: Hoare triple {16660#true} assume 0 == ~M_E~0;~M_E~0 := 1; {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 11: Hoare triple {16660#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 12: Hoare triple {16660#true} assume !(0 == ~T2_E~0); {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 13: Hoare triple {16660#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 14: Hoare triple {16660#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {16660#true} is VALID [2022-02-21 04:24:25,185 INFO L290 TraceCheckUtils]: 15: Hoare triple {16660#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,186 INFO L290 TraceCheckUtils]: 16: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,186 INFO L290 TraceCheckUtils]: 17: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,186 INFO L290 TraceCheckUtils]: 18: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,187 INFO L290 TraceCheckUtils]: 19: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,188 INFO L290 TraceCheckUtils]: 20: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,188 INFO L290 TraceCheckUtils]: 21: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,188 INFO L290 TraceCheckUtils]: 22: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,189 INFO L290 TraceCheckUtils]: 23: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,190 INFO L290 TraceCheckUtils]: 24: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,191 INFO L290 TraceCheckUtils]: 25: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,191 INFO L290 TraceCheckUtils]: 26: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,191 INFO L290 TraceCheckUtils]: 27: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,192 INFO L290 TraceCheckUtils]: 28: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,192 INFO L290 TraceCheckUtils]: 29: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,192 INFO L290 TraceCheckUtils]: 30: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,193 INFO L290 TraceCheckUtils]: 31: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,193 INFO L290 TraceCheckUtils]: 32: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,194 INFO L290 TraceCheckUtils]: 33: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,194 INFO L290 TraceCheckUtils]: 34: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,194 INFO L290 TraceCheckUtils]: 35: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,195 INFO L290 TraceCheckUtils]: 36: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,195 INFO L290 TraceCheckUtils]: 37: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,196 INFO L290 TraceCheckUtils]: 38: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,196 INFO L290 TraceCheckUtils]: 39: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,196 INFO L290 TraceCheckUtils]: 40: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,197 INFO L290 TraceCheckUtils]: 41: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,197 INFO L290 TraceCheckUtils]: 42: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,197 INFO L290 TraceCheckUtils]: 43: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,198 INFO L290 TraceCheckUtils]: 44: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,198 INFO L290 TraceCheckUtils]: 45: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,198 INFO L290 TraceCheckUtils]: 46: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,199 INFO L290 TraceCheckUtils]: 47: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,199 INFO L290 TraceCheckUtils]: 48: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,199 INFO L290 TraceCheckUtils]: 49: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,200 INFO L290 TraceCheckUtils]: 50: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,205 INFO L290 TraceCheckUtils]: 51: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 52: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 53: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,206 INFO L290 TraceCheckUtils]: 54: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 55: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 56: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,207 INFO L290 TraceCheckUtils]: 57: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 58: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 59: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,208 INFO L290 TraceCheckUtils]: 60: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 61: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 62: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,209 INFO L290 TraceCheckUtils]: 63: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 64: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 65: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,210 INFO L290 TraceCheckUtils]: 66: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 67: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 68: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,211 INFO L290 TraceCheckUtils]: 69: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 70: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 71: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 72: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,212 INFO L290 TraceCheckUtils]: 73: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,213 INFO L290 TraceCheckUtils]: 74: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,213 INFO L290 TraceCheckUtils]: 75: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,213 INFO L290 TraceCheckUtils]: 76: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,214 INFO L290 TraceCheckUtils]: 77: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,214 INFO L290 TraceCheckUtils]: 78: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,214 INFO L290 TraceCheckUtils]: 79: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,215 INFO L290 TraceCheckUtils]: 80: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,215 INFO L290 TraceCheckUtils]: 81: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,227 INFO L290 TraceCheckUtils]: 82: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,227 INFO L290 TraceCheckUtils]: 83: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,228 INFO L290 TraceCheckUtils]: 84: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,228 INFO L290 TraceCheckUtils]: 85: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,228 INFO L290 TraceCheckUtils]: 86: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,229 INFO L290 TraceCheckUtils]: 87: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,229 INFO L290 TraceCheckUtils]: 88: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,229 INFO L290 TraceCheckUtils]: 89: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,230 INFO L290 TraceCheckUtils]: 90: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,230 INFO L290 TraceCheckUtils]: 91: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,230 INFO L290 TraceCheckUtils]: 92: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,231 INFO L290 TraceCheckUtils]: 93: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,231 INFO L290 TraceCheckUtils]: 94: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,231 INFO L290 TraceCheckUtils]: 95: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,232 INFO L290 TraceCheckUtils]: 96: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,232 INFO L290 TraceCheckUtils]: 97: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,233 INFO L290 TraceCheckUtils]: 98: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,233 INFO L290 TraceCheckUtils]: 99: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,233 INFO L290 TraceCheckUtils]: 100: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,234 INFO L290 TraceCheckUtils]: 101: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,234 INFO L290 TraceCheckUtils]: 102: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {16662#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:25,234 INFO L290 TraceCheckUtils]: 103: Hoare triple {16662#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {16661#false} is VALID [2022-02-21 04:24:25,234 INFO L290 TraceCheckUtils]: 104: Hoare triple {16661#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,234 INFO L290 TraceCheckUtils]: 105: Hoare triple {16661#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,234 INFO L290 TraceCheckUtils]: 106: Hoare triple {16661#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 107: Hoare triple {16661#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 108: Hoare triple {16661#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 109: Hoare triple {16661#false} assume 1 == ~E_1~0;~E_1~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 110: Hoare triple {16661#false} assume 1 == ~E_2~0;~E_2~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 111: Hoare triple {16661#false} assume !(1 == ~E_3~0); {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 112: Hoare triple {16661#false} assume 1 == ~E_4~0;~E_4~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 113: Hoare triple {16661#false} assume 1 == ~E_5~0;~E_5~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 114: Hoare triple {16661#false} assume 1 == ~E_6~0;~E_6~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 115: Hoare triple {16661#false} assume 1 == ~E_7~0;~E_7~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 116: Hoare triple {16661#false} assume 1 == ~E_8~0;~E_8~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 117: Hoare triple {16661#false} assume 1 == ~E_9~0;~E_9~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 118: Hoare triple {16661#false} assume 1 == ~E_10~0;~E_10~0 := 2; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 119: Hoare triple {16661#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 120: Hoare triple {16661#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 121: Hoare triple {16661#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 122: Hoare triple {16661#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {16661#false} is VALID [2022-02-21 04:24:25,235 INFO L290 TraceCheckUtils]: 123: Hoare triple {16661#false} assume !(0 == start_simulation_~tmp~3#1); {16661#false} is VALID [2022-02-21 04:24:25,236 INFO L290 TraceCheckUtils]: 124: Hoare triple {16661#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {16661#false} is VALID [2022-02-21 04:24:25,236 INFO L290 TraceCheckUtils]: 125: Hoare triple {16661#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {16661#false} is VALID [2022-02-21 04:24:25,236 INFO L290 TraceCheckUtils]: 126: Hoare triple {16661#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {16661#false} is VALID [2022-02-21 04:24:25,236 INFO L290 TraceCheckUtils]: 127: Hoare triple {16661#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {16661#false} is VALID [2022-02-21 04:24:25,236 INFO L290 TraceCheckUtils]: 128: Hoare triple {16661#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {16661#false} is VALID [2022-02-21 04:24:25,236 INFO L290 TraceCheckUtils]: 129: Hoare triple {16661#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {16661#false} is VALID [2022-02-21 04:24:25,236 INFO L290 TraceCheckUtils]: 130: Hoare triple {16661#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {16661#false} is VALID [2022-02-21 04:24:25,236 INFO L290 TraceCheckUtils]: 131: Hoare triple {16661#false} assume !(0 != start_simulation_~tmp___0~1#1); {16661#false} is VALID [2022-02-21 04:24:25,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:25,237 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:25,237 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852830428] [2022-02-21 04:24:25,237 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852830428] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:25,237 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:25,237 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:25,237 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [153460273] [2022-02-21 04:24:25,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:25,238 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:25,238 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:25,238 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:25,238 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:25,239 INFO L87 Difference]: Start difference. First operand 1278 states and 1899 transitions. cyclomatic complexity: 622 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,293 INFO L93 Difference]: Finished difference Result 1278 states and 1898 transitions. [2022-02-21 04:24:26,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:26,293 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,362 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:26,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1898 transitions. [2022-02-21 04:24:26,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:26,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1898 transitions. [2022-02-21 04:24:26,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-02-21 04:24:26,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-02-21 04:24:26,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1898 transitions. [2022-02-21 04:24:26,440 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:26,440 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2022-02-21 04:24:26,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1898 transitions. [2022-02-21 04:24:26,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-02-21 04:24:26,449 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:26,451 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1278 states and 1898 transitions. Second operand has 1278 states, 1278 states have (on average 1.4851330203442878) internal successors, (1898), 1277 states have internal predecessors, (1898), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,452 INFO L74 IsIncluded]: Start isIncluded. First operand 1278 states and 1898 transitions. Second operand has 1278 states, 1278 states have (on average 1.4851330203442878) internal successors, (1898), 1277 states have internal predecessors, (1898), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,454 INFO L87 Difference]: Start difference. First operand 1278 states and 1898 transitions. Second operand has 1278 states, 1278 states have (on average 1.4851330203442878) internal successors, (1898), 1277 states have internal predecessors, (1898), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,489 INFO L93 Difference]: Finished difference Result 1278 states and 1898 transitions. [2022-02-21 04:24:26,489 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1898 transitions. [2022-02-21 04:24:26,491 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:26,491 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:26,493 INFO L74 IsIncluded]: Start isIncluded. First operand has 1278 states, 1278 states have (on average 1.4851330203442878) internal successors, (1898), 1277 states have internal predecessors, (1898), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1898 transitions. [2022-02-21 04:24:26,494 INFO L87 Difference]: Start difference. First operand has 1278 states, 1278 states have (on average 1.4851330203442878) internal successors, (1898), 1277 states have internal predecessors, (1898), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1898 transitions. [2022-02-21 04:24:26,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,529 INFO L93 Difference]: Finished difference Result 1278 states and 1898 transitions. [2022-02-21 04:24:26,529 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1898 transitions. [2022-02-21 04:24:26,531 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:26,531 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:26,531 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:26,531 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:26,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4851330203442878) internal successors, (1898), 1277 states have internal predecessors, (1898), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1898 transitions. [2022-02-21 04:24:26,568 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2022-02-21 04:24:26,568 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1898 transitions. [2022-02-21 04:24:26,568 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:26,569 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1898 transitions. [2022-02-21 04:24:26,572 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:26,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:26,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:26,573 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:26,573 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:26,574 INFO L791 eck$LassoCheckResult]: Stem: 18922#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 18923#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 19198#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19186#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19187#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 19207#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19208#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18491#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18209#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18210#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 19116#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19117#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19102#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19103#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19138#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18261#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18262#L1006 assume !(0 == ~M_E~0); 18112#L1006-2 assume !(0 == ~T1_E~0); 18113#L1011-1 assume !(0 == ~T2_E~0); 19160#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19175#L1021-1 assume !(0 == ~T4_E~0); 17992#L1026-1 assume !(0 == ~T5_E~0); 17993#L1031-1 assume !(0 == ~T6_E~0); 18868#L1036-1 assume !(0 == ~T7_E~0); 18864#L1041-1 assume !(0 == ~T8_E~0); 18865#L1046-1 assume !(0 == ~T9_E~0); 18294#L1051-1 assume !(0 == ~T10_E~0); 18295#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 18997#L1061-1 assume !(0 == ~E_2~0); 18213#L1066-1 assume !(0 == ~E_3~0); 18214#L1071-1 assume !(0 == ~E_4~0); 18976#L1076-1 assume !(0 == ~E_5~0); 18123#L1081-1 assume !(0 == ~E_6~0); 18124#L1086-1 assume !(0 == ~E_7~0); 18466#L1091-1 assume !(0 == ~E_8~0); 19152#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 19153#L1101-1 assume !(0 == ~E_10~0); 18528#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18529#L484 assume !(1 == ~m_pc~0); 18172#L484-2 is_master_triggered_~__retres1~0#1 := 0; 18171#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18787#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19071#L1245 assume !(0 != activate_threads_~tmp~1#1); 19072#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18856#L503 assume 1 == ~t1_pc~0; 18857#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18873#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18989#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18639#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 18022#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18023#L522 assume !(1 == ~t2_pc~0); 18823#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18226#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18227#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18697#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 19118#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19183#L541 assume 1 == ~t3_pc~0; 18772#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18588#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18403#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18404#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 18826#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18827#L560 assume !(1 == ~t4_pc~0); 18104#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18103#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18731#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17990#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 17991#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18275#L579 assume 1 == ~t5_pc~0; 17941#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17942#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18050#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18734#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 19173#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19195#L598 assume 1 == ~t6_pc~0; 18371#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18372#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18673#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19094#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 18905#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18847#L617 assume !(1 == ~t7_pc~0); 18344#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18343#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18629#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18630#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18565#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18566#L636 assume 1 == ~t8_pc~0; 18728#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18729#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18530#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18531#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 18681#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18682#L655 assume !(1 == ~t9_pc~0); 18709#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18710#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18323#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18324#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 18924#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18925#L674 assume 1 == ~t10_pc~0; 18099#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18100#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19185#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19216#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 18671#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18672#L1119 assume !(1 == ~M_E~0); 18195#L1119-2 assume !(1 == ~T1_E~0); 18196#L1124-1 assume !(1 == ~T2_E~0); 18014#L1129-1 assume !(1 == ~T3_E~0); 18015#L1134-1 assume !(1 == ~T4_E~0); 18325#L1139-1 assume !(1 == ~T5_E~0); 18326#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18561#L1149-1 assume !(1 == ~T7_E~0); 18190#L1154-1 assume !(1 == ~T8_E~0); 18191#L1159-1 assume !(1 == ~T9_E~0); 18278#L1164-1 assume !(1 == ~T10_E~0); 18700#L1169-1 assume !(1 == ~E_1~0); 18598#L1174-1 assume !(1 == ~E_2~0); 18385#L1179-1 assume !(1 == ~E_3~0); 18267#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18268#L1189-1 assume !(1 == ~E_5~0); 18320#L1194-1 assume !(1 == ~E_6~0); 18444#L1199-1 assume !(1 == ~E_7~0); 18395#L1204-1 assume !(1 == ~E_8~0); 18396#L1209-1 assume !(1 == ~E_9~0); 18919#L1214-1 assume !(1 == ~E_10~0); 18920#L1219-1 assume { :end_inline_reset_delta_events } true; 17978#L1520-2 [2022-02-21 04:24:26,574 INFO L793 eck$LassoCheckResult]: Loop: 17978#L1520-2 assume !false; 17979#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18079#L981 assume !false; 18271#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18946#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 17964#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19064#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19114#L836 assume !(0 != eval_~tmp~0#1); 18556#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18557#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18552#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18553#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19023#L1011-3 assume !(0 == ~T2_E~0); 19024#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19063#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18744#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18745#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18991#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18992#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19052#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19053#L1051-3 assume !(0 == ~T10_E~0); 18993#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18289#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18290#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18293#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19164#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18076#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18077#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18129#L1091-3 assume !(0 == ~E_8~0); 18130#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19139#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19140#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18766#L484-33 assume !(1 == ~m_pc~0); 18768#L484-35 is_master_triggered_~__retres1~0#1 := 0; 18686#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18687#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17984#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17985#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18453#L503-33 assume !(1 == ~t1_pc~0); 18454#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 18907#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18834#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18363#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18364#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18803#L522-33 assume 1 == ~t2_pc~0; 18804#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18117#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18118#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18912#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18821#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18822#L541-33 assume !(1 == ~t3_pc~0); 18144#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 17982#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17983#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18793#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18794#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18988#L560-33 assume 1 == ~t4_pc~0; 18693#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18054#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18055#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18313#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 18970#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17973#L579-33 assume 1 == ~t5_pc~0; 17974#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18220#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19179#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18848#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18849#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18877#L598-33 assume !(1 == ~t6_pc~0); 18651#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 18477#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18478#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18318#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18319#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19128#L617-33 assume 1 == ~t7_pc~0; 19134#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18111#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19062#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19169#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19165#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18042#L636-33 assume !(1 == ~t8_pc~0); 18043#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 18962#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18963#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19188#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18953#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18954#L655-33 assume 1 == ~t9_pc~0; 19212#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18420#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18421#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18777#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19041#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18597#L674-33 assume 1 == ~t10_pc~0; 18472#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18473#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18334#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18335#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18812#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19189#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19196#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19200#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19210#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18359#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18360#L1139-3 assume !(1 == ~T5_E~0); 18590#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18591#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18733#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19003#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19004#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19171#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18475#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18476#L1179-3 assume !(1 == ~E_3~0); 19095#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18105#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18106#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18416#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18417#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18720#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17996#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17997#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18911#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18082#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18433#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 18434#L1539 assume !(0 == start_simulation_~tmp~3#1); 18526#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18702#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18509#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18642#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 18425#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18426#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19030#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 18527#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 17978#L1520-2 [2022-02-21 04:24:26,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:26,575 INFO L85 PathProgramCache]: Analyzing trace with hash -1012009875, now seen corresponding path program 1 times [2022-02-21 04:24:26,575 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:26,576 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220452864] [2022-02-21 04:24:26,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:26,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:26,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:26,602 INFO L290 TraceCheckUtils]: 0: Hoare triple {21778#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {21778#true} is VALID [2022-02-21 04:24:26,602 INFO L290 TraceCheckUtils]: 1: Hoare triple {21778#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {21780#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:26,602 INFO L290 TraceCheckUtils]: 2: Hoare triple {21780#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {21780#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:26,603 INFO L290 TraceCheckUtils]: 3: Hoare triple {21780#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {21780#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:26,603 INFO L290 TraceCheckUtils]: 4: Hoare triple {21780#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {21780#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:26,603 INFO L290 TraceCheckUtils]: 5: Hoare triple {21780#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {21780#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:26,604 INFO L290 TraceCheckUtils]: 6: Hoare triple {21780#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {21780#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:26,604 INFO L290 TraceCheckUtils]: 7: Hoare triple {21780#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {21780#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:26,604 INFO L290 TraceCheckUtils]: 8: Hoare triple {21780#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {21780#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:26,604 INFO L290 TraceCheckUtils]: 9: Hoare triple {21780#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {21779#false} is VALID [2022-02-21 04:24:26,604 INFO L290 TraceCheckUtils]: 10: Hoare triple {21779#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {21779#false} is VALID [2022-02-21 04:24:26,605 INFO L290 TraceCheckUtils]: 11: Hoare triple {21779#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {21779#false} is VALID [2022-02-21 04:24:26,605 INFO L290 TraceCheckUtils]: 12: Hoare triple {21779#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {21779#false} is VALID [2022-02-21 04:24:26,605 INFO L290 TraceCheckUtils]: 13: Hoare triple {21779#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {21779#false} is VALID [2022-02-21 04:24:26,605 INFO L290 TraceCheckUtils]: 14: Hoare triple {21779#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {21779#false} is VALID [2022-02-21 04:24:26,605 INFO L290 TraceCheckUtils]: 15: Hoare triple {21779#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {21779#false} is VALID [2022-02-21 04:24:26,605 INFO L290 TraceCheckUtils]: 16: Hoare triple {21779#false} assume !(0 == ~M_E~0); {21779#false} is VALID [2022-02-21 04:24:26,605 INFO L290 TraceCheckUtils]: 17: Hoare triple {21779#false} assume !(0 == ~T1_E~0); {21779#false} is VALID [2022-02-21 04:24:26,605 INFO L290 TraceCheckUtils]: 18: Hoare triple {21779#false} assume !(0 == ~T2_E~0); {21779#false} is VALID [2022-02-21 04:24:26,606 INFO L290 TraceCheckUtils]: 19: Hoare triple {21779#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {21779#false} is VALID [2022-02-21 04:24:26,606 INFO L290 TraceCheckUtils]: 20: Hoare triple {21779#false} assume !(0 == ~T4_E~0); {21779#false} is VALID [2022-02-21 04:24:26,606 INFO L290 TraceCheckUtils]: 21: Hoare triple {21779#false} assume !(0 == ~T5_E~0); {21779#false} is VALID [2022-02-21 04:24:26,606 INFO L290 TraceCheckUtils]: 22: Hoare triple {21779#false} assume !(0 == ~T6_E~0); {21779#false} is VALID [2022-02-21 04:24:26,606 INFO L290 TraceCheckUtils]: 23: Hoare triple {21779#false} assume !(0 == ~T7_E~0); {21779#false} is VALID [2022-02-21 04:24:26,606 INFO L290 TraceCheckUtils]: 24: Hoare triple {21779#false} assume !(0 == ~T8_E~0); {21779#false} is VALID [2022-02-21 04:24:26,606 INFO L290 TraceCheckUtils]: 25: Hoare triple {21779#false} assume !(0 == ~T9_E~0); {21779#false} is VALID [2022-02-21 04:24:26,606 INFO L290 TraceCheckUtils]: 26: Hoare triple {21779#false} assume !(0 == ~T10_E~0); {21779#false} is VALID [2022-02-21 04:24:26,606 INFO L290 TraceCheckUtils]: 27: Hoare triple {21779#false} assume 0 == ~E_1~0;~E_1~0 := 1; {21779#false} is VALID [2022-02-21 04:24:26,607 INFO L290 TraceCheckUtils]: 28: Hoare triple {21779#false} assume !(0 == ~E_2~0); {21779#false} is VALID [2022-02-21 04:24:26,607 INFO L290 TraceCheckUtils]: 29: Hoare triple {21779#false} assume !(0 == ~E_3~0); {21779#false} is VALID [2022-02-21 04:24:26,607 INFO L290 TraceCheckUtils]: 30: Hoare triple {21779#false} assume !(0 == ~E_4~0); {21779#false} is VALID [2022-02-21 04:24:26,607 INFO L290 TraceCheckUtils]: 31: Hoare triple {21779#false} assume !(0 == ~E_5~0); {21779#false} is VALID [2022-02-21 04:24:26,607 INFO L290 TraceCheckUtils]: 32: Hoare triple {21779#false} assume !(0 == ~E_6~0); {21779#false} is VALID [2022-02-21 04:24:26,607 INFO L290 TraceCheckUtils]: 33: Hoare triple {21779#false} assume !(0 == ~E_7~0); {21779#false} is VALID [2022-02-21 04:24:26,607 INFO L290 TraceCheckUtils]: 34: Hoare triple {21779#false} assume !(0 == ~E_8~0); {21779#false} is VALID [2022-02-21 04:24:26,607 INFO L290 TraceCheckUtils]: 35: Hoare triple {21779#false} assume 0 == ~E_9~0;~E_9~0 := 1; {21779#false} is VALID [2022-02-21 04:24:26,607 INFO L290 TraceCheckUtils]: 36: Hoare triple {21779#false} assume !(0 == ~E_10~0); {21779#false} is VALID [2022-02-21 04:24:26,608 INFO L290 TraceCheckUtils]: 37: Hoare triple {21779#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {21779#false} is VALID [2022-02-21 04:24:26,608 INFO L290 TraceCheckUtils]: 38: Hoare triple {21779#false} assume !(1 == ~m_pc~0); {21779#false} is VALID [2022-02-21 04:24:26,608 INFO L290 TraceCheckUtils]: 39: Hoare triple {21779#false} is_master_triggered_~__retres1~0#1 := 0; {21779#false} is VALID [2022-02-21 04:24:26,608 INFO L290 TraceCheckUtils]: 40: Hoare triple {21779#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {21779#false} is VALID [2022-02-21 04:24:26,608 INFO L290 TraceCheckUtils]: 41: Hoare triple {21779#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {21779#false} is VALID [2022-02-21 04:24:26,608 INFO L290 TraceCheckUtils]: 42: Hoare triple {21779#false} assume !(0 != activate_threads_~tmp~1#1); {21779#false} is VALID [2022-02-21 04:24:26,608 INFO L290 TraceCheckUtils]: 43: Hoare triple {21779#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {21779#false} is VALID [2022-02-21 04:24:26,608 INFO L290 TraceCheckUtils]: 44: Hoare triple {21779#false} assume 1 == ~t1_pc~0; {21779#false} is VALID [2022-02-21 04:24:26,609 INFO L290 TraceCheckUtils]: 45: Hoare triple {21779#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {21779#false} is VALID [2022-02-21 04:24:26,609 INFO L290 TraceCheckUtils]: 46: Hoare triple {21779#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {21779#false} is VALID [2022-02-21 04:24:26,609 INFO L290 TraceCheckUtils]: 47: Hoare triple {21779#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {21779#false} is VALID [2022-02-21 04:24:26,609 INFO L290 TraceCheckUtils]: 48: Hoare triple {21779#false} assume !(0 != activate_threads_~tmp___0~0#1); {21779#false} is VALID [2022-02-21 04:24:26,609 INFO L290 TraceCheckUtils]: 49: Hoare triple {21779#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {21779#false} is VALID [2022-02-21 04:24:26,609 INFO L290 TraceCheckUtils]: 50: Hoare triple {21779#false} assume !(1 == ~t2_pc~0); {21779#false} is VALID [2022-02-21 04:24:26,609 INFO L290 TraceCheckUtils]: 51: Hoare triple {21779#false} is_transmit2_triggered_~__retres1~2#1 := 0; {21779#false} is VALID [2022-02-21 04:24:26,609 INFO L290 TraceCheckUtils]: 52: Hoare triple {21779#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {21779#false} is VALID [2022-02-21 04:24:26,609 INFO L290 TraceCheckUtils]: 53: Hoare triple {21779#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {21779#false} is VALID [2022-02-21 04:24:26,610 INFO L290 TraceCheckUtils]: 54: Hoare triple {21779#false} assume !(0 != activate_threads_~tmp___1~0#1); {21779#false} is VALID [2022-02-21 04:24:26,610 INFO L290 TraceCheckUtils]: 55: Hoare triple {21779#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {21779#false} is VALID [2022-02-21 04:24:26,610 INFO L290 TraceCheckUtils]: 56: Hoare triple {21779#false} assume 1 == ~t3_pc~0; {21779#false} is VALID [2022-02-21 04:24:26,610 INFO L290 TraceCheckUtils]: 57: Hoare triple {21779#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {21779#false} is VALID [2022-02-21 04:24:26,610 INFO L290 TraceCheckUtils]: 58: Hoare triple {21779#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {21779#false} is VALID [2022-02-21 04:24:26,610 INFO L290 TraceCheckUtils]: 59: Hoare triple {21779#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {21779#false} is VALID [2022-02-21 04:24:26,610 INFO L290 TraceCheckUtils]: 60: Hoare triple {21779#false} assume !(0 != activate_threads_~tmp___2~0#1); {21779#false} is VALID [2022-02-21 04:24:26,610 INFO L290 TraceCheckUtils]: 61: Hoare triple {21779#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {21779#false} is VALID [2022-02-21 04:24:26,610 INFO L290 TraceCheckUtils]: 62: Hoare triple {21779#false} assume !(1 == ~t4_pc~0); {21779#false} is VALID [2022-02-21 04:24:26,611 INFO L290 TraceCheckUtils]: 63: Hoare triple {21779#false} is_transmit4_triggered_~__retres1~4#1 := 0; {21779#false} is VALID [2022-02-21 04:24:26,611 INFO L290 TraceCheckUtils]: 64: Hoare triple {21779#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {21779#false} is VALID [2022-02-21 04:24:26,611 INFO L290 TraceCheckUtils]: 65: Hoare triple {21779#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {21779#false} is VALID [2022-02-21 04:24:26,611 INFO L290 TraceCheckUtils]: 66: Hoare triple {21779#false} assume !(0 != activate_threads_~tmp___3~0#1); {21779#false} is VALID [2022-02-21 04:24:26,611 INFO L290 TraceCheckUtils]: 67: Hoare triple {21779#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {21779#false} is VALID [2022-02-21 04:24:26,611 INFO L290 TraceCheckUtils]: 68: Hoare triple {21779#false} assume 1 == ~t5_pc~0; {21779#false} is VALID [2022-02-21 04:24:26,611 INFO L290 TraceCheckUtils]: 69: Hoare triple {21779#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {21779#false} is VALID [2022-02-21 04:24:26,611 INFO L290 TraceCheckUtils]: 70: Hoare triple {21779#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {21779#false} is VALID [2022-02-21 04:24:26,611 INFO L290 TraceCheckUtils]: 71: Hoare triple {21779#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {21779#false} is VALID [2022-02-21 04:24:26,612 INFO L290 TraceCheckUtils]: 72: Hoare triple {21779#false} assume !(0 != activate_threads_~tmp___4~0#1); {21779#false} is VALID [2022-02-21 04:24:26,612 INFO L290 TraceCheckUtils]: 73: Hoare triple {21779#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {21779#false} is VALID [2022-02-21 04:24:26,612 INFO L290 TraceCheckUtils]: 74: Hoare triple {21779#false} assume 1 == ~t6_pc~0; {21779#false} is VALID [2022-02-21 04:24:26,612 INFO L290 TraceCheckUtils]: 75: Hoare triple {21779#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {21779#false} is VALID [2022-02-21 04:24:26,612 INFO L290 TraceCheckUtils]: 76: Hoare triple {21779#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {21779#false} is VALID [2022-02-21 04:24:26,612 INFO L290 TraceCheckUtils]: 77: Hoare triple {21779#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {21779#false} is VALID [2022-02-21 04:24:26,612 INFO L290 TraceCheckUtils]: 78: Hoare triple {21779#false} assume !(0 != activate_threads_~tmp___5~0#1); {21779#false} is VALID [2022-02-21 04:24:26,612 INFO L290 TraceCheckUtils]: 79: Hoare triple {21779#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {21779#false} is VALID [2022-02-21 04:24:26,613 INFO L290 TraceCheckUtils]: 80: Hoare triple {21779#false} assume !(1 == ~t7_pc~0); {21779#false} is VALID [2022-02-21 04:24:26,613 INFO L290 TraceCheckUtils]: 81: Hoare triple {21779#false} is_transmit7_triggered_~__retres1~7#1 := 0; {21779#false} is VALID [2022-02-21 04:24:26,613 INFO L290 TraceCheckUtils]: 82: Hoare triple {21779#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {21779#false} is VALID [2022-02-21 04:24:26,613 INFO L290 TraceCheckUtils]: 83: Hoare triple {21779#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {21779#false} is VALID [2022-02-21 04:24:26,613 INFO L290 TraceCheckUtils]: 84: Hoare triple {21779#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {21779#false} is VALID [2022-02-21 04:24:26,613 INFO L290 TraceCheckUtils]: 85: Hoare triple {21779#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {21779#false} is VALID [2022-02-21 04:24:26,613 INFO L290 TraceCheckUtils]: 86: Hoare triple {21779#false} assume 1 == ~t8_pc~0; {21779#false} is VALID [2022-02-21 04:24:26,613 INFO L290 TraceCheckUtils]: 87: Hoare triple {21779#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {21779#false} is VALID [2022-02-21 04:24:26,613 INFO L290 TraceCheckUtils]: 88: Hoare triple {21779#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {21779#false} is VALID [2022-02-21 04:24:26,614 INFO L290 TraceCheckUtils]: 89: Hoare triple {21779#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {21779#false} is VALID [2022-02-21 04:24:26,614 INFO L290 TraceCheckUtils]: 90: Hoare triple {21779#false} assume !(0 != activate_threads_~tmp___7~0#1); {21779#false} is VALID [2022-02-21 04:24:26,614 INFO L290 TraceCheckUtils]: 91: Hoare triple {21779#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {21779#false} is VALID [2022-02-21 04:24:26,614 INFO L290 TraceCheckUtils]: 92: Hoare triple {21779#false} assume !(1 == ~t9_pc~0); {21779#false} is VALID [2022-02-21 04:24:26,614 INFO L290 TraceCheckUtils]: 93: Hoare triple {21779#false} is_transmit9_triggered_~__retres1~9#1 := 0; {21779#false} is VALID [2022-02-21 04:24:26,614 INFO L290 TraceCheckUtils]: 94: Hoare triple {21779#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {21779#false} is VALID [2022-02-21 04:24:26,614 INFO L290 TraceCheckUtils]: 95: Hoare triple {21779#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {21779#false} is VALID [2022-02-21 04:24:26,614 INFO L290 TraceCheckUtils]: 96: Hoare triple {21779#false} assume !(0 != activate_threads_~tmp___8~0#1); {21779#false} is VALID [2022-02-21 04:24:26,614 INFO L290 TraceCheckUtils]: 97: Hoare triple {21779#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {21779#false} is VALID [2022-02-21 04:24:26,615 INFO L290 TraceCheckUtils]: 98: Hoare triple {21779#false} assume 1 == ~t10_pc~0; {21779#false} is VALID [2022-02-21 04:24:26,615 INFO L290 TraceCheckUtils]: 99: Hoare triple {21779#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {21779#false} is VALID [2022-02-21 04:24:26,615 INFO L290 TraceCheckUtils]: 100: Hoare triple {21779#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {21779#false} is VALID [2022-02-21 04:24:26,615 INFO L290 TraceCheckUtils]: 101: Hoare triple {21779#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {21779#false} is VALID [2022-02-21 04:24:26,615 INFO L290 TraceCheckUtils]: 102: Hoare triple {21779#false} assume !(0 != activate_threads_~tmp___9~0#1); {21779#false} is VALID [2022-02-21 04:24:26,615 INFO L290 TraceCheckUtils]: 103: Hoare triple {21779#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {21779#false} is VALID [2022-02-21 04:24:26,615 INFO L290 TraceCheckUtils]: 104: Hoare triple {21779#false} assume !(1 == ~M_E~0); {21779#false} is VALID [2022-02-21 04:24:26,615 INFO L290 TraceCheckUtils]: 105: Hoare triple {21779#false} assume !(1 == ~T1_E~0); {21779#false} is VALID [2022-02-21 04:24:26,616 INFO L290 TraceCheckUtils]: 106: Hoare triple {21779#false} assume !(1 == ~T2_E~0); {21779#false} is VALID [2022-02-21 04:24:26,616 INFO L290 TraceCheckUtils]: 107: Hoare triple {21779#false} assume !(1 == ~T3_E~0); {21779#false} is VALID [2022-02-21 04:24:26,616 INFO L290 TraceCheckUtils]: 108: Hoare triple {21779#false} assume !(1 == ~T4_E~0); {21779#false} is VALID [2022-02-21 04:24:26,616 INFO L290 TraceCheckUtils]: 109: Hoare triple {21779#false} assume !(1 == ~T5_E~0); {21779#false} is VALID [2022-02-21 04:24:26,616 INFO L290 TraceCheckUtils]: 110: Hoare triple {21779#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {21779#false} is VALID [2022-02-21 04:24:26,616 INFO L290 TraceCheckUtils]: 111: Hoare triple {21779#false} assume !(1 == ~T7_E~0); {21779#false} is VALID [2022-02-21 04:24:26,616 INFO L290 TraceCheckUtils]: 112: Hoare triple {21779#false} assume !(1 == ~T8_E~0); {21779#false} is VALID [2022-02-21 04:24:26,616 INFO L290 TraceCheckUtils]: 113: Hoare triple {21779#false} assume !(1 == ~T9_E~0); {21779#false} is VALID [2022-02-21 04:24:26,616 INFO L290 TraceCheckUtils]: 114: Hoare triple {21779#false} assume !(1 == ~T10_E~0); {21779#false} is VALID [2022-02-21 04:24:26,617 INFO L290 TraceCheckUtils]: 115: Hoare triple {21779#false} assume !(1 == ~E_1~0); {21779#false} is VALID [2022-02-21 04:24:26,617 INFO L290 TraceCheckUtils]: 116: Hoare triple {21779#false} assume !(1 == ~E_2~0); {21779#false} is VALID [2022-02-21 04:24:26,617 INFO L290 TraceCheckUtils]: 117: Hoare triple {21779#false} assume !(1 == ~E_3~0); {21779#false} is VALID [2022-02-21 04:24:26,617 INFO L290 TraceCheckUtils]: 118: Hoare triple {21779#false} assume 1 == ~E_4~0;~E_4~0 := 2; {21779#false} is VALID [2022-02-21 04:24:26,617 INFO L290 TraceCheckUtils]: 119: Hoare triple {21779#false} assume !(1 == ~E_5~0); {21779#false} is VALID [2022-02-21 04:24:26,617 INFO L290 TraceCheckUtils]: 120: Hoare triple {21779#false} assume !(1 == ~E_6~0); {21779#false} is VALID [2022-02-21 04:24:26,617 INFO L290 TraceCheckUtils]: 121: Hoare triple {21779#false} assume !(1 == ~E_7~0); {21779#false} is VALID [2022-02-21 04:24:26,617 INFO L290 TraceCheckUtils]: 122: Hoare triple {21779#false} assume !(1 == ~E_8~0); {21779#false} is VALID [2022-02-21 04:24:26,617 INFO L290 TraceCheckUtils]: 123: Hoare triple {21779#false} assume !(1 == ~E_9~0); {21779#false} is VALID [2022-02-21 04:24:26,618 INFO L290 TraceCheckUtils]: 124: Hoare triple {21779#false} assume !(1 == ~E_10~0); {21779#false} is VALID [2022-02-21 04:24:26,618 INFO L290 TraceCheckUtils]: 125: Hoare triple {21779#false} assume { :end_inline_reset_delta_events } true; {21779#false} is VALID [2022-02-21 04:24:26,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:26,618 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:26,618 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220452864] [2022-02-21 04:24:26,618 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [220452864] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:26,619 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:26,619 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:26,619 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501679623] [2022-02-21 04:24:26,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:26,619 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:26,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:26,620 INFO L85 PathProgramCache]: Analyzing trace with hash -103858072, now seen corresponding path program 1 times [2022-02-21 04:24:26,620 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:26,620 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201673054] [2022-02-21 04:24:26,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:26,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:26,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:26,647 INFO L290 TraceCheckUtils]: 0: Hoare triple {21781#true} assume !false; {21781#true} is VALID [2022-02-21 04:24:26,648 INFO L290 TraceCheckUtils]: 1: Hoare triple {21781#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {21781#true} is VALID [2022-02-21 04:24:26,648 INFO L290 TraceCheckUtils]: 2: Hoare triple {21781#true} assume !false; {21781#true} is VALID [2022-02-21 04:24:26,648 INFO L290 TraceCheckUtils]: 3: Hoare triple {21781#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {21781#true} is VALID [2022-02-21 04:24:26,648 INFO L290 TraceCheckUtils]: 4: Hoare triple {21781#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {21781#true} is VALID [2022-02-21 04:24:26,648 INFO L290 TraceCheckUtils]: 5: Hoare triple {21781#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {21781#true} is VALID [2022-02-21 04:24:26,648 INFO L290 TraceCheckUtils]: 6: Hoare triple {21781#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {21781#true} is VALID [2022-02-21 04:24:26,648 INFO L290 TraceCheckUtils]: 7: Hoare triple {21781#true} assume !(0 != eval_~tmp~0#1); {21781#true} is VALID [2022-02-21 04:24:26,648 INFO L290 TraceCheckUtils]: 8: Hoare triple {21781#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {21781#true} is VALID [2022-02-21 04:24:26,649 INFO L290 TraceCheckUtils]: 9: Hoare triple {21781#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {21781#true} is VALID [2022-02-21 04:24:26,649 INFO L290 TraceCheckUtils]: 10: Hoare triple {21781#true} assume 0 == ~M_E~0;~M_E~0 := 1; {21781#true} is VALID [2022-02-21 04:24:26,649 INFO L290 TraceCheckUtils]: 11: Hoare triple {21781#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {21781#true} is VALID [2022-02-21 04:24:26,649 INFO L290 TraceCheckUtils]: 12: Hoare triple {21781#true} assume !(0 == ~T2_E~0); {21781#true} is VALID [2022-02-21 04:24:26,649 INFO L290 TraceCheckUtils]: 13: Hoare triple {21781#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {21781#true} is VALID [2022-02-21 04:24:26,649 INFO L290 TraceCheckUtils]: 14: Hoare triple {21781#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {21781#true} is VALID [2022-02-21 04:24:26,650 INFO L290 TraceCheckUtils]: 15: Hoare triple {21781#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,650 INFO L290 TraceCheckUtils]: 16: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,650 INFO L290 TraceCheckUtils]: 17: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,650 INFO L290 TraceCheckUtils]: 18: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,651 INFO L290 TraceCheckUtils]: 19: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,651 INFO L290 TraceCheckUtils]: 20: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,651 INFO L290 TraceCheckUtils]: 21: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,652 INFO L290 TraceCheckUtils]: 22: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,652 INFO L290 TraceCheckUtils]: 23: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,652 INFO L290 TraceCheckUtils]: 24: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,653 INFO L290 TraceCheckUtils]: 25: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,653 INFO L290 TraceCheckUtils]: 26: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,653 INFO L290 TraceCheckUtils]: 27: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,654 INFO L290 TraceCheckUtils]: 28: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,654 INFO L290 TraceCheckUtils]: 29: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,654 INFO L290 TraceCheckUtils]: 30: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,655 INFO L290 TraceCheckUtils]: 31: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,655 INFO L290 TraceCheckUtils]: 32: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,655 INFO L290 TraceCheckUtils]: 33: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,656 INFO L290 TraceCheckUtils]: 34: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,656 INFO L290 TraceCheckUtils]: 35: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,656 INFO L290 TraceCheckUtils]: 36: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,657 INFO L290 TraceCheckUtils]: 37: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,657 INFO L290 TraceCheckUtils]: 38: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,657 INFO L290 TraceCheckUtils]: 39: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,657 INFO L290 TraceCheckUtils]: 40: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,658 INFO L290 TraceCheckUtils]: 41: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,658 INFO L290 TraceCheckUtils]: 42: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,658 INFO L290 TraceCheckUtils]: 43: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,659 INFO L290 TraceCheckUtils]: 44: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,659 INFO L290 TraceCheckUtils]: 45: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,659 INFO L290 TraceCheckUtils]: 46: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,660 INFO L290 TraceCheckUtils]: 47: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,660 INFO L290 TraceCheckUtils]: 48: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,660 INFO L290 TraceCheckUtils]: 49: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,661 INFO L290 TraceCheckUtils]: 50: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,661 INFO L290 TraceCheckUtils]: 51: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,661 INFO L290 TraceCheckUtils]: 52: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,662 INFO L290 TraceCheckUtils]: 53: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,662 INFO L290 TraceCheckUtils]: 54: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,662 INFO L290 TraceCheckUtils]: 55: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,662 INFO L290 TraceCheckUtils]: 56: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,663 INFO L290 TraceCheckUtils]: 57: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,663 INFO L290 TraceCheckUtils]: 58: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,663 INFO L290 TraceCheckUtils]: 59: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,664 INFO L290 TraceCheckUtils]: 60: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,664 INFO L290 TraceCheckUtils]: 61: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,664 INFO L290 TraceCheckUtils]: 62: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,665 INFO L290 TraceCheckUtils]: 63: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,665 INFO L290 TraceCheckUtils]: 64: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,665 INFO L290 TraceCheckUtils]: 65: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,666 INFO L290 TraceCheckUtils]: 66: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,666 INFO L290 TraceCheckUtils]: 67: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,666 INFO L290 TraceCheckUtils]: 68: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,667 INFO L290 TraceCheckUtils]: 69: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,667 INFO L290 TraceCheckUtils]: 70: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,667 INFO L290 TraceCheckUtils]: 71: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,668 INFO L290 TraceCheckUtils]: 72: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,668 INFO L290 TraceCheckUtils]: 73: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,668 INFO L290 TraceCheckUtils]: 74: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,668 INFO L290 TraceCheckUtils]: 75: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,669 INFO L290 TraceCheckUtils]: 76: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,669 INFO L290 TraceCheckUtils]: 77: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,669 INFO L290 TraceCheckUtils]: 78: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,670 INFO L290 TraceCheckUtils]: 79: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,670 INFO L290 TraceCheckUtils]: 80: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,670 INFO L290 TraceCheckUtils]: 81: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,671 INFO L290 TraceCheckUtils]: 82: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,671 INFO L290 TraceCheckUtils]: 83: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,671 INFO L290 TraceCheckUtils]: 84: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,672 INFO L290 TraceCheckUtils]: 85: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,672 INFO L290 TraceCheckUtils]: 86: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,672 INFO L290 TraceCheckUtils]: 87: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,673 INFO L290 TraceCheckUtils]: 88: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,673 INFO L290 TraceCheckUtils]: 89: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,673 INFO L290 TraceCheckUtils]: 90: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,674 INFO L290 TraceCheckUtils]: 91: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,674 INFO L290 TraceCheckUtils]: 92: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,674 INFO L290 TraceCheckUtils]: 93: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,674 INFO L290 TraceCheckUtils]: 94: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,675 INFO L290 TraceCheckUtils]: 95: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,675 INFO L290 TraceCheckUtils]: 96: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,675 INFO L290 TraceCheckUtils]: 97: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,676 INFO L290 TraceCheckUtils]: 98: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,676 INFO L290 TraceCheckUtils]: 99: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,676 INFO L290 TraceCheckUtils]: 100: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,677 INFO L290 TraceCheckUtils]: 101: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,677 INFO L290 TraceCheckUtils]: 102: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {21783#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,677 INFO L290 TraceCheckUtils]: 103: Hoare triple {21783#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {21782#false} is VALID [2022-02-21 04:24:26,677 INFO L290 TraceCheckUtils]: 104: Hoare triple {21782#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,678 INFO L290 TraceCheckUtils]: 105: Hoare triple {21782#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,678 INFO L290 TraceCheckUtils]: 106: Hoare triple {21782#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,678 INFO L290 TraceCheckUtils]: 107: Hoare triple {21782#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,678 INFO L290 TraceCheckUtils]: 108: Hoare triple {21782#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,678 INFO L290 TraceCheckUtils]: 109: Hoare triple {21782#false} assume 1 == ~E_1~0;~E_1~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,678 INFO L290 TraceCheckUtils]: 110: Hoare triple {21782#false} assume 1 == ~E_2~0;~E_2~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,678 INFO L290 TraceCheckUtils]: 111: Hoare triple {21782#false} assume !(1 == ~E_3~0); {21782#false} is VALID [2022-02-21 04:24:26,678 INFO L290 TraceCheckUtils]: 112: Hoare triple {21782#false} assume 1 == ~E_4~0;~E_4~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,679 INFO L290 TraceCheckUtils]: 113: Hoare triple {21782#false} assume 1 == ~E_5~0;~E_5~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,679 INFO L290 TraceCheckUtils]: 114: Hoare triple {21782#false} assume 1 == ~E_6~0;~E_6~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,679 INFO L290 TraceCheckUtils]: 115: Hoare triple {21782#false} assume 1 == ~E_7~0;~E_7~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,679 INFO L290 TraceCheckUtils]: 116: Hoare triple {21782#false} assume 1 == ~E_8~0;~E_8~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,679 INFO L290 TraceCheckUtils]: 117: Hoare triple {21782#false} assume 1 == ~E_9~0;~E_9~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,679 INFO L290 TraceCheckUtils]: 118: Hoare triple {21782#false} assume 1 == ~E_10~0;~E_10~0 := 2; {21782#false} is VALID [2022-02-21 04:24:26,679 INFO L290 TraceCheckUtils]: 119: Hoare triple {21782#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {21782#false} is VALID [2022-02-21 04:24:26,679 INFO L290 TraceCheckUtils]: 120: Hoare triple {21782#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {21782#false} is VALID [2022-02-21 04:24:26,679 INFO L290 TraceCheckUtils]: 121: Hoare triple {21782#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {21782#false} is VALID [2022-02-21 04:24:26,680 INFO L290 TraceCheckUtils]: 122: Hoare triple {21782#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {21782#false} is VALID [2022-02-21 04:24:26,680 INFO L290 TraceCheckUtils]: 123: Hoare triple {21782#false} assume !(0 == start_simulation_~tmp~3#1); {21782#false} is VALID [2022-02-21 04:24:26,680 INFO L290 TraceCheckUtils]: 124: Hoare triple {21782#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {21782#false} is VALID [2022-02-21 04:24:26,680 INFO L290 TraceCheckUtils]: 125: Hoare triple {21782#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {21782#false} is VALID [2022-02-21 04:24:26,680 INFO L290 TraceCheckUtils]: 126: Hoare triple {21782#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {21782#false} is VALID [2022-02-21 04:24:26,680 INFO L290 TraceCheckUtils]: 127: Hoare triple {21782#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {21782#false} is VALID [2022-02-21 04:24:26,680 INFO L290 TraceCheckUtils]: 128: Hoare triple {21782#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {21782#false} is VALID [2022-02-21 04:24:26,680 INFO L290 TraceCheckUtils]: 129: Hoare triple {21782#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {21782#false} is VALID [2022-02-21 04:24:26,680 INFO L290 TraceCheckUtils]: 130: Hoare triple {21782#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {21782#false} is VALID [2022-02-21 04:24:26,681 INFO L290 TraceCheckUtils]: 131: Hoare triple {21782#false} assume !(0 != start_simulation_~tmp___0~1#1); {21782#false} is VALID [2022-02-21 04:24:26,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:26,681 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:26,681 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [201673054] [2022-02-21 04:24:26,681 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [201673054] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:26,682 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:26,682 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:26,682 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1723937060] [2022-02-21 04:24:26,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:26,682 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:26,682 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:26,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:26,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:26,684 INFO L87 Difference]: Start difference. First operand 1278 states and 1898 transitions. cyclomatic complexity: 621 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:27,435 INFO L93 Difference]: Finished difference Result 1278 states and 1897 transitions. [2022-02-21 04:24:27,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:27,436 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,522 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:27,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1897 transitions. [2022-02-21 04:24:27,568 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:27,617 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1897 transitions. [2022-02-21 04:24:27,617 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-02-21 04:24:27,617 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-02-21 04:24:27,617 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1897 transitions. [2022-02-21 04:24:27,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:27,620 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2022-02-21 04:24:27,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1897 transitions. [2022-02-21 04:24:27,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-02-21 04:24:27,631 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:27,632 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1278 states and 1897 transitions. Second operand has 1278 states, 1278 states have (on average 1.4843505477308294) internal successors, (1897), 1277 states have internal predecessors, (1897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,633 INFO L74 IsIncluded]: Start isIncluded. First operand 1278 states and 1897 transitions. Second operand has 1278 states, 1278 states have (on average 1.4843505477308294) internal successors, (1897), 1277 states have internal predecessors, (1897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,635 INFO L87 Difference]: Start difference. First operand 1278 states and 1897 transitions. Second operand has 1278 states, 1278 states have (on average 1.4843505477308294) internal successors, (1897), 1277 states have internal predecessors, (1897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:27,672 INFO L93 Difference]: Finished difference Result 1278 states and 1897 transitions. [2022-02-21 04:24:27,672 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1897 transitions. [2022-02-21 04:24:27,675 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:27,675 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:27,677 INFO L74 IsIncluded]: Start isIncluded. First operand has 1278 states, 1278 states have (on average 1.4843505477308294) internal successors, (1897), 1277 states have internal predecessors, (1897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1897 transitions. [2022-02-21 04:24:27,679 INFO L87 Difference]: Start difference. First operand has 1278 states, 1278 states have (on average 1.4843505477308294) internal successors, (1897), 1277 states have internal predecessors, (1897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1897 transitions. [2022-02-21 04:24:27,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:27,725 INFO L93 Difference]: Finished difference Result 1278 states and 1897 transitions. [2022-02-21 04:24:27,725 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1897 transitions. [2022-02-21 04:24:27,726 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:27,726 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:27,726 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:27,726 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:27,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4843505477308294) internal successors, (1897), 1277 states have internal predecessors, (1897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1897 transitions. [2022-02-21 04:24:27,771 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2022-02-21 04:24:27,771 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1897 transitions. [2022-02-21 04:24:27,771 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:27,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1897 transitions. [2022-02-21 04:24:27,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:27,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:27,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:27,776 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:27,776 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:27,776 INFO L791 eck$LassoCheckResult]: Stem: 24044#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 24045#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 24319#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24307#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24308#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 24328#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24329#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23612#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23330#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23331#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24237#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 24238#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 24223#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24224#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24259#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 23384#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23385#L1006 assume !(0 == ~M_E~0); 23233#L1006-2 assume !(0 == ~T1_E~0); 23234#L1011-1 assume !(0 == ~T2_E~0); 24281#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24296#L1021-1 assume !(0 == ~T4_E~0); 23115#L1026-1 assume !(0 == ~T5_E~0); 23116#L1031-1 assume !(0 == ~T6_E~0); 23989#L1036-1 assume !(0 == ~T7_E~0); 23985#L1041-1 assume !(0 == ~T8_E~0); 23986#L1046-1 assume !(0 == ~T9_E~0); 23415#L1051-1 assume !(0 == ~T10_E~0); 23416#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 24118#L1061-1 assume !(0 == ~E_2~0); 23334#L1066-1 assume !(0 == ~E_3~0); 23335#L1071-1 assume !(0 == ~E_4~0); 24097#L1076-1 assume !(0 == ~E_5~0); 23244#L1081-1 assume !(0 == ~E_6~0); 23245#L1086-1 assume !(0 == ~E_7~0); 23587#L1091-1 assume !(0 == ~E_8~0); 24274#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 24275#L1101-1 assume !(0 == ~E_10~0); 23649#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23650#L484 assume !(1 == ~m_pc~0); 23293#L484-2 is_master_triggered_~__retres1~0#1 := 0; 23292#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23908#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24192#L1245 assume !(0 != activate_threads_~tmp~1#1); 24193#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23977#L503 assume 1 == ~t1_pc~0; 23978#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23995#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24110#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23763#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 23143#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23144#L522 assume !(1 == ~t2_pc~0); 23944#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23347#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23348#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23818#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 24239#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24304#L541 assume 1 == ~t3_pc~0; 23893#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23709#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23524#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23525#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 23947#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23948#L560 assume !(1 == ~t4_pc~0); 23227#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23226#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23852#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23111#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 23112#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23398#L579 assume 1 == ~t5_pc~0; 23062#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23063#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23171#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23855#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 24295#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24316#L598 assume 1 == ~t6_pc~0; 23492#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23493#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23795#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24215#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 24026#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23968#L617 assume !(1 == ~t7_pc~0); 23465#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 23464#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23750#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23751#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23686#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23687#L636 assume 1 == ~t8_pc~0; 23849#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23850#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23651#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23652#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 23802#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23803#L655 assume !(1 == ~t9_pc~0); 23832#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 23833#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23444#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23445#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 24046#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24047#L674 assume 1 == ~t10_pc~0; 23220#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23221#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24306#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24337#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 23792#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23793#L1119 assume !(1 == ~M_E~0); 23316#L1119-2 assume !(1 == ~T1_E~0); 23317#L1124-1 assume !(1 == ~T2_E~0); 23135#L1129-1 assume !(1 == ~T3_E~0); 23136#L1134-1 assume !(1 == ~T4_E~0); 23449#L1139-1 assume !(1 == ~T5_E~0); 23450#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23682#L1149-1 assume !(1 == ~T7_E~0); 23311#L1154-1 assume !(1 == ~T8_E~0); 23312#L1159-1 assume !(1 == ~T9_E~0); 23399#L1164-1 assume !(1 == ~T10_E~0); 23821#L1169-1 assume !(1 == ~E_1~0); 23719#L1174-1 assume !(1 == ~E_2~0); 23506#L1179-1 assume !(1 == ~E_3~0); 23388#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 23389#L1189-1 assume !(1 == ~E_5~0); 23442#L1194-1 assume !(1 == ~E_6~0); 23565#L1199-1 assume !(1 == ~E_7~0); 23516#L1204-1 assume !(1 == ~E_8~0); 23517#L1209-1 assume !(1 == ~E_9~0); 24040#L1214-1 assume !(1 == ~E_10~0); 24041#L1219-1 assume { :end_inline_reset_delta_events } true; 23099#L1520-2 [2022-02-21 04:24:27,777 INFO L793 eck$LassoCheckResult]: Loop: 23099#L1520-2 assume !false; 23100#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23203#L981 assume !false; 23395#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24067#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23085#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24185#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24235#L836 assume !(0 != eval_~tmp~0#1); 23677#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23678#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23673#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23674#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24144#L1011-3 assume !(0 == ~T2_E~0); 24145#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24184#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23867#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23868#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24112#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24113#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24175#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24176#L1051-3 assume !(0 == ~T10_E~0); 24114#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23412#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23413#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23414#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24285#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23197#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23198#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23252#L1091-3 assume !(0 == ~E_8~0); 23253#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24260#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24261#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23887#L484-33 assume 1 == ~m_pc~0; 23888#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23807#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23808#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23105#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23106#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23577#L503-33 assume !(1 == ~t1_pc~0); 23578#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 24028#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23957#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23484#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23485#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23924#L522-33 assume 1 == ~t2_pc~0; 23925#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23240#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23241#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24034#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23942#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23943#L541-33 assume 1 == ~t3_pc~0; 23264#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23103#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23104#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23914#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23915#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24109#L560-33 assume 1 == ~t4_pc~0; 23814#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23175#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23176#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23432#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 24091#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23091#L579-33 assume 1 == ~t5_pc~0; 23092#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23340#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24300#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23969#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23970#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23994#L598-33 assume !(1 == ~t6_pc~0); 23767#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 23598#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23599#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23439#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23440#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24249#L617-33 assume 1 == ~t7_pc~0; 24255#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23232#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24183#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24290#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24286#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23163#L636-33 assume !(1 == ~t8_pc~0); 23164#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 24083#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24084#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24309#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24072#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24073#L655-33 assume 1 == ~t9_pc~0; 24333#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23539#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23540#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23898#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24162#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23718#L674-33 assume 1 == ~t10_pc~0; 23593#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23594#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23455#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23456#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23933#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24310#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24317#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24320#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24331#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23477#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23478#L1139-3 assume !(1 == ~T5_E~0); 23711#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23712#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23854#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24124#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24125#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24291#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23596#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23597#L1179-3 assume !(1 == ~E_3~0); 24216#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23223#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23224#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23537#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23538#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23841#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23117#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23118#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24031#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23200#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23554#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23555#L1539 assume !(0 == start_simulation_~tmp~3#1); 23647#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23823#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23630#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23762#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23546#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23547#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24151#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23648#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 23099#L1520-2 [2022-02-21 04:24:27,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:27,781 INFO L85 PathProgramCache]: Analyzing trace with hash 709992811, now seen corresponding path program 1 times [2022-02-21 04:24:27,781 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:27,781 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672167861] [2022-02-21 04:24:27,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:27,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:27,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:27,799 INFO L290 TraceCheckUtils]: 0: Hoare triple {26899#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {26899#true} is VALID [2022-02-21 04:24:27,800 INFO L290 TraceCheckUtils]: 1: Hoare triple {26899#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {26901#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:27,800 INFO L290 TraceCheckUtils]: 2: Hoare triple {26901#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {26901#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:27,800 INFO L290 TraceCheckUtils]: 3: Hoare triple {26901#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {26901#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:27,801 INFO L290 TraceCheckUtils]: 4: Hoare triple {26901#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {26901#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:27,801 INFO L290 TraceCheckUtils]: 5: Hoare triple {26901#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {26901#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:27,801 INFO L290 TraceCheckUtils]: 6: Hoare triple {26901#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {26901#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:27,801 INFO L290 TraceCheckUtils]: 7: Hoare triple {26901#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {26901#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:27,802 INFO L290 TraceCheckUtils]: 8: Hoare triple {26901#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {26901#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:27,802 INFO L290 TraceCheckUtils]: 9: Hoare triple {26901#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {26901#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:27,802 INFO L290 TraceCheckUtils]: 10: Hoare triple {26901#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {26900#false} is VALID [2022-02-21 04:24:27,802 INFO L290 TraceCheckUtils]: 11: Hoare triple {26900#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {26900#false} is VALID [2022-02-21 04:24:27,802 INFO L290 TraceCheckUtils]: 12: Hoare triple {26900#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {26900#false} is VALID [2022-02-21 04:24:27,803 INFO L290 TraceCheckUtils]: 13: Hoare triple {26900#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {26900#false} is VALID [2022-02-21 04:24:27,803 INFO L290 TraceCheckUtils]: 14: Hoare triple {26900#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {26900#false} is VALID [2022-02-21 04:24:27,803 INFO L290 TraceCheckUtils]: 15: Hoare triple {26900#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {26900#false} is VALID [2022-02-21 04:24:27,803 INFO L290 TraceCheckUtils]: 16: Hoare triple {26900#false} assume !(0 == ~M_E~0); {26900#false} is VALID [2022-02-21 04:24:27,803 INFO L290 TraceCheckUtils]: 17: Hoare triple {26900#false} assume !(0 == ~T1_E~0); {26900#false} is VALID [2022-02-21 04:24:27,803 INFO L290 TraceCheckUtils]: 18: Hoare triple {26900#false} assume !(0 == ~T2_E~0); {26900#false} is VALID [2022-02-21 04:24:27,803 INFO L290 TraceCheckUtils]: 19: Hoare triple {26900#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {26900#false} is VALID [2022-02-21 04:24:27,803 INFO L290 TraceCheckUtils]: 20: Hoare triple {26900#false} assume !(0 == ~T4_E~0); {26900#false} is VALID [2022-02-21 04:24:27,804 INFO L290 TraceCheckUtils]: 21: Hoare triple {26900#false} assume !(0 == ~T5_E~0); {26900#false} is VALID [2022-02-21 04:24:27,804 INFO L290 TraceCheckUtils]: 22: Hoare triple {26900#false} assume !(0 == ~T6_E~0); {26900#false} is VALID [2022-02-21 04:24:27,804 INFO L290 TraceCheckUtils]: 23: Hoare triple {26900#false} assume !(0 == ~T7_E~0); {26900#false} is VALID [2022-02-21 04:24:27,804 INFO L290 TraceCheckUtils]: 24: Hoare triple {26900#false} assume !(0 == ~T8_E~0); {26900#false} is VALID [2022-02-21 04:24:27,804 INFO L290 TraceCheckUtils]: 25: Hoare triple {26900#false} assume !(0 == ~T9_E~0); {26900#false} is VALID [2022-02-21 04:24:27,804 INFO L290 TraceCheckUtils]: 26: Hoare triple {26900#false} assume !(0 == ~T10_E~0); {26900#false} is VALID [2022-02-21 04:24:27,804 INFO L290 TraceCheckUtils]: 27: Hoare triple {26900#false} assume 0 == ~E_1~0;~E_1~0 := 1; {26900#false} is VALID [2022-02-21 04:24:27,804 INFO L290 TraceCheckUtils]: 28: Hoare triple {26900#false} assume !(0 == ~E_2~0); {26900#false} is VALID [2022-02-21 04:24:27,804 INFO L290 TraceCheckUtils]: 29: Hoare triple {26900#false} assume !(0 == ~E_3~0); {26900#false} is VALID [2022-02-21 04:24:27,805 INFO L290 TraceCheckUtils]: 30: Hoare triple {26900#false} assume !(0 == ~E_4~0); {26900#false} is VALID [2022-02-21 04:24:27,805 INFO L290 TraceCheckUtils]: 31: Hoare triple {26900#false} assume !(0 == ~E_5~0); {26900#false} is VALID [2022-02-21 04:24:27,805 INFO L290 TraceCheckUtils]: 32: Hoare triple {26900#false} assume !(0 == ~E_6~0); {26900#false} is VALID [2022-02-21 04:24:27,805 INFO L290 TraceCheckUtils]: 33: Hoare triple {26900#false} assume !(0 == ~E_7~0); {26900#false} is VALID [2022-02-21 04:24:27,805 INFO L290 TraceCheckUtils]: 34: Hoare triple {26900#false} assume !(0 == ~E_8~0); {26900#false} is VALID [2022-02-21 04:24:27,805 INFO L290 TraceCheckUtils]: 35: Hoare triple {26900#false} assume 0 == ~E_9~0;~E_9~0 := 1; {26900#false} is VALID [2022-02-21 04:24:27,805 INFO L290 TraceCheckUtils]: 36: Hoare triple {26900#false} assume !(0 == ~E_10~0); {26900#false} is VALID [2022-02-21 04:24:27,805 INFO L290 TraceCheckUtils]: 37: Hoare triple {26900#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26900#false} is VALID [2022-02-21 04:24:27,806 INFO L290 TraceCheckUtils]: 38: Hoare triple {26900#false} assume !(1 == ~m_pc~0); {26900#false} is VALID [2022-02-21 04:24:27,806 INFO L290 TraceCheckUtils]: 39: Hoare triple {26900#false} is_master_triggered_~__retres1~0#1 := 0; {26900#false} is VALID [2022-02-21 04:24:27,806 INFO L290 TraceCheckUtils]: 40: Hoare triple {26900#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26900#false} is VALID [2022-02-21 04:24:27,806 INFO L290 TraceCheckUtils]: 41: Hoare triple {26900#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {26900#false} is VALID [2022-02-21 04:24:27,806 INFO L290 TraceCheckUtils]: 42: Hoare triple {26900#false} assume !(0 != activate_threads_~tmp~1#1); {26900#false} is VALID [2022-02-21 04:24:27,806 INFO L290 TraceCheckUtils]: 43: Hoare triple {26900#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26900#false} is VALID [2022-02-21 04:24:27,806 INFO L290 TraceCheckUtils]: 44: Hoare triple {26900#false} assume 1 == ~t1_pc~0; {26900#false} is VALID [2022-02-21 04:24:27,806 INFO L290 TraceCheckUtils]: 45: Hoare triple {26900#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {26900#false} is VALID [2022-02-21 04:24:27,806 INFO L290 TraceCheckUtils]: 46: Hoare triple {26900#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26900#false} is VALID [2022-02-21 04:24:27,807 INFO L290 TraceCheckUtils]: 47: Hoare triple {26900#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {26900#false} is VALID [2022-02-21 04:24:27,807 INFO L290 TraceCheckUtils]: 48: Hoare triple {26900#false} assume !(0 != activate_threads_~tmp___0~0#1); {26900#false} is VALID [2022-02-21 04:24:27,807 INFO L290 TraceCheckUtils]: 49: Hoare triple {26900#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26900#false} is VALID [2022-02-21 04:24:27,807 INFO L290 TraceCheckUtils]: 50: Hoare triple {26900#false} assume !(1 == ~t2_pc~0); {26900#false} is VALID [2022-02-21 04:24:27,807 INFO L290 TraceCheckUtils]: 51: Hoare triple {26900#false} is_transmit2_triggered_~__retres1~2#1 := 0; {26900#false} is VALID [2022-02-21 04:24:27,807 INFO L290 TraceCheckUtils]: 52: Hoare triple {26900#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26900#false} is VALID [2022-02-21 04:24:27,807 INFO L290 TraceCheckUtils]: 53: Hoare triple {26900#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {26900#false} is VALID [2022-02-21 04:24:27,807 INFO L290 TraceCheckUtils]: 54: Hoare triple {26900#false} assume !(0 != activate_threads_~tmp___1~0#1); {26900#false} is VALID [2022-02-21 04:24:27,808 INFO L290 TraceCheckUtils]: 55: Hoare triple {26900#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26900#false} is VALID [2022-02-21 04:24:27,808 INFO L290 TraceCheckUtils]: 56: Hoare triple {26900#false} assume 1 == ~t3_pc~0; {26900#false} is VALID [2022-02-21 04:24:27,808 INFO L290 TraceCheckUtils]: 57: Hoare triple {26900#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {26900#false} is VALID [2022-02-21 04:24:27,808 INFO L290 TraceCheckUtils]: 58: Hoare triple {26900#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26900#false} is VALID [2022-02-21 04:24:27,808 INFO L290 TraceCheckUtils]: 59: Hoare triple {26900#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {26900#false} is VALID [2022-02-21 04:24:27,808 INFO L290 TraceCheckUtils]: 60: Hoare triple {26900#false} assume !(0 != activate_threads_~tmp___2~0#1); {26900#false} is VALID [2022-02-21 04:24:27,808 INFO L290 TraceCheckUtils]: 61: Hoare triple {26900#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26900#false} is VALID [2022-02-21 04:24:27,808 INFO L290 TraceCheckUtils]: 62: Hoare triple {26900#false} assume !(1 == ~t4_pc~0); {26900#false} is VALID [2022-02-21 04:24:27,808 INFO L290 TraceCheckUtils]: 63: Hoare triple {26900#false} is_transmit4_triggered_~__retres1~4#1 := 0; {26900#false} is VALID [2022-02-21 04:24:27,809 INFO L290 TraceCheckUtils]: 64: Hoare triple {26900#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26900#false} is VALID [2022-02-21 04:24:27,809 INFO L290 TraceCheckUtils]: 65: Hoare triple {26900#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {26900#false} is VALID [2022-02-21 04:24:27,809 INFO L290 TraceCheckUtils]: 66: Hoare triple {26900#false} assume !(0 != activate_threads_~tmp___3~0#1); {26900#false} is VALID [2022-02-21 04:24:27,809 INFO L290 TraceCheckUtils]: 67: Hoare triple {26900#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26900#false} is VALID [2022-02-21 04:24:27,809 INFO L290 TraceCheckUtils]: 68: Hoare triple {26900#false} assume 1 == ~t5_pc~0; {26900#false} is VALID [2022-02-21 04:24:27,809 INFO L290 TraceCheckUtils]: 69: Hoare triple {26900#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {26900#false} is VALID [2022-02-21 04:24:27,809 INFO L290 TraceCheckUtils]: 70: Hoare triple {26900#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26900#false} is VALID [2022-02-21 04:24:27,809 INFO L290 TraceCheckUtils]: 71: Hoare triple {26900#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26900#false} is VALID [2022-02-21 04:24:27,810 INFO L290 TraceCheckUtils]: 72: Hoare triple {26900#false} assume !(0 != activate_threads_~tmp___4~0#1); {26900#false} is VALID [2022-02-21 04:24:27,810 INFO L290 TraceCheckUtils]: 73: Hoare triple {26900#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26900#false} is VALID [2022-02-21 04:24:27,810 INFO L290 TraceCheckUtils]: 74: Hoare triple {26900#false} assume 1 == ~t6_pc~0; {26900#false} is VALID [2022-02-21 04:24:27,810 INFO L290 TraceCheckUtils]: 75: Hoare triple {26900#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {26900#false} is VALID [2022-02-21 04:24:27,810 INFO L290 TraceCheckUtils]: 76: Hoare triple {26900#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26900#false} is VALID [2022-02-21 04:24:27,810 INFO L290 TraceCheckUtils]: 77: Hoare triple {26900#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26900#false} is VALID [2022-02-21 04:24:27,810 INFO L290 TraceCheckUtils]: 78: Hoare triple {26900#false} assume !(0 != activate_threads_~tmp___5~0#1); {26900#false} is VALID [2022-02-21 04:24:27,810 INFO L290 TraceCheckUtils]: 79: Hoare triple {26900#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26900#false} is VALID [2022-02-21 04:24:27,810 INFO L290 TraceCheckUtils]: 80: Hoare triple {26900#false} assume !(1 == ~t7_pc~0); {26900#false} is VALID [2022-02-21 04:24:27,811 INFO L290 TraceCheckUtils]: 81: Hoare triple {26900#false} is_transmit7_triggered_~__retres1~7#1 := 0; {26900#false} is VALID [2022-02-21 04:24:27,811 INFO L290 TraceCheckUtils]: 82: Hoare triple {26900#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26900#false} is VALID [2022-02-21 04:24:27,811 INFO L290 TraceCheckUtils]: 83: Hoare triple {26900#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26900#false} is VALID [2022-02-21 04:24:27,811 INFO L290 TraceCheckUtils]: 84: Hoare triple {26900#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {26900#false} is VALID [2022-02-21 04:24:27,811 INFO L290 TraceCheckUtils]: 85: Hoare triple {26900#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26900#false} is VALID [2022-02-21 04:24:27,811 INFO L290 TraceCheckUtils]: 86: Hoare triple {26900#false} assume 1 == ~t8_pc~0; {26900#false} is VALID [2022-02-21 04:24:27,811 INFO L290 TraceCheckUtils]: 87: Hoare triple {26900#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {26900#false} is VALID [2022-02-21 04:24:27,811 INFO L290 TraceCheckUtils]: 88: Hoare triple {26900#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26900#false} is VALID [2022-02-21 04:24:27,811 INFO L290 TraceCheckUtils]: 89: Hoare triple {26900#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26900#false} is VALID [2022-02-21 04:24:27,812 INFO L290 TraceCheckUtils]: 90: Hoare triple {26900#false} assume !(0 != activate_threads_~tmp___7~0#1); {26900#false} is VALID [2022-02-21 04:24:27,812 INFO L290 TraceCheckUtils]: 91: Hoare triple {26900#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26900#false} is VALID [2022-02-21 04:24:27,812 INFO L290 TraceCheckUtils]: 92: Hoare triple {26900#false} assume !(1 == ~t9_pc~0); {26900#false} is VALID [2022-02-21 04:24:27,812 INFO L290 TraceCheckUtils]: 93: Hoare triple {26900#false} is_transmit9_triggered_~__retres1~9#1 := 0; {26900#false} is VALID [2022-02-21 04:24:27,812 INFO L290 TraceCheckUtils]: 94: Hoare triple {26900#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26900#false} is VALID [2022-02-21 04:24:27,812 INFO L290 TraceCheckUtils]: 95: Hoare triple {26900#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26900#false} is VALID [2022-02-21 04:24:27,812 INFO L290 TraceCheckUtils]: 96: Hoare triple {26900#false} assume !(0 != activate_threads_~tmp___8~0#1); {26900#false} is VALID [2022-02-21 04:24:27,812 INFO L290 TraceCheckUtils]: 97: Hoare triple {26900#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26900#false} is VALID [2022-02-21 04:24:27,813 INFO L290 TraceCheckUtils]: 98: Hoare triple {26900#false} assume 1 == ~t10_pc~0; {26900#false} is VALID [2022-02-21 04:24:27,813 INFO L290 TraceCheckUtils]: 99: Hoare triple {26900#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {26900#false} is VALID [2022-02-21 04:24:27,813 INFO L290 TraceCheckUtils]: 100: Hoare triple {26900#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26900#false} is VALID [2022-02-21 04:24:27,813 INFO L290 TraceCheckUtils]: 101: Hoare triple {26900#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26900#false} is VALID [2022-02-21 04:24:27,813 INFO L290 TraceCheckUtils]: 102: Hoare triple {26900#false} assume !(0 != activate_threads_~tmp___9~0#1); {26900#false} is VALID [2022-02-21 04:24:27,813 INFO L290 TraceCheckUtils]: 103: Hoare triple {26900#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26900#false} is VALID [2022-02-21 04:24:27,813 INFO L290 TraceCheckUtils]: 104: Hoare triple {26900#false} assume !(1 == ~M_E~0); {26900#false} is VALID [2022-02-21 04:24:27,813 INFO L290 TraceCheckUtils]: 105: Hoare triple {26900#false} assume !(1 == ~T1_E~0); {26900#false} is VALID [2022-02-21 04:24:27,813 INFO L290 TraceCheckUtils]: 106: Hoare triple {26900#false} assume !(1 == ~T2_E~0); {26900#false} is VALID [2022-02-21 04:24:27,814 INFO L290 TraceCheckUtils]: 107: Hoare triple {26900#false} assume !(1 == ~T3_E~0); {26900#false} is VALID [2022-02-21 04:24:27,814 INFO L290 TraceCheckUtils]: 108: Hoare triple {26900#false} assume !(1 == ~T4_E~0); {26900#false} is VALID [2022-02-21 04:24:27,814 INFO L290 TraceCheckUtils]: 109: Hoare triple {26900#false} assume !(1 == ~T5_E~0); {26900#false} is VALID [2022-02-21 04:24:27,814 INFO L290 TraceCheckUtils]: 110: Hoare triple {26900#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {26900#false} is VALID [2022-02-21 04:24:27,814 INFO L290 TraceCheckUtils]: 111: Hoare triple {26900#false} assume !(1 == ~T7_E~0); {26900#false} is VALID [2022-02-21 04:24:27,814 INFO L290 TraceCheckUtils]: 112: Hoare triple {26900#false} assume !(1 == ~T8_E~0); {26900#false} is VALID [2022-02-21 04:24:27,814 INFO L290 TraceCheckUtils]: 113: Hoare triple {26900#false} assume !(1 == ~T9_E~0); {26900#false} is VALID [2022-02-21 04:24:27,814 INFO L290 TraceCheckUtils]: 114: Hoare triple {26900#false} assume !(1 == ~T10_E~0); {26900#false} is VALID [2022-02-21 04:24:27,815 INFO L290 TraceCheckUtils]: 115: Hoare triple {26900#false} assume !(1 == ~E_1~0); {26900#false} is VALID [2022-02-21 04:24:27,815 INFO L290 TraceCheckUtils]: 116: Hoare triple {26900#false} assume !(1 == ~E_2~0); {26900#false} is VALID [2022-02-21 04:24:27,815 INFO L290 TraceCheckUtils]: 117: Hoare triple {26900#false} assume !(1 == ~E_3~0); {26900#false} is VALID [2022-02-21 04:24:27,815 INFO L290 TraceCheckUtils]: 118: Hoare triple {26900#false} assume 1 == ~E_4~0;~E_4~0 := 2; {26900#false} is VALID [2022-02-21 04:24:27,815 INFO L290 TraceCheckUtils]: 119: Hoare triple {26900#false} assume !(1 == ~E_5~0); {26900#false} is VALID [2022-02-21 04:24:27,815 INFO L290 TraceCheckUtils]: 120: Hoare triple {26900#false} assume !(1 == ~E_6~0); {26900#false} is VALID [2022-02-21 04:24:27,815 INFO L290 TraceCheckUtils]: 121: Hoare triple {26900#false} assume !(1 == ~E_7~0); {26900#false} is VALID [2022-02-21 04:24:27,815 INFO L290 TraceCheckUtils]: 122: Hoare triple {26900#false} assume !(1 == ~E_8~0); {26900#false} is VALID [2022-02-21 04:24:27,815 INFO L290 TraceCheckUtils]: 123: Hoare triple {26900#false} assume !(1 == ~E_9~0); {26900#false} is VALID [2022-02-21 04:24:27,816 INFO L290 TraceCheckUtils]: 124: Hoare triple {26900#false} assume !(1 == ~E_10~0); {26900#false} is VALID [2022-02-21 04:24:27,816 INFO L290 TraceCheckUtils]: 125: Hoare triple {26900#false} assume { :end_inline_reset_delta_events } true; {26900#false} is VALID [2022-02-21 04:24:27,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:27,816 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:27,816 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1672167861] [2022-02-21 04:24:27,816 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1672167861] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:27,817 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:27,817 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:27,817 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869255238] [2022-02-21 04:24:27,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:27,817 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:27,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:27,818 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 4 times [2022-02-21 04:24:27,818 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:27,822 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822955302] [2022-02-21 04:24:27,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:27,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:27,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:27,848 INFO L290 TraceCheckUtils]: 0: Hoare triple {26902#true} assume !false; {26902#true} is VALID [2022-02-21 04:24:27,849 INFO L290 TraceCheckUtils]: 1: Hoare triple {26902#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {26902#true} is VALID [2022-02-21 04:24:27,849 INFO L290 TraceCheckUtils]: 2: Hoare triple {26902#true} assume !false; {26902#true} is VALID [2022-02-21 04:24:27,849 INFO L290 TraceCheckUtils]: 3: Hoare triple {26902#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {26902#true} is VALID [2022-02-21 04:24:27,849 INFO L290 TraceCheckUtils]: 4: Hoare triple {26902#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {26902#true} is VALID [2022-02-21 04:24:27,849 INFO L290 TraceCheckUtils]: 5: Hoare triple {26902#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {26902#true} is VALID [2022-02-21 04:24:27,863 INFO L290 TraceCheckUtils]: 6: Hoare triple {26902#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {26902#true} is VALID [2022-02-21 04:24:27,863 INFO L290 TraceCheckUtils]: 7: Hoare triple {26902#true} assume !(0 != eval_~tmp~0#1); {26902#true} is VALID [2022-02-21 04:24:27,863 INFO L290 TraceCheckUtils]: 8: Hoare triple {26902#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {26902#true} is VALID [2022-02-21 04:24:27,864 INFO L290 TraceCheckUtils]: 9: Hoare triple {26902#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {26902#true} is VALID [2022-02-21 04:24:27,864 INFO L290 TraceCheckUtils]: 10: Hoare triple {26902#true} assume 0 == ~M_E~0;~M_E~0 := 1; {26902#true} is VALID [2022-02-21 04:24:27,864 INFO L290 TraceCheckUtils]: 11: Hoare triple {26902#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {26902#true} is VALID [2022-02-21 04:24:27,864 INFO L290 TraceCheckUtils]: 12: Hoare triple {26902#true} assume !(0 == ~T2_E~0); {26902#true} is VALID [2022-02-21 04:24:27,864 INFO L290 TraceCheckUtils]: 13: Hoare triple {26902#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {26902#true} is VALID [2022-02-21 04:24:27,864 INFO L290 TraceCheckUtils]: 14: Hoare triple {26902#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {26902#true} is VALID [2022-02-21 04:24:27,866 INFO L290 TraceCheckUtils]: 15: Hoare triple {26902#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,866 INFO L290 TraceCheckUtils]: 16: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,867 INFO L290 TraceCheckUtils]: 17: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,867 INFO L290 TraceCheckUtils]: 18: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,867 INFO L290 TraceCheckUtils]: 19: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,868 INFO L290 TraceCheckUtils]: 20: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,868 INFO L290 TraceCheckUtils]: 21: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,868 INFO L290 TraceCheckUtils]: 22: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,869 INFO L290 TraceCheckUtils]: 23: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,869 INFO L290 TraceCheckUtils]: 24: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,869 INFO L290 TraceCheckUtils]: 25: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,870 INFO L290 TraceCheckUtils]: 26: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,870 INFO L290 TraceCheckUtils]: 27: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,871 INFO L290 TraceCheckUtils]: 28: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,871 INFO L290 TraceCheckUtils]: 29: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,871 INFO L290 TraceCheckUtils]: 30: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,872 INFO L290 TraceCheckUtils]: 31: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,872 INFO L290 TraceCheckUtils]: 32: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,872 INFO L290 TraceCheckUtils]: 33: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,873 INFO L290 TraceCheckUtils]: 34: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,873 INFO L290 TraceCheckUtils]: 35: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,873 INFO L290 TraceCheckUtils]: 36: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,874 INFO L290 TraceCheckUtils]: 37: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,874 INFO L290 TraceCheckUtils]: 38: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,874 INFO L290 TraceCheckUtils]: 39: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,875 INFO L290 TraceCheckUtils]: 40: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,875 INFO L290 TraceCheckUtils]: 41: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,876 INFO L290 TraceCheckUtils]: 42: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,876 INFO L290 TraceCheckUtils]: 43: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,876 INFO L290 TraceCheckUtils]: 44: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,877 INFO L290 TraceCheckUtils]: 45: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,877 INFO L290 TraceCheckUtils]: 46: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,877 INFO L290 TraceCheckUtils]: 47: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,878 INFO L290 TraceCheckUtils]: 48: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,878 INFO L290 TraceCheckUtils]: 49: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,878 INFO L290 TraceCheckUtils]: 50: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,879 INFO L290 TraceCheckUtils]: 51: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,879 INFO L290 TraceCheckUtils]: 52: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,879 INFO L290 TraceCheckUtils]: 53: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,880 INFO L290 TraceCheckUtils]: 54: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,880 INFO L290 TraceCheckUtils]: 55: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,881 INFO L290 TraceCheckUtils]: 56: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,881 INFO L290 TraceCheckUtils]: 57: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,881 INFO L290 TraceCheckUtils]: 58: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,882 INFO L290 TraceCheckUtils]: 59: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,882 INFO L290 TraceCheckUtils]: 60: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,882 INFO L290 TraceCheckUtils]: 61: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,883 INFO L290 TraceCheckUtils]: 62: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,883 INFO L290 TraceCheckUtils]: 63: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,883 INFO L290 TraceCheckUtils]: 64: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,884 INFO L290 TraceCheckUtils]: 65: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,884 INFO L290 TraceCheckUtils]: 66: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,884 INFO L290 TraceCheckUtils]: 67: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,885 INFO L290 TraceCheckUtils]: 68: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,885 INFO L290 TraceCheckUtils]: 69: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,885 INFO L290 TraceCheckUtils]: 70: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,886 INFO L290 TraceCheckUtils]: 71: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,886 INFO L290 TraceCheckUtils]: 72: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,886 INFO L290 TraceCheckUtils]: 73: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,887 INFO L290 TraceCheckUtils]: 74: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,887 INFO L290 TraceCheckUtils]: 75: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,887 INFO L290 TraceCheckUtils]: 76: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,888 INFO L290 TraceCheckUtils]: 77: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,888 INFO L290 TraceCheckUtils]: 78: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,888 INFO L290 TraceCheckUtils]: 79: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,888 INFO L290 TraceCheckUtils]: 80: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,889 INFO L290 TraceCheckUtils]: 81: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,889 INFO L290 TraceCheckUtils]: 82: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,889 INFO L290 TraceCheckUtils]: 83: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,890 INFO L290 TraceCheckUtils]: 84: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,890 INFO L290 TraceCheckUtils]: 85: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,890 INFO L290 TraceCheckUtils]: 86: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,891 INFO L290 TraceCheckUtils]: 87: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,891 INFO L290 TraceCheckUtils]: 88: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,891 INFO L290 TraceCheckUtils]: 89: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,892 INFO L290 TraceCheckUtils]: 90: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,892 INFO L290 TraceCheckUtils]: 91: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,892 INFO L290 TraceCheckUtils]: 92: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,892 INFO L290 TraceCheckUtils]: 93: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,893 INFO L290 TraceCheckUtils]: 94: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,893 INFO L290 TraceCheckUtils]: 95: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,893 INFO L290 TraceCheckUtils]: 96: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,894 INFO L290 TraceCheckUtils]: 97: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,894 INFO L290 TraceCheckUtils]: 98: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,894 INFO L290 TraceCheckUtils]: 99: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,895 INFO L290 TraceCheckUtils]: 100: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,895 INFO L290 TraceCheckUtils]: 101: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,895 INFO L290 TraceCheckUtils]: 102: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {26904#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:27,895 INFO L290 TraceCheckUtils]: 103: Hoare triple {26904#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {26903#false} is VALID [2022-02-21 04:24:27,896 INFO L290 TraceCheckUtils]: 104: Hoare triple {26903#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,896 INFO L290 TraceCheckUtils]: 105: Hoare triple {26903#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,896 INFO L290 TraceCheckUtils]: 106: Hoare triple {26903#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,896 INFO L290 TraceCheckUtils]: 107: Hoare triple {26903#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,896 INFO L290 TraceCheckUtils]: 108: Hoare triple {26903#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,896 INFO L290 TraceCheckUtils]: 109: Hoare triple {26903#false} assume 1 == ~E_1~0;~E_1~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,896 INFO L290 TraceCheckUtils]: 110: Hoare triple {26903#false} assume 1 == ~E_2~0;~E_2~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,896 INFO L290 TraceCheckUtils]: 111: Hoare triple {26903#false} assume !(1 == ~E_3~0); {26903#false} is VALID [2022-02-21 04:24:27,896 INFO L290 TraceCheckUtils]: 112: Hoare triple {26903#false} assume 1 == ~E_4~0;~E_4~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,897 INFO L290 TraceCheckUtils]: 113: Hoare triple {26903#false} assume 1 == ~E_5~0;~E_5~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,897 INFO L290 TraceCheckUtils]: 114: Hoare triple {26903#false} assume 1 == ~E_6~0;~E_6~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,897 INFO L290 TraceCheckUtils]: 115: Hoare triple {26903#false} assume 1 == ~E_7~0;~E_7~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,897 INFO L290 TraceCheckUtils]: 116: Hoare triple {26903#false} assume 1 == ~E_8~0;~E_8~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,897 INFO L290 TraceCheckUtils]: 117: Hoare triple {26903#false} assume 1 == ~E_9~0;~E_9~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,897 INFO L290 TraceCheckUtils]: 118: Hoare triple {26903#false} assume 1 == ~E_10~0;~E_10~0 := 2; {26903#false} is VALID [2022-02-21 04:24:27,897 INFO L290 TraceCheckUtils]: 119: Hoare triple {26903#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {26903#false} is VALID [2022-02-21 04:24:27,897 INFO L290 TraceCheckUtils]: 120: Hoare triple {26903#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {26903#false} is VALID [2022-02-21 04:24:27,897 INFO L290 TraceCheckUtils]: 121: Hoare triple {26903#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {26903#false} is VALID [2022-02-21 04:24:27,898 INFO L290 TraceCheckUtils]: 122: Hoare triple {26903#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {26903#false} is VALID [2022-02-21 04:24:27,898 INFO L290 TraceCheckUtils]: 123: Hoare triple {26903#false} assume !(0 == start_simulation_~tmp~3#1); {26903#false} is VALID [2022-02-21 04:24:27,898 INFO L290 TraceCheckUtils]: 124: Hoare triple {26903#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {26903#false} is VALID [2022-02-21 04:24:27,898 INFO L290 TraceCheckUtils]: 125: Hoare triple {26903#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {26903#false} is VALID [2022-02-21 04:24:27,898 INFO L290 TraceCheckUtils]: 126: Hoare triple {26903#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {26903#false} is VALID [2022-02-21 04:24:27,898 INFO L290 TraceCheckUtils]: 127: Hoare triple {26903#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {26903#false} is VALID [2022-02-21 04:24:27,898 INFO L290 TraceCheckUtils]: 128: Hoare triple {26903#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {26903#false} is VALID [2022-02-21 04:24:27,898 INFO L290 TraceCheckUtils]: 129: Hoare triple {26903#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {26903#false} is VALID [2022-02-21 04:24:27,898 INFO L290 TraceCheckUtils]: 130: Hoare triple {26903#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {26903#false} is VALID [2022-02-21 04:24:27,899 INFO L290 TraceCheckUtils]: 131: Hoare triple {26903#false} assume !(0 != start_simulation_~tmp___0~1#1); {26903#false} is VALID [2022-02-21 04:24:27,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:27,899 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:27,899 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822955302] [2022-02-21 04:24:27,899 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822955302] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:27,900 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:27,900 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:27,900 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [291367476] [2022-02-21 04:24:27,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:27,901 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:27,901 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:27,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:27,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:27,901 INFO L87 Difference]: Start difference. First operand 1278 states and 1897 transitions. cyclomatic complexity: 620 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,509 INFO L93 Difference]: Finished difference Result 1278 states and 1896 transitions. [2022-02-21 04:24:28,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:28,510 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,596 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:28,598 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1896 transitions. [2022-02-21 04:24:28,634 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:28,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1896 transitions. [2022-02-21 04:24:28,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-02-21 04:24:28,671 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-02-21 04:24:28,671 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1896 transitions. [2022-02-21 04:24:28,672 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:28,672 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2022-02-21 04:24:28,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1896 transitions. [2022-02-21 04:24:28,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-02-21 04:24:28,691 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:28,693 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1278 states and 1896 transitions. Second operand has 1278 states, 1278 states have (on average 1.483568075117371) internal successors, (1896), 1277 states have internal predecessors, (1896), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,694 INFO L74 IsIncluded]: Start isIncluded. First operand 1278 states and 1896 transitions. Second operand has 1278 states, 1278 states have (on average 1.483568075117371) internal successors, (1896), 1277 states have internal predecessors, (1896), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,695 INFO L87 Difference]: Start difference. First operand 1278 states and 1896 transitions. Second operand has 1278 states, 1278 states have (on average 1.483568075117371) internal successors, (1896), 1277 states have internal predecessors, (1896), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,731 INFO L93 Difference]: Finished difference Result 1278 states and 1896 transitions. [2022-02-21 04:24:28,732 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1896 transitions. [2022-02-21 04:24:28,733 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:28,733 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:28,735 INFO L74 IsIncluded]: Start isIncluded. First operand has 1278 states, 1278 states have (on average 1.483568075117371) internal successors, (1896), 1277 states have internal predecessors, (1896), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1896 transitions. [2022-02-21 04:24:28,736 INFO L87 Difference]: Start difference. First operand has 1278 states, 1278 states have (on average 1.483568075117371) internal successors, (1896), 1277 states have internal predecessors, (1896), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1896 transitions. [2022-02-21 04:24:28,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,772 INFO L93 Difference]: Finished difference Result 1278 states and 1896 transitions. [2022-02-21 04:24:28,772 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1896 transitions. [2022-02-21 04:24:28,774 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:28,774 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:28,774 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:28,774 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:28,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.483568075117371) internal successors, (1896), 1277 states have internal predecessors, (1896), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1896 transitions. [2022-02-21 04:24:28,811 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2022-02-21 04:24:28,811 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1896 transitions. [2022-02-21 04:24:28,811 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:28,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1896 transitions. [2022-02-21 04:24:28,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:28,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:28,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:28,815 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:28,815 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:28,816 INFO L791 eck$LassoCheckResult]: Stem: 29164#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 29165#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 29440#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29428#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29429#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 29449#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29450#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28733#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28451#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28452#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29358#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29359#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29344#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29345#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29380#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28503#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28504#L1006 assume !(0 == ~M_E~0); 28354#L1006-2 assume !(0 == ~T1_E~0); 28355#L1011-1 assume !(0 == ~T2_E~0); 29402#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29417#L1021-1 assume !(0 == ~T4_E~0); 28234#L1026-1 assume !(0 == ~T5_E~0); 28235#L1031-1 assume !(0 == ~T6_E~0); 29110#L1036-1 assume !(0 == ~T7_E~0); 29106#L1041-1 assume !(0 == ~T8_E~0); 29107#L1046-1 assume !(0 == ~T9_E~0); 28536#L1051-1 assume !(0 == ~T10_E~0); 28537#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 29239#L1061-1 assume !(0 == ~E_2~0); 28455#L1066-1 assume !(0 == ~E_3~0); 28456#L1071-1 assume !(0 == ~E_4~0); 29218#L1076-1 assume !(0 == ~E_5~0); 28365#L1081-1 assume !(0 == ~E_6~0); 28366#L1086-1 assume !(0 == ~E_7~0); 28708#L1091-1 assume !(0 == ~E_8~0); 29394#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 29395#L1101-1 assume !(0 == ~E_10~0); 28770#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28771#L484 assume !(1 == ~m_pc~0); 28414#L484-2 is_master_triggered_~__retres1~0#1 := 0; 28413#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29029#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29313#L1245 assume !(0 != activate_threads_~tmp~1#1); 29314#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29098#L503 assume 1 == ~t1_pc~0; 29099#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29115#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29231#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28881#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 28264#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28265#L522 assume !(1 == ~t2_pc~0); 29065#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28468#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28469#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28939#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 29360#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29425#L541 assume 1 == ~t3_pc~0; 29014#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28830#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28645#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28646#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 29068#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29069#L560 assume !(1 == ~t4_pc~0); 28346#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28345#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28973#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28232#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 28233#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28517#L579 assume 1 == ~t5_pc~0; 28183#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28184#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28292#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28976#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 29415#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29437#L598 assume 1 == ~t6_pc~0; 28613#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28614#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28915#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29336#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 29147#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29089#L617 assume !(1 == ~t7_pc~0); 28586#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 28585#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28871#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28872#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28807#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28808#L636 assume 1 == ~t8_pc~0; 28970#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28971#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28772#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28773#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 28923#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28924#L655 assume !(1 == ~t9_pc~0); 28951#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 28952#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28565#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28566#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 29166#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29167#L674 assume 1 == ~t10_pc~0; 28341#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28342#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29427#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29458#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 28913#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28914#L1119 assume !(1 == ~M_E~0); 28437#L1119-2 assume !(1 == ~T1_E~0); 28438#L1124-1 assume !(1 == ~T2_E~0); 28256#L1129-1 assume !(1 == ~T3_E~0); 28257#L1134-1 assume !(1 == ~T4_E~0); 28567#L1139-1 assume !(1 == ~T5_E~0); 28568#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28803#L1149-1 assume !(1 == ~T7_E~0); 28432#L1154-1 assume !(1 == ~T8_E~0); 28433#L1159-1 assume !(1 == ~T9_E~0); 28520#L1164-1 assume !(1 == ~T10_E~0); 28942#L1169-1 assume !(1 == ~E_1~0); 28840#L1174-1 assume !(1 == ~E_2~0); 28627#L1179-1 assume !(1 == ~E_3~0); 28509#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 28510#L1189-1 assume !(1 == ~E_5~0); 28562#L1194-1 assume !(1 == ~E_6~0); 28686#L1199-1 assume !(1 == ~E_7~0); 28637#L1204-1 assume !(1 == ~E_8~0); 28638#L1209-1 assume !(1 == ~E_9~0); 29161#L1214-1 assume !(1 == ~E_10~0); 29162#L1219-1 assume { :end_inline_reset_delta_events } true; 28220#L1520-2 [2022-02-21 04:24:28,816 INFO L793 eck$LassoCheckResult]: Loop: 28220#L1520-2 assume !false; 28221#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28321#L981 assume !false; 28513#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29188#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28206#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29306#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 29356#L836 assume !(0 != eval_~tmp~0#1); 28798#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28799#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28794#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28795#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29265#L1011-3 assume !(0 == ~T2_E~0); 29266#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29305#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28986#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28987#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29233#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29234#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29294#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29295#L1051-3 assume !(0 == ~T10_E~0); 29235#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28531#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28532#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28535#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29406#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28318#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28319#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28371#L1091-3 assume !(0 == ~E_8~0); 28372#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29381#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29382#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29008#L484-33 assume 1 == ~m_pc~0; 29009#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 28928#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28929#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28226#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28227#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28695#L503-33 assume !(1 == ~t1_pc~0); 28696#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 29149#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29076#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28605#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28606#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29045#L522-33 assume 1 == ~t2_pc~0; 29046#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28359#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28360#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29154#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29063#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29064#L541-33 assume 1 == ~t3_pc~0; 28385#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28224#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28225#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29035#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29036#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29230#L560-33 assume 1 == ~t4_pc~0; 28935#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28296#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28297#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28555#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 29212#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28215#L579-33 assume 1 == ~t5_pc~0; 28216#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28462#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29421#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29090#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29091#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29119#L598-33 assume !(1 == ~t6_pc~0); 28893#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 28719#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28720#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28560#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 28561#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29370#L617-33 assume 1 == ~t7_pc~0; 29376#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28353#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29304#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29411#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29407#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28284#L636-33 assume !(1 == ~t8_pc~0); 28285#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 29204#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29205#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29430#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29195#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29196#L655-33 assume 1 == ~t9_pc~0; 29454#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28662#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28663#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29019#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29283#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28839#L674-33 assume 1 == ~t10_pc~0; 28714#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28715#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28576#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28577#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29054#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29431#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29438#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29442#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29452#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28601#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28602#L1139-3 assume !(1 == ~T5_E~0); 28832#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28833#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28975#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29245#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29246#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29413#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28717#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28718#L1179-3 assume !(1 == ~E_3~0); 29337#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28347#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28348#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28658#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28659#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28962#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28238#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28239#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29153#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28324#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28675#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 28676#L1539 assume !(0 == start_simulation_~tmp~3#1); 28768#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28944#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28751#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28884#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 28667#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28668#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29272#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 28769#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 28220#L1520-2 [2022-02-21 04:24:28,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:28,816 INFO L85 PathProgramCache]: Analyzing trace with hash 1042635949, now seen corresponding path program 1 times [2022-02-21 04:24:28,817 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:28,817 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954075654] [2022-02-21 04:24:28,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:28,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:28,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:28,833 INFO L290 TraceCheckUtils]: 0: Hoare triple {32020#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {32020#true} is VALID [2022-02-21 04:24:28,834 INFO L290 TraceCheckUtils]: 1: Hoare triple {32020#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {32022#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:28,834 INFO L290 TraceCheckUtils]: 2: Hoare triple {32022#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {32022#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:28,834 INFO L290 TraceCheckUtils]: 3: Hoare triple {32022#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {32022#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:28,835 INFO L290 TraceCheckUtils]: 4: Hoare triple {32022#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {32022#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:28,835 INFO L290 TraceCheckUtils]: 5: Hoare triple {32022#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {32022#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:28,835 INFO L290 TraceCheckUtils]: 6: Hoare triple {32022#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {32022#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:28,835 INFO L290 TraceCheckUtils]: 7: Hoare triple {32022#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {32022#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:28,836 INFO L290 TraceCheckUtils]: 8: Hoare triple {32022#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {32022#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:28,836 INFO L290 TraceCheckUtils]: 9: Hoare triple {32022#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {32022#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:28,836 INFO L290 TraceCheckUtils]: 10: Hoare triple {32022#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {32022#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:28,836 INFO L290 TraceCheckUtils]: 11: Hoare triple {32022#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {32021#false} is VALID [2022-02-21 04:24:28,837 INFO L290 TraceCheckUtils]: 12: Hoare triple {32021#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {32021#false} is VALID [2022-02-21 04:24:28,837 INFO L290 TraceCheckUtils]: 13: Hoare triple {32021#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {32021#false} is VALID [2022-02-21 04:24:28,837 INFO L290 TraceCheckUtils]: 14: Hoare triple {32021#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {32021#false} is VALID [2022-02-21 04:24:28,837 INFO L290 TraceCheckUtils]: 15: Hoare triple {32021#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {32021#false} is VALID [2022-02-21 04:24:28,837 INFO L290 TraceCheckUtils]: 16: Hoare triple {32021#false} assume !(0 == ~M_E~0); {32021#false} is VALID [2022-02-21 04:24:28,837 INFO L290 TraceCheckUtils]: 17: Hoare triple {32021#false} assume !(0 == ~T1_E~0); {32021#false} is VALID [2022-02-21 04:24:28,837 INFO L290 TraceCheckUtils]: 18: Hoare triple {32021#false} assume !(0 == ~T2_E~0); {32021#false} is VALID [2022-02-21 04:24:28,837 INFO L290 TraceCheckUtils]: 19: Hoare triple {32021#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {32021#false} is VALID [2022-02-21 04:24:28,837 INFO L290 TraceCheckUtils]: 20: Hoare triple {32021#false} assume !(0 == ~T4_E~0); {32021#false} is VALID [2022-02-21 04:24:28,838 INFO L290 TraceCheckUtils]: 21: Hoare triple {32021#false} assume !(0 == ~T5_E~0); {32021#false} is VALID [2022-02-21 04:24:28,838 INFO L290 TraceCheckUtils]: 22: Hoare triple {32021#false} assume !(0 == ~T6_E~0); {32021#false} is VALID [2022-02-21 04:24:28,838 INFO L290 TraceCheckUtils]: 23: Hoare triple {32021#false} assume !(0 == ~T7_E~0); {32021#false} is VALID [2022-02-21 04:24:28,838 INFO L290 TraceCheckUtils]: 24: Hoare triple {32021#false} assume !(0 == ~T8_E~0); {32021#false} is VALID [2022-02-21 04:24:28,838 INFO L290 TraceCheckUtils]: 25: Hoare triple {32021#false} assume !(0 == ~T9_E~0); {32021#false} is VALID [2022-02-21 04:24:28,838 INFO L290 TraceCheckUtils]: 26: Hoare triple {32021#false} assume !(0 == ~T10_E~0); {32021#false} is VALID [2022-02-21 04:24:28,838 INFO L290 TraceCheckUtils]: 27: Hoare triple {32021#false} assume 0 == ~E_1~0;~E_1~0 := 1; {32021#false} is VALID [2022-02-21 04:24:28,838 INFO L290 TraceCheckUtils]: 28: Hoare triple {32021#false} assume !(0 == ~E_2~0); {32021#false} is VALID [2022-02-21 04:24:28,838 INFO L290 TraceCheckUtils]: 29: Hoare triple {32021#false} assume !(0 == ~E_3~0); {32021#false} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 30: Hoare triple {32021#false} assume !(0 == ~E_4~0); {32021#false} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 31: Hoare triple {32021#false} assume !(0 == ~E_5~0); {32021#false} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 32: Hoare triple {32021#false} assume !(0 == ~E_6~0); {32021#false} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 33: Hoare triple {32021#false} assume !(0 == ~E_7~0); {32021#false} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 34: Hoare triple {32021#false} assume !(0 == ~E_8~0); {32021#false} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 35: Hoare triple {32021#false} assume 0 == ~E_9~0;~E_9~0 := 1; {32021#false} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 36: Hoare triple {32021#false} assume !(0 == ~E_10~0); {32021#false} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 37: Hoare triple {32021#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {32021#false} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 38: Hoare triple {32021#false} assume !(1 == ~m_pc~0); {32021#false} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 39: Hoare triple {32021#false} is_master_triggered_~__retres1~0#1 := 0; {32021#false} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 40: Hoare triple {32021#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {32021#false} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 41: Hoare triple {32021#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {32021#false} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 42: Hoare triple {32021#false} assume !(0 != activate_threads_~tmp~1#1); {32021#false} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 43: Hoare triple {32021#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {32021#false} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 44: Hoare triple {32021#false} assume 1 == ~t1_pc~0; {32021#false} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 45: Hoare triple {32021#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {32021#false} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 46: Hoare triple {32021#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {32021#false} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 47: Hoare triple {32021#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {32021#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 48: Hoare triple {32021#false} assume !(0 != activate_threads_~tmp___0~0#1); {32021#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 49: Hoare triple {32021#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {32021#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 50: Hoare triple {32021#false} assume !(1 == ~t2_pc~0); {32021#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 51: Hoare triple {32021#false} is_transmit2_triggered_~__retres1~2#1 := 0; {32021#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 52: Hoare triple {32021#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {32021#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 53: Hoare triple {32021#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {32021#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 54: Hoare triple {32021#false} assume !(0 != activate_threads_~tmp___1~0#1); {32021#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 55: Hoare triple {32021#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {32021#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 56: Hoare triple {32021#false} assume 1 == ~t3_pc~0; {32021#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 57: Hoare triple {32021#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {32021#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 58: Hoare triple {32021#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {32021#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 59: Hoare triple {32021#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {32021#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 60: Hoare triple {32021#false} assume !(0 != activate_threads_~tmp___2~0#1); {32021#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 61: Hoare triple {32021#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {32021#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 62: Hoare triple {32021#false} assume !(1 == ~t4_pc~0); {32021#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 63: Hoare triple {32021#false} is_transmit4_triggered_~__retres1~4#1 := 0; {32021#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 64: Hoare triple {32021#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {32021#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 65: Hoare triple {32021#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {32021#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 66: Hoare triple {32021#false} assume !(0 != activate_threads_~tmp___3~0#1); {32021#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 67: Hoare triple {32021#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {32021#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 68: Hoare triple {32021#false} assume 1 == ~t5_pc~0; {32021#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 69: Hoare triple {32021#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {32021#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 70: Hoare triple {32021#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {32021#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 71: Hoare triple {32021#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {32021#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 72: Hoare triple {32021#false} assume !(0 != activate_threads_~tmp___4~0#1); {32021#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 73: Hoare triple {32021#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {32021#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 74: Hoare triple {32021#false} assume 1 == ~t6_pc~0; {32021#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 75: Hoare triple {32021#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {32021#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 76: Hoare triple {32021#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {32021#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 77: Hoare triple {32021#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {32021#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 78: Hoare triple {32021#false} assume !(0 != activate_threads_~tmp___5~0#1); {32021#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 79: Hoare triple {32021#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {32021#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 80: Hoare triple {32021#false} assume !(1 == ~t7_pc~0); {32021#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 81: Hoare triple {32021#false} is_transmit7_triggered_~__retres1~7#1 := 0; {32021#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 82: Hoare triple {32021#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {32021#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 83: Hoare triple {32021#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {32021#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 84: Hoare triple {32021#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {32021#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 85: Hoare triple {32021#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {32021#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 86: Hoare triple {32021#false} assume 1 == ~t8_pc~0; {32021#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 87: Hoare triple {32021#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {32021#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 88: Hoare triple {32021#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {32021#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 89: Hoare triple {32021#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {32021#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 90: Hoare triple {32021#false} assume !(0 != activate_threads_~tmp___7~0#1); {32021#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 91: Hoare triple {32021#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {32021#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 92: Hoare triple {32021#false} assume !(1 == ~t9_pc~0); {32021#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 93: Hoare triple {32021#false} is_transmit9_triggered_~__retres1~9#1 := 0; {32021#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 94: Hoare triple {32021#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {32021#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 95: Hoare triple {32021#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {32021#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 96: Hoare triple {32021#false} assume !(0 != activate_threads_~tmp___8~0#1); {32021#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 97: Hoare triple {32021#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {32021#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 98: Hoare triple {32021#false} assume 1 == ~t10_pc~0; {32021#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 99: Hoare triple {32021#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {32021#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 100: Hoare triple {32021#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {32021#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 101: Hoare triple {32021#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {32021#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 102: Hoare triple {32021#false} assume !(0 != activate_threads_~tmp___9~0#1); {32021#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 103: Hoare triple {32021#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {32021#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 104: Hoare triple {32021#false} assume !(1 == ~M_E~0); {32021#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 105: Hoare triple {32021#false} assume !(1 == ~T1_E~0); {32021#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 106: Hoare triple {32021#false} assume !(1 == ~T2_E~0); {32021#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 107: Hoare triple {32021#false} assume !(1 == ~T3_E~0); {32021#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 108: Hoare triple {32021#false} assume !(1 == ~T4_E~0); {32021#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 109: Hoare triple {32021#false} assume !(1 == ~T5_E~0); {32021#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 110: Hoare triple {32021#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {32021#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 111: Hoare triple {32021#false} assume !(1 == ~T7_E~0); {32021#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 112: Hoare triple {32021#false} assume !(1 == ~T8_E~0); {32021#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 113: Hoare triple {32021#false} assume !(1 == ~T9_E~0); {32021#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 114: Hoare triple {32021#false} assume !(1 == ~T10_E~0); {32021#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 115: Hoare triple {32021#false} assume !(1 == ~E_1~0); {32021#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 116: Hoare triple {32021#false} assume !(1 == ~E_2~0); {32021#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 117: Hoare triple {32021#false} assume !(1 == ~E_3~0); {32021#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 118: Hoare triple {32021#false} assume 1 == ~E_4~0;~E_4~0 := 2; {32021#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 119: Hoare triple {32021#false} assume !(1 == ~E_5~0); {32021#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 120: Hoare triple {32021#false} assume !(1 == ~E_6~0); {32021#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 121: Hoare triple {32021#false} assume !(1 == ~E_7~0); {32021#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 122: Hoare triple {32021#false} assume !(1 == ~E_8~0); {32021#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 123: Hoare triple {32021#false} assume !(1 == ~E_9~0); {32021#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 124: Hoare triple {32021#false} assume !(1 == ~E_10~0); {32021#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 125: Hoare triple {32021#false} assume { :end_inline_reset_delta_events } true; {32021#false} is VALID [2022-02-21 04:24:28,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:28,850 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:28,850 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [954075654] [2022-02-21 04:24:28,850 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [954075654] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:28,850 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:28,850 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:28,850 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1971007579] [2022-02-21 04:24:28,851 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:28,851 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:28,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:28,851 INFO L85 PathProgramCache]: Analyzing trace with hash -1410939798, now seen corresponding path program 5 times [2022-02-21 04:24:28,851 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:28,851 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058907135] [2022-02-21 04:24:28,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:28,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:28,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:28,873 INFO L290 TraceCheckUtils]: 0: Hoare triple {32023#true} assume !false; {32023#true} is VALID [2022-02-21 04:24:28,874 INFO L290 TraceCheckUtils]: 1: Hoare triple {32023#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {32023#true} is VALID [2022-02-21 04:24:28,874 INFO L290 TraceCheckUtils]: 2: Hoare triple {32023#true} assume !false; {32023#true} is VALID [2022-02-21 04:24:28,874 INFO L290 TraceCheckUtils]: 3: Hoare triple {32023#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {32023#true} is VALID [2022-02-21 04:24:28,874 INFO L290 TraceCheckUtils]: 4: Hoare triple {32023#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {32023#true} is VALID [2022-02-21 04:24:28,874 INFO L290 TraceCheckUtils]: 5: Hoare triple {32023#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {32023#true} is VALID [2022-02-21 04:24:28,874 INFO L290 TraceCheckUtils]: 6: Hoare triple {32023#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {32023#true} is VALID [2022-02-21 04:24:28,874 INFO L290 TraceCheckUtils]: 7: Hoare triple {32023#true} assume !(0 != eval_~tmp~0#1); {32023#true} is VALID [2022-02-21 04:24:28,875 INFO L290 TraceCheckUtils]: 8: Hoare triple {32023#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {32023#true} is VALID [2022-02-21 04:24:28,875 INFO L290 TraceCheckUtils]: 9: Hoare triple {32023#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {32023#true} is VALID [2022-02-21 04:24:28,875 INFO L290 TraceCheckUtils]: 10: Hoare triple {32023#true} assume 0 == ~M_E~0;~M_E~0 := 1; {32023#true} is VALID [2022-02-21 04:24:28,875 INFO L290 TraceCheckUtils]: 11: Hoare triple {32023#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {32023#true} is VALID [2022-02-21 04:24:28,875 INFO L290 TraceCheckUtils]: 12: Hoare triple {32023#true} assume !(0 == ~T2_E~0); {32023#true} is VALID [2022-02-21 04:24:28,875 INFO L290 TraceCheckUtils]: 13: Hoare triple {32023#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {32023#true} is VALID [2022-02-21 04:24:28,875 INFO L290 TraceCheckUtils]: 14: Hoare triple {32023#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {32023#true} is VALID [2022-02-21 04:24:28,876 INFO L290 TraceCheckUtils]: 15: Hoare triple {32023#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,876 INFO L290 TraceCheckUtils]: 16: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,876 INFO L290 TraceCheckUtils]: 17: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,876 INFO L290 TraceCheckUtils]: 18: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,877 INFO L290 TraceCheckUtils]: 19: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,877 INFO L290 TraceCheckUtils]: 20: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,877 INFO L290 TraceCheckUtils]: 21: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,878 INFO L290 TraceCheckUtils]: 22: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,878 INFO L290 TraceCheckUtils]: 23: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,878 INFO L290 TraceCheckUtils]: 24: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,879 INFO L290 TraceCheckUtils]: 25: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,879 INFO L290 TraceCheckUtils]: 26: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,879 INFO L290 TraceCheckUtils]: 27: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,879 INFO L290 TraceCheckUtils]: 28: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,880 INFO L290 TraceCheckUtils]: 29: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,880 INFO L290 TraceCheckUtils]: 30: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,880 INFO L290 TraceCheckUtils]: 31: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,881 INFO L290 TraceCheckUtils]: 32: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,881 INFO L290 TraceCheckUtils]: 33: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,881 INFO L290 TraceCheckUtils]: 34: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,882 INFO L290 TraceCheckUtils]: 35: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,882 INFO L290 TraceCheckUtils]: 36: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,882 INFO L290 TraceCheckUtils]: 37: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,882 INFO L290 TraceCheckUtils]: 38: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,883 INFO L290 TraceCheckUtils]: 39: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,883 INFO L290 TraceCheckUtils]: 40: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,883 INFO L290 TraceCheckUtils]: 41: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,884 INFO L290 TraceCheckUtils]: 42: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,884 INFO L290 TraceCheckUtils]: 43: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,884 INFO L290 TraceCheckUtils]: 44: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,884 INFO L290 TraceCheckUtils]: 45: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,885 INFO L290 TraceCheckUtils]: 46: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,885 INFO L290 TraceCheckUtils]: 47: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,885 INFO L290 TraceCheckUtils]: 48: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,886 INFO L290 TraceCheckUtils]: 49: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,886 INFO L290 TraceCheckUtils]: 50: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,886 INFO L290 TraceCheckUtils]: 51: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,887 INFO L290 TraceCheckUtils]: 52: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,887 INFO L290 TraceCheckUtils]: 53: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,887 INFO L290 TraceCheckUtils]: 54: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,887 INFO L290 TraceCheckUtils]: 55: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,888 INFO L290 TraceCheckUtils]: 56: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,888 INFO L290 TraceCheckUtils]: 57: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,888 INFO L290 TraceCheckUtils]: 58: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,889 INFO L290 TraceCheckUtils]: 59: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,889 INFO L290 TraceCheckUtils]: 60: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,889 INFO L290 TraceCheckUtils]: 61: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,889 INFO L290 TraceCheckUtils]: 62: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,890 INFO L290 TraceCheckUtils]: 63: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,890 INFO L290 TraceCheckUtils]: 64: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,890 INFO L290 TraceCheckUtils]: 65: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,891 INFO L290 TraceCheckUtils]: 66: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,891 INFO L290 TraceCheckUtils]: 67: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,891 INFO L290 TraceCheckUtils]: 68: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,892 INFO L290 TraceCheckUtils]: 69: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,892 INFO L290 TraceCheckUtils]: 70: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,892 INFO L290 TraceCheckUtils]: 71: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,892 INFO L290 TraceCheckUtils]: 72: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,893 INFO L290 TraceCheckUtils]: 73: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,893 INFO L290 TraceCheckUtils]: 74: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,893 INFO L290 TraceCheckUtils]: 75: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,894 INFO L290 TraceCheckUtils]: 76: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,894 INFO L290 TraceCheckUtils]: 77: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,894 INFO L290 TraceCheckUtils]: 78: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,894 INFO L290 TraceCheckUtils]: 79: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,895 INFO L290 TraceCheckUtils]: 80: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,895 INFO L290 TraceCheckUtils]: 81: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,895 INFO L290 TraceCheckUtils]: 82: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,896 INFO L290 TraceCheckUtils]: 83: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,896 INFO L290 TraceCheckUtils]: 84: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,896 INFO L290 TraceCheckUtils]: 85: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,897 INFO L290 TraceCheckUtils]: 86: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,897 INFO L290 TraceCheckUtils]: 87: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,897 INFO L290 TraceCheckUtils]: 88: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,897 INFO L290 TraceCheckUtils]: 89: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,898 INFO L290 TraceCheckUtils]: 90: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,898 INFO L290 TraceCheckUtils]: 91: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,898 INFO L290 TraceCheckUtils]: 92: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,899 INFO L290 TraceCheckUtils]: 93: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,899 INFO L290 TraceCheckUtils]: 94: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,899 INFO L290 TraceCheckUtils]: 95: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,900 INFO L290 TraceCheckUtils]: 96: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,900 INFO L290 TraceCheckUtils]: 97: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,900 INFO L290 TraceCheckUtils]: 98: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,900 INFO L290 TraceCheckUtils]: 99: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,901 INFO L290 TraceCheckUtils]: 100: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,901 INFO L290 TraceCheckUtils]: 101: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,901 INFO L290 TraceCheckUtils]: 102: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {32025#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:28,902 INFO L290 TraceCheckUtils]: 103: Hoare triple {32025#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {32024#false} is VALID [2022-02-21 04:24:28,902 INFO L290 TraceCheckUtils]: 104: Hoare triple {32024#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,902 INFO L290 TraceCheckUtils]: 105: Hoare triple {32024#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,902 INFO L290 TraceCheckUtils]: 106: Hoare triple {32024#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,902 INFO L290 TraceCheckUtils]: 107: Hoare triple {32024#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,902 INFO L290 TraceCheckUtils]: 108: Hoare triple {32024#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,902 INFO L290 TraceCheckUtils]: 109: Hoare triple {32024#false} assume 1 == ~E_1~0;~E_1~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,902 INFO L290 TraceCheckUtils]: 110: Hoare triple {32024#false} assume 1 == ~E_2~0;~E_2~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,902 INFO L290 TraceCheckUtils]: 111: Hoare triple {32024#false} assume !(1 == ~E_3~0); {32024#false} is VALID [2022-02-21 04:24:28,903 INFO L290 TraceCheckUtils]: 112: Hoare triple {32024#false} assume 1 == ~E_4~0;~E_4~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,903 INFO L290 TraceCheckUtils]: 113: Hoare triple {32024#false} assume 1 == ~E_5~0;~E_5~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,903 INFO L290 TraceCheckUtils]: 114: Hoare triple {32024#false} assume 1 == ~E_6~0;~E_6~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,903 INFO L290 TraceCheckUtils]: 115: Hoare triple {32024#false} assume 1 == ~E_7~0;~E_7~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,903 INFO L290 TraceCheckUtils]: 116: Hoare triple {32024#false} assume 1 == ~E_8~0;~E_8~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,903 INFO L290 TraceCheckUtils]: 117: Hoare triple {32024#false} assume 1 == ~E_9~0;~E_9~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,903 INFO L290 TraceCheckUtils]: 118: Hoare triple {32024#false} assume 1 == ~E_10~0;~E_10~0 := 2; {32024#false} is VALID [2022-02-21 04:24:28,903 INFO L290 TraceCheckUtils]: 119: Hoare triple {32024#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {32024#false} is VALID [2022-02-21 04:24:28,903 INFO L290 TraceCheckUtils]: 120: Hoare triple {32024#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {32024#false} is VALID [2022-02-21 04:24:28,904 INFO L290 TraceCheckUtils]: 121: Hoare triple {32024#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {32024#false} is VALID [2022-02-21 04:24:28,904 INFO L290 TraceCheckUtils]: 122: Hoare triple {32024#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {32024#false} is VALID [2022-02-21 04:24:28,904 INFO L290 TraceCheckUtils]: 123: Hoare triple {32024#false} assume !(0 == start_simulation_~tmp~3#1); {32024#false} is VALID [2022-02-21 04:24:28,904 INFO L290 TraceCheckUtils]: 124: Hoare triple {32024#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {32024#false} is VALID [2022-02-21 04:24:28,904 INFO L290 TraceCheckUtils]: 125: Hoare triple {32024#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {32024#false} is VALID [2022-02-21 04:24:28,904 INFO L290 TraceCheckUtils]: 126: Hoare triple {32024#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {32024#false} is VALID [2022-02-21 04:24:28,904 INFO L290 TraceCheckUtils]: 127: Hoare triple {32024#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {32024#false} is VALID [2022-02-21 04:24:28,904 INFO L290 TraceCheckUtils]: 128: Hoare triple {32024#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {32024#false} is VALID [2022-02-21 04:24:28,905 INFO L290 TraceCheckUtils]: 129: Hoare triple {32024#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {32024#false} is VALID [2022-02-21 04:24:28,905 INFO L290 TraceCheckUtils]: 130: Hoare triple {32024#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {32024#false} is VALID [2022-02-21 04:24:28,905 INFO L290 TraceCheckUtils]: 131: Hoare triple {32024#false} assume !(0 != start_simulation_~tmp___0~1#1); {32024#false} is VALID [2022-02-21 04:24:28,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:28,905 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:28,905 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2058907135] [2022-02-21 04:24:28,906 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2058907135] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:28,906 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:28,906 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:28,906 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864870136] [2022-02-21 04:24:28,906 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:28,906 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:28,906 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:28,907 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:28,907 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:28,908 INFO L87 Difference]: Start difference. First operand 1278 states and 1896 transitions. cyclomatic complexity: 619 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:29,865 INFO L93 Difference]: Finished difference Result 1278 states and 1895 transitions. [2022-02-21 04:24:29,865 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:29,865 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:29,938 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:29,940 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1895 transitions. [2022-02-21 04:24:29,978 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:30,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1895 transitions. [2022-02-21 04:24:30,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-02-21 04:24:30,018 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-02-21 04:24:30,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1895 transitions. [2022-02-21 04:24:30,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:30,021 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2022-02-21 04:24:30,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1895 transitions. [2022-02-21 04:24:30,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-02-21 04:24:30,034 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:30,035 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1278 states and 1895 transitions. Second operand has 1278 states, 1278 states have (on average 1.4827856025039123) internal successors, (1895), 1277 states have internal predecessors, (1895), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,036 INFO L74 IsIncluded]: Start isIncluded. First operand 1278 states and 1895 transitions. Second operand has 1278 states, 1278 states have (on average 1.4827856025039123) internal successors, (1895), 1277 states have internal predecessors, (1895), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,037 INFO L87 Difference]: Start difference. First operand 1278 states and 1895 transitions. Second operand has 1278 states, 1278 states have (on average 1.4827856025039123) internal successors, (1895), 1277 states have internal predecessors, (1895), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,073 INFO L93 Difference]: Finished difference Result 1278 states and 1895 transitions. [2022-02-21 04:24:30,073 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1895 transitions. [2022-02-21 04:24:30,075 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:30,075 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:30,076 INFO L74 IsIncluded]: Start isIncluded. First operand has 1278 states, 1278 states have (on average 1.4827856025039123) internal successors, (1895), 1277 states have internal predecessors, (1895), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1895 transitions. [2022-02-21 04:24:30,077 INFO L87 Difference]: Start difference. First operand has 1278 states, 1278 states have (on average 1.4827856025039123) internal successors, (1895), 1277 states have internal predecessors, (1895), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1895 transitions. [2022-02-21 04:24:30,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,114 INFO L93 Difference]: Finished difference Result 1278 states and 1895 transitions. [2022-02-21 04:24:30,114 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1895 transitions. [2022-02-21 04:24:30,115 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:30,115 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:30,115 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:30,116 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:30,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4827856025039123) internal successors, (1895), 1277 states have internal predecessors, (1895), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1895 transitions. [2022-02-21 04:24:30,161 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2022-02-21 04:24:30,161 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1895 transitions. [2022-02-21 04:24:30,161 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:30,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1895 transitions. [2022-02-21 04:24:30,164 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:30,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:30,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:30,166 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:30,166 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:30,166 INFO L791 eck$LassoCheckResult]: Stem: 34286#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 34287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 34561#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34549#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34550#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 34570#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34571#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33854#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33572#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33573#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34479#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34480#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34465#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 34466#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34501#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33626#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33627#L1006 assume !(0 == ~M_E~0); 33475#L1006-2 assume !(0 == ~T1_E~0); 33476#L1011-1 assume !(0 == ~T2_E~0); 34523#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34538#L1021-1 assume !(0 == ~T4_E~0); 33357#L1026-1 assume !(0 == ~T5_E~0); 33358#L1031-1 assume !(0 == ~T6_E~0); 34231#L1036-1 assume !(0 == ~T7_E~0); 34227#L1041-1 assume !(0 == ~T8_E~0); 34228#L1046-1 assume !(0 == ~T9_E~0); 33657#L1051-1 assume !(0 == ~T10_E~0); 33658#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 34360#L1061-1 assume !(0 == ~E_2~0); 33576#L1066-1 assume !(0 == ~E_3~0); 33577#L1071-1 assume !(0 == ~E_4~0); 34339#L1076-1 assume !(0 == ~E_5~0); 33486#L1081-1 assume !(0 == ~E_6~0); 33487#L1086-1 assume !(0 == ~E_7~0); 33829#L1091-1 assume !(0 == ~E_8~0); 34516#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 34517#L1101-1 assume !(0 == ~E_10~0); 33891#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33892#L484 assume !(1 == ~m_pc~0); 33535#L484-2 is_master_triggered_~__retres1~0#1 := 0; 33534#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34150#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34434#L1245 assume !(0 != activate_threads_~tmp~1#1); 34435#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34219#L503 assume 1 == ~t1_pc~0; 34220#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34237#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34352#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34005#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 33385#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33386#L522 assume !(1 == ~t2_pc~0); 34186#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33589#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33590#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34060#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 34481#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34546#L541 assume 1 == ~t3_pc~0; 34135#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33951#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33766#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33767#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 34189#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34190#L560 assume !(1 == ~t4_pc~0); 33469#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33468#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34094#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33353#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 33354#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33640#L579 assume 1 == ~t5_pc~0; 33304#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33305#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33413#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34097#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 34537#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34558#L598 assume 1 == ~t6_pc~0; 33734#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33735#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34037#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34457#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 34268#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34210#L617 assume !(1 == ~t7_pc~0); 33707#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33706#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33992#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33993#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33928#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33929#L636 assume 1 == ~t8_pc~0; 34091#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34092#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33893#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33894#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 34044#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34045#L655 assume !(1 == ~t9_pc~0); 34074#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 34075#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33686#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33687#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 34288#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34289#L674 assume 1 == ~t10_pc~0; 33462#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33463#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34548#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34579#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 34034#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34035#L1119 assume !(1 == ~M_E~0); 33558#L1119-2 assume !(1 == ~T1_E~0); 33559#L1124-1 assume !(1 == ~T2_E~0); 33377#L1129-1 assume !(1 == ~T3_E~0); 33378#L1134-1 assume !(1 == ~T4_E~0); 33691#L1139-1 assume !(1 == ~T5_E~0); 33692#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33924#L1149-1 assume !(1 == ~T7_E~0); 33553#L1154-1 assume !(1 == ~T8_E~0); 33554#L1159-1 assume !(1 == ~T9_E~0); 33641#L1164-1 assume !(1 == ~T10_E~0); 34063#L1169-1 assume !(1 == ~E_1~0); 33961#L1174-1 assume !(1 == ~E_2~0); 33748#L1179-1 assume !(1 == ~E_3~0); 33630#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33631#L1189-1 assume !(1 == ~E_5~0); 33684#L1194-1 assume !(1 == ~E_6~0); 33807#L1199-1 assume !(1 == ~E_7~0); 33758#L1204-1 assume !(1 == ~E_8~0); 33759#L1209-1 assume !(1 == ~E_9~0); 34282#L1214-1 assume !(1 == ~E_10~0); 34283#L1219-1 assume { :end_inline_reset_delta_events } true; 33341#L1520-2 [2022-02-21 04:24:30,167 INFO L793 eck$LassoCheckResult]: Loop: 33341#L1520-2 assume !false; 33342#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33445#L981 assume !false; 33637#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 34309#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 33327#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 34427#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34477#L836 assume !(0 != eval_~tmp~0#1); 33919#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33920#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33915#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33916#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34386#L1011-3 assume !(0 == ~T2_E~0); 34387#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34426#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34109#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34110#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34354#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34355#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 34417#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34418#L1051-3 assume !(0 == ~T10_E~0); 34356#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33654#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33655#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33656#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34527#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33439#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33440#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33494#L1091-3 assume !(0 == ~E_8~0); 33495#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34502#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34503#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34129#L484-33 assume 1 == ~m_pc~0; 34130#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34049#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34050#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33347#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33348#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33819#L503-33 assume !(1 == ~t1_pc~0); 33820#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 34270#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34199#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33726#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33727#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34166#L522-33 assume 1 == ~t2_pc~0; 34167#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33482#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33483#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34276#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34184#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34185#L541-33 assume 1 == ~t3_pc~0; 33506#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33345#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33346#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34156#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34157#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34351#L560-33 assume 1 == ~t4_pc~0; 34056#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33417#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33418#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33674#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 34333#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33333#L579-33 assume 1 == ~t5_pc~0; 33334#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33582#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34542#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34211#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34212#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34236#L598-33 assume !(1 == ~t6_pc~0); 34009#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 33840#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33841#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33681#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33682#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34491#L617-33 assume 1 == ~t7_pc~0; 34497#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33474#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34425#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34532#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34528#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33405#L636-33 assume !(1 == ~t8_pc~0); 33406#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 34325#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34326#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34551#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 34314#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34315#L655-33 assume !(1 == ~t9_pc~0); 34576#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 33781#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33782#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34140#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34404#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33960#L674-33 assume 1 == ~t10_pc~0; 33835#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33836#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33697#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33698#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34175#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34552#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34559#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34562#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34573#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33719#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33720#L1139-3 assume !(1 == ~T5_E~0); 33953#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33954#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34096#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34366#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34367#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34533#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33838#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33839#L1179-3 assume !(1 == ~E_3~0); 34458#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33465#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33466#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33779#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33780#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34083#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 33359#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33360#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 34273#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 33442#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 33796#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 33797#L1539 assume !(0 == start_simulation_~tmp~3#1); 33889#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 34065#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 33872#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 34004#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 33788#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33789#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34393#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 33890#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 33341#L1520-2 [2022-02-21 04:24:30,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:30,168 INFO L85 PathProgramCache]: Analyzing trace with hash -886296277, now seen corresponding path program 1 times [2022-02-21 04:24:30,168 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:30,168 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [915057836] [2022-02-21 04:24:30,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:30,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:30,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:30,191 INFO L290 TraceCheckUtils]: 0: Hoare triple {37141#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {37141#true} is VALID [2022-02-21 04:24:30,192 INFO L290 TraceCheckUtils]: 1: Hoare triple {37141#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {37143#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:30,192 INFO L290 TraceCheckUtils]: 2: Hoare triple {37143#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {37143#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:30,193 INFO L290 TraceCheckUtils]: 3: Hoare triple {37143#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {37143#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:30,193 INFO L290 TraceCheckUtils]: 4: Hoare triple {37143#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {37143#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:30,193 INFO L290 TraceCheckUtils]: 5: Hoare triple {37143#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {37143#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:30,194 INFO L290 TraceCheckUtils]: 6: Hoare triple {37143#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {37143#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:30,194 INFO L290 TraceCheckUtils]: 7: Hoare triple {37143#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {37143#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:30,194 INFO L290 TraceCheckUtils]: 8: Hoare triple {37143#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {37143#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:30,195 INFO L290 TraceCheckUtils]: 9: Hoare triple {37143#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {37143#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:30,195 INFO L290 TraceCheckUtils]: 10: Hoare triple {37143#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {37143#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:30,195 INFO L290 TraceCheckUtils]: 11: Hoare triple {37143#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {37143#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:30,196 INFO L290 TraceCheckUtils]: 12: Hoare triple {37143#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {37142#false} is VALID [2022-02-21 04:24:30,196 INFO L290 TraceCheckUtils]: 13: Hoare triple {37142#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {37142#false} is VALID [2022-02-21 04:24:30,196 INFO L290 TraceCheckUtils]: 14: Hoare triple {37142#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {37142#false} is VALID [2022-02-21 04:24:30,196 INFO L290 TraceCheckUtils]: 15: Hoare triple {37142#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {37142#false} is VALID [2022-02-21 04:24:30,196 INFO L290 TraceCheckUtils]: 16: Hoare triple {37142#false} assume !(0 == ~M_E~0); {37142#false} is VALID [2022-02-21 04:24:30,197 INFO L290 TraceCheckUtils]: 17: Hoare triple {37142#false} assume !(0 == ~T1_E~0); {37142#false} is VALID [2022-02-21 04:24:30,197 INFO L290 TraceCheckUtils]: 18: Hoare triple {37142#false} assume !(0 == ~T2_E~0); {37142#false} is VALID [2022-02-21 04:24:30,197 INFO L290 TraceCheckUtils]: 19: Hoare triple {37142#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {37142#false} is VALID [2022-02-21 04:24:30,197 INFO L290 TraceCheckUtils]: 20: Hoare triple {37142#false} assume !(0 == ~T4_E~0); {37142#false} is VALID [2022-02-21 04:24:30,197 INFO L290 TraceCheckUtils]: 21: Hoare triple {37142#false} assume !(0 == ~T5_E~0); {37142#false} is VALID [2022-02-21 04:24:30,197 INFO L290 TraceCheckUtils]: 22: Hoare triple {37142#false} assume !(0 == ~T6_E~0); {37142#false} is VALID [2022-02-21 04:24:30,197 INFO L290 TraceCheckUtils]: 23: Hoare triple {37142#false} assume !(0 == ~T7_E~0); {37142#false} is VALID [2022-02-21 04:24:30,198 INFO L290 TraceCheckUtils]: 24: Hoare triple {37142#false} assume !(0 == ~T8_E~0); {37142#false} is VALID [2022-02-21 04:24:30,198 INFO L290 TraceCheckUtils]: 25: Hoare triple {37142#false} assume !(0 == ~T9_E~0); {37142#false} is VALID [2022-02-21 04:24:30,198 INFO L290 TraceCheckUtils]: 26: Hoare triple {37142#false} assume !(0 == ~T10_E~0); {37142#false} is VALID [2022-02-21 04:24:30,198 INFO L290 TraceCheckUtils]: 27: Hoare triple {37142#false} assume 0 == ~E_1~0;~E_1~0 := 1; {37142#false} is VALID [2022-02-21 04:24:30,198 INFO L290 TraceCheckUtils]: 28: Hoare triple {37142#false} assume !(0 == ~E_2~0); {37142#false} is VALID [2022-02-21 04:24:30,198 INFO L290 TraceCheckUtils]: 29: Hoare triple {37142#false} assume !(0 == ~E_3~0); {37142#false} is VALID [2022-02-21 04:24:30,198 INFO L290 TraceCheckUtils]: 30: Hoare triple {37142#false} assume !(0 == ~E_4~0); {37142#false} is VALID [2022-02-21 04:24:30,198 INFO L290 TraceCheckUtils]: 31: Hoare triple {37142#false} assume !(0 == ~E_5~0); {37142#false} is VALID [2022-02-21 04:24:30,199 INFO L290 TraceCheckUtils]: 32: Hoare triple {37142#false} assume !(0 == ~E_6~0); {37142#false} is VALID [2022-02-21 04:24:30,199 INFO L290 TraceCheckUtils]: 33: Hoare triple {37142#false} assume !(0 == ~E_7~0); {37142#false} is VALID [2022-02-21 04:24:30,199 INFO L290 TraceCheckUtils]: 34: Hoare triple {37142#false} assume !(0 == ~E_8~0); {37142#false} is VALID [2022-02-21 04:24:30,199 INFO L290 TraceCheckUtils]: 35: Hoare triple {37142#false} assume 0 == ~E_9~0;~E_9~0 := 1; {37142#false} is VALID [2022-02-21 04:24:30,199 INFO L290 TraceCheckUtils]: 36: Hoare triple {37142#false} assume !(0 == ~E_10~0); {37142#false} is VALID [2022-02-21 04:24:30,199 INFO L290 TraceCheckUtils]: 37: Hoare triple {37142#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37142#false} is VALID [2022-02-21 04:24:30,199 INFO L290 TraceCheckUtils]: 38: Hoare triple {37142#false} assume !(1 == ~m_pc~0); {37142#false} is VALID [2022-02-21 04:24:30,199 INFO L290 TraceCheckUtils]: 39: Hoare triple {37142#false} is_master_triggered_~__retres1~0#1 := 0; {37142#false} is VALID [2022-02-21 04:24:30,200 INFO L290 TraceCheckUtils]: 40: Hoare triple {37142#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37142#false} is VALID [2022-02-21 04:24:30,200 INFO L290 TraceCheckUtils]: 41: Hoare triple {37142#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {37142#false} is VALID [2022-02-21 04:24:30,200 INFO L290 TraceCheckUtils]: 42: Hoare triple {37142#false} assume !(0 != activate_threads_~tmp~1#1); {37142#false} is VALID [2022-02-21 04:24:30,200 INFO L290 TraceCheckUtils]: 43: Hoare triple {37142#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37142#false} is VALID [2022-02-21 04:24:30,200 INFO L290 TraceCheckUtils]: 44: Hoare triple {37142#false} assume 1 == ~t1_pc~0; {37142#false} is VALID [2022-02-21 04:24:30,200 INFO L290 TraceCheckUtils]: 45: Hoare triple {37142#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {37142#false} is VALID [2022-02-21 04:24:30,200 INFO L290 TraceCheckUtils]: 46: Hoare triple {37142#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37142#false} is VALID [2022-02-21 04:24:30,201 INFO L290 TraceCheckUtils]: 47: Hoare triple {37142#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {37142#false} is VALID [2022-02-21 04:24:30,201 INFO L290 TraceCheckUtils]: 48: Hoare triple {37142#false} assume !(0 != activate_threads_~tmp___0~0#1); {37142#false} is VALID [2022-02-21 04:24:30,201 INFO L290 TraceCheckUtils]: 49: Hoare triple {37142#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37142#false} is VALID [2022-02-21 04:24:30,201 INFO L290 TraceCheckUtils]: 50: Hoare triple {37142#false} assume !(1 == ~t2_pc~0); {37142#false} is VALID [2022-02-21 04:24:30,201 INFO L290 TraceCheckUtils]: 51: Hoare triple {37142#false} is_transmit2_triggered_~__retres1~2#1 := 0; {37142#false} is VALID [2022-02-21 04:24:30,201 INFO L290 TraceCheckUtils]: 52: Hoare triple {37142#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37142#false} is VALID [2022-02-21 04:24:30,201 INFO L290 TraceCheckUtils]: 53: Hoare triple {37142#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {37142#false} is VALID [2022-02-21 04:24:30,201 INFO L290 TraceCheckUtils]: 54: Hoare triple {37142#false} assume !(0 != activate_threads_~tmp___1~0#1); {37142#false} is VALID [2022-02-21 04:24:30,202 INFO L290 TraceCheckUtils]: 55: Hoare triple {37142#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {37142#false} is VALID [2022-02-21 04:24:30,202 INFO L290 TraceCheckUtils]: 56: Hoare triple {37142#false} assume 1 == ~t3_pc~0; {37142#false} is VALID [2022-02-21 04:24:30,202 INFO L290 TraceCheckUtils]: 57: Hoare triple {37142#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {37142#false} is VALID [2022-02-21 04:24:30,202 INFO L290 TraceCheckUtils]: 58: Hoare triple {37142#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {37142#false} is VALID [2022-02-21 04:24:30,202 INFO L290 TraceCheckUtils]: 59: Hoare triple {37142#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {37142#false} is VALID [2022-02-21 04:24:30,202 INFO L290 TraceCheckUtils]: 60: Hoare triple {37142#false} assume !(0 != activate_threads_~tmp___2~0#1); {37142#false} is VALID [2022-02-21 04:24:30,202 INFO L290 TraceCheckUtils]: 61: Hoare triple {37142#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {37142#false} is VALID [2022-02-21 04:24:30,202 INFO L290 TraceCheckUtils]: 62: Hoare triple {37142#false} assume !(1 == ~t4_pc~0); {37142#false} is VALID [2022-02-21 04:24:30,203 INFO L290 TraceCheckUtils]: 63: Hoare triple {37142#false} is_transmit4_triggered_~__retres1~4#1 := 0; {37142#false} is VALID [2022-02-21 04:24:30,203 INFO L290 TraceCheckUtils]: 64: Hoare triple {37142#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {37142#false} is VALID [2022-02-21 04:24:30,203 INFO L290 TraceCheckUtils]: 65: Hoare triple {37142#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {37142#false} is VALID [2022-02-21 04:24:30,203 INFO L290 TraceCheckUtils]: 66: Hoare triple {37142#false} assume !(0 != activate_threads_~tmp___3~0#1); {37142#false} is VALID [2022-02-21 04:24:30,203 INFO L290 TraceCheckUtils]: 67: Hoare triple {37142#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {37142#false} is VALID [2022-02-21 04:24:30,203 INFO L290 TraceCheckUtils]: 68: Hoare triple {37142#false} assume 1 == ~t5_pc~0; {37142#false} is VALID [2022-02-21 04:24:30,203 INFO L290 TraceCheckUtils]: 69: Hoare triple {37142#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {37142#false} is VALID [2022-02-21 04:24:30,204 INFO L290 TraceCheckUtils]: 70: Hoare triple {37142#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {37142#false} is VALID [2022-02-21 04:24:30,204 INFO L290 TraceCheckUtils]: 71: Hoare triple {37142#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {37142#false} is VALID [2022-02-21 04:24:30,204 INFO L290 TraceCheckUtils]: 72: Hoare triple {37142#false} assume !(0 != activate_threads_~tmp___4~0#1); {37142#false} is VALID [2022-02-21 04:24:30,204 INFO L290 TraceCheckUtils]: 73: Hoare triple {37142#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {37142#false} is VALID [2022-02-21 04:24:30,204 INFO L290 TraceCheckUtils]: 74: Hoare triple {37142#false} assume 1 == ~t6_pc~0; {37142#false} is VALID [2022-02-21 04:24:30,204 INFO L290 TraceCheckUtils]: 75: Hoare triple {37142#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {37142#false} is VALID [2022-02-21 04:24:30,204 INFO L290 TraceCheckUtils]: 76: Hoare triple {37142#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {37142#false} is VALID [2022-02-21 04:24:30,204 INFO L290 TraceCheckUtils]: 77: Hoare triple {37142#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {37142#false} is VALID [2022-02-21 04:24:30,205 INFO L290 TraceCheckUtils]: 78: Hoare triple {37142#false} assume !(0 != activate_threads_~tmp___5~0#1); {37142#false} is VALID [2022-02-21 04:24:30,205 INFO L290 TraceCheckUtils]: 79: Hoare triple {37142#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {37142#false} is VALID [2022-02-21 04:24:30,205 INFO L290 TraceCheckUtils]: 80: Hoare triple {37142#false} assume !(1 == ~t7_pc~0); {37142#false} is VALID [2022-02-21 04:24:30,205 INFO L290 TraceCheckUtils]: 81: Hoare triple {37142#false} is_transmit7_triggered_~__retres1~7#1 := 0; {37142#false} is VALID [2022-02-21 04:24:30,205 INFO L290 TraceCheckUtils]: 82: Hoare triple {37142#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {37142#false} is VALID [2022-02-21 04:24:30,205 INFO L290 TraceCheckUtils]: 83: Hoare triple {37142#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {37142#false} is VALID [2022-02-21 04:24:30,205 INFO L290 TraceCheckUtils]: 84: Hoare triple {37142#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {37142#false} is VALID [2022-02-21 04:24:30,205 INFO L290 TraceCheckUtils]: 85: Hoare triple {37142#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {37142#false} is VALID [2022-02-21 04:24:30,206 INFO L290 TraceCheckUtils]: 86: Hoare triple {37142#false} assume 1 == ~t8_pc~0; {37142#false} is VALID [2022-02-21 04:24:30,206 INFO L290 TraceCheckUtils]: 87: Hoare triple {37142#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {37142#false} is VALID [2022-02-21 04:24:30,206 INFO L290 TraceCheckUtils]: 88: Hoare triple {37142#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {37142#false} is VALID [2022-02-21 04:24:30,206 INFO L290 TraceCheckUtils]: 89: Hoare triple {37142#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {37142#false} is VALID [2022-02-21 04:24:30,206 INFO L290 TraceCheckUtils]: 90: Hoare triple {37142#false} assume !(0 != activate_threads_~tmp___7~0#1); {37142#false} is VALID [2022-02-21 04:24:30,206 INFO L290 TraceCheckUtils]: 91: Hoare triple {37142#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {37142#false} is VALID [2022-02-21 04:24:30,206 INFO L290 TraceCheckUtils]: 92: Hoare triple {37142#false} assume !(1 == ~t9_pc~0); {37142#false} is VALID [2022-02-21 04:24:30,206 INFO L290 TraceCheckUtils]: 93: Hoare triple {37142#false} is_transmit9_triggered_~__retres1~9#1 := 0; {37142#false} is VALID [2022-02-21 04:24:30,207 INFO L290 TraceCheckUtils]: 94: Hoare triple {37142#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {37142#false} is VALID [2022-02-21 04:24:30,207 INFO L290 TraceCheckUtils]: 95: Hoare triple {37142#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {37142#false} is VALID [2022-02-21 04:24:30,207 INFO L290 TraceCheckUtils]: 96: Hoare triple {37142#false} assume !(0 != activate_threads_~tmp___8~0#1); {37142#false} is VALID [2022-02-21 04:24:30,207 INFO L290 TraceCheckUtils]: 97: Hoare triple {37142#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {37142#false} is VALID [2022-02-21 04:24:30,207 INFO L290 TraceCheckUtils]: 98: Hoare triple {37142#false} assume 1 == ~t10_pc~0; {37142#false} is VALID [2022-02-21 04:24:30,207 INFO L290 TraceCheckUtils]: 99: Hoare triple {37142#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {37142#false} is VALID [2022-02-21 04:24:30,207 INFO L290 TraceCheckUtils]: 100: Hoare triple {37142#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {37142#false} is VALID [2022-02-21 04:24:30,208 INFO L290 TraceCheckUtils]: 101: Hoare triple {37142#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {37142#false} is VALID [2022-02-21 04:24:30,208 INFO L290 TraceCheckUtils]: 102: Hoare triple {37142#false} assume !(0 != activate_threads_~tmp___9~0#1); {37142#false} is VALID [2022-02-21 04:24:30,208 INFO L290 TraceCheckUtils]: 103: Hoare triple {37142#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37142#false} is VALID [2022-02-21 04:24:30,208 INFO L290 TraceCheckUtils]: 104: Hoare triple {37142#false} assume !(1 == ~M_E~0); {37142#false} is VALID [2022-02-21 04:24:30,208 INFO L290 TraceCheckUtils]: 105: Hoare triple {37142#false} assume !(1 == ~T1_E~0); {37142#false} is VALID [2022-02-21 04:24:30,208 INFO L290 TraceCheckUtils]: 106: Hoare triple {37142#false} assume !(1 == ~T2_E~0); {37142#false} is VALID [2022-02-21 04:24:30,208 INFO L290 TraceCheckUtils]: 107: Hoare triple {37142#false} assume !(1 == ~T3_E~0); {37142#false} is VALID [2022-02-21 04:24:30,208 INFO L290 TraceCheckUtils]: 108: Hoare triple {37142#false} assume !(1 == ~T4_E~0); {37142#false} is VALID [2022-02-21 04:24:30,209 INFO L290 TraceCheckUtils]: 109: Hoare triple {37142#false} assume !(1 == ~T5_E~0); {37142#false} is VALID [2022-02-21 04:24:30,209 INFO L290 TraceCheckUtils]: 110: Hoare triple {37142#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {37142#false} is VALID [2022-02-21 04:24:30,209 INFO L290 TraceCheckUtils]: 111: Hoare triple {37142#false} assume !(1 == ~T7_E~0); {37142#false} is VALID [2022-02-21 04:24:30,209 INFO L290 TraceCheckUtils]: 112: Hoare triple {37142#false} assume !(1 == ~T8_E~0); {37142#false} is VALID [2022-02-21 04:24:30,209 INFO L290 TraceCheckUtils]: 113: Hoare triple {37142#false} assume !(1 == ~T9_E~0); {37142#false} is VALID [2022-02-21 04:24:30,209 INFO L290 TraceCheckUtils]: 114: Hoare triple {37142#false} assume !(1 == ~T10_E~0); {37142#false} is VALID [2022-02-21 04:24:30,209 INFO L290 TraceCheckUtils]: 115: Hoare triple {37142#false} assume !(1 == ~E_1~0); {37142#false} is VALID [2022-02-21 04:24:30,209 INFO L290 TraceCheckUtils]: 116: Hoare triple {37142#false} assume !(1 == ~E_2~0); {37142#false} is VALID [2022-02-21 04:24:30,210 INFO L290 TraceCheckUtils]: 117: Hoare triple {37142#false} assume !(1 == ~E_3~0); {37142#false} is VALID [2022-02-21 04:24:30,210 INFO L290 TraceCheckUtils]: 118: Hoare triple {37142#false} assume 1 == ~E_4~0;~E_4~0 := 2; {37142#false} is VALID [2022-02-21 04:24:30,210 INFO L290 TraceCheckUtils]: 119: Hoare triple {37142#false} assume !(1 == ~E_5~0); {37142#false} is VALID [2022-02-21 04:24:30,210 INFO L290 TraceCheckUtils]: 120: Hoare triple {37142#false} assume !(1 == ~E_6~0); {37142#false} is VALID [2022-02-21 04:24:30,210 INFO L290 TraceCheckUtils]: 121: Hoare triple {37142#false} assume !(1 == ~E_7~0); {37142#false} is VALID [2022-02-21 04:24:30,210 INFO L290 TraceCheckUtils]: 122: Hoare triple {37142#false} assume !(1 == ~E_8~0); {37142#false} is VALID [2022-02-21 04:24:30,210 INFO L290 TraceCheckUtils]: 123: Hoare triple {37142#false} assume !(1 == ~E_9~0); {37142#false} is VALID [2022-02-21 04:24:30,210 INFO L290 TraceCheckUtils]: 124: Hoare triple {37142#false} assume !(1 == ~E_10~0); {37142#false} is VALID [2022-02-21 04:24:30,211 INFO L290 TraceCheckUtils]: 125: Hoare triple {37142#false} assume { :end_inline_reset_delta_events } true; {37142#false} is VALID [2022-02-21 04:24:30,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:30,211 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:30,211 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [915057836] [2022-02-21 04:24:30,212 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [915057836] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:30,212 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:30,212 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:30,212 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738915693] [2022-02-21 04:24:30,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:30,213 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:30,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:30,213 INFO L85 PathProgramCache]: Analyzing trace with hash 1576022729, now seen corresponding path program 1 times [2022-02-21 04:24:30,213 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:30,213 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853239711] [2022-02-21 04:24:30,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:30,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:30,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 0: Hoare triple {37144#true} assume !false; {37144#true} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 1: Hoare triple {37144#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {37144#true} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 2: Hoare triple {37144#true} assume !false; {37144#true} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 3: Hoare triple {37144#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {37144#true} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 4: Hoare triple {37144#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {37144#true} is VALID [2022-02-21 04:24:30,241 INFO L290 TraceCheckUtils]: 5: Hoare triple {37144#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {37144#true} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 6: Hoare triple {37144#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {37144#true} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 7: Hoare triple {37144#true} assume !(0 != eval_~tmp~0#1); {37144#true} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 8: Hoare triple {37144#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {37144#true} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 9: Hoare triple {37144#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {37144#true} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 10: Hoare triple {37144#true} assume 0 == ~M_E~0;~M_E~0 := 1; {37144#true} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 11: Hoare triple {37144#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {37144#true} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 12: Hoare triple {37144#true} assume !(0 == ~T2_E~0); {37144#true} is VALID [2022-02-21 04:24:30,242 INFO L290 TraceCheckUtils]: 13: Hoare triple {37144#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {37144#true} is VALID [2022-02-21 04:24:30,243 INFO L290 TraceCheckUtils]: 14: Hoare triple {37144#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {37144#true} is VALID [2022-02-21 04:24:30,243 INFO L290 TraceCheckUtils]: 15: Hoare triple {37144#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,243 INFO L290 TraceCheckUtils]: 16: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 17: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 18: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 19: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,244 INFO L290 TraceCheckUtils]: 20: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 21: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 22: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,245 INFO L290 TraceCheckUtils]: 23: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 24: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 25: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,246 INFO L290 TraceCheckUtils]: 26: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 27: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 28: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,247 INFO L290 TraceCheckUtils]: 29: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 30: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 31: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,248 INFO L290 TraceCheckUtils]: 32: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 33: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 34: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,249 INFO L290 TraceCheckUtils]: 35: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,250 INFO L290 TraceCheckUtils]: 36: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,250 INFO L290 TraceCheckUtils]: 37: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,250 INFO L290 TraceCheckUtils]: 38: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,251 INFO L290 TraceCheckUtils]: 39: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,251 INFO L290 TraceCheckUtils]: 40: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,252 INFO L290 TraceCheckUtils]: 41: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,252 INFO L290 TraceCheckUtils]: 42: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,252 INFO L290 TraceCheckUtils]: 43: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,253 INFO L290 TraceCheckUtils]: 44: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,253 INFO L290 TraceCheckUtils]: 45: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,253 INFO L290 TraceCheckUtils]: 46: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,254 INFO L290 TraceCheckUtils]: 47: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,254 INFO L290 TraceCheckUtils]: 48: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,254 INFO L290 TraceCheckUtils]: 49: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,255 INFO L290 TraceCheckUtils]: 50: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,255 INFO L290 TraceCheckUtils]: 51: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,255 INFO L290 TraceCheckUtils]: 52: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,256 INFO L290 TraceCheckUtils]: 53: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,256 INFO L290 TraceCheckUtils]: 54: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,257 INFO L290 TraceCheckUtils]: 55: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,257 INFO L290 TraceCheckUtils]: 56: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,257 INFO L290 TraceCheckUtils]: 57: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,258 INFO L290 TraceCheckUtils]: 58: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,258 INFO L290 TraceCheckUtils]: 59: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,258 INFO L290 TraceCheckUtils]: 60: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,259 INFO L290 TraceCheckUtils]: 61: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,259 INFO L290 TraceCheckUtils]: 62: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,259 INFO L290 TraceCheckUtils]: 63: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,260 INFO L290 TraceCheckUtils]: 64: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,260 INFO L290 TraceCheckUtils]: 65: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,260 INFO L290 TraceCheckUtils]: 66: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,260 INFO L290 TraceCheckUtils]: 67: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,261 INFO L290 TraceCheckUtils]: 68: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,261 INFO L290 TraceCheckUtils]: 69: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,261 INFO L290 TraceCheckUtils]: 70: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,262 INFO L290 TraceCheckUtils]: 71: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,262 INFO L290 TraceCheckUtils]: 72: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,262 INFO L290 TraceCheckUtils]: 73: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,263 INFO L290 TraceCheckUtils]: 74: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,263 INFO L290 TraceCheckUtils]: 75: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,263 INFO L290 TraceCheckUtils]: 76: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,264 INFO L290 TraceCheckUtils]: 77: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,264 INFO L290 TraceCheckUtils]: 78: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,264 INFO L290 TraceCheckUtils]: 79: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,265 INFO L290 TraceCheckUtils]: 80: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,265 INFO L290 TraceCheckUtils]: 81: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,265 INFO L290 TraceCheckUtils]: 82: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,266 INFO L290 TraceCheckUtils]: 83: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,266 INFO L290 TraceCheckUtils]: 84: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,266 INFO L290 TraceCheckUtils]: 85: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,267 INFO L290 TraceCheckUtils]: 86: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,267 INFO L290 TraceCheckUtils]: 87: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,267 INFO L290 TraceCheckUtils]: 88: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,268 INFO L290 TraceCheckUtils]: 89: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,268 INFO L290 TraceCheckUtils]: 90: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,268 INFO L290 TraceCheckUtils]: 91: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,269 INFO L290 TraceCheckUtils]: 92: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,269 INFO L290 TraceCheckUtils]: 93: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,269 INFO L290 TraceCheckUtils]: 94: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,270 INFO L290 TraceCheckUtils]: 95: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,270 INFO L290 TraceCheckUtils]: 96: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,270 INFO L290 TraceCheckUtils]: 97: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,271 INFO L290 TraceCheckUtils]: 98: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,271 INFO L290 TraceCheckUtils]: 99: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,271 INFO L290 TraceCheckUtils]: 100: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,272 INFO L290 TraceCheckUtils]: 101: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,272 INFO L290 TraceCheckUtils]: 102: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {37146#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:30,272 INFO L290 TraceCheckUtils]: 103: Hoare triple {37146#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {37145#false} is VALID [2022-02-21 04:24:30,272 INFO L290 TraceCheckUtils]: 104: Hoare triple {37145#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,272 INFO L290 TraceCheckUtils]: 105: Hoare triple {37145#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,273 INFO L290 TraceCheckUtils]: 106: Hoare triple {37145#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,273 INFO L290 TraceCheckUtils]: 107: Hoare triple {37145#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,273 INFO L290 TraceCheckUtils]: 108: Hoare triple {37145#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,273 INFO L290 TraceCheckUtils]: 109: Hoare triple {37145#false} assume 1 == ~E_1~0;~E_1~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,273 INFO L290 TraceCheckUtils]: 110: Hoare triple {37145#false} assume 1 == ~E_2~0;~E_2~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,273 INFO L290 TraceCheckUtils]: 111: Hoare triple {37145#false} assume !(1 == ~E_3~0); {37145#false} is VALID [2022-02-21 04:24:30,273 INFO L290 TraceCheckUtils]: 112: Hoare triple {37145#false} assume 1 == ~E_4~0;~E_4~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,273 INFO L290 TraceCheckUtils]: 113: Hoare triple {37145#false} assume 1 == ~E_5~0;~E_5~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,273 INFO L290 TraceCheckUtils]: 114: Hoare triple {37145#false} assume 1 == ~E_6~0;~E_6~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,274 INFO L290 TraceCheckUtils]: 115: Hoare triple {37145#false} assume 1 == ~E_7~0;~E_7~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,274 INFO L290 TraceCheckUtils]: 116: Hoare triple {37145#false} assume 1 == ~E_8~0;~E_8~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,274 INFO L290 TraceCheckUtils]: 117: Hoare triple {37145#false} assume 1 == ~E_9~0;~E_9~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,274 INFO L290 TraceCheckUtils]: 118: Hoare triple {37145#false} assume 1 == ~E_10~0;~E_10~0 := 2; {37145#false} is VALID [2022-02-21 04:24:30,274 INFO L290 TraceCheckUtils]: 119: Hoare triple {37145#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {37145#false} is VALID [2022-02-21 04:24:30,274 INFO L290 TraceCheckUtils]: 120: Hoare triple {37145#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {37145#false} is VALID [2022-02-21 04:24:30,274 INFO L290 TraceCheckUtils]: 121: Hoare triple {37145#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {37145#false} is VALID [2022-02-21 04:24:30,274 INFO L290 TraceCheckUtils]: 122: Hoare triple {37145#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {37145#false} is VALID [2022-02-21 04:24:30,275 INFO L290 TraceCheckUtils]: 123: Hoare triple {37145#false} assume !(0 == start_simulation_~tmp~3#1); {37145#false} is VALID [2022-02-21 04:24:30,275 INFO L290 TraceCheckUtils]: 124: Hoare triple {37145#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {37145#false} is VALID [2022-02-21 04:24:30,275 INFO L290 TraceCheckUtils]: 125: Hoare triple {37145#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {37145#false} is VALID [2022-02-21 04:24:30,275 INFO L290 TraceCheckUtils]: 126: Hoare triple {37145#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {37145#false} is VALID [2022-02-21 04:24:30,275 INFO L290 TraceCheckUtils]: 127: Hoare triple {37145#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {37145#false} is VALID [2022-02-21 04:24:30,275 INFO L290 TraceCheckUtils]: 128: Hoare triple {37145#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {37145#false} is VALID [2022-02-21 04:24:30,275 INFO L290 TraceCheckUtils]: 129: Hoare triple {37145#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {37145#false} is VALID [2022-02-21 04:24:30,275 INFO L290 TraceCheckUtils]: 130: Hoare triple {37145#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {37145#false} is VALID [2022-02-21 04:24:30,275 INFO L290 TraceCheckUtils]: 131: Hoare triple {37145#false} assume !(0 != start_simulation_~tmp___0~1#1); {37145#false} is VALID [2022-02-21 04:24:30,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:30,276 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:30,276 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1853239711] [2022-02-21 04:24:30,276 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1853239711] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:30,276 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:30,276 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:30,277 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [448269677] [2022-02-21 04:24:30,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:30,277 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:30,277 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:30,278 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:30,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:30,278 INFO L87 Difference]: Start difference. First operand 1278 states and 1895 transitions. cyclomatic complexity: 618 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:31,113 INFO L93 Difference]: Finished difference Result 1278 states and 1894 transitions. [2022-02-21 04:24:31,113 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:31,113 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,195 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:31,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1894 transitions. [2022-02-21 04:24:31,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:31,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1894 transitions. [2022-02-21 04:24:31,270 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-02-21 04:24:31,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-02-21 04:24:31,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1894 transitions. [2022-02-21 04:24:31,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:31,272 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2022-02-21 04:24:31,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1894 transitions. [2022-02-21 04:24:31,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-02-21 04:24:31,283 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:31,284 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1278 states and 1894 transitions. Second operand has 1278 states, 1278 states have (on average 1.482003129890454) internal successors, (1894), 1277 states have internal predecessors, (1894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,285 INFO L74 IsIncluded]: Start isIncluded. First operand 1278 states and 1894 transitions. Second operand has 1278 states, 1278 states have (on average 1.482003129890454) internal successors, (1894), 1277 states have internal predecessors, (1894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,300 INFO L87 Difference]: Start difference. First operand 1278 states and 1894 transitions. Second operand has 1278 states, 1278 states have (on average 1.482003129890454) internal successors, (1894), 1277 states have internal predecessors, (1894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:31,340 INFO L93 Difference]: Finished difference Result 1278 states and 1894 transitions. [2022-02-21 04:24:31,340 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1894 transitions. [2022-02-21 04:24:31,342 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:31,342 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:31,344 INFO L74 IsIncluded]: Start isIncluded. First operand has 1278 states, 1278 states have (on average 1.482003129890454) internal successors, (1894), 1277 states have internal predecessors, (1894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1894 transitions. [2022-02-21 04:24:31,345 INFO L87 Difference]: Start difference. First operand has 1278 states, 1278 states have (on average 1.482003129890454) internal successors, (1894), 1277 states have internal predecessors, (1894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1894 transitions. [2022-02-21 04:24:31,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:31,380 INFO L93 Difference]: Finished difference Result 1278 states and 1894 transitions. [2022-02-21 04:24:31,380 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1894 transitions. [2022-02-21 04:24:31,381 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:31,381 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:31,381 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:31,381 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:31,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.482003129890454) internal successors, (1894), 1277 states have internal predecessors, (1894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1894 transitions. [2022-02-21 04:24:31,447 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2022-02-21 04:24:31,447 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1894 transitions. [2022-02-21 04:24:31,447 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:31,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1894 transitions. [2022-02-21 04:24:31,449 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:31,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:31,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:31,450 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:31,451 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:31,451 INFO L791 eck$LassoCheckResult]: Stem: 39406#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 39407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 39682#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39670#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39671#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 39691#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39692#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38975#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38693#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38694#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39600#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39601#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39586#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39587#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39622#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 38745#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38746#L1006 assume !(0 == ~M_E~0); 38596#L1006-2 assume !(0 == ~T1_E~0); 38597#L1011-1 assume !(0 == ~T2_E~0); 39644#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39659#L1021-1 assume !(0 == ~T4_E~0); 38476#L1026-1 assume !(0 == ~T5_E~0); 38477#L1031-1 assume !(0 == ~T6_E~0); 39352#L1036-1 assume !(0 == ~T7_E~0); 39348#L1041-1 assume !(0 == ~T8_E~0); 39349#L1046-1 assume !(0 == ~T9_E~0); 38778#L1051-1 assume !(0 == ~T10_E~0); 38779#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 39481#L1061-1 assume !(0 == ~E_2~0); 38697#L1066-1 assume !(0 == ~E_3~0); 38698#L1071-1 assume !(0 == ~E_4~0); 39460#L1076-1 assume !(0 == ~E_5~0); 38607#L1081-1 assume !(0 == ~E_6~0); 38608#L1086-1 assume !(0 == ~E_7~0); 38950#L1091-1 assume !(0 == ~E_8~0); 39636#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 39637#L1101-1 assume !(0 == ~E_10~0); 39012#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39013#L484 assume !(1 == ~m_pc~0); 38656#L484-2 is_master_triggered_~__retres1~0#1 := 0; 38655#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39271#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39555#L1245 assume !(0 != activate_threads_~tmp~1#1); 39556#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39340#L503 assume 1 == ~t1_pc~0; 39341#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39357#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39473#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 39123#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 38506#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38507#L522 assume !(1 == ~t2_pc~0); 39307#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38710#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38711#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39181#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 39602#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39667#L541 assume 1 == ~t3_pc~0; 39256#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39072#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38887#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38888#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 39310#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39311#L560 assume !(1 == ~t4_pc~0); 38588#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 38587#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39215#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38474#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 38475#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38759#L579 assume 1 == ~t5_pc~0; 38425#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38426#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38534#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39218#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 39657#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39679#L598 assume 1 == ~t6_pc~0; 38855#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38856#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39157#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39578#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 39389#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39331#L617 assume !(1 == ~t7_pc~0); 38828#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 38827#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39113#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39114#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39049#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39050#L636 assume 1 == ~t8_pc~0; 39212#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39213#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39014#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39015#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 39165#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39166#L655 assume !(1 == ~t9_pc~0); 39193#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 39194#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38807#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38808#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 39408#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39409#L674 assume 1 == ~t10_pc~0; 38583#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38584#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39669#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39700#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 39155#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39156#L1119 assume !(1 == ~M_E~0); 38679#L1119-2 assume !(1 == ~T1_E~0); 38680#L1124-1 assume !(1 == ~T2_E~0); 38498#L1129-1 assume !(1 == ~T3_E~0); 38499#L1134-1 assume !(1 == ~T4_E~0); 38809#L1139-1 assume !(1 == ~T5_E~0); 38810#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39045#L1149-1 assume !(1 == ~T7_E~0); 38674#L1154-1 assume !(1 == ~T8_E~0); 38675#L1159-1 assume !(1 == ~T9_E~0); 38762#L1164-1 assume !(1 == ~T10_E~0); 39184#L1169-1 assume !(1 == ~E_1~0); 39082#L1174-1 assume !(1 == ~E_2~0); 38869#L1179-1 assume !(1 == ~E_3~0); 38751#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 38752#L1189-1 assume !(1 == ~E_5~0); 38804#L1194-1 assume !(1 == ~E_6~0); 38928#L1199-1 assume !(1 == ~E_7~0); 38879#L1204-1 assume !(1 == ~E_8~0); 38880#L1209-1 assume !(1 == ~E_9~0); 39403#L1214-1 assume !(1 == ~E_10~0); 39404#L1219-1 assume { :end_inline_reset_delta_events } true; 38462#L1520-2 [2022-02-21 04:24:31,451 INFO L793 eck$LassoCheckResult]: Loop: 38462#L1520-2 assume !false; 38463#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38563#L981 assume !false; 38755#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 39430#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 38448#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 39548#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 39598#L836 assume !(0 != eval_~tmp~0#1); 39040#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39041#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39036#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 39037#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39507#L1011-3 assume !(0 == ~T2_E~0); 39508#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39547#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39228#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39229#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39475#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39476#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39536#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39537#L1051-3 assume !(0 == ~T10_E~0); 39477#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38773#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38774#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38777#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 39648#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38560#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38561#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38613#L1091-3 assume !(0 == ~E_8~0); 38614#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 39623#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 39624#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39250#L484-33 assume 1 == ~m_pc~0; 39251#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39170#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39171#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38468#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38469#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38937#L503-33 assume !(1 == ~t1_pc~0); 38938#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 39391#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39318#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38847#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38848#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39287#L522-33 assume 1 == ~t2_pc~0; 39288#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38601#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38602#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39396#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39305#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39306#L541-33 assume 1 == ~t3_pc~0; 38627#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38466#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38467#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39277#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 39278#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39472#L560-33 assume 1 == ~t4_pc~0; 39177#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38538#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38539#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38797#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 39454#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38457#L579-33 assume 1 == ~t5_pc~0; 38458#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38704#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39663#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39332#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39333#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39361#L598-33 assume 1 == ~t6_pc~0; 39665#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38961#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38962#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38802#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38803#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39612#L617-33 assume 1 == ~t7_pc~0; 39618#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38595#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39546#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39653#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39649#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38526#L636-33 assume 1 == ~t8_pc~0; 38528#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39446#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39447#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39672#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39437#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39438#L655-33 assume 1 == ~t9_pc~0; 39696#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38904#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38905#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39261#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 39525#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39081#L674-33 assume 1 == ~t10_pc~0; 38956#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38957#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38818#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38819#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39296#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39673#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 39680#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39684#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39694#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38843#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38844#L1139-3 assume !(1 == ~T5_E~0); 39074#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39075#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39217#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39487#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39488#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39655#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38959#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38960#L1179-3 assume !(1 == ~E_3~0); 39579#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38589#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38590#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38900#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38901#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 39204#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38480#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 38481#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 39395#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 38566#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 38917#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 38918#L1539 assume !(0 == start_simulation_~tmp~3#1); 39010#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 39186#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 38993#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 39126#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 38909#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38910#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39514#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 39011#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 38462#L1520-2 [2022-02-21 04:24:31,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:31,452 INFO L85 PathProgramCache]: Analyzing trace with hash 1406784749, now seen corresponding path program 1 times [2022-02-21 04:24:31,452 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:31,452 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616328262] [2022-02-21 04:24:31,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:31,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:31,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:31,475 INFO L290 TraceCheckUtils]: 0: Hoare triple {42262#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {42262#true} is VALID [2022-02-21 04:24:31,476 INFO L290 TraceCheckUtils]: 1: Hoare triple {42262#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,476 INFO L290 TraceCheckUtils]: 2: Hoare triple {42264#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,476 INFO L290 TraceCheckUtils]: 3: Hoare triple {42264#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,476 INFO L290 TraceCheckUtils]: 4: Hoare triple {42264#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,477 INFO L290 TraceCheckUtils]: 5: Hoare triple {42264#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,477 INFO L290 TraceCheckUtils]: 6: Hoare triple {42264#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,477 INFO L290 TraceCheckUtils]: 7: Hoare triple {42264#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,478 INFO L290 TraceCheckUtils]: 8: Hoare triple {42264#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,478 INFO L290 TraceCheckUtils]: 9: Hoare triple {42264#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,478 INFO L290 TraceCheckUtils]: 10: Hoare triple {42264#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,478 INFO L290 TraceCheckUtils]: 11: Hoare triple {42264#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,479 INFO L290 TraceCheckUtils]: 12: Hoare triple {42264#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,479 INFO L290 TraceCheckUtils]: 13: Hoare triple {42264#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {42264#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:31,479 INFO L290 TraceCheckUtils]: 14: Hoare triple {42264#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {42263#false} is VALID [2022-02-21 04:24:31,479 INFO L290 TraceCheckUtils]: 15: Hoare triple {42263#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {42263#false} is VALID [2022-02-21 04:24:31,480 INFO L290 TraceCheckUtils]: 16: Hoare triple {42263#false} assume !(0 == ~M_E~0); {42263#false} is VALID [2022-02-21 04:24:31,480 INFO L290 TraceCheckUtils]: 17: Hoare triple {42263#false} assume !(0 == ~T1_E~0); {42263#false} is VALID [2022-02-21 04:24:31,480 INFO L290 TraceCheckUtils]: 18: Hoare triple {42263#false} assume !(0 == ~T2_E~0); {42263#false} is VALID [2022-02-21 04:24:31,480 INFO L290 TraceCheckUtils]: 19: Hoare triple {42263#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {42263#false} is VALID [2022-02-21 04:24:31,480 INFO L290 TraceCheckUtils]: 20: Hoare triple {42263#false} assume !(0 == ~T4_E~0); {42263#false} is VALID [2022-02-21 04:24:31,480 INFO L290 TraceCheckUtils]: 21: Hoare triple {42263#false} assume !(0 == ~T5_E~0); {42263#false} is VALID [2022-02-21 04:24:31,480 INFO L290 TraceCheckUtils]: 22: Hoare triple {42263#false} assume !(0 == ~T6_E~0); {42263#false} is VALID [2022-02-21 04:24:31,480 INFO L290 TraceCheckUtils]: 23: Hoare triple {42263#false} assume !(0 == ~T7_E~0); {42263#false} is VALID [2022-02-21 04:24:31,480 INFO L290 TraceCheckUtils]: 24: Hoare triple {42263#false} assume !(0 == ~T8_E~0); {42263#false} is VALID [2022-02-21 04:24:31,481 INFO L290 TraceCheckUtils]: 25: Hoare triple {42263#false} assume !(0 == ~T9_E~0); {42263#false} is VALID [2022-02-21 04:24:31,481 INFO L290 TraceCheckUtils]: 26: Hoare triple {42263#false} assume !(0 == ~T10_E~0); {42263#false} is VALID [2022-02-21 04:24:31,481 INFO L290 TraceCheckUtils]: 27: Hoare triple {42263#false} assume 0 == ~E_1~0;~E_1~0 := 1; {42263#false} is VALID [2022-02-21 04:24:31,481 INFO L290 TraceCheckUtils]: 28: Hoare triple {42263#false} assume !(0 == ~E_2~0); {42263#false} is VALID [2022-02-21 04:24:31,481 INFO L290 TraceCheckUtils]: 29: Hoare triple {42263#false} assume !(0 == ~E_3~0); {42263#false} is VALID [2022-02-21 04:24:31,481 INFO L290 TraceCheckUtils]: 30: Hoare triple {42263#false} assume !(0 == ~E_4~0); {42263#false} is VALID [2022-02-21 04:24:31,481 INFO L290 TraceCheckUtils]: 31: Hoare triple {42263#false} assume !(0 == ~E_5~0); {42263#false} is VALID [2022-02-21 04:24:31,481 INFO L290 TraceCheckUtils]: 32: Hoare triple {42263#false} assume !(0 == ~E_6~0); {42263#false} is VALID [2022-02-21 04:24:31,481 INFO L290 TraceCheckUtils]: 33: Hoare triple {42263#false} assume !(0 == ~E_7~0); {42263#false} is VALID [2022-02-21 04:24:31,482 INFO L290 TraceCheckUtils]: 34: Hoare triple {42263#false} assume !(0 == ~E_8~0); {42263#false} is VALID [2022-02-21 04:24:31,482 INFO L290 TraceCheckUtils]: 35: Hoare triple {42263#false} assume 0 == ~E_9~0;~E_9~0 := 1; {42263#false} is VALID [2022-02-21 04:24:31,482 INFO L290 TraceCheckUtils]: 36: Hoare triple {42263#false} assume !(0 == ~E_10~0); {42263#false} is VALID [2022-02-21 04:24:31,482 INFO L290 TraceCheckUtils]: 37: Hoare triple {42263#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {42263#false} is VALID [2022-02-21 04:24:31,482 INFO L290 TraceCheckUtils]: 38: Hoare triple {42263#false} assume !(1 == ~m_pc~0); {42263#false} is VALID [2022-02-21 04:24:31,482 INFO L290 TraceCheckUtils]: 39: Hoare triple {42263#false} is_master_triggered_~__retres1~0#1 := 0; {42263#false} is VALID [2022-02-21 04:24:31,482 INFO L290 TraceCheckUtils]: 40: Hoare triple {42263#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {42263#false} is VALID [2022-02-21 04:24:31,482 INFO L290 TraceCheckUtils]: 41: Hoare triple {42263#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {42263#false} is VALID [2022-02-21 04:24:31,482 INFO L290 TraceCheckUtils]: 42: Hoare triple {42263#false} assume !(0 != activate_threads_~tmp~1#1); {42263#false} is VALID [2022-02-21 04:24:31,483 INFO L290 TraceCheckUtils]: 43: Hoare triple {42263#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {42263#false} is VALID [2022-02-21 04:24:31,483 INFO L290 TraceCheckUtils]: 44: Hoare triple {42263#false} assume 1 == ~t1_pc~0; {42263#false} is VALID [2022-02-21 04:24:31,483 INFO L290 TraceCheckUtils]: 45: Hoare triple {42263#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {42263#false} is VALID [2022-02-21 04:24:31,483 INFO L290 TraceCheckUtils]: 46: Hoare triple {42263#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {42263#false} is VALID [2022-02-21 04:24:31,483 INFO L290 TraceCheckUtils]: 47: Hoare triple {42263#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {42263#false} is VALID [2022-02-21 04:24:31,483 INFO L290 TraceCheckUtils]: 48: Hoare triple {42263#false} assume !(0 != activate_threads_~tmp___0~0#1); {42263#false} is VALID [2022-02-21 04:24:31,483 INFO L290 TraceCheckUtils]: 49: Hoare triple {42263#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {42263#false} is VALID [2022-02-21 04:24:31,483 INFO L290 TraceCheckUtils]: 50: Hoare triple {42263#false} assume !(1 == ~t2_pc~0); {42263#false} is VALID [2022-02-21 04:24:31,483 INFO L290 TraceCheckUtils]: 51: Hoare triple {42263#false} is_transmit2_triggered_~__retres1~2#1 := 0; {42263#false} is VALID [2022-02-21 04:24:31,484 INFO L290 TraceCheckUtils]: 52: Hoare triple {42263#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {42263#false} is VALID [2022-02-21 04:24:31,484 INFO L290 TraceCheckUtils]: 53: Hoare triple {42263#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {42263#false} is VALID [2022-02-21 04:24:31,484 INFO L290 TraceCheckUtils]: 54: Hoare triple {42263#false} assume !(0 != activate_threads_~tmp___1~0#1); {42263#false} is VALID [2022-02-21 04:24:31,484 INFO L290 TraceCheckUtils]: 55: Hoare triple {42263#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {42263#false} is VALID [2022-02-21 04:24:31,484 INFO L290 TraceCheckUtils]: 56: Hoare triple {42263#false} assume 1 == ~t3_pc~0; {42263#false} is VALID [2022-02-21 04:24:31,484 INFO L290 TraceCheckUtils]: 57: Hoare triple {42263#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {42263#false} is VALID [2022-02-21 04:24:31,484 INFO L290 TraceCheckUtils]: 58: Hoare triple {42263#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {42263#false} is VALID [2022-02-21 04:24:31,484 INFO L290 TraceCheckUtils]: 59: Hoare triple {42263#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {42263#false} is VALID [2022-02-21 04:24:31,484 INFO L290 TraceCheckUtils]: 60: Hoare triple {42263#false} assume !(0 != activate_threads_~tmp___2~0#1); {42263#false} is VALID [2022-02-21 04:24:31,485 INFO L290 TraceCheckUtils]: 61: Hoare triple {42263#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {42263#false} is VALID [2022-02-21 04:24:31,485 INFO L290 TraceCheckUtils]: 62: Hoare triple {42263#false} assume !(1 == ~t4_pc~0); {42263#false} is VALID [2022-02-21 04:24:31,485 INFO L290 TraceCheckUtils]: 63: Hoare triple {42263#false} is_transmit4_triggered_~__retres1~4#1 := 0; {42263#false} is VALID [2022-02-21 04:24:31,485 INFO L290 TraceCheckUtils]: 64: Hoare triple {42263#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {42263#false} is VALID [2022-02-21 04:24:31,485 INFO L290 TraceCheckUtils]: 65: Hoare triple {42263#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {42263#false} is VALID [2022-02-21 04:24:31,485 INFO L290 TraceCheckUtils]: 66: Hoare triple {42263#false} assume !(0 != activate_threads_~tmp___3~0#1); {42263#false} is VALID [2022-02-21 04:24:31,485 INFO L290 TraceCheckUtils]: 67: Hoare triple {42263#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {42263#false} is VALID [2022-02-21 04:24:31,485 INFO L290 TraceCheckUtils]: 68: Hoare triple {42263#false} assume 1 == ~t5_pc~0; {42263#false} is VALID [2022-02-21 04:24:31,485 INFO L290 TraceCheckUtils]: 69: Hoare triple {42263#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {42263#false} is VALID [2022-02-21 04:24:31,486 INFO L290 TraceCheckUtils]: 70: Hoare triple {42263#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {42263#false} is VALID [2022-02-21 04:24:31,486 INFO L290 TraceCheckUtils]: 71: Hoare triple {42263#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {42263#false} is VALID [2022-02-21 04:24:31,486 INFO L290 TraceCheckUtils]: 72: Hoare triple {42263#false} assume !(0 != activate_threads_~tmp___4~0#1); {42263#false} is VALID [2022-02-21 04:24:31,486 INFO L290 TraceCheckUtils]: 73: Hoare triple {42263#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {42263#false} is VALID [2022-02-21 04:24:31,486 INFO L290 TraceCheckUtils]: 74: Hoare triple {42263#false} assume 1 == ~t6_pc~0; {42263#false} is VALID [2022-02-21 04:24:31,486 INFO L290 TraceCheckUtils]: 75: Hoare triple {42263#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {42263#false} is VALID [2022-02-21 04:24:31,486 INFO L290 TraceCheckUtils]: 76: Hoare triple {42263#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {42263#false} is VALID [2022-02-21 04:24:31,486 INFO L290 TraceCheckUtils]: 77: Hoare triple {42263#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {42263#false} is VALID [2022-02-21 04:24:31,487 INFO L290 TraceCheckUtils]: 78: Hoare triple {42263#false} assume !(0 != activate_threads_~tmp___5~0#1); {42263#false} is VALID [2022-02-21 04:24:31,487 INFO L290 TraceCheckUtils]: 79: Hoare triple {42263#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {42263#false} is VALID [2022-02-21 04:24:31,487 INFO L290 TraceCheckUtils]: 80: Hoare triple {42263#false} assume !(1 == ~t7_pc~0); {42263#false} is VALID [2022-02-21 04:24:31,487 INFO L290 TraceCheckUtils]: 81: Hoare triple {42263#false} is_transmit7_triggered_~__retres1~7#1 := 0; {42263#false} is VALID [2022-02-21 04:24:31,487 INFO L290 TraceCheckUtils]: 82: Hoare triple {42263#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {42263#false} is VALID [2022-02-21 04:24:31,487 INFO L290 TraceCheckUtils]: 83: Hoare triple {42263#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {42263#false} is VALID [2022-02-21 04:24:31,487 INFO L290 TraceCheckUtils]: 84: Hoare triple {42263#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {42263#false} is VALID [2022-02-21 04:24:31,487 INFO L290 TraceCheckUtils]: 85: Hoare triple {42263#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {42263#false} is VALID [2022-02-21 04:24:31,487 INFO L290 TraceCheckUtils]: 86: Hoare triple {42263#false} assume 1 == ~t8_pc~0; {42263#false} is VALID [2022-02-21 04:24:31,488 INFO L290 TraceCheckUtils]: 87: Hoare triple {42263#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {42263#false} is VALID [2022-02-21 04:24:31,488 INFO L290 TraceCheckUtils]: 88: Hoare triple {42263#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {42263#false} is VALID [2022-02-21 04:24:31,488 INFO L290 TraceCheckUtils]: 89: Hoare triple {42263#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {42263#false} is VALID [2022-02-21 04:24:31,488 INFO L290 TraceCheckUtils]: 90: Hoare triple {42263#false} assume !(0 != activate_threads_~tmp___7~0#1); {42263#false} is VALID [2022-02-21 04:24:31,488 INFO L290 TraceCheckUtils]: 91: Hoare triple {42263#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {42263#false} is VALID [2022-02-21 04:24:31,488 INFO L290 TraceCheckUtils]: 92: Hoare triple {42263#false} assume !(1 == ~t9_pc~0); {42263#false} is VALID [2022-02-21 04:24:31,488 INFO L290 TraceCheckUtils]: 93: Hoare triple {42263#false} is_transmit9_triggered_~__retres1~9#1 := 0; {42263#false} is VALID [2022-02-21 04:24:31,488 INFO L290 TraceCheckUtils]: 94: Hoare triple {42263#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {42263#false} is VALID [2022-02-21 04:24:31,488 INFO L290 TraceCheckUtils]: 95: Hoare triple {42263#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {42263#false} is VALID [2022-02-21 04:24:31,489 INFO L290 TraceCheckUtils]: 96: Hoare triple {42263#false} assume !(0 != activate_threads_~tmp___8~0#1); {42263#false} is VALID [2022-02-21 04:24:31,489 INFO L290 TraceCheckUtils]: 97: Hoare triple {42263#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {42263#false} is VALID [2022-02-21 04:24:31,489 INFO L290 TraceCheckUtils]: 98: Hoare triple {42263#false} assume 1 == ~t10_pc~0; {42263#false} is VALID [2022-02-21 04:24:31,489 INFO L290 TraceCheckUtils]: 99: Hoare triple {42263#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {42263#false} is VALID [2022-02-21 04:24:31,489 INFO L290 TraceCheckUtils]: 100: Hoare triple {42263#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {42263#false} is VALID [2022-02-21 04:24:31,489 INFO L290 TraceCheckUtils]: 101: Hoare triple {42263#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {42263#false} is VALID [2022-02-21 04:24:31,489 INFO L290 TraceCheckUtils]: 102: Hoare triple {42263#false} assume !(0 != activate_threads_~tmp___9~0#1); {42263#false} is VALID [2022-02-21 04:24:31,489 INFO L290 TraceCheckUtils]: 103: Hoare triple {42263#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {42263#false} is VALID [2022-02-21 04:24:31,489 INFO L290 TraceCheckUtils]: 104: Hoare triple {42263#false} assume !(1 == ~M_E~0); {42263#false} is VALID [2022-02-21 04:24:31,490 INFO L290 TraceCheckUtils]: 105: Hoare triple {42263#false} assume !(1 == ~T1_E~0); {42263#false} is VALID [2022-02-21 04:24:31,490 INFO L290 TraceCheckUtils]: 106: Hoare triple {42263#false} assume !(1 == ~T2_E~0); {42263#false} is VALID [2022-02-21 04:24:31,490 INFO L290 TraceCheckUtils]: 107: Hoare triple {42263#false} assume !(1 == ~T3_E~0); {42263#false} is VALID [2022-02-21 04:24:31,490 INFO L290 TraceCheckUtils]: 108: Hoare triple {42263#false} assume !(1 == ~T4_E~0); {42263#false} is VALID [2022-02-21 04:24:31,490 INFO L290 TraceCheckUtils]: 109: Hoare triple {42263#false} assume !(1 == ~T5_E~0); {42263#false} is VALID [2022-02-21 04:24:31,490 INFO L290 TraceCheckUtils]: 110: Hoare triple {42263#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {42263#false} is VALID [2022-02-21 04:24:31,490 INFO L290 TraceCheckUtils]: 111: Hoare triple {42263#false} assume !(1 == ~T7_E~0); {42263#false} is VALID [2022-02-21 04:24:31,490 INFO L290 TraceCheckUtils]: 112: Hoare triple {42263#false} assume !(1 == ~T8_E~0); {42263#false} is VALID [2022-02-21 04:24:31,490 INFO L290 TraceCheckUtils]: 113: Hoare triple {42263#false} assume !(1 == ~T9_E~0); {42263#false} is VALID [2022-02-21 04:24:31,491 INFO L290 TraceCheckUtils]: 114: Hoare triple {42263#false} assume !(1 == ~T10_E~0); {42263#false} is VALID [2022-02-21 04:24:31,491 INFO L290 TraceCheckUtils]: 115: Hoare triple {42263#false} assume !(1 == ~E_1~0); {42263#false} is VALID [2022-02-21 04:24:31,491 INFO L290 TraceCheckUtils]: 116: Hoare triple {42263#false} assume !(1 == ~E_2~0); {42263#false} is VALID [2022-02-21 04:24:31,491 INFO L290 TraceCheckUtils]: 117: Hoare triple {42263#false} assume !(1 == ~E_3~0); {42263#false} is VALID [2022-02-21 04:24:31,491 INFO L290 TraceCheckUtils]: 118: Hoare triple {42263#false} assume 1 == ~E_4~0;~E_4~0 := 2; {42263#false} is VALID [2022-02-21 04:24:31,491 INFO L290 TraceCheckUtils]: 119: Hoare triple {42263#false} assume !(1 == ~E_5~0); {42263#false} is VALID [2022-02-21 04:24:31,491 INFO L290 TraceCheckUtils]: 120: Hoare triple {42263#false} assume !(1 == ~E_6~0); {42263#false} is VALID [2022-02-21 04:24:31,491 INFO L290 TraceCheckUtils]: 121: Hoare triple {42263#false} assume !(1 == ~E_7~0); {42263#false} is VALID [2022-02-21 04:24:31,491 INFO L290 TraceCheckUtils]: 122: Hoare triple {42263#false} assume !(1 == ~E_8~0); {42263#false} is VALID [2022-02-21 04:24:31,492 INFO L290 TraceCheckUtils]: 123: Hoare triple {42263#false} assume !(1 == ~E_9~0); {42263#false} is VALID [2022-02-21 04:24:31,492 INFO L290 TraceCheckUtils]: 124: Hoare triple {42263#false} assume !(1 == ~E_10~0); {42263#false} is VALID [2022-02-21 04:24:31,492 INFO L290 TraceCheckUtils]: 125: Hoare triple {42263#false} assume { :end_inline_reset_delta_events } true; {42263#false} is VALID [2022-02-21 04:24:31,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:31,492 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:31,492 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1616328262] [2022-02-21 04:24:31,492 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1616328262] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:31,493 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:31,493 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:31,493 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046365230] [2022-02-21 04:24:31,493 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:31,493 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:31,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:31,494 INFO L85 PathProgramCache]: Analyzing trace with hash -1414290260, now seen corresponding path program 1 times [2022-02-21 04:24:31,494 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:31,494 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113939901] [2022-02-21 04:24:31,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:31,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:31,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:31,520 INFO L290 TraceCheckUtils]: 0: Hoare triple {42265#true} assume !false; {42265#true} is VALID [2022-02-21 04:24:31,520 INFO L290 TraceCheckUtils]: 1: Hoare triple {42265#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {42265#true} is VALID [2022-02-21 04:24:31,520 INFO L290 TraceCheckUtils]: 2: Hoare triple {42265#true} assume !false; {42265#true} is VALID [2022-02-21 04:24:31,520 INFO L290 TraceCheckUtils]: 3: Hoare triple {42265#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {42265#true} is VALID [2022-02-21 04:24:31,520 INFO L290 TraceCheckUtils]: 4: Hoare triple {42265#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {42265#true} is VALID [2022-02-21 04:24:31,521 INFO L290 TraceCheckUtils]: 5: Hoare triple {42265#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {42265#true} is VALID [2022-02-21 04:24:31,521 INFO L290 TraceCheckUtils]: 6: Hoare triple {42265#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {42265#true} is VALID [2022-02-21 04:24:31,521 INFO L290 TraceCheckUtils]: 7: Hoare triple {42265#true} assume !(0 != eval_~tmp~0#1); {42265#true} is VALID [2022-02-21 04:24:31,521 INFO L290 TraceCheckUtils]: 8: Hoare triple {42265#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {42265#true} is VALID [2022-02-21 04:24:31,521 INFO L290 TraceCheckUtils]: 9: Hoare triple {42265#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {42265#true} is VALID [2022-02-21 04:24:31,521 INFO L290 TraceCheckUtils]: 10: Hoare triple {42265#true} assume 0 == ~M_E~0;~M_E~0 := 1; {42265#true} is VALID [2022-02-21 04:24:31,521 INFO L290 TraceCheckUtils]: 11: Hoare triple {42265#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {42265#true} is VALID [2022-02-21 04:24:31,521 INFO L290 TraceCheckUtils]: 12: Hoare triple {42265#true} assume !(0 == ~T2_E~0); {42265#true} is VALID [2022-02-21 04:24:31,522 INFO L290 TraceCheckUtils]: 13: Hoare triple {42265#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {42265#true} is VALID [2022-02-21 04:24:31,522 INFO L290 TraceCheckUtils]: 14: Hoare triple {42265#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {42265#true} is VALID [2022-02-21 04:24:31,522 INFO L290 TraceCheckUtils]: 15: Hoare triple {42265#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,522 INFO L290 TraceCheckUtils]: 16: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,523 INFO L290 TraceCheckUtils]: 17: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,523 INFO L290 TraceCheckUtils]: 18: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,523 INFO L290 TraceCheckUtils]: 19: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,523 INFO L290 TraceCheckUtils]: 20: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,524 INFO L290 TraceCheckUtils]: 21: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,524 INFO L290 TraceCheckUtils]: 22: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,524 INFO L290 TraceCheckUtils]: 23: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,525 INFO L290 TraceCheckUtils]: 24: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,525 INFO L290 TraceCheckUtils]: 25: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,525 INFO L290 TraceCheckUtils]: 26: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,526 INFO L290 TraceCheckUtils]: 27: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,526 INFO L290 TraceCheckUtils]: 28: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,526 INFO L290 TraceCheckUtils]: 29: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,527 INFO L290 TraceCheckUtils]: 30: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,527 INFO L290 TraceCheckUtils]: 31: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,527 INFO L290 TraceCheckUtils]: 32: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,527 INFO L290 TraceCheckUtils]: 33: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,528 INFO L290 TraceCheckUtils]: 34: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,528 INFO L290 TraceCheckUtils]: 35: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,528 INFO L290 TraceCheckUtils]: 36: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,529 INFO L290 TraceCheckUtils]: 37: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,529 INFO L290 TraceCheckUtils]: 38: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,529 INFO L290 TraceCheckUtils]: 39: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,530 INFO L290 TraceCheckUtils]: 40: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,530 INFO L290 TraceCheckUtils]: 41: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,530 INFO L290 TraceCheckUtils]: 42: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,530 INFO L290 TraceCheckUtils]: 43: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,531 INFO L290 TraceCheckUtils]: 44: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,531 INFO L290 TraceCheckUtils]: 45: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,531 INFO L290 TraceCheckUtils]: 46: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,532 INFO L290 TraceCheckUtils]: 47: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,532 INFO L290 TraceCheckUtils]: 48: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,532 INFO L290 TraceCheckUtils]: 49: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,533 INFO L290 TraceCheckUtils]: 50: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,533 INFO L290 TraceCheckUtils]: 51: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,533 INFO L290 TraceCheckUtils]: 52: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,533 INFO L290 TraceCheckUtils]: 53: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,534 INFO L290 TraceCheckUtils]: 54: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,534 INFO L290 TraceCheckUtils]: 55: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,534 INFO L290 TraceCheckUtils]: 56: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,535 INFO L290 TraceCheckUtils]: 57: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,535 INFO L290 TraceCheckUtils]: 58: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,535 INFO L290 TraceCheckUtils]: 59: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,536 INFO L290 TraceCheckUtils]: 60: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,536 INFO L290 TraceCheckUtils]: 61: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,536 INFO L290 TraceCheckUtils]: 62: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,537 INFO L290 TraceCheckUtils]: 63: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,537 INFO L290 TraceCheckUtils]: 64: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,537 INFO L290 TraceCheckUtils]: 65: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,537 INFO L290 TraceCheckUtils]: 66: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,538 INFO L290 TraceCheckUtils]: 67: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,538 INFO L290 TraceCheckUtils]: 68: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,538 INFO L290 TraceCheckUtils]: 69: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,539 INFO L290 TraceCheckUtils]: 70: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,539 INFO L290 TraceCheckUtils]: 71: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,539 INFO L290 TraceCheckUtils]: 72: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,540 INFO L290 TraceCheckUtils]: 73: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,540 INFO L290 TraceCheckUtils]: 74: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,540 INFO L290 TraceCheckUtils]: 75: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,541 INFO L290 TraceCheckUtils]: 76: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,541 INFO L290 TraceCheckUtils]: 77: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,541 INFO L290 TraceCheckUtils]: 78: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,541 INFO L290 TraceCheckUtils]: 79: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,542 INFO L290 TraceCheckUtils]: 80: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,542 INFO L290 TraceCheckUtils]: 81: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,542 INFO L290 TraceCheckUtils]: 82: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,543 INFO L290 TraceCheckUtils]: 83: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,543 INFO L290 TraceCheckUtils]: 84: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,543 INFO L290 TraceCheckUtils]: 85: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,544 INFO L290 TraceCheckUtils]: 86: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,544 INFO L290 TraceCheckUtils]: 87: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,544 INFO L290 TraceCheckUtils]: 88: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,544 INFO L290 TraceCheckUtils]: 89: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,545 INFO L290 TraceCheckUtils]: 90: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,545 INFO L290 TraceCheckUtils]: 91: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,545 INFO L290 TraceCheckUtils]: 92: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,546 INFO L290 TraceCheckUtils]: 93: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,546 INFO L290 TraceCheckUtils]: 94: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,546 INFO L290 TraceCheckUtils]: 95: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,547 INFO L290 TraceCheckUtils]: 96: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,547 INFO L290 TraceCheckUtils]: 97: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,547 INFO L290 TraceCheckUtils]: 98: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,548 INFO L290 TraceCheckUtils]: 99: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,548 INFO L290 TraceCheckUtils]: 100: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,548 INFO L290 TraceCheckUtils]: 101: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,548 INFO L290 TraceCheckUtils]: 102: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {42267#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,549 INFO L290 TraceCheckUtils]: 103: Hoare triple {42267#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {42266#false} is VALID [2022-02-21 04:24:31,549 INFO L290 TraceCheckUtils]: 104: Hoare triple {42266#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,549 INFO L290 TraceCheckUtils]: 105: Hoare triple {42266#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,549 INFO L290 TraceCheckUtils]: 106: Hoare triple {42266#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,549 INFO L290 TraceCheckUtils]: 107: Hoare triple {42266#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,549 INFO L290 TraceCheckUtils]: 108: Hoare triple {42266#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,549 INFO L290 TraceCheckUtils]: 109: Hoare triple {42266#false} assume 1 == ~E_1~0;~E_1~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,550 INFO L290 TraceCheckUtils]: 110: Hoare triple {42266#false} assume 1 == ~E_2~0;~E_2~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,550 INFO L290 TraceCheckUtils]: 111: Hoare triple {42266#false} assume !(1 == ~E_3~0); {42266#false} is VALID [2022-02-21 04:24:31,550 INFO L290 TraceCheckUtils]: 112: Hoare triple {42266#false} assume 1 == ~E_4~0;~E_4~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,550 INFO L290 TraceCheckUtils]: 113: Hoare triple {42266#false} assume 1 == ~E_5~0;~E_5~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,550 INFO L290 TraceCheckUtils]: 114: Hoare triple {42266#false} assume 1 == ~E_6~0;~E_6~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,550 INFO L290 TraceCheckUtils]: 115: Hoare triple {42266#false} assume 1 == ~E_7~0;~E_7~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,550 INFO L290 TraceCheckUtils]: 116: Hoare triple {42266#false} assume 1 == ~E_8~0;~E_8~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,550 INFO L290 TraceCheckUtils]: 117: Hoare triple {42266#false} assume 1 == ~E_9~0;~E_9~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,550 INFO L290 TraceCheckUtils]: 118: Hoare triple {42266#false} assume 1 == ~E_10~0;~E_10~0 := 2; {42266#false} is VALID [2022-02-21 04:24:31,551 INFO L290 TraceCheckUtils]: 119: Hoare triple {42266#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {42266#false} is VALID [2022-02-21 04:24:31,551 INFO L290 TraceCheckUtils]: 120: Hoare triple {42266#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {42266#false} is VALID [2022-02-21 04:24:31,551 INFO L290 TraceCheckUtils]: 121: Hoare triple {42266#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {42266#false} is VALID [2022-02-21 04:24:31,551 INFO L290 TraceCheckUtils]: 122: Hoare triple {42266#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {42266#false} is VALID [2022-02-21 04:24:31,551 INFO L290 TraceCheckUtils]: 123: Hoare triple {42266#false} assume !(0 == start_simulation_~tmp~3#1); {42266#false} is VALID [2022-02-21 04:24:31,551 INFO L290 TraceCheckUtils]: 124: Hoare triple {42266#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {42266#false} is VALID [2022-02-21 04:24:31,551 INFO L290 TraceCheckUtils]: 125: Hoare triple {42266#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {42266#false} is VALID [2022-02-21 04:24:31,551 INFO L290 TraceCheckUtils]: 126: Hoare triple {42266#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {42266#false} is VALID [2022-02-21 04:24:31,551 INFO L290 TraceCheckUtils]: 127: Hoare triple {42266#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {42266#false} is VALID [2022-02-21 04:24:31,552 INFO L290 TraceCheckUtils]: 128: Hoare triple {42266#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {42266#false} is VALID [2022-02-21 04:24:31,552 INFO L290 TraceCheckUtils]: 129: Hoare triple {42266#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {42266#false} is VALID [2022-02-21 04:24:31,552 INFO L290 TraceCheckUtils]: 130: Hoare triple {42266#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {42266#false} is VALID [2022-02-21 04:24:31,552 INFO L290 TraceCheckUtils]: 131: Hoare triple {42266#false} assume !(0 != start_simulation_~tmp___0~1#1); {42266#false} is VALID [2022-02-21 04:24:31,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:31,552 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:31,553 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113939901] [2022-02-21 04:24:31,553 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113939901] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:31,553 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:31,553 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:31,553 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2011693357] [2022-02-21 04:24:31,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:31,553 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:31,554 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:31,554 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:31,554 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:31,555 INFO L87 Difference]: Start difference. First operand 1278 states and 1894 transitions. cyclomatic complexity: 617 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:32,430 INFO L93 Difference]: Finished difference Result 1278 states and 1893 transitions. [2022-02-21 04:24:32,430 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:32,430 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,505 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:32,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1278 states and 1893 transitions. [2022-02-21 04:24:32,542 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:32,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1278 states to 1278 states and 1893 transitions. [2022-02-21 04:24:32,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1278 [2022-02-21 04:24:32,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1278 [2022-02-21 04:24:32,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1278 states and 1893 transitions. [2022-02-21 04:24:32,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:32,580 INFO L681 BuchiCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2022-02-21 04:24:32,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1278 states and 1893 transitions. [2022-02-21 04:24:32,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1278 to 1278. [2022-02-21 04:24:32,590 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:32,591 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1278 states and 1893 transitions. Second operand has 1278 states, 1278 states have (on average 1.4812206572769953) internal successors, (1893), 1277 states have internal predecessors, (1893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,593 INFO L74 IsIncluded]: Start isIncluded. First operand 1278 states and 1893 transitions. Second operand has 1278 states, 1278 states have (on average 1.4812206572769953) internal successors, (1893), 1277 states have internal predecessors, (1893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,593 INFO L87 Difference]: Start difference. First operand 1278 states and 1893 transitions. Second operand has 1278 states, 1278 states have (on average 1.4812206572769953) internal successors, (1893), 1277 states have internal predecessors, (1893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:32,627 INFO L93 Difference]: Finished difference Result 1278 states and 1893 transitions. [2022-02-21 04:24:32,627 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1893 transitions. [2022-02-21 04:24:32,628 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:32,628 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:32,629 INFO L74 IsIncluded]: Start isIncluded. First operand has 1278 states, 1278 states have (on average 1.4812206572769953) internal successors, (1893), 1277 states have internal predecessors, (1893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1893 transitions. [2022-02-21 04:24:32,630 INFO L87 Difference]: Start difference. First operand has 1278 states, 1278 states have (on average 1.4812206572769953) internal successors, (1893), 1277 states have internal predecessors, (1893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1278 states and 1893 transitions. [2022-02-21 04:24:32,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:32,665 INFO L93 Difference]: Finished difference Result 1278 states and 1893 transitions. [2022-02-21 04:24:32,665 INFO L276 IsEmpty]: Start isEmpty. Operand 1278 states and 1893 transitions. [2022-02-21 04:24:32,666 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:32,666 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:32,666 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:32,666 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:32,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1278 states, 1278 states have (on average 1.4812206572769953) internal successors, (1893), 1277 states have internal predecessors, (1893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1278 states to 1278 states and 1893 transitions. [2022-02-21 04:24:32,701 INFO L704 BuchiCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2022-02-21 04:24:32,701 INFO L587 BuchiCegarLoop]: Abstraction has 1278 states and 1893 transitions. [2022-02-21 04:24:32,701 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:24:32,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1278 states and 1893 transitions. [2022-02-21 04:24:32,703 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1141 [2022-02-21 04:24:32,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:32,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:32,705 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:32,705 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:32,706 INFO L791 eck$LassoCheckResult]: Stem: 44528#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 44529#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 44803#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44791#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44792#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 44812#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44813#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44096#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43814#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43815#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44721#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44722#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44707#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44708#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44743#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43868#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43869#L1006 assume !(0 == ~M_E~0); 43717#L1006-2 assume !(0 == ~T1_E~0); 43718#L1011-1 assume !(0 == ~T2_E~0); 44765#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44780#L1021-1 assume !(0 == ~T4_E~0); 43599#L1026-1 assume !(0 == ~T5_E~0); 43600#L1031-1 assume !(0 == ~T6_E~0); 44473#L1036-1 assume !(0 == ~T7_E~0); 44469#L1041-1 assume !(0 == ~T8_E~0); 44470#L1046-1 assume !(0 == ~T9_E~0); 43899#L1051-1 assume !(0 == ~T10_E~0); 43900#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 44602#L1061-1 assume !(0 == ~E_2~0); 43818#L1066-1 assume !(0 == ~E_3~0); 43819#L1071-1 assume !(0 == ~E_4~0); 44581#L1076-1 assume !(0 == ~E_5~0); 43728#L1081-1 assume !(0 == ~E_6~0); 43729#L1086-1 assume !(0 == ~E_7~0); 44071#L1091-1 assume !(0 == ~E_8~0); 44758#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 44759#L1101-1 assume !(0 == ~E_10~0); 44133#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44134#L484 assume !(1 == ~m_pc~0); 43777#L484-2 is_master_triggered_~__retres1~0#1 := 0; 43776#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44392#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44676#L1245 assume !(0 != activate_threads_~tmp~1#1); 44677#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44461#L503 assume 1 == ~t1_pc~0; 44462#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44479#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44594#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44247#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 43627#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43628#L522 assume !(1 == ~t2_pc~0); 44428#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43831#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43832#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44302#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 44723#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44788#L541 assume 1 == ~t3_pc~0; 44377#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44193#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44008#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44009#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 44431#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44432#L560 assume !(1 == ~t4_pc~0); 43711#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43710#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44336#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43595#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 43596#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43882#L579 assume 1 == ~t5_pc~0; 43546#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43547#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43655#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44339#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 44779#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44800#L598 assume 1 == ~t6_pc~0; 43976#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43977#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44279#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44699#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 44510#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44452#L617 assume !(1 == ~t7_pc~0); 43949#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 43948#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44234#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44235#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44170#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44171#L636 assume 1 == ~t8_pc~0; 44333#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44334#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44135#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44136#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 44286#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44287#L655 assume !(1 == ~t9_pc~0); 44316#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 44317#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43928#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43929#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 44530#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44531#L674 assume 1 == ~t10_pc~0; 43704#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 43705#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44790#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44821#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 44276#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44277#L1119 assume !(1 == ~M_E~0); 43800#L1119-2 assume !(1 == ~T1_E~0); 43801#L1124-1 assume !(1 == ~T2_E~0); 43619#L1129-1 assume !(1 == ~T3_E~0); 43620#L1134-1 assume !(1 == ~T4_E~0); 43933#L1139-1 assume !(1 == ~T5_E~0); 43934#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44166#L1149-1 assume !(1 == ~T7_E~0); 43795#L1154-1 assume !(1 == ~T8_E~0); 43796#L1159-1 assume !(1 == ~T9_E~0); 43883#L1164-1 assume !(1 == ~T10_E~0); 44305#L1169-1 assume !(1 == ~E_1~0); 44203#L1174-1 assume !(1 == ~E_2~0); 43990#L1179-1 assume !(1 == ~E_3~0); 43872#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43873#L1189-1 assume !(1 == ~E_5~0); 43926#L1194-1 assume !(1 == ~E_6~0); 44049#L1199-1 assume !(1 == ~E_7~0); 44000#L1204-1 assume !(1 == ~E_8~0); 44001#L1209-1 assume !(1 == ~E_9~0); 44524#L1214-1 assume !(1 == ~E_10~0); 44525#L1219-1 assume { :end_inline_reset_delta_events } true; 43583#L1520-2 [2022-02-21 04:24:32,706 INFO L793 eck$LassoCheckResult]: Loop: 43583#L1520-2 assume !false; 43584#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43687#L981 assume !false; 43879#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 44551#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 43569#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 44669#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 44719#L836 assume !(0 != eval_~tmp~0#1); 44161#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44162#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44157#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44158#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44628#L1011-3 assume !(0 == ~T2_E~0); 44629#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44668#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44351#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44352#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44596#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44597#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44659#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44660#L1051-3 assume !(0 == ~T10_E~0); 44598#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43896#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43897#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43898#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44769#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43681#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43682#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43736#L1091-3 assume !(0 == ~E_8~0); 43737#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 44744#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44745#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44371#L484-33 assume 1 == ~m_pc~0; 44372#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 44291#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44292#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 43589#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43590#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44061#L503-33 assume !(1 == ~t1_pc~0); 44062#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 44512#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44441#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43968#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43969#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44408#L522-33 assume 1 == ~t2_pc~0; 44409#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43724#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43725#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44518#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44426#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44427#L541-33 assume 1 == ~t3_pc~0; 43748#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43587#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43588#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44398#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44399#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44593#L560-33 assume 1 == ~t4_pc~0; 44298#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43659#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43660#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43916#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 44575#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43575#L579-33 assume 1 == ~t5_pc~0; 43576#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43824#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44784#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44453#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44454#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44478#L598-33 assume 1 == ~t6_pc~0; 44785#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44082#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44083#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43923#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43924#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44733#L617-33 assume 1 == ~t7_pc~0; 44739#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43716#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44667#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44774#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 44770#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43647#L636-33 assume !(1 == ~t8_pc~0); 43648#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 44567#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44568#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44793#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44556#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44557#L655-33 assume 1 == ~t9_pc~0; 44817#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44023#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44024#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44382#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44646#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44202#L674-33 assume 1 == ~t10_pc~0; 44077#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44078#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43939#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43940#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44417#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44794#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44801#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44804#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44815#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43961#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43962#L1139-3 assume !(1 == ~T5_E~0); 44195#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44196#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44338#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44608#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44609#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44775#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44080#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44081#L1179-3 assume !(1 == ~E_3~0); 44700#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43707#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43708#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44021#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 44022#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44325#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43601#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43602#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 44515#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 43684#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 44038#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 44039#L1539 assume !(0 == start_simulation_~tmp~3#1); 44131#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 44307#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 44114#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 44246#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 44030#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44031#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44635#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 44132#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 43583#L1520-2 [2022-02-21 04:24:32,706 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:32,706 INFO L85 PathProgramCache]: Analyzing trace with hash 935428399, now seen corresponding path program 1 times [2022-02-21 04:24:32,707 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:32,707 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667610488] [2022-02-21 04:24:32,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:32,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:32,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:32,735 INFO L290 TraceCheckUtils]: 0: Hoare triple {47383#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,736 INFO L290 TraceCheckUtils]: 1: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,736 INFO L290 TraceCheckUtils]: 2: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,736 INFO L290 TraceCheckUtils]: 3: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,737 INFO L290 TraceCheckUtils]: 4: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,737 INFO L290 TraceCheckUtils]: 5: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,737 INFO L290 TraceCheckUtils]: 6: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,737 INFO L290 TraceCheckUtils]: 7: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,738 INFO L290 TraceCheckUtils]: 8: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,738 INFO L290 TraceCheckUtils]: 9: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,738 INFO L290 TraceCheckUtils]: 10: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,739 INFO L290 TraceCheckUtils]: 11: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,739 INFO L290 TraceCheckUtils]: 12: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,739 INFO L290 TraceCheckUtils]: 13: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,739 INFO L290 TraceCheckUtils]: 14: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,740 INFO L290 TraceCheckUtils]: 15: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,740 INFO L290 TraceCheckUtils]: 16: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume !(0 == ~M_E~0); {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,740 INFO L290 TraceCheckUtils]: 17: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume !(0 == ~T1_E~0); {47385#(= ~T2_E~0 ~T3_E~0)} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 18: Hoare triple {47385#(= ~T2_E~0 ~T3_E~0)} assume !(0 == ~T2_E~0); {47386#(not (= ~T3_E~0 0))} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 19: Hoare triple {47386#(not (= ~T3_E~0 0))} assume 0 == ~T3_E~0;~T3_E~0 := 1; {47384#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 20: Hoare triple {47384#false} assume !(0 == ~T4_E~0); {47384#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 21: Hoare triple {47384#false} assume !(0 == ~T5_E~0); {47384#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 22: Hoare triple {47384#false} assume !(0 == ~T6_E~0); {47384#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 23: Hoare triple {47384#false} assume !(0 == ~T7_E~0); {47384#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 24: Hoare triple {47384#false} assume !(0 == ~T8_E~0); {47384#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 25: Hoare triple {47384#false} assume !(0 == ~T9_E~0); {47384#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 26: Hoare triple {47384#false} assume !(0 == ~T10_E~0); {47384#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 27: Hoare triple {47384#false} assume 0 == ~E_1~0;~E_1~0 := 1; {47384#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 28: Hoare triple {47384#false} assume !(0 == ~E_2~0); {47384#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 29: Hoare triple {47384#false} assume !(0 == ~E_3~0); {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 30: Hoare triple {47384#false} assume !(0 == ~E_4~0); {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 31: Hoare triple {47384#false} assume !(0 == ~E_5~0); {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 32: Hoare triple {47384#false} assume !(0 == ~E_6~0); {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 33: Hoare triple {47384#false} assume !(0 == ~E_7~0); {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 34: Hoare triple {47384#false} assume !(0 == ~E_8~0); {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 35: Hoare triple {47384#false} assume 0 == ~E_9~0;~E_9~0 := 1; {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 36: Hoare triple {47384#false} assume !(0 == ~E_10~0); {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 37: Hoare triple {47384#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 38: Hoare triple {47384#false} assume !(1 == ~m_pc~0); {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 39: Hoare triple {47384#false} is_master_triggered_~__retres1~0#1 := 0; {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 40: Hoare triple {47384#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 41: Hoare triple {47384#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 42: Hoare triple {47384#false} assume !(0 != activate_threads_~tmp~1#1); {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 43: Hoare triple {47384#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 44: Hoare triple {47384#false} assume 1 == ~t1_pc~0; {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 45: Hoare triple {47384#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 46: Hoare triple {47384#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 47: Hoare triple {47384#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {47384#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 48: Hoare triple {47384#false} assume !(0 != activate_threads_~tmp___0~0#1); {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 49: Hoare triple {47384#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 50: Hoare triple {47384#false} assume !(1 == ~t2_pc~0); {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 51: Hoare triple {47384#false} is_transmit2_triggered_~__retres1~2#1 := 0; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 52: Hoare triple {47384#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 53: Hoare triple {47384#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 54: Hoare triple {47384#false} assume !(0 != activate_threads_~tmp___1~0#1); {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 55: Hoare triple {47384#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 56: Hoare triple {47384#false} assume 1 == ~t3_pc~0; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 57: Hoare triple {47384#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 58: Hoare triple {47384#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 59: Hoare triple {47384#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 60: Hoare triple {47384#false} assume !(0 != activate_threads_~tmp___2~0#1); {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 61: Hoare triple {47384#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 62: Hoare triple {47384#false} assume !(1 == ~t4_pc~0); {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 63: Hoare triple {47384#false} is_transmit4_triggered_~__retres1~4#1 := 0; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 64: Hoare triple {47384#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 65: Hoare triple {47384#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {47384#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 66: Hoare triple {47384#false} assume !(0 != activate_threads_~tmp___3~0#1); {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 67: Hoare triple {47384#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 68: Hoare triple {47384#false} assume 1 == ~t5_pc~0; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 69: Hoare triple {47384#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 70: Hoare triple {47384#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 71: Hoare triple {47384#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 72: Hoare triple {47384#false} assume !(0 != activate_threads_~tmp___4~0#1); {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 73: Hoare triple {47384#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 74: Hoare triple {47384#false} assume 1 == ~t6_pc~0; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 75: Hoare triple {47384#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 76: Hoare triple {47384#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 77: Hoare triple {47384#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 78: Hoare triple {47384#false} assume !(0 != activate_threads_~tmp___5~0#1); {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 79: Hoare triple {47384#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 80: Hoare triple {47384#false} assume !(1 == ~t7_pc~0); {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 81: Hoare triple {47384#false} is_transmit7_triggered_~__retres1~7#1 := 0; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 82: Hoare triple {47384#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 83: Hoare triple {47384#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 84: Hoare triple {47384#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {47384#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 85: Hoare triple {47384#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 86: Hoare triple {47384#false} assume 1 == ~t8_pc~0; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 87: Hoare triple {47384#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 88: Hoare triple {47384#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 89: Hoare triple {47384#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 90: Hoare triple {47384#false} assume !(0 != activate_threads_~tmp___7~0#1); {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 91: Hoare triple {47384#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 92: Hoare triple {47384#false} assume !(1 == ~t9_pc~0); {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 93: Hoare triple {47384#false} is_transmit9_triggered_~__retres1~9#1 := 0; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 94: Hoare triple {47384#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 95: Hoare triple {47384#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 96: Hoare triple {47384#false} assume !(0 != activate_threads_~tmp___8~0#1); {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 97: Hoare triple {47384#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 98: Hoare triple {47384#false} assume 1 == ~t10_pc~0; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 99: Hoare triple {47384#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 100: Hoare triple {47384#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 101: Hoare triple {47384#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 102: Hoare triple {47384#false} assume !(0 != activate_threads_~tmp___9~0#1); {47384#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 103: Hoare triple {47384#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 104: Hoare triple {47384#false} assume !(1 == ~M_E~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 105: Hoare triple {47384#false} assume !(1 == ~T1_E~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 106: Hoare triple {47384#false} assume !(1 == ~T2_E~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 107: Hoare triple {47384#false} assume !(1 == ~T3_E~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 108: Hoare triple {47384#false} assume !(1 == ~T4_E~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 109: Hoare triple {47384#false} assume !(1 == ~T5_E~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 110: Hoare triple {47384#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 111: Hoare triple {47384#false} assume !(1 == ~T7_E~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 112: Hoare triple {47384#false} assume !(1 == ~T8_E~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 113: Hoare triple {47384#false} assume !(1 == ~T9_E~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 114: Hoare triple {47384#false} assume !(1 == ~T10_E~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 115: Hoare triple {47384#false} assume !(1 == ~E_1~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 116: Hoare triple {47384#false} assume !(1 == ~E_2~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 117: Hoare triple {47384#false} assume !(1 == ~E_3~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 118: Hoare triple {47384#false} assume 1 == ~E_4~0;~E_4~0 := 2; {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 119: Hoare triple {47384#false} assume !(1 == ~E_5~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 120: Hoare triple {47384#false} assume !(1 == ~E_6~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 121: Hoare triple {47384#false} assume !(1 == ~E_7~0); {47384#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 122: Hoare triple {47384#false} assume !(1 == ~E_8~0); {47384#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 123: Hoare triple {47384#false} assume !(1 == ~E_9~0); {47384#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 124: Hoare triple {47384#false} assume !(1 == ~E_10~0); {47384#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 125: Hoare triple {47384#false} assume { :end_inline_reset_delta_events } true; {47384#false} is VALID [2022-02-21 04:24:32,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:32,747 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:32,747 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667610488] [2022-02-21 04:24:32,747 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667610488] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:32,747 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:32,747 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:32,747 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8933184] [2022-02-21 04:24:32,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:32,748 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:32,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:32,748 INFO L85 PathProgramCache]: Analyzing trace with hash -2115858485, now seen corresponding path program 1 times [2022-02-21 04:24:32,748 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:32,748 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227261221] [2022-02-21 04:24:32,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:32,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:32,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:32,787 INFO L290 TraceCheckUtils]: 0: Hoare triple {47387#true} assume !false; {47387#true} is VALID [2022-02-21 04:24:32,787 INFO L290 TraceCheckUtils]: 1: Hoare triple {47387#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {47387#true} is VALID [2022-02-21 04:24:32,788 INFO L290 TraceCheckUtils]: 2: Hoare triple {47387#true} assume !false; {47387#true} is VALID [2022-02-21 04:24:32,788 INFO L290 TraceCheckUtils]: 3: Hoare triple {47387#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {47387#true} is VALID [2022-02-21 04:24:32,788 INFO L290 TraceCheckUtils]: 4: Hoare triple {47387#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {47387#true} is VALID [2022-02-21 04:24:32,788 INFO L290 TraceCheckUtils]: 5: Hoare triple {47387#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {47387#true} is VALID [2022-02-21 04:24:32,788 INFO L290 TraceCheckUtils]: 6: Hoare triple {47387#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {47387#true} is VALID [2022-02-21 04:24:32,788 INFO L290 TraceCheckUtils]: 7: Hoare triple {47387#true} assume !(0 != eval_~tmp~0#1); {47387#true} is VALID [2022-02-21 04:24:32,788 INFO L290 TraceCheckUtils]: 8: Hoare triple {47387#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {47387#true} is VALID [2022-02-21 04:24:32,788 INFO L290 TraceCheckUtils]: 9: Hoare triple {47387#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {47387#true} is VALID [2022-02-21 04:24:32,788 INFO L290 TraceCheckUtils]: 10: Hoare triple {47387#true} assume 0 == ~M_E~0;~M_E~0 := 1; {47387#true} is VALID [2022-02-21 04:24:32,789 INFO L290 TraceCheckUtils]: 11: Hoare triple {47387#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {47387#true} is VALID [2022-02-21 04:24:32,789 INFO L290 TraceCheckUtils]: 12: Hoare triple {47387#true} assume !(0 == ~T2_E~0); {47387#true} is VALID [2022-02-21 04:24:32,789 INFO L290 TraceCheckUtils]: 13: Hoare triple {47387#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {47387#true} is VALID [2022-02-21 04:24:32,789 INFO L290 TraceCheckUtils]: 14: Hoare triple {47387#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {47387#true} is VALID [2022-02-21 04:24:32,789 INFO L290 TraceCheckUtils]: 15: Hoare triple {47387#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,790 INFO L290 TraceCheckUtils]: 16: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,790 INFO L290 TraceCheckUtils]: 17: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,790 INFO L290 TraceCheckUtils]: 18: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,791 INFO L290 TraceCheckUtils]: 19: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,791 INFO L290 TraceCheckUtils]: 20: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,791 INFO L290 TraceCheckUtils]: 21: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,792 INFO L290 TraceCheckUtils]: 22: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,792 INFO L290 TraceCheckUtils]: 23: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,792 INFO L290 TraceCheckUtils]: 24: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,793 INFO L290 TraceCheckUtils]: 25: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,793 INFO L290 TraceCheckUtils]: 26: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,793 INFO L290 TraceCheckUtils]: 27: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,794 INFO L290 TraceCheckUtils]: 28: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,794 INFO L290 TraceCheckUtils]: 29: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,794 INFO L290 TraceCheckUtils]: 30: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,795 INFO L290 TraceCheckUtils]: 31: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,795 INFO L290 TraceCheckUtils]: 32: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,795 INFO L290 TraceCheckUtils]: 33: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,796 INFO L290 TraceCheckUtils]: 34: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,796 INFO L290 TraceCheckUtils]: 35: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,796 INFO L290 TraceCheckUtils]: 36: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,796 INFO L290 TraceCheckUtils]: 37: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,797 INFO L290 TraceCheckUtils]: 38: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,797 INFO L290 TraceCheckUtils]: 39: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,797 INFO L290 TraceCheckUtils]: 40: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,798 INFO L290 TraceCheckUtils]: 41: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,798 INFO L290 TraceCheckUtils]: 42: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,798 INFO L290 TraceCheckUtils]: 43: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,799 INFO L290 TraceCheckUtils]: 44: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,799 INFO L290 TraceCheckUtils]: 45: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,799 INFO L290 TraceCheckUtils]: 46: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,800 INFO L290 TraceCheckUtils]: 47: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,800 INFO L290 TraceCheckUtils]: 48: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,800 INFO L290 TraceCheckUtils]: 49: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,801 INFO L290 TraceCheckUtils]: 50: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,801 INFO L290 TraceCheckUtils]: 51: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,801 INFO L290 TraceCheckUtils]: 52: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,802 INFO L290 TraceCheckUtils]: 53: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,802 INFO L290 TraceCheckUtils]: 54: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,802 INFO L290 TraceCheckUtils]: 55: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,803 INFO L290 TraceCheckUtils]: 56: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,803 INFO L290 TraceCheckUtils]: 57: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,803 INFO L290 TraceCheckUtils]: 58: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,804 INFO L290 TraceCheckUtils]: 59: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,804 INFO L290 TraceCheckUtils]: 60: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,804 INFO L290 TraceCheckUtils]: 61: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,805 INFO L290 TraceCheckUtils]: 62: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,805 INFO L290 TraceCheckUtils]: 63: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,805 INFO L290 TraceCheckUtils]: 64: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,806 INFO L290 TraceCheckUtils]: 65: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,831 INFO L290 TraceCheckUtils]: 66: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,832 INFO L290 TraceCheckUtils]: 67: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,832 INFO L290 TraceCheckUtils]: 68: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,832 INFO L290 TraceCheckUtils]: 69: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,832 INFO L290 TraceCheckUtils]: 70: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,833 INFO L290 TraceCheckUtils]: 71: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,833 INFO L290 TraceCheckUtils]: 72: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,833 INFO L290 TraceCheckUtils]: 73: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,833 INFO L290 TraceCheckUtils]: 74: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,834 INFO L290 TraceCheckUtils]: 75: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,834 INFO L290 TraceCheckUtils]: 76: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,834 INFO L290 TraceCheckUtils]: 77: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,835 INFO L290 TraceCheckUtils]: 78: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,835 INFO L290 TraceCheckUtils]: 79: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,835 INFO L290 TraceCheckUtils]: 80: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,835 INFO L290 TraceCheckUtils]: 81: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,836 INFO L290 TraceCheckUtils]: 82: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,836 INFO L290 TraceCheckUtils]: 83: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,836 INFO L290 TraceCheckUtils]: 84: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,836 INFO L290 TraceCheckUtils]: 85: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,837 INFO L290 TraceCheckUtils]: 86: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,837 INFO L290 TraceCheckUtils]: 87: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,837 INFO L290 TraceCheckUtils]: 88: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,838 INFO L290 TraceCheckUtils]: 89: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,838 INFO L290 TraceCheckUtils]: 90: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,838 INFO L290 TraceCheckUtils]: 91: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,838 INFO L290 TraceCheckUtils]: 92: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,839 INFO L290 TraceCheckUtils]: 93: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,839 INFO L290 TraceCheckUtils]: 94: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,839 INFO L290 TraceCheckUtils]: 95: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,839 INFO L290 TraceCheckUtils]: 96: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,840 INFO L290 TraceCheckUtils]: 97: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,840 INFO L290 TraceCheckUtils]: 98: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,840 INFO L290 TraceCheckUtils]: 99: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,841 INFO L290 TraceCheckUtils]: 100: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,841 INFO L290 TraceCheckUtils]: 101: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,841 INFO L290 TraceCheckUtils]: 102: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {47389#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:32,841 INFO L290 TraceCheckUtils]: 103: Hoare triple {47389#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {47388#false} is VALID [2022-02-21 04:24:32,841 INFO L290 TraceCheckUtils]: 104: Hoare triple {47388#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 105: Hoare triple {47388#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 106: Hoare triple {47388#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 107: Hoare triple {47388#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 108: Hoare triple {47388#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 109: Hoare triple {47388#false} assume 1 == ~E_1~0;~E_1~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 110: Hoare triple {47388#false} assume 1 == ~E_2~0;~E_2~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 111: Hoare triple {47388#false} assume !(1 == ~E_3~0); {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 112: Hoare triple {47388#false} assume 1 == ~E_4~0;~E_4~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 113: Hoare triple {47388#false} assume 1 == ~E_5~0;~E_5~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 114: Hoare triple {47388#false} assume 1 == ~E_6~0;~E_6~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 115: Hoare triple {47388#false} assume 1 == ~E_7~0;~E_7~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 116: Hoare triple {47388#false} assume 1 == ~E_8~0;~E_8~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 117: Hoare triple {47388#false} assume 1 == ~E_9~0;~E_9~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 118: Hoare triple {47388#false} assume 1 == ~E_10~0;~E_10~0 := 2; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 119: Hoare triple {47388#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 120: Hoare triple {47388#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 121: Hoare triple {47388#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 122: Hoare triple {47388#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {47388#false} is VALID [2022-02-21 04:24:32,842 INFO L290 TraceCheckUtils]: 123: Hoare triple {47388#false} assume !(0 == start_simulation_~tmp~3#1); {47388#false} is VALID [2022-02-21 04:24:32,843 INFO L290 TraceCheckUtils]: 124: Hoare triple {47388#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {47388#false} is VALID [2022-02-21 04:24:32,843 INFO L290 TraceCheckUtils]: 125: Hoare triple {47388#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {47388#false} is VALID [2022-02-21 04:24:32,843 INFO L290 TraceCheckUtils]: 126: Hoare triple {47388#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {47388#false} is VALID [2022-02-21 04:24:32,843 INFO L290 TraceCheckUtils]: 127: Hoare triple {47388#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {47388#false} is VALID [2022-02-21 04:24:32,843 INFO L290 TraceCheckUtils]: 128: Hoare triple {47388#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {47388#false} is VALID [2022-02-21 04:24:32,843 INFO L290 TraceCheckUtils]: 129: Hoare triple {47388#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {47388#false} is VALID [2022-02-21 04:24:32,843 INFO L290 TraceCheckUtils]: 130: Hoare triple {47388#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {47388#false} is VALID [2022-02-21 04:24:32,843 INFO L290 TraceCheckUtils]: 131: Hoare triple {47388#false} assume !(0 != start_simulation_~tmp___0~1#1); {47388#false} is VALID [2022-02-21 04:24:32,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:32,843 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:32,843 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227261221] [2022-02-21 04:24:32,843 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1227261221] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:32,844 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:32,844 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:32,844 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1698034076] [2022-02-21 04:24:32,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:32,844 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:32,844 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:32,844 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:32,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:32,845 INFO L87 Difference]: Start difference. First operand 1278 states and 1893 transitions. cyclomatic complexity: 616 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:35,242 INFO L93 Difference]: Finished difference Result 2438 states and 3604 transitions. [2022-02-21 04:24:35,242 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:35,242 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,302 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:35,303 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2438 states and 3604 transitions. [2022-02-21 04:24:35,435 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2282 [2022-02-21 04:24:35,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2438 states to 2438 states and 3604 transitions. [2022-02-21 04:24:35,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2438 [2022-02-21 04:24:35,560 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2438 [2022-02-21 04:24:35,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2438 states and 3604 transitions. [2022-02-21 04:24:35,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:35,562 INFO L681 BuchiCegarLoop]: Abstraction has 2438 states and 3604 transitions. [2022-02-21 04:24:35,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2438 states and 3604 transitions. [2022-02-21 04:24:35,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2438 to 2438. [2022-02-21 04:24:35,587 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:35,589 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2438 states and 3604 transitions. Second operand has 2438 states, 2438 states have (on average 1.4782608695652173) internal successors, (3604), 2437 states have internal predecessors, (3604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,590 INFO L74 IsIncluded]: Start isIncluded. First operand 2438 states and 3604 transitions. Second operand has 2438 states, 2438 states have (on average 1.4782608695652173) internal successors, (3604), 2437 states have internal predecessors, (3604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,592 INFO L87 Difference]: Start difference. First operand 2438 states and 3604 transitions. Second operand has 2438 states, 2438 states have (on average 1.4782608695652173) internal successors, (3604), 2437 states have internal predecessors, (3604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:35,721 INFO L93 Difference]: Finished difference Result 2438 states and 3604 transitions. [2022-02-21 04:24:35,721 INFO L276 IsEmpty]: Start isEmpty. Operand 2438 states and 3604 transitions. [2022-02-21 04:24:35,723 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:35,723 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:35,726 INFO L74 IsIncluded]: Start isIncluded. First operand has 2438 states, 2438 states have (on average 1.4782608695652173) internal successors, (3604), 2437 states have internal predecessors, (3604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2438 states and 3604 transitions. [2022-02-21 04:24:35,727 INFO L87 Difference]: Start difference. First operand has 2438 states, 2438 states have (on average 1.4782608695652173) internal successors, (3604), 2437 states have internal predecessors, (3604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2438 states and 3604 transitions. [2022-02-21 04:24:35,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:35,861 INFO L93 Difference]: Finished difference Result 2438 states and 3604 transitions. [2022-02-21 04:24:35,861 INFO L276 IsEmpty]: Start isEmpty. Operand 2438 states and 3604 transitions. [2022-02-21 04:24:35,863 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:35,863 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:35,864 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:35,864 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:35,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2438 states, 2438 states have (on average 1.4782608695652173) internal successors, (3604), 2437 states have internal predecessors, (3604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2438 states to 2438 states and 3604 transitions. [2022-02-21 04:24:36,055 INFO L704 BuchiCegarLoop]: Abstraction has 2438 states and 3604 transitions. [2022-02-21 04:24:36,055 INFO L587 BuchiCegarLoop]: Abstraction has 2438 states and 3604 transitions. [2022-02-21 04:24:36,055 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:24:36,055 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2438 states and 3604 transitions. [2022-02-21 04:24:36,061 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2282 [2022-02-21 04:24:36,061 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:36,061 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:36,062 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:36,062 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:36,063 INFO L791 eck$LassoCheckResult]: Stem: 50823#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 50824#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 51144#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51121#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51122#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 51155#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51156#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50383#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50100#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50101#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51031#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 51032#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 51015#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 51016#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 51054#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50155#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50156#L1006 assume !(0 == ~M_E~0); 50003#L1006-2 assume !(0 == ~T1_E~0); 50004#L1011-1 assume !(0 == ~T2_E~0); 51081#L1016-1 assume !(0 == ~T3_E~0); 51105#L1021-1 assume !(0 == ~T4_E~0); 49883#L1026-1 assume !(0 == ~T5_E~0); 49884#L1031-1 assume !(0 == ~T6_E~0); 50769#L1036-1 assume !(0 == ~T7_E~0); 50765#L1041-1 assume !(0 == ~T8_E~0); 50766#L1046-1 assume !(0 == ~T9_E~0); 50186#L1051-1 assume !(0 == ~T10_E~0); 50187#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 50906#L1061-1 assume !(0 == ~E_2~0); 50104#L1066-1 assume !(0 == ~E_3~0); 50105#L1071-1 assume !(0 == ~E_4~0); 50881#L1076-1 assume !(0 == ~E_5~0); 50014#L1081-1 assume !(0 == ~E_6~0); 50015#L1086-1 assume !(0 == ~E_7~0); 50358#L1091-1 assume !(0 == ~E_8~0); 51069#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 51070#L1101-1 assume !(0 == ~E_10~0); 50422#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50423#L484 assume !(1 == ~m_pc~0); 50063#L484-2 is_master_triggered_~__retres1~0#1 := 0; 50062#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50686#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50984#L1245 assume !(0 != activate_threads_~tmp~1#1); 50985#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50757#L503 assume 1 == ~t1_pc~0; 50758#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50774#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50897#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50540#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 49912#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49913#L522 assume !(1 == ~t2_pc~0); 50722#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50117#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50118#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50595#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 51033#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51116#L541 assume 1 == ~t3_pc~0; 50671#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50482#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50295#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50296#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 50725#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50726#L560 assume !(1 == ~t4_pc~0); 49997#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 49996#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50629#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49879#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 49880#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50169#L579 assume 1 == ~t5_pc~0; 49830#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49831#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49940#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50632#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 51103#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51138#L598 assume 1 == ~t6_pc~0; 50263#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50264#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50572#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51007#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 50806#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50748#L617 assume !(1 == ~t7_pc~0); 50236#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 50235#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50527#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50528#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50459#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50460#L636 assume 1 == ~t8_pc~0; 50626#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50627#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50424#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50425#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 50579#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50580#L655 assume !(1 == ~t9_pc~0); 50609#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 50610#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50215#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50216#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 50825#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50826#L674 assume 1 == ~t10_pc~0; 49990#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49991#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51119#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51167#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 50569#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50570#L1119 assume !(1 == ~M_E~0); 50086#L1119-2 assume !(1 == ~T1_E~0); 50087#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50502#L1129-1 assume !(1 == ~T3_E~0); 49904#L1134-1 assume !(1 == ~T4_E~0); 51525#L1139-1 assume !(1 == ~T5_E~0); 51523#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51516#L1149-1 assume !(1 == ~T7_E~0); 51509#L1154-1 assume !(1 == ~T8_E~0); 51507#L1159-1 assume !(1 == ~T9_E~0); 51506#L1164-1 assume !(1 == ~T10_E~0); 51505#L1169-1 assume !(1 == ~E_1~0); 51504#L1174-1 assume !(1 == ~E_2~0); 51502#L1179-1 assume !(1 == ~E_3~0); 51233#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 51221#L1189-1 assume !(1 == ~E_5~0); 51219#L1194-1 assume !(1 == ~E_6~0); 51217#L1199-1 assume !(1 == ~E_7~0); 51215#L1204-1 assume !(1 == ~E_8~0); 51213#L1209-1 assume !(1 == ~E_9~0); 51211#L1214-1 assume !(1 == ~E_10~0); 51206#L1219-1 assume { :end_inline_reset_delta_events } true; 51200#L1520-2 [2022-02-21 04:24:36,063 INFO L793 eck$LassoCheckResult]: Loop: 51200#L1520-2 assume !false; 51196#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51195#L981 assume !false; 51194#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51185#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51182#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51181#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 51180#L836 assume !(0 != eval_~tmp~0#1); 51179#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51178#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51177#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51176#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51175#L1011-3 assume !(0 == ~T2_E~0); 51078#L1016-3 assume !(0 == ~T3_E~0); 50976#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50642#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50643#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50899#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50900#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50965#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50966#L1051-3 assume !(0 == ~T10_E~0); 50901#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50183#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50184#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50185#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51089#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49967#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49968#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50022#L1091-3 assume !(0 == ~E_8~0); 50023#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 51055#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51056#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51456#L484-33 assume 1 == ~m_pc~0; 51453#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51451#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51449#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 51447#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51445#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51442#L503-33 assume 1 == ~t1_pc~0; 51440#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51437#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51435#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 51433#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51431#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51428#L522-33 assume 1 == ~t2_pc~0; 51425#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51423#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51421#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51419#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51417#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51414#L541-33 assume !(1 == ~t3_pc~0); 51411#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 51409#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51407#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51405#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51403#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51400#L560-33 assume 1 == ~t4_pc~0; 51397#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51395#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51393#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51391#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 51390#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51389#L579-33 assume 1 == ~t5_pc~0; 51387#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51386#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51385#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51384#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51383#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51382#L598-33 assume !(1 == ~t6_pc~0); 51380#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 51379#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51378#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51377#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51376#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51375#L617-33 assume 1 == ~t7_pc~0; 51373#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51372#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51371#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51370#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 51369#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51368#L636-33 assume !(1 == ~t8_pc~0); 51366#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 51365#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51364#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51363#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51362#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51361#L655-33 assume !(1 == ~t9_pc~0); 51360#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 51358#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51357#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51356#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51355#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51354#L674-33 assume !(1 == ~t10_pc~0); 51352#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 51350#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51348#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51346#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51344#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51342#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51339#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51337#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51173#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51159#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51333#L1139-3 assume !(1 == ~T5_E~0); 51331#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51328#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51326#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 51324#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 51322#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51320#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51318#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51315#L1179-3 assume !(1 == ~E_3~0); 51313#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51311#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51309#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 51307#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 51305#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51303#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51301#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51300#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51275#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51273#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51271#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 51270#L1539 assume !(0 == start_simulation_~tmp~3#1); 51265#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 51226#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 51220#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 51218#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 51216#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51214#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51212#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 51207#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 51200#L1520-2 [2022-02-21 04:24:36,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:36,064 INFO L85 PathProgramCache]: Analyzing trace with hash -388783629, now seen corresponding path program 1 times [2022-02-21 04:24:36,064 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:36,064 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649178588] [2022-02-21 04:24:36,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:36,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:36,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:36,095 INFO L290 TraceCheckUtils]: 0: Hoare triple {57147#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,096 INFO L290 TraceCheckUtils]: 1: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,096 INFO L290 TraceCheckUtils]: 2: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,097 INFO L290 TraceCheckUtils]: 3: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,097 INFO L290 TraceCheckUtils]: 4: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,097 INFO L290 TraceCheckUtils]: 5: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,098 INFO L290 TraceCheckUtils]: 6: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,098 INFO L290 TraceCheckUtils]: 7: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,098 INFO L290 TraceCheckUtils]: 8: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,099 INFO L290 TraceCheckUtils]: 9: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,099 INFO L290 TraceCheckUtils]: 10: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,099 INFO L290 TraceCheckUtils]: 11: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,100 INFO L290 TraceCheckUtils]: 12: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,100 INFO L290 TraceCheckUtils]: 13: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,101 INFO L290 TraceCheckUtils]: 14: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,101 INFO L290 TraceCheckUtils]: 15: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,101 INFO L290 TraceCheckUtils]: 16: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~M_E~0); {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,102 INFO L290 TraceCheckUtils]: 17: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~T1_E~0); {57149#(= ~T2_E~0 ~E_1~0)} is VALID [2022-02-21 04:24:36,102 INFO L290 TraceCheckUtils]: 18: Hoare triple {57149#(= ~T2_E~0 ~E_1~0)} assume !(0 == ~T2_E~0); {57150#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:36,102 INFO L290 TraceCheckUtils]: 19: Hoare triple {57150#(not (= ~E_1~0 0))} assume !(0 == ~T3_E~0); {57150#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:36,103 INFO L290 TraceCheckUtils]: 20: Hoare triple {57150#(not (= ~E_1~0 0))} assume !(0 == ~T4_E~0); {57150#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:36,103 INFO L290 TraceCheckUtils]: 21: Hoare triple {57150#(not (= ~E_1~0 0))} assume !(0 == ~T5_E~0); {57150#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:36,103 INFO L290 TraceCheckUtils]: 22: Hoare triple {57150#(not (= ~E_1~0 0))} assume !(0 == ~T6_E~0); {57150#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:36,104 INFO L290 TraceCheckUtils]: 23: Hoare triple {57150#(not (= ~E_1~0 0))} assume !(0 == ~T7_E~0); {57150#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:36,104 INFO L290 TraceCheckUtils]: 24: Hoare triple {57150#(not (= ~E_1~0 0))} assume !(0 == ~T8_E~0); {57150#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:36,104 INFO L290 TraceCheckUtils]: 25: Hoare triple {57150#(not (= ~E_1~0 0))} assume !(0 == ~T9_E~0); {57150#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:36,104 INFO L290 TraceCheckUtils]: 26: Hoare triple {57150#(not (= ~E_1~0 0))} assume !(0 == ~T10_E~0); {57150#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:24:36,105 INFO L290 TraceCheckUtils]: 27: Hoare triple {57150#(not (= ~E_1~0 0))} assume 0 == ~E_1~0;~E_1~0 := 1; {57148#false} is VALID [2022-02-21 04:24:36,105 INFO L290 TraceCheckUtils]: 28: Hoare triple {57148#false} assume !(0 == ~E_2~0); {57148#false} is VALID [2022-02-21 04:24:36,105 INFO L290 TraceCheckUtils]: 29: Hoare triple {57148#false} assume !(0 == ~E_3~0); {57148#false} is VALID [2022-02-21 04:24:36,105 INFO L290 TraceCheckUtils]: 30: Hoare triple {57148#false} assume !(0 == ~E_4~0); {57148#false} is VALID [2022-02-21 04:24:36,105 INFO L290 TraceCheckUtils]: 31: Hoare triple {57148#false} assume !(0 == ~E_5~0); {57148#false} is VALID [2022-02-21 04:24:36,106 INFO L290 TraceCheckUtils]: 32: Hoare triple {57148#false} assume !(0 == ~E_6~0); {57148#false} is VALID [2022-02-21 04:24:36,106 INFO L290 TraceCheckUtils]: 33: Hoare triple {57148#false} assume !(0 == ~E_7~0); {57148#false} is VALID [2022-02-21 04:24:36,106 INFO L290 TraceCheckUtils]: 34: Hoare triple {57148#false} assume !(0 == ~E_8~0); {57148#false} is VALID [2022-02-21 04:24:36,106 INFO L290 TraceCheckUtils]: 35: Hoare triple {57148#false} assume 0 == ~E_9~0;~E_9~0 := 1; {57148#false} is VALID [2022-02-21 04:24:36,106 INFO L290 TraceCheckUtils]: 36: Hoare triple {57148#false} assume !(0 == ~E_10~0); {57148#false} is VALID [2022-02-21 04:24:36,106 INFO L290 TraceCheckUtils]: 37: Hoare triple {57148#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {57148#false} is VALID [2022-02-21 04:24:36,106 INFO L290 TraceCheckUtils]: 38: Hoare triple {57148#false} assume !(1 == ~m_pc~0); {57148#false} is VALID [2022-02-21 04:24:36,107 INFO L290 TraceCheckUtils]: 39: Hoare triple {57148#false} is_master_triggered_~__retres1~0#1 := 0; {57148#false} is VALID [2022-02-21 04:24:36,107 INFO L290 TraceCheckUtils]: 40: Hoare triple {57148#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {57148#false} is VALID [2022-02-21 04:24:36,107 INFO L290 TraceCheckUtils]: 41: Hoare triple {57148#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {57148#false} is VALID [2022-02-21 04:24:36,107 INFO L290 TraceCheckUtils]: 42: Hoare triple {57148#false} assume !(0 != activate_threads_~tmp~1#1); {57148#false} is VALID [2022-02-21 04:24:36,107 INFO L290 TraceCheckUtils]: 43: Hoare triple {57148#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {57148#false} is VALID [2022-02-21 04:24:36,107 INFO L290 TraceCheckUtils]: 44: Hoare triple {57148#false} assume 1 == ~t1_pc~0; {57148#false} is VALID [2022-02-21 04:24:36,107 INFO L290 TraceCheckUtils]: 45: Hoare triple {57148#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {57148#false} is VALID [2022-02-21 04:24:36,107 INFO L290 TraceCheckUtils]: 46: Hoare triple {57148#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {57148#false} is VALID [2022-02-21 04:24:36,108 INFO L290 TraceCheckUtils]: 47: Hoare triple {57148#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {57148#false} is VALID [2022-02-21 04:24:36,108 INFO L290 TraceCheckUtils]: 48: Hoare triple {57148#false} assume !(0 != activate_threads_~tmp___0~0#1); {57148#false} is VALID [2022-02-21 04:24:36,108 INFO L290 TraceCheckUtils]: 49: Hoare triple {57148#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {57148#false} is VALID [2022-02-21 04:24:36,108 INFO L290 TraceCheckUtils]: 50: Hoare triple {57148#false} assume !(1 == ~t2_pc~0); {57148#false} is VALID [2022-02-21 04:24:36,108 INFO L290 TraceCheckUtils]: 51: Hoare triple {57148#false} is_transmit2_triggered_~__retres1~2#1 := 0; {57148#false} is VALID [2022-02-21 04:24:36,108 INFO L290 TraceCheckUtils]: 52: Hoare triple {57148#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {57148#false} is VALID [2022-02-21 04:24:36,108 INFO L290 TraceCheckUtils]: 53: Hoare triple {57148#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {57148#false} is VALID [2022-02-21 04:24:36,109 INFO L290 TraceCheckUtils]: 54: Hoare triple {57148#false} assume !(0 != activate_threads_~tmp___1~0#1); {57148#false} is VALID [2022-02-21 04:24:36,109 INFO L290 TraceCheckUtils]: 55: Hoare triple {57148#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {57148#false} is VALID [2022-02-21 04:24:36,109 INFO L290 TraceCheckUtils]: 56: Hoare triple {57148#false} assume 1 == ~t3_pc~0; {57148#false} is VALID [2022-02-21 04:24:36,109 INFO L290 TraceCheckUtils]: 57: Hoare triple {57148#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {57148#false} is VALID [2022-02-21 04:24:36,109 INFO L290 TraceCheckUtils]: 58: Hoare triple {57148#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {57148#false} is VALID [2022-02-21 04:24:36,109 INFO L290 TraceCheckUtils]: 59: Hoare triple {57148#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {57148#false} is VALID [2022-02-21 04:24:36,109 INFO L290 TraceCheckUtils]: 60: Hoare triple {57148#false} assume !(0 != activate_threads_~tmp___2~0#1); {57148#false} is VALID [2022-02-21 04:24:36,110 INFO L290 TraceCheckUtils]: 61: Hoare triple {57148#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {57148#false} is VALID [2022-02-21 04:24:36,110 INFO L290 TraceCheckUtils]: 62: Hoare triple {57148#false} assume !(1 == ~t4_pc~0); {57148#false} is VALID [2022-02-21 04:24:36,110 INFO L290 TraceCheckUtils]: 63: Hoare triple {57148#false} is_transmit4_triggered_~__retres1~4#1 := 0; {57148#false} is VALID [2022-02-21 04:24:36,110 INFO L290 TraceCheckUtils]: 64: Hoare triple {57148#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {57148#false} is VALID [2022-02-21 04:24:36,110 INFO L290 TraceCheckUtils]: 65: Hoare triple {57148#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {57148#false} is VALID [2022-02-21 04:24:36,110 INFO L290 TraceCheckUtils]: 66: Hoare triple {57148#false} assume !(0 != activate_threads_~tmp___3~0#1); {57148#false} is VALID [2022-02-21 04:24:36,110 INFO L290 TraceCheckUtils]: 67: Hoare triple {57148#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {57148#false} is VALID [2022-02-21 04:24:36,111 INFO L290 TraceCheckUtils]: 68: Hoare triple {57148#false} assume 1 == ~t5_pc~0; {57148#false} is VALID [2022-02-21 04:24:36,111 INFO L290 TraceCheckUtils]: 69: Hoare triple {57148#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {57148#false} is VALID [2022-02-21 04:24:36,111 INFO L290 TraceCheckUtils]: 70: Hoare triple {57148#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {57148#false} is VALID [2022-02-21 04:24:36,111 INFO L290 TraceCheckUtils]: 71: Hoare triple {57148#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {57148#false} is VALID [2022-02-21 04:24:36,111 INFO L290 TraceCheckUtils]: 72: Hoare triple {57148#false} assume !(0 != activate_threads_~tmp___4~0#1); {57148#false} is VALID [2022-02-21 04:24:36,111 INFO L290 TraceCheckUtils]: 73: Hoare triple {57148#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {57148#false} is VALID [2022-02-21 04:24:36,111 INFO L290 TraceCheckUtils]: 74: Hoare triple {57148#false} assume 1 == ~t6_pc~0; {57148#false} is VALID [2022-02-21 04:24:36,112 INFO L290 TraceCheckUtils]: 75: Hoare triple {57148#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {57148#false} is VALID [2022-02-21 04:24:36,112 INFO L290 TraceCheckUtils]: 76: Hoare triple {57148#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {57148#false} is VALID [2022-02-21 04:24:36,112 INFO L290 TraceCheckUtils]: 77: Hoare triple {57148#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {57148#false} is VALID [2022-02-21 04:24:36,112 INFO L290 TraceCheckUtils]: 78: Hoare triple {57148#false} assume !(0 != activate_threads_~tmp___5~0#1); {57148#false} is VALID [2022-02-21 04:24:36,112 INFO L290 TraceCheckUtils]: 79: Hoare triple {57148#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {57148#false} is VALID [2022-02-21 04:24:36,112 INFO L290 TraceCheckUtils]: 80: Hoare triple {57148#false} assume !(1 == ~t7_pc~0); {57148#false} is VALID [2022-02-21 04:24:36,112 INFO L290 TraceCheckUtils]: 81: Hoare triple {57148#false} is_transmit7_triggered_~__retres1~7#1 := 0; {57148#false} is VALID [2022-02-21 04:24:36,113 INFO L290 TraceCheckUtils]: 82: Hoare triple {57148#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {57148#false} is VALID [2022-02-21 04:24:36,113 INFO L290 TraceCheckUtils]: 83: Hoare triple {57148#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {57148#false} is VALID [2022-02-21 04:24:36,113 INFO L290 TraceCheckUtils]: 84: Hoare triple {57148#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {57148#false} is VALID [2022-02-21 04:24:36,113 INFO L290 TraceCheckUtils]: 85: Hoare triple {57148#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {57148#false} is VALID [2022-02-21 04:24:36,113 INFO L290 TraceCheckUtils]: 86: Hoare triple {57148#false} assume 1 == ~t8_pc~0; {57148#false} is VALID [2022-02-21 04:24:36,113 INFO L290 TraceCheckUtils]: 87: Hoare triple {57148#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {57148#false} is VALID [2022-02-21 04:24:36,113 INFO L290 TraceCheckUtils]: 88: Hoare triple {57148#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {57148#false} is VALID [2022-02-21 04:24:36,113 INFO L290 TraceCheckUtils]: 89: Hoare triple {57148#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {57148#false} is VALID [2022-02-21 04:24:36,114 INFO L290 TraceCheckUtils]: 90: Hoare triple {57148#false} assume !(0 != activate_threads_~tmp___7~0#1); {57148#false} is VALID [2022-02-21 04:24:36,114 INFO L290 TraceCheckUtils]: 91: Hoare triple {57148#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {57148#false} is VALID [2022-02-21 04:24:36,114 INFO L290 TraceCheckUtils]: 92: Hoare triple {57148#false} assume !(1 == ~t9_pc~0); {57148#false} is VALID [2022-02-21 04:24:36,114 INFO L290 TraceCheckUtils]: 93: Hoare triple {57148#false} is_transmit9_triggered_~__retres1~9#1 := 0; {57148#false} is VALID [2022-02-21 04:24:36,114 INFO L290 TraceCheckUtils]: 94: Hoare triple {57148#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {57148#false} is VALID [2022-02-21 04:24:36,114 INFO L290 TraceCheckUtils]: 95: Hoare triple {57148#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {57148#false} is VALID [2022-02-21 04:24:36,114 INFO L290 TraceCheckUtils]: 96: Hoare triple {57148#false} assume !(0 != activate_threads_~tmp___8~0#1); {57148#false} is VALID [2022-02-21 04:24:36,115 INFO L290 TraceCheckUtils]: 97: Hoare triple {57148#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {57148#false} is VALID [2022-02-21 04:24:36,115 INFO L290 TraceCheckUtils]: 98: Hoare triple {57148#false} assume 1 == ~t10_pc~0; {57148#false} is VALID [2022-02-21 04:24:36,115 INFO L290 TraceCheckUtils]: 99: Hoare triple {57148#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {57148#false} is VALID [2022-02-21 04:24:36,115 INFO L290 TraceCheckUtils]: 100: Hoare triple {57148#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {57148#false} is VALID [2022-02-21 04:24:36,115 INFO L290 TraceCheckUtils]: 101: Hoare triple {57148#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {57148#false} is VALID [2022-02-21 04:24:36,115 INFO L290 TraceCheckUtils]: 102: Hoare triple {57148#false} assume !(0 != activate_threads_~tmp___9~0#1); {57148#false} is VALID [2022-02-21 04:24:36,115 INFO L290 TraceCheckUtils]: 103: Hoare triple {57148#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {57148#false} is VALID [2022-02-21 04:24:36,116 INFO L290 TraceCheckUtils]: 104: Hoare triple {57148#false} assume !(1 == ~M_E~0); {57148#false} is VALID [2022-02-21 04:24:36,116 INFO L290 TraceCheckUtils]: 105: Hoare triple {57148#false} assume !(1 == ~T1_E~0); {57148#false} is VALID [2022-02-21 04:24:36,116 INFO L290 TraceCheckUtils]: 106: Hoare triple {57148#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {57148#false} is VALID [2022-02-21 04:24:36,116 INFO L290 TraceCheckUtils]: 107: Hoare triple {57148#false} assume !(1 == ~T3_E~0); {57148#false} is VALID [2022-02-21 04:24:36,116 INFO L290 TraceCheckUtils]: 108: Hoare triple {57148#false} assume !(1 == ~T4_E~0); {57148#false} is VALID [2022-02-21 04:24:36,116 INFO L290 TraceCheckUtils]: 109: Hoare triple {57148#false} assume !(1 == ~T5_E~0); {57148#false} is VALID [2022-02-21 04:24:36,116 INFO L290 TraceCheckUtils]: 110: Hoare triple {57148#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {57148#false} is VALID [2022-02-21 04:24:36,117 INFO L290 TraceCheckUtils]: 111: Hoare triple {57148#false} assume !(1 == ~T7_E~0); {57148#false} is VALID [2022-02-21 04:24:36,117 INFO L290 TraceCheckUtils]: 112: Hoare triple {57148#false} assume !(1 == ~T8_E~0); {57148#false} is VALID [2022-02-21 04:24:36,117 INFO L290 TraceCheckUtils]: 113: Hoare triple {57148#false} assume !(1 == ~T9_E~0); {57148#false} is VALID [2022-02-21 04:24:36,117 INFO L290 TraceCheckUtils]: 114: Hoare triple {57148#false} assume !(1 == ~T10_E~0); {57148#false} is VALID [2022-02-21 04:24:36,117 INFO L290 TraceCheckUtils]: 115: Hoare triple {57148#false} assume !(1 == ~E_1~0); {57148#false} is VALID [2022-02-21 04:24:36,117 INFO L290 TraceCheckUtils]: 116: Hoare triple {57148#false} assume !(1 == ~E_2~0); {57148#false} is VALID [2022-02-21 04:24:36,117 INFO L290 TraceCheckUtils]: 117: Hoare triple {57148#false} assume !(1 == ~E_3~0); {57148#false} is VALID [2022-02-21 04:24:36,118 INFO L290 TraceCheckUtils]: 118: Hoare triple {57148#false} assume 1 == ~E_4~0;~E_4~0 := 2; {57148#false} is VALID [2022-02-21 04:24:36,118 INFO L290 TraceCheckUtils]: 119: Hoare triple {57148#false} assume !(1 == ~E_5~0); {57148#false} is VALID [2022-02-21 04:24:36,118 INFO L290 TraceCheckUtils]: 120: Hoare triple {57148#false} assume !(1 == ~E_6~0); {57148#false} is VALID [2022-02-21 04:24:36,118 INFO L290 TraceCheckUtils]: 121: Hoare triple {57148#false} assume !(1 == ~E_7~0); {57148#false} is VALID [2022-02-21 04:24:36,118 INFO L290 TraceCheckUtils]: 122: Hoare triple {57148#false} assume !(1 == ~E_8~0); {57148#false} is VALID [2022-02-21 04:24:36,118 INFO L290 TraceCheckUtils]: 123: Hoare triple {57148#false} assume !(1 == ~E_9~0); {57148#false} is VALID [2022-02-21 04:24:36,118 INFO L290 TraceCheckUtils]: 124: Hoare triple {57148#false} assume !(1 == ~E_10~0); {57148#false} is VALID [2022-02-21 04:24:36,119 INFO L290 TraceCheckUtils]: 125: Hoare triple {57148#false} assume { :end_inline_reset_delta_events } true; {57148#false} is VALID [2022-02-21 04:24:36,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:36,119 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:36,119 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649178588] [2022-02-21 04:24:36,119 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1649178588] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:36,120 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:36,120 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:36,120 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [87158463] [2022-02-21 04:24:36,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:36,120 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:36,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:36,121 INFO L85 PathProgramCache]: Analyzing trace with hash -1563982486, now seen corresponding path program 1 times [2022-02-21 04:24:36,121 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:36,121 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588486116] [2022-02-21 04:24:36,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:36,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:36,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:36,155 INFO L290 TraceCheckUtils]: 0: Hoare triple {57151#true} assume !false; {57151#true} is VALID [2022-02-21 04:24:36,155 INFO L290 TraceCheckUtils]: 1: Hoare triple {57151#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {57151#true} is VALID [2022-02-21 04:24:36,155 INFO L290 TraceCheckUtils]: 2: Hoare triple {57151#true} assume !false; {57151#true} is VALID [2022-02-21 04:24:36,155 INFO L290 TraceCheckUtils]: 3: Hoare triple {57151#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {57151#true} is VALID [2022-02-21 04:24:36,156 INFO L290 TraceCheckUtils]: 4: Hoare triple {57151#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {57151#true} is VALID [2022-02-21 04:24:36,156 INFO L290 TraceCheckUtils]: 5: Hoare triple {57151#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {57151#true} is VALID [2022-02-21 04:24:36,156 INFO L290 TraceCheckUtils]: 6: Hoare triple {57151#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {57151#true} is VALID [2022-02-21 04:24:36,156 INFO L290 TraceCheckUtils]: 7: Hoare triple {57151#true} assume !(0 != eval_~tmp~0#1); {57151#true} is VALID [2022-02-21 04:24:36,156 INFO L290 TraceCheckUtils]: 8: Hoare triple {57151#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {57151#true} is VALID [2022-02-21 04:24:36,156 INFO L290 TraceCheckUtils]: 9: Hoare triple {57151#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {57151#true} is VALID [2022-02-21 04:24:36,156 INFO L290 TraceCheckUtils]: 10: Hoare triple {57151#true} assume 0 == ~M_E~0;~M_E~0 := 1; {57151#true} is VALID [2022-02-21 04:24:36,157 INFO L290 TraceCheckUtils]: 11: Hoare triple {57151#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {57151#true} is VALID [2022-02-21 04:24:36,157 INFO L290 TraceCheckUtils]: 12: Hoare triple {57151#true} assume !(0 == ~T2_E~0); {57151#true} is VALID [2022-02-21 04:24:36,157 INFO L290 TraceCheckUtils]: 13: Hoare triple {57151#true} assume !(0 == ~T3_E~0); {57151#true} is VALID [2022-02-21 04:24:36,157 INFO L290 TraceCheckUtils]: 14: Hoare triple {57151#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {57151#true} is VALID [2022-02-21 04:24:36,157 INFO L290 TraceCheckUtils]: 15: Hoare triple {57151#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,158 INFO L290 TraceCheckUtils]: 16: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,158 INFO L290 TraceCheckUtils]: 17: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,159 INFO L290 TraceCheckUtils]: 18: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,159 INFO L290 TraceCheckUtils]: 19: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,159 INFO L290 TraceCheckUtils]: 20: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,160 INFO L290 TraceCheckUtils]: 21: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,160 INFO L290 TraceCheckUtils]: 22: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,160 INFO L290 TraceCheckUtils]: 23: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,161 INFO L290 TraceCheckUtils]: 24: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,161 INFO L290 TraceCheckUtils]: 25: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,161 INFO L290 TraceCheckUtils]: 26: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,162 INFO L290 TraceCheckUtils]: 27: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,162 INFO L290 TraceCheckUtils]: 28: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,162 INFO L290 TraceCheckUtils]: 29: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,163 INFO L290 TraceCheckUtils]: 30: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,163 INFO L290 TraceCheckUtils]: 31: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,163 INFO L290 TraceCheckUtils]: 32: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,164 INFO L290 TraceCheckUtils]: 33: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,164 INFO L290 TraceCheckUtils]: 34: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,165 INFO L290 TraceCheckUtils]: 35: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,165 INFO L290 TraceCheckUtils]: 36: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,165 INFO L290 TraceCheckUtils]: 37: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,166 INFO L290 TraceCheckUtils]: 38: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,166 INFO L290 TraceCheckUtils]: 39: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,166 INFO L290 TraceCheckUtils]: 40: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,167 INFO L290 TraceCheckUtils]: 41: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,167 INFO L290 TraceCheckUtils]: 42: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,168 INFO L290 TraceCheckUtils]: 43: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,168 INFO L290 TraceCheckUtils]: 44: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,168 INFO L290 TraceCheckUtils]: 45: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,169 INFO L290 TraceCheckUtils]: 46: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,169 INFO L290 TraceCheckUtils]: 47: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,169 INFO L290 TraceCheckUtils]: 48: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,170 INFO L290 TraceCheckUtils]: 49: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,170 INFO L290 TraceCheckUtils]: 50: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,170 INFO L290 TraceCheckUtils]: 51: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,171 INFO L290 TraceCheckUtils]: 52: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,171 INFO L290 TraceCheckUtils]: 53: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,172 INFO L290 TraceCheckUtils]: 54: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,172 INFO L290 TraceCheckUtils]: 55: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,172 INFO L290 TraceCheckUtils]: 56: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,173 INFO L290 TraceCheckUtils]: 57: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,173 INFO L290 TraceCheckUtils]: 58: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,173 INFO L290 TraceCheckUtils]: 59: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,174 INFO L290 TraceCheckUtils]: 60: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,174 INFO L290 TraceCheckUtils]: 61: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,174 INFO L290 TraceCheckUtils]: 62: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,175 INFO L290 TraceCheckUtils]: 63: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,175 INFO L290 TraceCheckUtils]: 64: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,176 INFO L290 TraceCheckUtils]: 65: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,176 INFO L290 TraceCheckUtils]: 66: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,176 INFO L290 TraceCheckUtils]: 67: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,177 INFO L290 TraceCheckUtils]: 68: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,177 INFO L290 TraceCheckUtils]: 69: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,177 INFO L290 TraceCheckUtils]: 70: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,178 INFO L290 TraceCheckUtils]: 71: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,178 INFO L290 TraceCheckUtils]: 72: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,178 INFO L290 TraceCheckUtils]: 73: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,179 INFO L290 TraceCheckUtils]: 74: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,179 INFO L290 TraceCheckUtils]: 75: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,179 INFO L290 TraceCheckUtils]: 76: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,180 INFO L290 TraceCheckUtils]: 77: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,180 INFO L290 TraceCheckUtils]: 78: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,180 INFO L290 TraceCheckUtils]: 79: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,181 INFO L290 TraceCheckUtils]: 80: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,181 INFO L290 TraceCheckUtils]: 81: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,181 INFO L290 TraceCheckUtils]: 82: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,182 INFO L290 TraceCheckUtils]: 83: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,182 INFO L290 TraceCheckUtils]: 84: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,183 INFO L290 TraceCheckUtils]: 85: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,183 INFO L290 TraceCheckUtils]: 86: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,183 INFO L290 TraceCheckUtils]: 87: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,184 INFO L290 TraceCheckUtils]: 88: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,184 INFO L290 TraceCheckUtils]: 89: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,184 INFO L290 TraceCheckUtils]: 90: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,185 INFO L290 TraceCheckUtils]: 91: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,185 INFO L290 TraceCheckUtils]: 92: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,186 INFO L290 TraceCheckUtils]: 93: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,186 INFO L290 TraceCheckUtils]: 94: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,186 INFO L290 TraceCheckUtils]: 95: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,187 INFO L290 TraceCheckUtils]: 96: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,187 INFO L290 TraceCheckUtils]: 97: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,187 INFO L290 TraceCheckUtils]: 98: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,188 INFO L290 TraceCheckUtils]: 99: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,188 INFO L290 TraceCheckUtils]: 100: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,188 INFO L290 TraceCheckUtils]: 101: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,189 INFO L290 TraceCheckUtils]: 102: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {57153#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,189 INFO L290 TraceCheckUtils]: 103: Hoare triple {57153#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {57152#false} is VALID [2022-02-21 04:24:36,189 INFO L290 TraceCheckUtils]: 104: Hoare triple {57152#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,189 INFO L290 TraceCheckUtils]: 105: Hoare triple {57152#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,189 INFO L290 TraceCheckUtils]: 106: Hoare triple {57152#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,190 INFO L290 TraceCheckUtils]: 107: Hoare triple {57152#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,190 INFO L290 TraceCheckUtils]: 108: Hoare triple {57152#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,190 INFO L290 TraceCheckUtils]: 109: Hoare triple {57152#false} assume 1 == ~E_1~0;~E_1~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,190 INFO L290 TraceCheckUtils]: 110: Hoare triple {57152#false} assume 1 == ~E_2~0;~E_2~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,190 INFO L290 TraceCheckUtils]: 111: Hoare triple {57152#false} assume !(1 == ~E_3~0); {57152#false} is VALID [2022-02-21 04:24:36,190 INFO L290 TraceCheckUtils]: 112: Hoare triple {57152#false} assume 1 == ~E_4~0;~E_4~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,190 INFO L290 TraceCheckUtils]: 113: Hoare triple {57152#false} assume 1 == ~E_5~0;~E_5~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,190 INFO L290 TraceCheckUtils]: 114: Hoare triple {57152#false} assume 1 == ~E_6~0;~E_6~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,190 INFO L290 TraceCheckUtils]: 115: Hoare triple {57152#false} assume 1 == ~E_7~0;~E_7~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,191 INFO L290 TraceCheckUtils]: 116: Hoare triple {57152#false} assume 1 == ~E_8~0;~E_8~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,191 INFO L290 TraceCheckUtils]: 117: Hoare triple {57152#false} assume 1 == ~E_9~0;~E_9~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,191 INFO L290 TraceCheckUtils]: 118: Hoare triple {57152#false} assume 1 == ~E_10~0;~E_10~0 := 2; {57152#false} is VALID [2022-02-21 04:24:36,191 INFO L290 TraceCheckUtils]: 119: Hoare triple {57152#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {57152#false} is VALID [2022-02-21 04:24:36,191 INFO L290 TraceCheckUtils]: 120: Hoare triple {57152#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {57152#false} is VALID [2022-02-21 04:24:36,191 INFO L290 TraceCheckUtils]: 121: Hoare triple {57152#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {57152#false} is VALID [2022-02-21 04:24:36,191 INFO L290 TraceCheckUtils]: 122: Hoare triple {57152#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {57152#false} is VALID [2022-02-21 04:24:36,191 INFO L290 TraceCheckUtils]: 123: Hoare triple {57152#false} assume !(0 == start_simulation_~tmp~3#1); {57152#false} is VALID [2022-02-21 04:24:36,192 INFO L290 TraceCheckUtils]: 124: Hoare triple {57152#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {57152#false} is VALID [2022-02-21 04:24:36,192 INFO L290 TraceCheckUtils]: 125: Hoare triple {57152#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {57152#false} is VALID [2022-02-21 04:24:36,192 INFO L290 TraceCheckUtils]: 126: Hoare triple {57152#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {57152#false} is VALID [2022-02-21 04:24:36,192 INFO L290 TraceCheckUtils]: 127: Hoare triple {57152#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {57152#false} is VALID [2022-02-21 04:24:36,192 INFO L290 TraceCheckUtils]: 128: Hoare triple {57152#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {57152#false} is VALID [2022-02-21 04:24:36,192 INFO L290 TraceCheckUtils]: 129: Hoare triple {57152#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {57152#false} is VALID [2022-02-21 04:24:36,192 INFO L290 TraceCheckUtils]: 130: Hoare triple {57152#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {57152#false} is VALID [2022-02-21 04:24:36,193 INFO L290 TraceCheckUtils]: 131: Hoare triple {57152#false} assume !(0 != start_simulation_~tmp___0~1#1); {57152#false} is VALID [2022-02-21 04:24:36,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:36,193 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:36,193 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588486116] [2022-02-21 04:24:36,194 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588486116] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:36,194 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:36,194 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:36,194 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1942982885] [2022-02-21 04:24:36,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:36,194 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:36,195 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:36,195 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:36,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:36,196 INFO L87 Difference]: Start difference. First operand 2438 states and 3604 transitions. cyclomatic complexity: 1168 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:38,902 INFO L93 Difference]: Finished difference Result 4592 states and 6785 transitions. [2022-02-21 04:24:38,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:38,902 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,953 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:38,953 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4592 states and 6785 transitions. [2022-02-21 04:24:39,418 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4404 [2022-02-21 04:24:39,856 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4592 states to 4592 states and 6785 transitions. [2022-02-21 04:24:39,857 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4592 [2022-02-21 04:24:39,858 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4592 [2022-02-21 04:24:39,858 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4592 states and 6785 transitions. [2022-02-21 04:24:39,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:39,861 INFO L681 BuchiCegarLoop]: Abstraction has 4592 states and 6785 transitions. [2022-02-21 04:24:39,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4592 states and 6785 transitions. [2022-02-21 04:24:39,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4592 to 4588. [2022-02-21 04:24:39,901 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:39,905 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4592 states and 6785 transitions. Second operand has 4588 states, 4588 states have (on average 1.4779860505666957) internal successors, (6781), 4587 states have internal predecessors, (6781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,908 INFO L74 IsIncluded]: Start isIncluded. First operand 4592 states and 6785 transitions. Second operand has 4588 states, 4588 states have (on average 1.4779860505666957) internal successors, (6781), 4587 states have internal predecessors, (6781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,910 INFO L87 Difference]: Start difference. First operand 4592 states and 6785 transitions. Second operand has 4588 states, 4588 states have (on average 1.4779860505666957) internal successors, (6781), 4587 states have internal predecessors, (6781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:40,347 INFO L93 Difference]: Finished difference Result 4592 states and 6785 transitions. [2022-02-21 04:24:40,347 INFO L276 IsEmpty]: Start isEmpty. Operand 4592 states and 6785 transitions. [2022-02-21 04:24:40,352 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:40,352 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:40,356 INFO L74 IsIncluded]: Start isIncluded. First operand has 4588 states, 4588 states have (on average 1.4779860505666957) internal successors, (6781), 4587 states have internal predecessors, (6781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4592 states and 6785 transitions. [2022-02-21 04:24:40,359 INFO L87 Difference]: Start difference. First operand has 4588 states, 4588 states have (on average 1.4779860505666957) internal successors, (6781), 4587 states have internal predecessors, (6781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4592 states and 6785 transitions. [2022-02-21 04:24:40,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:40,792 INFO L93 Difference]: Finished difference Result 4592 states and 6785 transitions. [2022-02-21 04:24:40,792 INFO L276 IsEmpty]: Start isEmpty. Operand 4592 states and 6785 transitions. [2022-02-21 04:24:40,796 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:40,796 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:40,796 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:40,796 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:40,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4588 states, 4588 states have (on average 1.4779860505666957) internal successors, (6781), 4587 states have internal predecessors, (6781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4588 states to 4588 states and 6781 transitions. [2022-02-21 04:24:41,268 INFO L704 BuchiCegarLoop]: Abstraction has 4588 states and 6781 transitions. [2022-02-21 04:24:41,268 INFO L587 BuchiCegarLoop]: Abstraction has 4588 states and 6781 transitions. [2022-02-21 04:24:41,268 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:24:41,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4588 states and 6781 transitions. [2022-02-21 04:24:41,277 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4404 [2022-02-21 04:24:41,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:41,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:41,278 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:41,278 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:41,279 INFO L791 eck$LassoCheckResult]: Stem: 62747#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 62748#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 63043#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63026#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63027#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 63052#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63053#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62302#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62019#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62020#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62953#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62954#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 62938#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62939#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62975#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 62072#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 62073#L1006 assume !(0 == ~M_E~0); 61923#L1006-2 assume !(0 == ~T1_E~0); 61924#L1011-1 assume !(0 == ~T2_E~0); 62999#L1016-1 assume !(0 == ~T3_E~0); 63014#L1021-1 assume !(0 == ~T4_E~0); 61801#L1026-1 assume !(0 == ~T5_E~0); 61802#L1031-1 assume !(0 == ~T6_E~0); 62693#L1036-1 assume !(0 == ~T7_E~0); 62687#L1041-1 assume !(0 == ~T8_E~0); 62688#L1046-1 assume !(0 == ~T9_E~0); 62103#L1051-1 assume !(0 == ~T10_E~0); 62104#L1056-1 assume !(0 == ~E_1~0); 62827#L1061-1 assume !(0 == ~E_2~0); 62021#L1066-1 assume !(0 == ~E_3~0); 62022#L1071-1 assume !(0 == ~E_4~0); 62804#L1076-1 assume !(0 == ~E_5~0); 61931#L1081-1 assume !(0 == ~E_6~0); 61932#L1086-1 assume !(0 == ~E_7~0); 62278#L1091-1 assume !(0 == ~E_8~0); 62990#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 62991#L1101-1 assume !(0 == ~E_10~0); 62340#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62341#L484 assume !(1 == ~m_pc~0); 61980#L484-2 is_master_triggered_~__retres1~0#1 := 0; 61979#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62605#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 62905#L1245 assume !(0 != activate_threads_~tmp~1#1); 62906#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62679#L503 assume 1 == ~t1_pc~0; 62680#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 62700#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62819#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62457#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 61831#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61832#L522 assume !(1 == ~t2_pc~0); 62642#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 62035#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62036#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62512#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 62955#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63022#L541 assume 1 == ~t3_pc~0; 62592#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 62401#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 62213#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 62214#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 62649#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62650#L560 assume !(1 == ~t4_pc~0); 61914#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 61913#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62549#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61797#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 61798#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62086#L579 assume 1 == ~t5_pc~0; 61748#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 61749#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61857#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 62552#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 63013#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63038#L598 assume 1 == ~t6_pc~0; 62183#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 62184#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 62491#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 62928#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 62728#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62670#L617 assume !(1 == ~t7_pc~0); 62154#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 62153#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62444#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62445#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 62379#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 62380#L636 assume 1 == ~t8_pc~0; 62546#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 62547#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 62342#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 62343#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 62498#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62499#L655 assume !(1 == ~t9_pc~0); 62531#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 62532#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 62133#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 62134#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 62749#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62750#L674 assume 1 == ~t10_pc~0; 61907#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 61908#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63024#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63063#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 62486#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62487#L1119 assume !(1 == ~M_E~0); 62003#L1119-2 assume !(1 == ~T1_E~0); 62004#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61821#L1129-1 assume !(1 == ~T3_E~0); 61822#L1134-1 assume !(1 == ~T4_E~0); 62138#L1139-1 assume !(1 == ~T5_E~0); 62139#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62377#L1149-1 assume !(1 == ~T7_E~0); 61998#L1154-1 assume !(1 == ~T8_E~0); 61999#L1159-1 assume !(1 == ~T9_E~0); 62087#L1164-1 assume !(1 == ~T10_E~0); 63064#L1169-1 assume !(1 == ~E_1~0); 63327#L1174-1 assume !(1 == ~E_2~0); 63186#L1179-1 assume !(1 == ~E_3~0); 63174#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 63172#L1189-1 assume !(1 == ~E_5~0); 63170#L1194-1 assume !(1 == ~E_6~0); 63135#L1199-1 assume !(1 == ~E_7~0); 63131#L1204-1 assume !(1 == ~E_8~0); 63120#L1209-1 assume !(1 == ~E_9~0); 63112#L1214-1 assume !(1 == ~E_10~0); 63104#L1219-1 assume { :end_inline_reset_delta_events } true; 63098#L1520-2 [2022-02-21 04:24:41,279 INFO L793 eck$LassoCheckResult]: Loop: 63098#L1520-2 assume !false; 63093#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63091#L981 assume !false; 63090#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 63081#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 63078#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 63077#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 63075#L836 assume !(0 != eval_~tmp~0#1); 63074#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63073#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63072#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 63071#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 63070#L1011-3 assume !(0 == ~T2_E~0); 62996#L1016-3 assume !(0 == ~T3_E~0); 62896#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62562#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 62563#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 62821#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 62822#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 62885#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 62886#L1051-3 assume !(0 == ~T10_E~0); 62823#L1056-3 assume !(0 == ~E_1~0); 62098#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62099#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62102#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 63003#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 61884#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61885#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 61937#L1091-3 assume !(0 == ~E_8~0); 61938#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 62976#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 62977#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62584#L484-33 assume 1 == ~m_pc~0; 62585#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 62501#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62502#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 61791#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61792#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 62264#L503-33 assume !(1 == ~t1_pc~0); 62265#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 62730#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62653#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62173#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 62174#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64279#L522-33 assume 1 == ~t2_pc~0; 64276#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64274#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64273#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64271#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64269#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64266#L541-33 assume !(1 == ~t3_pc~0); 64263#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 64261#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64259#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64063#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64060#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64058#L560-33 assume 1 == ~t4_pc~0; 64055#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64053#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64051#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64049#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 64046#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64044#L579-33 assume 1 == ~t5_pc~0; 64041#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64039#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64037#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64035#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64032#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64030#L598-33 assume !(1 == ~t6_pc~0); 64027#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 64025#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64023#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64021#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64018#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64016#L617-33 assume 1 == ~t7_pc~0; 64013#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64011#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64009#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64007#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64006#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64005#L636-33 assume !(1 == ~t8_pc~0); 64003#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 64002#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64001#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64000#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63999#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63998#L655-33 assume 1 == ~t9_pc~0; 63996#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63995#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63994#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63993#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 63992#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 63991#L674-33 assume !(1 == ~t10_pc~0); 63989#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 63988#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63987#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 63986#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 63985#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63984#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 63982#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63979#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63068#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 63056#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63975#L1139-3 assume !(1 == ~T5_E~0); 63973#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 63971#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63970#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63967#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 63965#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63963#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 63657#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 63960#L1179-3 assume !(1 == ~E_3~0); 63958#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 63957#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 63954#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 63952#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 63950#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 63948#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 63946#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 63944#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 63762#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 63760#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 63758#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 63269#L1539 assume !(0 == start_simulation_~tmp~3#1); 63266#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 63179#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 63173#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 63171#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 63136#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 63121#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 63113#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 63105#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 63098#L1520-2 [2022-02-21 04:24:41,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:41,280 INFO L85 PathProgramCache]: Analyzing trace with hash 642257269, now seen corresponding path program 1 times [2022-02-21 04:24:41,280 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:41,280 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306698921] [2022-02-21 04:24:41,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:41,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:41,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:41,302 INFO L290 TraceCheckUtils]: 0: Hoare triple {75523#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,302 INFO L290 TraceCheckUtils]: 1: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,303 INFO L290 TraceCheckUtils]: 2: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,303 INFO L290 TraceCheckUtils]: 3: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,303 INFO L290 TraceCheckUtils]: 4: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,304 INFO L290 TraceCheckUtils]: 5: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,304 INFO L290 TraceCheckUtils]: 6: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,304 INFO L290 TraceCheckUtils]: 7: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,304 INFO L290 TraceCheckUtils]: 8: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,305 INFO L290 TraceCheckUtils]: 9: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,305 INFO L290 TraceCheckUtils]: 10: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,305 INFO L290 TraceCheckUtils]: 11: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,306 INFO L290 TraceCheckUtils]: 12: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,306 INFO L290 TraceCheckUtils]: 13: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,306 INFO L290 TraceCheckUtils]: 14: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,306 INFO L290 TraceCheckUtils]: 15: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,307 INFO L290 TraceCheckUtils]: 16: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume !(0 == ~M_E~0); {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,307 INFO L290 TraceCheckUtils]: 17: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume !(0 == ~T1_E~0); {75525#(= ~T2_E~0 ~E_9~0)} is VALID [2022-02-21 04:24:41,307 INFO L290 TraceCheckUtils]: 18: Hoare triple {75525#(= ~T2_E~0 ~E_9~0)} assume !(0 == ~T2_E~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,308 INFO L290 TraceCheckUtils]: 19: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~T3_E~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,308 INFO L290 TraceCheckUtils]: 20: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~T4_E~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,308 INFO L290 TraceCheckUtils]: 21: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~T5_E~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,308 INFO L290 TraceCheckUtils]: 22: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~T6_E~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,309 INFO L290 TraceCheckUtils]: 23: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~T7_E~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,309 INFO L290 TraceCheckUtils]: 24: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~T8_E~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,309 INFO L290 TraceCheckUtils]: 25: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~T9_E~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,309 INFO L290 TraceCheckUtils]: 26: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~T10_E~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,310 INFO L290 TraceCheckUtils]: 27: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~E_1~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,310 INFO L290 TraceCheckUtils]: 28: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~E_2~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,310 INFO L290 TraceCheckUtils]: 29: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~E_3~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,311 INFO L290 TraceCheckUtils]: 30: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~E_4~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,311 INFO L290 TraceCheckUtils]: 31: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~E_5~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,311 INFO L290 TraceCheckUtils]: 32: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~E_6~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,311 INFO L290 TraceCheckUtils]: 33: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~E_7~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,312 INFO L290 TraceCheckUtils]: 34: Hoare triple {75526#(not (= ~E_9~0 0))} assume !(0 == ~E_8~0); {75526#(not (= ~E_9~0 0))} is VALID [2022-02-21 04:24:41,312 INFO L290 TraceCheckUtils]: 35: Hoare triple {75526#(not (= ~E_9~0 0))} assume 0 == ~E_9~0;~E_9~0 := 1; {75524#false} is VALID [2022-02-21 04:24:41,312 INFO L290 TraceCheckUtils]: 36: Hoare triple {75524#false} assume !(0 == ~E_10~0); {75524#false} is VALID [2022-02-21 04:24:41,312 INFO L290 TraceCheckUtils]: 37: Hoare triple {75524#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {75524#false} is VALID [2022-02-21 04:24:41,312 INFO L290 TraceCheckUtils]: 38: Hoare triple {75524#false} assume !(1 == ~m_pc~0); {75524#false} is VALID [2022-02-21 04:24:41,312 INFO L290 TraceCheckUtils]: 39: Hoare triple {75524#false} is_master_triggered_~__retres1~0#1 := 0; {75524#false} is VALID [2022-02-21 04:24:41,313 INFO L290 TraceCheckUtils]: 40: Hoare triple {75524#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {75524#false} is VALID [2022-02-21 04:24:41,313 INFO L290 TraceCheckUtils]: 41: Hoare triple {75524#false} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {75524#false} is VALID [2022-02-21 04:24:41,313 INFO L290 TraceCheckUtils]: 42: Hoare triple {75524#false} assume !(0 != activate_threads_~tmp~1#1); {75524#false} is VALID [2022-02-21 04:24:41,313 INFO L290 TraceCheckUtils]: 43: Hoare triple {75524#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {75524#false} is VALID [2022-02-21 04:24:41,313 INFO L290 TraceCheckUtils]: 44: Hoare triple {75524#false} assume 1 == ~t1_pc~0; {75524#false} is VALID [2022-02-21 04:24:41,313 INFO L290 TraceCheckUtils]: 45: Hoare triple {75524#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {75524#false} is VALID [2022-02-21 04:24:41,313 INFO L290 TraceCheckUtils]: 46: Hoare triple {75524#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {75524#false} is VALID [2022-02-21 04:24:41,313 INFO L290 TraceCheckUtils]: 47: Hoare triple {75524#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {75524#false} is VALID [2022-02-21 04:24:41,313 INFO L290 TraceCheckUtils]: 48: Hoare triple {75524#false} assume !(0 != activate_threads_~tmp___0~0#1); {75524#false} is VALID [2022-02-21 04:24:41,314 INFO L290 TraceCheckUtils]: 49: Hoare triple {75524#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {75524#false} is VALID [2022-02-21 04:24:41,314 INFO L290 TraceCheckUtils]: 50: Hoare triple {75524#false} assume !(1 == ~t2_pc~0); {75524#false} is VALID [2022-02-21 04:24:41,314 INFO L290 TraceCheckUtils]: 51: Hoare triple {75524#false} is_transmit2_triggered_~__retres1~2#1 := 0; {75524#false} is VALID [2022-02-21 04:24:41,314 INFO L290 TraceCheckUtils]: 52: Hoare triple {75524#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {75524#false} is VALID [2022-02-21 04:24:41,314 INFO L290 TraceCheckUtils]: 53: Hoare triple {75524#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {75524#false} is VALID [2022-02-21 04:24:41,314 INFO L290 TraceCheckUtils]: 54: Hoare triple {75524#false} assume !(0 != activate_threads_~tmp___1~0#1); {75524#false} is VALID [2022-02-21 04:24:41,314 INFO L290 TraceCheckUtils]: 55: Hoare triple {75524#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {75524#false} is VALID [2022-02-21 04:24:41,314 INFO L290 TraceCheckUtils]: 56: Hoare triple {75524#false} assume 1 == ~t3_pc~0; {75524#false} is VALID [2022-02-21 04:24:41,314 INFO L290 TraceCheckUtils]: 57: Hoare triple {75524#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {75524#false} is VALID [2022-02-21 04:24:41,315 INFO L290 TraceCheckUtils]: 58: Hoare triple {75524#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {75524#false} is VALID [2022-02-21 04:24:41,315 INFO L290 TraceCheckUtils]: 59: Hoare triple {75524#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {75524#false} is VALID [2022-02-21 04:24:41,315 INFO L290 TraceCheckUtils]: 60: Hoare triple {75524#false} assume !(0 != activate_threads_~tmp___2~0#1); {75524#false} is VALID [2022-02-21 04:24:41,315 INFO L290 TraceCheckUtils]: 61: Hoare triple {75524#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {75524#false} is VALID [2022-02-21 04:24:41,315 INFO L290 TraceCheckUtils]: 62: Hoare triple {75524#false} assume !(1 == ~t4_pc~0); {75524#false} is VALID [2022-02-21 04:24:41,315 INFO L290 TraceCheckUtils]: 63: Hoare triple {75524#false} is_transmit4_triggered_~__retres1~4#1 := 0; {75524#false} is VALID [2022-02-21 04:24:41,315 INFO L290 TraceCheckUtils]: 64: Hoare triple {75524#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {75524#false} is VALID [2022-02-21 04:24:41,315 INFO L290 TraceCheckUtils]: 65: Hoare triple {75524#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {75524#false} is VALID [2022-02-21 04:24:41,315 INFO L290 TraceCheckUtils]: 66: Hoare triple {75524#false} assume !(0 != activate_threads_~tmp___3~0#1); {75524#false} is VALID [2022-02-21 04:24:41,316 INFO L290 TraceCheckUtils]: 67: Hoare triple {75524#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {75524#false} is VALID [2022-02-21 04:24:41,316 INFO L290 TraceCheckUtils]: 68: Hoare triple {75524#false} assume 1 == ~t5_pc~0; {75524#false} is VALID [2022-02-21 04:24:41,316 INFO L290 TraceCheckUtils]: 69: Hoare triple {75524#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {75524#false} is VALID [2022-02-21 04:24:41,316 INFO L290 TraceCheckUtils]: 70: Hoare triple {75524#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {75524#false} is VALID [2022-02-21 04:24:41,316 INFO L290 TraceCheckUtils]: 71: Hoare triple {75524#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {75524#false} is VALID [2022-02-21 04:24:41,316 INFO L290 TraceCheckUtils]: 72: Hoare triple {75524#false} assume !(0 != activate_threads_~tmp___4~0#1); {75524#false} is VALID [2022-02-21 04:24:41,316 INFO L290 TraceCheckUtils]: 73: Hoare triple {75524#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {75524#false} is VALID [2022-02-21 04:24:41,316 INFO L290 TraceCheckUtils]: 74: Hoare triple {75524#false} assume 1 == ~t6_pc~0; {75524#false} is VALID [2022-02-21 04:24:41,316 INFO L290 TraceCheckUtils]: 75: Hoare triple {75524#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {75524#false} is VALID [2022-02-21 04:24:41,317 INFO L290 TraceCheckUtils]: 76: Hoare triple {75524#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {75524#false} is VALID [2022-02-21 04:24:41,317 INFO L290 TraceCheckUtils]: 77: Hoare triple {75524#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {75524#false} is VALID [2022-02-21 04:24:41,317 INFO L290 TraceCheckUtils]: 78: Hoare triple {75524#false} assume !(0 != activate_threads_~tmp___5~0#1); {75524#false} is VALID [2022-02-21 04:24:41,317 INFO L290 TraceCheckUtils]: 79: Hoare triple {75524#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {75524#false} is VALID [2022-02-21 04:24:41,317 INFO L290 TraceCheckUtils]: 80: Hoare triple {75524#false} assume !(1 == ~t7_pc~0); {75524#false} is VALID [2022-02-21 04:24:41,317 INFO L290 TraceCheckUtils]: 81: Hoare triple {75524#false} is_transmit7_triggered_~__retres1~7#1 := 0; {75524#false} is VALID [2022-02-21 04:24:41,317 INFO L290 TraceCheckUtils]: 82: Hoare triple {75524#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {75524#false} is VALID [2022-02-21 04:24:41,317 INFO L290 TraceCheckUtils]: 83: Hoare triple {75524#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {75524#false} is VALID [2022-02-21 04:24:41,317 INFO L290 TraceCheckUtils]: 84: Hoare triple {75524#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {75524#false} is VALID [2022-02-21 04:24:41,318 INFO L290 TraceCheckUtils]: 85: Hoare triple {75524#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {75524#false} is VALID [2022-02-21 04:24:41,318 INFO L290 TraceCheckUtils]: 86: Hoare triple {75524#false} assume 1 == ~t8_pc~0; {75524#false} is VALID [2022-02-21 04:24:41,318 INFO L290 TraceCheckUtils]: 87: Hoare triple {75524#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {75524#false} is VALID [2022-02-21 04:24:41,318 INFO L290 TraceCheckUtils]: 88: Hoare triple {75524#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {75524#false} is VALID [2022-02-21 04:24:41,318 INFO L290 TraceCheckUtils]: 89: Hoare triple {75524#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {75524#false} is VALID [2022-02-21 04:24:41,318 INFO L290 TraceCheckUtils]: 90: Hoare triple {75524#false} assume !(0 != activate_threads_~tmp___7~0#1); {75524#false} is VALID [2022-02-21 04:24:41,318 INFO L290 TraceCheckUtils]: 91: Hoare triple {75524#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {75524#false} is VALID [2022-02-21 04:24:41,318 INFO L290 TraceCheckUtils]: 92: Hoare triple {75524#false} assume !(1 == ~t9_pc~0); {75524#false} is VALID [2022-02-21 04:24:41,318 INFO L290 TraceCheckUtils]: 93: Hoare triple {75524#false} is_transmit9_triggered_~__retres1~9#1 := 0; {75524#false} is VALID [2022-02-21 04:24:41,319 INFO L290 TraceCheckUtils]: 94: Hoare triple {75524#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {75524#false} is VALID [2022-02-21 04:24:41,319 INFO L290 TraceCheckUtils]: 95: Hoare triple {75524#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {75524#false} is VALID [2022-02-21 04:24:41,319 INFO L290 TraceCheckUtils]: 96: Hoare triple {75524#false} assume !(0 != activate_threads_~tmp___8~0#1); {75524#false} is VALID [2022-02-21 04:24:41,319 INFO L290 TraceCheckUtils]: 97: Hoare triple {75524#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {75524#false} is VALID [2022-02-21 04:24:41,319 INFO L290 TraceCheckUtils]: 98: Hoare triple {75524#false} assume 1 == ~t10_pc~0; {75524#false} is VALID [2022-02-21 04:24:41,319 INFO L290 TraceCheckUtils]: 99: Hoare triple {75524#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {75524#false} is VALID [2022-02-21 04:24:41,319 INFO L290 TraceCheckUtils]: 100: Hoare triple {75524#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {75524#false} is VALID [2022-02-21 04:24:41,319 INFO L290 TraceCheckUtils]: 101: Hoare triple {75524#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {75524#false} is VALID [2022-02-21 04:24:41,319 INFO L290 TraceCheckUtils]: 102: Hoare triple {75524#false} assume !(0 != activate_threads_~tmp___9~0#1); {75524#false} is VALID [2022-02-21 04:24:41,320 INFO L290 TraceCheckUtils]: 103: Hoare triple {75524#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {75524#false} is VALID [2022-02-21 04:24:41,320 INFO L290 TraceCheckUtils]: 104: Hoare triple {75524#false} assume !(1 == ~M_E~0); {75524#false} is VALID [2022-02-21 04:24:41,320 INFO L290 TraceCheckUtils]: 105: Hoare triple {75524#false} assume !(1 == ~T1_E~0); {75524#false} is VALID [2022-02-21 04:24:41,320 INFO L290 TraceCheckUtils]: 106: Hoare triple {75524#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {75524#false} is VALID [2022-02-21 04:24:41,320 INFO L290 TraceCheckUtils]: 107: Hoare triple {75524#false} assume !(1 == ~T3_E~0); {75524#false} is VALID [2022-02-21 04:24:41,320 INFO L290 TraceCheckUtils]: 108: Hoare triple {75524#false} assume !(1 == ~T4_E~0); {75524#false} is VALID [2022-02-21 04:24:41,320 INFO L290 TraceCheckUtils]: 109: Hoare triple {75524#false} assume !(1 == ~T5_E~0); {75524#false} is VALID [2022-02-21 04:24:41,320 INFO L290 TraceCheckUtils]: 110: Hoare triple {75524#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {75524#false} is VALID [2022-02-21 04:24:41,320 INFO L290 TraceCheckUtils]: 111: Hoare triple {75524#false} assume !(1 == ~T7_E~0); {75524#false} is VALID [2022-02-21 04:24:41,321 INFO L290 TraceCheckUtils]: 112: Hoare triple {75524#false} assume !(1 == ~T8_E~0); {75524#false} is VALID [2022-02-21 04:24:41,321 INFO L290 TraceCheckUtils]: 113: Hoare triple {75524#false} assume !(1 == ~T9_E~0); {75524#false} is VALID [2022-02-21 04:24:41,321 INFO L290 TraceCheckUtils]: 114: Hoare triple {75524#false} assume !(1 == ~T10_E~0); {75524#false} is VALID [2022-02-21 04:24:41,321 INFO L290 TraceCheckUtils]: 115: Hoare triple {75524#false} assume !(1 == ~E_1~0); {75524#false} is VALID [2022-02-21 04:24:41,321 INFO L290 TraceCheckUtils]: 116: Hoare triple {75524#false} assume !(1 == ~E_2~0); {75524#false} is VALID [2022-02-21 04:24:41,321 INFO L290 TraceCheckUtils]: 117: Hoare triple {75524#false} assume !(1 == ~E_3~0); {75524#false} is VALID [2022-02-21 04:24:41,321 INFO L290 TraceCheckUtils]: 118: Hoare triple {75524#false} assume 1 == ~E_4~0;~E_4~0 := 2; {75524#false} is VALID [2022-02-21 04:24:41,321 INFO L290 TraceCheckUtils]: 119: Hoare triple {75524#false} assume !(1 == ~E_5~0); {75524#false} is VALID [2022-02-21 04:24:41,321 INFO L290 TraceCheckUtils]: 120: Hoare triple {75524#false} assume !(1 == ~E_6~0); {75524#false} is VALID [2022-02-21 04:24:41,322 INFO L290 TraceCheckUtils]: 121: Hoare triple {75524#false} assume !(1 == ~E_7~0); {75524#false} is VALID [2022-02-21 04:24:41,322 INFO L290 TraceCheckUtils]: 122: Hoare triple {75524#false} assume !(1 == ~E_8~0); {75524#false} is VALID [2022-02-21 04:24:41,322 INFO L290 TraceCheckUtils]: 123: Hoare triple {75524#false} assume !(1 == ~E_9~0); {75524#false} is VALID [2022-02-21 04:24:41,322 INFO L290 TraceCheckUtils]: 124: Hoare triple {75524#false} assume !(1 == ~E_10~0); {75524#false} is VALID [2022-02-21 04:24:41,322 INFO L290 TraceCheckUtils]: 125: Hoare triple {75524#false} assume { :end_inline_reset_delta_events } true; {75524#false} is VALID [2022-02-21 04:24:41,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:41,322 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:41,323 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [306698921] [2022-02-21 04:24:41,323 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [306698921] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:41,323 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:41,323 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:41,323 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141548759] [2022-02-21 04:24:41,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:41,324 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:41,324 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:41,324 INFO L85 PathProgramCache]: Analyzing trace with hash -1630345236, now seen corresponding path program 1 times [2022-02-21 04:24:41,324 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:41,324 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033849717] [2022-02-21 04:24:41,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:41,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:41,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:41,345 INFO L290 TraceCheckUtils]: 0: Hoare triple {75527#true} assume !false; {75527#true} is VALID [2022-02-21 04:24:41,345 INFO L290 TraceCheckUtils]: 1: Hoare triple {75527#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {75527#true} is VALID [2022-02-21 04:24:41,345 INFO L290 TraceCheckUtils]: 2: Hoare triple {75527#true} assume !false; {75527#true} is VALID [2022-02-21 04:24:41,345 INFO L290 TraceCheckUtils]: 3: Hoare triple {75527#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {75527#true} is VALID [2022-02-21 04:24:41,345 INFO L290 TraceCheckUtils]: 4: Hoare triple {75527#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {75527#true} is VALID [2022-02-21 04:24:41,346 INFO L290 TraceCheckUtils]: 5: Hoare triple {75527#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {75527#true} is VALID [2022-02-21 04:24:41,346 INFO L290 TraceCheckUtils]: 6: Hoare triple {75527#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {75527#true} is VALID [2022-02-21 04:24:41,346 INFO L290 TraceCheckUtils]: 7: Hoare triple {75527#true} assume !(0 != eval_~tmp~0#1); {75527#true} is VALID [2022-02-21 04:24:41,346 INFO L290 TraceCheckUtils]: 8: Hoare triple {75527#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {75527#true} is VALID [2022-02-21 04:24:41,346 INFO L290 TraceCheckUtils]: 9: Hoare triple {75527#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {75527#true} is VALID [2022-02-21 04:24:41,346 INFO L290 TraceCheckUtils]: 10: Hoare triple {75527#true} assume 0 == ~M_E~0;~M_E~0 := 1; {75527#true} is VALID [2022-02-21 04:24:41,346 INFO L290 TraceCheckUtils]: 11: Hoare triple {75527#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {75527#true} is VALID [2022-02-21 04:24:41,346 INFO L290 TraceCheckUtils]: 12: Hoare triple {75527#true} assume !(0 == ~T2_E~0); {75527#true} is VALID [2022-02-21 04:24:41,346 INFO L290 TraceCheckUtils]: 13: Hoare triple {75527#true} assume !(0 == ~T3_E~0); {75527#true} is VALID [2022-02-21 04:24:41,347 INFO L290 TraceCheckUtils]: 14: Hoare triple {75527#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {75527#true} is VALID [2022-02-21 04:24:41,347 INFO L290 TraceCheckUtils]: 15: Hoare triple {75527#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,347 INFO L290 TraceCheckUtils]: 16: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,348 INFO L290 TraceCheckUtils]: 17: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,348 INFO L290 TraceCheckUtils]: 18: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,348 INFO L290 TraceCheckUtils]: 19: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,348 INFO L290 TraceCheckUtils]: 20: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,349 INFO L290 TraceCheckUtils]: 21: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_1~0); {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,349 INFO L290 TraceCheckUtils]: 22: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,349 INFO L290 TraceCheckUtils]: 23: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,350 INFO L290 TraceCheckUtils]: 24: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,350 INFO L290 TraceCheckUtils]: 25: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,350 INFO L290 TraceCheckUtils]: 26: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,351 INFO L290 TraceCheckUtils]: 27: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,351 INFO L290 TraceCheckUtils]: 28: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,351 INFO L290 TraceCheckUtils]: 29: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,352 INFO L290 TraceCheckUtils]: 30: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,352 INFO L290 TraceCheckUtils]: 31: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,352 INFO L290 TraceCheckUtils]: 32: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,353 INFO L290 TraceCheckUtils]: 33: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,353 INFO L290 TraceCheckUtils]: 34: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,353 INFO L290 TraceCheckUtils]: 35: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,353 INFO L290 TraceCheckUtils]: 36: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,354 INFO L290 TraceCheckUtils]: 37: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,354 INFO L290 TraceCheckUtils]: 38: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,354 INFO L290 TraceCheckUtils]: 39: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,355 INFO L290 TraceCheckUtils]: 40: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,355 INFO L290 TraceCheckUtils]: 41: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,355 INFO L290 TraceCheckUtils]: 42: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,356 INFO L290 TraceCheckUtils]: 43: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,356 INFO L290 TraceCheckUtils]: 44: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,356 INFO L290 TraceCheckUtils]: 45: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,357 INFO L290 TraceCheckUtils]: 46: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,357 INFO L290 TraceCheckUtils]: 47: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,357 INFO L290 TraceCheckUtils]: 48: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,357 INFO L290 TraceCheckUtils]: 49: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,358 INFO L290 TraceCheckUtils]: 50: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,358 INFO L290 TraceCheckUtils]: 51: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,358 INFO L290 TraceCheckUtils]: 52: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,359 INFO L290 TraceCheckUtils]: 53: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,359 INFO L290 TraceCheckUtils]: 54: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,359 INFO L290 TraceCheckUtils]: 55: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,360 INFO L290 TraceCheckUtils]: 56: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,360 INFO L290 TraceCheckUtils]: 57: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,360 INFO L290 TraceCheckUtils]: 58: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,361 INFO L290 TraceCheckUtils]: 59: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,361 INFO L290 TraceCheckUtils]: 60: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,361 INFO L290 TraceCheckUtils]: 61: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,361 INFO L290 TraceCheckUtils]: 62: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,362 INFO L290 TraceCheckUtils]: 63: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,362 INFO L290 TraceCheckUtils]: 64: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,362 INFO L290 TraceCheckUtils]: 65: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,363 INFO L290 TraceCheckUtils]: 66: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,363 INFO L290 TraceCheckUtils]: 67: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,363 INFO L290 TraceCheckUtils]: 68: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,364 INFO L290 TraceCheckUtils]: 69: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,364 INFO L290 TraceCheckUtils]: 70: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,364 INFO L290 TraceCheckUtils]: 71: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,365 INFO L290 TraceCheckUtils]: 72: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,365 INFO L290 TraceCheckUtils]: 73: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,365 INFO L290 TraceCheckUtils]: 74: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,365 INFO L290 TraceCheckUtils]: 75: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,366 INFO L290 TraceCheckUtils]: 76: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,366 INFO L290 TraceCheckUtils]: 77: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,366 INFO L290 TraceCheckUtils]: 78: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,367 INFO L290 TraceCheckUtils]: 79: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,367 INFO L290 TraceCheckUtils]: 80: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,367 INFO L290 TraceCheckUtils]: 81: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,368 INFO L290 TraceCheckUtils]: 82: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,368 INFO L290 TraceCheckUtils]: 83: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,368 INFO L290 TraceCheckUtils]: 84: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,369 INFO L290 TraceCheckUtils]: 85: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,369 INFO L290 TraceCheckUtils]: 86: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,369 INFO L290 TraceCheckUtils]: 87: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,369 INFO L290 TraceCheckUtils]: 88: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,370 INFO L290 TraceCheckUtils]: 89: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,370 INFO L290 TraceCheckUtils]: 90: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,370 INFO L290 TraceCheckUtils]: 91: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,371 INFO L290 TraceCheckUtils]: 92: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,371 INFO L290 TraceCheckUtils]: 93: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,371 INFO L290 TraceCheckUtils]: 94: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,372 INFO L290 TraceCheckUtils]: 95: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,372 INFO L290 TraceCheckUtils]: 96: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,372 INFO L290 TraceCheckUtils]: 97: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,373 INFO L290 TraceCheckUtils]: 98: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,373 INFO L290 TraceCheckUtils]: 99: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,373 INFO L290 TraceCheckUtils]: 100: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,373 INFO L290 TraceCheckUtils]: 101: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,374 INFO L290 TraceCheckUtils]: 102: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {75529#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,374 INFO L290 TraceCheckUtils]: 103: Hoare triple {75529#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {75528#false} is VALID [2022-02-21 04:24:41,374 INFO L290 TraceCheckUtils]: 104: Hoare triple {75528#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,374 INFO L290 TraceCheckUtils]: 105: Hoare triple {75528#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,374 INFO L290 TraceCheckUtils]: 106: Hoare triple {75528#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,374 INFO L290 TraceCheckUtils]: 107: Hoare triple {75528#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,375 INFO L290 TraceCheckUtils]: 108: Hoare triple {75528#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,375 INFO L290 TraceCheckUtils]: 109: Hoare triple {75528#false} assume 1 == ~E_1~0;~E_1~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,375 INFO L290 TraceCheckUtils]: 110: Hoare triple {75528#false} assume 1 == ~E_2~0;~E_2~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,375 INFO L290 TraceCheckUtils]: 111: Hoare triple {75528#false} assume !(1 == ~E_3~0); {75528#false} is VALID [2022-02-21 04:24:41,375 INFO L290 TraceCheckUtils]: 112: Hoare triple {75528#false} assume 1 == ~E_4~0;~E_4~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,375 INFO L290 TraceCheckUtils]: 113: Hoare triple {75528#false} assume 1 == ~E_5~0;~E_5~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,375 INFO L290 TraceCheckUtils]: 114: Hoare triple {75528#false} assume 1 == ~E_6~0;~E_6~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,375 INFO L290 TraceCheckUtils]: 115: Hoare triple {75528#false} assume 1 == ~E_7~0;~E_7~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,375 INFO L290 TraceCheckUtils]: 116: Hoare triple {75528#false} assume 1 == ~E_8~0;~E_8~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,376 INFO L290 TraceCheckUtils]: 117: Hoare triple {75528#false} assume 1 == ~E_9~0;~E_9~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,376 INFO L290 TraceCheckUtils]: 118: Hoare triple {75528#false} assume 1 == ~E_10~0;~E_10~0 := 2; {75528#false} is VALID [2022-02-21 04:24:41,376 INFO L290 TraceCheckUtils]: 119: Hoare triple {75528#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {75528#false} is VALID [2022-02-21 04:24:41,376 INFO L290 TraceCheckUtils]: 120: Hoare triple {75528#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {75528#false} is VALID [2022-02-21 04:24:41,376 INFO L290 TraceCheckUtils]: 121: Hoare triple {75528#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {75528#false} is VALID [2022-02-21 04:24:41,376 INFO L290 TraceCheckUtils]: 122: Hoare triple {75528#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {75528#false} is VALID [2022-02-21 04:24:41,376 INFO L290 TraceCheckUtils]: 123: Hoare triple {75528#false} assume !(0 == start_simulation_~tmp~3#1); {75528#false} is VALID [2022-02-21 04:24:41,376 INFO L290 TraceCheckUtils]: 124: Hoare triple {75528#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {75528#false} is VALID [2022-02-21 04:24:41,376 INFO L290 TraceCheckUtils]: 125: Hoare triple {75528#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {75528#false} is VALID [2022-02-21 04:24:41,377 INFO L290 TraceCheckUtils]: 126: Hoare triple {75528#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {75528#false} is VALID [2022-02-21 04:24:41,377 INFO L290 TraceCheckUtils]: 127: Hoare triple {75528#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {75528#false} is VALID [2022-02-21 04:24:41,377 INFO L290 TraceCheckUtils]: 128: Hoare triple {75528#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {75528#false} is VALID [2022-02-21 04:24:41,377 INFO L290 TraceCheckUtils]: 129: Hoare triple {75528#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {75528#false} is VALID [2022-02-21 04:24:41,377 INFO L290 TraceCheckUtils]: 130: Hoare triple {75528#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {75528#false} is VALID [2022-02-21 04:24:41,377 INFO L290 TraceCheckUtils]: 131: Hoare triple {75528#false} assume !(0 != start_simulation_~tmp___0~1#1); {75528#false} is VALID [2022-02-21 04:24:41,378 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:41,378 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:41,378 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1033849717] [2022-02-21 04:24:41,378 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1033849717] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:41,378 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:41,378 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:41,378 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214362172] [2022-02-21 04:24:41,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:41,379 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:41,379 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:41,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:41,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:41,379 INFO L87 Difference]: Start difference. First operand 4588 states and 6781 transitions. cyclomatic complexity: 2197 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:45,265 INFO L93 Difference]: Finished difference Result 8696 states and 12834 transitions. [2022-02-21 04:24:45,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:45,266 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,341 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:45,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8696 states and 12834 transitions. [2022-02-21 04:24:47,123 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8492 [2022-02-21 04:24:48,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8696 states to 8696 states and 12834 transitions. [2022-02-21 04:24:48,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8696 [2022-02-21 04:24:48,697 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8696 [2022-02-21 04:24:48,697 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8696 states and 12834 transitions. [2022-02-21 04:24:48,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:48,702 INFO L681 BuchiCegarLoop]: Abstraction has 8696 states and 12834 transitions. [2022-02-21 04:24:48,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8696 states and 12834 transitions. [2022-02-21 04:24:48,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8696 to 8692. [2022-02-21 04:24:48,771 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:48,779 INFO L82 GeneralOperation]: Start isEquivalent. First operand 8696 states and 12834 transitions. Second operand has 8692 states, 8692 states have (on average 1.476069949378739) internal successors, (12830), 8691 states have internal predecessors, (12830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:48,786 INFO L74 IsIncluded]: Start isIncluded. First operand 8696 states and 12834 transitions. Second operand has 8692 states, 8692 states have (on average 1.476069949378739) internal successors, (12830), 8691 states have internal predecessors, (12830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:48,794 INFO L87 Difference]: Start difference. First operand 8696 states and 12834 transitions. Second operand has 8692 states, 8692 states have (on average 1.476069949378739) internal successors, (12830), 8691 states have internal predecessors, (12830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:50,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:50,368 INFO L93 Difference]: Finished difference Result 8696 states and 12834 transitions. [2022-02-21 04:24:50,368 INFO L276 IsEmpty]: Start isEmpty. Operand 8696 states and 12834 transitions. [2022-02-21 04:24:50,377 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:50,378 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:50,386 INFO L74 IsIncluded]: Start isIncluded. First operand has 8692 states, 8692 states have (on average 1.476069949378739) internal successors, (12830), 8691 states have internal predecessors, (12830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8696 states and 12834 transitions. [2022-02-21 04:24:50,392 INFO L87 Difference]: Start difference. First operand has 8692 states, 8692 states have (on average 1.476069949378739) internal successors, (12830), 8691 states have internal predecessors, (12830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8696 states and 12834 transitions. [2022-02-21 04:24:52,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:52,008 INFO L93 Difference]: Finished difference Result 8696 states and 12834 transitions. [2022-02-21 04:24:52,008 INFO L276 IsEmpty]: Start isEmpty. Operand 8696 states and 12834 transitions. [2022-02-21 04:24:52,016 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:52,016 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:52,016 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:52,016 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:52,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8692 states, 8692 states have (on average 1.476069949378739) internal successors, (12830), 8691 states have internal predecessors, (12830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:53,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8692 states to 8692 states and 12830 transitions. [2022-02-21 04:24:53,782 INFO L704 BuchiCegarLoop]: Abstraction has 8692 states and 12830 transitions. [2022-02-21 04:24:53,782 INFO L587 BuchiCegarLoop]: Abstraction has 8692 states and 12830 transitions. [2022-02-21 04:24:53,782 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:24:53,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8692 states and 12830 transitions. [2022-02-21 04:24:53,797 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8492 [2022-02-21 04:24:53,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:53,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:53,799 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:53,799 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:53,799 INFO L791 eck$LassoCheckResult]: Stem: 85223#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 85224#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 85512#L1483 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85500#L694 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 85501#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 85524#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85525#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84783#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84498#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84499#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 85425#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 85426#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85409#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85410#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 85447#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 84554#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84555#L1006 assume !(0 == ~M_E~0); 84401#L1006-2 assume !(0 == ~T1_E~0); 84402#L1011-1 assume !(0 == ~T2_E~0); 85472#L1016-1 assume !(0 == ~T3_E~0); 85488#L1021-1 assume !(0 == ~T4_E~0); 84281#L1026-1 assume !(0 == ~T5_E~0); 84282#L1031-1 assume !(0 == ~T6_E~0); 85167#L1036-1 assume !(0 == ~T7_E~0); 85163#L1041-1 assume !(0 == ~T8_E~0); 85164#L1046-1 assume !(0 == ~T9_E~0); 84585#L1051-1 assume !(0 == ~T10_E~0); 84586#L1056-1 assume !(0 == ~E_1~0); 85299#L1061-1 assume !(0 == ~E_2~0); 84502#L1066-1 assume !(0 == ~E_3~0); 84503#L1071-1 assume !(0 == ~E_4~0); 85278#L1076-1 assume !(0 == ~E_5~0); 84412#L1081-1 assume !(0 == ~E_6~0); 84413#L1086-1 assume !(0 == ~E_7~0); 84758#L1091-1 assume !(0 == ~E_8~0); 85463#L1096-1 assume !(0 == ~E_9~0); 85464#L1101-1 assume !(0 == ~E_10~0); 84820#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84821#L484 assume !(1 == ~m_pc~0); 84461#L484-2 is_master_triggered_~__retres1~0#1 := 0; 84460#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85084#L496 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 85376#L1245 assume !(0 != activate_threads_~tmp~1#1); 85377#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85155#L503 assume 1 == ~t1_pc~0; 85156#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85172#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85291#L515 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 84934#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 84310#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84311#L522 assume !(1 == ~t2_pc~0); 85121#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 84515#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84516#L534 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 84991#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 85427#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85496#L541 assume 1 == ~t3_pc~0; 85069#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 84880#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84695#L553 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 84696#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 85124#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85125#L560 assume !(1 == ~t4_pc~0); 84395#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 84394#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85027#L572 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 84277#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 84278#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84568#L579 assume 1 == ~t5_pc~0; 84228#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 84229#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84338#L591 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85030#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 85486#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85509#L598 assume 1 == ~t6_pc~0; 84663#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 84664#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84968#L610 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85400#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 85205#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85146#L617 assume !(1 == ~t7_pc~0); 84636#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 84635#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84923#L629 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84924#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 84857#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84858#L636 assume 1 == ~t8_pc~0; 85024#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85025#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84822#L648 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 84823#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 84975#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84976#L655 assume !(1 == ~t9_pc~0); 85007#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 85008#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84615#L667 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84616#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 85225#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85226#L674 assume 1 == ~t10_pc~0; 84388#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 84389#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85499#L686 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85534#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 84965#L1325-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84966#L1119 assume !(1 == ~M_E~0); 84484#L1119-2 assume !(1 == ~T1_E~0); 84485#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84898#L1129-1 assume !(1 == ~T3_E~0); 85848#L1134-1 assume !(1 == ~T4_E~0); 85846#L1139-1 assume !(1 == ~T5_E~0); 85843#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 85841#L1149-1 assume !(1 == ~T7_E~0); 85675#L1154-1 assume !(1 == ~T8_E~0); 85673#L1159-1 assume !(1 == ~T9_E~0); 85672#L1164-1 assume !(1 == ~T10_E~0); 85671#L1169-1 assume !(1 == ~E_1~0); 85670#L1174-1 assume !(1 == ~E_2~0); 85669#L1179-1 assume !(1 == ~E_3~0); 85665#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 85663#L1189-1 assume !(1 == ~E_5~0); 85662#L1194-1 assume !(1 == ~E_6~0); 85661#L1199-1 assume !(1 == ~E_7~0); 85610#L1204-1 assume !(1 == ~E_8~0); 85594#L1209-1 assume !(1 == ~E_9~0); 85584#L1214-1 assume !(1 == ~E_10~0); 85576#L1219-1 assume { :end_inline_reset_delta_events } true; 85570#L1520-2 [2022-02-21 04:24:53,800 INFO L793 eck$LassoCheckResult]: Loop: 85570#L1520-2 assume !false; 85565#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85563#L981 assume !false; 85562#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 85553#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 85550#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 85549#L822 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 85547#L836 assume !(0 != eval_~tmp~0#1); 85546#L996 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85545#L694-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85544#L1006-3 assume 0 == ~M_E~0;~M_E~0 := 1; 85543#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 85542#L1011-3 assume !(0 == ~T2_E~0); 85470#L1016-3 assume !(0 == ~T3_E~0); 85368#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85040#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 85041#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85293#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85294#L1041-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 85357#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 85358#L1051-3 assume !(0 == ~T10_E~0); 85295#L1056-3 assume !(0 == ~E_1~0); 84582#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 84583#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 84584#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 85476#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 84365#L1081-3 assume 0 == ~E_6~0;~E_6~0 := 1; 84366#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 84420#L1091-3 assume !(0 == ~E_8~0); 84421#L1096-3 assume !(0 == ~E_9~0); 85448#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 85449#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85063#L484-33 assume !(1 == ~m_pc~0); 85065#L484-35 is_master_triggered_~__retres1~0#1 := 0; 84980#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84981#L496-11 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 84271#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 84272#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84748#L503-33 assume !(1 == ~t1_pc~0); 84749#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 85207#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85134#L515-11 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 84655#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 84656#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85101#L522-33 assume !(1 == ~t2_pc~0); 85103#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 84406#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84407#L534-11 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 85213#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 85119#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85120#L541-33 assume !(1 == ~t3_pc~0); 84433#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 84269#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84270#L553-11 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 85091#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85092#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85290#L560-33 assume 1 == ~t4_pc~0; 84987#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 84342#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84343#L572-11 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 84604#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 85272#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84260#L579-33 assume 1 == ~t5_pc~0; 84261#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 84509#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85492#L591-11 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85147#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 85148#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85176#L598-33 assume !(1 == ~t6_pc~0); 84946#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 84769#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84770#L610-11 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84609#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 84610#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85437#L617-33 assume 1 == ~t7_pc~0; 85443#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84397#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85367#L629-11 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 85481#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 85477#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84327#L636-33 assume 1 == ~t8_pc~0; 84329#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85263#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85264#L648-11 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85502#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85252#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85253#L655-33 assume !(1 == ~t9_pc~0); 85531#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 84710#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84711#L667-11 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85074#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 85343#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 84889#L674-33 assume 1 == ~t10_pc~0; 84762#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 84763#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 84626#L686-11 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84627#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85110#L1325-35 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85503#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 85510#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85513#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 85539#L1129-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86650#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86648#L1139-3 assume !(1 == ~T5_E~0); 86646#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 86644#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86642#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86640#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86639#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86142#L1169-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86139#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86137#L1179-3 assume !(1 == ~E_3~0); 86135#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86133#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86131#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86129#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86127#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 86125#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 86121#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 86120#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 85826#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 85824#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 85822#L822-1 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 85667#L1539 assume !(0 == start_simulation_~tmp~3#1); 85664#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 85621#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 85615#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 85613#L822-2 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 85611#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 85595#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 85585#L1502 start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 85577#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 85570#L1520-2 [2022-02-21 04:24:53,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:53,800 INFO L85 PathProgramCache]: Analyzing trace with hash -1298324745, now seen corresponding path program 1 times [2022-02-21 04:24:53,800 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:53,800 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635173676] [2022-02-21 04:24:53,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:53,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:53,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:53,824 INFO L290 TraceCheckUtils]: 0: Hoare triple {110315#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,825 INFO L290 TraceCheckUtils]: 1: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,825 INFO L290 TraceCheckUtils]: 2: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,826 INFO L290 TraceCheckUtils]: 3: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,826 INFO L290 TraceCheckUtils]: 4: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,826 INFO L290 TraceCheckUtils]: 5: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,826 INFO L290 TraceCheckUtils]: 6: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,827 INFO L290 TraceCheckUtils]: 7: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,827 INFO L290 TraceCheckUtils]: 8: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,827 INFO L290 TraceCheckUtils]: 9: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,828 INFO L290 TraceCheckUtils]: 10: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,828 INFO L290 TraceCheckUtils]: 11: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,828 INFO L290 TraceCheckUtils]: 12: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,829 INFO L290 TraceCheckUtils]: 13: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,829 INFO L290 TraceCheckUtils]: 14: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,829 INFO L290 TraceCheckUtils]: 15: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,830 INFO L290 TraceCheckUtils]: 16: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,830 INFO L290 TraceCheckUtils]: 17: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,830 INFO L290 TraceCheckUtils]: 18: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,831 INFO L290 TraceCheckUtils]: 19: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,831 INFO L290 TraceCheckUtils]: 20: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,831 INFO L290 TraceCheckUtils]: 21: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T5_E~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,832 INFO L290 TraceCheckUtils]: 22: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T6_E~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,832 INFO L290 TraceCheckUtils]: 23: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T7_E~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,832 INFO L290 TraceCheckUtils]: 24: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T8_E~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,832 INFO L290 TraceCheckUtils]: 25: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T9_E~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,833 INFO L290 TraceCheckUtils]: 26: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T10_E~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,833 INFO L290 TraceCheckUtils]: 27: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,833 INFO L290 TraceCheckUtils]: 28: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,834 INFO L290 TraceCheckUtils]: 29: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,834 INFO L290 TraceCheckUtils]: 30: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,834 INFO L290 TraceCheckUtils]: 31: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_5~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,835 INFO L290 TraceCheckUtils]: 32: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_6~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,835 INFO L290 TraceCheckUtils]: 33: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_7~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,835 INFO L290 TraceCheckUtils]: 34: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_8~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,836 INFO L290 TraceCheckUtils]: 35: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_9~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,836 INFO L290 TraceCheckUtils]: 36: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_10~0); {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,836 INFO L290 TraceCheckUtils]: 37: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {110317#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:24:53,836 INFO L290 TraceCheckUtils]: 38: Hoare triple {110317#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {110318#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:53,837 INFO L290 TraceCheckUtils]: 39: Hoare triple {110318#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {110318#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:53,837 INFO L290 TraceCheckUtils]: 40: Hoare triple {110318#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {110318#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:53,837 INFO L290 TraceCheckUtils]: 41: Hoare triple {110318#(not (= ~t1_pc~0 1))} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {110318#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:53,838 INFO L290 TraceCheckUtils]: 42: Hoare triple {110318#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {110318#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:53,838 INFO L290 TraceCheckUtils]: 43: Hoare triple {110318#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {110318#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:24:53,838 INFO L290 TraceCheckUtils]: 44: Hoare triple {110318#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {110316#false} is VALID [2022-02-21 04:24:53,838 INFO L290 TraceCheckUtils]: 45: Hoare triple {110316#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {110316#false} is VALID [2022-02-21 04:24:53,838 INFO L290 TraceCheckUtils]: 46: Hoare triple {110316#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {110316#false} is VALID [2022-02-21 04:24:53,839 INFO L290 TraceCheckUtils]: 47: Hoare triple {110316#false} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {110316#false} is VALID [2022-02-21 04:24:53,839 INFO L290 TraceCheckUtils]: 48: Hoare triple {110316#false} assume !(0 != activate_threads_~tmp___0~0#1); {110316#false} is VALID [2022-02-21 04:24:53,839 INFO L290 TraceCheckUtils]: 49: Hoare triple {110316#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {110316#false} is VALID [2022-02-21 04:24:53,839 INFO L290 TraceCheckUtils]: 50: Hoare triple {110316#false} assume !(1 == ~t2_pc~0); {110316#false} is VALID [2022-02-21 04:24:53,839 INFO L290 TraceCheckUtils]: 51: Hoare triple {110316#false} is_transmit2_triggered_~__retres1~2#1 := 0; {110316#false} is VALID [2022-02-21 04:24:53,839 INFO L290 TraceCheckUtils]: 52: Hoare triple {110316#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {110316#false} is VALID [2022-02-21 04:24:53,839 INFO L290 TraceCheckUtils]: 53: Hoare triple {110316#false} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {110316#false} is VALID [2022-02-21 04:24:53,839 INFO L290 TraceCheckUtils]: 54: Hoare triple {110316#false} assume !(0 != activate_threads_~tmp___1~0#1); {110316#false} is VALID [2022-02-21 04:24:53,839 INFO L290 TraceCheckUtils]: 55: Hoare triple {110316#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {110316#false} is VALID [2022-02-21 04:24:53,840 INFO L290 TraceCheckUtils]: 56: Hoare triple {110316#false} assume 1 == ~t3_pc~0; {110316#false} is VALID [2022-02-21 04:24:53,840 INFO L290 TraceCheckUtils]: 57: Hoare triple {110316#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {110316#false} is VALID [2022-02-21 04:24:53,840 INFO L290 TraceCheckUtils]: 58: Hoare triple {110316#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {110316#false} is VALID [2022-02-21 04:24:53,840 INFO L290 TraceCheckUtils]: 59: Hoare triple {110316#false} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {110316#false} is VALID [2022-02-21 04:24:53,840 INFO L290 TraceCheckUtils]: 60: Hoare triple {110316#false} assume !(0 != activate_threads_~tmp___2~0#1); {110316#false} is VALID [2022-02-21 04:24:53,840 INFO L290 TraceCheckUtils]: 61: Hoare triple {110316#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {110316#false} is VALID [2022-02-21 04:24:53,840 INFO L290 TraceCheckUtils]: 62: Hoare triple {110316#false} assume !(1 == ~t4_pc~0); {110316#false} is VALID [2022-02-21 04:24:53,840 INFO L290 TraceCheckUtils]: 63: Hoare triple {110316#false} is_transmit4_triggered_~__retres1~4#1 := 0; {110316#false} is VALID [2022-02-21 04:24:53,840 INFO L290 TraceCheckUtils]: 64: Hoare triple {110316#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {110316#false} is VALID [2022-02-21 04:24:53,841 INFO L290 TraceCheckUtils]: 65: Hoare triple {110316#false} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {110316#false} is VALID [2022-02-21 04:24:53,841 INFO L290 TraceCheckUtils]: 66: Hoare triple {110316#false} assume !(0 != activate_threads_~tmp___3~0#1); {110316#false} is VALID [2022-02-21 04:24:53,841 INFO L290 TraceCheckUtils]: 67: Hoare triple {110316#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {110316#false} is VALID [2022-02-21 04:24:53,841 INFO L290 TraceCheckUtils]: 68: Hoare triple {110316#false} assume 1 == ~t5_pc~0; {110316#false} is VALID [2022-02-21 04:24:53,841 INFO L290 TraceCheckUtils]: 69: Hoare triple {110316#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {110316#false} is VALID [2022-02-21 04:24:53,841 INFO L290 TraceCheckUtils]: 70: Hoare triple {110316#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {110316#false} is VALID [2022-02-21 04:24:53,841 INFO L290 TraceCheckUtils]: 71: Hoare triple {110316#false} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {110316#false} is VALID [2022-02-21 04:24:53,841 INFO L290 TraceCheckUtils]: 72: Hoare triple {110316#false} assume !(0 != activate_threads_~tmp___4~0#1); {110316#false} is VALID [2022-02-21 04:24:53,841 INFO L290 TraceCheckUtils]: 73: Hoare triple {110316#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {110316#false} is VALID [2022-02-21 04:24:53,842 INFO L290 TraceCheckUtils]: 74: Hoare triple {110316#false} assume 1 == ~t6_pc~0; {110316#false} is VALID [2022-02-21 04:24:53,842 INFO L290 TraceCheckUtils]: 75: Hoare triple {110316#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {110316#false} is VALID [2022-02-21 04:24:53,842 INFO L290 TraceCheckUtils]: 76: Hoare triple {110316#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {110316#false} is VALID [2022-02-21 04:24:53,842 INFO L290 TraceCheckUtils]: 77: Hoare triple {110316#false} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {110316#false} is VALID [2022-02-21 04:24:53,842 INFO L290 TraceCheckUtils]: 78: Hoare triple {110316#false} assume !(0 != activate_threads_~tmp___5~0#1); {110316#false} is VALID [2022-02-21 04:24:53,842 INFO L290 TraceCheckUtils]: 79: Hoare triple {110316#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {110316#false} is VALID [2022-02-21 04:24:53,842 INFO L290 TraceCheckUtils]: 80: Hoare triple {110316#false} assume !(1 == ~t7_pc~0); {110316#false} is VALID [2022-02-21 04:24:53,842 INFO L290 TraceCheckUtils]: 81: Hoare triple {110316#false} is_transmit7_triggered_~__retres1~7#1 := 0; {110316#false} is VALID [2022-02-21 04:24:53,842 INFO L290 TraceCheckUtils]: 82: Hoare triple {110316#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {110316#false} is VALID [2022-02-21 04:24:53,843 INFO L290 TraceCheckUtils]: 83: Hoare triple {110316#false} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {110316#false} is VALID [2022-02-21 04:24:53,843 INFO L290 TraceCheckUtils]: 84: Hoare triple {110316#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {110316#false} is VALID [2022-02-21 04:24:53,843 INFO L290 TraceCheckUtils]: 85: Hoare triple {110316#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {110316#false} is VALID [2022-02-21 04:24:53,843 INFO L290 TraceCheckUtils]: 86: Hoare triple {110316#false} assume 1 == ~t8_pc~0; {110316#false} is VALID [2022-02-21 04:24:53,843 INFO L290 TraceCheckUtils]: 87: Hoare triple {110316#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {110316#false} is VALID [2022-02-21 04:24:53,843 INFO L290 TraceCheckUtils]: 88: Hoare triple {110316#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {110316#false} is VALID [2022-02-21 04:24:53,843 INFO L290 TraceCheckUtils]: 89: Hoare triple {110316#false} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {110316#false} is VALID [2022-02-21 04:24:53,843 INFO L290 TraceCheckUtils]: 90: Hoare triple {110316#false} assume !(0 != activate_threads_~tmp___7~0#1); {110316#false} is VALID [2022-02-21 04:24:53,843 INFO L290 TraceCheckUtils]: 91: Hoare triple {110316#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {110316#false} is VALID [2022-02-21 04:24:53,844 INFO L290 TraceCheckUtils]: 92: Hoare triple {110316#false} assume !(1 == ~t9_pc~0); {110316#false} is VALID [2022-02-21 04:24:53,844 INFO L290 TraceCheckUtils]: 93: Hoare triple {110316#false} is_transmit9_triggered_~__retres1~9#1 := 0; {110316#false} is VALID [2022-02-21 04:24:53,844 INFO L290 TraceCheckUtils]: 94: Hoare triple {110316#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {110316#false} is VALID [2022-02-21 04:24:53,844 INFO L290 TraceCheckUtils]: 95: Hoare triple {110316#false} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {110316#false} is VALID [2022-02-21 04:24:53,844 INFO L290 TraceCheckUtils]: 96: Hoare triple {110316#false} assume !(0 != activate_threads_~tmp___8~0#1); {110316#false} is VALID [2022-02-21 04:24:53,844 INFO L290 TraceCheckUtils]: 97: Hoare triple {110316#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {110316#false} is VALID [2022-02-21 04:24:53,844 INFO L290 TraceCheckUtils]: 98: Hoare triple {110316#false} assume 1 == ~t10_pc~0; {110316#false} is VALID [2022-02-21 04:24:53,844 INFO L290 TraceCheckUtils]: 99: Hoare triple {110316#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {110316#false} is VALID [2022-02-21 04:24:53,844 INFO L290 TraceCheckUtils]: 100: Hoare triple {110316#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {110316#false} is VALID [2022-02-21 04:24:53,845 INFO L290 TraceCheckUtils]: 101: Hoare triple {110316#false} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {110316#false} is VALID [2022-02-21 04:24:53,845 INFO L290 TraceCheckUtils]: 102: Hoare triple {110316#false} assume !(0 != activate_threads_~tmp___9~0#1); {110316#false} is VALID [2022-02-21 04:24:53,845 INFO L290 TraceCheckUtils]: 103: Hoare triple {110316#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {110316#false} is VALID [2022-02-21 04:24:53,845 INFO L290 TraceCheckUtils]: 104: Hoare triple {110316#false} assume !(1 == ~M_E~0); {110316#false} is VALID [2022-02-21 04:24:53,845 INFO L290 TraceCheckUtils]: 105: Hoare triple {110316#false} assume !(1 == ~T1_E~0); {110316#false} is VALID [2022-02-21 04:24:53,845 INFO L290 TraceCheckUtils]: 106: Hoare triple {110316#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {110316#false} is VALID [2022-02-21 04:24:53,845 INFO L290 TraceCheckUtils]: 107: Hoare triple {110316#false} assume !(1 == ~T3_E~0); {110316#false} is VALID [2022-02-21 04:24:53,845 INFO L290 TraceCheckUtils]: 108: Hoare triple {110316#false} assume !(1 == ~T4_E~0); {110316#false} is VALID [2022-02-21 04:24:53,845 INFO L290 TraceCheckUtils]: 109: Hoare triple {110316#false} assume !(1 == ~T5_E~0); {110316#false} is VALID [2022-02-21 04:24:53,846 INFO L290 TraceCheckUtils]: 110: Hoare triple {110316#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {110316#false} is VALID [2022-02-21 04:24:53,846 INFO L290 TraceCheckUtils]: 111: Hoare triple {110316#false} assume !(1 == ~T7_E~0); {110316#false} is VALID [2022-02-21 04:24:53,846 INFO L290 TraceCheckUtils]: 112: Hoare triple {110316#false} assume !(1 == ~T8_E~0); {110316#false} is VALID [2022-02-21 04:24:53,846 INFO L290 TraceCheckUtils]: 113: Hoare triple {110316#false} assume !(1 == ~T9_E~0); {110316#false} is VALID [2022-02-21 04:24:53,846 INFO L290 TraceCheckUtils]: 114: Hoare triple {110316#false} assume !(1 == ~T10_E~0); {110316#false} is VALID [2022-02-21 04:24:53,846 INFO L290 TraceCheckUtils]: 115: Hoare triple {110316#false} assume !(1 == ~E_1~0); {110316#false} is VALID [2022-02-21 04:24:53,846 INFO L290 TraceCheckUtils]: 116: Hoare triple {110316#false} assume !(1 == ~E_2~0); {110316#false} is VALID [2022-02-21 04:24:53,846 INFO L290 TraceCheckUtils]: 117: Hoare triple {110316#false} assume !(1 == ~E_3~0); {110316#false} is VALID [2022-02-21 04:24:53,846 INFO L290 TraceCheckUtils]: 118: Hoare triple {110316#false} assume 1 == ~E_4~0;~E_4~0 := 2; {110316#false} is VALID [2022-02-21 04:24:53,847 INFO L290 TraceCheckUtils]: 119: Hoare triple {110316#false} assume !(1 == ~E_5~0); {110316#false} is VALID [2022-02-21 04:24:53,847 INFO L290 TraceCheckUtils]: 120: Hoare triple {110316#false} assume !(1 == ~E_6~0); {110316#false} is VALID [2022-02-21 04:24:53,847 INFO L290 TraceCheckUtils]: 121: Hoare triple {110316#false} assume !(1 == ~E_7~0); {110316#false} is VALID [2022-02-21 04:24:53,847 INFO L290 TraceCheckUtils]: 122: Hoare triple {110316#false} assume !(1 == ~E_8~0); {110316#false} is VALID [2022-02-21 04:24:53,847 INFO L290 TraceCheckUtils]: 123: Hoare triple {110316#false} assume !(1 == ~E_9~0); {110316#false} is VALID [2022-02-21 04:24:53,847 INFO L290 TraceCheckUtils]: 124: Hoare triple {110316#false} assume !(1 == ~E_10~0); {110316#false} is VALID [2022-02-21 04:24:53,847 INFO L290 TraceCheckUtils]: 125: Hoare triple {110316#false} assume { :end_inline_reset_delta_events } true; {110316#false} is VALID [2022-02-21 04:24:53,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:53,848 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:53,848 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [635173676] [2022-02-21 04:24:53,848 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [635173676] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:53,848 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:53,848 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:53,848 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762857357] [2022-02-21 04:24:53,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:53,849 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:53,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:53,850 INFO L85 PathProgramCache]: Analyzing trace with hash -176062259, now seen corresponding path program 1 times [2022-02-21 04:24:53,850 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:53,850 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143600054] [2022-02-21 04:24:53,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:53,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:53,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:53,875 INFO L290 TraceCheckUtils]: 0: Hoare triple {110319#true} assume !false; {110319#true} is VALID [2022-02-21 04:24:53,875 INFO L290 TraceCheckUtils]: 1: Hoare triple {110319#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {110319#true} is VALID [2022-02-21 04:24:53,876 INFO L290 TraceCheckUtils]: 2: Hoare triple {110319#true} assume !false; {110319#true} is VALID [2022-02-21 04:24:53,876 INFO L290 TraceCheckUtils]: 3: Hoare triple {110319#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {110319#true} is VALID [2022-02-21 04:24:53,876 INFO L290 TraceCheckUtils]: 4: Hoare triple {110319#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {110319#true} is VALID [2022-02-21 04:24:53,876 INFO L290 TraceCheckUtils]: 5: Hoare triple {110319#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {110319#true} is VALID [2022-02-21 04:24:53,876 INFO L290 TraceCheckUtils]: 6: Hoare triple {110319#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {110319#true} is VALID [2022-02-21 04:24:53,876 INFO L290 TraceCheckUtils]: 7: Hoare triple {110319#true} assume !(0 != eval_~tmp~0#1); {110319#true} is VALID [2022-02-21 04:24:53,876 INFO L290 TraceCheckUtils]: 8: Hoare triple {110319#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {110319#true} is VALID [2022-02-21 04:24:53,876 INFO L290 TraceCheckUtils]: 9: Hoare triple {110319#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {110319#true} is VALID [2022-02-21 04:24:53,877 INFO L290 TraceCheckUtils]: 10: Hoare triple {110319#true} assume 0 == ~M_E~0;~M_E~0 := 1; {110319#true} is VALID [2022-02-21 04:24:53,877 INFO L290 TraceCheckUtils]: 11: Hoare triple {110319#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {110319#true} is VALID [2022-02-21 04:24:53,877 INFO L290 TraceCheckUtils]: 12: Hoare triple {110319#true} assume !(0 == ~T2_E~0); {110319#true} is VALID [2022-02-21 04:24:53,877 INFO L290 TraceCheckUtils]: 13: Hoare triple {110319#true} assume !(0 == ~T3_E~0); {110319#true} is VALID [2022-02-21 04:24:53,877 INFO L290 TraceCheckUtils]: 14: Hoare triple {110319#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {110319#true} is VALID [2022-02-21 04:24:53,877 INFO L290 TraceCheckUtils]: 15: Hoare triple {110319#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,878 INFO L290 TraceCheckUtils]: 16: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,878 INFO L290 TraceCheckUtils]: 17: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,878 INFO L290 TraceCheckUtils]: 18: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,879 INFO L290 TraceCheckUtils]: 19: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,879 INFO L290 TraceCheckUtils]: 20: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T10_E~0); {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,879 INFO L290 TraceCheckUtils]: 21: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_1~0); {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,880 INFO L290 TraceCheckUtils]: 22: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,880 INFO L290 TraceCheckUtils]: 23: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,880 INFO L290 TraceCheckUtils]: 24: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,881 INFO L290 TraceCheckUtils]: 25: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,881 INFO L290 TraceCheckUtils]: 26: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,881 INFO L290 TraceCheckUtils]: 27: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,881 INFO L290 TraceCheckUtils]: 28: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_8~0); {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,882 INFO L290 TraceCheckUtils]: 29: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_9~0); {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,882 INFO L290 TraceCheckUtils]: 30: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,882 INFO L290 TraceCheckUtils]: 31: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,883 INFO L290 TraceCheckUtils]: 32: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,883 INFO L290 TraceCheckUtils]: 33: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,883 INFO L290 TraceCheckUtils]: 34: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,884 INFO L290 TraceCheckUtils]: 35: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret16#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,884 INFO L290 TraceCheckUtils]: 36: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,884 INFO L290 TraceCheckUtils]: 37: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,885 INFO L290 TraceCheckUtils]: 38: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,885 INFO L290 TraceCheckUtils]: 39: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,885 INFO L290 TraceCheckUtils]: 40: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,886 INFO L290 TraceCheckUtils]: 41: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,886 INFO L290 TraceCheckUtils]: 42: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,887 INFO L290 TraceCheckUtils]: 43: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,887 INFO L290 TraceCheckUtils]: 44: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,887 INFO L290 TraceCheckUtils]: 45: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,888 INFO L290 TraceCheckUtils]: 46: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,888 INFO L290 TraceCheckUtils]: 47: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,888 INFO L290 TraceCheckUtils]: 48: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,889 INFO L290 TraceCheckUtils]: 49: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,889 INFO L290 TraceCheckUtils]: 50: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,889 INFO L290 TraceCheckUtils]: 51: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,889 INFO L290 TraceCheckUtils]: 52: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,890 INFO L290 TraceCheckUtils]: 53: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,890 INFO L290 TraceCheckUtils]: 54: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,890 INFO L290 TraceCheckUtils]: 55: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,891 INFO L290 TraceCheckUtils]: 56: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,891 INFO L290 TraceCheckUtils]: 57: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,891 INFO L290 TraceCheckUtils]: 58: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,892 INFO L290 TraceCheckUtils]: 59: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,892 INFO L290 TraceCheckUtils]: 60: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___3~0#1); {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,892 INFO L290 TraceCheckUtils]: 61: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,893 INFO L290 TraceCheckUtils]: 62: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,893 INFO L290 TraceCheckUtils]: 63: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,893 INFO L290 TraceCheckUtils]: 64: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,894 INFO L290 TraceCheckUtils]: 65: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,894 INFO L290 TraceCheckUtils]: 66: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,894 INFO L290 TraceCheckUtils]: 67: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,894 INFO L290 TraceCheckUtils]: 68: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,895 INFO L290 TraceCheckUtils]: 69: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,895 INFO L290 TraceCheckUtils]: 70: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,895 INFO L290 TraceCheckUtils]: 71: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,899 INFO L290 TraceCheckUtils]: 72: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,899 INFO L290 TraceCheckUtils]: 73: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,899 INFO L290 TraceCheckUtils]: 74: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,900 INFO L290 TraceCheckUtils]: 75: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,900 INFO L290 TraceCheckUtils]: 76: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,900 INFO L290 TraceCheckUtils]: 77: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,901 INFO L290 TraceCheckUtils]: 78: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,901 INFO L290 TraceCheckUtils]: 79: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,901 INFO L290 TraceCheckUtils]: 80: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,902 INFO L290 TraceCheckUtils]: 81: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,902 INFO L290 TraceCheckUtils]: 82: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,902 INFO L290 TraceCheckUtils]: 83: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,903 INFO L290 TraceCheckUtils]: 84: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,903 INFO L290 TraceCheckUtils]: 85: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,903 INFO L290 TraceCheckUtils]: 86: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,903 INFO L290 TraceCheckUtils]: 87: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,904 INFO L290 TraceCheckUtils]: 88: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,904 INFO L290 TraceCheckUtils]: 89: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,904 INFO L290 TraceCheckUtils]: 90: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,905 INFO L290 TraceCheckUtils]: 91: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,905 INFO L290 TraceCheckUtils]: 92: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,905 INFO L290 TraceCheckUtils]: 93: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,906 INFO L290 TraceCheckUtils]: 94: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,906 INFO L290 TraceCheckUtils]: 95: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,906 INFO L290 TraceCheckUtils]: 96: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,907 INFO L290 TraceCheckUtils]: 97: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,907 INFO L290 TraceCheckUtils]: 98: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,907 INFO L290 TraceCheckUtils]: 99: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,908 INFO L290 TraceCheckUtils]: 100: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,908 INFO L290 TraceCheckUtils]: 101: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,908 INFO L290 TraceCheckUtils]: 102: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {110321#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,909 INFO L290 TraceCheckUtils]: 103: Hoare triple {110321#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {110320#false} is VALID [2022-02-21 04:24:53,909 INFO L290 TraceCheckUtils]: 104: Hoare triple {110320#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,909 INFO L290 TraceCheckUtils]: 105: Hoare triple {110320#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,909 INFO L290 TraceCheckUtils]: 106: Hoare triple {110320#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,909 INFO L290 TraceCheckUtils]: 107: Hoare triple {110320#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,909 INFO L290 TraceCheckUtils]: 108: Hoare triple {110320#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,909 INFO L290 TraceCheckUtils]: 109: Hoare triple {110320#false} assume 1 == ~E_1~0;~E_1~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,909 INFO L290 TraceCheckUtils]: 110: Hoare triple {110320#false} assume 1 == ~E_2~0;~E_2~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,910 INFO L290 TraceCheckUtils]: 111: Hoare triple {110320#false} assume !(1 == ~E_3~0); {110320#false} is VALID [2022-02-21 04:24:53,910 INFO L290 TraceCheckUtils]: 112: Hoare triple {110320#false} assume 1 == ~E_4~0;~E_4~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,910 INFO L290 TraceCheckUtils]: 113: Hoare triple {110320#false} assume 1 == ~E_5~0;~E_5~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,910 INFO L290 TraceCheckUtils]: 114: Hoare triple {110320#false} assume 1 == ~E_6~0;~E_6~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,910 INFO L290 TraceCheckUtils]: 115: Hoare triple {110320#false} assume 1 == ~E_7~0;~E_7~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,910 INFO L290 TraceCheckUtils]: 116: Hoare triple {110320#false} assume 1 == ~E_8~0;~E_8~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,910 INFO L290 TraceCheckUtils]: 117: Hoare triple {110320#false} assume 1 == ~E_9~0;~E_9~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,910 INFO L290 TraceCheckUtils]: 118: Hoare triple {110320#false} assume 1 == ~E_10~0;~E_10~0 := 2; {110320#false} is VALID [2022-02-21 04:24:53,910 INFO L290 TraceCheckUtils]: 119: Hoare triple {110320#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {110320#false} is VALID [2022-02-21 04:24:53,911 INFO L290 TraceCheckUtils]: 120: Hoare triple {110320#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {110320#false} is VALID [2022-02-21 04:24:53,911 INFO L290 TraceCheckUtils]: 121: Hoare triple {110320#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {110320#false} is VALID [2022-02-21 04:24:53,911 INFO L290 TraceCheckUtils]: 122: Hoare triple {110320#false} start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; {110320#false} is VALID [2022-02-21 04:24:53,911 INFO L290 TraceCheckUtils]: 123: Hoare triple {110320#false} assume !(0 == start_simulation_~tmp~3#1); {110320#false} is VALID [2022-02-21 04:24:53,911 INFO L290 TraceCheckUtils]: 124: Hoare triple {110320#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; {110320#false} is VALID [2022-02-21 04:24:53,911 INFO L290 TraceCheckUtils]: 125: Hoare triple {110320#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; {110320#false} is VALID [2022-02-21 04:24:53,911 INFO L290 TraceCheckUtils]: 126: Hoare triple {110320#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; {110320#false} is VALID [2022-02-21 04:24:53,911 INFO L290 TraceCheckUtils]: 127: Hoare triple {110320#false} stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; {110320#false} is VALID [2022-02-21 04:24:53,911 INFO L290 TraceCheckUtils]: 128: Hoare triple {110320#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {110320#false} is VALID [2022-02-21 04:24:53,912 INFO L290 TraceCheckUtils]: 129: Hoare triple {110320#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {110320#false} is VALID [2022-02-21 04:24:53,912 INFO L290 TraceCheckUtils]: 130: Hoare triple {110320#false} start_simulation_#t~ret29#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; {110320#false} is VALID [2022-02-21 04:24:53,912 INFO L290 TraceCheckUtils]: 131: Hoare triple {110320#false} assume !(0 != start_simulation_~tmp___0~1#1); {110320#false} is VALID [2022-02-21 04:24:53,912 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:53,912 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:53,912 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1143600054] [2022-02-21 04:24:53,913 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1143600054] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:53,913 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:53,913 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:53,913 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1770983799] [2022-02-21 04:24:53,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:53,938 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:53,938 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:53,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:53,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:53,939 INFO L87 Difference]: Start difference. First operand 8692 states and 12830 transitions. cyclomatic complexity: 4146 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:09,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:09,031 INFO L93 Difference]: Finished difference Result 24690 states and 36034 transitions. [2022-02-21 04:25:09,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:25:09,032 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:09,104 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:09,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24690 states and 36034 transitions. [2022-02-21 04:25:22,068 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24124