./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.12.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.12.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:24:17,501 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:24:17,503 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:24:17,533 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:24:17,534 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:24:17,536 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:24:17,538 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:24:17,540 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:24:17,541 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:24:17,544 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:24:17,545 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:24:17,546 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:24:17,546 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:24:17,548 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:24:17,550 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:24:17,552 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:24:17,553 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:24:17,553 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:24:17,555 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:24:17,558 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:24:17,559 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:24:17,560 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:24:17,561 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:24:17,562 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:24:17,567 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:24:17,567 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:24:17,568 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:24:17,569 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:24:17,569 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:24:17,570 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:24:17,570 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:24:17,571 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:24:17,572 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:24:17,573 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:24:17,574 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:24:17,575 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:24:17,575 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:24:17,575 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:24:17,575 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:24:17,576 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:24:17,577 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:24:17,577 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:24:17,603 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:24:17,603 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:24:17,604 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:24:17,604 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:24:17,605 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:24:17,605 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:24:17,606 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:24:17,606 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:24:17,606 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:24:17,606 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:24:17,607 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:24:17,607 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:24:17,607 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:24:17,607 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:24:17,607 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:24:17,608 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:24:17,608 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:24:17,608 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:24:17,608 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:24:17,608 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:24:17,608 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:24:17,609 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:24:17,609 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:24:17,609 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:24:17,609 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:24:17,609 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:24:17,609 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:24:17,610 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:24:17,610 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:24:17,610 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:24:17,610 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:24:17,611 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:24:17,611 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 [2022-02-21 04:24:17,934 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:24:17,965 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:24:17,970 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:24:17,971 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:24:17,972 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:24:17,973 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.12.cil.c [2022-02-21 04:24:18,040 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5e81e4088/68d32ee21e544c6eb59461716a22983f/FLAG88ae202f8 [2022-02-21 04:24:18,520 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:18,531 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.12.cil.c [2022-02-21 04:24:18,553 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5e81e4088/68d32ee21e544c6eb59461716a22983f/FLAG88ae202f8 [2022-02-21 04:24:18,904 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5e81e4088/68d32ee21e544c6eb59461716a22983f [2022-02-21 04:24:18,906 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:18,908 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:18,915 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:18,915 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:18,918 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:18,919 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:18" (1/1) ... [2022-02-21 04:24:18,920 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@18e44b7b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:18, skipping insertion in model container [2022-02-21 04:24:18,920 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:18" (1/1) ... [2022-02-21 04:24:18,925 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:18,969 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:19,131 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2022-02-21 04:24:19,369 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:19,393 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:19,420 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.12.cil.c[706,719] [2022-02-21 04:24:19,550 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:19,566 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:19,567 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19 WrapperNode [2022-02-21 04:24:19,567 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:19,568 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:19,568 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:19,568 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:19,573 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,597 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,687 INFO L137 Inliner]: procedures = 52, calls = 66, calls flagged for inlining = 61, calls inlined = 254, statements flattened = 3910 [2022-02-21 04:24:19,687 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:19,688 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:19,688 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:19,688 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:19,694 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,694 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,700 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,701 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,725 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,756 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,762 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,772 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:19,773 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:19,773 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:19,773 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:19,774 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,780 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:19,789 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:19,834 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:19,858 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:19,874 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:19,875 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:19,875 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:19,875 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:19,980 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:19,981 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:21,708 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:21,755 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:21,756 INFO L299 CfgBuilder]: Removed 16 assume(true) statements. [2022-02-21 04:24:21,762 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:21 BoogieIcfgContainer [2022-02-21 04:24:21,762 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:21,764 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:21,764 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:21,766 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:21,767 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:21,767 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:18" (1/3) ... [2022-02-21 04:24:21,768 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@45af6993 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:21, skipping insertion in model container [2022-02-21 04:24:21,768 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:21,768 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (2/3) ... [2022-02-21 04:24:21,768 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@45af6993 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:21, skipping insertion in model container [2022-02-21 04:24:21,768 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:21,768 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:21" (3/3) ... [2022-02-21 04:24:21,769 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.12.cil.c [2022-02-21 04:24:21,838 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:21,838 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:21,838 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:21,839 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:21,839 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:21,839 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:21,839 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:21,839 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:21,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2022-02-21 04:24:22,177 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:22,177 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:22,187 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,188 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,188 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:22,192 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1530 [2022-02-21 04:24:22,345 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:22,345 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:22,347 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,347 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,354 INFO L791 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 1609#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1450#L1731true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 696#L814true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 529#L821true assume !(1 == ~m_i~0);~m_st~0 := 2; 598#L821-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 877#L826-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1186#L831-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1031#L836-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1332#L841-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 120#L846-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1624#L851-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 945#L856-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 451#L861-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 481#L866-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 392#L871-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 700#L876-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 693#L881-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 244#L1174true assume !(0 == ~M_E~0); 1354#L1174-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 167#L1179-1true assume !(0 == ~T2_E~0); 119#L1184-1true assume !(0 == ~T3_E~0); 138#L1189-1true assume !(0 == ~T4_E~0); 188#L1194-1true assume !(0 == ~T5_E~0); 819#L1199-1true assume !(0 == ~T6_E~0); 979#L1204-1true assume !(0 == ~T7_E~0); 742#L1209-1true assume !(0 == ~T8_E~0); 1244#L1214-1true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1637#L1219-1true assume !(0 == ~T10_E~0); 1555#L1224-1true assume !(0 == ~T11_E~0); 307#L1229-1true assume !(0 == ~T12_E~0); 83#L1234-1true assume !(0 == ~E_1~0); 491#L1239-1true assume !(0 == ~E_2~0); 98#L1244-1true assume !(0 == ~E_3~0); 1336#L1249-1true assume !(0 == ~E_4~0); 468#L1254-1true assume 0 == ~E_5~0;~E_5~0 := 1; 51#L1259-1true assume !(0 == ~E_6~0); 31#L1264-1true assume !(0 == ~E_7~0); 1688#L1269-1true assume !(0 == ~E_8~0); 1612#L1274-1true assume !(0 == ~E_9~0); 1325#L1279-1true assume !(0 == ~E_10~0); 140#L1284-1true assume !(0 == ~E_11~0); 1466#L1289-1true assume !(0 == ~E_12~0); 508#L1294-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1341#L566true assume 1 == ~m_pc~0; 39#L567true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 972#L577true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 767#L578true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1189#L1455true assume !(0 != activate_threads_~tmp~1#1); 256#L1455-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 791#L585true assume 1 == ~t1_pc~0; 82#L586true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1616#L596true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 714#L597true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1535#L1463true assume !(0 != activate_threads_~tmp___0~0#1); 1404#L1463-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1397#L604true assume !(1 == ~t2_pc~0); 783#L604-2true is_transmit2_triggered_~__retres1~2#1 := 0; 1363#L615true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 413#L616true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1198#L1471true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 986#L1471-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1465#L623true assume 1 == ~t3_pc~0; 359#L624true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1662#L634true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 454#L635true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1025#L1479true assume !(0 != activate_threads_~tmp___2~0#1); 1242#L1479-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38#L642true assume !(1 == ~t4_pc~0); 663#L642-2true is_transmit4_triggered_~__retres1~4#1 := 0; 265#L653true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 521#L654true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71#L1487true assume !(0 != activate_threads_~tmp___3~0#1); 796#L1487-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1123#L661true assume 1 == ~t5_pc~0; 149#L662true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 708#L672true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130#L673true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1100#L1495true assume !(0 != activate_threads_~tmp___4~0#1); 827#L1495-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1689#L680true assume !(1 == ~t6_pc~0); 1691#L680-2true is_transmit6_triggered_~__retres1~6#1 := 0; 1490#L691true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 562#L692true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1115#L1503true assume !(0 != activate_threads_~tmp___5~0#1); 1401#L1503-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1393#L699true assume 1 == ~t7_pc~0; 674#L700true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 894#L710true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 144#L711true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 589#L1511true assume !(0 != activate_threads_~tmp___6~0#1); 804#L1511-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 509#L718true assume !(1 == ~t8_pc~0); 1250#L718-2true is_transmit8_triggered_~__retres1~8#1 := 0; 137#L729true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1499#L730true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 158#L1519true assume !(0 != activate_threads_~tmp___7~0#1); 226#L1519-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 857#L737true assume 1 == ~t9_pc~0; 1502#L738true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1284#L748true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 735#L749true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1638#L1527true assume !(0 != activate_threads_~tmp___8~0#1); 404#L1527-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1094#L756true assume 1 == ~t10_pc~0; 887#L757true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 814#L767true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5#L768true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 536#L1535true assume !(0 != activate_threads_~tmp___9~0#1); 290#L1535-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 754#L775true assume !(1 == ~t11_pc~0); 445#L775-2true is_transmit11_triggered_~__retres1~11#1 := 0; 1262#L786true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 223#L787true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104#L1543true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 849#L1543-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 198#L794true assume 1 == ~t12_pc~0; 117#L795true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1101#L805true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 975#L806true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 181#L1551true assume !(0 != activate_threads_~tmp___11~0#1); 690#L1551-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 456#L1307true assume !(1 == ~M_E~0); 541#L1307-2true assume !(1 == ~T1_E~0); 1445#L1312-1true assume !(1 == ~T2_E~0); 479#L1317-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 640#L1322-1true assume !(1 == ~T4_E~0); 295#L1327-1true assume !(1 == ~T5_E~0); 677#L1332-1true assume !(1 == ~T6_E~0); 1414#L1337-1true assume !(1 == ~T7_E~0); 636#L1342-1true assume !(1 == ~T8_E~0); 1322#L1347-1true assume !(1 == ~T9_E~0); 1065#L1352-1true assume !(1 == ~T10_E~0); 895#L1357-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 391#L1362-1true assume !(1 == ~T12_E~0); 1136#L1367-1true assume !(1 == ~E_1~0); 189#L1372-1true assume !(1 == ~E_2~0); 488#L1377-1true assume !(1 == ~E_3~0); 351#L1382-1true assume !(1 == ~E_4~0); 784#L1387-1true assume !(1 == ~E_5~0); 1258#L1392-1true assume !(1 == ~E_6~0); 363#L1397-1true assume 1 == ~E_7~0;~E_7~0 := 2; 1389#L1402-1true assume !(1 == ~E_8~0); 195#L1407-1true assume !(1 == ~E_9~0); 1520#L1412-1true assume !(1 == ~E_10~0); 974#L1417-1true assume !(1 == ~E_11~0); 1696#L1422-1true assume !(1 == ~E_12~0); 1385#L1427-1true assume { :end_inline_reset_delta_events } true; 96#L1768-2true [2022-02-21 04:24:22,357 INFO L793 eck$LassoCheckResult]: Loop: 96#L1768-2true assume !false; 522#L1769true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 844#L1149true assume false; 1434#L1164true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1419#L814-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 999#L1174-3true assume !(0 == ~M_E~0); 992#L1174-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 717#L1179-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1398#L1184-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 896#L1189-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 577#L1194-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 176#L1199-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 824#L1204-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 302#L1209-3true assume !(0 == ~T8_E~0); 14#L1214-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 629#L1219-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 412#L1224-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1693#L1229-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 425#L1234-3true assume 0 == ~E_1~0;~E_1~0 := 1; 100#L1239-3true assume 0 == ~E_2~0;~E_2~0 := 1; 336#L1244-3true assume 0 == ~E_3~0;~E_3~0 := 1; 662#L1249-3true assume !(0 == ~E_4~0); 1446#L1254-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1237#L1259-3true assume 0 == ~E_6~0;~E_6~0 := 1; 765#L1264-3true assume 0 == ~E_7~0;~E_7~0 := 1; 103#L1269-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1504#L1274-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1321#L1279-3true assume 0 == ~E_10~0;~E_10~0 := 1; 411#L1284-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1379#L1289-3true assume !(0 == ~E_12~0); 403#L1294-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 218#L566-39true assume !(1 == ~m_pc~0); 654#L566-41true is_master_triggered_~__retres1~0#1 := 0; 606#L577-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 396#L578-13true activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1251#L1455-39true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 836#L1455-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1298#L585-39true assume 1 == ~t1_pc~0; 968#L586-13true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 333#L596-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 260#L597-13true activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1225#L1463-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 871#L1463-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 593#L604-39true assume !(1 == ~t2_pc~0); 1222#L604-41true is_transmit2_triggered_~__retres1~2#1 := 0; 339#L615-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1134#L616-13true activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 631#L1471-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1007#L1471-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326#L623-39true assume !(1 == ~t3_pc~0); 650#L623-41true is_transmit3_triggered_~__retres1~3#1 := 0; 853#L634-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1486#L635-13true activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 245#L1479-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 803#L1479-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1304#L642-39true assume 1 == ~t4_pc~0; 448#L643-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 753#L653-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 179#L654-13true activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1040#L1487-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1184#L1487-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 204#L661-39true assume !(1 == ~t5_pc~0); 25#L661-41true is_transmit5_triggered_~__retres1~5#1 := 0; 1627#L672-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 961#L673-13true activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1151#L1495-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 855#L1495-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1176#L680-39true assume !(1 == ~t6_pc~0); 977#L680-41true is_transmit6_triggered_~__retres1~6#1 := 0; 1145#L691-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 785#L692-13true activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 289#L1503-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1491#L1503-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1248#L699-39true assume 1 == ~t7_pc~0; 579#L700-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 381#L710-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 982#L711-13true activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1269#L1511-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1143#L1511-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1141#L718-39true assume 1 == ~t8_pc~0; 511#L719-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1388#L729-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 461#L730-13true activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1153#L1519-39true assume !(0 != activate_threads_~tmp___7~0#1); 707#L1519-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 683#L737-39true assume 1 == ~t9_pc~0; 276#L738-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 452#L748-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1323#L749-13true activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1449#L1527-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1099#L1527-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1027#L756-39true assume 1 == ~t10_pc~0; 1376#L757-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1515#L767-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 352#L768-13true activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 434#L1535-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 565#L1535-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77#L775-39true assume !(1 == ~t11_pc~0); 460#L775-41true is_transmit11_triggered_~__retres1~11#1 := 0; 431#L786-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1694#L787-13true activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1546#L1543-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 759#L1543-41true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 467#L794-39true assume 1 == ~t12_pc~0; 277#L795-13true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 914#L805-13true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1347#L806-13true activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 810#L1551-39true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49#L1551-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1307#L1307-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1199#L1307-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1610#L1312-3true assume !(1 == ~T2_E~0); 1604#L1317-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 828#L1322-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1672#L1327-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 112#L1332-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 99#L1337-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 533#L1342-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 957#L1347-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 632#L1352-3true assume !(1 == ~T10_E~0); 1112#L1357-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1683#L1362-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1541#L1367-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1508#L1372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 20#L1377-3true assume 1 == ~E_3~0;~E_3~0 := 2; 428#L1382-3true assume 1 == ~E_4~0;~E_4~0 := 2; 343#L1387-3true assume 1 == ~E_5~0;~E_5~0 := 2; 927#L1392-3true assume !(1 == ~E_6~0); 1595#L1397-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1373#L1402-3true assume 1 == ~E_8~0;~E_8~0 := 2; 605#L1407-3true assume 1 == ~E_9~0;~E_9~0 := 2; 156#L1412-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1149#L1417-3true assume 1 == ~E_11~0;~E_11~0 := 2; 547#L1422-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1105#L1427-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 161#L894-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1651#L961-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 739#L962-1true start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 609#L1787true assume !(0 == start_simulation_~tmp~3#1); 1433#L1787-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1215#L894-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1010#L961-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 647#L962-2true stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 1318#L1742true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 330#L1749true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 331#L1750true start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 1590#L1800true assume !(0 != start_simulation_~tmp___0~1#1); 96#L1768-2true [2022-02-21 04:24:22,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:22,362 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 1 times [2022-02-21 04:24:22,369 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:22,369 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933916517] [2022-02-21 04:24:22,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:22,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:22,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:22,534 INFO L290 TraceCheckUtils]: 0: Hoare triple {1699#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {1699#true} is VALID [2022-02-21 04:24:22,535 INFO L290 TraceCheckUtils]: 1: Hoare triple {1699#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {1701#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:22,536 INFO L290 TraceCheckUtils]: 2: Hoare triple {1701#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1701#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:22,536 INFO L290 TraceCheckUtils]: 3: Hoare triple {1701#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1701#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:22,536 INFO L290 TraceCheckUtils]: 4: Hoare triple {1701#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,537 INFO L290 TraceCheckUtils]: 5: Hoare triple {1700#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1700#false} is VALID [2022-02-21 04:24:22,537 INFO L290 TraceCheckUtils]: 6: Hoare triple {1700#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,537 INFO L290 TraceCheckUtils]: 7: Hoare triple {1700#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,537 INFO L290 TraceCheckUtils]: 8: Hoare triple {1700#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,537 INFO L290 TraceCheckUtils]: 9: Hoare triple {1700#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,538 INFO L290 TraceCheckUtils]: 10: Hoare triple {1700#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,538 INFO L290 TraceCheckUtils]: 11: Hoare triple {1700#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,538 INFO L290 TraceCheckUtils]: 12: Hoare triple {1700#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,538 INFO L290 TraceCheckUtils]: 13: Hoare triple {1700#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {1700#false} is VALID [2022-02-21 04:24:22,539 INFO L290 TraceCheckUtils]: 14: Hoare triple {1700#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,539 INFO L290 TraceCheckUtils]: 15: Hoare triple {1700#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,539 INFO L290 TraceCheckUtils]: 16: Hoare triple {1700#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,539 INFO L290 TraceCheckUtils]: 17: Hoare triple {1700#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1700#false} is VALID [2022-02-21 04:24:22,539 INFO L290 TraceCheckUtils]: 18: Hoare triple {1700#false} assume !(0 == ~M_E~0); {1700#false} is VALID [2022-02-21 04:24:22,540 INFO L290 TraceCheckUtils]: 19: Hoare triple {1700#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1700#false} is VALID [2022-02-21 04:24:22,540 INFO L290 TraceCheckUtils]: 20: Hoare triple {1700#false} assume !(0 == ~T2_E~0); {1700#false} is VALID [2022-02-21 04:24:22,540 INFO L290 TraceCheckUtils]: 21: Hoare triple {1700#false} assume !(0 == ~T3_E~0); {1700#false} is VALID [2022-02-21 04:24:22,540 INFO L290 TraceCheckUtils]: 22: Hoare triple {1700#false} assume !(0 == ~T4_E~0); {1700#false} is VALID [2022-02-21 04:24:22,540 INFO L290 TraceCheckUtils]: 23: Hoare triple {1700#false} assume !(0 == ~T5_E~0); {1700#false} is VALID [2022-02-21 04:24:22,541 INFO L290 TraceCheckUtils]: 24: Hoare triple {1700#false} assume !(0 == ~T6_E~0); {1700#false} is VALID [2022-02-21 04:24:22,541 INFO L290 TraceCheckUtils]: 25: Hoare triple {1700#false} assume !(0 == ~T7_E~0); {1700#false} is VALID [2022-02-21 04:24:22,541 INFO L290 TraceCheckUtils]: 26: Hoare triple {1700#false} assume !(0 == ~T8_E~0); {1700#false} is VALID [2022-02-21 04:24:22,541 INFO L290 TraceCheckUtils]: 27: Hoare triple {1700#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1700#false} is VALID [2022-02-21 04:24:22,541 INFO L290 TraceCheckUtils]: 28: Hoare triple {1700#false} assume !(0 == ~T10_E~0); {1700#false} is VALID [2022-02-21 04:24:22,542 INFO L290 TraceCheckUtils]: 29: Hoare triple {1700#false} assume !(0 == ~T11_E~0); {1700#false} is VALID [2022-02-21 04:24:22,542 INFO L290 TraceCheckUtils]: 30: Hoare triple {1700#false} assume !(0 == ~T12_E~0); {1700#false} is VALID [2022-02-21 04:24:22,542 INFO L290 TraceCheckUtils]: 31: Hoare triple {1700#false} assume !(0 == ~E_1~0); {1700#false} is VALID [2022-02-21 04:24:22,542 INFO L290 TraceCheckUtils]: 32: Hoare triple {1700#false} assume !(0 == ~E_2~0); {1700#false} is VALID [2022-02-21 04:24:22,542 INFO L290 TraceCheckUtils]: 33: Hoare triple {1700#false} assume !(0 == ~E_3~0); {1700#false} is VALID [2022-02-21 04:24:22,543 INFO L290 TraceCheckUtils]: 34: Hoare triple {1700#false} assume !(0 == ~E_4~0); {1700#false} is VALID [2022-02-21 04:24:22,543 INFO L290 TraceCheckUtils]: 35: Hoare triple {1700#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1700#false} is VALID [2022-02-21 04:24:22,543 INFO L290 TraceCheckUtils]: 36: Hoare triple {1700#false} assume !(0 == ~E_6~0); {1700#false} is VALID [2022-02-21 04:24:22,543 INFO L290 TraceCheckUtils]: 37: Hoare triple {1700#false} assume !(0 == ~E_7~0); {1700#false} is VALID [2022-02-21 04:24:22,543 INFO L290 TraceCheckUtils]: 38: Hoare triple {1700#false} assume !(0 == ~E_8~0); {1700#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 39: Hoare triple {1700#false} assume !(0 == ~E_9~0); {1700#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 40: Hoare triple {1700#false} assume !(0 == ~E_10~0); {1700#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 41: Hoare triple {1700#false} assume !(0 == ~E_11~0); {1700#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 42: Hoare triple {1700#false} assume !(0 == ~E_12~0); {1700#false} is VALID [2022-02-21 04:24:22,544 INFO L290 TraceCheckUtils]: 43: Hoare triple {1700#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1700#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 44: Hoare triple {1700#false} assume 1 == ~m_pc~0; {1700#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 45: Hoare triple {1700#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {1700#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 46: Hoare triple {1700#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1700#false} is VALID [2022-02-21 04:24:22,545 INFO L290 TraceCheckUtils]: 47: Hoare triple {1700#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1700#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 48: Hoare triple {1700#false} assume !(0 != activate_threads_~tmp~1#1); {1700#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 49: Hoare triple {1700#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1700#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 50: Hoare triple {1700#false} assume 1 == ~t1_pc~0; {1700#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 51: Hoare triple {1700#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1700#false} is VALID [2022-02-21 04:24:22,546 INFO L290 TraceCheckUtils]: 52: Hoare triple {1700#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1700#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 53: Hoare triple {1700#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1700#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 54: Hoare triple {1700#false} assume !(0 != activate_threads_~tmp___0~0#1); {1700#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 55: Hoare triple {1700#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1700#false} is VALID [2022-02-21 04:24:22,547 INFO L290 TraceCheckUtils]: 56: Hoare triple {1700#false} assume !(1 == ~t2_pc~0); {1700#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 57: Hoare triple {1700#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1700#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 58: Hoare triple {1700#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1700#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 59: Hoare triple {1700#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1700#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 60: Hoare triple {1700#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1700#false} is VALID [2022-02-21 04:24:22,548 INFO L290 TraceCheckUtils]: 61: Hoare triple {1700#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1700#false} is VALID [2022-02-21 04:24:22,549 INFO L290 TraceCheckUtils]: 62: Hoare triple {1700#false} assume 1 == ~t3_pc~0; {1700#false} is VALID [2022-02-21 04:24:22,549 INFO L290 TraceCheckUtils]: 63: Hoare triple {1700#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1700#false} is VALID [2022-02-21 04:24:22,549 INFO L290 TraceCheckUtils]: 64: Hoare triple {1700#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1700#false} is VALID [2022-02-21 04:24:22,549 INFO L290 TraceCheckUtils]: 65: Hoare triple {1700#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1700#false} is VALID [2022-02-21 04:24:22,549 INFO L290 TraceCheckUtils]: 66: Hoare triple {1700#false} assume !(0 != activate_threads_~tmp___2~0#1); {1700#false} is VALID [2022-02-21 04:24:22,550 INFO L290 TraceCheckUtils]: 67: Hoare triple {1700#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1700#false} is VALID [2022-02-21 04:24:22,550 INFO L290 TraceCheckUtils]: 68: Hoare triple {1700#false} assume !(1 == ~t4_pc~0); {1700#false} is VALID [2022-02-21 04:24:22,550 INFO L290 TraceCheckUtils]: 69: Hoare triple {1700#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1700#false} is VALID [2022-02-21 04:24:22,550 INFO L290 TraceCheckUtils]: 70: Hoare triple {1700#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1700#false} is VALID [2022-02-21 04:24:22,551 INFO L290 TraceCheckUtils]: 71: Hoare triple {1700#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1700#false} is VALID [2022-02-21 04:24:22,551 INFO L290 TraceCheckUtils]: 72: Hoare triple {1700#false} assume !(0 != activate_threads_~tmp___3~0#1); {1700#false} is VALID [2022-02-21 04:24:22,551 INFO L290 TraceCheckUtils]: 73: Hoare triple {1700#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1700#false} is VALID [2022-02-21 04:24:22,551 INFO L290 TraceCheckUtils]: 74: Hoare triple {1700#false} assume 1 == ~t5_pc~0; {1700#false} is VALID [2022-02-21 04:24:22,551 INFO L290 TraceCheckUtils]: 75: Hoare triple {1700#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1700#false} is VALID [2022-02-21 04:24:22,552 INFO L290 TraceCheckUtils]: 76: Hoare triple {1700#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1700#false} is VALID [2022-02-21 04:24:22,552 INFO L290 TraceCheckUtils]: 77: Hoare triple {1700#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1700#false} is VALID [2022-02-21 04:24:22,552 INFO L290 TraceCheckUtils]: 78: Hoare triple {1700#false} assume !(0 != activate_threads_~tmp___4~0#1); {1700#false} is VALID [2022-02-21 04:24:22,552 INFO L290 TraceCheckUtils]: 79: Hoare triple {1700#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1700#false} is VALID [2022-02-21 04:24:22,552 INFO L290 TraceCheckUtils]: 80: Hoare triple {1700#false} assume !(1 == ~t6_pc~0); {1700#false} is VALID [2022-02-21 04:24:22,553 INFO L290 TraceCheckUtils]: 81: Hoare triple {1700#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1700#false} is VALID [2022-02-21 04:24:22,553 INFO L290 TraceCheckUtils]: 82: Hoare triple {1700#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1700#false} is VALID [2022-02-21 04:24:22,553 INFO L290 TraceCheckUtils]: 83: Hoare triple {1700#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1700#false} is VALID [2022-02-21 04:24:22,553 INFO L290 TraceCheckUtils]: 84: Hoare triple {1700#false} assume !(0 != activate_threads_~tmp___5~0#1); {1700#false} is VALID [2022-02-21 04:24:22,553 INFO L290 TraceCheckUtils]: 85: Hoare triple {1700#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1700#false} is VALID [2022-02-21 04:24:22,554 INFO L290 TraceCheckUtils]: 86: Hoare triple {1700#false} assume 1 == ~t7_pc~0; {1700#false} is VALID [2022-02-21 04:24:22,554 INFO L290 TraceCheckUtils]: 87: Hoare triple {1700#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1700#false} is VALID [2022-02-21 04:24:22,554 INFO L290 TraceCheckUtils]: 88: Hoare triple {1700#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1700#false} is VALID [2022-02-21 04:24:22,554 INFO L290 TraceCheckUtils]: 89: Hoare triple {1700#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1700#false} is VALID [2022-02-21 04:24:22,555 INFO L290 TraceCheckUtils]: 90: Hoare triple {1700#false} assume !(0 != activate_threads_~tmp___6~0#1); {1700#false} is VALID [2022-02-21 04:24:22,555 INFO L290 TraceCheckUtils]: 91: Hoare triple {1700#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1700#false} is VALID [2022-02-21 04:24:22,555 INFO L290 TraceCheckUtils]: 92: Hoare triple {1700#false} assume !(1 == ~t8_pc~0); {1700#false} is VALID [2022-02-21 04:24:22,555 INFO L290 TraceCheckUtils]: 93: Hoare triple {1700#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1700#false} is VALID [2022-02-21 04:24:22,555 INFO L290 TraceCheckUtils]: 94: Hoare triple {1700#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1700#false} is VALID [2022-02-21 04:24:22,556 INFO L290 TraceCheckUtils]: 95: Hoare triple {1700#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1700#false} is VALID [2022-02-21 04:24:22,556 INFO L290 TraceCheckUtils]: 96: Hoare triple {1700#false} assume !(0 != activate_threads_~tmp___7~0#1); {1700#false} is VALID [2022-02-21 04:24:22,556 INFO L290 TraceCheckUtils]: 97: Hoare triple {1700#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1700#false} is VALID [2022-02-21 04:24:22,556 INFO L290 TraceCheckUtils]: 98: Hoare triple {1700#false} assume 1 == ~t9_pc~0; {1700#false} is VALID [2022-02-21 04:24:22,556 INFO L290 TraceCheckUtils]: 99: Hoare triple {1700#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1700#false} is VALID [2022-02-21 04:24:22,557 INFO L290 TraceCheckUtils]: 100: Hoare triple {1700#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1700#false} is VALID [2022-02-21 04:24:22,557 INFO L290 TraceCheckUtils]: 101: Hoare triple {1700#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1700#false} is VALID [2022-02-21 04:24:22,557 INFO L290 TraceCheckUtils]: 102: Hoare triple {1700#false} assume !(0 != activate_threads_~tmp___8~0#1); {1700#false} is VALID [2022-02-21 04:24:22,557 INFO L290 TraceCheckUtils]: 103: Hoare triple {1700#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1700#false} is VALID [2022-02-21 04:24:22,557 INFO L290 TraceCheckUtils]: 104: Hoare triple {1700#false} assume 1 == ~t10_pc~0; {1700#false} is VALID [2022-02-21 04:24:22,558 INFO L290 TraceCheckUtils]: 105: Hoare triple {1700#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {1700#false} is VALID [2022-02-21 04:24:22,558 INFO L290 TraceCheckUtils]: 106: Hoare triple {1700#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1700#false} is VALID [2022-02-21 04:24:22,558 INFO L290 TraceCheckUtils]: 107: Hoare triple {1700#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1700#false} is VALID [2022-02-21 04:24:22,558 INFO L290 TraceCheckUtils]: 108: Hoare triple {1700#false} assume !(0 != activate_threads_~tmp___9~0#1); {1700#false} is VALID [2022-02-21 04:24:22,558 INFO L290 TraceCheckUtils]: 109: Hoare triple {1700#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1700#false} is VALID [2022-02-21 04:24:22,559 INFO L290 TraceCheckUtils]: 110: Hoare triple {1700#false} assume !(1 == ~t11_pc~0); {1700#false} is VALID [2022-02-21 04:24:22,559 INFO L290 TraceCheckUtils]: 111: Hoare triple {1700#false} is_transmit11_triggered_~__retres1~11#1 := 0; {1700#false} is VALID [2022-02-21 04:24:22,559 INFO L290 TraceCheckUtils]: 112: Hoare triple {1700#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1700#false} is VALID [2022-02-21 04:24:22,559 INFO L290 TraceCheckUtils]: 113: Hoare triple {1700#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1700#false} is VALID [2022-02-21 04:24:22,559 INFO L290 TraceCheckUtils]: 114: Hoare triple {1700#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {1700#false} is VALID [2022-02-21 04:24:22,560 INFO L290 TraceCheckUtils]: 115: Hoare triple {1700#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {1700#false} is VALID [2022-02-21 04:24:22,560 INFO L290 TraceCheckUtils]: 116: Hoare triple {1700#false} assume 1 == ~t12_pc~0; {1700#false} is VALID [2022-02-21 04:24:22,560 INFO L290 TraceCheckUtils]: 117: Hoare triple {1700#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {1700#false} is VALID [2022-02-21 04:24:22,560 INFO L290 TraceCheckUtils]: 118: Hoare triple {1700#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {1700#false} is VALID [2022-02-21 04:24:22,560 INFO L290 TraceCheckUtils]: 119: Hoare triple {1700#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {1700#false} is VALID [2022-02-21 04:24:22,561 INFO L290 TraceCheckUtils]: 120: Hoare triple {1700#false} assume !(0 != activate_threads_~tmp___11~0#1); {1700#false} is VALID [2022-02-21 04:24:22,561 INFO L290 TraceCheckUtils]: 121: Hoare triple {1700#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1700#false} is VALID [2022-02-21 04:24:22,561 INFO L290 TraceCheckUtils]: 122: Hoare triple {1700#false} assume !(1 == ~M_E~0); {1700#false} is VALID [2022-02-21 04:24:22,561 INFO L290 TraceCheckUtils]: 123: Hoare triple {1700#false} assume !(1 == ~T1_E~0); {1700#false} is VALID [2022-02-21 04:24:22,561 INFO L290 TraceCheckUtils]: 124: Hoare triple {1700#false} assume !(1 == ~T2_E~0); {1700#false} is VALID [2022-02-21 04:24:22,562 INFO L290 TraceCheckUtils]: 125: Hoare triple {1700#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,562 INFO L290 TraceCheckUtils]: 126: Hoare triple {1700#false} assume !(1 == ~T4_E~0); {1700#false} is VALID [2022-02-21 04:24:22,562 INFO L290 TraceCheckUtils]: 127: Hoare triple {1700#false} assume !(1 == ~T5_E~0); {1700#false} is VALID [2022-02-21 04:24:22,562 INFO L290 TraceCheckUtils]: 128: Hoare triple {1700#false} assume !(1 == ~T6_E~0); {1700#false} is VALID [2022-02-21 04:24:22,562 INFO L290 TraceCheckUtils]: 129: Hoare triple {1700#false} assume !(1 == ~T7_E~0); {1700#false} is VALID [2022-02-21 04:24:22,563 INFO L290 TraceCheckUtils]: 130: Hoare triple {1700#false} assume !(1 == ~T8_E~0); {1700#false} is VALID [2022-02-21 04:24:22,563 INFO L290 TraceCheckUtils]: 131: Hoare triple {1700#false} assume !(1 == ~T9_E~0); {1700#false} is VALID [2022-02-21 04:24:22,563 INFO L290 TraceCheckUtils]: 132: Hoare triple {1700#false} assume !(1 == ~T10_E~0); {1700#false} is VALID [2022-02-21 04:24:22,563 INFO L290 TraceCheckUtils]: 133: Hoare triple {1700#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,563 INFO L290 TraceCheckUtils]: 134: Hoare triple {1700#false} assume !(1 == ~T12_E~0); {1700#false} is VALID [2022-02-21 04:24:22,564 INFO L290 TraceCheckUtils]: 135: Hoare triple {1700#false} assume !(1 == ~E_1~0); {1700#false} is VALID [2022-02-21 04:24:22,564 INFO L290 TraceCheckUtils]: 136: Hoare triple {1700#false} assume !(1 == ~E_2~0); {1700#false} is VALID [2022-02-21 04:24:22,564 INFO L290 TraceCheckUtils]: 137: Hoare triple {1700#false} assume !(1 == ~E_3~0); {1700#false} is VALID [2022-02-21 04:24:22,564 INFO L290 TraceCheckUtils]: 138: Hoare triple {1700#false} assume !(1 == ~E_4~0); {1700#false} is VALID [2022-02-21 04:24:22,564 INFO L290 TraceCheckUtils]: 139: Hoare triple {1700#false} assume !(1 == ~E_5~0); {1700#false} is VALID [2022-02-21 04:24:22,564 INFO L290 TraceCheckUtils]: 140: Hoare triple {1700#false} assume !(1 == ~E_6~0); {1700#false} is VALID [2022-02-21 04:24:22,565 INFO L290 TraceCheckUtils]: 141: Hoare triple {1700#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1700#false} is VALID [2022-02-21 04:24:22,565 INFO L290 TraceCheckUtils]: 142: Hoare triple {1700#false} assume !(1 == ~E_8~0); {1700#false} is VALID [2022-02-21 04:24:22,565 INFO L290 TraceCheckUtils]: 143: Hoare triple {1700#false} assume !(1 == ~E_9~0); {1700#false} is VALID [2022-02-21 04:24:22,565 INFO L290 TraceCheckUtils]: 144: Hoare triple {1700#false} assume !(1 == ~E_10~0); {1700#false} is VALID [2022-02-21 04:24:22,565 INFO L290 TraceCheckUtils]: 145: Hoare triple {1700#false} assume !(1 == ~E_11~0); {1700#false} is VALID [2022-02-21 04:24:22,566 INFO L290 TraceCheckUtils]: 146: Hoare triple {1700#false} assume !(1 == ~E_12~0); {1700#false} is VALID [2022-02-21 04:24:22,566 INFO L290 TraceCheckUtils]: 147: Hoare triple {1700#false} assume { :end_inline_reset_delta_events } true; {1700#false} is VALID [2022-02-21 04:24:22,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:22,568 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:22,568 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [933916517] [2022-02-21 04:24:22,569 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [933916517] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:22,569 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:22,569 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:22,570 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1129045414] [2022-02-21 04:24:22,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:22,574 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:22,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:22,575 INFO L85 PathProgramCache]: Analyzing trace with hash -1819192778, now seen corresponding path program 1 times [2022-02-21 04:24:22,575 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:22,575 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308638165] [2022-02-21 04:24:22,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:22,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:22,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:22,611 INFO L290 TraceCheckUtils]: 0: Hoare triple {1702#true} assume !false; {1702#true} is VALID [2022-02-21 04:24:22,611 INFO L290 TraceCheckUtils]: 1: Hoare triple {1702#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1702#true} is VALID [2022-02-21 04:24:22,611 INFO L290 TraceCheckUtils]: 2: Hoare triple {1702#true} assume false; {1703#false} is VALID [2022-02-21 04:24:22,612 INFO L290 TraceCheckUtils]: 3: Hoare triple {1703#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1703#false} is VALID [2022-02-21 04:24:22,612 INFO L290 TraceCheckUtils]: 4: Hoare triple {1703#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1703#false} is VALID [2022-02-21 04:24:22,612 INFO L290 TraceCheckUtils]: 5: Hoare triple {1703#false} assume !(0 == ~M_E~0); {1703#false} is VALID [2022-02-21 04:24:22,612 INFO L290 TraceCheckUtils]: 6: Hoare triple {1703#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,612 INFO L290 TraceCheckUtils]: 7: Hoare triple {1703#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 8: Hoare triple {1703#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 9: Hoare triple {1703#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 10: Hoare triple {1703#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 11: Hoare triple {1703#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 12: Hoare triple {1703#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,613 INFO L290 TraceCheckUtils]: 13: Hoare triple {1703#false} assume !(0 == ~T8_E~0); {1703#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 14: Hoare triple {1703#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 15: Hoare triple {1703#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 16: Hoare triple {1703#false} assume 0 == ~T11_E~0;~T11_E~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 17: Hoare triple {1703#false} assume 0 == ~T12_E~0;~T12_E~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,614 INFO L290 TraceCheckUtils]: 18: Hoare triple {1703#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 19: Hoare triple {1703#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 20: Hoare triple {1703#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 21: Hoare triple {1703#false} assume !(0 == ~E_4~0); {1703#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 22: Hoare triple {1703#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,615 INFO L290 TraceCheckUtils]: 23: Hoare triple {1703#false} assume 0 == ~E_6~0;~E_6~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,616 INFO L290 TraceCheckUtils]: 24: Hoare triple {1703#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,616 INFO L290 TraceCheckUtils]: 25: Hoare triple {1703#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,616 INFO L290 TraceCheckUtils]: 26: Hoare triple {1703#false} assume 0 == ~E_9~0;~E_9~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,616 INFO L290 TraceCheckUtils]: 27: Hoare triple {1703#false} assume 0 == ~E_10~0;~E_10~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,616 INFO L290 TraceCheckUtils]: 28: Hoare triple {1703#false} assume 0 == ~E_11~0;~E_11~0 := 1; {1703#false} is VALID [2022-02-21 04:24:22,617 INFO L290 TraceCheckUtils]: 29: Hoare triple {1703#false} assume !(0 == ~E_12~0); {1703#false} is VALID [2022-02-21 04:24:22,617 INFO L290 TraceCheckUtils]: 30: Hoare triple {1703#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1703#false} is VALID [2022-02-21 04:24:22,617 INFO L290 TraceCheckUtils]: 31: Hoare triple {1703#false} assume !(1 == ~m_pc~0); {1703#false} is VALID [2022-02-21 04:24:22,617 INFO L290 TraceCheckUtils]: 32: Hoare triple {1703#false} is_master_triggered_~__retres1~0#1 := 0; {1703#false} is VALID [2022-02-21 04:24:22,617 INFO L290 TraceCheckUtils]: 33: Hoare triple {1703#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1703#false} is VALID [2022-02-21 04:24:22,618 INFO L290 TraceCheckUtils]: 34: Hoare triple {1703#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {1703#false} is VALID [2022-02-21 04:24:22,618 INFO L290 TraceCheckUtils]: 35: Hoare triple {1703#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,618 INFO L290 TraceCheckUtils]: 36: Hoare triple {1703#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1703#false} is VALID [2022-02-21 04:24:22,618 INFO L290 TraceCheckUtils]: 37: Hoare triple {1703#false} assume 1 == ~t1_pc~0; {1703#false} is VALID [2022-02-21 04:24:22,618 INFO L290 TraceCheckUtils]: 38: Hoare triple {1703#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1703#false} is VALID [2022-02-21 04:24:22,619 INFO L290 TraceCheckUtils]: 39: Hoare triple {1703#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1703#false} is VALID [2022-02-21 04:24:22,619 INFO L290 TraceCheckUtils]: 40: Hoare triple {1703#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1703#false} is VALID [2022-02-21 04:24:22,619 INFO L290 TraceCheckUtils]: 41: Hoare triple {1703#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,619 INFO L290 TraceCheckUtils]: 42: Hoare triple {1703#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1703#false} is VALID [2022-02-21 04:24:22,619 INFO L290 TraceCheckUtils]: 43: Hoare triple {1703#false} assume !(1 == ~t2_pc~0); {1703#false} is VALID [2022-02-21 04:24:22,620 INFO L290 TraceCheckUtils]: 44: Hoare triple {1703#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1703#false} is VALID [2022-02-21 04:24:22,620 INFO L290 TraceCheckUtils]: 45: Hoare triple {1703#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1703#false} is VALID [2022-02-21 04:24:22,629 INFO L290 TraceCheckUtils]: 46: Hoare triple {1703#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1703#false} is VALID [2022-02-21 04:24:22,632 INFO L290 TraceCheckUtils]: 47: Hoare triple {1703#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,633 INFO L290 TraceCheckUtils]: 48: Hoare triple {1703#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1703#false} is VALID [2022-02-21 04:24:22,633 INFO L290 TraceCheckUtils]: 49: Hoare triple {1703#false} assume !(1 == ~t3_pc~0); {1703#false} is VALID [2022-02-21 04:24:22,633 INFO L290 TraceCheckUtils]: 50: Hoare triple {1703#false} is_transmit3_triggered_~__retres1~3#1 := 0; {1703#false} is VALID [2022-02-21 04:24:22,633 INFO L290 TraceCheckUtils]: 51: Hoare triple {1703#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1703#false} is VALID [2022-02-21 04:24:22,633 INFO L290 TraceCheckUtils]: 52: Hoare triple {1703#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1703#false} is VALID [2022-02-21 04:24:22,633 INFO L290 TraceCheckUtils]: 53: Hoare triple {1703#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,634 INFO L290 TraceCheckUtils]: 54: Hoare triple {1703#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1703#false} is VALID [2022-02-21 04:24:22,634 INFO L290 TraceCheckUtils]: 55: Hoare triple {1703#false} assume 1 == ~t4_pc~0; {1703#false} is VALID [2022-02-21 04:24:22,634 INFO L290 TraceCheckUtils]: 56: Hoare triple {1703#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {1703#false} is VALID [2022-02-21 04:24:22,634 INFO L290 TraceCheckUtils]: 57: Hoare triple {1703#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1703#false} is VALID [2022-02-21 04:24:22,634 INFO L290 TraceCheckUtils]: 58: Hoare triple {1703#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1703#false} is VALID [2022-02-21 04:24:22,634 INFO L290 TraceCheckUtils]: 59: Hoare triple {1703#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,635 INFO L290 TraceCheckUtils]: 60: Hoare triple {1703#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1703#false} is VALID [2022-02-21 04:24:22,635 INFO L290 TraceCheckUtils]: 61: Hoare triple {1703#false} assume !(1 == ~t5_pc~0); {1703#false} is VALID [2022-02-21 04:24:22,635 INFO L290 TraceCheckUtils]: 62: Hoare triple {1703#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1703#false} is VALID [2022-02-21 04:24:22,635 INFO L290 TraceCheckUtils]: 63: Hoare triple {1703#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1703#false} is VALID [2022-02-21 04:24:22,635 INFO L290 TraceCheckUtils]: 64: Hoare triple {1703#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1703#false} is VALID [2022-02-21 04:24:22,635 INFO L290 TraceCheckUtils]: 65: Hoare triple {1703#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,639 INFO L290 TraceCheckUtils]: 66: Hoare triple {1703#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1703#false} is VALID [2022-02-21 04:24:22,640 INFO L290 TraceCheckUtils]: 67: Hoare triple {1703#false} assume !(1 == ~t6_pc~0); {1703#false} is VALID [2022-02-21 04:24:22,640 INFO L290 TraceCheckUtils]: 68: Hoare triple {1703#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1703#false} is VALID [2022-02-21 04:24:22,640 INFO L290 TraceCheckUtils]: 69: Hoare triple {1703#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1703#false} is VALID [2022-02-21 04:24:22,640 INFO L290 TraceCheckUtils]: 70: Hoare triple {1703#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1703#false} is VALID [2022-02-21 04:24:22,640 INFO L290 TraceCheckUtils]: 71: Hoare triple {1703#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,641 INFO L290 TraceCheckUtils]: 72: Hoare triple {1703#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1703#false} is VALID [2022-02-21 04:24:22,641 INFO L290 TraceCheckUtils]: 73: Hoare triple {1703#false} assume 1 == ~t7_pc~0; {1703#false} is VALID [2022-02-21 04:24:22,641 INFO L290 TraceCheckUtils]: 74: Hoare triple {1703#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1703#false} is VALID [2022-02-21 04:24:22,641 INFO L290 TraceCheckUtils]: 75: Hoare triple {1703#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1703#false} is VALID [2022-02-21 04:24:22,641 INFO L290 TraceCheckUtils]: 76: Hoare triple {1703#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1703#false} is VALID [2022-02-21 04:24:22,642 INFO L290 TraceCheckUtils]: 77: Hoare triple {1703#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,642 INFO L290 TraceCheckUtils]: 78: Hoare triple {1703#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1703#false} is VALID [2022-02-21 04:24:22,642 INFO L290 TraceCheckUtils]: 79: Hoare triple {1703#false} assume 1 == ~t8_pc~0; {1703#false} is VALID [2022-02-21 04:24:22,642 INFO L290 TraceCheckUtils]: 80: Hoare triple {1703#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1703#false} is VALID [2022-02-21 04:24:22,642 INFO L290 TraceCheckUtils]: 81: Hoare triple {1703#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1703#false} is VALID [2022-02-21 04:24:22,643 INFO L290 TraceCheckUtils]: 82: Hoare triple {1703#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1703#false} is VALID [2022-02-21 04:24:22,643 INFO L290 TraceCheckUtils]: 83: Hoare triple {1703#false} assume !(0 != activate_threads_~tmp___7~0#1); {1703#false} is VALID [2022-02-21 04:24:22,643 INFO L290 TraceCheckUtils]: 84: Hoare triple {1703#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1703#false} is VALID [2022-02-21 04:24:22,644 INFO L290 TraceCheckUtils]: 85: Hoare triple {1703#false} assume 1 == ~t9_pc~0; {1703#false} is VALID [2022-02-21 04:24:22,644 INFO L290 TraceCheckUtils]: 86: Hoare triple {1703#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1703#false} is VALID [2022-02-21 04:24:22,644 INFO L290 TraceCheckUtils]: 87: Hoare triple {1703#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1703#false} is VALID [2022-02-21 04:24:22,644 INFO L290 TraceCheckUtils]: 88: Hoare triple {1703#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1703#false} is VALID [2022-02-21 04:24:22,644 INFO L290 TraceCheckUtils]: 89: Hoare triple {1703#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,645 INFO L290 TraceCheckUtils]: 90: Hoare triple {1703#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1703#false} is VALID [2022-02-21 04:24:22,645 INFO L290 TraceCheckUtils]: 91: Hoare triple {1703#false} assume 1 == ~t10_pc~0; {1703#false} is VALID [2022-02-21 04:24:22,646 INFO L290 TraceCheckUtils]: 92: Hoare triple {1703#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {1703#false} is VALID [2022-02-21 04:24:22,646 INFO L290 TraceCheckUtils]: 93: Hoare triple {1703#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1703#false} is VALID [2022-02-21 04:24:22,646 INFO L290 TraceCheckUtils]: 94: Hoare triple {1703#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1703#false} is VALID [2022-02-21 04:24:22,647 INFO L290 TraceCheckUtils]: 95: Hoare triple {1703#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,647 INFO L290 TraceCheckUtils]: 96: Hoare triple {1703#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1703#false} is VALID [2022-02-21 04:24:22,647 INFO L290 TraceCheckUtils]: 97: Hoare triple {1703#false} assume !(1 == ~t11_pc~0); {1703#false} is VALID [2022-02-21 04:24:22,647 INFO L290 TraceCheckUtils]: 98: Hoare triple {1703#false} is_transmit11_triggered_~__retres1~11#1 := 0; {1703#false} is VALID [2022-02-21 04:24:22,647 INFO L290 TraceCheckUtils]: 99: Hoare triple {1703#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1703#false} is VALID [2022-02-21 04:24:22,648 INFO L290 TraceCheckUtils]: 100: Hoare triple {1703#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1703#false} is VALID [2022-02-21 04:24:22,648 INFO L290 TraceCheckUtils]: 101: Hoare triple {1703#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,648 INFO L290 TraceCheckUtils]: 102: Hoare triple {1703#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {1703#false} is VALID [2022-02-21 04:24:22,648 INFO L290 TraceCheckUtils]: 103: Hoare triple {1703#false} assume 1 == ~t12_pc~0; {1703#false} is VALID [2022-02-21 04:24:22,648 INFO L290 TraceCheckUtils]: 104: Hoare triple {1703#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {1703#false} is VALID [2022-02-21 04:24:22,649 INFO L290 TraceCheckUtils]: 105: Hoare triple {1703#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {1703#false} is VALID [2022-02-21 04:24:22,649 INFO L290 TraceCheckUtils]: 106: Hoare triple {1703#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {1703#false} is VALID [2022-02-21 04:24:22,649 INFO L290 TraceCheckUtils]: 107: Hoare triple {1703#false} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {1703#false} is VALID [2022-02-21 04:24:22,649 INFO L290 TraceCheckUtils]: 108: Hoare triple {1703#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1703#false} is VALID [2022-02-21 04:24:22,649 INFO L290 TraceCheckUtils]: 109: Hoare triple {1703#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,650 INFO L290 TraceCheckUtils]: 110: Hoare triple {1703#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,650 INFO L290 TraceCheckUtils]: 111: Hoare triple {1703#false} assume !(1 == ~T2_E~0); {1703#false} is VALID [2022-02-21 04:24:22,650 INFO L290 TraceCheckUtils]: 112: Hoare triple {1703#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,650 INFO L290 TraceCheckUtils]: 113: Hoare triple {1703#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,650 INFO L290 TraceCheckUtils]: 114: Hoare triple {1703#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,651 INFO L290 TraceCheckUtils]: 115: Hoare triple {1703#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,651 INFO L290 TraceCheckUtils]: 116: Hoare triple {1703#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,651 INFO L290 TraceCheckUtils]: 117: Hoare triple {1703#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,651 INFO L290 TraceCheckUtils]: 118: Hoare triple {1703#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,651 INFO L290 TraceCheckUtils]: 119: Hoare triple {1703#false} assume !(1 == ~T10_E~0); {1703#false} is VALID [2022-02-21 04:24:22,652 INFO L290 TraceCheckUtils]: 120: Hoare triple {1703#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,652 INFO L290 TraceCheckUtils]: 121: Hoare triple {1703#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,652 INFO L290 TraceCheckUtils]: 122: Hoare triple {1703#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,652 INFO L290 TraceCheckUtils]: 123: Hoare triple {1703#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,652 INFO L290 TraceCheckUtils]: 124: Hoare triple {1703#false} assume 1 == ~E_3~0;~E_3~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,653 INFO L290 TraceCheckUtils]: 125: Hoare triple {1703#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,653 INFO L290 TraceCheckUtils]: 126: Hoare triple {1703#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,653 INFO L290 TraceCheckUtils]: 127: Hoare triple {1703#false} assume !(1 == ~E_6~0); {1703#false} is VALID [2022-02-21 04:24:22,653 INFO L290 TraceCheckUtils]: 128: Hoare triple {1703#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,653 INFO L290 TraceCheckUtils]: 129: Hoare triple {1703#false} assume 1 == ~E_8~0;~E_8~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,653 INFO L290 TraceCheckUtils]: 130: Hoare triple {1703#false} assume 1 == ~E_9~0;~E_9~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,654 INFO L290 TraceCheckUtils]: 131: Hoare triple {1703#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,654 INFO L290 TraceCheckUtils]: 132: Hoare triple {1703#false} assume 1 == ~E_11~0;~E_11~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,654 INFO L290 TraceCheckUtils]: 133: Hoare triple {1703#false} assume 1 == ~E_12~0;~E_12~0 := 2; {1703#false} is VALID [2022-02-21 04:24:22,654 INFO L290 TraceCheckUtils]: 134: Hoare triple {1703#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {1703#false} is VALID [2022-02-21 04:24:22,654 INFO L290 TraceCheckUtils]: 135: Hoare triple {1703#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {1703#false} is VALID [2022-02-21 04:24:22,655 INFO L290 TraceCheckUtils]: 136: Hoare triple {1703#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {1703#false} is VALID [2022-02-21 04:24:22,655 INFO L290 TraceCheckUtils]: 137: Hoare triple {1703#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {1703#false} is VALID [2022-02-21 04:24:22,655 INFO L290 TraceCheckUtils]: 138: Hoare triple {1703#false} assume !(0 == start_simulation_~tmp~3#1); {1703#false} is VALID [2022-02-21 04:24:22,655 INFO L290 TraceCheckUtils]: 139: Hoare triple {1703#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {1703#false} is VALID [2022-02-21 04:24:22,655 INFO L290 TraceCheckUtils]: 140: Hoare triple {1703#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {1703#false} is VALID [2022-02-21 04:24:22,656 INFO L290 TraceCheckUtils]: 141: Hoare triple {1703#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {1703#false} is VALID [2022-02-21 04:24:22,656 INFO L290 TraceCheckUtils]: 142: Hoare triple {1703#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {1703#false} is VALID [2022-02-21 04:24:22,656 INFO L290 TraceCheckUtils]: 143: Hoare triple {1703#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1703#false} is VALID [2022-02-21 04:24:22,656 INFO L290 TraceCheckUtils]: 144: Hoare triple {1703#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1703#false} is VALID [2022-02-21 04:24:22,656 INFO L290 TraceCheckUtils]: 145: Hoare triple {1703#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {1703#false} is VALID [2022-02-21 04:24:22,657 INFO L290 TraceCheckUtils]: 146: Hoare triple {1703#false} assume !(0 != start_simulation_~tmp___0~1#1); {1703#false} is VALID [2022-02-21 04:24:22,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:22,658 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:22,658 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308638165] [2022-02-21 04:24:22,658 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308638165] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:22,658 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:22,658 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:22,659 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226261545] [2022-02-21 04:24:22,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:22,660 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:22,661 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:22,696 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-02-21 04:24:22,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-02-21 04:24:22,702 INFO L87 Difference]: Start difference. First operand has 1695 states, 1694 states have (on average 1.5017709563164108) internal successors, (2544), 1694 states have internal predecessors, (2544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 73.5) internal successors, (147), 2 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:23,599 INFO L93 Difference]: Finished difference Result 1694 states and 2510 transitions. [2022-02-21 04:24:23,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-21 04:24:23,600 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 2 states, 2 states have (on average 73.5) internal successors, (147), 2 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,707 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 147 edges. 147 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:23,719 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1694 states and 2510 transitions. [2022-02-21 04:24:23,804 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:23,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1694 states to 1688 states and 2504 transitions. [2022-02-21 04:24:23,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:23,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:23,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2504 transitions. [2022-02-21 04:24:23,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:23,925 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2022-02-21 04:24:23,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2504 transitions. [2022-02-21 04:24:23,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:23,994 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:24,000 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2504 transitions. Second operand has 1688 states, 1688 states have (on average 1.4834123222748816) internal successors, (2504), 1687 states have internal predecessors, (2504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,003 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2504 transitions. Second operand has 1688 states, 1688 states have (on average 1.4834123222748816) internal successors, (2504), 1687 states have internal predecessors, (2504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,006 INFO L87 Difference]: Start difference. First operand 1688 states and 2504 transitions. Second operand has 1688 states, 1688 states have (on average 1.4834123222748816) internal successors, (2504), 1687 states have internal predecessors, (2504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,076 INFO L93 Difference]: Finished difference Result 1688 states and 2504 transitions. [2022-02-21 04:24:24,077 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2504 transitions. [2022-02-21 04:24:24,081 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:24,081 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:24,084 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.4834123222748816) internal successors, (2504), 1687 states have internal predecessors, (2504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2504 transitions. [2022-02-21 04:24:24,086 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.4834123222748816) internal successors, (2504), 1687 states have internal predecessors, (2504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2504 transitions. [2022-02-21 04:24:24,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,152 INFO L93 Difference]: Finished difference Result 1688 states and 2504 transitions. [2022-02-21 04:24:24,152 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2504 transitions. [2022-02-21 04:24:24,154 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:24,154 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:24,154 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:24,154 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:24,159 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4834123222748816) internal successors, (2504), 1687 states have internal predecessors, (2504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2504 transitions. [2022-02-21 04:24:24,246 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2022-02-21 04:24:24,246 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2504 transitions. [2022-02-21 04:24:24,246 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:24,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2504 transitions. [2022-02-21 04:24:24,251 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:24,251 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:24,251 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:24,253 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:24,253 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:24,253 INFO L791 eck$LassoCheckResult]: Stem: 4201#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 4202#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 5055#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4547#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4354#L821 assume !(1 == ~m_i~0);~m_st~0 := 2; 4355#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4440#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4741#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4863#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4864#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3652#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3653#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4801#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4247#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4248#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4154#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4155#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4543#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3896#L1174 assume !(0 == ~M_E~0); 3897#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3748#L1179-1 assume !(0 == ~T2_E~0); 3650#L1184-1 assume !(0 == ~T3_E~0); 3651#L1189-1 assume !(0 == ~T4_E~0); 3689#L1194-1 assume !(0 == ~T5_E~0); 3789#L1199-1 assume !(0 == ~T6_E~0); 4684#L1204-1 assume !(0 == ~T7_E~0); 4603#L1209-1 assume !(0 == ~T8_E~0); 4604#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4992#L1219-1 assume !(0 == ~T10_E~0); 5077#L1224-1 assume !(0 == ~T11_E~0); 4014#L1229-1 assume !(0 == ~T12_E~0); 3575#L1234-1 assume !(0 == ~E_1~0); 3576#L1239-1 assume !(0 == ~E_2~0); 3609#L1244-1 assume !(0 == ~E_3~0); 3610#L1249-1 assume !(0 == ~E_4~0); 4271#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3505#L1259-1 assume !(0 == ~E_6~0); 3460#L1264-1 assume !(0 == ~E_7~0); 3461#L1269-1 assume !(0 == ~E_8~0); 5082#L1274-1 assume !(0 == ~E_9~0); 5017#L1279-1 assume !(0 == ~E_10~0); 3693#L1284-1 assume !(0 == ~E_11~0); 3694#L1289-1 assume !(0 == ~E_12~0); 4323#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4324#L566 assume 1 == ~m_pc~0; 3477#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3478#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4632#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4633#L1455 assume !(0 != activate_threads_~tmp~1#1); 3923#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3924#L585 assume 1 == ~t1_pc~0; 3572#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3573#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4573#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4574#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 5042#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5040#L604 assume !(1 == ~t2_pc~0); 4652#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4653#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4186#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4187#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4824#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4825#L623 assume 1 == ~t3_pc~0; 4101#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3441#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4251#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4252#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 4859#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3474#L642 assume !(1 == ~t4_pc~0); 3475#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3940#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3941#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3546#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 3547#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4664#L661 assume 1 == ~t5_pc~0; 3711#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3712#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3673#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3674#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 4693#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4694#L680 assume !(1 == ~t6_pc~0); 4134#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4135#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4396#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4397#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 4925#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5038#L699 assume 1 == ~t7_pc~0; 4524#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4525#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3701#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3702#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 4426#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4325#L718 assume !(1 == ~t8_pc~0); 4326#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3687#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3688#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3729#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 3730#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3863#L737 assume 1 == ~t9_pc~0; 4728#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3998#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4599#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4600#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 4172#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4173#L756 assume 1 == ~t10_pc~0; 4752#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4418#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3404#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3405#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 3980#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3981#L775 assume !(1 == ~t11_pc~0); 4235#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4236#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3857#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3621#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3622#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3808#L794 assume 1 == ~t12_pc~0; 3648#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 3626#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4819#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3774#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 3775#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4254#L1307 assume !(1 == ~M_E~0); 4255#L1307-2 assume !(1 == ~T1_E~0); 4366#L1312-1 assume !(1 == ~T2_E~0); 4285#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4286#L1322-1 assume !(1 == ~T4_E~0); 3989#L1327-1 assume !(1 == ~T5_E~0); 3990#L1332-1 assume !(1 == ~T6_E~0); 4528#L1337-1 assume !(1 == ~T7_E~0); 4490#L1342-1 assume !(1 == ~T8_E~0); 4491#L1347-1 assume !(1 == ~T9_E~0); 4888#L1352-1 assume !(1 == ~T10_E~0); 4761#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4152#L1362-1 assume !(1 == ~T12_E~0); 4153#L1367-1 assume !(1 == ~E_1~0); 3790#L1372-1 assume !(1 == ~E_2~0); 3791#L1377-1 assume !(1 == ~E_3~0); 4084#L1382-1 assume !(1 == ~E_4~0); 4085#L1387-1 assume !(1 == ~E_5~0); 4654#L1392-1 assume !(1 == ~E_6~0); 4104#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4105#L1402-1 assume !(1 == ~E_8~0); 3801#L1407-1 assume !(1 == ~E_9~0); 3802#L1412-1 assume !(1 == ~E_10~0); 4817#L1417-1 assume !(1 == ~E_11~0); 4818#L1422-1 assume !(1 == ~E_12~0); 5036#L1427-1 assume { :end_inline_reset_delta_events } true; 3605#L1768-2 [2022-02-21 04:24:24,254 INFO L793 eck$LassoCheckResult]: Loop: 3605#L1768-2 assume !false; 3606#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4344#L1149 assume !false; 4716#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4869#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3995#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 3901#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3902#L976 assume !(0 != eval_~tmp~0#1); 5035#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5045#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4836#L1174-3 assume !(0 == ~M_E~0); 4829#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4578#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4579#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4762#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4413#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3763#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3764#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4005#L1209-3 assume !(0 == ~T8_E~0); 3425#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3426#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4184#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4185#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4203#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3613#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3614#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4057#L1249-3 assume !(0 == ~E_4~0); 4516#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4988#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4630#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3619#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3620#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5015#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4182#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4183#L1289-3 assume !(0 == ~E_12~0); 4171#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3847#L566-39 assume 1 == ~m_pc~0; 3848#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4450#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4162#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4163#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4705#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4706#L585-39 assume 1 == ~t1_pc~0; 4816#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3856#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3931#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3932#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4738#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4431#L604-39 assume 1 == ~t2_pc~0; 4432#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4063#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4064#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4481#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4482#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4046#L623-39 assume 1 == ~t3_pc~0; 3442#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3444#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4722#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3898#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3899#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4670#L642-39 assume 1 == ~t4_pc~0; 4241#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4242#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3770#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3771#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4868#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3819#L661-39 assume !(1 == ~t5_pc~0); 3450#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 3451#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4811#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4812#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4725#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4726#L680-39 assume 1 == ~t6_pc~0; 3512#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3513#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4655#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3978#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3979#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4993#L699-39 assume !(1 == ~t7_pc~0); 4416#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4137#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4138#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4821#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4942#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4940#L718-39 assume 1 == ~t8_pc~0; 4329#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4330#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4262#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4263#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 4565#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4534#L737-39 assume 1 == ~t9_pc~0; 3959#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3960#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4249#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5016#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4917#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4860#L756-39 assume !(1 == ~t10_pc~0); 4341#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 4342#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4086#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4087#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4219#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3559#L775-39 assume 1 == ~t11_pc~0; 3560#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4212#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4213#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5075#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4623#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4270#L794-39 assume !(1 == ~t12_pc~0); 3955#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 3956#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4776#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4677#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3501#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3502#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4969#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4970#L1312-3 assume !(1 == ~T2_E~0); 5081#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4695#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4696#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3640#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3611#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3612#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4358#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4483#L1352-3 assume !(1 == ~T10_E~0); 4484#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4923#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5074#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5065#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3438#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3439#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4070#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4071#L1392-3 assume !(1 == ~E_6~0); 4786#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5032#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4449#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3725#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3726#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4374#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4375#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 3735#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3736#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4602#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 4454#L1787 assume !(0 == start_simulation_~tmp~3#1); 4455#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4978#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3706#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4501#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 4502#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4053#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4054#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 4055#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 3605#L1768-2 [2022-02-21 04:24:24,254 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:24,255 INFO L85 PathProgramCache]: Analyzing trace with hash -1422298547, now seen corresponding path program 2 times [2022-02-21 04:24:24,255 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:24,255 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088887633] [2022-02-21 04:24:24,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:24,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:24,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,327 INFO L290 TraceCheckUtils]: 0: Hoare triple {8465#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {8465#true} is VALID [2022-02-21 04:24:24,327 INFO L290 TraceCheckUtils]: 1: Hoare triple {8465#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {8467#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:24,328 INFO L290 TraceCheckUtils]: 2: Hoare triple {8467#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {8467#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:24,328 INFO L290 TraceCheckUtils]: 3: Hoare triple {8467#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {8467#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:24,329 INFO L290 TraceCheckUtils]: 4: Hoare triple {8467#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,329 INFO L290 TraceCheckUtils]: 5: Hoare triple {8466#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {8466#false} is VALID [2022-02-21 04:24:24,329 INFO L290 TraceCheckUtils]: 6: Hoare triple {8466#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,329 INFO L290 TraceCheckUtils]: 7: Hoare triple {8466#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,329 INFO L290 TraceCheckUtils]: 8: Hoare triple {8466#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,329 INFO L290 TraceCheckUtils]: 9: Hoare triple {8466#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,330 INFO L290 TraceCheckUtils]: 10: Hoare triple {8466#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,330 INFO L290 TraceCheckUtils]: 11: Hoare triple {8466#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,330 INFO L290 TraceCheckUtils]: 12: Hoare triple {8466#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,330 INFO L290 TraceCheckUtils]: 13: Hoare triple {8466#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {8466#false} is VALID [2022-02-21 04:24:24,330 INFO L290 TraceCheckUtils]: 14: Hoare triple {8466#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,331 INFO L290 TraceCheckUtils]: 15: Hoare triple {8466#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,331 INFO L290 TraceCheckUtils]: 16: Hoare triple {8466#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,331 INFO L290 TraceCheckUtils]: 17: Hoare triple {8466#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {8466#false} is VALID [2022-02-21 04:24:24,331 INFO L290 TraceCheckUtils]: 18: Hoare triple {8466#false} assume !(0 == ~M_E~0); {8466#false} is VALID [2022-02-21 04:24:24,331 INFO L290 TraceCheckUtils]: 19: Hoare triple {8466#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {8466#false} is VALID [2022-02-21 04:24:24,331 INFO L290 TraceCheckUtils]: 20: Hoare triple {8466#false} assume !(0 == ~T2_E~0); {8466#false} is VALID [2022-02-21 04:24:24,332 INFO L290 TraceCheckUtils]: 21: Hoare triple {8466#false} assume !(0 == ~T3_E~0); {8466#false} is VALID [2022-02-21 04:24:24,334 INFO L290 TraceCheckUtils]: 22: Hoare triple {8466#false} assume !(0 == ~T4_E~0); {8466#false} is VALID [2022-02-21 04:24:24,334 INFO L290 TraceCheckUtils]: 23: Hoare triple {8466#false} assume !(0 == ~T5_E~0); {8466#false} is VALID [2022-02-21 04:24:24,334 INFO L290 TraceCheckUtils]: 24: Hoare triple {8466#false} assume !(0 == ~T6_E~0); {8466#false} is VALID [2022-02-21 04:24:24,334 INFO L290 TraceCheckUtils]: 25: Hoare triple {8466#false} assume !(0 == ~T7_E~0); {8466#false} is VALID [2022-02-21 04:24:24,334 INFO L290 TraceCheckUtils]: 26: Hoare triple {8466#false} assume !(0 == ~T8_E~0); {8466#false} is VALID [2022-02-21 04:24:24,335 INFO L290 TraceCheckUtils]: 27: Hoare triple {8466#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {8466#false} is VALID [2022-02-21 04:24:24,335 INFO L290 TraceCheckUtils]: 28: Hoare triple {8466#false} assume !(0 == ~T10_E~0); {8466#false} is VALID [2022-02-21 04:24:24,335 INFO L290 TraceCheckUtils]: 29: Hoare triple {8466#false} assume !(0 == ~T11_E~0); {8466#false} is VALID [2022-02-21 04:24:24,335 INFO L290 TraceCheckUtils]: 30: Hoare triple {8466#false} assume !(0 == ~T12_E~0); {8466#false} is VALID [2022-02-21 04:24:24,335 INFO L290 TraceCheckUtils]: 31: Hoare triple {8466#false} assume !(0 == ~E_1~0); {8466#false} is VALID [2022-02-21 04:24:24,336 INFO L290 TraceCheckUtils]: 32: Hoare triple {8466#false} assume !(0 == ~E_2~0); {8466#false} is VALID [2022-02-21 04:24:24,336 INFO L290 TraceCheckUtils]: 33: Hoare triple {8466#false} assume !(0 == ~E_3~0); {8466#false} is VALID [2022-02-21 04:24:24,336 INFO L290 TraceCheckUtils]: 34: Hoare triple {8466#false} assume !(0 == ~E_4~0); {8466#false} is VALID [2022-02-21 04:24:24,337 INFO L290 TraceCheckUtils]: 35: Hoare triple {8466#false} assume 0 == ~E_5~0;~E_5~0 := 1; {8466#false} is VALID [2022-02-21 04:24:24,338 INFO L290 TraceCheckUtils]: 36: Hoare triple {8466#false} assume !(0 == ~E_6~0); {8466#false} is VALID [2022-02-21 04:24:24,338 INFO L290 TraceCheckUtils]: 37: Hoare triple {8466#false} assume !(0 == ~E_7~0); {8466#false} is VALID [2022-02-21 04:24:24,338 INFO L290 TraceCheckUtils]: 38: Hoare triple {8466#false} assume !(0 == ~E_8~0); {8466#false} is VALID [2022-02-21 04:24:24,338 INFO L290 TraceCheckUtils]: 39: Hoare triple {8466#false} assume !(0 == ~E_9~0); {8466#false} is VALID [2022-02-21 04:24:24,338 INFO L290 TraceCheckUtils]: 40: Hoare triple {8466#false} assume !(0 == ~E_10~0); {8466#false} is VALID [2022-02-21 04:24:24,339 INFO L290 TraceCheckUtils]: 41: Hoare triple {8466#false} assume !(0 == ~E_11~0); {8466#false} is VALID [2022-02-21 04:24:24,339 INFO L290 TraceCheckUtils]: 42: Hoare triple {8466#false} assume !(0 == ~E_12~0); {8466#false} is VALID [2022-02-21 04:24:24,339 INFO L290 TraceCheckUtils]: 43: Hoare triple {8466#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8466#false} is VALID [2022-02-21 04:24:24,339 INFO L290 TraceCheckUtils]: 44: Hoare triple {8466#false} assume 1 == ~m_pc~0; {8466#false} is VALID [2022-02-21 04:24:24,339 INFO L290 TraceCheckUtils]: 45: Hoare triple {8466#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {8466#false} is VALID [2022-02-21 04:24:24,339 INFO L290 TraceCheckUtils]: 46: Hoare triple {8466#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8466#false} is VALID [2022-02-21 04:24:24,340 INFO L290 TraceCheckUtils]: 47: Hoare triple {8466#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {8466#false} is VALID [2022-02-21 04:24:24,340 INFO L290 TraceCheckUtils]: 48: Hoare triple {8466#false} assume !(0 != activate_threads_~tmp~1#1); {8466#false} is VALID [2022-02-21 04:24:24,340 INFO L290 TraceCheckUtils]: 49: Hoare triple {8466#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8466#false} is VALID [2022-02-21 04:24:24,340 INFO L290 TraceCheckUtils]: 50: Hoare triple {8466#false} assume 1 == ~t1_pc~0; {8466#false} is VALID [2022-02-21 04:24:24,340 INFO L290 TraceCheckUtils]: 51: Hoare triple {8466#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {8466#false} is VALID [2022-02-21 04:24:24,341 INFO L290 TraceCheckUtils]: 52: Hoare triple {8466#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8466#false} is VALID [2022-02-21 04:24:24,341 INFO L290 TraceCheckUtils]: 53: Hoare triple {8466#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {8466#false} is VALID [2022-02-21 04:24:24,344 INFO L290 TraceCheckUtils]: 54: Hoare triple {8466#false} assume !(0 != activate_threads_~tmp___0~0#1); {8466#false} is VALID [2022-02-21 04:24:24,344 INFO L290 TraceCheckUtils]: 55: Hoare triple {8466#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8466#false} is VALID [2022-02-21 04:24:24,345 INFO L290 TraceCheckUtils]: 56: Hoare triple {8466#false} assume !(1 == ~t2_pc~0); {8466#false} is VALID [2022-02-21 04:24:24,345 INFO L290 TraceCheckUtils]: 57: Hoare triple {8466#false} is_transmit2_triggered_~__retres1~2#1 := 0; {8466#false} is VALID [2022-02-21 04:24:24,345 INFO L290 TraceCheckUtils]: 58: Hoare triple {8466#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8466#false} is VALID [2022-02-21 04:24:24,345 INFO L290 TraceCheckUtils]: 59: Hoare triple {8466#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8466#false} is VALID [2022-02-21 04:24:24,345 INFO L290 TraceCheckUtils]: 60: Hoare triple {8466#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {8466#false} is VALID [2022-02-21 04:24:24,345 INFO L290 TraceCheckUtils]: 61: Hoare triple {8466#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8466#false} is VALID [2022-02-21 04:24:24,346 INFO L290 TraceCheckUtils]: 62: Hoare triple {8466#false} assume 1 == ~t3_pc~0; {8466#false} is VALID [2022-02-21 04:24:24,346 INFO L290 TraceCheckUtils]: 63: Hoare triple {8466#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {8466#false} is VALID [2022-02-21 04:24:24,346 INFO L290 TraceCheckUtils]: 64: Hoare triple {8466#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8466#false} is VALID [2022-02-21 04:24:24,346 INFO L290 TraceCheckUtils]: 65: Hoare triple {8466#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {8466#false} is VALID [2022-02-21 04:24:24,346 INFO L290 TraceCheckUtils]: 66: Hoare triple {8466#false} assume !(0 != activate_threads_~tmp___2~0#1); {8466#false} is VALID [2022-02-21 04:24:24,346 INFO L290 TraceCheckUtils]: 67: Hoare triple {8466#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8466#false} is VALID [2022-02-21 04:24:24,347 INFO L290 TraceCheckUtils]: 68: Hoare triple {8466#false} assume !(1 == ~t4_pc~0); {8466#false} is VALID [2022-02-21 04:24:24,347 INFO L290 TraceCheckUtils]: 69: Hoare triple {8466#false} is_transmit4_triggered_~__retres1~4#1 := 0; {8466#false} is VALID [2022-02-21 04:24:24,347 INFO L290 TraceCheckUtils]: 70: Hoare triple {8466#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8466#false} is VALID [2022-02-21 04:24:24,347 INFO L290 TraceCheckUtils]: 71: Hoare triple {8466#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {8466#false} is VALID [2022-02-21 04:24:24,350 INFO L290 TraceCheckUtils]: 72: Hoare triple {8466#false} assume !(0 != activate_threads_~tmp___3~0#1); {8466#false} is VALID [2022-02-21 04:24:24,350 INFO L290 TraceCheckUtils]: 73: Hoare triple {8466#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8466#false} is VALID [2022-02-21 04:24:24,350 INFO L290 TraceCheckUtils]: 74: Hoare triple {8466#false} assume 1 == ~t5_pc~0; {8466#false} is VALID [2022-02-21 04:24:24,350 INFO L290 TraceCheckUtils]: 75: Hoare triple {8466#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {8466#false} is VALID [2022-02-21 04:24:24,351 INFO L290 TraceCheckUtils]: 76: Hoare triple {8466#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8466#false} is VALID [2022-02-21 04:24:24,351 INFO L290 TraceCheckUtils]: 77: Hoare triple {8466#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {8466#false} is VALID [2022-02-21 04:24:24,351 INFO L290 TraceCheckUtils]: 78: Hoare triple {8466#false} assume !(0 != activate_threads_~tmp___4~0#1); {8466#false} is VALID [2022-02-21 04:24:24,351 INFO L290 TraceCheckUtils]: 79: Hoare triple {8466#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8466#false} is VALID [2022-02-21 04:24:24,351 INFO L290 TraceCheckUtils]: 80: Hoare triple {8466#false} assume !(1 == ~t6_pc~0); {8466#false} is VALID [2022-02-21 04:24:24,351 INFO L290 TraceCheckUtils]: 81: Hoare triple {8466#false} is_transmit6_triggered_~__retres1~6#1 := 0; {8466#false} is VALID [2022-02-21 04:24:24,358 INFO L290 TraceCheckUtils]: 82: Hoare triple {8466#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8466#false} is VALID [2022-02-21 04:24:24,359 INFO L290 TraceCheckUtils]: 83: Hoare triple {8466#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {8466#false} is VALID [2022-02-21 04:24:24,359 INFO L290 TraceCheckUtils]: 84: Hoare triple {8466#false} assume !(0 != activate_threads_~tmp___5~0#1); {8466#false} is VALID [2022-02-21 04:24:24,359 INFO L290 TraceCheckUtils]: 85: Hoare triple {8466#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {8466#false} is VALID [2022-02-21 04:24:24,359 INFO L290 TraceCheckUtils]: 86: Hoare triple {8466#false} assume 1 == ~t7_pc~0; {8466#false} is VALID [2022-02-21 04:24:24,360 INFO L290 TraceCheckUtils]: 87: Hoare triple {8466#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {8466#false} is VALID [2022-02-21 04:24:24,360 INFO L290 TraceCheckUtils]: 88: Hoare triple {8466#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {8466#false} is VALID [2022-02-21 04:24:24,360 INFO L290 TraceCheckUtils]: 89: Hoare triple {8466#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {8466#false} is VALID [2022-02-21 04:24:24,360 INFO L290 TraceCheckUtils]: 90: Hoare triple {8466#false} assume !(0 != activate_threads_~tmp___6~0#1); {8466#false} is VALID [2022-02-21 04:24:24,360 INFO L290 TraceCheckUtils]: 91: Hoare triple {8466#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {8466#false} is VALID [2022-02-21 04:24:24,360 INFO L290 TraceCheckUtils]: 92: Hoare triple {8466#false} assume !(1 == ~t8_pc~0); {8466#false} is VALID [2022-02-21 04:24:24,361 INFO L290 TraceCheckUtils]: 93: Hoare triple {8466#false} is_transmit8_triggered_~__retres1~8#1 := 0; {8466#false} is VALID [2022-02-21 04:24:24,361 INFO L290 TraceCheckUtils]: 94: Hoare triple {8466#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {8466#false} is VALID [2022-02-21 04:24:24,361 INFO L290 TraceCheckUtils]: 95: Hoare triple {8466#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {8466#false} is VALID [2022-02-21 04:24:24,361 INFO L290 TraceCheckUtils]: 96: Hoare triple {8466#false} assume !(0 != activate_threads_~tmp___7~0#1); {8466#false} is VALID [2022-02-21 04:24:24,361 INFO L290 TraceCheckUtils]: 97: Hoare triple {8466#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {8466#false} is VALID [2022-02-21 04:24:24,361 INFO L290 TraceCheckUtils]: 98: Hoare triple {8466#false} assume 1 == ~t9_pc~0; {8466#false} is VALID [2022-02-21 04:24:24,362 INFO L290 TraceCheckUtils]: 99: Hoare triple {8466#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {8466#false} is VALID [2022-02-21 04:24:24,362 INFO L290 TraceCheckUtils]: 100: Hoare triple {8466#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {8466#false} is VALID [2022-02-21 04:24:24,362 INFO L290 TraceCheckUtils]: 101: Hoare triple {8466#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {8466#false} is VALID [2022-02-21 04:24:24,362 INFO L290 TraceCheckUtils]: 102: Hoare triple {8466#false} assume !(0 != activate_threads_~tmp___8~0#1); {8466#false} is VALID [2022-02-21 04:24:24,362 INFO L290 TraceCheckUtils]: 103: Hoare triple {8466#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {8466#false} is VALID [2022-02-21 04:24:24,362 INFO L290 TraceCheckUtils]: 104: Hoare triple {8466#false} assume 1 == ~t10_pc~0; {8466#false} is VALID [2022-02-21 04:24:24,363 INFO L290 TraceCheckUtils]: 105: Hoare triple {8466#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {8466#false} is VALID [2022-02-21 04:24:24,363 INFO L290 TraceCheckUtils]: 106: Hoare triple {8466#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {8466#false} is VALID [2022-02-21 04:24:24,363 INFO L290 TraceCheckUtils]: 107: Hoare triple {8466#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {8466#false} is VALID [2022-02-21 04:24:24,363 INFO L290 TraceCheckUtils]: 108: Hoare triple {8466#false} assume !(0 != activate_threads_~tmp___9~0#1); {8466#false} is VALID [2022-02-21 04:24:24,363 INFO L290 TraceCheckUtils]: 109: Hoare triple {8466#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {8466#false} is VALID [2022-02-21 04:24:24,363 INFO L290 TraceCheckUtils]: 110: Hoare triple {8466#false} assume !(1 == ~t11_pc~0); {8466#false} is VALID [2022-02-21 04:24:24,364 INFO L290 TraceCheckUtils]: 111: Hoare triple {8466#false} is_transmit11_triggered_~__retres1~11#1 := 0; {8466#false} is VALID [2022-02-21 04:24:24,364 INFO L290 TraceCheckUtils]: 112: Hoare triple {8466#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {8466#false} is VALID [2022-02-21 04:24:24,364 INFO L290 TraceCheckUtils]: 113: Hoare triple {8466#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {8466#false} is VALID [2022-02-21 04:24:24,364 INFO L290 TraceCheckUtils]: 114: Hoare triple {8466#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {8466#false} is VALID [2022-02-21 04:24:24,364 INFO L290 TraceCheckUtils]: 115: Hoare triple {8466#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {8466#false} is VALID [2022-02-21 04:24:24,364 INFO L290 TraceCheckUtils]: 116: Hoare triple {8466#false} assume 1 == ~t12_pc~0; {8466#false} is VALID [2022-02-21 04:24:24,365 INFO L290 TraceCheckUtils]: 117: Hoare triple {8466#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {8466#false} is VALID [2022-02-21 04:24:24,365 INFO L290 TraceCheckUtils]: 118: Hoare triple {8466#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {8466#false} is VALID [2022-02-21 04:24:24,365 INFO L290 TraceCheckUtils]: 119: Hoare triple {8466#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {8466#false} is VALID [2022-02-21 04:24:24,365 INFO L290 TraceCheckUtils]: 120: Hoare triple {8466#false} assume !(0 != activate_threads_~tmp___11~0#1); {8466#false} is VALID [2022-02-21 04:24:24,365 INFO L290 TraceCheckUtils]: 121: Hoare triple {8466#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8466#false} is VALID [2022-02-21 04:24:24,365 INFO L290 TraceCheckUtils]: 122: Hoare triple {8466#false} assume !(1 == ~M_E~0); {8466#false} is VALID [2022-02-21 04:24:24,366 INFO L290 TraceCheckUtils]: 123: Hoare triple {8466#false} assume !(1 == ~T1_E~0); {8466#false} is VALID [2022-02-21 04:24:24,366 INFO L290 TraceCheckUtils]: 124: Hoare triple {8466#false} assume !(1 == ~T2_E~0); {8466#false} is VALID [2022-02-21 04:24:24,366 INFO L290 TraceCheckUtils]: 125: Hoare triple {8466#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,366 INFO L290 TraceCheckUtils]: 126: Hoare triple {8466#false} assume !(1 == ~T4_E~0); {8466#false} is VALID [2022-02-21 04:24:24,366 INFO L290 TraceCheckUtils]: 127: Hoare triple {8466#false} assume !(1 == ~T5_E~0); {8466#false} is VALID [2022-02-21 04:24:24,366 INFO L290 TraceCheckUtils]: 128: Hoare triple {8466#false} assume !(1 == ~T6_E~0); {8466#false} is VALID [2022-02-21 04:24:24,367 INFO L290 TraceCheckUtils]: 129: Hoare triple {8466#false} assume !(1 == ~T7_E~0); {8466#false} is VALID [2022-02-21 04:24:24,367 INFO L290 TraceCheckUtils]: 130: Hoare triple {8466#false} assume !(1 == ~T8_E~0); {8466#false} is VALID [2022-02-21 04:24:24,367 INFO L290 TraceCheckUtils]: 131: Hoare triple {8466#false} assume !(1 == ~T9_E~0); {8466#false} is VALID [2022-02-21 04:24:24,369 INFO L290 TraceCheckUtils]: 132: Hoare triple {8466#false} assume !(1 == ~T10_E~0); {8466#false} is VALID [2022-02-21 04:24:24,369 INFO L290 TraceCheckUtils]: 133: Hoare triple {8466#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,370 INFO L290 TraceCheckUtils]: 134: Hoare triple {8466#false} assume !(1 == ~T12_E~0); {8466#false} is VALID [2022-02-21 04:24:24,370 INFO L290 TraceCheckUtils]: 135: Hoare triple {8466#false} assume !(1 == ~E_1~0); {8466#false} is VALID [2022-02-21 04:24:24,370 INFO L290 TraceCheckUtils]: 136: Hoare triple {8466#false} assume !(1 == ~E_2~0); {8466#false} is VALID [2022-02-21 04:24:24,370 INFO L290 TraceCheckUtils]: 137: Hoare triple {8466#false} assume !(1 == ~E_3~0); {8466#false} is VALID [2022-02-21 04:24:24,370 INFO L290 TraceCheckUtils]: 138: Hoare triple {8466#false} assume !(1 == ~E_4~0); {8466#false} is VALID [2022-02-21 04:24:24,370 INFO L290 TraceCheckUtils]: 139: Hoare triple {8466#false} assume !(1 == ~E_5~0); {8466#false} is VALID [2022-02-21 04:24:24,371 INFO L290 TraceCheckUtils]: 140: Hoare triple {8466#false} assume !(1 == ~E_6~0); {8466#false} is VALID [2022-02-21 04:24:24,371 INFO L290 TraceCheckUtils]: 141: Hoare triple {8466#false} assume 1 == ~E_7~0;~E_7~0 := 2; {8466#false} is VALID [2022-02-21 04:24:24,371 INFO L290 TraceCheckUtils]: 142: Hoare triple {8466#false} assume !(1 == ~E_8~0); {8466#false} is VALID [2022-02-21 04:24:24,371 INFO L290 TraceCheckUtils]: 143: Hoare triple {8466#false} assume !(1 == ~E_9~0); {8466#false} is VALID [2022-02-21 04:24:24,371 INFO L290 TraceCheckUtils]: 144: Hoare triple {8466#false} assume !(1 == ~E_10~0); {8466#false} is VALID [2022-02-21 04:24:24,371 INFO L290 TraceCheckUtils]: 145: Hoare triple {8466#false} assume !(1 == ~E_11~0); {8466#false} is VALID [2022-02-21 04:24:24,372 INFO L290 TraceCheckUtils]: 146: Hoare triple {8466#false} assume !(1 == ~E_12~0); {8466#false} is VALID [2022-02-21 04:24:24,372 INFO L290 TraceCheckUtils]: 147: Hoare triple {8466#false} assume { :end_inline_reset_delta_events } true; {8466#false} is VALID [2022-02-21 04:24:24,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,375 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,375 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088887633] [2022-02-21 04:24:24,376 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088887633] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,376 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,376 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:24,376 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139011905] [2022-02-21 04:24:24,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,377 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:24,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:24,379 INFO L85 PathProgramCache]: Analyzing trace with hash -1764555615, now seen corresponding path program 1 times [2022-02-21 04:24:24,379 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:24,380 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169334997] [2022-02-21 04:24:24,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:24,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:24,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:24,478 INFO L290 TraceCheckUtils]: 0: Hoare triple {8468#true} assume !false; {8468#true} is VALID [2022-02-21 04:24:24,478 INFO L290 TraceCheckUtils]: 1: Hoare triple {8468#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {8468#true} is VALID [2022-02-21 04:24:24,478 INFO L290 TraceCheckUtils]: 2: Hoare triple {8468#true} assume !false; {8468#true} is VALID [2022-02-21 04:24:24,478 INFO L290 TraceCheckUtils]: 3: Hoare triple {8468#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {8468#true} is VALID [2022-02-21 04:24:24,478 INFO L290 TraceCheckUtils]: 4: Hoare triple {8468#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {8468#true} is VALID [2022-02-21 04:24:24,478 INFO L290 TraceCheckUtils]: 5: Hoare triple {8468#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {8468#true} is VALID [2022-02-21 04:24:24,479 INFO L290 TraceCheckUtils]: 6: Hoare triple {8468#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {8468#true} is VALID [2022-02-21 04:24:24,479 INFO L290 TraceCheckUtils]: 7: Hoare triple {8468#true} assume !(0 != eval_~tmp~0#1); {8468#true} is VALID [2022-02-21 04:24:24,479 INFO L290 TraceCheckUtils]: 8: Hoare triple {8468#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {8468#true} is VALID [2022-02-21 04:24:24,479 INFO L290 TraceCheckUtils]: 9: Hoare triple {8468#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {8468#true} is VALID [2022-02-21 04:24:24,479 INFO L290 TraceCheckUtils]: 10: Hoare triple {8468#true} assume !(0 == ~M_E~0); {8468#true} is VALID [2022-02-21 04:24:24,479 INFO L290 TraceCheckUtils]: 11: Hoare triple {8468#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {8468#true} is VALID [2022-02-21 04:24:24,480 INFO L290 TraceCheckUtils]: 12: Hoare triple {8468#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,480 INFO L290 TraceCheckUtils]: 13: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,481 INFO L290 TraceCheckUtils]: 14: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,481 INFO L290 TraceCheckUtils]: 15: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,481 INFO L290 TraceCheckUtils]: 16: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,482 INFO L290 TraceCheckUtils]: 17: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,482 INFO L290 TraceCheckUtils]: 18: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,482 INFO L290 TraceCheckUtils]: 19: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,483 INFO L290 TraceCheckUtils]: 20: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,483 INFO L290 TraceCheckUtils]: 21: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,483 INFO L290 TraceCheckUtils]: 22: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,484 INFO L290 TraceCheckUtils]: 23: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,484 INFO L290 TraceCheckUtils]: 24: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,484 INFO L290 TraceCheckUtils]: 25: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,485 INFO L290 TraceCheckUtils]: 26: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,485 INFO L290 TraceCheckUtils]: 27: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,485 INFO L290 TraceCheckUtils]: 28: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,486 INFO L290 TraceCheckUtils]: 29: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,486 INFO L290 TraceCheckUtils]: 30: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,487 INFO L290 TraceCheckUtils]: 31: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,487 INFO L290 TraceCheckUtils]: 32: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,487 INFO L290 TraceCheckUtils]: 33: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,488 INFO L290 TraceCheckUtils]: 34: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,488 INFO L290 TraceCheckUtils]: 35: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,488 INFO L290 TraceCheckUtils]: 36: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,489 INFO L290 TraceCheckUtils]: 37: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,489 INFO L290 TraceCheckUtils]: 38: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,489 INFO L290 TraceCheckUtils]: 39: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,490 INFO L290 TraceCheckUtils]: 40: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,490 INFO L290 TraceCheckUtils]: 41: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,490 INFO L290 TraceCheckUtils]: 42: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,491 INFO L290 TraceCheckUtils]: 43: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,491 INFO L290 TraceCheckUtils]: 44: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,492 INFO L290 TraceCheckUtils]: 45: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,492 INFO L290 TraceCheckUtils]: 46: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,492 INFO L290 TraceCheckUtils]: 47: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,493 INFO L290 TraceCheckUtils]: 48: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,493 INFO L290 TraceCheckUtils]: 49: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,493 INFO L290 TraceCheckUtils]: 50: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,494 INFO L290 TraceCheckUtils]: 51: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,494 INFO L290 TraceCheckUtils]: 52: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,494 INFO L290 TraceCheckUtils]: 53: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,495 INFO L290 TraceCheckUtils]: 54: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,495 INFO L290 TraceCheckUtils]: 55: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,495 INFO L290 TraceCheckUtils]: 56: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,496 INFO L290 TraceCheckUtils]: 57: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,496 INFO L290 TraceCheckUtils]: 58: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,496 INFO L290 TraceCheckUtils]: 59: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,497 INFO L290 TraceCheckUtils]: 60: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,497 INFO L290 TraceCheckUtils]: 61: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,498 INFO L290 TraceCheckUtils]: 62: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,498 INFO L290 TraceCheckUtils]: 63: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,498 INFO L290 TraceCheckUtils]: 64: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,499 INFO L290 TraceCheckUtils]: 65: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,499 INFO L290 TraceCheckUtils]: 66: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,499 INFO L290 TraceCheckUtils]: 67: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,500 INFO L290 TraceCheckUtils]: 68: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,500 INFO L290 TraceCheckUtils]: 69: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,500 INFO L290 TraceCheckUtils]: 70: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,501 INFO L290 TraceCheckUtils]: 71: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,501 INFO L290 TraceCheckUtils]: 72: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,502 INFO L290 TraceCheckUtils]: 73: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,502 INFO L290 TraceCheckUtils]: 74: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,502 INFO L290 TraceCheckUtils]: 75: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,503 INFO L290 TraceCheckUtils]: 76: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,503 INFO L290 TraceCheckUtils]: 77: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,503 INFO L290 TraceCheckUtils]: 78: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,504 INFO L290 TraceCheckUtils]: 79: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,504 INFO L290 TraceCheckUtils]: 80: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,504 INFO L290 TraceCheckUtils]: 81: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,505 INFO L290 TraceCheckUtils]: 82: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,505 INFO L290 TraceCheckUtils]: 83: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,505 INFO L290 TraceCheckUtils]: 84: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,506 INFO L290 TraceCheckUtils]: 85: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,506 INFO L290 TraceCheckUtils]: 86: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,506 INFO L290 TraceCheckUtils]: 87: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,507 INFO L290 TraceCheckUtils]: 88: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,507 INFO L290 TraceCheckUtils]: 89: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,507 INFO L290 TraceCheckUtils]: 90: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,508 INFO L290 TraceCheckUtils]: 91: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,508 INFO L290 TraceCheckUtils]: 92: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,508 INFO L290 TraceCheckUtils]: 93: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,509 INFO L290 TraceCheckUtils]: 94: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,509 INFO L290 TraceCheckUtils]: 95: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,509 INFO L290 TraceCheckUtils]: 96: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t10_pc~0); {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,510 INFO L290 TraceCheckUtils]: 97: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,510 INFO L290 TraceCheckUtils]: 98: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,510 INFO L290 TraceCheckUtils]: 99: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,511 INFO L290 TraceCheckUtils]: 100: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,511 INFO L290 TraceCheckUtils]: 101: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,511 INFO L290 TraceCheckUtils]: 102: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,512 INFO L290 TraceCheckUtils]: 103: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,512 INFO L290 TraceCheckUtils]: 104: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,513 INFO L290 TraceCheckUtils]: 105: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,513 INFO L290 TraceCheckUtils]: 106: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,513 INFO L290 TraceCheckUtils]: 107: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,514 INFO L290 TraceCheckUtils]: 108: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t12_pc~0); {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,514 INFO L290 TraceCheckUtils]: 109: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,514 INFO L290 TraceCheckUtils]: 110: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,515 INFO L290 TraceCheckUtils]: 111: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,515 INFO L290 TraceCheckUtils]: 112: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,515 INFO L290 TraceCheckUtils]: 113: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,516 INFO L290 TraceCheckUtils]: 114: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,516 INFO L290 TraceCheckUtils]: 115: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {8470#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:24,516 INFO L290 TraceCheckUtils]: 116: Hoare triple {8470#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {8469#false} is VALID [2022-02-21 04:24:24,516 INFO L290 TraceCheckUtils]: 117: Hoare triple {8469#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,517 INFO L290 TraceCheckUtils]: 118: Hoare triple {8469#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,517 INFO L290 TraceCheckUtils]: 119: Hoare triple {8469#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,517 INFO L290 TraceCheckUtils]: 120: Hoare triple {8469#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,517 INFO L290 TraceCheckUtils]: 121: Hoare triple {8469#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,517 INFO L290 TraceCheckUtils]: 122: Hoare triple {8469#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,517 INFO L290 TraceCheckUtils]: 123: Hoare triple {8469#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,518 INFO L290 TraceCheckUtils]: 124: Hoare triple {8469#false} assume !(1 == ~T10_E~0); {8469#false} is VALID [2022-02-21 04:24:24,518 INFO L290 TraceCheckUtils]: 125: Hoare triple {8469#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,518 INFO L290 TraceCheckUtils]: 126: Hoare triple {8469#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,518 INFO L290 TraceCheckUtils]: 127: Hoare triple {8469#false} assume 1 == ~E_1~0;~E_1~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,518 INFO L290 TraceCheckUtils]: 128: Hoare triple {8469#false} assume 1 == ~E_2~0;~E_2~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,518 INFO L290 TraceCheckUtils]: 129: Hoare triple {8469#false} assume 1 == ~E_3~0;~E_3~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,518 INFO L290 TraceCheckUtils]: 130: Hoare triple {8469#false} assume 1 == ~E_4~0;~E_4~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,519 INFO L290 TraceCheckUtils]: 131: Hoare triple {8469#false} assume 1 == ~E_5~0;~E_5~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,519 INFO L290 TraceCheckUtils]: 132: Hoare triple {8469#false} assume !(1 == ~E_6~0); {8469#false} is VALID [2022-02-21 04:24:24,519 INFO L290 TraceCheckUtils]: 133: Hoare triple {8469#false} assume 1 == ~E_7~0;~E_7~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,519 INFO L290 TraceCheckUtils]: 134: Hoare triple {8469#false} assume 1 == ~E_8~0;~E_8~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,519 INFO L290 TraceCheckUtils]: 135: Hoare triple {8469#false} assume 1 == ~E_9~0;~E_9~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,519 INFO L290 TraceCheckUtils]: 136: Hoare triple {8469#false} assume 1 == ~E_10~0;~E_10~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,519 INFO L290 TraceCheckUtils]: 137: Hoare triple {8469#false} assume 1 == ~E_11~0;~E_11~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,520 INFO L290 TraceCheckUtils]: 138: Hoare triple {8469#false} assume 1 == ~E_12~0;~E_12~0 := 2; {8469#false} is VALID [2022-02-21 04:24:24,520 INFO L290 TraceCheckUtils]: 139: Hoare triple {8469#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {8469#false} is VALID [2022-02-21 04:24:24,520 INFO L290 TraceCheckUtils]: 140: Hoare triple {8469#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {8469#false} is VALID [2022-02-21 04:24:24,520 INFO L290 TraceCheckUtils]: 141: Hoare triple {8469#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {8469#false} is VALID [2022-02-21 04:24:24,520 INFO L290 TraceCheckUtils]: 142: Hoare triple {8469#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {8469#false} is VALID [2022-02-21 04:24:24,520 INFO L290 TraceCheckUtils]: 143: Hoare triple {8469#false} assume !(0 == start_simulation_~tmp~3#1); {8469#false} is VALID [2022-02-21 04:24:24,520 INFO L290 TraceCheckUtils]: 144: Hoare triple {8469#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {8469#false} is VALID [2022-02-21 04:24:24,521 INFO L290 TraceCheckUtils]: 145: Hoare triple {8469#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {8469#false} is VALID [2022-02-21 04:24:24,521 INFO L290 TraceCheckUtils]: 146: Hoare triple {8469#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {8469#false} is VALID [2022-02-21 04:24:24,521 INFO L290 TraceCheckUtils]: 147: Hoare triple {8469#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {8469#false} is VALID [2022-02-21 04:24:24,521 INFO L290 TraceCheckUtils]: 148: Hoare triple {8469#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {8469#false} is VALID [2022-02-21 04:24:24,521 INFO L290 TraceCheckUtils]: 149: Hoare triple {8469#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {8469#false} is VALID [2022-02-21 04:24:24,521 INFO L290 TraceCheckUtils]: 150: Hoare triple {8469#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {8469#false} is VALID [2022-02-21 04:24:24,521 INFO L290 TraceCheckUtils]: 151: Hoare triple {8469#false} assume !(0 != start_simulation_~tmp___0~1#1); {8469#false} is VALID [2022-02-21 04:24:24,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:24,523 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:24,523 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1169334997] [2022-02-21 04:24:24,523 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1169334997] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:24,523 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:24,523 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:24,524 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1141969889] [2022-02-21 04:24:24,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:24,524 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:24,524 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:24,525 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:24,525 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:24,526 INFO L87 Difference]: Start difference. First operand 1688 states and 2504 transitions. cyclomatic complexity: 817 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:25,911 INFO L93 Difference]: Finished difference Result 1688 states and 2503 transitions. [2022-02-21 04:24:25,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:25,912 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,014 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:26,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2503 transitions. [2022-02-21 04:24:26,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:26,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2503 transitions. [2022-02-21 04:24:26,365 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:26,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:26,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2503 transitions. [2022-02-21 04:24:26,368 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:26,368 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2022-02-21 04:24:26,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2503 transitions. [2022-02-21 04:24:26,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:26,422 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:26,425 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2503 transitions. Second operand has 1688 states, 1688 states have (on average 1.4828199052132702) internal successors, (2503), 1687 states have internal predecessors, (2503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,427 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2503 transitions. Second operand has 1688 states, 1688 states have (on average 1.4828199052132702) internal successors, (2503), 1687 states have internal predecessors, (2503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,430 INFO L87 Difference]: Start difference. First operand 1688 states and 2503 transitions. Second operand has 1688 states, 1688 states have (on average 1.4828199052132702) internal successors, (2503), 1687 states have internal predecessors, (2503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,550 INFO L93 Difference]: Finished difference Result 1688 states and 2503 transitions. [2022-02-21 04:24:26,550 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2503 transitions. [2022-02-21 04:24:26,573 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:26,573 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:26,576 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.4828199052132702) internal successors, (2503), 1687 states have internal predecessors, (2503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2503 transitions. [2022-02-21 04:24:26,578 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.4828199052132702) internal successors, (2503), 1687 states have internal predecessors, (2503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2503 transitions. [2022-02-21 04:24:26,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:26,656 INFO L93 Difference]: Finished difference Result 1688 states and 2503 transitions. [2022-02-21 04:24:26,656 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2503 transitions. [2022-02-21 04:24:26,658 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:26,658 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:26,658 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:26,658 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:26,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4828199052132702) internal successors, (2503), 1687 states have internal predecessors, (2503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:26,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2503 transitions. [2022-02-21 04:24:26,722 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2022-02-21 04:24:26,722 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2503 transitions. [2022-02-21 04:24:26,723 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:26,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2503 transitions. [2022-02-21 04:24:26,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:26,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:26,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:26,728 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:26,728 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:26,729 INFO L791 eck$LassoCheckResult]: Stem: 10962#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 10963#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11816#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11308#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11115#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 11116#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11201#L826-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 11502#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 11624#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11625#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10413#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10414#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11562#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11008#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11009#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10915#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10916#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11304#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10657#L1174 assume !(0 == ~M_E~0); 10658#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10509#L1179-1 assume !(0 == ~T2_E~0); 10411#L1184-1 assume !(0 == ~T3_E~0); 10412#L1189-1 assume !(0 == ~T4_E~0); 10450#L1194-1 assume !(0 == ~T5_E~0); 10550#L1199-1 assume !(0 == ~T6_E~0); 11445#L1204-1 assume !(0 == ~T7_E~0); 11364#L1209-1 assume !(0 == ~T8_E~0); 11365#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11753#L1219-1 assume !(0 == ~T10_E~0); 11838#L1224-1 assume !(0 == ~T11_E~0); 10775#L1229-1 assume !(0 == ~T12_E~0); 10336#L1234-1 assume !(0 == ~E_1~0); 10337#L1239-1 assume !(0 == ~E_2~0); 10370#L1244-1 assume !(0 == ~E_3~0); 10371#L1249-1 assume !(0 == ~E_4~0); 11032#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10266#L1259-1 assume !(0 == ~E_6~0); 10221#L1264-1 assume !(0 == ~E_7~0); 10222#L1269-1 assume !(0 == ~E_8~0); 11843#L1274-1 assume !(0 == ~E_9~0); 11778#L1279-1 assume !(0 == ~E_10~0); 10454#L1284-1 assume !(0 == ~E_11~0); 10455#L1289-1 assume !(0 == ~E_12~0); 11084#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11085#L566 assume 1 == ~m_pc~0; 10238#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10239#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11393#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11394#L1455 assume !(0 != activate_threads_~tmp~1#1); 10684#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10685#L585 assume 1 == ~t1_pc~0; 10333#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10334#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11334#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11335#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 11803#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11801#L604 assume !(1 == ~t2_pc~0); 11413#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11414#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10947#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10948#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11585#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11586#L623 assume 1 == ~t3_pc~0; 10862#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10202#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11012#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11013#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 11620#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10235#L642 assume !(1 == ~t4_pc~0); 10236#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10701#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10702#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10307#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 10308#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11425#L661 assume 1 == ~t5_pc~0; 10472#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10473#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10434#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10435#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 11454#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11455#L680 assume !(1 == ~t6_pc~0); 10895#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10896#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11157#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11158#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 11686#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11799#L699 assume 1 == ~t7_pc~0; 11285#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11286#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10462#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10463#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 11187#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11086#L718 assume !(1 == ~t8_pc~0); 11087#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10448#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10449#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10490#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 10491#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10624#L737 assume 1 == ~t9_pc~0; 11489#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10759#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11360#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11361#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 10933#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10934#L756 assume 1 == ~t10_pc~0; 11513#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11179#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10165#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10166#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 10741#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10742#L775 assume !(1 == ~t11_pc~0); 10996#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 10997#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10618#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10382#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10383#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 10569#L794 assume 1 == ~t12_pc~0; 10409#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10387#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11580#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10535#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 10536#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11015#L1307 assume !(1 == ~M_E~0); 11016#L1307-2 assume !(1 == ~T1_E~0); 11127#L1312-1 assume !(1 == ~T2_E~0); 11046#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11047#L1322-1 assume !(1 == ~T4_E~0); 10750#L1327-1 assume !(1 == ~T5_E~0); 10751#L1332-1 assume !(1 == ~T6_E~0); 11289#L1337-1 assume !(1 == ~T7_E~0); 11251#L1342-1 assume !(1 == ~T8_E~0); 11252#L1347-1 assume !(1 == ~T9_E~0); 11649#L1352-1 assume !(1 == ~T10_E~0); 11522#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10913#L1362-1 assume !(1 == ~T12_E~0); 10914#L1367-1 assume !(1 == ~E_1~0); 10551#L1372-1 assume !(1 == ~E_2~0); 10552#L1377-1 assume !(1 == ~E_3~0); 10845#L1382-1 assume !(1 == ~E_4~0); 10846#L1387-1 assume !(1 == ~E_5~0); 11415#L1392-1 assume !(1 == ~E_6~0); 10865#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 10866#L1402-1 assume !(1 == ~E_8~0); 10562#L1407-1 assume !(1 == ~E_9~0); 10563#L1412-1 assume !(1 == ~E_10~0); 11578#L1417-1 assume !(1 == ~E_11~0); 11579#L1422-1 assume !(1 == ~E_12~0); 11797#L1427-1 assume { :end_inline_reset_delta_events } true; 10366#L1768-2 [2022-02-21 04:24:26,729 INFO L793 eck$LassoCheckResult]: Loop: 10366#L1768-2 assume !false; 10367#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11105#L1149 assume !false; 11477#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11630#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10756#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 10662#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10663#L976 assume !(0 != eval_~tmp~0#1); 11796#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11806#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11597#L1174-3 assume !(0 == ~M_E~0); 11590#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11339#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11340#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11523#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11174#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10524#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10525#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10766#L1209-3 assume !(0 == ~T8_E~0); 10186#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10187#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10945#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 10946#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 10964#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10374#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10375#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10818#L1249-3 assume !(0 == ~E_4~0); 11277#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11749#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11391#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10380#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10381#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11776#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10943#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10944#L1289-3 assume !(0 == ~E_12~0); 10932#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10608#L566-39 assume 1 == ~m_pc~0; 10609#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11211#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10923#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10924#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11466#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11467#L585-39 assume !(1 == ~t1_pc~0); 10616#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 10617#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10692#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10693#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11499#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11192#L604-39 assume 1 == ~t2_pc~0; 11193#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10824#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10825#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11242#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11243#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10807#L623-39 assume 1 == ~t3_pc~0; 10203#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10205#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11483#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10659#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10660#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11431#L642-39 assume 1 == ~t4_pc~0; 11002#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11003#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10531#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10532#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11629#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10580#L661-39 assume !(1 == ~t5_pc~0); 10211#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 10212#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11572#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11573#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11486#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11487#L680-39 assume 1 == ~t6_pc~0; 10273#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10274#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11416#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10739#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10740#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11754#L699-39 assume 1 == ~t7_pc~0; 11176#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10898#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10899#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11582#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11703#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11701#L718-39 assume 1 == ~t8_pc~0; 11090#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11091#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11023#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11024#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 11326#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11295#L737-39 assume 1 == ~t9_pc~0; 10720#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10721#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11010#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11777#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11678#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11621#L756-39 assume 1 == ~t10_pc~0; 11622#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11103#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10847#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10848#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10980#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10320#L775-39 assume 1 == ~t11_pc~0; 10321#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10973#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10974#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11836#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11384#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11031#L794-39 assume 1 == ~t12_pc~0; 10723#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10717#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11537#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11438#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10262#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10263#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11730#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11731#L1312-3 assume !(1 == ~T2_E~0); 11842#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11456#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11457#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10401#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10372#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10373#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11119#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11244#L1352-3 assume !(1 == ~T10_E~0); 11245#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11684#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11835#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11826#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10199#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10200#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10831#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10832#L1392-3 assume !(1 == ~E_6~0); 11547#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11793#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11210#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10486#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10487#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 11135#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 11136#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 10496#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10497#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11363#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 11215#L1787 assume !(0 == start_simulation_~tmp~3#1); 11216#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11739#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 10467#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11262#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 11263#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10814#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10815#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 10816#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 10366#L1768-2 [2022-02-21 04:24:26,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:26,730 INFO L85 PathProgramCache]: Analyzing trace with hash -1760586097, now seen corresponding path program 1 times [2022-02-21 04:24:26,730 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:26,730 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100848393] [2022-02-21 04:24:26,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:26,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:26,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:26,772 INFO L290 TraceCheckUtils]: 0: Hoare triple {15226#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {15226#true} is VALID [2022-02-21 04:24:26,772 INFO L290 TraceCheckUtils]: 1: Hoare triple {15226#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {15228#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:26,772 INFO L290 TraceCheckUtils]: 2: Hoare triple {15228#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {15228#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:26,773 INFO L290 TraceCheckUtils]: 3: Hoare triple {15228#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {15228#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:26,773 INFO L290 TraceCheckUtils]: 4: Hoare triple {15228#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {15228#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:26,773 INFO L290 TraceCheckUtils]: 5: Hoare triple {15228#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {15228#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:26,774 INFO L290 TraceCheckUtils]: 6: Hoare triple {15228#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,774 INFO L290 TraceCheckUtils]: 7: Hoare triple {15227#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,774 INFO L290 TraceCheckUtils]: 8: Hoare triple {15227#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,774 INFO L290 TraceCheckUtils]: 9: Hoare triple {15227#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,774 INFO L290 TraceCheckUtils]: 10: Hoare triple {15227#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,775 INFO L290 TraceCheckUtils]: 11: Hoare triple {15227#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,775 INFO L290 TraceCheckUtils]: 12: Hoare triple {15227#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,775 INFO L290 TraceCheckUtils]: 13: Hoare triple {15227#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {15227#false} is VALID [2022-02-21 04:24:26,775 INFO L290 TraceCheckUtils]: 14: Hoare triple {15227#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,775 INFO L290 TraceCheckUtils]: 15: Hoare triple {15227#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,775 INFO L290 TraceCheckUtils]: 16: Hoare triple {15227#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,775 INFO L290 TraceCheckUtils]: 17: Hoare triple {15227#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {15227#false} is VALID [2022-02-21 04:24:26,776 INFO L290 TraceCheckUtils]: 18: Hoare triple {15227#false} assume !(0 == ~M_E~0); {15227#false} is VALID [2022-02-21 04:24:26,776 INFO L290 TraceCheckUtils]: 19: Hoare triple {15227#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {15227#false} is VALID [2022-02-21 04:24:26,776 INFO L290 TraceCheckUtils]: 20: Hoare triple {15227#false} assume !(0 == ~T2_E~0); {15227#false} is VALID [2022-02-21 04:24:26,776 INFO L290 TraceCheckUtils]: 21: Hoare triple {15227#false} assume !(0 == ~T3_E~0); {15227#false} is VALID [2022-02-21 04:24:26,776 INFO L290 TraceCheckUtils]: 22: Hoare triple {15227#false} assume !(0 == ~T4_E~0); {15227#false} is VALID [2022-02-21 04:24:26,776 INFO L290 TraceCheckUtils]: 23: Hoare triple {15227#false} assume !(0 == ~T5_E~0); {15227#false} is VALID [2022-02-21 04:24:26,776 INFO L290 TraceCheckUtils]: 24: Hoare triple {15227#false} assume !(0 == ~T6_E~0); {15227#false} is VALID [2022-02-21 04:24:26,776 INFO L290 TraceCheckUtils]: 25: Hoare triple {15227#false} assume !(0 == ~T7_E~0); {15227#false} is VALID [2022-02-21 04:24:26,777 INFO L290 TraceCheckUtils]: 26: Hoare triple {15227#false} assume !(0 == ~T8_E~0); {15227#false} is VALID [2022-02-21 04:24:26,777 INFO L290 TraceCheckUtils]: 27: Hoare triple {15227#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {15227#false} is VALID [2022-02-21 04:24:26,777 INFO L290 TraceCheckUtils]: 28: Hoare triple {15227#false} assume !(0 == ~T10_E~0); {15227#false} is VALID [2022-02-21 04:24:26,777 INFO L290 TraceCheckUtils]: 29: Hoare triple {15227#false} assume !(0 == ~T11_E~0); {15227#false} is VALID [2022-02-21 04:24:26,777 INFO L290 TraceCheckUtils]: 30: Hoare triple {15227#false} assume !(0 == ~T12_E~0); {15227#false} is VALID [2022-02-21 04:24:26,777 INFO L290 TraceCheckUtils]: 31: Hoare triple {15227#false} assume !(0 == ~E_1~0); {15227#false} is VALID [2022-02-21 04:24:26,777 INFO L290 TraceCheckUtils]: 32: Hoare triple {15227#false} assume !(0 == ~E_2~0); {15227#false} is VALID [2022-02-21 04:24:26,778 INFO L290 TraceCheckUtils]: 33: Hoare triple {15227#false} assume !(0 == ~E_3~0); {15227#false} is VALID [2022-02-21 04:24:26,778 INFO L290 TraceCheckUtils]: 34: Hoare triple {15227#false} assume !(0 == ~E_4~0); {15227#false} is VALID [2022-02-21 04:24:26,778 INFO L290 TraceCheckUtils]: 35: Hoare triple {15227#false} assume 0 == ~E_5~0;~E_5~0 := 1; {15227#false} is VALID [2022-02-21 04:24:26,778 INFO L290 TraceCheckUtils]: 36: Hoare triple {15227#false} assume !(0 == ~E_6~0); {15227#false} is VALID [2022-02-21 04:24:26,778 INFO L290 TraceCheckUtils]: 37: Hoare triple {15227#false} assume !(0 == ~E_7~0); {15227#false} is VALID [2022-02-21 04:24:26,778 INFO L290 TraceCheckUtils]: 38: Hoare triple {15227#false} assume !(0 == ~E_8~0); {15227#false} is VALID [2022-02-21 04:24:26,778 INFO L290 TraceCheckUtils]: 39: Hoare triple {15227#false} assume !(0 == ~E_9~0); {15227#false} is VALID [2022-02-21 04:24:26,779 INFO L290 TraceCheckUtils]: 40: Hoare triple {15227#false} assume !(0 == ~E_10~0); {15227#false} is VALID [2022-02-21 04:24:26,779 INFO L290 TraceCheckUtils]: 41: Hoare triple {15227#false} assume !(0 == ~E_11~0); {15227#false} is VALID [2022-02-21 04:24:26,779 INFO L290 TraceCheckUtils]: 42: Hoare triple {15227#false} assume !(0 == ~E_12~0); {15227#false} is VALID [2022-02-21 04:24:26,779 INFO L290 TraceCheckUtils]: 43: Hoare triple {15227#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {15227#false} is VALID [2022-02-21 04:24:26,779 INFO L290 TraceCheckUtils]: 44: Hoare triple {15227#false} assume 1 == ~m_pc~0; {15227#false} is VALID [2022-02-21 04:24:26,779 INFO L290 TraceCheckUtils]: 45: Hoare triple {15227#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {15227#false} is VALID [2022-02-21 04:24:26,779 INFO L290 TraceCheckUtils]: 46: Hoare triple {15227#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {15227#false} is VALID [2022-02-21 04:24:26,780 INFO L290 TraceCheckUtils]: 47: Hoare triple {15227#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {15227#false} is VALID [2022-02-21 04:24:26,780 INFO L290 TraceCheckUtils]: 48: Hoare triple {15227#false} assume !(0 != activate_threads_~tmp~1#1); {15227#false} is VALID [2022-02-21 04:24:26,780 INFO L290 TraceCheckUtils]: 49: Hoare triple {15227#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {15227#false} is VALID [2022-02-21 04:24:26,780 INFO L290 TraceCheckUtils]: 50: Hoare triple {15227#false} assume 1 == ~t1_pc~0; {15227#false} is VALID [2022-02-21 04:24:26,780 INFO L290 TraceCheckUtils]: 51: Hoare triple {15227#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {15227#false} is VALID [2022-02-21 04:24:26,780 INFO L290 TraceCheckUtils]: 52: Hoare triple {15227#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {15227#false} is VALID [2022-02-21 04:24:26,780 INFO L290 TraceCheckUtils]: 53: Hoare triple {15227#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {15227#false} is VALID [2022-02-21 04:24:26,781 INFO L290 TraceCheckUtils]: 54: Hoare triple {15227#false} assume !(0 != activate_threads_~tmp___0~0#1); {15227#false} is VALID [2022-02-21 04:24:26,781 INFO L290 TraceCheckUtils]: 55: Hoare triple {15227#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {15227#false} is VALID [2022-02-21 04:24:26,781 INFO L290 TraceCheckUtils]: 56: Hoare triple {15227#false} assume !(1 == ~t2_pc~0); {15227#false} is VALID [2022-02-21 04:24:26,781 INFO L290 TraceCheckUtils]: 57: Hoare triple {15227#false} is_transmit2_triggered_~__retres1~2#1 := 0; {15227#false} is VALID [2022-02-21 04:24:26,781 INFO L290 TraceCheckUtils]: 58: Hoare triple {15227#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {15227#false} is VALID [2022-02-21 04:24:26,781 INFO L290 TraceCheckUtils]: 59: Hoare triple {15227#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {15227#false} is VALID [2022-02-21 04:24:26,781 INFO L290 TraceCheckUtils]: 60: Hoare triple {15227#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {15227#false} is VALID [2022-02-21 04:24:26,782 INFO L290 TraceCheckUtils]: 61: Hoare triple {15227#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {15227#false} is VALID [2022-02-21 04:24:26,782 INFO L290 TraceCheckUtils]: 62: Hoare triple {15227#false} assume 1 == ~t3_pc~0; {15227#false} is VALID [2022-02-21 04:24:26,782 INFO L290 TraceCheckUtils]: 63: Hoare triple {15227#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {15227#false} is VALID [2022-02-21 04:24:26,782 INFO L290 TraceCheckUtils]: 64: Hoare triple {15227#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {15227#false} is VALID [2022-02-21 04:24:26,782 INFO L290 TraceCheckUtils]: 65: Hoare triple {15227#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {15227#false} is VALID [2022-02-21 04:24:26,782 INFO L290 TraceCheckUtils]: 66: Hoare triple {15227#false} assume !(0 != activate_threads_~tmp___2~0#1); {15227#false} is VALID [2022-02-21 04:24:26,782 INFO L290 TraceCheckUtils]: 67: Hoare triple {15227#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {15227#false} is VALID [2022-02-21 04:24:26,783 INFO L290 TraceCheckUtils]: 68: Hoare triple {15227#false} assume !(1 == ~t4_pc~0); {15227#false} is VALID [2022-02-21 04:24:26,783 INFO L290 TraceCheckUtils]: 69: Hoare triple {15227#false} is_transmit4_triggered_~__retres1~4#1 := 0; {15227#false} is VALID [2022-02-21 04:24:26,783 INFO L290 TraceCheckUtils]: 70: Hoare triple {15227#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {15227#false} is VALID [2022-02-21 04:24:26,783 INFO L290 TraceCheckUtils]: 71: Hoare triple {15227#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {15227#false} is VALID [2022-02-21 04:24:26,783 INFO L290 TraceCheckUtils]: 72: Hoare triple {15227#false} assume !(0 != activate_threads_~tmp___3~0#1); {15227#false} is VALID [2022-02-21 04:24:26,783 INFO L290 TraceCheckUtils]: 73: Hoare triple {15227#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {15227#false} is VALID [2022-02-21 04:24:26,783 INFO L290 TraceCheckUtils]: 74: Hoare triple {15227#false} assume 1 == ~t5_pc~0; {15227#false} is VALID [2022-02-21 04:24:26,784 INFO L290 TraceCheckUtils]: 75: Hoare triple {15227#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {15227#false} is VALID [2022-02-21 04:24:26,784 INFO L290 TraceCheckUtils]: 76: Hoare triple {15227#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {15227#false} is VALID [2022-02-21 04:24:26,784 INFO L290 TraceCheckUtils]: 77: Hoare triple {15227#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {15227#false} is VALID [2022-02-21 04:24:26,784 INFO L290 TraceCheckUtils]: 78: Hoare triple {15227#false} assume !(0 != activate_threads_~tmp___4~0#1); {15227#false} is VALID [2022-02-21 04:24:26,784 INFO L290 TraceCheckUtils]: 79: Hoare triple {15227#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {15227#false} is VALID [2022-02-21 04:24:26,784 INFO L290 TraceCheckUtils]: 80: Hoare triple {15227#false} assume !(1 == ~t6_pc~0); {15227#false} is VALID [2022-02-21 04:24:26,784 INFO L290 TraceCheckUtils]: 81: Hoare triple {15227#false} is_transmit6_triggered_~__retres1~6#1 := 0; {15227#false} is VALID [2022-02-21 04:24:26,785 INFO L290 TraceCheckUtils]: 82: Hoare triple {15227#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {15227#false} is VALID [2022-02-21 04:24:26,785 INFO L290 TraceCheckUtils]: 83: Hoare triple {15227#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {15227#false} is VALID [2022-02-21 04:24:26,785 INFO L290 TraceCheckUtils]: 84: Hoare triple {15227#false} assume !(0 != activate_threads_~tmp___5~0#1); {15227#false} is VALID [2022-02-21 04:24:26,785 INFO L290 TraceCheckUtils]: 85: Hoare triple {15227#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {15227#false} is VALID [2022-02-21 04:24:26,785 INFO L290 TraceCheckUtils]: 86: Hoare triple {15227#false} assume 1 == ~t7_pc~0; {15227#false} is VALID [2022-02-21 04:24:26,785 INFO L290 TraceCheckUtils]: 87: Hoare triple {15227#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {15227#false} is VALID [2022-02-21 04:24:26,785 INFO L290 TraceCheckUtils]: 88: Hoare triple {15227#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {15227#false} is VALID [2022-02-21 04:24:26,786 INFO L290 TraceCheckUtils]: 89: Hoare triple {15227#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {15227#false} is VALID [2022-02-21 04:24:26,786 INFO L290 TraceCheckUtils]: 90: Hoare triple {15227#false} assume !(0 != activate_threads_~tmp___6~0#1); {15227#false} is VALID [2022-02-21 04:24:26,786 INFO L290 TraceCheckUtils]: 91: Hoare triple {15227#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {15227#false} is VALID [2022-02-21 04:24:26,786 INFO L290 TraceCheckUtils]: 92: Hoare triple {15227#false} assume !(1 == ~t8_pc~0); {15227#false} is VALID [2022-02-21 04:24:26,786 INFO L290 TraceCheckUtils]: 93: Hoare triple {15227#false} is_transmit8_triggered_~__retres1~8#1 := 0; {15227#false} is VALID [2022-02-21 04:24:26,786 INFO L290 TraceCheckUtils]: 94: Hoare triple {15227#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {15227#false} is VALID [2022-02-21 04:24:26,786 INFO L290 TraceCheckUtils]: 95: Hoare triple {15227#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {15227#false} is VALID [2022-02-21 04:24:26,787 INFO L290 TraceCheckUtils]: 96: Hoare triple {15227#false} assume !(0 != activate_threads_~tmp___7~0#1); {15227#false} is VALID [2022-02-21 04:24:26,787 INFO L290 TraceCheckUtils]: 97: Hoare triple {15227#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {15227#false} is VALID [2022-02-21 04:24:26,787 INFO L290 TraceCheckUtils]: 98: Hoare triple {15227#false} assume 1 == ~t9_pc~0; {15227#false} is VALID [2022-02-21 04:24:26,787 INFO L290 TraceCheckUtils]: 99: Hoare triple {15227#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {15227#false} is VALID [2022-02-21 04:24:26,787 INFO L290 TraceCheckUtils]: 100: Hoare triple {15227#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {15227#false} is VALID [2022-02-21 04:24:26,787 INFO L290 TraceCheckUtils]: 101: Hoare triple {15227#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {15227#false} is VALID [2022-02-21 04:24:26,787 INFO L290 TraceCheckUtils]: 102: Hoare triple {15227#false} assume !(0 != activate_threads_~tmp___8~0#1); {15227#false} is VALID [2022-02-21 04:24:26,788 INFO L290 TraceCheckUtils]: 103: Hoare triple {15227#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {15227#false} is VALID [2022-02-21 04:24:26,788 INFO L290 TraceCheckUtils]: 104: Hoare triple {15227#false} assume 1 == ~t10_pc~0; {15227#false} is VALID [2022-02-21 04:24:26,788 INFO L290 TraceCheckUtils]: 105: Hoare triple {15227#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {15227#false} is VALID [2022-02-21 04:24:26,788 INFO L290 TraceCheckUtils]: 106: Hoare triple {15227#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {15227#false} is VALID [2022-02-21 04:24:26,788 INFO L290 TraceCheckUtils]: 107: Hoare triple {15227#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {15227#false} is VALID [2022-02-21 04:24:26,788 INFO L290 TraceCheckUtils]: 108: Hoare triple {15227#false} assume !(0 != activate_threads_~tmp___9~0#1); {15227#false} is VALID [2022-02-21 04:24:26,788 INFO L290 TraceCheckUtils]: 109: Hoare triple {15227#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {15227#false} is VALID [2022-02-21 04:24:26,789 INFO L290 TraceCheckUtils]: 110: Hoare triple {15227#false} assume !(1 == ~t11_pc~0); {15227#false} is VALID [2022-02-21 04:24:26,789 INFO L290 TraceCheckUtils]: 111: Hoare triple {15227#false} is_transmit11_triggered_~__retres1~11#1 := 0; {15227#false} is VALID [2022-02-21 04:24:26,789 INFO L290 TraceCheckUtils]: 112: Hoare triple {15227#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {15227#false} is VALID [2022-02-21 04:24:26,789 INFO L290 TraceCheckUtils]: 113: Hoare triple {15227#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {15227#false} is VALID [2022-02-21 04:24:26,789 INFO L290 TraceCheckUtils]: 114: Hoare triple {15227#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {15227#false} is VALID [2022-02-21 04:24:26,789 INFO L290 TraceCheckUtils]: 115: Hoare triple {15227#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {15227#false} is VALID [2022-02-21 04:24:26,789 INFO L290 TraceCheckUtils]: 116: Hoare triple {15227#false} assume 1 == ~t12_pc~0; {15227#false} is VALID [2022-02-21 04:24:26,790 INFO L290 TraceCheckUtils]: 117: Hoare triple {15227#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {15227#false} is VALID [2022-02-21 04:24:26,790 INFO L290 TraceCheckUtils]: 118: Hoare triple {15227#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {15227#false} is VALID [2022-02-21 04:24:26,790 INFO L290 TraceCheckUtils]: 119: Hoare triple {15227#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {15227#false} is VALID [2022-02-21 04:24:26,790 INFO L290 TraceCheckUtils]: 120: Hoare triple {15227#false} assume !(0 != activate_threads_~tmp___11~0#1); {15227#false} is VALID [2022-02-21 04:24:26,790 INFO L290 TraceCheckUtils]: 121: Hoare triple {15227#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {15227#false} is VALID [2022-02-21 04:24:26,790 INFO L290 TraceCheckUtils]: 122: Hoare triple {15227#false} assume !(1 == ~M_E~0); {15227#false} is VALID [2022-02-21 04:24:26,790 INFO L290 TraceCheckUtils]: 123: Hoare triple {15227#false} assume !(1 == ~T1_E~0); {15227#false} is VALID [2022-02-21 04:24:26,791 INFO L290 TraceCheckUtils]: 124: Hoare triple {15227#false} assume !(1 == ~T2_E~0); {15227#false} is VALID [2022-02-21 04:24:26,791 INFO L290 TraceCheckUtils]: 125: Hoare triple {15227#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,791 INFO L290 TraceCheckUtils]: 126: Hoare triple {15227#false} assume !(1 == ~T4_E~0); {15227#false} is VALID [2022-02-21 04:24:26,791 INFO L290 TraceCheckUtils]: 127: Hoare triple {15227#false} assume !(1 == ~T5_E~0); {15227#false} is VALID [2022-02-21 04:24:26,791 INFO L290 TraceCheckUtils]: 128: Hoare triple {15227#false} assume !(1 == ~T6_E~0); {15227#false} is VALID [2022-02-21 04:24:26,791 INFO L290 TraceCheckUtils]: 129: Hoare triple {15227#false} assume !(1 == ~T7_E~0); {15227#false} is VALID [2022-02-21 04:24:26,791 INFO L290 TraceCheckUtils]: 130: Hoare triple {15227#false} assume !(1 == ~T8_E~0); {15227#false} is VALID [2022-02-21 04:24:26,792 INFO L290 TraceCheckUtils]: 131: Hoare triple {15227#false} assume !(1 == ~T9_E~0); {15227#false} is VALID [2022-02-21 04:24:26,792 INFO L290 TraceCheckUtils]: 132: Hoare triple {15227#false} assume !(1 == ~T10_E~0); {15227#false} is VALID [2022-02-21 04:24:26,792 INFO L290 TraceCheckUtils]: 133: Hoare triple {15227#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,792 INFO L290 TraceCheckUtils]: 134: Hoare triple {15227#false} assume !(1 == ~T12_E~0); {15227#false} is VALID [2022-02-21 04:24:26,792 INFO L290 TraceCheckUtils]: 135: Hoare triple {15227#false} assume !(1 == ~E_1~0); {15227#false} is VALID [2022-02-21 04:24:26,792 INFO L290 TraceCheckUtils]: 136: Hoare triple {15227#false} assume !(1 == ~E_2~0); {15227#false} is VALID [2022-02-21 04:24:26,792 INFO L290 TraceCheckUtils]: 137: Hoare triple {15227#false} assume !(1 == ~E_3~0); {15227#false} is VALID [2022-02-21 04:24:26,793 INFO L290 TraceCheckUtils]: 138: Hoare triple {15227#false} assume !(1 == ~E_4~0); {15227#false} is VALID [2022-02-21 04:24:26,793 INFO L290 TraceCheckUtils]: 139: Hoare triple {15227#false} assume !(1 == ~E_5~0); {15227#false} is VALID [2022-02-21 04:24:26,793 INFO L290 TraceCheckUtils]: 140: Hoare triple {15227#false} assume !(1 == ~E_6~0); {15227#false} is VALID [2022-02-21 04:24:26,793 INFO L290 TraceCheckUtils]: 141: Hoare triple {15227#false} assume 1 == ~E_7~0;~E_7~0 := 2; {15227#false} is VALID [2022-02-21 04:24:26,793 INFO L290 TraceCheckUtils]: 142: Hoare triple {15227#false} assume !(1 == ~E_8~0); {15227#false} is VALID [2022-02-21 04:24:26,793 INFO L290 TraceCheckUtils]: 143: Hoare triple {15227#false} assume !(1 == ~E_9~0); {15227#false} is VALID [2022-02-21 04:24:26,793 INFO L290 TraceCheckUtils]: 144: Hoare triple {15227#false} assume !(1 == ~E_10~0); {15227#false} is VALID [2022-02-21 04:24:26,794 INFO L290 TraceCheckUtils]: 145: Hoare triple {15227#false} assume !(1 == ~E_11~0); {15227#false} is VALID [2022-02-21 04:24:26,794 INFO L290 TraceCheckUtils]: 146: Hoare triple {15227#false} assume !(1 == ~E_12~0); {15227#false} is VALID [2022-02-21 04:24:26,794 INFO L290 TraceCheckUtils]: 147: Hoare triple {15227#false} assume { :end_inline_reset_delta_events } true; {15227#false} is VALID [2022-02-21 04:24:26,794 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:26,794 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:26,795 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [100848393] [2022-02-21 04:24:26,795 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [100848393] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:26,795 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:26,795 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:26,795 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782123242] [2022-02-21 04:24:26,795 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:26,796 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:26,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:26,796 INFO L85 PathProgramCache]: Analyzing trace with hash -2002386077, now seen corresponding path program 1 times [2022-02-21 04:24:26,796 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:26,797 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752378456] [2022-02-21 04:24:26,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:26,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:26,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:26,843 INFO L290 TraceCheckUtils]: 0: Hoare triple {15229#true} assume !false; {15229#true} is VALID [2022-02-21 04:24:26,843 INFO L290 TraceCheckUtils]: 1: Hoare triple {15229#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {15229#true} is VALID [2022-02-21 04:24:26,844 INFO L290 TraceCheckUtils]: 2: Hoare triple {15229#true} assume !false; {15229#true} is VALID [2022-02-21 04:24:26,844 INFO L290 TraceCheckUtils]: 3: Hoare triple {15229#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {15229#true} is VALID [2022-02-21 04:24:26,844 INFO L290 TraceCheckUtils]: 4: Hoare triple {15229#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {15229#true} is VALID [2022-02-21 04:24:26,844 INFO L290 TraceCheckUtils]: 5: Hoare triple {15229#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {15229#true} is VALID [2022-02-21 04:24:26,844 INFO L290 TraceCheckUtils]: 6: Hoare triple {15229#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {15229#true} is VALID [2022-02-21 04:24:26,844 INFO L290 TraceCheckUtils]: 7: Hoare triple {15229#true} assume !(0 != eval_~tmp~0#1); {15229#true} is VALID [2022-02-21 04:24:26,844 INFO L290 TraceCheckUtils]: 8: Hoare triple {15229#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {15229#true} is VALID [2022-02-21 04:24:26,845 INFO L290 TraceCheckUtils]: 9: Hoare triple {15229#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {15229#true} is VALID [2022-02-21 04:24:26,845 INFO L290 TraceCheckUtils]: 10: Hoare triple {15229#true} assume !(0 == ~M_E~0); {15229#true} is VALID [2022-02-21 04:24:26,845 INFO L290 TraceCheckUtils]: 11: Hoare triple {15229#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {15229#true} is VALID [2022-02-21 04:24:26,845 INFO L290 TraceCheckUtils]: 12: Hoare triple {15229#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,846 INFO L290 TraceCheckUtils]: 13: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,846 INFO L290 TraceCheckUtils]: 14: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,846 INFO L290 TraceCheckUtils]: 15: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,847 INFO L290 TraceCheckUtils]: 16: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,847 INFO L290 TraceCheckUtils]: 17: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,847 INFO L290 TraceCheckUtils]: 18: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,848 INFO L290 TraceCheckUtils]: 19: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,848 INFO L290 TraceCheckUtils]: 20: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,848 INFO L290 TraceCheckUtils]: 21: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,849 INFO L290 TraceCheckUtils]: 22: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,849 INFO L290 TraceCheckUtils]: 23: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,849 INFO L290 TraceCheckUtils]: 24: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,850 INFO L290 TraceCheckUtils]: 25: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,850 INFO L290 TraceCheckUtils]: 26: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,850 INFO L290 TraceCheckUtils]: 27: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,850 INFO L290 TraceCheckUtils]: 28: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,851 INFO L290 TraceCheckUtils]: 29: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,851 INFO L290 TraceCheckUtils]: 30: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,851 INFO L290 TraceCheckUtils]: 31: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,852 INFO L290 TraceCheckUtils]: 32: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,852 INFO L290 TraceCheckUtils]: 33: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,852 INFO L290 TraceCheckUtils]: 34: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,853 INFO L290 TraceCheckUtils]: 35: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,853 INFO L290 TraceCheckUtils]: 36: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,853 INFO L290 TraceCheckUtils]: 37: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,853 INFO L290 TraceCheckUtils]: 38: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,854 INFO L290 TraceCheckUtils]: 39: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,854 INFO L290 TraceCheckUtils]: 40: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,854 INFO L290 TraceCheckUtils]: 41: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,855 INFO L290 TraceCheckUtils]: 42: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,855 INFO L290 TraceCheckUtils]: 43: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,855 INFO L290 TraceCheckUtils]: 44: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,855 INFO L290 TraceCheckUtils]: 45: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,856 INFO L290 TraceCheckUtils]: 46: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,856 INFO L290 TraceCheckUtils]: 47: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,856 INFO L290 TraceCheckUtils]: 48: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,857 INFO L290 TraceCheckUtils]: 49: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,857 INFO L290 TraceCheckUtils]: 50: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,857 INFO L290 TraceCheckUtils]: 51: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,858 INFO L290 TraceCheckUtils]: 52: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,858 INFO L290 TraceCheckUtils]: 53: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,858 INFO L290 TraceCheckUtils]: 54: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,859 INFO L290 TraceCheckUtils]: 55: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,859 INFO L290 TraceCheckUtils]: 56: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,859 INFO L290 TraceCheckUtils]: 57: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,860 INFO L290 TraceCheckUtils]: 58: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,860 INFO L290 TraceCheckUtils]: 59: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,860 INFO L290 TraceCheckUtils]: 60: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,861 INFO L290 TraceCheckUtils]: 61: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,861 INFO L290 TraceCheckUtils]: 62: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,861 INFO L290 TraceCheckUtils]: 63: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,862 INFO L290 TraceCheckUtils]: 64: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,862 INFO L290 TraceCheckUtils]: 65: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,862 INFO L290 TraceCheckUtils]: 66: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,863 INFO L290 TraceCheckUtils]: 67: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,863 INFO L290 TraceCheckUtils]: 68: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,863 INFO L290 TraceCheckUtils]: 69: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,864 INFO L290 TraceCheckUtils]: 70: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,864 INFO L290 TraceCheckUtils]: 71: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,864 INFO L290 TraceCheckUtils]: 72: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,865 INFO L290 TraceCheckUtils]: 73: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,865 INFO L290 TraceCheckUtils]: 74: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,865 INFO L290 TraceCheckUtils]: 75: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,866 INFO L290 TraceCheckUtils]: 76: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,866 INFO L290 TraceCheckUtils]: 77: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,866 INFO L290 TraceCheckUtils]: 78: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,867 INFO L290 TraceCheckUtils]: 79: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,867 INFO L290 TraceCheckUtils]: 80: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,867 INFO L290 TraceCheckUtils]: 81: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,868 INFO L290 TraceCheckUtils]: 82: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,868 INFO L290 TraceCheckUtils]: 83: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,868 INFO L290 TraceCheckUtils]: 84: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,868 INFO L290 TraceCheckUtils]: 85: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,869 INFO L290 TraceCheckUtils]: 86: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,869 INFO L290 TraceCheckUtils]: 87: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,869 INFO L290 TraceCheckUtils]: 88: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,870 INFO L290 TraceCheckUtils]: 89: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,870 INFO L290 TraceCheckUtils]: 90: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,870 INFO L290 TraceCheckUtils]: 91: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,871 INFO L290 TraceCheckUtils]: 92: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,871 INFO L290 TraceCheckUtils]: 93: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,871 INFO L290 TraceCheckUtils]: 94: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,872 INFO L290 TraceCheckUtils]: 95: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,872 INFO L290 TraceCheckUtils]: 96: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,872 INFO L290 TraceCheckUtils]: 97: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,873 INFO L290 TraceCheckUtils]: 98: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,873 INFO L290 TraceCheckUtils]: 99: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,873 INFO L290 TraceCheckUtils]: 100: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,874 INFO L290 TraceCheckUtils]: 101: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,874 INFO L290 TraceCheckUtils]: 102: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,874 INFO L290 TraceCheckUtils]: 103: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,875 INFO L290 TraceCheckUtils]: 104: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,875 INFO L290 TraceCheckUtils]: 105: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,875 INFO L290 TraceCheckUtils]: 106: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,876 INFO L290 TraceCheckUtils]: 107: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,876 INFO L290 TraceCheckUtils]: 108: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t12_pc~0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,876 INFO L290 TraceCheckUtils]: 109: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,877 INFO L290 TraceCheckUtils]: 110: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,877 INFO L290 TraceCheckUtils]: 111: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,877 INFO L290 TraceCheckUtils]: 112: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,878 INFO L290 TraceCheckUtils]: 113: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,878 INFO L290 TraceCheckUtils]: 114: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,878 INFO L290 TraceCheckUtils]: 115: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {15231#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:26,879 INFO L290 TraceCheckUtils]: 116: Hoare triple {15231#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {15230#false} is VALID [2022-02-21 04:24:26,879 INFO L290 TraceCheckUtils]: 117: Hoare triple {15230#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,879 INFO L290 TraceCheckUtils]: 118: Hoare triple {15230#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,879 INFO L290 TraceCheckUtils]: 119: Hoare triple {15230#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,879 INFO L290 TraceCheckUtils]: 120: Hoare triple {15230#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,879 INFO L290 TraceCheckUtils]: 121: Hoare triple {15230#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,880 INFO L290 TraceCheckUtils]: 122: Hoare triple {15230#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,880 INFO L290 TraceCheckUtils]: 123: Hoare triple {15230#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,880 INFO L290 TraceCheckUtils]: 124: Hoare triple {15230#false} assume !(1 == ~T10_E~0); {15230#false} is VALID [2022-02-21 04:24:26,880 INFO L290 TraceCheckUtils]: 125: Hoare triple {15230#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,880 INFO L290 TraceCheckUtils]: 126: Hoare triple {15230#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,880 INFO L290 TraceCheckUtils]: 127: Hoare triple {15230#false} assume 1 == ~E_1~0;~E_1~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,880 INFO L290 TraceCheckUtils]: 128: Hoare triple {15230#false} assume 1 == ~E_2~0;~E_2~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,880 INFO L290 TraceCheckUtils]: 129: Hoare triple {15230#false} assume 1 == ~E_3~0;~E_3~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,881 INFO L290 TraceCheckUtils]: 130: Hoare triple {15230#false} assume 1 == ~E_4~0;~E_4~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,881 INFO L290 TraceCheckUtils]: 131: Hoare triple {15230#false} assume 1 == ~E_5~0;~E_5~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,881 INFO L290 TraceCheckUtils]: 132: Hoare triple {15230#false} assume !(1 == ~E_6~0); {15230#false} is VALID [2022-02-21 04:24:26,881 INFO L290 TraceCheckUtils]: 133: Hoare triple {15230#false} assume 1 == ~E_7~0;~E_7~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,881 INFO L290 TraceCheckUtils]: 134: Hoare triple {15230#false} assume 1 == ~E_8~0;~E_8~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,881 INFO L290 TraceCheckUtils]: 135: Hoare triple {15230#false} assume 1 == ~E_9~0;~E_9~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,881 INFO L290 TraceCheckUtils]: 136: Hoare triple {15230#false} assume 1 == ~E_10~0;~E_10~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,882 INFO L290 TraceCheckUtils]: 137: Hoare triple {15230#false} assume 1 == ~E_11~0;~E_11~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,882 INFO L290 TraceCheckUtils]: 138: Hoare triple {15230#false} assume 1 == ~E_12~0;~E_12~0 := 2; {15230#false} is VALID [2022-02-21 04:24:26,882 INFO L290 TraceCheckUtils]: 139: Hoare triple {15230#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {15230#false} is VALID [2022-02-21 04:24:26,882 INFO L290 TraceCheckUtils]: 140: Hoare triple {15230#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {15230#false} is VALID [2022-02-21 04:24:26,882 INFO L290 TraceCheckUtils]: 141: Hoare triple {15230#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {15230#false} is VALID [2022-02-21 04:24:26,882 INFO L290 TraceCheckUtils]: 142: Hoare triple {15230#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {15230#false} is VALID [2022-02-21 04:24:26,882 INFO L290 TraceCheckUtils]: 143: Hoare triple {15230#false} assume !(0 == start_simulation_~tmp~3#1); {15230#false} is VALID [2022-02-21 04:24:26,883 INFO L290 TraceCheckUtils]: 144: Hoare triple {15230#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {15230#false} is VALID [2022-02-21 04:24:26,883 INFO L290 TraceCheckUtils]: 145: Hoare triple {15230#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {15230#false} is VALID [2022-02-21 04:24:26,883 INFO L290 TraceCheckUtils]: 146: Hoare triple {15230#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {15230#false} is VALID [2022-02-21 04:24:26,883 INFO L290 TraceCheckUtils]: 147: Hoare triple {15230#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {15230#false} is VALID [2022-02-21 04:24:26,883 INFO L290 TraceCheckUtils]: 148: Hoare triple {15230#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {15230#false} is VALID [2022-02-21 04:24:26,883 INFO L290 TraceCheckUtils]: 149: Hoare triple {15230#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {15230#false} is VALID [2022-02-21 04:24:26,883 INFO L290 TraceCheckUtils]: 150: Hoare triple {15230#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {15230#false} is VALID [2022-02-21 04:24:26,884 INFO L290 TraceCheckUtils]: 151: Hoare triple {15230#false} assume !(0 != start_simulation_~tmp___0~1#1); {15230#false} is VALID [2022-02-21 04:24:26,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:26,884 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:26,885 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752378456] [2022-02-21 04:24:26,885 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [752378456] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:26,885 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:26,885 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:26,885 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502959356] [2022-02-21 04:24:26,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:26,886 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:26,886 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:26,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:26,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:26,887 INFO L87 Difference]: Start difference. First operand 1688 states and 2503 transitions. cyclomatic complexity: 816 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,114 INFO L93 Difference]: Finished difference Result 1688 states and 2502 transitions. [2022-02-21 04:24:28,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:28,115 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,203 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:28,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2502 transitions. [2022-02-21 04:24:28,312 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:28,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2502 transitions. [2022-02-21 04:24:28,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:28,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:28,424 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2502 transitions. [2022-02-21 04:24:28,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:28,427 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2022-02-21 04:24:28,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2502 transitions. [2022-02-21 04:24:28,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:28,446 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:28,449 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2502 transitions. Second operand has 1688 states, 1688 states have (on average 1.4822274881516588) internal successors, (2502), 1687 states have internal predecessors, (2502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,452 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2502 transitions. Second operand has 1688 states, 1688 states have (on average 1.4822274881516588) internal successors, (2502), 1687 states have internal predecessors, (2502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,454 INFO L87 Difference]: Start difference. First operand 1688 states and 2502 transitions. Second operand has 1688 states, 1688 states have (on average 1.4822274881516588) internal successors, (2502), 1687 states have internal predecessors, (2502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,562 INFO L93 Difference]: Finished difference Result 1688 states and 2502 transitions. [2022-02-21 04:24:28,563 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2502 transitions. [2022-02-21 04:24:28,565 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:28,565 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:28,569 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.4822274881516588) internal successors, (2502), 1687 states have internal predecessors, (2502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2502 transitions. [2022-02-21 04:24:28,571 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.4822274881516588) internal successors, (2502), 1687 states have internal predecessors, (2502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2502 transitions. [2022-02-21 04:24:28,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,683 INFO L93 Difference]: Finished difference Result 1688 states and 2502 transitions. [2022-02-21 04:24:28,683 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2502 transitions. [2022-02-21 04:24:28,686 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:28,686 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:28,686 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:28,686 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:28,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4822274881516588) internal successors, (2502), 1687 states have internal predecessors, (2502), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2502 transitions. [2022-02-21 04:24:28,797 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2022-02-21 04:24:28,797 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2502 transitions. [2022-02-21 04:24:28,797 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:28,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2502 transitions. [2022-02-21 04:24:28,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:28,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:28,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:28,805 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:28,806 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:28,806 INFO L791 eck$LassoCheckResult]: Stem: 17723#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 17724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18577#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18071#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17876#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 17877#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17962#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18263#L831-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 18385#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18386#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17174#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17175#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18323#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17769#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17770#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17676#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17677#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18066#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17418#L1174 assume !(0 == ~M_E~0); 17419#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17270#L1179-1 assume !(0 == ~T2_E~0); 17172#L1184-1 assume !(0 == ~T3_E~0); 17173#L1189-1 assume !(0 == ~T4_E~0); 17211#L1194-1 assume !(0 == ~T5_E~0); 17311#L1199-1 assume !(0 == ~T6_E~0); 18206#L1204-1 assume !(0 == ~T7_E~0); 18125#L1209-1 assume !(0 == ~T8_E~0); 18126#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18514#L1219-1 assume !(0 == ~T10_E~0); 18599#L1224-1 assume !(0 == ~T11_E~0); 17536#L1229-1 assume !(0 == ~T12_E~0); 17097#L1234-1 assume !(0 == ~E_1~0); 17098#L1239-1 assume !(0 == ~E_2~0); 17133#L1244-1 assume !(0 == ~E_3~0); 17134#L1249-1 assume !(0 == ~E_4~0); 17793#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17027#L1259-1 assume !(0 == ~E_6~0); 16982#L1264-1 assume !(0 == ~E_7~0); 16983#L1269-1 assume !(0 == ~E_8~0); 18604#L1274-1 assume !(0 == ~E_9~0); 18539#L1279-1 assume !(0 == ~E_10~0); 17215#L1284-1 assume !(0 == ~E_11~0); 17216#L1289-1 assume !(0 == ~E_12~0); 17845#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17846#L566 assume 1 == ~m_pc~0; 16999#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17000#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18154#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18155#L1455 assume !(0 != activate_threads_~tmp~1#1); 17445#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17446#L585 assume 1 == ~t1_pc~0; 17094#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17095#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18095#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18096#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 18564#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18562#L604 assume !(1 == ~t2_pc~0); 18174#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18175#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17708#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17709#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18348#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18349#L623 assume 1 == ~t3_pc~0; 17623#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16963#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17773#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17774#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 18381#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16996#L642 assume !(1 == ~t4_pc~0); 16997#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 17462#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17463#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17068#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 17069#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18186#L661 assume 1 == ~t5_pc~0; 17233#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17234#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17195#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17196#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 18217#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18218#L680 assume !(1 == ~t6_pc~0); 17656#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17657#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17918#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17919#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 18447#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18560#L699 assume 1 == ~t7_pc~0; 18046#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18047#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17223#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17224#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 17948#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17847#L718 assume !(1 == ~t8_pc~0); 17848#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 17209#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17210#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17251#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 17252#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17385#L737 assume 1 == ~t9_pc~0; 18251#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17520#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18121#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18122#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 17694#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17695#L756 assume 1 == ~t10_pc~0; 18274#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17940#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16926#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16927#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 17502#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17503#L775 assume !(1 == ~t11_pc~0); 17757#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 17758#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17379#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17143#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17144#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17330#L794 assume 1 == ~t12_pc~0; 17171#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17148#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18341#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17298#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 17299#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17776#L1307 assume !(1 == ~M_E~0); 17777#L1307-2 assume !(1 == ~T1_E~0); 17888#L1312-1 assume !(1 == ~T2_E~0); 17807#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17808#L1322-1 assume !(1 == ~T4_E~0); 17511#L1327-1 assume !(1 == ~T5_E~0); 17512#L1332-1 assume !(1 == ~T6_E~0); 18050#L1337-1 assume !(1 == ~T7_E~0); 18012#L1342-1 assume !(1 == ~T8_E~0); 18013#L1347-1 assume !(1 == ~T9_E~0); 18410#L1352-1 assume !(1 == ~T10_E~0); 18283#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17674#L1362-1 assume !(1 == ~T12_E~0); 17675#L1367-1 assume !(1 == ~E_1~0); 17312#L1372-1 assume !(1 == ~E_2~0); 17313#L1377-1 assume !(1 == ~E_3~0); 17606#L1382-1 assume !(1 == ~E_4~0); 17607#L1387-1 assume !(1 == ~E_5~0); 18176#L1392-1 assume !(1 == ~E_6~0); 17628#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 17629#L1402-1 assume !(1 == ~E_8~0); 17325#L1407-1 assume !(1 == ~E_9~0); 17326#L1412-1 assume !(1 == ~E_10~0); 18339#L1417-1 assume !(1 == ~E_11~0); 18340#L1422-1 assume !(1 == ~E_12~0); 18558#L1427-1 assume { :end_inline_reset_delta_events } true; 17127#L1768-2 [2022-02-21 04:24:28,806 INFO L793 eck$LassoCheckResult]: Loop: 17127#L1768-2 assume !false; 17128#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17866#L1149 assume !false; 18238#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18391#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17517#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 17423#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17424#L976 assume !(0 != eval_~tmp~0#1); 18557#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18567#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18358#L1174-3 assume !(0 == ~M_E~0); 18351#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18100#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18101#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18285#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17935#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17288#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17289#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17527#L1209-3 assume !(0 == ~T8_E~0); 16947#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16948#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17706#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17707#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17725#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17135#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17136#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17579#L1249-3 assume !(0 == ~E_4~0); 18038#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18510#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18152#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17141#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17142#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18537#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17704#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 17705#L1289-3 assume !(0 == ~E_12~0); 17693#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17369#L566-39 assume 1 == ~m_pc~0; 17370#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17972#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17684#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17685#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18227#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18228#L585-39 assume !(1 == ~t1_pc~0); 17377#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 17378#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17453#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17454#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18260#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17953#L604-39 assume 1 == ~t2_pc~0; 17954#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17585#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17586#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18005#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18006#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17568#L623-39 assume 1 == ~t3_pc~0; 16966#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16968#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18244#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17420#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17421#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18192#L642-39 assume 1 == ~t4_pc~0; 17765#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17766#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17292#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17293#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18390#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17343#L661-39 assume 1 == ~t5_pc~0; 17344#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16973#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18333#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18334#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18248#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18249#L680-39 assume 1 == ~t6_pc~0; 17036#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17037#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18177#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17500#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17501#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18515#L699-39 assume 1 == ~t7_pc~0; 17937#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17659#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17660#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18343#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18463#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18461#L718-39 assume 1 == ~t8_pc~0; 17851#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17852#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17784#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17785#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 18086#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18056#L737-39 assume 1 == ~t9_pc~0; 17481#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17482#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17771#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18538#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18439#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18382#L756-39 assume !(1 == ~t10_pc~0); 17863#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 17864#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17608#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17609#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17741#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17081#L775-39 assume 1 == ~t11_pc~0; 17082#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17734#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17735#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18597#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18145#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17792#L794-39 assume !(1 == ~t12_pc~0); 17477#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 17478#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18298#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18199#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17023#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17024#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18491#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18492#L1312-3 assume !(1 == ~T2_E~0); 18603#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18215#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18216#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17160#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17131#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17132#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17880#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18003#L1352-3 assume !(1 == ~T10_E~0); 18004#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18444#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18596#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18587#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16957#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16958#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17592#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17593#L1392-3 assume !(1 == ~E_6~0); 18308#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18554#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17971#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17247#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17248#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17894#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17895#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 17257#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17258#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18124#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 17975#L1787 assume !(0 == start_simulation_~tmp~3#1); 17976#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 18500#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 17228#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 18023#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 18024#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17575#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17576#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 17577#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 17127#L1768-2 [2022-02-21 04:24:28,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:28,807 INFO L85 PathProgramCache]: Analyzing trace with hash -1220156591, now seen corresponding path program 1 times [2022-02-21 04:24:28,808 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:28,808 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322917475] [2022-02-21 04:24:28,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:28,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:28,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:28,838 INFO L290 TraceCheckUtils]: 0: Hoare triple {21987#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {21987#true} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 1: Hoare triple {21987#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {21989#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 2: Hoare triple {21989#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {21989#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:28,839 INFO L290 TraceCheckUtils]: 3: Hoare triple {21989#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {21989#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 4: Hoare triple {21989#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {21989#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 5: Hoare triple {21989#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {21989#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:28,840 INFO L290 TraceCheckUtils]: 6: Hoare triple {21989#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {21989#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 7: Hoare triple {21989#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 8: Hoare triple {21988#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 9: Hoare triple {21988#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 10: Hoare triple {21988#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 11: Hoare triple {21988#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 12: Hoare triple {21988#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,841 INFO L290 TraceCheckUtils]: 13: Hoare triple {21988#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {21988#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 14: Hoare triple {21988#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 15: Hoare triple {21988#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 16: Hoare triple {21988#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 17: Hoare triple {21988#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {21988#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 18: Hoare triple {21988#false} assume !(0 == ~M_E~0); {21988#false} is VALID [2022-02-21 04:24:28,842 INFO L290 TraceCheckUtils]: 19: Hoare triple {21988#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {21988#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 20: Hoare triple {21988#false} assume !(0 == ~T2_E~0); {21988#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 21: Hoare triple {21988#false} assume !(0 == ~T3_E~0); {21988#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 22: Hoare triple {21988#false} assume !(0 == ~T4_E~0); {21988#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 23: Hoare triple {21988#false} assume !(0 == ~T5_E~0); {21988#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 24: Hoare triple {21988#false} assume !(0 == ~T6_E~0); {21988#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 25: Hoare triple {21988#false} assume !(0 == ~T7_E~0); {21988#false} is VALID [2022-02-21 04:24:28,843 INFO L290 TraceCheckUtils]: 26: Hoare triple {21988#false} assume !(0 == ~T8_E~0); {21988#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 27: Hoare triple {21988#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {21988#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 28: Hoare triple {21988#false} assume !(0 == ~T10_E~0); {21988#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 29: Hoare triple {21988#false} assume !(0 == ~T11_E~0); {21988#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 30: Hoare triple {21988#false} assume !(0 == ~T12_E~0); {21988#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 31: Hoare triple {21988#false} assume !(0 == ~E_1~0); {21988#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 32: Hoare triple {21988#false} assume !(0 == ~E_2~0); {21988#false} is VALID [2022-02-21 04:24:28,844 INFO L290 TraceCheckUtils]: 33: Hoare triple {21988#false} assume !(0 == ~E_3~0); {21988#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 34: Hoare triple {21988#false} assume !(0 == ~E_4~0); {21988#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 35: Hoare triple {21988#false} assume 0 == ~E_5~0;~E_5~0 := 1; {21988#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 36: Hoare triple {21988#false} assume !(0 == ~E_6~0); {21988#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 37: Hoare triple {21988#false} assume !(0 == ~E_7~0); {21988#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 38: Hoare triple {21988#false} assume !(0 == ~E_8~0); {21988#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 39: Hoare triple {21988#false} assume !(0 == ~E_9~0); {21988#false} is VALID [2022-02-21 04:24:28,845 INFO L290 TraceCheckUtils]: 40: Hoare triple {21988#false} assume !(0 == ~E_10~0); {21988#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 41: Hoare triple {21988#false} assume !(0 == ~E_11~0); {21988#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 42: Hoare triple {21988#false} assume !(0 == ~E_12~0); {21988#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 43: Hoare triple {21988#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {21988#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 44: Hoare triple {21988#false} assume 1 == ~m_pc~0; {21988#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 45: Hoare triple {21988#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {21988#false} is VALID [2022-02-21 04:24:28,846 INFO L290 TraceCheckUtils]: 46: Hoare triple {21988#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {21988#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 47: Hoare triple {21988#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {21988#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 48: Hoare triple {21988#false} assume !(0 != activate_threads_~tmp~1#1); {21988#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 49: Hoare triple {21988#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {21988#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 50: Hoare triple {21988#false} assume 1 == ~t1_pc~0; {21988#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 51: Hoare triple {21988#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {21988#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 52: Hoare triple {21988#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {21988#false} is VALID [2022-02-21 04:24:28,847 INFO L290 TraceCheckUtils]: 53: Hoare triple {21988#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {21988#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 54: Hoare triple {21988#false} assume !(0 != activate_threads_~tmp___0~0#1); {21988#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 55: Hoare triple {21988#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {21988#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 56: Hoare triple {21988#false} assume !(1 == ~t2_pc~0); {21988#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 57: Hoare triple {21988#false} is_transmit2_triggered_~__retres1~2#1 := 0; {21988#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 58: Hoare triple {21988#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {21988#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 59: Hoare triple {21988#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {21988#false} is VALID [2022-02-21 04:24:28,848 INFO L290 TraceCheckUtils]: 60: Hoare triple {21988#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {21988#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 61: Hoare triple {21988#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {21988#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 62: Hoare triple {21988#false} assume 1 == ~t3_pc~0; {21988#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 63: Hoare triple {21988#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {21988#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 64: Hoare triple {21988#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {21988#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 65: Hoare triple {21988#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {21988#false} is VALID [2022-02-21 04:24:28,849 INFO L290 TraceCheckUtils]: 66: Hoare triple {21988#false} assume !(0 != activate_threads_~tmp___2~0#1); {21988#false} is VALID [2022-02-21 04:24:28,850 INFO L290 TraceCheckUtils]: 67: Hoare triple {21988#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {21988#false} is VALID [2022-02-21 04:24:28,850 INFO L290 TraceCheckUtils]: 68: Hoare triple {21988#false} assume !(1 == ~t4_pc~0); {21988#false} is VALID [2022-02-21 04:24:28,850 INFO L290 TraceCheckUtils]: 69: Hoare triple {21988#false} is_transmit4_triggered_~__retres1~4#1 := 0; {21988#false} is VALID [2022-02-21 04:24:28,850 INFO L290 TraceCheckUtils]: 70: Hoare triple {21988#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {21988#false} is VALID [2022-02-21 04:24:28,850 INFO L290 TraceCheckUtils]: 71: Hoare triple {21988#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {21988#false} is VALID [2022-02-21 04:24:28,850 INFO L290 TraceCheckUtils]: 72: Hoare triple {21988#false} assume !(0 != activate_threads_~tmp___3~0#1); {21988#false} is VALID [2022-02-21 04:24:28,850 INFO L290 TraceCheckUtils]: 73: Hoare triple {21988#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {21988#false} is VALID [2022-02-21 04:24:28,851 INFO L290 TraceCheckUtils]: 74: Hoare triple {21988#false} assume 1 == ~t5_pc~0; {21988#false} is VALID [2022-02-21 04:24:28,851 INFO L290 TraceCheckUtils]: 75: Hoare triple {21988#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {21988#false} is VALID [2022-02-21 04:24:28,851 INFO L290 TraceCheckUtils]: 76: Hoare triple {21988#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {21988#false} is VALID [2022-02-21 04:24:28,851 INFO L290 TraceCheckUtils]: 77: Hoare triple {21988#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {21988#false} is VALID [2022-02-21 04:24:28,851 INFO L290 TraceCheckUtils]: 78: Hoare triple {21988#false} assume !(0 != activate_threads_~tmp___4~0#1); {21988#false} is VALID [2022-02-21 04:24:28,851 INFO L290 TraceCheckUtils]: 79: Hoare triple {21988#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {21988#false} is VALID [2022-02-21 04:24:28,851 INFO L290 TraceCheckUtils]: 80: Hoare triple {21988#false} assume !(1 == ~t6_pc~0); {21988#false} is VALID [2022-02-21 04:24:28,852 INFO L290 TraceCheckUtils]: 81: Hoare triple {21988#false} is_transmit6_triggered_~__retres1~6#1 := 0; {21988#false} is VALID [2022-02-21 04:24:28,852 INFO L290 TraceCheckUtils]: 82: Hoare triple {21988#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {21988#false} is VALID [2022-02-21 04:24:28,852 INFO L290 TraceCheckUtils]: 83: Hoare triple {21988#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {21988#false} is VALID [2022-02-21 04:24:28,852 INFO L290 TraceCheckUtils]: 84: Hoare triple {21988#false} assume !(0 != activate_threads_~tmp___5~0#1); {21988#false} is VALID [2022-02-21 04:24:28,852 INFO L290 TraceCheckUtils]: 85: Hoare triple {21988#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {21988#false} is VALID [2022-02-21 04:24:28,852 INFO L290 TraceCheckUtils]: 86: Hoare triple {21988#false} assume 1 == ~t7_pc~0; {21988#false} is VALID [2022-02-21 04:24:28,852 INFO L290 TraceCheckUtils]: 87: Hoare triple {21988#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {21988#false} is VALID [2022-02-21 04:24:28,853 INFO L290 TraceCheckUtils]: 88: Hoare triple {21988#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {21988#false} is VALID [2022-02-21 04:24:28,853 INFO L290 TraceCheckUtils]: 89: Hoare triple {21988#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {21988#false} is VALID [2022-02-21 04:24:28,853 INFO L290 TraceCheckUtils]: 90: Hoare triple {21988#false} assume !(0 != activate_threads_~tmp___6~0#1); {21988#false} is VALID [2022-02-21 04:24:28,853 INFO L290 TraceCheckUtils]: 91: Hoare triple {21988#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {21988#false} is VALID [2022-02-21 04:24:28,853 INFO L290 TraceCheckUtils]: 92: Hoare triple {21988#false} assume !(1 == ~t8_pc~0); {21988#false} is VALID [2022-02-21 04:24:28,853 INFO L290 TraceCheckUtils]: 93: Hoare triple {21988#false} is_transmit8_triggered_~__retres1~8#1 := 0; {21988#false} is VALID [2022-02-21 04:24:28,853 INFO L290 TraceCheckUtils]: 94: Hoare triple {21988#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {21988#false} is VALID [2022-02-21 04:24:28,854 INFO L290 TraceCheckUtils]: 95: Hoare triple {21988#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {21988#false} is VALID [2022-02-21 04:24:28,854 INFO L290 TraceCheckUtils]: 96: Hoare triple {21988#false} assume !(0 != activate_threads_~tmp___7~0#1); {21988#false} is VALID [2022-02-21 04:24:28,854 INFO L290 TraceCheckUtils]: 97: Hoare triple {21988#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {21988#false} is VALID [2022-02-21 04:24:28,854 INFO L290 TraceCheckUtils]: 98: Hoare triple {21988#false} assume 1 == ~t9_pc~0; {21988#false} is VALID [2022-02-21 04:24:28,854 INFO L290 TraceCheckUtils]: 99: Hoare triple {21988#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {21988#false} is VALID [2022-02-21 04:24:28,854 INFO L290 TraceCheckUtils]: 100: Hoare triple {21988#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {21988#false} is VALID [2022-02-21 04:24:28,854 INFO L290 TraceCheckUtils]: 101: Hoare triple {21988#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {21988#false} is VALID [2022-02-21 04:24:28,855 INFO L290 TraceCheckUtils]: 102: Hoare triple {21988#false} assume !(0 != activate_threads_~tmp___8~0#1); {21988#false} is VALID [2022-02-21 04:24:28,855 INFO L290 TraceCheckUtils]: 103: Hoare triple {21988#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {21988#false} is VALID [2022-02-21 04:24:28,855 INFO L290 TraceCheckUtils]: 104: Hoare triple {21988#false} assume 1 == ~t10_pc~0; {21988#false} is VALID [2022-02-21 04:24:28,855 INFO L290 TraceCheckUtils]: 105: Hoare triple {21988#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {21988#false} is VALID [2022-02-21 04:24:28,855 INFO L290 TraceCheckUtils]: 106: Hoare triple {21988#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {21988#false} is VALID [2022-02-21 04:24:28,855 INFO L290 TraceCheckUtils]: 107: Hoare triple {21988#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {21988#false} is VALID [2022-02-21 04:24:28,856 INFO L290 TraceCheckUtils]: 108: Hoare triple {21988#false} assume !(0 != activate_threads_~tmp___9~0#1); {21988#false} is VALID [2022-02-21 04:24:28,856 INFO L290 TraceCheckUtils]: 109: Hoare triple {21988#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {21988#false} is VALID [2022-02-21 04:24:28,856 INFO L290 TraceCheckUtils]: 110: Hoare triple {21988#false} assume !(1 == ~t11_pc~0); {21988#false} is VALID [2022-02-21 04:24:28,856 INFO L290 TraceCheckUtils]: 111: Hoare triple {21988#false} is_transmit11_triggered_~__retres1~11#1 := 0; {21988#false} is VALID [2022-02-21 04:24:28,856 INFO L290 TraceCheckUtils]: 112: Hoare triple {21988#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {21988#false} is VALID [2022-02-21 04:24:28,856 INFO L290 TraceCheckUtils]: 113: Hoare triple {21988#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {21988#false} is VALID [2022-02-21 04:24:28,856 INFO L290 TraceCheckUtils]: 114: Hoare triple {21988#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {21988#false} is VALID [2022-02-21 04:24:28,857 INFO L290 TraceCheckUtils]: 115: Hoare triple {21988#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {21988#false} is VALID [2022-02-21 04:24:28,857 INFO L290 TraceCheckUtils]: 116: Hoare triple {21988#false} assume 1 == ~t12_pc~0; {21988#false} is VALID [2022-02-21 04:24:28,857 INFO L290 TraceCheckUtils]: 117: Hoare triple {21988#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {21988#false} is VALID [2022-02-21 04:24:28,857 INFO L290 TraceCheckUtils]: 118: Hoare triple {21988#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {21988#false} is VALID [2022-02-21 04:24:28,857 INFO L290 TraceCheckUtils]: 119: Hoare triple {21988#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {21988#false} is VALID [2022-02-21 04:24:28,857 INFO L290 TraceCheckUtils]: 120: Hoare triple {21988#false} assume !(0 != activate_threads_~tmp___11~0#1); {21988#false} is VALID [2022-02-21 04:24:28,857 INFO L290 TraceCheckUtils]: 121: Hoare triple {21988#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {21988#false} is VALID [2022-02-21 04:24:28,858 INFO L290 TraceCheckUtils]: 122: Hoare triple {21988#false} assume !(1 == ~M_E~0); {21988#false} is VALID [2022-02-21 04:24:28,858 INFO L290 TraceCheckUtils]: 123: Hoare triple {21988#false} assume !(1 == ~T1_E~0); {21988#false} is VALID [2022-02-21 04:24:28,858 INFO L290 TraceCheckUtils]: 124: Hoare triple {21988#false} assume !(1 == ~T2_E~0); {21988#false} is VALID [2022-02-21 04:24:28,858 INFO L290 TraceCheckUtils]: 125: Hoare triple {21988#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,858 INFO L290 TraceCheckUtils]: 126: Hoare triple {21988#false} assume !(1 == ~T4_E~0); {21988#false} is VALID [2022-02-21 04:24:28,858 INFO L290 TraceCheckUtils]: 127: Hoare triple {21988#false} assume !(1 == ~T5_E~0); {21988#false} is VALID [2022-02-21 04:24:28,859 INFO L290 TraceCheckUtils]: 128: Hoare triple {21988#false} assume !(1 == ~T6_E~0); {21988#false} is VALID [2022-02-21 04:24:28,859 INFO L290 TraceCheckUtils]: 129: Hoare triple {21988#false} assume !(1 == ~T7_E~0); {21988#false} is VALID [2022-02-21 04:24:28,859 INFO L290 TraceCheckUtils]: 130: Hoare triple {21988#false} assume !(1 == ~T8_E~0); {21988#false} is VALID [2022-02-21 04:24:28,859 INFO L290 TraceCheckUtils]: 131: Hoare triple {21988#false} assume !(1 == ~T9_E~0); {21988#false} is VALID [2022-02-21 04:24:28,859 INFO L290 TraceCheckUtils]: 132: Hoare triple {21988#false} assume !(1 == ~T10_E~0); {21988#false} is VALID [2022-02-21 04:24:28,859 INFO L290 TraceCheckUtils]: 133: Hoare triple {21988#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,859 INFO L290 TraceCheckUtils]: 134: Hoare triple {21988#false} assume !(1 == ~T12_E~0); {21988#false} is VALID [2022-02-21 04:24:28,860 INFO L290 TraceCheckUtils]: 135: Hoare triple {21988#false} assume !(1 == ~E_1~0); {21988#false} is VALID [2022-02-21 04:24:28,860 INFO L290 TraceCheckUtils]: 136: Hoare triple {21988#false} assume !(1 == ~E_2~0); {21988#false} is VALID [2022-02-21 04:24:28,860 INFO L290 TraceCheckUtils]: 137: Hoare triple {21988#false} assume !(1 == ~E_3~0); {21988#false} is VALID [2022-02-21 04:24:28,860 INFO L290 TraceCheckUtils]: 138: Hoare triple {21988#false} assume !(1 == ~E_4~0); {21988#false} is VALID [2022-02-21 04:24:28,860 INFO L290 TraceCheckUtils]: 139: Hoare triple {21988#false} assume !(1 == ~E_5~0); {21988#false} is VALID [2022-02-21 04:24:28,860 INFO L290 TraceCheckUtils]: 140: Hoare triple {21988#false} assume !(1 == ~E_6~0); {21988#false} is VALID [2022-02-21 04:24:28,860 INFO L290 TraceCheckUtils]: 141: Hoare triple {21988#false} assume 1 == ~E_7~0;~E_7~0 := 2; {21988#false} is VALID [2022-02-21 04:24:28,861 INFO L290 TraceCheckUtils]: 142: Hoare triple {21988#false} assume !(1 == ~E_8~0); {21988#false} is VALID [2022-02-21 04:24:28,861 INFO L290 TraceCheckUtils]: 143: Hoare triple {21988#false} assume !(1 == ~E_9~0); {21988#false} is VALID [2022-02-21 04:24:28,861 INFO L290 TraceCheckUtils]: 144: Hoare triple {21988#false} assume !(1 == ~E_10~0); {21988#false} is VALID [2022-02-21 04:24:28,861 INFO L290 TraceCheckUtils]: 145: Hoare triple {21988#false} assume !(1 == ~E_11~0); {21988#false} is VALID [2022-02-21 04:24:28,861 INFO L290 TraceCheckUtils]: 146: Hoare triple {21988#false} assume !(1 == ~E_12~0); {21988#false} is VALID [2022-02-21 04:24:28,861 INFO L290 TraceCheckUtils]: 147: Hoare triple {21988#false} assume { :end_inline_reset_delta_events } true; {21988#false} is VALID [2022-02-21 04:24:28,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:28,862 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:28,862 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1322917475] [2022-02-21 04:24:28,862 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1322917475] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:28,863 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:28,863 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:28,863 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1576051424] [2022-02-21 04:24:28,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:28,863 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:28,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:28,864 INFO L85 PathProgramCache]: Analyzing trace with hash 103308738, now seen corresponding path program 1 times [2022-02-21 04:24:28,864 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:28,865 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1230208902] [2022-02-21 04:24:28,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:28,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:28,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:28,912 INFO L290 TraceCheckUtils]: 0: Hoare triple {21990#true} assume !false; {21990#true} is VALID [2022-02-21 04:24:28,912 INFO L290 TraceCheckUtils]: 1: Hoare triple {21990#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {21990#true} is VALID [2022-02-21 04:24:28,913 INFO L290 TraceCheckUtils]: 2: Hoare triple {21990#true} assume !false; {21990#true} is VALID [2022-02-21 04:24:28,913 INFO L290 TraceCheckUtils]: 3: Hoare triple {21990#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {21990#true} is VALID [2022-02-21 04:24:28,913 INFO L290 TraceCheckUtils]: 4: Hoare triple {21990#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {21990#true} is VALID [2022-02-21 04:24:28,913 INFO L290 TraceCheckUtils]: 5: Hoare triple {21990#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {21990#true} is VALID [2022-02-21 04:24:28,913 INFO L290 TraceCheckUtils]: 6: Hoare triple {21990#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {21990#true} is VALID [2022-02-21 04:24:28,914 INFO L290 TraceCheckUtils]: 7: Hoare triple {21990#true} assume !(0 != eval_~tmp~0#1); {21990#true} is VALID [2022-02-21 04:24:28,914 INFO L290 TraceCheckUtils]: 8: Hoare triple {21990#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {21990#true} is VALID [2022-02-21 04:24:28,914 INFO L290 TraceCheckUtils]: 9: Hoare triple {21990#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {21990#true} is VALID [2022-02-21 04:24:28,914 INFO L290 TraceCheckUtils]: 10: Hoare triple {21990#true} assume !(0 == ~M_E~0); {21990#true} is VALID [2022-02-21 04:24:28,914 INFO L290 TraceCheckUtils]: 11: Hoare triple {21990#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {21990#true} is VALID [2022-02-21 04:24:28,914 INFO L290 TraceCheckUtils]: 12: Hoare triple {21990#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,915 INFO L290 TraceCheckUtils]: 13: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,915 INFO L290 TraceCheckUtils]: 14: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,915 INFO L290 TraceCheckUtils]: 15: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,915 INFO L290 TraceCheckUtils]: 16: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,916 INFO L290 TraceCheckUtils]: 17: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,916 INFO L290 TraceCheckUtils]: 18: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,916 INFO L290 TraceCheckUtils]: 19: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,917 INFO L290 TraceCheckUtils]: 20: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,917 INFO L290 TraceCheckUtils]: 21: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,917 INFO L290 TraceCheckUtils]: 22: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,917 INFO L290 TraceCheckUtils]: 23: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,918 INFO L290 TraceCheckUtils]: 24: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,918 INFO L290 TraceCheckUtils]: 25: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,918 INFO L290 TraceCheckUtils]: 26: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,919 INFO L290 TraceCheckUtils]: 27: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,919 INFO L290 TraceCheckUtils]: 28: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,919 INFO L290 TraceCheckUtils]: 29: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,919 INFO L290 TraceCheckUtils]: 30: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,920 INFO L290 TraceCheckUtils]: 31: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,920 INFO L290 TraceCheckUtils]: 32: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,920 INFO L290 TraceCheckUtils]: 33: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,921 INFO L290 TraceCheckUtils]: 34: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,921 INFO L290 TraceCheckUtils]: 35: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,921 INFO L290 TraceCheckUtils]: 36: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,921 INFO L290 TraceCheckUtils]: 37: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,922 INFO L290 TraceCheckUtils]: 38: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,922 INFO L290 TraceCheckUtils]: 39: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,922 INFO L290 TraceCheckUtils]: 40: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,923 INFO L290 TraceCheckUtils]: 41: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,923 INFO L290 TraceCheckUtils]: 42: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,923 INFO L290 TraceCheckUtils]: 43: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,923 INFO L290 TraceCheckUtils]: 44: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,924 INFO L290 TraceCheckUtils]: 45: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,924 INFO L290 TraceCheckUtils]: 46: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,924 INFO L290 TraceCheckUtils]: 47: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,925 INFO L290 TraceCheckUtils]: 48: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,925 INFO L290 TraceCheckUtils]: 49: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,925 INFO L290 TraceCheckUtils]: 50: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,925 INFO L290 TraceCheckUtils]: 51: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,926 INFO L290 TraceCheckUtils]: 52: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,926 INFO L290 TraceCheckUtils]: 53: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,926 INFO L290 TraceCheckUtils]: 54: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,927 INFO L290 TraceCheckUtils]: 55: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,927 INFO L290 TraceCheckUtils]: 56: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,927 INFO L290 TraceCheckUtils]: 57: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,927 INFO L290 TraceCheckUtils]: 58: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,928 INFO L290 TraceCheckUtils]: 59: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,928 INFO L290 TraceCheckUtils]: 60: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,928 INFO L290 TraceCheckUtils]: 61: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,929 INFO L290 TraceCheckUtils]: 62: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,929 INFO L290 TraceCheckUtils]: 63: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,929 INFO L290 TraceCheckUtils]: 64: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,929 INFO L290 TraceCheckUtils]: 65: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,930 INFO L290 TraceCheckUtils]: 66: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,930 INFO L290 TraceCheckUtils]: 67: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,930 INFO L290 TraceCheckUtils]: 68: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,931 INFO L290 TraceCheckUtils]: 69: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,931 INFO L290 TraceCheckUtils]: 70: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,931 INFO L290 TraceCheckUtils]: 71: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,931 INFO L290 TraceCheckUtils]: 72: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,932 INFO L290 TraceCheckUtils]: 73: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,932 INFO L290 TraceCheckUtils]: 74: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,932 INFO L290 TraceCheckUtils]: 75: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,933 INFO L290 TraceCheckUtils]: 76: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,933 INFO L290 TraceCheckUtils]: 77: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,933 INFO L290 TraceCheckUtils]: 78: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,933 INFO L290 TraceCheckUtils]: 79: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,934 INFO L290 TraceCheckUtils]: 80: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,934 INFO L290 TraceCheckUtils]: 81: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,934 INFO L290 TraceCheckUtils]: 82: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,934 INFO L290 TraceCheckUtils]: 83: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,935 INFO L290 TraceCheckUtils]: 84: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,935 INFO L290 TraceCheckUtils]: 85: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,935 INFO L290 TraceCheckUtils]: 86: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,936 INFO L290 TraceCheckUtils]: 87: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,936 INFO L290 TraceCheckUtils]: 88: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,936 INFO L290 TraceCheckUtils]: 89: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,936 INFO L290 TraceCheckUtils]: 90: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,937 INFO L290 TraceCheckUtils]: 91: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,937 INFO L290 TraceCheckUtils]: 92: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,937 INFO L290 TraceCheckUtils]: 93: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,938 INFO L290 TraceCheckUtils]: 94: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,938 INFO L290 TraceCheckUtils]: 95: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,938 INFO L290 TraceCheckUtils]: 96: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t10_pc~0); {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,938 INFO L290 TraceCheckUtils]: 97: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,939 INFO L290 TraceCheckUtils]: 98: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,939 INFO L290 TraceCheckUtils]: 99: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,939 INFO L290 TraceCheckUtils]: 100: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,940 INFO L290 TraceCheckUtils]: 101: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,940 INFO L290 TraceCheckUtils]: 102: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,940 INFO L290 TraceCheckUtils]: 103: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,941 INFO L290 TraceCheckUtils]: 104: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,941 INFO L290 TraceCheckUtils]: 105: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,941 INFO L290 TraceCheckUtils]: 106: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,941 INFO L290 TraceCheckUtils]: 107: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,942 INFO L290 TraceCheckUtils]: 108: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t12_pc~0); {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,942 INFO L290 TraceCheckUtils]: 109: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,942 INFO L290 TraceCheckUtils]: 110: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,943 INFO L290 TraceCheckUtils]: 111: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,943 INFO L290 TraceCheckUtils]: 112: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,943 INFO L290 TraceCheckUtils]: 113: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,943 INFO L290 TraceCheckUtils]: 114: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,944 INFO L290 TraceCheckUtils]: 115: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {21992#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:28,944 INFO L290 TraceCheckUtils]: 116: Hoare triple {21992#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {21991#false} is VALID [2022-02-21 04:24:28,944 INFO L290 TraceCheckUtils]: 117: Hoare triple {21991#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,944 INFO L290 TraceCheckUtils]: 118: Hoare triple {21991#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,944 INFO L290 TraceCheckUtils]: 119: Hoare triple {21991#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,944 INFO L290 TraceCheckUtils]: 120: Hoare triple {21991#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,945 INFO L290 TraceCheckUtils]: 121: Hoare triple {21991#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,945 INFO L290 TraceCheckUtils]: 122: Hoare triple {21991#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,945 INFO L290 TraceCheckUtils]: 123: Hoare triple {21991#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,945 INFO L290 TraceCheckUtils]: 124: Hoare triple {21991#false} assume !(1 == ~T10_E~0); {21991#false} is VALID [2022-02-21 04:24:28,945 INFO L290 TraceCheckUtils]: 125: Hoare triple {21991#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,945 INFO L290 TraceCheckUtils]: 126: Hoare triple {21991#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,945 INFO L290 TraceCheckUtils]: 127: Hoare triple {21991#false} assume 1 == ~E_1~0;~E_1~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,946 INFO L290 TraceCheckUtils]: 128: Hoare triple {21991#false} assume 1 == ~E_2~0;~E_2~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,946 INFO L290 TraceCheckUtils]: 129: Hoare triple {21991#false} assume 1 == ~E_3~0;~E_3~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,946 INFO L290 TraceCheckUtils]: 130: Hoare triple {21991#false} assume 1 == ~E_4~0;~E_4~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,946 INFO L290 TraceCheckUtils]: 131: Hoare triple {21991#false} assume 1 == ~E_5~0;~E_5~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,946 INFO L290 TraceCheckUtils]: 132: Hoare triple {21991#false} assume !(1 == ~E_6~0); {21991#false} is VALID [2022-02-21 04:24:28,947 INFO L290 TraceCheckUtils]: 133: Hoare triple {21991#false} assume 1 == ~E_7~0;~E_7~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,947 INFO L290 TraceCheckUtils]: 134: Hoare triple {21991#false} assume 1 == ~E_8~0;~E_8~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,947 INFO L290 TraceCheckUtils]: 135: Hoare triple {21991#false} assume 1 == ~E_9~0;~E_9~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,947 INFO L290 TraceCheckUtils]: 136: Hoare triple {21991#false} assume 1 == ~E_10~0;~E_10~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,947 INFO L290 TraceCheckUtils]: 137: Hoare triple {21991#false} assume 1 == ~E_11~0;~E_11~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,947 INFO L290 TraceCheckUtils]: 138: Hoare triple {21991#false} assume 1 == ~E_12~0;~E_12~0 := 2; {21991#false} is VALID [2022-02-21 04:24:28,948 INFO L290 TraceCheckUtils]: 139: Hoare triple {21991#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {21991#false} is VALID [2022-02-21 04:24:28,948 INFO L290 TraceCheckUtils]: 140: Hoare triple {21991#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {21991#false} is VALID [2022-02-21 04:24:28,948 INFO L290 TraceCheckUtils]: 141: Hoare triple {21991#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {21991#false} is VALID [2022-02-21 04:24:28,948 INFO L290 TraceCheckUtils]: 142: Hoare triple {21991#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {21991#false} is VALID [2022-02-21 04:24:28,948 INFO L290 TraceCheckUtils]: 143: Hoare triple {21991#false} assume !(0 == start_simulation_~tmp~3#1); {21991#false} is VALID [2022-02-21 04:24:28,949 INFO L290 TraceCheckUtils]: 144: Hoare triple {21991#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {21991#false} is VALID [2022-02-21 04:24:28,949 INFO L290 TraceCheckUtils]: 145: Hoare triple {21991#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {21991#false} is VALID [2022-02-21 04:24:28,949 INFO L290 TraceCheckUtils]: 146: Hoare triple {21991#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {21991#false} is VALID [2022-02-21 04:24:28,949 INFO L290 TraceCheckUtils]: 147: Hoare triple {21991#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {21991#false} is VALID [2022-02-21 04:24:28,949 INFO L290 TraceCheckUtils]: 148: Hoare triple {21991#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {21991#false} is VALID [2022-02-21 04:24:28,949 INFO L290 TraceCheckUtils]: 149: Hoare triple {21991#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {21991#false} is VALID [2022-02-21 04:24:28,950 INFO L290 TraceCheckUtils]: 150: Hoare triple {21991#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {21991#false} is VALID [2022-02-21 04:24:28,950 INFO L290 TraceCheckUtils]: 151: Hoare triple {21991#false} assume !(0 != start_simulation_~tmp___0~1#1); {21991#false} is VALID [2022-02-21 04:24:28,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:28,951 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:28,952 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1230208902] [2022-02-21 04:24:28,952 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1230208902] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:28,952 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:28,952 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:28,952 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920639250] [2022-02-21 04:24:28,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:28,953 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:28,953 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:28,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:28,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:28,954 INFO L87 Difference]: Start difference. First operand 1688 states and 2502 transitions. cyclomatic complexity: 815 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,201 INFO L93 Difference]: Finished difference Result 1688 states and 2501 transitions. [2022-02-21 04:24:30,201 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:30,202 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,281 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:30,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2501 transitions. [2022-02-21 04:24:30,408 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:30,517 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2501 transitions. [2022-02-21 04:24:30,517 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:30,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:30,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2501 transitions. [2022-02-21 04:24:30,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:30,521 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2022-02-21 04:24:30,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2501 transitions. [2022-02-21 04:24:30,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:30,540 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:30,543 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2501 transitions. Second operand has 1688 states, 1688 states have (on average 1.4816350710900474) internal successors, (2501), 1687 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,545 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2501 transitions. Second operand has 1688 states, 1688 states have (on average 1.4816350710900474) internal successors, (2501), 1687 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,548 INFO L87 Difference]: Start difference. First operand 1688 states and 2501 transitions. Second operand has 1688 states, 1688 states have (on average 1.4816350710900474) internal successors, (2501), 1687 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,646 INFO L93 Difference]: Finished difference Result 1688 states and 2501 transitions. [2022-02-21 04:24:30,646 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2501 transitions. [2022-02-21 04:24:30,649 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:30,649 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:30,653 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.4816350710900474) internal successors, (2501), 1687 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2501 transitions. [2022-02-21 04:24:30,655 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.4816350710900474) internal successors, (2501), 1687 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2501 transitions. [2022-02-21 04:24:30,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,758 INFO L93 Difference]: Finished difference Result 1688 states and 2501 transitions. [2022-02-21 04:24:30,758 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2501 transitions. [2022-02-21 04:24:30,760 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:30,760 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:30,761 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:30,761 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:30,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4816350710900474) internal successors, (2501), 1687 states have internal predecessors, (2501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2501 transitions. [2022-02-21 04:24:30,861 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2022-02-21 04:24:30,861 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2501 transitions. [2022-02-21 04:24:30,861 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:30,862 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2501 transitions. [2022-02-21 04:24:30,866 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:30,866 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:30,866 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:30,868 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:30,868 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:30,868 INFO L791 eck$LassoCheckResult]: Stem: 24484#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 24485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 25338#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24830#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24637#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 24638#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24723#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25024#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25146#L836-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 25147#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 23935#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 23936#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25084#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24530#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24531#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24437#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24438#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24826#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24179#L1174 assume !(0 == ~M_E~0); 24180#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24031#L1179-1 assume !(0 == ~T2_E~0); 23933#L1184-1 assume !(0 == ~T3_E~0); 23934#L1189-1 assume !(0 == ~T4_E~0); 23972#L1194-1 assume !(0 == ~T5_E~0); 24072#L1199-1 assume !(0 == ~T6_E~0); 24967#L1204-1 assume !(0 == ~T7_E~0); 24886#L1209-1 assume !(0 == ~T8_E~0); 24887#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25275#L1219-1 assume !(0 == ~T10_E~0); 25360#L1224-1 assume !(0 == ~T11_E~0); 24297#L1229-1 assume !(0 == ~T12_E~0); 23858#L1234-1 assume !(0 == ~E_1~0); 23859#L1239-1 assume !(0 == ~E_2~0); 23892#L1244-1 assume !(0 == ~E_3~0); 23893#L1249-1 assume !(0 == ~E_4~0); 24554#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 23788#L1259-1 assume !(0 == ~E_6~0); 23743#L1264-1 assume !(0 == ~E_7~0); 23744#L1269-1 assume !(0 == ~E_8~0); 25365#L1274-1 assume !(0 == ~E_9~0); 25300#L1279-1 assume !(0 == ~E_10~0); 23976#L1284-1 assume !(0 == ~E_11~0); 23977#L1289-1 assume !(0 == ~E_12~0); 24606#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24607#L566 assume 1 == ~m_pc~0; 23760#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 23761#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24915#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24916#L1455 assume !(0 != activate_threads_~tmp~1#1); 24206#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24207#L585 assume 1 == ~t1_pc~0; 23855#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23856#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24856#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24857#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 25325#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25323#L604 assume !(1 == ~t2_pc~0); 24935#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24936#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24469#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24470#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25107#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25108#L623 assume 1 == ~t3_pc~0; 24384#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23724#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24534#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24535#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 25142#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23757#L642 assume !(1 == ~t4_pc~0); 23758#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 24223#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24224#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23829#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 23830#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24947#L661 assume 1 == ~t5_pc~0; 23994#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23995#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23956#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23957#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 24976#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24977#L680 assume !(1 == ~t6_pc~0); 24417#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 24418#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24679#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24680#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 25208#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25321#L699 assume 1 == ~t7_pc~0; 24807#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24808#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23984#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23985#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 24709#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24608#L718 assume !(1 == ~t8_pc~0); 24609#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 23970#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23971#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24012#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 24013#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24146#L737 assume 1 == ~t9_pc~0; 25011#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24281#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24882#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24883#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 24455#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24456#L756 assume 1 == ~t10_pc~0; 25035#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24701#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23687#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23688#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 24263#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24264#L775 assume !(1 == ~t11_pc~0); 24518#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 24519#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24140#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23904#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23905#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24091#L794 assume 1 == ~t12_pc~0; 23931#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23909#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25102#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24057#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 24058#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24537#L1307 assume !(1 == ~M_E~0); 24538#L1307-2 assume !(1 == ~T1_E~0); 24649#L1312-1 assume !(1 == ~T2_E~0); 24568#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24569#L1322-1 assume !(1 == ~T4_E~0); 24272#L1327-1 assume !(1 == ~T5_E~0); 24273#L1332-1 assume !(1 == ~T6_E~0); 24811#L1337-1 assume !(1 == ~T7_E~0); 24773#L1342-1 assume !(1 == ~T8_E~0); 24774#L1347-1 assume !(1 == ~T9_E~0); 25171#L1352-1 assume !(1 == ~T10_E~0); 25044#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24435#L1362-1 assume !(1 == ~T12_E~0); 24436#L1367-1 assume !(1 == ~E_1~0); 24073#L1372-1 assume !(1 == ~E_2~0); 24074#L1377-1 assume !(1 == ~E_3~0); 24367#L1382-1 assume !(1 == ~E_4~0); 24368#L1387-1 assume !(1 == ~E_5~0); 24937#L1392-1 assume !(1 == ~E_6~0); 24387#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 24388#L1402-1 assume !(1 == ~E_8~0); 24084#L1407-1 assume !(1 == ~E_9~0); 24085#L1412-1 assume !(1 == ~E_10~0); 25100#L1417-1 assume !(1 == ~E_11~0); 25101#L1422-1 assume !(1 == ~E_12~0); 25319#L1427-1 assume { :end_inline_reset_delta_events } true; 23888#L1768-2 [2022-02-21 04:24:30,868 INFO L793 eck$LassoCheckResult]: Loop: 23888#L1768-2 assume !false; 23889#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24627#L1149 assume !false; 24999#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25152#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24278#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24184#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24185#L976 assume !(0 != eval_~tmp~0#1); 25318#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25328#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25119#L1174-3 assume !(0 == ~M_E~0); 25112#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24861#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24862#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25045#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24696#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24046#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24047#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24288#L1209-3 assume !(0 == ~T8_E~0); 23708#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23709#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24467#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24468#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24486#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23896#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23897#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24340#L1249-3 assume !(0 == ~E_4~0); 24799#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25271#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24913#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23902#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23903#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25298#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24465#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24466#L1289-3 assume !(0 == ~E_12~0); 24454#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24130#L566-39 assume 1 == ~m_pc~0; 24131#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24733#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24445#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24446#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24988#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24989#L585-39 assume !(1 == ~t1_pc~0); 24138#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 24139#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24214#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24215#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25021#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24714#L604-39 assume 1 == ~t2_pc~0; 24715#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24346#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24347#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24764#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24765#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24329#L623-39 assume 1 == ~t3_pc~0; 23725#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23727#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25005#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24181#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24182#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24953#L642-39 assume 1 == ~t4_pc~0; 24524#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24525#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24053#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24054#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25151#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24102#L661-39 assume !(1 == ~t5_pc~0); 23733#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 23734#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25094#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25095#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25008#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25009#L680-39 assume 1 == ~t6_pc~0; 23795#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23796#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24938#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24261#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24262#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25276#L699-39 assume 1 == ~t7_pc~0; 24698#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24420#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24421#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25104#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25225#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25223#L718-39 assume 1 == ~t8_pc~0; 24612#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24613#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24545#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24546#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 24848#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24817#L737-39 assume 1 == ~t9_pc~0; 24242#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24243#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24532#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25299#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25200#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25143#L756-39 assume !(1 == ~t10_pc~0); 24624#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 24625#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24369#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24370#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24502#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23842#L775-39 assume 1 == ~t11_pc~0; 23843#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24495#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24496#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25358#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24906#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24553#L794-39 assume 1 == ~t12_pc~0; 24245#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24239#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25059#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24960#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 23784#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23785#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25252#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25253#L1312-3 assume !(1 == ~T2_E~0); 25364#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24978#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24979#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23923#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23894#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23895#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24641#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24766#L1352-3 assume !(1 == ~T10_E~0); 24767#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25206#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25357#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25348#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23721#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23722#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24353#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24354#L1392-3 assume !(1 == ~E_6~0); 25069#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25315#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24732#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24008#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24009#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24657#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24658#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 24018#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 24019#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24885#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 24737#L1787 assume !(0 == start_simulation_~tmp~3#1); 24738#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 25261#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 23989#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 24784#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 24785#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24336#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24337#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 24338#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 23888#L1768-2 [2022-02-21 04:24:30,869 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:30,869 INFO L85 PathProgramCache]: Analyzing trace with hash -1064176049, now seen corresponding path program 1 times [2022-02-21 04:24:30,869 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:30,869 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013350619] [2022-02-21 04:24:30,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:30,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:30,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:30,892 INFO L290 TraceCheckUtils]: 0: Hoare triple {28748#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {28748#true} is VALID [2022-02-21 04:24:30,893 INFO L290 TraceCheckUtils]: 1: Hoare triple {28748#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {28750#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:30,893 INFO L290 TraceCheckUtils]: 2: Hoare triple {28750#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {28750#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:30,893 INFO L290 TraceCheckUtils]: 3: Hoare triple {28750#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {28750#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:30,894 INFO L290 TraceCheckUtils]: 4: Hoare triple {28750#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {28750#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:30,894 INFO L290 TraceCheckUtils]: 5: Hoare triple {28750#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {28750#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:30,894 INFO L290 TraceCheckUtils]: 6: Hoare triple {28750#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {28750#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:30,895 INFO L290 TraceCheckUtils]: 7: Hoare triple {28750#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {28750#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:30,895 INFO L290 TraceCheckUtils]: 8: Hoare triple {28750#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {28749#false} is VALID [2022-02-21 04:24:30,895 INFO L290 TraceCheckUtils]: 9: Hoare triple {28749#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {28749#false} is VALID [2022-02-21 04:24:30,895 INFO L290 TraceCheckUtils]: 10: Hoare triple {28749#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {28749#false} is VALID [2022-02-21 04:24:30,895 INFO L290 TraceCheckUtils]: 11: Hoare triple {28749#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {28749#false} is VALID [2022-02-21 04:24:30,895 INFO L290 TraceCheckUtils]: 12: Hoare triple {28749#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {28749#false} is VALID [2022-02-21 04:24:30,895 INFO L290 TraceCheckUtils]: 13: Hoare triple {28749#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {28749#false} is VALID [2022-02-21 04:24:30,896 INFO L290 TraceCheckUtils]: 14: Hoare triple {28749#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {28749#false} is VALID [2022-02-21 04:24:30,896 INFO L290 TraceCheckUtils]: 15: Hoare triple {28749#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {28749#false} is VALID [2022-02-21 04:24:30,896 INFO L290 TraceCheckUtils]: 16: Hoare triple {28749#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {28749#false} is VALID [2022-02-21 04:24:30,896 INFO L290 TraceCheckUtils]: 17: Hoare triple {28749#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {28749#false} is VALID [2022-02-21 04:24:30,896 INFO L290 TraceCheckUtils]: 18: Hoare triple {28749#false} assume !(0 == ~M_E~0); {28749#false} is VALID [2022-02-21 04:24:30,896 INFO L290 TraceCheckUtils]: 19: Hoare triple {28749#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {28749#false} is VALID [2022-02-21 04:24:30,896 INFO L290 TraceCheckUtils]: 20: Hoare triple {28749#false} assume !(0 == ~T2_E~0); {28749#false} is VALID [2022-02-21 04:24:30,896 INFO L290 TraceCheckUtils]: 21: Hoare triple {28749#false} assume !(0 == ~T3_E~0); {28749#false} is VALID [2022-02-21 04:24:30,896 INFO L290 TraceCheckUtils]: 22: Hoare triple {28749#false} assume !(0 == ~T4_E~0); {28749#false} is VALID [2022-02-21 04:24:30,897 INFO L290 TraceCheckUtils]: 23: Hoare triple {28749#false} assume !(0 == ~T5_E~0); {28749#false} is VALID [2022-02-21 04:24:30,897 INFO L290 TraceCheckUtils]: 24: Hoare triple {28749#false} assume !(0 == ~T6_E~0); {28749#false} is VALID [2022-02-21 04:24:30,897 INFO L290 TraceCheckUtils]: 25: Hoare triple {28749#false} assume !(0 == ~T7_E~0); {28749#false} is VALID [2022-02-21 04:24:30,897 INFO L290 TraceCheckUtils]: 26: Hoare triple {28749#false} assume !(0 == ~T8_E~0); {28749#false} is VALID [2022-02-21 04:24:30,897 INFO L290 TraceCheckUtils]: 27: Hoare triple {28749#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {28749#false} is VALID [2022-02-21 04:24:30,897 INFO L290 TraceCheckUtils]: 28: Hoare triple {28749#false} assume !(0 == ~T10_E~0); {28749#false} is VALID [2022-02-21 04:24:30,897 INFO L290 TraceCheckUtils]: 29: Hoare triple {28749#false} assume !(0 == ~T11_E~0); {28749#false} is VALID [2022-02-21 04:24:30,897 INFO L290 TraceCheckUtils]: 30: Hoare triple {28749#false} assume !(0 == ~T12_E~0); {28749#false} is VALID [2022-02-21 04:24:30,897 INFO L290 TraceCheckUtils]: 31: Hoare triple {28749#false} assume !(0 == ~E_1~0); {28749#false} is VALID [2022-02-21 04:24:30,898 INFO L290 TraceCheckUtils]: 32: Hoare triple {28749#false} assume !(0 == ~E_2~0); {28749#false} is VALID [2022-02-21 04:24:30,898 INFO L290 TraceCheckUtils]: 33: Hoare triple {28749#false} assume !(0 == ~E_3~0); {28749#false} is VALID [2022-02-21 04:24:30,898 INFO L290 TraceCheckUtils]: 34: Hoare triple {28749#false} assume !(0 == ~E_4~0); {28749#false} is VALID [2022-02-21 04:24:30,898 INFO L290 TraceCheckUtils]: 35: Hoare triple {28749#false} assume 0 == ~E_5~0;~E_5~0 := 1; {28749#false} is VALID [2022-02-21 04:24:30,898 INFO L290 TraceCheckUtils]: 36: Hoare triple {28749#false} assume !(0 == ~E_6~0); {28749#false} is VALID [2022-02-21 04:24:30,898 INFO L290 TraceCheckUtils]: 37: Hoare triple {28749#false} assume !(0 == ~E_7~0); {28749#false} is VALID [2022-02-21 04:24:30,898 INFO L290 TraceCheckUtils]: 38: Hoare triple {28749#false} assume !(0 == ~E_8~0); {28749#false} is VALID [2022-02-21 04:24:30,898 INFO L290 TraceCheckUtils]: 39: Hoare triple {28749#false} assume !(0 == ~E_9~0); {28749#false} is VALID [2022-02-21 04:24:30,898 INFO L290 TraceCheckUtils]: 40: Hoare triple {28749#false} assume !(0 == ~E_10~0); {28749#false} is VALID [2022-02-21 04:24:30,899 INFO L290 TraceCheckUtils]: 41: Hoare triple {28749#false} assume !(0 == ~E_11~0); {28749#false} is VALID [2022-02-21 04:24:30,899 INFO L290 TraceCheckUtils]: 42: Hoare triple {28749#false} assume !(0 == ~E_12~0); {28749#false} is VALID [2022-02-21 04:24:30,899 INFO L290 TraceCheckUtils]: 43: Hoare triple {28749#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28749#false} is VALID [2022-02-21 04:24:30,899 INFO L290 TraceCheckUtils]: 44: Hoare triple {28749#false} assume 1 == ~m_pc~0; {28749#false} is VALID [2022-02-21 04:24:30,899 INFO L290 TraceCheckUtils]: 45: Hoare triple {28749#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {28749#false} is VALID [2022-02-21 04:24:30,899 INFO L290 TraceCheckUtils]: 46: Hoare triple {28749#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28749#false} is VALID [2022-02-21 04:24:30,899 INFO L290 TraceCheckUtils]: 47: Hoare triple {28749#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {28749#false} is VALID [2022-02-21 04:24:30,899 INFO L290 TraceCheckUtils]: 48: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp~1#1); {28749#false} is VALID [2022-02-21 04:24:30,899 INFO L290 TraceCheckUtils]: 49: Hoare triple {28749#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28749#false} is VALID [2022-02-21 04:24:30,900 INFO L290 TraceCheckUtils]: 50: Hoare triple {28749#false} assume 1 == ~t1_pc~0; {28749#false} is VALID [2022-02-21 04:24:30,900 INFO L290 TraceCheckUtils]: 51: Hoare triple {28749#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {28749#false} is VALID [2022-02-21 04:24:30,900 INFO L290 TraceCheckUtils]: 52: Hoare triple {28749#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28749#false} is VALID [2022-02-21 04:24:30,900 INFO L290 TraceCheckUtils]: 53: Hoare triple {28749#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {28749#false} is VALID [2022-02-21 04:24:30,900 INFO L290 TraceCheckUtils]: 54: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___0~0#1); {28749#false} is VALID [2022-02-21 04:24:30,900 INFO L290 TraceCheckUtils]: 55: Hoare triple {28749#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28749#false} is VALID [2022-02-21 04:24:30,900 INFO L290 TraceCheckUtils]: 56: Hoare triple {28749#false} assume !(1 == ~t2_pc~0); {28749#false} is VALID [2022-02-21 04:24:30,900 INFO L290 TraceCheckUtils]: 57: Hoare triple {28749#false} is_transmit2_triggered_~__retres1~2#1 := 0; {28749#false} is VALID [2022-02-21 04:24:30,900 INFO L290 TraceCheckUtils]: 58: Hoare triple {28749#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28749#false} is VALID [2022-02-21 04:24:30,901 INFO L290 TraceCheckUtils]: 59: Hoare triple {28749#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {28749#false} is VALID [2022-02-21 04:24:30,901 INFO L290 TraceCheckUtils]: 60: Hoare triple {28749#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {28749#false} is VALID [2022-02-21 04:24:30,901 INFO L290 TraceCheckUtils]: 61: Hoare triple {28749#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28749#false} is VALID [2022-02-21 04:24:30,901 INFO L290 TraceCheckUtils]: 62: Hoare triple {28749#false} assume 1 == ~t3_pc~0; {28749#false} is VALID [2022-02-21 04:24:30,901 INFO L290 TraceCheckUtils]: 63: Hoare triple {28749#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {28749#false} is VALID [2022-02-21 04:24:30,901 INFO L290 TraceCheckUtils]: 64: Hoare triple {28749#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28749#false} is VALID [2022-02-21 04:24:30,901 INFO L290 TraceCheckUtils]: 65: Hoare triple {28749#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {28749#false} is VALID [2022-02-21 04:24:30,901 INFO L290 TraceCheckUtils]: 66: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___2~0#1); {28749#false} is VALID [2022-02-21 04:24:30,901 INFO L290 TraceCheckUtils]: 67: Hoare triple {28749#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28749#false} is VALID [2022-02-21 04:24:30,902 INFO L290 TraceCheckUtils]: 68: Hoare triple {28749#false} assume !(1 == ~t4_pc~0); {28749#false} is VALID [2022-02-21 04:24:30,902 INFO L290 TraceCheckUtils]: 69: Hoare triple {28749#false} is_transmit4_triggered_~__retres1~4#1 := 0; {28749#false} is VALID [2022-02-21 04:24:30,902 INFO L290 TraceCheckUtils]: 70: Hoare triple {28749#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28749#false} is VALID [2022-02-21 04:24:30,902 INFO L290 TraceCheckUtils]: 71: Hoare triple {28749#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {28749#false} is VALID [2022-02-21 04:24:30,902 INFO L290 TraceCheckUtils]: 72: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___3~0#1); {28749#false} is VALID [2022-02-21 04:24:30,902 INFO L290 TraceCheckUtils]: 73: Hoare triple {28749#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {28749#false} is VALID [2022-02-21 04:24:30,902 INFO L290 TraceCheckUtils]: 74: Hoare triple {28749#false} assume 1 == ~t5_pc~0; {28749#false} is VALID [2022-02-21 04:24:30,902 INFO L290 TraceCheckUtils]: 75: Hoare triple {28749#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {28749#false} is VALID [2022-02-21 04:24:30,902 INFO L290 TraceCheckUtils]: 76: Hoare triple {28749#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {28749#false} is VALID [2022-02-21 04:24:30,903 INFO L290 TraceCheckUtils]: 77: Hoare triple {28749#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {28749#false} is VALID [2022-02-21 04:24:30,903 INFO L290 TraceCheckUtils]: 78: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___4~0#1); {28749#false} is VALID [2022-02-21 04:24:30,903 INFO L290 TraceCheckUtils]: 79: Hoare triple {28749#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {28749#false} is VALID [2022-02-21 04:24:30,903 INFO L290 TraceCheckUtils]: 80: Hoare triple {28749#false} assume !(1 == ~t6_pc~0); {28749#false} is VALID [2022-02-21 04:24:30,903 INFO L290 TraceCheckUtils]: 81: Hoare triple {28749#false} is_transmit6_triggered_~__retres1~6#1 := 0; {28749#false} is VALID [2022-02-21 04:24:30,903 INFO L290 TraceCheckUtils]: 82: Hoare triple {28749#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {28749#false} is VALID [2022-02-21 04:24:30,903 INFO L290 TraceCheckUtils]: 83: Hoare triple {28749#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {28749#false} is VALID [2022-02-21 04:24:30,903 INFO L290 TraceCheckUtils]: 84: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___5~0#1); {28749#false} is VALID [2022-02-21 04:24:30,903 INFO L290 TraceCheckUtils]: 85: Hoare triple {28749#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {28749#false} is VALID [2022-02-21 04:24:30,904 INFO L290 TraceCheckUtils]: 86: Hoare triple {28749#false} assume 1 == ~t7_pc~0; {28749#false} is VALID [2022-02-21 04:24:30,904 INFO L290 TraceCheckUtils]: 87: Hoare triple {28749#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {28749#false} is VALID [2022-02-21 04:24:30,904 INFO L290 TraceCheckUtils]: 88: Hoare triple {28749#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {28749#false} is VALID [2022-02-21 04:24:30,904 INFO L290 TraceCheckUtils]: 89: Hoare triple {28749#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {28749#false} is VALID [2022-02-21 04:24:30,904 INFO L290 TraceCheckUtils]: 90: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___6~0#1); {28749#false} is VALID [2022-02-21 04:24:30,904 INFO L290 TraceCheckUtils]: 91: Hoare triple {28749#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {28749#false} is VALID [2022-02-21 04:24:30,904 INFO L290 TraceCheckUtils]: 92: Hoare triple {28749#false} assume !(1 == ~t8_pc~0); {28749#false} is VALID [2022-02-21 04:24:30,904 INFO L290 TraceCheckUtils]: 93: Hoare triple {28749#false} is_transmit8_triggered_~__retres1~8#1 := 0; {28749#false} is VALID [2022-02-21 04:24:30,904 INFO L290 TraceCheckUtils]: 94: Hoare triple {28749#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {28749#false} is VALID [2022-02-21 04:24:30,905 INFO L290 TraceCheckUtils]: 95: Hoare triple {28749#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {28749#false} is VALID [2022-02-21 04:24:30,905 INFO L290 TraceCheckUtils]: 96: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___7~0#1); {28749#false} is VALID [2022-02-21 04:24:30,905 INFO L290 TraceCheckUtils]: 97: Hoare triple {28749#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {28749#false} is VALID [2022-02-21 04:24:30,905 INFO L290 TraceCheckUtils]: 98: Hoare triple {28749#false} assume 1 == ~t9_pc~0; {28749#false} is VALID [2022-02-21 04:24:30,905 INFO L290 TraceCheckUtils]: 99: Hoare triple {28749#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {28749#false} is VALID [2022-02-21 04:24:30,905 INFO L290 TraceCheckUtils]: 100: Hoare triple {28749#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {28749#false} is VALID [2022-02-21 04:24:30,905 INFO L290 TraceCheckUtils]: 101: Hoare triple {28749#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {28749#false} is VALID [2022-02-21 04:24:30,905 INFO L290 TraceCheckUtils]: 102: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___8~0#1); {28749#false} is VALID [2022-02-21 04:24:30,905 INFO L290 TraceCheckUtils]: 103: Hoare triple {28749#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {28749#false} is VALID [2022-02-21 04:24:30,906 INFO L290 TraceCheckUtils]: 104: Hoare triple {28749#false} assume 1 == ~t10_pc~0; {28749#false} is VALID [2022-02-21 04:24:30,906 INFO L290 TraceCheckUtils]: 105: Hoare triple {28749#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {28749#false} is VALID [2022-02-21 04:24:30,906 INFO L290 TraceCheckUtils]: 106: Hoare triple {28749#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {28749#false} is VALID [2022-02-21 04:24:30,906 INFO L290 TraceCheckUtils]: 107: Hoare triple {28749#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {28749#false} is VALID [2022-02-21 04:24:30,906 INFO L290 TraceCheckUtils]: 108: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___9~0#1); {28749#false} is VALID [2022-02-21 04:24:30,906 INFO L290 TraceCheckUtils]: 109: Hoare triple {28749#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {28749#false} is VALID [2022-02-21 04:24:30,906 INFO L290 TraceCheckUtils]: 110: Hoare triple {28749#false} assume !(1 == ~t11_pc~0); {28749#false} is VALID [2022-02-21 04:24:30,906 INFO L290 TraceCheckUtils]: 111: Hoare triple {28749#false} is_transmit11_triggered_~__retres1~11#1 := 0; {28749#false} is VALID [2022-02-21 04:24:30,906 INFO L290 TraceCheckUtils]: 112: Hoare triple {28749#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {28749#false} is VALID [2022-02-21 04:24:30,907 INFO L290 TraceCheckUtils]: 113: Hoare triple {28749#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {28749#false} is VALID [2022-02-21 04:24:30,907 INFO L290 TraceCheckUtils]: 114: Hoare triple {28749#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {28749#false} is VALID [2022-02-21 04:24:30,907 INFO L290 TraceCheckUtils]: 115: Hoare triple {28749#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {28749#false} is VALID [2022-02-21 04:24:30,907 INFO L290 TraceCheckUtils]: 116: Hoare triple {28749#false} assume 1 == ~t12_pc~0; {28749#false} is VALID [2022-02-21 04:24:30,907 INFO L290 TraceCheckUtils]: 117: Hoare triple {28749#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {28749#false} is VALID [2022-02-21 04:24:30,907 INFO L290 TraceCheckUtils]: 118: Hoare triple {28749#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {28749#false} is VALID [2022-02-21 04:24:30,907 INFO L290 TraceCheckUtils]: 119: Hoare triple {28749#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {28749#false} is VALID [2022-02-21 04:24:30,907 INFO L290 TraceCheckUtils]: 120: Hoare triple {28749#false} assume !(0 != activate_threads_~tmp___11~0#1); {28749#false} is VALID [2022-02-21 04:24:30,907 INFO L290 TraceCheckUtils]: 121: Hoare triple {28749#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28749#false} is VALID [2022-02-21 04:24:30,908 INFO L290 TraceCheckUtils]: 122: Hoare triple {28749#false} assume !(1 == ~M_E~0); {28749#false} is VALID [2022-02-21 04:24:30,908 INFO L290 TraceCheckUtils]: 123: Hoare triple {28749#false} assume !(1 == ~T1_E~0); {28749#false} is VALID [2022-02-21 04:24:30,908 INFO L290 TraceCheckUtils]: 124: Hoare triple {28749#false} assume !(1 == ~T2_E~0); {28749#false} is VALID [2022-02-21 04:24:30,908 INFO L290 TraceCheckUtils]: 125: Hoare triple {28749#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {28749#false} is VALID [2022-02-21 04:24:30,908 INFO L290 TraceCheckUtils]: 126: Hoare triple {28749#false} assume !(1 == ~T4_E~0); {28749#false} is VALID [2022-02-21 04:24:30,908 INFO L290 TraceCheckUtils]: 127: Hoare triple {28749#false} assume !(1 == ~T5_E~0); {28749#false} is VALID [2022-02-21 04:24:30,908 INFO L290 TraceCheckUtils]: 128: Hoare triple {28749#false} assume !(1 == ~T6_E~0); {28749#false} is VALID [2022-02-21 04:24:30,908 INFO L290 TraceCheckUtils]: 129: Hoare triple {28749#false} assume !(1 == ~T7_E~0); {28749#false} is VALID [2022-02-21 04:24:30,908 INFO L290 TraceCheckUtils]: 130: Hoare triple {28749#false} assume !(1 == ~T8_E~0); {28749#false} is VALID [2022-02-21 04:24:30,909 INFO L290 TraceCheckUtils]: 131: Hoare triple {28749#false} assume !(1 == ~T9_E~0); {28749#false} is VALID [2022-02-21 04:24:30,909 INFO L290 TraceCheckUtils]: 132: Hoare triple {28749#false} assume !(1 == ~T10_E~0); {28749#false} is VALID [2022-02-21 04:24:30,909 INFO L290 TraceCheckUtils]: 133: Hoare triple {28749#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {28749#false} is VALID [2022-02-21 04:24:30,909 INFO L290 TraceCheckUtils]: 134: Hoare triple {28749#false} assume !(1 == ~T12_E~0); {28749#false} is VALID [2022-02-21 04:24:30,909 INFO L290 TraceCheckUtils]: 135: Hoare triple {28749#false} assume !(1 == ~E_1~0); {28749#false} is VALID [2022-02-21 04:24:30,909 INFO L290 TraceCheckUtils]: 136: Hoare triple {28749#false} assume !(1 == ~E_2~0); {28749#false} is VALID [2022-02-21 04:24:30,909 INFO L290 TraceCheckUtils]: 137: Hoare triple {28749#false} assume !(1 == ~E_3~0); {28749#false} is VALID [2022-02-21 04:24:30,909 INFO L290 TraceCheckUtils]: 138: Hoare triple {28749#false} assume !(1 == ~E_4~0); {28749#false} is VALID [2022-02-21 04:24:30,909 INFO L290 TraceCheckUtils]: 139: Hoare triple {28749#false} assume !(1 == ~E_5~0); {28749#false} is VALID [2022-02-21 04:24:30,910 INFO L290 TraceCheckUtils]: 140: Hoare triple {28749#false} assume !(1 == ~E_6~0); {28749#false} is VALID [2022-02-21 04:24:30,910 INFO L290 TraceCheckUtils]: 141: Hoare triple {28749#false} assume 1 == ~E_7~0;~E_7~0 := 2; {28749#false} is VALID [2022-02-21 04:24:30,910 INFO L290 TraceCheckUtils]: 142: Hoare triple {28749#false} assume !(1 == ~E_8~0); {28749#false} is VALID [2022-02-21 04:24:30,910 INFO L290 TraceCheckUtils]: 143: Hoare triple {28749#false} assume !(1 == ~E_9~0); {28749#false} is VALID [2022-02-21 04:24:30,910 INFO L290 TraceCheckUtils]: 144: Hoare triple {28749#false} assume !(1 == ~E_10~0); {28749#false} is VALID [2022-02-21 04:24:30,910 INFO L290 TraceCheckUtils]: 145: Hoare triple {28749#false} assume !(1 == ~E_11~0); {28749#false} is VALID [2022-02-21 04:24:30,910 INFO L290 TraceCheckUtils]: 146: Hoare triple {28749#false} assume !(1 == ~E_12~0); {28749#false} is VALID [2022-02-21 04:24:30,910 INFO L290 TraceCheckUtils]: 147: Hoare triple {28749#false} assume { :end_inline_reset_delta_events } true; {28749#false} is VALID [2022-02-21 04:24:30,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:30,911 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:30,911 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013350619] [2022-02-21 04:24:30,911 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013350619] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:30,911 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:30,911 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:30,912 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246337908] [2022-02-21 04:24:30,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:30,912 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:30,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:30,912 INFO L85 PathProgramCache]: Analyzing trace with hash -1994635518, now seen corresponding path program 1 times [2022-02-21 04:24:30,913 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:30,913 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281067654] [2022-02-21 04:24:30,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:30,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:30,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:30,943 INFO L290 TraceCheckUtils]: 0: Hoare triple {28751#true} assume !false; {28751#true} is VALID [2022-02-21 04:24:30,943 INFO L290 TraceCheckUtils]: 1: Hoare triple {28751#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {28751#true} is VALID [2022-02-21 04:24:30,943 INFO L290 TraceCheckUtils]: 2: Hoare triple {28751#true} assume !false; {28751#true} is VALID [2022-02-21 04:24:30,943 INFO L290 TraceCheckUtils]: 3: Hoare triple {28751#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {28751#true} is VALID [2022-02-21 04:24:30,944 INFO L290 TraceCheckUtils]: 4: Hoare triple {28751#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {28751#true} is VALID [2022-02-21 04:24:30,944 INFO L290 TraceCheckUtils]: 5: Hoare triple {28751#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {28751#true} is VALID [2022-02-21 04:24:30,944 INFO L290 TraceCheckUtils]: 6: Hoare triple {28751#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {28751#true} is VALID [2022-02-21 04:24:30,944 INFO L290 TraceCheckUtils]: 7: Hoare triple {28751#true} assume !(0 != eval_~tmp~0#1); {28751#true} is VALID [2022-02-21 04:24:30,944 INFO L290 TraceCheckUtils]: 8: Hoare triple {28751#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {28751#true} is VALID [2022-02-21 04:24:30,944 INFO L290 TraceCheckUtils]: 9: Hoare triple {28751#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {28751#true} is VALID [2022-02-21 04:24:30,944 INFO L290 TraceCheckUtils]: 10: Hoare triple {28751#true} assume !(0 == ~M_E~0); {28751#true} is VALID [2022-02-21 04:24:30,944 INFO L290 TraceCheckUtils]: 11: Hoare triple {28751#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {28751#true} is VALID [2022-02-21 04:24:30,945 INFO L290 TraceCheckUtils]: 12: Hoare triple {28751#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,945 INFO L290 TraceCheckUtils]: 13: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,945 INFO L290 TraceCheckUtils]: 14: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,946 INFO L290 TraceCheckUtils]: 15: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,946 INFO L290 TraceCheckUtils]: 16: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,946 INFO L290 TraceCheckUtils]: 17: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,947 INFO L290 TraceCheckUtils]: 18: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,947 INFO L290 TraceCheckUtils]: 19: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,947 INFO L290 TraceCheckUtils]: 20: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,947 INFO L290 TraceCheckUtils]: 21: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,948 INFO L290 TraceCheckUtils]: 22: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,948 INFO L290 TraceCheckUtils]: 23: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,948 INFO L290 TraceCheckUtils]: 24: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,949 INFO L290 TraceCheckUtils]: 25: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,949 INFO L290 TraceCheckUtils]: 26: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,949 INFO L290 TraceCheckUtils]: 27: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,949 INFO L290 TraceCheckUtils]: 28: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,950 INFO L290 TraceCheckUtils]: 29: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,950 INFO L290 TraceCheckUtils]: 30: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,950 INFO L290 TraceCheckUtils]: 31: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,951 INFO L290 TraceCheckUtils]: 32: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,951 INFO L290 TraceCheckUtils]: 33: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,951 INFO L290 TraceCheckUtils]: 34: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,951 INFO L290 TraceCheckUtils]: 35: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,952 INFO L290 TraceCheckUtils]: 36: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,952 INFO L290 TraceCheckUtils]: 37: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,952 INFO L290 TraceCheckUtils]: 38: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,953 INFO L290 TraceCheckUtils]: 39: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,953 INFO L290 TraceCheckUtils]: 40: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,953 INFO L290 TraceCheckUtils]: 41: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,953 INFO L290 TraceCheckUtils]: 42: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,954 INFO L290 TraceCheckUtils]: 43: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,954 INFO L290 TraceCheckUtils]: 44: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,954 INFO L290 TraceCheckUtils]: 45: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,955 INFO L290 TraceCheckUtils]: 46: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,955 INFO L290 TraceCheckUtils]: 47: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,955 INFO L290 TraceCheckUtils]: 48: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,956 INFO L290 TraceCheckUtils]: 49: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,956 INFO L290 TraceCheckUtils]: 50: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,956 INFO L290 TraceCheckUtils]: 51: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,957 INFO L290 TraceCheckUtils]: 52: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,957 INFO L290 TraceCheckUtils]: 53: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,957 INFO L290 TraceCheckUtils]: 54: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,958 INFO L290 TraceCheckUtils]: 55: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,958 INFO L290 TraceCheckUtils]: 56: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,958 INFO L290 TraceCheckUtils]: 57: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,959 INFO L290 TraceCheckUtils]: 58: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,959 INFO L290 TraceCheckUtils]: 59: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,959 INFO L290 TraceCheckUtils]: 60: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,960 INFO L290 TraceCheckUtils]: 61: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,960 INFO L290 TraceCheckUtils]: 62: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,960 INFO L290 TraceCheckUtils]: 63: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,961 INFO L290 TraceCheckUtils]: 64: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,961 INFO L290 TraceCheckUtils]: 65: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,961 INFO L290 TraceCheckUtils]: 66: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,962 INFO L290 TraceCheckUtils]: 67: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,962 INFO L290 TraceCheckUtils]: 68: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,962 INFO L290 TraceCheckUtils]: 69: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,963 INFO L290 TraceCheckUtils]: 70: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,963 INFO L290 TraceCheckUtils]: 71: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,964 INFO L290 TraceCheckUtils]: 72: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,964 INFO L290 TraceCheckUtils]: 73: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,964 INFO L290 TraceCheckUtils]: 74: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,965 INFO L290 TraceCheckUtils]: 75: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,966 INFO L290 TraceCheckUtils]: 76: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,966 INFO L290 TraceCheckUtils]: 77: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,966 INFO L290 TraceCheckUtils]: 78: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,967 INFO L290 TraceCheckUtils]: 79: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,967 INFO L290 TraceCheckUtils]: 80: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,967 INFO L290 TraceCheckUtils]: 81: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,968 INFO L290 TraceCheckUtils]: 82: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,968 INFO L290 TraceCheckUtils]: 83: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,968 INFO L290 TraceCheckUtils]: 84: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,968 INFO L290 TraceCheckUtils]: 85: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,969 INFO L290 TraceCheckUtils]: 86: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,969 INFO L290 TraceCheckUtils]: 87: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,969 INFO L290 TraceCheckUtils]: 88: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,970 INFO L290 TraceCheckUtils]: 89: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,970 INFO L290 TraceCheckUtils]: 90: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,970 INFO L290 TraceCheckUtils]: 91: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,970 INFO L290 TraceCheckUtils]: 92: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,971 INFO L290 TraceCheckUtils]: 93: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,971 INFO L290 TraceCheckUtils]: 94: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,971 INFO L290 TraceCheckUtils]: 95: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,972 INFO L290 TraceCheckUtils]: 96: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t10_pc~0); {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,972 INFO L290 TraceCheckUtils]: 97: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,972 INFO L290 TraceCheckUtils]: 98: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,972 INFO L290 TraceCheckUtils]: 99: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:30,999 INFO L290 TraceCheckUtils]: 100: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,000 INFO L290 TraceCheckUtils]: 101: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,000 INFO L290 TraceCheckUtils]: 102: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,000 INFO L290 TraceCheckUtils]: 103: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,001 INFO L290 TraceCheckUtils]: 104: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,001 INFO L290 TraceCheckUtils]: 105: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,001 INFO L290 TraceCheckUtils]: 106: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,002 INFO L290 TraceCheckUtils]: 107: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,002 INFO L290 TraceCheckUtils]: 108: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t12_pc~0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,002 INFO L290 TraceCheckUtils]: 109: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,002 INFO L290 TraceCheckUtils]: 110: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,003 INFO L290 TraceCheckUtils]: 111: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,003 INFO L290 TraceCheckUtils]: 112: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,003 INFO L290 TraceCheckUtils]: 113: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,004 INFO L290 TraceCheckUtils]: 114: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,004 INFO L290 TraceCheckUtils]: 115: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {28753#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:31,004 INFO L290 TraceCheckUtils]: 116: Hoare triple {28753#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {28752#false} is VALID [2022-02-21 04:24:31,004 INFO L290 TraceCheckUtils]: 117: Hoare triple {28752#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,004 INFO L290 TraceCheckUtils]: 118: Hoare triple {28752#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,004 INFO L290 TraceCheckUtils]: 119: Hoare triple {28752#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,004 INFO L290 TraceCheckUtils]: 120: Hoare triple {28752#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 121: Hoare triple {28752#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 122: Hoare triple {28752#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 123: Hoare triple {28752#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 124: Hoare triple {28752#false} assume !(1 == ~T10_E~0); {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 125: Hoare triple {28752#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 126: Hoare triple {28752#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 127: Hoare triple {28752#false} assume 1 == ~E_1~0;~E_1~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 128: Hoare triple {28752#false} assume 1 == ~E_2~0;~E_2~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 129: Hoare triple {28752#false} assume 1 == ~E_3~0;~E_3~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 130: Hoare triple {28752#false} assume 1 == ~E_4~0;~E_4~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 131: Hoare triple {28752#false} assume 1 == ~E_5~0;~E_5~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 132: Hoare triple {28752#false} assume !(1 == ~E_6~0); {28752#false} is VALID [2022-02-21 04:24:31,005 INFO L290 TraceCheckUtils]: 133: Hoare triple {28752#false} assume 1 == ~E_7~0;~E_7~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,006 INFO L290 TraceCheckUtils]: 134: Hoare triple {28752#false} assume 1 == ~E_8~0;~E_8~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,006 INFO L290 TraceCheckUtils]: 135: Hoare triple {28752#false} assume 1 == ~E_9~0;~E_9~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,006 INFO L290 TraceCheckUtils]: 136: Hoare triple {28752#false} assume 1 == ~E_10~0;~E_10~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,006 INFO L290 TraceCheckUtils]: 137: Hoare triple {28752#false} assume 1 == ~E_11~0;~E_11~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,006 INFO L290 TraceCheckUtils]: 138: Hoare triple {28752#false} assume 1 == ~E_12~0;~E_12~0 := 2; {28752#false} is VALID [2022-02-21 04:24:31,006 INFO L290 TraceCheckUtils]: 139: Hoare triple {28752#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {28752#false} is VALID [2022-02-21 04:24:31,006 INFO L290 TraceCheckUtils]: 140: Hoare triple {28752#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {28752#false} is VALID [2022-02-21 04:24:31,006 INFO L290 TraceCheckUtils]: 141: Hoare triple {28752#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {28752#false} is VALID [2022-02-21 04:24:31,006 INFO L290 TraceCheckUtils]: 142: Hoare triple {28752#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {28752#false} is VALID [2022-02-21 04:24:31,007 INFO L290 TraceCheckUtils]: 143: Hoare triple {28752#false} assume !(0 == start_simulation_~tmp~3#1); {28752#false} is VALID [2022-02-21 04:24:31,007 INFO L290 TraceCheckUtils]: 144: Hoare triple {28752#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {28752#false} is VALID [2022-02-21 04:24:31,007 INFO L290 TraceCheckUtils]: 145: Hoare triple {28752#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {28752#false} is VALID [2022-02-21 04:24:31,007 INFO L290 TraceCheckUtils]: 146: Hoare triple {28752#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {28752#false} is VALID [2022-02-21 04:24:31,007 INFO L290 TraceCheckUtils]: 147: Hoare triple {28752#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {28752#false} is VALID [2022-02-21 04:24:31,007 INFO L290 TraceCheckUtils]: 148: Hoare triple {28752#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {28752#false} is VALID [2022-02-21 04:24:31,007 INFO L290 TraceCheckUtils]: 149: Hoare triple {28752#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {28752#false} is VALID [2022-02-21 04:24:31,007 INFO L290 TraceCheckUtils]: 150: Hoare triple {28752#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {28752#false} is VALID [2022-02-21 04:24:31,007 INFO L290 TraceCheckUtils]: 151: Hoare triple {28752#false} assume !(0 != start_simulation_~tmp___0~1#1); {28752#false} is VALID [2022-02-21 04:24:31,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:31,008 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:31,008 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281067654] [2022-02-21 04:24:31,008 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281067654] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:31,008 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:31,008 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:31,008 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369476537] [2022-02-21 04:24:31,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:31,008 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:31,008 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:31,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:31,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:31,009 INFO L87 Difference]: Start difference. First operand 1688 states and 2501 transitions. cyclomatic complexity: 814 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:32,265 INFO L93 Difference]: Finished difference Result 1688 states and 2500 transitions. [2022-02-21 04:24:32,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:32,265 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,361 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:32,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2500 transitions. [2022-02-21 04:24:32,437 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:32,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2500 transitions. [2022-02-21 04:24:32,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:32,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:32,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2500 transitions. [2022-02-21 04:24:32,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:32,507 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2022-02-21 04:24:32,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2500 transitions. [2022-02-21 04:24:32,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:32,520 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:32,522 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2500 transitions. Second operand has 1688 states, 1688 states have (on average 1.481042654028436) internal successors, (2500), 1687 states have internal predecessors, (2500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,523 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2500 transitions. Second operand has 1688 states, 1688 states have (on average 1.481042654028436) internal successors, (2500), 1687 states have internal predecessors, (2500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,524 INFO L87 Difference]: Start difference. First operand 1688 states and 2500 transitions. Second operand has 1688 states, 1688 states have (on average 1.481042654028436) internal successors, (2500), 1687 states have internal predecessors, (2500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:32,583 INFO L93 Difference]: Finished difference Result 1688 states and 2500 transitions. [2022-02-21 04:24:32,583 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2500 transitions. [2022-02-21 04:24:32,584 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:32,584 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:32,586 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.481042654028436) internal successors, (2500), 1687 states have internal predecessors, (2500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2500 transitions. [2022-02-21 04:24:32,587 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.481042654028436) internal successors, (2500), 1687 states have internal predecessors, (2500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2500 transitions. [2022-02-21 04:24:32,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:32,649 INFO L93 Difference]: Finished difference Result 1688 states and 2500 transitions. [2022-02-21 04:24:32,649 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2500 transitions. [2022-02-21 04:24:32,650 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:32,651 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:32,651 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:32,651 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:32,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.481042654028436) internal successors, (2500), 1687 states have internal predecessors, (2500), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:32,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2500 transitions. [2022-02-21 04:24:32,712 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2022-02-21 04:24:32,712 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2500 transitions. [2022-02-21 04:24:32,712 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:32,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2500 transitions. [2022-02-21 04:24:32,715 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:32,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:32,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:32,717 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:32,717 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:32,717 INFO L791 eck$LassoCheckResult]: Stem: 31245#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 31246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 32099#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31591#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31398#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 31399#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31484#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31785#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31907#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31908#L841-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 30696#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 30697#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 31845#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31291#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31292#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31198#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31199#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31587#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30940#L1174 assume !(0 == ~M_E~0); 30941#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30792#L1179-1 assume !(0 == ~T2_E~0); 30694#L1184-1 assume !(0 == ~T3_E~0); 30695#L1189-1 assume !(0 == ~T4_E~0); 30733#L1194-1 assume !(0 == ~T5_E~0); 30833#L1199-1 assume !(0 == ~T6_E~0); 31728#L1204-1 assume !(0 == ~T7_E~0); 31647#L1209-1 assume !(0 == ~T8_E~0); 31648#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32036#L1219-1 assume !(0 == ~T10_E~0); 32121#L1224-1 assume !(0 == ~T11_E~0); 31058#L1229-1 assume !(0 == ~T12_E~0); 30619#L1234-1 assume !(0 == ~E_1~0); 30620#L1239-1 assume !(0 == ~E_2~0); 30653#L1244-1 assume !(0 == ~E_3~0); 30654#L1249-1 assume !(0 == ~E_4~0); 31315#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 30549#L1259-1 assume !(0 == ~E_6~0); 30504#L1264-1 assume !(0 == ~E_7~0); 30505#L1269-1 assume !(0 == ~E_8~0); 32126#L1274-1 assume !(0 == ~E_9~0); 32061#L1279-1 assume !(0 == ~E_10~0); 30737#L1284-1 assume !(0 == ~E_11~0); 30738#L1289-1 assume !(0 == ~E_12~0); 31367#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31368#L566 assume 1 == ~m_pc~0; 30521#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30522#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31676#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31677#L1455 assume !(0 != activate_threads_~tmp~1#1); 30967#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30968#L585 assume 1 == ~t1_pc~0; 30616#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30617#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31617#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31618#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 32086#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32084#L604 assume !(1 == ~t2_pc~0); 31696#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31697#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31230#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31231#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31868#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31869#L623 assume 1 == ~t3_pc~0; 31145#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30485#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31295#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31296#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 31903#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30518#L642 assume !(1 == ~t4_pc~0); 30519#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 30984#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30985#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30590#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 30591#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31708#L661 assume 1 == ~t5_pc~0; 30755#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30756#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30717#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30718#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 31737#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31738#L680 assume !(1 == ~t6_pc~0); 31178#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31179#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31440#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31441#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 31969#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32082#L699 assume 1 == ~t7_pc~0; 31568#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31569#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30745#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30746#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 31470#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31369#L718 assume !(1 == ~t8_pc~0); 31370#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 30731#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30732#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30773#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 30774#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30907#L737 assume 1 == ~t9_pc~0; 31772#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31042#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31643#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31644#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 31216#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31217#L756 assume 1 == ~t10_pc~0; 31796#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31462#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30448#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30449#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 31024#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31025#L775 assume !(1 == ~t11_pc~0); 31279#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 31280#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30901#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30665#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30666#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30852#L794 assume 1 == ~t12_pc~0; 30692#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30670#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31863#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30818#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 30819#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31298#L1307 assume !(1 == ~M_E~0); 31299#L1307-2 assume !(1 == ~T1_E~0); 31410#L1312-1 assume !(1 == ~T2_E~0); 31329#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31330#L1322-1 assume !(1 == ~T4_E~0); 31033#L1327-1 assume !(1 == ~T5_E~0); 31034#L1332-1 assume !(1 == ~T6_E~0); 31572#L1337-1 assume !(1 == ~T7_E~0); 31534#L1342-1 assume !(1 == ~T8_E~0); 31535#L1347-1 assume !(1 == ~T9_E~0); 31932#L1352-1 assume !(1 == ~T10_E~0); 31805#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31196#L1362-1 assume !(1 == ~T12_E~0); 31197#L1367-1 assume !(1 == ~E_1~0); 30834#L1372-1 assume !(1 == ~E_2~0); 30835#L1377-1 assume !(1 == ~E_3~0); 31128#L1382-1 assume !(1 == ~E_4~0); 31129#L1387-1 assume !(1 == ~E_5~0); 31698#L1392-1 assume !(1 == ~E_6~0); 31148#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 31149#L1402-1 assume !(1 == ~E_8~0); 30845#L1407-1 assume !(1 == ~E_9~0); 30846#L1412-1 assume !(1 == ~E_10~0); 31861#L1417-1 assume !(1 == ~E_11~0); 31862#L1422-1 assume !(1 == ~E_12~0); 32080#L1427-1 assume { :end_inline_reset_delta_events } true; 30649#L1768-2 [2022-02-21 04:24:32,718 INFO L793 eck$LassoCheckResult]: Loop: 30649#L1768-2 assume !false; 30650#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31388#L1149 assume !false; 31760#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 31913#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 31039#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30945#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 30946#L976 assume !(0 != eval_~tmp~0#1); 32079#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32089#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31880#L1174-3 assume !(0 == ~M_E~0); 31873#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31622#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31623#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31806#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31457#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30807#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30808#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31049#L1209-3 assume !(0 == ~T8_E~0); 30469#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30470#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31228#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 31229#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31247#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30657#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30658#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31101#L1249-3 assume !(0 == ~E_4~0); 31560#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32032#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31674#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 30663#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 30664#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32059#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31226#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31227#L1289-3 assume !(0 == ~E_12~0); 31215#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30891#L566-39 assume 1 == ~m_pc~0; 30892#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31494#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31206#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31207#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31749#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31750#L585-39 assume !(1 == ~t1_pc~0); 30899#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 30900#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30975#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30976#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31782#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31475#L604-39 assume 1 == ~t2_pc~0; 31476#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31107#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31108#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31525#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31526#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31090#L623-39 assume 1 == ~t3_pc~0; 30486#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30488#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31766#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30942#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30943#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31714#L642-39 assume 1 == ~t4_pc~0; 31285#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31286#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30814#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30815#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31912#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30863#L661-39 assume 1 == ~t5_pc~0; 30864#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30495#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31855#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31856#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31769#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31770#L680-39 assume 1 == ~t6_pc~0; 30556#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30557#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31699#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31022#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31023#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32037#L699-39 assume 1 == ~t7_pc~0; 31459#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31181#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31182#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31865#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31986#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31984#L718-39 assume 1 == ~t8_pc~0; 31373#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31374#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31306#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31307#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 31609#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31578#L737-39 assume 1 == ~t9_pc~0; 31003#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31004#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31293#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32060#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31961#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31904#L756-39 assume 1 == ~t10_pc~0; 31905#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31386#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31130#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31131#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31263#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30603#L775-39 assume 1 == ~t11_pc~0; 30604#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31256#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31257#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32119#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31667#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31314#L794-39 assume !(1 == ~t12_pc~0); 30999#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 31000#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31820#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31721#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30545#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30546#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32013#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32014#L1312-3 assume !(1 == ~T2_E~0); 32125#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31739#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31740#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30684#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30655#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30656#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31402#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31527#L1352-3 assume !(1 == ~T10_E~0); 31528#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31967#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32118#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32109#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30482#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30483#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31114#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31115#L1392-3 assume !(1 == ~E_6~0); 31830#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32076#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31493#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 30769#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 30770#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 31418#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31419#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30779#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30780#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31646#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 31498#L1787 assume !(0 == start_simulation_~tmp~3#1); 31499#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 32022#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30750#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 31545#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 31546#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31097#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31098#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 31099#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 30649#L1768-2 [2022-02-21 04:24:32,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:32,718 INFO L85 PathProgramCache]: Analyzing trace with hash -1474786415, now seen corresponding path program 1 times [2022-02-21 04:24:32,718 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:32,719 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199669944] [2022-02-21 04:24:32,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:32,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:32,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:32,738 INFO L290 TraceCheckUtils]: 0: Hoare triple {35509#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {35509#true} is VALID [2022-02-21 04:24:32,738 INFO L290 TraceCheckUtils]: 1: Hoare triple {35509#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {35511#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:32,738 INFO L290 TraceCheckUtils]: 2: Hoare triple {35511#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {35511#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:32,739 INFO L290 TraceCheckUtils]: 3: Hoare triple {35511#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {35511#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:32,739 INFO L290 TraceCheckUtils]: 4: Hoare triple {35511#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {35511#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:32,739 INFO L290 TraceCheckUtils]: 5: Hoare triple {35511#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {35511#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:32,740 INFO L290 TraceCheckUtils]: 6: Hoare triple {35511#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {35511#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:32,740 INFO L290 TraceCheckUtils]: 7: Hoare triple {35511#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {35511#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:32,740 INFO L290 TraceCheckUtils]: 8: Hoare triple {35511#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {35511#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:32,740 INFO L290 TraceCheckUtils]: 9: Hoare triple {35511#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {35510#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 10: Hoare triple {35510#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {35510#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 11: Hoare triple {35510#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {35510#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 12: Hoare triple {35510#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {35510#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 13: Hoare triple {35510#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {35510#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 14: Hoare triple {35510#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {35510#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 15: Hoare triple {35510#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {35510#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 16: Hoare triple {35510#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {35510#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 17: Hoare triple {35510#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {35510#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 18: Hoare triple {35510#false} assume !(0 == ~M_E~0); {35510#false} is VALID [2022-02-21 04:24:32,741 INFO L290 TraceCheckUtils]: 19: Hoare triple {35510#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {35510#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 20: Hoare triple {35510#false} assume !(0 == ~T2_E~0); {35510#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 21: Hoare triple {35510#false} assume !(0 == ~T3_E~0); {35510#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 22: Hoare triple {35510#false} assume !(0 == ~T4_E~0); {35510#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 23: Hoare triple {35510#false} assume !(0 == ~T5_E~0); {35510#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 24: Hoare triple {35510#false} assume !(0 == ~T6_E~0); {35510#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 25: Hoare triple {35510#false} assume !(0 == ~T7_E~0); {35510#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 26: Hoare triple {35510#false} assume !(0 == ~T8_E~0); {35510#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 27: Hoare triple {35510#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {35510#false} is VALID [2022-02-21 04:24:32,742 INFO L290 TraceCheckUtils]: 28: Hoare triple {35510#false} assume !(0 == ~T10_E~0); {35510#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 29: Hoare triple {35510#false} assume !(0 == ~T11_E~0); {35510#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 30: Hoare triple {35510#false} assume !(0 == ~T12_E~0); {35510#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 31: Hoare triple {35510#false} assume !(0 == ~E_1~0); {35510#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 32: Hoare triple {35510#false} assume !(0 == ~E_2~0); {35510#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 33: Hoare triple {35510#false} assume !(0 == ~E_3~0); {35510#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 34: Hoare triple {35510#false} assume !(0 == ~E_4~0); {35510#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 35: Hoare triple {35510#false} assume 0 == ~E_5~0;~E_5~0 := 1; {35510#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 36: Hoare triple {35510#false} assume !(0 == ~E_6~0); {35510#false} is VALID [2022-02-21 04:24:32,743 INFO L290 TraceCheckUtils]: 37: Hoare triple {35510#false} assume !(0 == ~E_7~0); {35510#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 38: Hoare triple {35510#false} assume !(0 == ~E_8~0); {35510#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 39: Hoare triple {35510#false} assume !(0 == ~E_9~0); {35510#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 40: Hoare triple {35510#false} assume !(0 == ~E_10~0); {35510#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 41: Hoare triple {35510#false} assume !(0 == ~E_11~0); {35510#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 42: Hoare triple {35510#false} assume !(0 == ~E_12~0); {35510#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 43: Hoare triple {35510#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {35510#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 44: Hoare triple {35510#false} assume 1 == ~m_pc~0; {35510#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 45: Hoare triple {35510#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {35510#false} is VALID [2022-02-21 04:24:32,744 INFO L290 TraceCheckUtils]: 46: Hoare triple {35510#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {35510#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 47: Hoare triple {35510#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {35510#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 48: Hoare triple {35510#false} assume !(0 != activate_threads_~tmp~1#1); {35510#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 49: Hoare triple {35510#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {35510#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 50: Hoare triple {35510#false} assume 1 == ~t1_pc~0; {35510#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 51: Hoare triple {35510#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {35510#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 52: Hoare triple {35510#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {35510#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 53: Hoare triple {35510#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {35510#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 54: Hoare triple {35510#false} assume !(0 != activate_threads_~tmp___0~0#1); {35510#false} is VALID [2022-02-21 04:24:32,745 INFO L290 TraceCheckUtils]: 55: Hoare triple {35510#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {35510#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 56: Hoare triple {35510#false} assume !(1 == ~t2_pc~0); {35510#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 57: Hoare triple {35510#false} is_transmit2_triggered_~__retres1~2#1 := 0; {35510#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 58: Hoare triple {35510#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {35510#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 59: Hoare triple {35510#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {35510#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 60: Hoare triple {35510#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {35510#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 61: Hoare triple {35510#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {35510#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 62: Hoare triple {35510#false} assume 1 == ~t3_pc~0; {35510#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 63: Hoare triple {35510#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {35510#false} is VALID [2022-02-21 04:24:32,746 INFO L290 TraceCheckUtils]: 64: Hoare triple {35510#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {35510#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 65: Hoare triple {35510#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {35510#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 66: Hoare triple {35510#false} assume !(0 != activate_threads_~tmp___2~0#1); {35510#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 67: Hoare triple {35510#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {35510#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 68: Hoare triple {35510#false} assume !(1 == ~t4_pc~0); {35510#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 69: Hoare triple {35510#false} is_transmit4_triggered_~__retres1~4#1 := 0; {35510#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 70: Hoare triple {35510#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {35510#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 71: Hoare triple {35510#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {35510#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 72: Hoare triple {35510#false} assume !(0 != activate_threads_~tmp___3~0#1); {35510#false} is VALID [2022-02-21 04:24:32,747 INFO L290 TraceCheckUtils]: 73: Hoare triple {35510#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {35510#false} is VALID [2022-02-21 04:24:32,748 INFO L290 TraceCheckUtils]: 74: Hoare triple {35510#false} assume 1 == ~t5_pc~0; {35510#false} is VALID [2022-02-21 04:24:32,748 INFO L290 TraceCheckUtils]: 75: Hoare triple {35510#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {35510#false} is VALID [2022-02-21 04:24:32,748 INFO L290 TraceCheckUtils]: 76: Hoare triple {35510#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {35510#false} is VALID [2022-02-21 04:24:32,748 INFO L290 TraceCheckUtils]: 77: Hoare triple {35510#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {35510#false} is VALID [2022-02-21 04:24:32,748 INFO L290 TraceCheckUtils]: 78: Hoare triple {35510#false} assume !(0 != activate_threads_~tmp___4~0#1); {35510#false} is VALID [2022-02-21 04:24:32,748 INFO L290 TraceCheckUtils]: 79: Hoare triple {35510#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {35510#false} is VALID [2022-02-21 04:24:32,748 INFO L290 TraceCheckUtils]: 80: Hoare triple {35510#false} assume !(1 == ~t6_pc~0); {35510#false} is VALID [2022-02-21 04:24:32,748 INFO L290 TraceCheckUtils]: 81: Hoare triple {35510#false} is_transmit6_triggered_~__retres1~6#1 := 0; {35510#false} is VALID [2022-02-21 04:24:32,748 INFO L290 TraceCheckUtils]: 82: Hoare triple {35510#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {35510#false} is VALID [2022-02-21 04:24:32,749 INFO L290 TraceCheckUtils]: 83: Hoare triple {35510#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {35510#false} is VALID [2022-02-21 04:24:32,749 INFO L290 TraceCheckUtils]: 84: Hoare triple {35510#false} assume !(0 != activate_threads_~tmp___5~0#1); {35510#false} is VALID [2022-02-21 04:24:32,749 INFO L290 TraceCheckUtils]: 85: Hoare triple {35510#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {35510#false} is VALID [2022-02-21 04:24:32,749 INFO L290 TraceCheckUtils]: 86: Hoare triple {35510#false} assume 1 == ~t7_pc~0; {35510#false} is VALID [2022-02-21 04:24:32,749 INFO L290 TraceCheckUtils]: 87: Hoare triple {35510#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {35510#false} is VALID [2022-02-21 04:24:32,749 INFO L290 TraceCheckUtils]: 88: Hoare triple {35510#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {35510#false} is VALID [2022-02-21 04:24:32,749 INFO L290 TraceCheckUtils]: 89: Hoare triple {35510#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {35510#false} is VALID [2022-02-21 04:24:32,749 INFO L290 TraceCheckUtils]: 90: Hoare triple {35510#false} assume !(0 != activate_threads_~tmp___6~0#1); {35510#false} is VALID [2022-02-21 04:24:32,749 INFO L290 TraceCheckUtils]: 91: Hoare triple {35510#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {35510#false} is VALID [2022-02-21 04:24:32,750 INFO L290 TraceCheckUtils]: 92: Hoare triple {35510#false} assume !(1 == ~t8_pc~0); {35510#false} is VALID [2022-02-21 04:24:32,750 INFO L290 TraceCheckUtils]: 93: Hoare triple {35510#false} is_transmit8_triggered_~__retres1~8#1 := 0; {35510#false} is VALID [2022-02-21 04:24:32,750 INFO L290 TraceCheckUtils]: 94: Hoare triple {35510#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {35510#false} is VALID [2022-02-21 04:24:32,750 INFO L290 TraceCheckUtils]: 95: Hoare triple {35510#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {35510#false} is VALID [2022-02-21 04:24:32,750 INFO L290 TraceCheckUtils]: 96: Hoare triple {35510#false} assume !(0 != activate_threads_~tmp___7~0#1); {35510#false} is VALID [2022-02-21 04:24:32,750 INFO L290 TraceCheckUtils]: 97: Hoare triple {35510#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {35510#false} is VALID [2022-02-21 04:24:32,750 INFO L290 TraceCheckUtils]: 98: Hoare triple {35510#false} assume 1 == ~t9_pc~0; {35510#false} is VALID [2022-02-21 04:24:32,750 INFO L290 TraceCheckUtils]: 99: Hoare triple {35510#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {35510#false} is VALID [2022-02-21 04:24:32,750 INFO L290 TraceCheckUtils]: 100: Hoare triple {35510#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {35510#false} is VALID [2022-02-21 04:24:32,751 INFO L290 TraceCheckUtils]: 101: Hoare triple {35510#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {35510#false} is VALID [2022-02-21 04:24:32,751 INFO L290 TraceCheckUtils]: 102: Hoare triple {35510#false} assume !(0 != activate_threads_~tmp___8~0#1); {35510#false} is VALID [2022-02-21 04:24:32,751 INFO L290 TraceCheckUtils]: 103: Hoare triple {35510#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {35510#false} is VALID [2022-02-21 04:24:32,751 INFO L290 TraceCheckUtils]: 104: Hoare triple {35510#false} assume 1 == ~t10_pc~0; {35510#false} is VALID [2022-02-21 04:24:32,751 INFO L290 TraceCheckUtils]: 105: Hoare triple {35510#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {35510#false} is VALID [2022-02-21 04:24:32,751 INFO L290 TraceCheckUtils]: 106: Hoare triple {35510#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {35510#false} is VALID [2022-02-21 04:24:32,751 INFO L290 TraceCheckUtils]: 107: Hoare triple {35510#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {35510#false} is VALID [2022-02-21 04:24:32,751 INFO L290 TraceCheckUtils]: 108: Hoare triple {35510#false} assume !(0 != activate_threads_~tmp___9~0#1); {35510#false} is VALID [2022-02-21 04:24:32,751 INFO L290 TraceCheckUtils]: 109: Hoare triple {35510#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {35510#false} is VALID [2022-02-21 04:24:32,752 INFO L290 TraceCheckUtils]: 110: Hoare triple {35510#false} assume !(1 == ~t11_pc~0); {35510#false} is VALID [2022-02-21 04:24:32,752 INFO L290 TraceCheckUtils]: 111: Hoare triple {35510#false} is_transmit11_triggered_~__retres1~11#1 := 0; {35510#false} is VALID [2022-02-21 04:24:32,752 INFO L290 TraceCheckUtils]: 112: Hoare triple {35510#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {35510#false} is VALID [2022-02-21 04:24:32,752 INFO L290 TraceCheckUtils]: 113: Hoare triple {35510#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {35510#false} is VALID [2022-02-21 04:24:32,752 INFO L290 TraceCheckUtils]: 114: Hoare triple {35510#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {35510#false} is VALID [2022-02-21 04:24:32,752 INFO L290 TraceCheckUtils]: 115: Hoare triple {35510#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {35510#false} is VALID [2022-02-21 04:24:32,752 INFO L290 TraceCheckUtils]: 116: Hoare triple {35510#false} assume 1 == ~t12_pc~0; {35510#false} is VALID [2022-02-21 04:24:32,752 INFO L290 TraceCheckUtils]: 117: Hoare triple {35510#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {35510#false} is VALID [2022-02-21 04:24:32,752 INFO L290 TraceCheckUtils]: 118: Hoare triple {35510#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {35510#false} is VALID [2022-02-21 04:24:32,753 INFO L290 TraceCheckUtils]: 119: Hoare triple {35510#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {35510#false} is VALID [2022-02-21 04:24:32,753 INFO L290 TraceCheckUtils]: 120: Hoare triple {35510#false} assume !(0 != activate_threads_~tmp___11~0#1); {35510#false} is VALID [2022-02-21 04:24:32,753 INFO L290 TraceCheckUtils]: 121: Hoare triple {35510#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {35510#false} is VALID [2022-02-21 04:24:32,753 INFO L290 TraceCheckUtils]: 122: Hoare triple {35510#false} assume !(1 == ~M_E~0); {35510#false} is VALID [2022-02-21 04:24:32,753 INFO L290 TraceCheckUtils]: 123: Hoare triple {35510#false} assume !(1 == ~T1_E~0); {35510#false} is VALID [2022-02-21 04:24:32,753 INFO L290 TraceCheckUtils]: 124: Hoare triple {35510#false} assume !(1 == ~T2_E~0); {35510#false} is VALID [2022-02-21 04:24:32,753 INFO L290 TraceCheckUtils]: 125: Hoare triple {35510#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {35510#false} is VALID [2022-02-21 04:24:32,753 INFO L290 TraceCheckUtils]: 126: Hoare triple {35510#false} assume !(1 == ~T4_E~0); {35510#false} is VALID [2022-02-21 04:24:32,753 INFO L290 TraceCheckUtils]: 127: Hoare triple {35510#false} assume !(1 == ~T5_E~0); {35510#false} is VALID [2022-02-21 04:24:32,754 INFO L290 TraceCheckUtils]: 128: Hoare triple {35510#false} assume !(1 == ~T6_E~0); {35510#false} is VALID [2022-02-21 04:24:32,754 INFO L290 TraceCheckUtils]: 129: Hoare triple {35510#false} assume !(1 == ~T7_E~0); {35510#false} is VALID [2022-02-21 04:24:32,754 INFO L290 TraceCheckUtils]: 130: Hoare triple {35510#false} assume !(1 == ~T8_E~0); {35510#false} is VALID [2022-02-21 04:24:32,754 INFO L290 TraceCheckUtils]: 131: Hoare triple {35510#false} assume !(1 == ~T9_E~0); {35510#false} is VALID [2022-02-21 04:24:32,754 INFO L290 TraceCheckUtils]: 132: Hoare triple {35510#false} assume !(1 == ~T10_E~0); {35510#false} is VALID [2022-02-21 04:24:32,754 INFO L290 TraceCheckUtils]: 133: Hoare triple {35510#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {35510#false} is VALID [2022-02-21 04:24:32,754 INFO L290 TraceCheckUtils]: 134: Hoare triple {35510#false} assume !(1 == ~T12_E~0); {35510#false} is VALID [2022-02-21 04:24:32,754 INFO L290 TraceCheckUtils]: 135: Hoare triple {35510#false} assume !(1 == ~E_1~0); {35510#false} is VALID [2022-02-21 04:24:32,754 INFO L290 TraceCheckUtils]: 136: Hoare triple {35510#false} assume !(1 == ~E_2~0); {35510#false} is VALID [2022-02-21 04:24:32,755 INFO L290 TraceCheckUtils]: 137: Hoare triple {35510#false} assume !(1 == ~E_3~0); {35510#false} is VALID [2022-02-21 04:24:32,755 INFO L290 TraceCheckUtils]: 138: Hoare triple {35510#false} assume !(1 == ~E_4~0); {35510#false} is VALID [2022-02-21 04:24:32,755 INFO L290 TraceCheckUtils]: 139: Hoare triple {35510#false} assume !(1 == ~E_5~0); {35510#false} is VALID [2022-02-21 04:24:32,755 INFO L290 TraceCheckUtils]: 140: Hoare triple {35510#false} assume !(1 == ~E_6~0); {35510#false} is VALID [2022-02-21 04:24:32,755 INFO L290 TraceCheckUtils]: 141: Hoare triple {35510#false} assume 1 == ~E_7~0;~E_7~0 := 2; {35510#false} is VALID [2022-02-21 04:24:32,755 INFO L290 TraceCheckUtils]: 142: Hoare triple {35510#false} assume !(1 == ~E_8~0); {35510#false} is VALID [2022-02-21 04:24:32,755 INFO L290 TraceCheckUtils]: 143: Hoare triple {35510#false} assume !(1 == ~E_9~0); {35510#false} is VALID [2022-02-21 04:24:32,755 INFO L290 TraceCheckUtils]: 144: Hoare triple {35510#false} assume !(1 == ~E_10~0); {35510#false} is VALID [2022-02-21 04:24:32,755 INFO L290 TraceCheckUtils]: 145: Hoare triple {35510#false} assume !(1 == ~E_11~0); {35510#false} is VALID [2022-02-21 04:24:32,756 INFO L290 TraceCheckUtils]: 146: Hoare triple {35510#false} assume !(1 == ~E_12~0); {35510#false} is VALID [2022-02-21 04:24:32,756 INFO L290 TraceCheckUtils]: 147: Hoare triple {35510#false} assume { :end_inline_reset_delta_events } true; {35510#false} is VALID [2022-02-21 04:24:32,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:32,756 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:32,757 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199669944] [2022-02-21 04:24:32,757 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1199669944] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:32,757 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:32,757 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:32,757 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258352466] [2022-02-21 04:24:32,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:32,757 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:32,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:32,758 INFO L85 PathProgramCache]: Analyzing trace with hash 95558179, now seen corresponding path program 1 times [2022-02-21 04:24:32,758 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:32,761 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283517099] [2022-02-21 04:24:32,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:32,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:32,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:32,793 INFO L290 TraceCheckUtils]: 0: Hoare triple {35512#true} assume !false; {35512#true} is VALID [2022-02-21 04:24:32,793 INFO L290 TraceCheckUtils]: 1: Hoare triple {35512#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {35512#true} is VALID [2022-02-21 04:24:32,793 INFO L290 TraceCheckUtils]: 2: Hoare triple {35512#true} assume !false; {35512#true} is VALID [2022-02-21 04:24:32,794 INFO L290 TraceCheckUtils]: 3: Hoare triple {35512#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {35512#true} is VALID [2022-02-21 04:24:32,794 INFO L290 TraceCheckUtils]: 4: Hoare triple {35512#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {35512#true} is VALID [2022-02-21 04:24:32,794 INFO L290 TraceCheckUtils]: 5: Hoare triple {35512#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {35512#true} is VALID [2022-02-21 04:24:32,794 INFO L290 TraceCheckUtils]: 6: Hoare triple {35512#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {35512#true} is VALID [2022-02-21 04:24:32,794 INFO L290 TraceCheckUtils]: 7: Hoare triple {35512#true} assume !(0 != eval_~tmp~0#1); {35512#true} is VALID [2022-02-21 04:24:32,794 INFO L290 TraceCheckUtils]: 8: Hoare triple {35512#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {35512#true} is VALID [2022-02-21 04:24:32,794 INFO L290 TraceCheckUtils]: 9: Hoare triple {35512#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {35512#true} is VALID [2022-02-21 04:24:32,794 INFO L290 TraceCheckUtils]: 10: Hoare triple {35512#true} assume !(0 == ~M_E~0); {35512#true} is VALID [2022-02-21 04:24:32,795 INFO L290 TraceCheckUtils]: 11: Hoare triple {35512#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {35512#true} is VALID [2022-02-21 04:24:32,795 INFO L290 TraceCheckUtils]: 12: Hoare triple {35512#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,795 INFO L290 TraceCheckUtils]: 13: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,795 INFO L290 TraceCheckUtils]: 14: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,796 INFO L290 TraceCheckUtils]: 15: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,796 INFO L290 TraceCheckUtils]: 16: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,796 INFO L290 TraceCheckUtils]: 17: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,796 INFO L290 TraceCheckUtils]: 18: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,797 INFO L290 TraceCheckUtils]: 19: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,797 INFO L290 TraceCheckUtils]: 20: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,797 INFO L290 TraceCheckUtils]: 21: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,798 INFO L290 TraceCheckUtils]: 22: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,798 INFO L290 TraceCheckUtils]: 23: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,798 INFO L290 TraceCheckUtils]: 24: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,798 INFO L290 TraceCheckUtils]: 25: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,799 INFO L290 TraceCheckUtils]: 26: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,799 INFO L290 TraceCheckUtils]: 27: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,799 INFO L290 TraceCheckUtils]: 28: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,799 INFO L290 TraceCheckUtils]: 29: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,800 INFO L290 TraceCheckUtils]: 30: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,800 INFO L290 TraceCheckUtils]: 31: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,800 INFO L290 TraceCheckUtils]: 32: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,801 INFO L290 TraceCheckUtils]: 33: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,801 INFO L290 TraceCheckUtils]: 34: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,801 INFO L290 TraceCheckUtils]: 35: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,801 INFO L290 TraceCheckUtils]: 36: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,802 INFO L290 TraceCheckUtils]: 37: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,802 INFO L290 TraceCheckUtils]: 38: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,802 INFO L290 TraceCheckUtils]: 39: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,802 INFO L290 TraceCheckUtils]: 40: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,803 INFO L290 TraceCheckUtils]: 41: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,803 INFO L290 TraceCheckUtils]: 42: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,803 INFO L290 TraceCheckUtils]: 43: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,804 INFO L290 TraceCheckUtils]: 44: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,804 INFO L290 TraceCheckUtils]: 45: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,804 INFO L290 TraceCheckUtils]: 46: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,804 INFO L290 TraceCheckUtils]: 47: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,805 INFO L290 TraceCheckUtils]: 48: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,805 INFO L290 TraceCheckUtils]: 49: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,805 INFO L290 TraceCheckUtils]: 50: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,805 INFO L290 TraceCheckUtils]: 51: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,806 INFO L290 TraceCheckUtils]: 52: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,806 INFO L290 TraceCheckUtils]: 53: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,806 INFO L290 TraceCheckUtils]: 54: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,807 INFO L290 TraceCheckUtils]: 55: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,807 INFO L290 TraceCheckUtils]: 56: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,807 INFO L290 TraceCheckUtils]: 57: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,807 INFO L290 TraceCheckUtils]: 58: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,808 INFO L290 TraceCheckUtils]: 59: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,808 INFO L290 TraceCheckUtils]: 60: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,808 INFO L290 TraceCheckUtils]: 61: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,808 INFO L290 TraceCheckUtils]: 62: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,809 INFO L290 TraceCheckUtils]: 63: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,809 INFO L290 TraceCheckUtils]: 64: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,809 INFO L290 TraceCheckUtils]: 65: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,810 INFO L290 TraceCheckUtils]: 66: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,810 INFO L290 TraceCheckUtils]: 67: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,810 INFO L290 TraceCheckUtils]: 68: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,810 INFO L290 TraceCheckUtils]: 69: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,811 INFO L290 TraceCheckUtils]: 70: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,811 INFO L290 TraceCheckUtils]: 71: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,811 INFO L290 TraceCheckUtils]: 72: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,812 INFO L290 TraceCheckUtils]: 73: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,812 INFO L290 TraceCheckUtils]: 74: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,812 INFO L290 TraceCheckUtils]: 75: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,812 INFO L290 TraceCheckUtils]: 76: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,813 INFO L290 TraceCheckUtils]: 77: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,813 INFO L290 TraceCheckUtils]: 78: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,813 INFO L290 TraceCheckUtils]: 79: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,813 INFO L290 TraceCheckUtils]: 80: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,814 INFO L290 TraceCheckUtils]: 81: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,814 INFO L290 TraceCheckUtils]: 82: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,814 INFO L290 TraceCheckUtils]: 83: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,815 INFO L290 TraceCheckUtils]: 84: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,815 INFO L290 TraceCheckUtils]: 85: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,815 INFO L290 TraceCheckUtils]: 86: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,815 INFO L290 TraceCheckUtils]: 87: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,816 INFO L290 TraceCheckUtils]: 88: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,816 INFO L290 TraceCheckUtils]: 89: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,816 INFO L290 TraceCheckUtils]: 90: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,817 INFO L290 TraceCheckUtils]: 91: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,817 INFO L290 TraceCheckUtils]: 92: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,817 INFO L290 TraceCheckUtils]: 93: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,817 INFO L290 TraceCheckUtils]: 94: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,818 INFO L290 TraceCheckUtils]: 95: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,818 INFO L290 TraceCheckUtils]: 96: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,818 INFO L290 TraceCheckUtils]: 97: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,818 INFO L290 TraceCheckUtils]: 98: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,819 INFO L290 TraceCheckUtils]: 99: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,819 INFO L290 TraceCheckUtils]: 100: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,819 INFO L290 TraceCheckUtils]: 101: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,820 INFO L290 TraceCheckUtils]: 102: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,820 INFO L290 TraceCheckUtils]: 103: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,820 INFO L290 TraceCheckUtils]: 104: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,820 INFO L290 TraceCheckUtils]: 105: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,821 INFO L290 TraceCheckUtils]: 106: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,821 INFO L290 TraceCheckUtils]: 107: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,821 INFO L290 TraceCheckUtils]: 108: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t12_pc~0); {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,821 INFO L290 TraceCheckUtils]: 109: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,822 INFO L290 TraceCheckUtils]: 110: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,822 INFO L290 TraceCheckUtils]: 111: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,822 INFO L290 TraceCheckUtils]: 112: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,823 INFO L290 TraceCheckUtils]: 113: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,823 INFO L290 TraceCheckUtils]: 114: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,823 INFO L290 TraceCheckUtils]: 115: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {35514#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:32,823 INFO L290 TraceCheckUtils]: 116: Hoare triple {35514#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {35513#false} is VALID [2022-02-21 04:24:32,824 INFO L290 TraceCheckUtils]: 117: Hoare triple {35513#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,824 INFO L290 TraceCheckUtils]: 118: Hoare triple {35513#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,824 INFO L290 TraceCheckUtils]: 119: Hoare triple {35513#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,824 INFO L290 TraceCheckUtils]: 120: Hoare triple {35513#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,824 INFO L290 TraceCheckUtils]: 121: Hoare triple {35513#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,824 INFO L290 TraceCheckUtils]: 122: Hoare triple {35513#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,824 INFO L290 TraceCheckUtils]: 123: Hoare triple {35513#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,824 INFO L290 TraceCheckUtils]: 124: Hoare triple {35513#false} assume !(1 == ~T10_E~0); {35513#false} is VALID [2022-02-21 04:24:32,825 INFO L290 TraceCheckUtils]: 125: Hoare triple {35513#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,825 INFO L290 TraceCheckUtils]: 126: Hoare triple {35513#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,825 INFO L290 TraceCheckUtils]: 127: Hoare triple {35513#false} assume 1 == ~E_1~0;~E_1~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,825 INFO L290 TraceCheckUtils]: 128: Hoare triple {35513#false} assume 1 == ~E_2~0;~E_2~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,825 INFO L290 TraceCheckUtils]: 129: Hoare triple {35513#false} assume 1 == ~E_3~0;~E_3~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,825 INFO L290 TraceCheckUtils]: 130: Hoare triple {35513#false} assume 1 == ~E_4~0;~E_4~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,825 INFO L290 TraceCheckUtils]: 131: Hoare triple {35513#false} assume 1 == ~E_5~0;~E_5~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,825 INFO L290 TraceCheckUtils]: 132: Hoare triple {35513#false} assume !(1 == ~E_6~0); {35513#false} is VALID [2022-02-21 04:24:32,826 INFO L290 TraceCheckUtils]: 133: Hoare triple {35513#false} assume 1 == ~E_7~0;~E_7~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,826 INFO L290 TraceCheckUtils]: 134: Hoare triple {35513#false} assume 1 == ~E_8~0;~E_8~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,826 INFO L290 TraceCheckUtils]: 135: Hoare triple {35513#false} assume 1 == ~E_9~0;~E_9~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,826 INFO L290 TraceCheckUtils]: 136: Hoare triple {35513#false} assume 1 == ~E_10~0;~E_10~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,826 INFO L290 TraceCheckUtils]: 137: Hoare triple {35513#false} assume 1 == ~E_11~0;~E_11~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,826 INFO L290 TraceCheckUtils]: 138: Hoare triple {35513#false} assume 1 == ~E_12~0;~E_12~0 := 2; {35513#false} is VALID [2022-02-21 04:24:32,826 INFO L290 TraceCheckUtils]: 139: Hoare triple {35513#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {35513#false} is VALID [2022-02-21 04:24:32,826 INFO L290 TraceCheckUtils]: 140: Hoare triple {35513#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {35513#false} is VALID [2022-02-21 04:24:32,827 INFO L290 TraceCheckUtils]: 141: Hoare triple {35513#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {35513#false} is VALID [2022-02-21 04:24:32,827 INFO L290 TraceCheckUtils]: 142: Hoare triple {35513#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {35513#false} is VALID [2022-02-21 04:24:32,827 INFO L290 TraceCheckUtils]: 143: Hoare triple {35513#false} assume !(0 == start_simulation_~tmp~3#1); {35513#false} is VALID [2022-02-21 04:24:32,827 INFO L290 TraceCheckUtils]: 144: Hoare triple {35513#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {35513#false} is VALID [2022-02-21 04:24:32,827 INFO L290 TraceCheckUtils]: 145: Hoare triple {35513#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {35513#false} is VALID [2022-02-21 04:24:32,827 INFO L290 TraceCheckUtils]: 146: Hoare triple {35513#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {35513#false} is VALID [2022-02-21 04:24:32,827 INFO L290 TraceCheckUtils]: 147: Hoare triple {35513#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {35513#false} is VALID [2022-02-21 04:24:32,827 INFO L290 TraceCheckUtils]: 148: Hoare triple {35513#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {35513#false} is VALID [2022-02-21 04:24:32,827 INFO L290 TraceCheckUtils]: 149: Hoare triple {35513#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {35513#false} is VALID [2022-02-21 04:24:32,828 INFO L290 TraceCheckUtils]: 150: Hoare triple {35513#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {35513#false} is VALID [2022-02-21 04:24:32,828 INFO L290 TraceCheckUtils]: 151: Hoare triple {35513#false} assume !(0 != start_simulation_~tmp___0~1#1); {35513#false} is VALID [2022-02-21 04:24:32,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:32,828 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:32,829 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1283517099] [2022-02-21 04:24:32,829 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1283517099] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:32,829 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:32,829 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:32,829 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [843254757] [2022-02-21 04:24:32,829 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:32,830 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:32,830 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:32,830 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:32,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:32,831 INFO L87 Difference]: Start difference. First operand 1688 states and 2500 transitions. cyclomatic complexity: 813 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:34,060 INFO L93 Difference]: Finished difference Result 1688 states and 2499 transitions. [2022-02-21 04:24:34,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:34,060 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,182 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:34,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2499 transitions. [2022-02-21 04:24:34,282 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:34,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2499 transitions. [2022-02-21 04:24:34,369 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:34,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:34,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2499 transitions. [2022-02-21 04:24:34,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:34,371 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2022-02-21 04:24:34,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2499 transitions. [2022-02-21 04:24:34,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:34,394 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:34,396 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2499 transitions. Second operand has 1688 states, 1688 states have (on average 1.4804502369668247) internal successors, (2499), 1687 states have internal predecessors, (2499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,398 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2499 transitions. Second operand has 1688 states, 1688 states have (on average 1.4804502369668247) internal successors, (2499), 1687 states have internal predecessors, (2499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,399 INFO L87 Difference]: Start difference. First operand 1688 states and 2499 transitions. Second operand has 1688 states, 1688 states have (on average 1.4804502369668247) internal successors, (2499), 1687 states have internal predecessors, (2499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:34,486 INFO L93 Difference]: Finished difference Result 1688 states and 2499 transitions. [2022-02-21 04:24:34,486 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2499 transitions. [2022-02-21 04:24:34,487 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:34,488 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:34,491 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.4804502369668247) internal successors, (2499), 1687 states have internal predecessors, (2499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2499 transitions. [2022-02-21 04:24:34,492 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.4804502369668247) internal successors, (2499), 1687 states have internal predecessors, (2499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2499 transitions. [2022-02-21 04:24:34,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:34,579 INFO L93 Difference]: Finished difference Result 1688 states and 2499 transitions. [2022-02-21 04:24:34,579 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2499 transitions. [2022-02-21 04:24:34,581 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:34,581 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:34,581 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:34,581 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:34,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4804502369668247) internal successors, (2499), 1687 states have internal predecessors, (2499), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2499 transitions. [2022-02-21 04:24:34,655 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2022-02-21 04:24:34,655 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2499 transitions. [2022-02-21 04:24:34,655 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:34,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2499 transitions. [2022-02-21 04:24:34,659 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:34,659 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:34,659 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:34,661 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:34,661 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:34,661 INFO L791 eck$LassoCheckResult]: Stem: 38006#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 38007#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 38860#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38354#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38159#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 38160#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38245#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38546#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38668#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38669#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37457#L846-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 37458#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 38606#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 38052#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38053#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37959#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37960#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 38349#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37701#L1174 assume !(0 == ~M_E~0); 37702#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37553#L1179-1 assume !(0 == ~T2_E~0); 37455#L1184-1 assume !(0 == ~T3_E~0); 37456#L1189-1 assume !(0 == ~T4_E~0); 37494#L1194-1 assume !(0 == ~T5_E~0); 37594#L1199-1 assume !(0 == ~T6_E~0); 38489#L1204-1 assume !(0 == ~T7_E~0); 38408#L1209-1 assume !(0 == ~T8_E~0); 38409#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38797#L1219-1 assume !(0 == ~T10_E~0); 38882#L1224-1 assume !(0 == ~T11_E~0); 37819#L1229-1 assume !(0 == ~T12_E~0); 37380#L1234-1 assume !(0 == ~E_1~0); 37381#L1239-1 assume !(0 == ~E_2~0); 37416#L1244-1 assume !(0 == ~E_3~0); 37417#L1249-1 assume !(0 == ~E_4~0); 38076#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 37310#L1259-1 assume !(0 == ~E_6~0); 37265#L1264-1 assume !(0 == ~E_7~0); 37266#L1269-1 assume !(0 == ~E_8~0); 38887#L1274-1 assume !(0 == ~E_9~0); 38822#L1279-1 assume !(0 == ~E_10~0); 37498#L1284-1 assume !(0 == ~E_11~0); 37499#L1289-1 assume !(0 == ~E_12~0); 38128#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38129#L566 assume 1 == ~m_pc~0; 37282#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37283#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38437#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38438#L1455 assume !(0 != activate_threads_~tmp~1#1); 37728#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37729#L585 assume 1 == ~t1_pc~0; 37377#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37378#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38378#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38379#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 38847#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38845#L604 assume !(1 == ~t2_pc~0); 38457#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38458#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37991#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37992#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38629#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38630#L623 assume 1 == ~t3_pc~0; 37906#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37246#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38056#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38057#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 38664#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37279#L642 assume !(1 == ~t4_pc~0); 37280#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 37745#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37746#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37351#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 37352#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38469#L661 assume 1 == ~t5_pc~0; 37516#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37517#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37478#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37479#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 38500#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38501#L680 assume !(1 == ~t6_pc~0); 37939#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 37940#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38201#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38202#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 38730#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38843#L699 assume 1 == ~t7_pc~0; 38329#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38330#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37506#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37507#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 38231#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38130#L718 assume !(1 == ~t8_pc~0); 38131#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 37492#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37493#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37534#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 37535#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37668#L737 assume 1 == ~t9_pc~0; 38533#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37803#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38404#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38405#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 37977#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37978#L756 assume 1 == ~t10_pc~0; 38557#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38223#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37209#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37210#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 37785#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37786#L775 assume !(1 == ~t11_pc~0); 38040#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 38041#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37662#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37426#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37427#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37613#L794 assume 1 == ~t12_pc~0; 37454#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37431#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38624#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37579#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 37580#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38059#L1307 assume !(1 == ~M_E~0); 38060#L1307-2 assume !(1 == ~T1_E~0); 38171#L1312-1 assume !(1 == ~T2_E~0); 38090#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38091#L1322-1 assume !(1 == ~T4_E~0); 37794#L1327-1 assume !(1 == ~T5_E~0); 37795#L1332-1 assume !(1 == ~T6_E~0); 38333#L1337-1 assume !(1 == ~T7_E~0); 38295#L1342-1 assume !(1 == ~T8_E~0); 38296#L1347-1 assume !(1 == ~T9_E~0); 38693#L1352-1 assume !(1 == ~T10_E~0); 38566#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37957#L1362-1 assume !(1 == ~T12_E~0); 37958#L1367-1 assume !(1 == ~E_1~0); 37595#L1372-1 assume !(1 == ~E_2~0); 37596#L1377-1 assume !(1 == ~E_3~0); 37889#L1382-1 assume !(1 == ~E_4~0); 37890#L1387-1 assume !(1 == ~E_5~0); 38459#L1392-1 assume !(1 == ~E_6~0); 37909#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 37910#L1402-1 assume !(1 == ~E_8~0); 37606#L1407-1 assume !(1 == ~E_9~0); 37607#L1412-1 assume !(1 == ~E_10~0); 38622#L1417-1 assume !(1 == ~E_11~0); 38623#L1422-1 assume !(1 == ~E_12~0); 38841#L1427-1 assume { :end_inline_reset_delta_events } true; 37410#L1768-2 [2022-02-21 04:24:34,662 INFO L793 eck$LassoCheckResult]: Loop: 37410#L1768-2 assume !false; 37411#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38149#L1149 assume !false; 38521#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38674#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37800#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37706#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 37707#L976 assume !(0 != eval_~tmp~0#1); 38840#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38850#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38641#L1174-3 assume !(0 == ~M_E~0); 38634#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38383#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38384#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38568#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38218#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37568#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37569#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37810#L1209-3 assume !(0 == ~T8_E~0); 37230#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37231#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37989#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37990#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38008#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37418#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37419#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37862#L1249-3 assume !(0 == ~E_4~0); 38321#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38793#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38435#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37424#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37425#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38820#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37987#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 37988#L1289-3 assume !(0 == ~E_12~0); 37976#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37652#L566-39 assume 1 == ~m_pc~0; 37653#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 38255#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37967#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 37968#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38510#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38511#L585-39 assume !(1 == ~t1_pc~0); 37660#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 37661#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37736#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37737#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38543#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38236#L604-39 assume 1 == ~t2_pc~0; 38237#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37868#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37869#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38288#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38289#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37851#L623-39 assume 1 == ~t3_pc~0; 37249#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37251#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38527#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37703#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37704#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38475#L642-39 assume 1 == ~t4_pc~0; 38048#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38049#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37575#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37576#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38673#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37626#L661-39 assume !(1 == ~t5_pc~0); 37255#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 37256#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38616#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38617#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38530#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38531#L680-39 assume 1 == ~t6_pc~0; 37319#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37320#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38460#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37783#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37784#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38798#L699-39 assume 1 == ~t7_pc~0; 38220#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37942#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37943#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38626#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38747#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38745#L718-39 assume 1 == ~t8_pc~0; 38135#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38136#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38067#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38068#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 38369#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38338#L737-39 assume 1 == ~t9_pc~0; 37764#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37765#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38054#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38821#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38722#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38665#L756-39 assume 1 == ~t10_pc~0; 38666#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38144#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37891#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37892#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38024#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37362#L775-39 assume 1 == ~t11_pc~0; 37363#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38017#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38018#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38880#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38428#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38075#L794-39 assume !(1 == ~t12_pc~0); 37760#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 37761#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38581#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38482#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37306#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37307#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38774#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38775#L1312-3 assume !(1 == ~T2_E~0); 38886#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38498#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38499#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37443#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37414#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37415#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38163#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38286#L1352-3 assume !(1 == ~T10_E~0); 38287#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38727#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38879#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38870#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37240#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37241#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37875#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37876#L1392-3 assume !(1 == ~E_6~0); 38591#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38837#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38254#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37530#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37531#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38177#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38178#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37540#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37541#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38407#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 38258#L1787 assume !(0 == start_simulation_~tmp~3#1); 38259#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38783#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37511#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38306#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 38307#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37858#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37859#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 37860#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 37410#L1768-2 [2022-02-21 04:24:34,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:34,662 INFO L85 PathProgramCache]: Analyzing trace with hash 313083407, now seen corresponding path program 1 times [2022-02-21 04:24:34,662 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:34,663 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922196277] [2022-02-21 04:24:34,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:34,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:34,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:34,700 INFO L290 TraceCheckUtils]: 0: Hoare triple {42270#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {42270#true} is VALID [2022-02-21 04:24:34,700 INFO L290 TraceCheckUtils]: 1: Hoare triple {42270#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {42272#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:34,700 INFO L290 TraceCheckUtils]: 2: Hoare triple {42272#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {42272#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:34,701 INFO L290 TraceCheckUtils]: 3: Hoare triple {42272#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {42272#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:34,701 INFO L290 TraceCheckUtils]: 4: Hoare triple {42272#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {42272#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:34,701 INFO L290 TraceCheckUtils]: 5: Hoare triple {42272#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {42272#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:34,702 INFO L290 TraceCheckUtils]: 6: Hoare triple {42272#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {42272#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:34,702 INFO L290 TraceCheckUtils]: 7: Hoare triple {42272#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {42272#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:34,702 INFO L290 TraceCheckUtils]: 8: Hoare triple {42272#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {42272#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:34,703 INFO L290 TraceCheckUtils]: 9: Hoare triple {42272#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {42272#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:34,703 INFO L290 TraceCheckUtils]: 10: Hoare triple {42272#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {42271#false} is VALID [2022-02-21 04:24:34,703 INFO L290 TraceCheckUtils]: 11: Hoare triple {42271#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {42271#false} is VALID [2022-02-21 04:24:34,703 INFO L290 TraceCheckUtils]: 12: Hoare triple {42271#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {42271#false} is VALID [2022-02-21 04:24:34,703 INFO L290 TraceCheckUtils]: 13: Hoare triple {42271#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {42271#false} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 14: Hoare triple {42271#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {42271#false} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 15: Hoare triple {42271#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {42271#false} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 16: Hoare triple {42271#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {42271#false} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 17: Hoare triple {42271#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {42271#false} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 18: Hoare triple {42271#false} assume !(0 == ~M_E~0); {42271#false} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 19: Hoare triple {42271#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {42271#false} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 20: Hoare triple {42271#false} assume !(0 == ~T2_E~0); {42271#false} is VALID [2022-02-21 04:24:34,704 INFO L290 TraceCheckUtils]: 21: Hoare triple {42271#false} assume !(0 == ~T3_E~0); {42271#false} is VALID [2022-02-21 04:24:34,705 INFO L290 TraceCheckUtils]: 22: Hoare triple {42271#false} assume !(0 == ~T4_E~0); {42271#false} is VALID [2022-02-21 04:24:34,705 INFO L290 TraceCheckUtils]: 23: Hoare triple {42271#false} assume !(0 == ~T5_E~0); {42271#false} is VALID [2022-02-21 04:24:34,705 INFO L290 TraceCheckUtils]: 24: Hoare triple {42271#false} assume !(0 == ~T6_E~0); {42271#false} is VALID [2022-02-21 04:24:34,705 INFO L290 TraceCheckUtils]: 25: Hoare triple {42271#false} assume !(0 == ~T7_E~0); {42271#false} is VALID [2022-02-21 04:24:34,705 INFO L290 TraceCheckUtils]: 26: Hoare triple {42271#false} assume !(0 == ~T8_E~0); {42271#false} is VALID [2022-02-21 04:24:34,705 INFO L290 TraceCheckUtils]: 27: Hoare triple {42271#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {42271#false} is VALID [2022-02-21 04:24:34,705 INFO L290 TraceCheckUtils]: 28: Hoare triple {42271#false} assume !(0 == ~T10_E~0); {42271#false} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 29: Hoare triple {42271#false} assume !(0 == ~T11_E~0); {42271#false} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 30: Hoare triple {42271#false} assume !(0 == ~T12_E~0); {42271#false} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 31: Hoare triple {42271#false} assume !(0 == ~E_1~0); {42271#false} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 32: Hoare triple {42271#false} assume !(0 == ~E_2~0); {42271#false} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 33: Hoare triple {42271#false} assume !(0 == ~E_3~0); {42271#false} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 34: Hoare triple {42271#false} assume !(0 == ~E_4~0); {42271#false} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 35: Hoare triple {42271#false} assume 0 == ~E_5~0;~E_5~0 := 1; {42271#false} is VALID [2022-02-21 04:24:34,706 INFO L290 TraceCheckUtils]: 36: Hoare triple {42271#false} assume !(0 == ~E_6~0); {42271#false} is VALID [2022-02-21 04:24:34,707 INFO L290 TraceCheckUtils]: 37: Hoare triple {42271#false} assume !(0 == ~E_7~0); {42271#false} is VALID [2022-02-21 04:24:34,707 INFO L290 TraceCheckUtils]: 38: Hoare triple {42271#false} assume !(0 == ~E_8~0); {42271#false} is VALID [2022-02-21 04:24:34,707 INFO L290 TraceCheckUtils]: 39: Hoare triple {42271#false} assume !(0 == ~E_9~0); {42271#false} is VALID [2022-02-21 04:24:34,707 INFO L290 TraceCheckUtils]: 40: Hoare triple {42271#false} assume !(0 == ~E_10~0); {42271#false} is VALID [2022-02-21 04:24:34,707 INFO L290 TraceCheckUtils]: 41: Hoare triple {42271#false} assume !(0 == ~E_11~0); {42271#false} is VALID [2022-02-21 04:24:34,707 INFO L290 TraceCheckUtils]: 42: Hoare triple {42271#false} assume !(0 == ~E_12~0); {42271#false} is VALID [2022-02-21 04:24:34,707 INFO L290 TraceCheckUtils]: 43: Hoare triple {42271#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {42271#false} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 44: Hoare triple {42271#false} assume 1 == ~m_pc~0; {42271#false} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 45: Hoare triple {42271#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {42271#false} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 46: Hoare triple {42271#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {42271#false} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 47: Hoare triple {42271#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {42271#false} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 48: Hoare triple {42271#false} assume !(0 != activate_threads_~tmp~1#1); {42271#false} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 49: Hoare triple {42271#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {42271#false} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 50: Hoare triple {42271#false} assume 1 == ~t1_pc~0; {42271#false} is VALID [2022-02-21 04:24:34,708 INFO L290 TraceCheckUtils]: 51: Hoare triple {42271#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {42271#false} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 52: Hoare triple {42271#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {42271#false} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 53: Hoare triple {42271#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {42271#false} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 54: Hoare triple {42271#false} assume !(0 != activate_threads_~tmp___0~0#1); {42271#false} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 55: Hoare triple {42271#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {42271#false} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 56: Hoare triple {42271#false} assume !(1 == ~t2_pc~0); {42271#false} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 57: Hoare triple {42271#false} is_transmit2_triggered_~__retres1~2#1 := 0; {42271#false} is VALID [2022-02-21 04:24:34,709 INFO L290 TraceCheckUtils]: 58: Hoare triple {42271#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {42271#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 59: Hoare triple {42271#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {42271#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 60: Hoare triple {42271#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {42271#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 61: Hoare triple {42271#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {42271#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 62: Hoare triple {42271#false} assume 1 == ~t3_pc~0; {42271#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 63: Hoare triple {42271#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {42271#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 64: Hoare triple {42271#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {42271#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 65: Hoare triple {42271#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {42271#false} is VALID [2022-02-21 04:24:34,710 INFO L290 TraceCheckUtils]: 66: Hoare triple {42271#false} assume !(0 != activate_threads_~tmp___2~0#1); {42271#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 67: Hoare triple {42271#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {42271#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 68: Hoare triple {42271#false} assume !(1 == ~t4_pc~0); {42271#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 69: Hoare triple {42271#false} is_transmit4_triggered_~__retres1~4#1 := 0; {42271#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 70: Hoare triple {42271#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {42271#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 71: Hoare triple {42271#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {42271#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 72: Hoare triple {42271#false} assume !(0 != activate_threads_~tmp___3~0#1); {42271#false} is VALID [2022-02-21 04:24:34,711 INFO L290 TraceCheckUtils]: 73: Hoare triple {42271#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {42271#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 74: Hoare triple {42271#false} assume 1 == ~t5_pc~0; {42271#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 75: Hoare triple {42271#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {42271#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 76: Hoare triple {42271#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {42271#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 77: Hoare triple {42271#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {42271#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 78: Hoare triple {42271#false} assume !(0 != activate_threads_~tmp___4~0#1); {42271#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 79: Hoare triple {42271#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {42271#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 80: Hoare triple {42271#false} assume !(1 == ~t6_pc~0); {42271#false} is VALID [2022-02-21 04:24:34,712 INFO L290 TraceCheckUtils]: 81: Hoare triple {42271#false} is_transmit6_triggered_~__retres1~6#1 := 0; {42271#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 82: Hoare triple {42271#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {42271#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 83: Hoare triple {42271#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {42271#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 84: Hoare triple {42271#false} assume !(0 != activate_threads_~tmp___5~0#1); {42271#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 85: Hoare triple {42271#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {42271#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 86: Hoare triple {42271#false} assume 1 == ~t7_pc~0; {42271#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 87: Hoare triple {42271#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {42271#false} is VALID [2022-02-21 04:24:34,713 INFO L290 TraceCheckUtils]: 88: Hoare triple {42271#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {42271#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 89: Hoare triple {42271#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {42271#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 90: Hoare triple {42271#false} assume !(0 != activate_threads_~tmp___6~0#1); {42271#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 91: Hoare triple {42271#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {42271#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 92: Hoare triple {42271#false} assume !(1 == ~t8_pc~0); {42271#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 93: Hoare triple {42271#false} is_transmit8_triggered_~__retres1~8#1 := 0; {42271#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 94: Hoare triple {42271#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {42271#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 95: Hoare triple {42271#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {42271#false} is VALID [2022-02-21 04:24:34,714 INFO L290 TraceCheckUtils]: 96: Hoare triple {42271#false} assume !(0 != activate_threads_~tmp___7~0#1); {42271#false} is VALID [2022-02-21 04:24:34,715 INFO L290 TraceCheckUtils]: 97: Hoare triple {42271#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {42271#false} is VALID [2022-02-21 04:24:34,715 INFO L290 TraceCheckUtils]: 98: Hoare triple {42271#false} assume 1 == ~t9_pc~0; {42271#false} is VALID [2022-02-21 04:24:34,715 INFO L290 TraceCheckUtils]: 99: Hoare triple {42271#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {42271#false} is VALID [2022-02-21 04:24:34,715 INFO L290 TraceCheckUtils]: 100: Hoare triple {42271#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {42271#false} is VALID [2022-02-21 04:24:34,715 INFO L290 TraceCheckUtils]: 101: Hoare triple {42271#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {42271#false} is VALID [2022-02-21 04:24:34,715 INFO L290 TraceCheckUtils]: 102: Hoare triple {42271#false} assume !(0 != activate_threads_~tmp___8~0#1); {42271#false} is VALID [2022-02-21 04:24:34,715 INFO L290 TraceCheckUtils]: 103: Hoare triple {42271#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {42271#false} is VALID [2022-02-21 04:24:34,716 INFO L290 TraceCheckUtils]: 104: Hoare triple {42271#false} assume 1 == ~t10_pc~0; {42271#false} is VALID [2022-02-21 04:24:34,716 INFO L290 TraceCheckUtils]: 105: Hoare triple {42271#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {42271#false} is VALID [2022-02-21 04:24:34,716 INFO L290 TraceCheckUtils]: 106: Hoare triple {42271#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {42271#false} is VALID [2022-02-21 04:24:34,716 INFO L290 TraceCheckUtils]: 107: Hoare triple {42271#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {42271#false} is VALID [2022-02-21 04:24:34,716 INFO L290 TraceCheckUtils]: 108: Hoare triple {42271#false} assume !(0 != activate_threads_~tmp___9~0#1); {42271#false} is VALID [2022-02-21 04:24:34,716 INFO L290 TraceCheckUtils]: 109: Hoare triple {42271#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {42271#false} is VALID [2022-02-21 04:24:34,716 INFO L290 TraceCheckUtils]: 110: Hoare triple {42271#false} assume !(1 == ~t11_pc~0); {42271#false} is VALID [2022-02-21 04:24:34,716 INFO L290 TraceCheckUtils]: 111: Hoare triple {42271#false} is_transmit11_triggered_~__retres1~11#1 := 0; {42271#false} is VALID [2022-02-21 04:24:34,717 INFO L290 TraceCheckUtils]: 112: Hoare triple {42271#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {42271#false} is VALID [2022-02-21 04:24:34,717 INFO L290 TraceCheckUtils]: 113: Hoare triple {42271#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {42271#false} is VALID [2022-02-21 04:24:34,717 INFO L290 TraceCheckUtils]: 114: Hoare triple {42271#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {42271#false} is VALID [2022-02-21 04:24:34,717 INFO L290 TraceCheckUtils]: 115: Hoare triple {42271#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {42271#false} is VALID [2022-02-21 04:24:34,717 INFO L290 TraceCheckUtils]: 116: Hoare triple {42271#false} assume 1 == ~t12_pc~0; {42271#false} is VALID [2022-02-21 04:24:34,717 INFO L290 TraceCheckUtils]: 117: Hoare triple {42271#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {42271#false} is VALID [2022-02-21 04:24:34,717 INFO L290 TraceCheckUtils]: 118: Hoare triple {42271#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {42271#false} is VALID [2022-02-21 04:24:34,717 INFO L290 TraceCheckUtils]: 119: Hoare triple {42271#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {42271#false} is VALID [2022-02-21 04:24:34,718 INFO L290 TraceCheckUtils]: 120: Hoare triple {42271#false} assume !(0 != activate_threads_~tmp___11~0#1); {42271#false} is VALID [2022-02-21 04:24:34,718 INFO L290 TraceCheckUtils]: 121: Hoare triple {42271#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {42271#false} is VALID [2022-02-21 04:24:34,718 INFO L290 TraceCheckUtils]: 122: Hoare triple {42271#false} assume !(1 == ~M_E~0); {42271#false} is VALID [2022-02-21 04:24:34,718 INFO L290 TraceCheckUtils]: 123: Hoare triple {42271#false} assume !(1 == ~T1_E~0); {42271#false} is VALID [2022-02-21 04:24:34,718 INFO L290 TraceCheckUtils]: 124: Hoare triple {42271#false} assume !(1 == ~T2_E~0); {42271#false} is VALID [2022-02-21 04:24:34,718 INFO L290 TraceCheckUtils]: 125: Hoare triple {42271#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {42271#false} is VALID [2022-02-21 04:24:34,718 INFO L290 TraceCheckUtils]: 126: Hoare triple {42271#false} assume !(1 == ~T4_E~0); {42271#false} is VALID [2022-02-21 04:24:34,719 INFO L290 TraceCheckUtils]: 127: Hoare triple {42271#false} assume !(1 == ~T5_E~0); {42271#false} is VALID [2022-02-21 04:24:34,719 INFO L290 TraceCheckUtils]: 128: Hoare triple {42271#false} assume !(1 == ~T6_E~0); {42271#false} is VALID [2022-02-21 04:24:34,719 INFO L290 TraceCheckUtils]: 129: Hoare triple {42271#false} assume !(1 == ~T7_E~0); {42271#false} is VALID [2022-02-21 04:24:34,719 INFO L290 TraceCheckUtils]: 130: Hoare triple {42271#false} assume !(1 == ~T8_E~0); {42271#false} is VALID [2022-02-21 04:24:34,719 INFO L290 TraceCheckUtils]: 131: Hoare triple {42271#false} assume !(1 == ~T9_E~0); {42271#false} is VALID [2022-02-21 04:24:34,719 INFO L290 TraceCheckUtils]: 132: Hoare triple {42271#false} assume !(1 == ~T10_E~0); {42271#false} is VALID [2022-02-21 04:24:34,719 INFO L290 TraceCheckUtils]: 133: Hoare triple {42271#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {42271#false} is VALID [2022-02-21 04:24:34,719 INFO L290 TraceCheckUtils]: 134: Hoare triple {42271#false} assume !(1 == ~T12_E~0); {42271#false} is VALID [2022-02-21 04:24:34,720 INFO L290 TraceCheckUtils]: 135: Hoare triple {42271#false} assume !(1 == ~E_1~0); {42271#false} is VALID [2022-02-21 04:24:34,720 INFO L290 TraceCheckUtils]: 136: Hoare triple {42271#false} assume !(1 == ~E_2~0); {42271#false} is VALID [2022-02-21 04:24:34,720 INFO L290 TraceCheckUtils]: 137: Hoare triple {42271#false} assume !(1 == ~E_3~0); {42271#false} is VALID [2022-02-21 04:24:34,720 INFO L290 TraceCheckUtils]: 138: Hoare triple {42271#false} assume !(1 == ~E_4~0); {42271#false} is VALID [2022-02-21 04:24:34,720 INFO L290 TraceCheckUtils]: 139: Hoare triple {42271#false} assume !(1 == ~E_5~0); {42271#false} is VALID [2022-02-21 04:24:34,720 INFO L290 TraceCheckUtils]: 140: Hoare triple {42271#false} assume !(1 == ~E_6~0); {42271#false} is VALID [2022-02-21 04:24:34,720 INFO L290 TraceCheckUtils]: 141: Hoare triple {42271#false} assume 1 == ~E_7~0;~E_7~0 := 2; {42271#false} is VALID [2022-02-21 04:24:34,721 INFO L290 TraceCheckUtils]: 142: Hoare triple {42271#false} assume !(1 == ~E_8~0); {42271#false} is VALID [2022-02-21 04:24:34,721 INFO L290 TraceCheckUtils]: 143: Hoare triple {42271#false} assume !(1 == ~E_9~0); {42271#false} is VALID [2022-02-21 04:24:34,721 INFO L290 TraceCheckUtils]: 144: Hoare triple {42271#false} assume !(1 == ~E_10~0); {42271#false} is VALID [2022-02-21 04:24:34,721 INFO L290 TraceCheckUtils]: 145: Hoare triple {42271#false} assume !(1 == ~E_11~0); {42271#false} is VALID [2022-02-21 04:24:34,721 INFO L290 TraceCheckUtils]: 146: Hoare triple {42271#false} assume !(1 == ~E_12~0); {42271#false} is VALID [2022-02-21 04:24:34,721 INFO L290 TraceCheckUtils]: 147: Hoare triple {42271#false} assume { :end_inline_reset_delta_events } true; {42271#false} is VALID [2022-02-21 04:24:34,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:34,722 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:34,722 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922196277] [2022-02-21 04:24:34,722 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1922196277] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:34,722 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:34,722 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:34,723 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1743300146] [2022-02-21 04:24:34,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:34,723 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:34,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:34,724 INFO L85 PathProgramCache]: Analyzing trace with hash 1017478530, now seen corresponding path program 1 times [2022-02-21 04:24:34,724 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:34,724 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159888559] [2022-02-21 04:24:34,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:34,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:34,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:34,774 INFO L290 TraceCheckUtils]: 0: Hoare triple {42273#true} assume !false; {42273#true} is VALID [2022-02-21 04:24:34,774 INFO L290 TraceCheckUtils]: 1: Hoare triple {42273#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {42273#true} is VALID [2022-02-21 04:24:34,774 INFO L290 TraceCheckUtils]: 2: Hoare triple {42273#true} assume !false; {42273#true} is VALID [2022-02-21 04:24:34,774 INFO L290 TraceCheckUtils]: 3: Hoare triple {42273#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {42273#true} is VALID [2022-02-21 04:24:34,774 INFO L290 TraceCheckUtils]: 4: Hoare triple {42273#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {42273#true} is VALID [2022-02-21 04:24:34,775 INFO L290 TraceCheckUtils]: 5: Hoare triple {42273#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {42273#true} is VALID [2022-02-21 04:24:34,775 INFO L290 TraceCheckUtils]: 6: Hoare triple {42273#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {42273#true} is VALID [2022-02-21 04:24:34,775 INFO L290 TraceCheckUtils]: 7: Hoare triple {42273#true} assume !(0 != eval_~tmp~0#1); {42273#true} is VALID [2022-02-21 04:24:34,775 INFO L290 TraceCheckUtils]: 8: Hoare triple {42273#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {42273#true} is VALID [2022-02-21 04:24:34,775 INFO L290 TraceCheckUtils]: 9: Hoare triple {42273#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {42273#true} is VALID [2022-02-21 04:24:34,775 INFO L290 TraceCheckUtils]: 10: Hoare triple {42273#true} assume !(0 == ~M_E~0); {42273#true} is VALID [2022-02-21 04:24:34,775 INFO L290 TraceCheckUtils]: 11: Hoare triple {42273#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {42273#true} is VALID [2022-02-21 04:24:34,776 INFO L290 TraceCheckUtils]: 12: Hoare triple {42273#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,776 INFO L290 TraceCheckUtils]: 13: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,776 INFO L290 TraceCheckUtils]: 14: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,777 INFO L290 TraceCheckUtils]: 15: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,777 INFO L290 TraceCheckUtils]: 16: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,777 INFO L290 TraceCheckUtils]: 17: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,778 INFO L290 TraceCheckUtils]: 18: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,778 INFO L290 TraceCheckUtils]: 19: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,778 INFO L290 TraceCheckUtils]: 20: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,779 INFO L290 TraceCheckUtils]: 21: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,779 INFO L290 TraceCheckUtils]: 22: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,779 INFO L290 TraceCheckUtils]: 23: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,780 INFO L290 TraceCheckUtils]: 24: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,780 INFO L290 TraceCheckUtils]: 25: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,780 INFO L290 TraceCheckUtils]: 26: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,781 INFO L290 TraceCheckUtils]: 27: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,781 INFO L290 TraceCheckUtils]: 28: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,783 INFO L290 TraceCheckUtils]: 29: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,784 INFO L290 TraceCheckUtils]: 30: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,784 INFO L290 TraceCheckUtils]: 31: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,785 INFO L290 TraceCheckUtils]: 32: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,785 INFO L290 TraceCheckUtils]: 33: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,785 INFO L290 TraceCheckUtils]: 34: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,786 INFO L290 TraceCheckUtils]: 35: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,786 INFO L290 TraceCheckUtils]: 36: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,786 INFO L290 TraceCheckUtils]: 37: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,787 INFO L290 TraceCheckUtils]: 38: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,787 INFO L290 TraceCheckUtils]: 39: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,787 INFO L290 TraceCheckUtils]: 40: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,788 INFO L290 TraceCheckUtils]: 41: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,788 INFO L290 TraceCheckUtils]: 42: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,788 INFO L290 TraceCheckUtils]: 43: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,789 INFO L290 TraceCheckUtils]: 44: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,789 INFO L290 TraceCheckUtils]: 45: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,789 INFO L290 TraceCheckUtils]: 46: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,790 INFO L290 TraceCheckUtils]: 47: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,790 INFO L290 TraceCheckUtils]: 48: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,790 INFO L290 TraceCheckUtils]: 49: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,791 INFO L290 TraceCheckUtils]: 50: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,791 INFO L290 TraceCheckUtils]: 51: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,791 INFO L290 TraceCheckUtils]: 52: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,792 INFO L290 TraceCheckUtils]: 53: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,792 INFO L290 TraceCheckUtils]: 54: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,792 INFO L290 TraceCheckUtils]: 55: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,793 INFO L290 TraceCheckUtils]: 56: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,793 INFO L290 TraceCheckUtils]: 57: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,793 INFO L290 TraceCheckUtils]: 58: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,794 INFO L290 TraceCheckUtils]: 59: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,794 INFO L290 TraceCheckUtils]: 60: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,794 INFO L290 TraceCheckUtils]: 61: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,795 INFO L290 TraceCheckUtils]: 62: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,795 INFO L290 TraceCheckUtils]: 63: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,796 INFO L290 TraceCheckUtils]: 64: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,796 INFO L290 TraceCheckUtils]: 65: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,796 INFO L290 TraceCheckUtils]: 66: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,797 INFO L290 TraceCheckUtils]: 67: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,797 INFO L290 TraceCheckUtils]: 68: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,797 INFO L290 TraceCheckUtils]: 69: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,798 INFO L290 TraceCheckUtils]: 70: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,798 INFO L290 TraceCheckUtils]: 71: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,798 INFO L290 TraceCheckUtils]: 72: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,799 INFO L290 TraceCheckUtils]: 73: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,799 INFO L290 TraceCheckUtils]: 74: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,799 INFO L290 TraceCheckUtils]: 75: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,800 INFO L290 TraceCheckUtils]: 76: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,800 INFO L290 TraceCheckUtils]: 77: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,800 INFO L290 TraceCheckUtils]: 78: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,801 INFO L290 TraceCheckUtils]: 79: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,801 INFO L290 TraceCheckUtils]: 80: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,801 INFO L290 TraceCheckUtils]: 81: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,802 INFO L290 TraceCheckUtils]: 82: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,802 INFO L290 TraceCheckUtils]: 83: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,802 INFO L290 TraceCheckUtils]: 84: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,803 INFO L290 TraceCheckUtils]: 85: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,803 INFO L290 TraceCheckUtils]: 86: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,803 INFO L290 TraceCheckUtils]: 87: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,804 INFO L290 TraceCheckUtils]: 88: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,804 INFO L290 TraceCheckUtils]: 89: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,804 INFO L290 TraceCheckUtils]: 90: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,805 INFO L290 TraceCheckUtils]: 91: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,805 INFO L290 TraceCheckUtils]: 92: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,805 INFO L290 TraceCheckUtils]: 93: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,806 INFO L290 TraceCheckUtils]: 94: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,806 INFO L290 TraceCheckUtils]: 95: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,806 INFO L290 TraceCheckUtils]: 96: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,807 INFO L290 TraceCheckUtils]: 97: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,807 INFO L290 TraceCheckUtils]: 98: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,807 INFO L290 TraceCheckUtils]: 99: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,808 INFO L290 TraceCheckUtils]: 100: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,808 INFO L290 TraceCheckUtils]: 101: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,808 INFO L290 TraceCheckUtils]: 102: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,809 INFO L290 TraceCheckUtils]: 103: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,809 INFO L290 TraceCheckUtils]: 104: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,809 INFO L290 TraceCheckUtils]: 105: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,810 INFO L290 TraceCheckUtils]: 106: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,810 INFO L290 TraceCheckUtils]: 107: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,810 INFO L290 TraceCheckUtils]: 108: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t12_pc~0); {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,811 INFO L290 TraceCheckUtils]: 109: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,811 INFO L290 TraceCheckUtils]: 110: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,811 INFO L290 TraceCheckUtils]: 111: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,812 INFO L290 TraceCheckUtils]: 112: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,812 INFO L290 TraceCheckUtils]: 113: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,812 INFO L290 TraceCheckUtils]: 114: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,813 INFO L290 TraceCheckUtils]: 115: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {42275#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:34,813 INFO L290 TraceCheckUtils]: 116: Hoare triple {42275#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {42274#false} is VALID [2022-02-21 04:24:34,813 INFO L290 TraceCheckUtils]: 117: Hoare triple {42274#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,813 INFO L290 TraceCheckUtils]: 118: Hoare triple {42274#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,813 INFO L290 TraceCheckUtils]: 119: Hoare triple {42274#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,813 INFO L290 TraceCheckUtils]: 120: Hoare triple {42274#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,814 INFO L290 TraceCheckUtils]: 121: Hoare triple {42274#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,814 INFO L290 TraceCheckUtils]: 122: Hoare triple {42274#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,814 INFO L290 TraceCheckUtils]: 123: Hoare triple {42274#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,814 INFO L290 TraceCheckUtils]: 124: Hoare triple {42274#false} assume !(1 == ~T10_E~0); {42274#false} is VALID [2022-02-21 04:24:34,814 INFO L290 TraceCheckUtils]: 125: Hoare triple {42274#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,814 INFO L290 TraceCheckUtils]: 126: Hoare triple {42274#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,814 INFO L290 TraceCheckUtils]: 127: Hoare triple {42274#false} assume 1 == ~E_1~0;~E_1~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,814 INFO L290 TraceCheckUtils]: 128: Hoare triple {42274#false} assume 1 == ~E_2~0;~E_2~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,815 INFO L290 TraceCheckUtils]: 129: Hoare triple {42274#false} assume 1 == ~E_3~0;~E_3~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,815 INFO L290 TraceCheckUtils]: 130: Hoare triple {42274#false} assume 1 == ~E_4~0;~E_4~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,815 INFO L290 TraceCheckUtils]: 131: Hoare triple {42274#false} assume 1 == ~E_5~0;~E_5~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,815 INFO L290 TraceCheckUtils]: 132: Hoare triple {42274#false} assume !(1 == ~E_6~0); {42274#false} is VALID [2022-02-21 04:24:34,815 INFO L290 TraceCheckUtils]: 133: Hoare triple {42274#false} assume 1 == ~E_7~0;~E_7~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,815 INFO L290 TraceCheckUtils]: 134: Hoare triple {42274#false} assume 1 == ~E_8~0;~E_8~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,815 INFO L290 TraceCheckUtils]: 135: Hoare triple {42274#false} assume 1 == ~E_9~0;~E_9~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,816 INFO L290 TraceCheckUtils]: 136: Hoare triple {42274#false} assume 1 == ~E_10~0;~E_10~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,816 INFO L290 TraceCheckUtils]: 137: Hoare triple {42274#false} assume 1 == ~E_11~0;~E_11~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,816 INFO L290 TraceCheckUtils]: 138: Hoare triple {42274#false} assume 1 == ~E_12~0;~E_12~0 := 2; {42274#false} is VALID [2022-02-21 04:24:34,816 INFO L290 TraceCheckUtils]: 139: Hoare triple {42274#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {42274#false} is VALID [2022-02-21 04:24:34,816 INFO L290 TraceCheckUtils]: 140: Hoare triple {42274#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {42274#false} is VALID [2022-02-21 04:24:34,816 INFO L290 TraceCheckUtils]: 141: Hoare triple {42274#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {42274#false} is VALID [2022-02-21 04:24:34,816 INFO L290 TraceCheckUtils]: 142: Hoare triple {42274#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {42274#false} is VALID [2022-02-21 04:24:34,817 INFO L290 TraceCheckUtils]: 143: Hoare triple {42274#false} assume !(0 == start_simulation_~tmp~3#1); {42274#false} is VALID [2022-02-21 04:24:34,817 INFO L290 TraceCheckUtils]: 144: Hoare triple {42274#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {42274#false} is VALID [2022-02-21 04:24:34,817 INFO L290 TraceCheckUtils]: 145: Hoare triple {42274#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {42274#false} is VALID [2022-02-21 04:24:34,817 INFO L290 TraceCheckUtils]: 146: Hoare triple {42274#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {42274#false} is VALID [2022-02-21 04:24:34,817 INFO L290 TraceCheckUtils]: 147: Hoare triple {42274#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {42274#false} is VALID [2022-02-21 04:24:34,817 INFO L290 TraceCheckUtils]: 148: Hoare triple {42274#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {42274#false} is VALID [2022-02-21 04:24:34,817 INFO L290 TraceCheckUtils]: 149: Hoare triple {42274#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {42274#false} is VALID [2022-02-21 04:24:34,817 INFO L290 TraceCheckUtils]: 150: Hoare triple {42274#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {42274#false} is VALID [2022-02-21 04:24:34,818 INFO L290 TraceCheckUtils]: 151: Hoare triple {42274#false} assume !(0 != start_simulation_~tmp___0~1#1); {42274#false} is VALID [2022-02-21 04:24:34,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:34,818 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:34,819 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1159888559] [2022-02-21 04:24:34,819 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1159888559] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:34,819 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:34,819 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:34,819 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1868031617] [2022-02-21 04:24:34,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:34,820 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:34,820 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:34,820 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:34,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:34,821 INFO L87 Difference]: Start difference. First operand 1688 states and 2499 transitions. cyclomatic complexity: 812 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:36,044 INFO L93 Difference]: Finished difference Result 1688 states and 2498 transitions. [2022-02-21 04:24:36,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:36,045 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,143 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:36,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2498 transitions. [2022-02-21 04:24:36,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:36,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2498 transitions. [2022-02-21 04:24:36,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:36,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:36,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2498 transitions. [2022-02-21 04:24:36,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:36,282 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2022-02-21 04:24:36,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2498 transitions. [2022-02-21 04:24:36,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:36,301 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:36,303 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2498 transitions. Second operand has 1688 states, 1688 states have (on average 1.4798578199052133) internal successors, (2498), 1687 states have internal predecessors, (2498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,304 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2498 transitions. Second operand has 1688 states, 1688 states have (on average 1.4798578199052133) internal successors, (2498), 1687 states have internal predecessors, (2498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,305 INFO L87 Difference]: Start difference. First operand 1688 states and 2498 transitions. Second operand has 1688 states, 1688 states have (on average 1.4798578199052133) internal successors, (2498), 1687 states have internal predecessors, (2498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:36,381 INFO L93 Difference]: Finished difference Result 1688 states and 2498 transitions. [2022-02-21 04:24:36,381 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2498 transitions. [2022-02-21 04:24:36,383 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:36,383 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:36,385 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.4798578199052133) internal successors, (2498), 1687 states have internal predecessors, (2498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2498 transitions. [2022-02-21 04:24:36,387 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.4798578199052133) internal successors, (2498), 1687 states have internal predecessors, (2498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2498 transitions. [2022-02-21 04:24:36,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:36,473 INFO L93 Difference]: Finished difference Result 1688 states and 2498 transitions. [2022-02-21 04:24:36,473 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2498 transitions. [2022-02-21 04:24:36,474 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:36,474 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:36,474 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:36,474 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:36,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4798578199052133) internal successors, (2498), 1687 states have internal predecessors, (2498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2498 transitions. [2022-02-21 04:24:36,551 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2022-02-21 04:24:36,551 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2498 transitions. [2022-02-21 04:24:36,551 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:36,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2498 transitions. [2022-02-21 04:24:36,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:36,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:36,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:36,556 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:36,556 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:36,557 INFO L791 eck$LassoCheckResult]: Stem: 44767#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 44768#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 45621#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45113#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44920#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 44921#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45006#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45307#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45429#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45430#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44218#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44219#L851-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 45367#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 44813#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44814#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 44720#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 44721#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45109#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44462#L1174 assume !(0 == ~M_E~0); 44463#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44314#L1179-1 assume !(0 == ~T2_E~0); 44216#L1184-1 assume !(0 == ~T3_E~0); 44217#L1189-1 assume !(0 == ~T4_E~0); 44255#L1194-1 assume !(0 == ~T5_E~0); 44355#L1199-1 assume !(0 == ~T6_E~0); 45250#L1204-1 assume !(0 == ~T7_E~0); 45169#L1209-1 assume !(0 == ~T8_E~0); 45170#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45558#L1219-1 assume !(0 == ~T10_E~0); 45643#L1224-1 assume !(0 == ~T11_E~0); 44580#L1229-1 assume !(0 == ~T12_E~0); 44141#L1234-1 assume !(0 == ~E_1~0); 44142#L1239-1 assume !(0 == ~E_2~0); 44175#L1244-1 assume !(0 == ~E_3~0); 44176#L1249-1 assume !(0 == ~E_4~0); 44837#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 44071#L1259-1 assume !(0 == ~E_6~0); 44026#L1264-1 assume !(0 == ~E_7~0); 44027#L1269-1 assume !(0 == ~E_8~0); 45648#L1274-1 assume !(0 == ~E_9~0); 45583#L1279-1 assume !(0 == ~E_10~0); 44259#L1284-1 assume !(0 == ~E_11~0); 44260#L1289-1 assume !(0 == ~E_12~0); 44889#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44890#L566 assume 1 == ~m_pc~0; 44043#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 44044#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45198#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45199#L1455 assume !(0 != activate_threads_~tmp~1#1); 44489#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44490#L585 assume 1 == ~t1_pc~0; 44138#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44139#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45139#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45140#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 45608#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45606#L604 assume !(1 == ~t2_pc~0); 45218#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 45219#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44752#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44753#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45390#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45391#L623 assume 1 == ~t3_pc~0; 44667#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44007#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44817#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44818#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 45425#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44040#L642 assume !(1 == ~t4_pc~0); 44041#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44506#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44507#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44112#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 44113#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45230#L661 assume 1 == ~t5_pc~0; 44277#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44278#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44239#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44240#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 45259#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45260#L680 assume !(1 == ~t6_pc~0); 44700#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 44701#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44962#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44963#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 45491#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45604#L699 assume 1 == ~t7_pc~0; 45090#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45091#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44267#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44268#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 44992#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44891#L718 assume !(1 == ~t8_pc~0); 44892#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 44253#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44254#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44295#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 44296#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44429#L737 assume 1 == ~t9_pc~0; 45294#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44564#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45165#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45166#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 44738#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44739#L756 assume 1 == ~t10_pc~0; 45318#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44984#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43970#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43971#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 44546#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44547#L775 assume !(1 == ~t11_pc~0); 44801#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 44802#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44423#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44187#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 44188#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44374#L794 assume 1 == ~t12_pc~0; 44214#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44192#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45385#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44340#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 44341#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44820#L1307 assume !(1 == ~M_E~0); 44821#L1307-2 assume !(1 == ~T1_E~0); 44932#L1312-1 assume !(1 == ~T2_E~0); 44851#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44852#L1322-1 assume !(1 == ~T4_E~0); 44555#L1327-1 assume !(1 == ~T5_E~0); 44556#L1332-1 assume !(1 == ~T6_E~0); 45094#L1337-1 assume !(1 == ~T7_E~0); 45056#L1342-1 assume !(1 == ~T8_E~0); 45057#L1347-1 assume !(1 == ~T9_E~0); 45454#L1352-1 assume !(1 == ~T10_E~0); 45327#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44718#L1362-1 assume !(1 == ~T12_E~0); 44719#L1367-1 assume !(1 == ~E_1~0); 44356#L1372-1 assume !(1 == ~E_2~0); 44357#L1377-1 assume !(1 == ~E_3~0); 44650#L1382-1 assume !(1 == ~E_4~0); 44651#L1387-1 assume !(1 == ~E_5~0); 45220#L1392-1 assume !(1 == ~E_6~0); 44670#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 44671#L1402-1 assume !(1 == ~E_8~0); 44367#L1407-1 assume !(1 == ~E_9~0); 44368#L1412-1 assume !(1 == ~E_10~0); 45383#L1417-1 assume !(1 == ~E_11~0); 45384#L1422-1 assume !(1 == ~E_12~0); 45602#L1427-1 assume { :end_inline_reset_delta_events } true; 44171#L1768-2 [2022-02-21 04:24:36,557 INFO L793 eck$LassoCheckResult]: Loop: 44171#L1768-2 assume !false; 44172#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44910#L1149 assume !false; 45282#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45435#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44561#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44467#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 44468#L976 assume !(0 != eval_~tmp~0#1); 45601#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45611#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45402#L1174-3 assume !(0 == ~M_E~0); 45395#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45144#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45145#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45328#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44979#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44329#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44330#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44571#L1209-3 assume !(0 == ~T8_E~0); 43991#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 43992#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 44750#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44751#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44769#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44179#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44180#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44623#L1249-3 assume !(0 == ~E_4~0); 45082#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45554#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45196#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 44185#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 44186#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45581#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44748#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44749#L1289-3 assume !(0 == ~E_12~0); 44737#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44413#L566-39 assume 1 == ~m_pc~0; 44414#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 45016#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44728#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 44729#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45271#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45272#L585-39 assume !(1 == ~t1_pc~0); 44421#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 44422#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44497#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 44498#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45304#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44997#L604-39 assume 1 == ~t2_pc~0; 44998#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44629#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44630#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45047#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45048#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44612#L623-39 assume 1 == ~t3_pc~0; 44008#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44010#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45288#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44464#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44465#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45236#L642-39 assume 1 == ~t4_pc~0; 44807#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44808#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44336#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44337#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45434#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44385#L661-39 assume !(1 == ~t5_pc~0); 44016#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 44017#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45377#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45378#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45291#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45292#L680-39 assume !(1 == ~t6_pc~0); 44080#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 44079#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45221#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44544#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 44545#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45559#L699-39 assume 1 == ~t7_pc~0; 44981#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44703#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44704#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45387#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45508#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45506#L718-39 assume !(1 == ~t8_pc~0); 44897#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 44896#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44828#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44829#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 45131#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45100#L737-39 assume 1 == ~t9_pc~0; 44525#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44526#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44815#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45582#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45483#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45426#L756-39 assume 1 == ~t10_pc~0; 45427#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44908#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44652#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44653#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44785#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44125#L775-39 assume 1 == ~t11_pc~0; 44126#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44778#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44779#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45641#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45189#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 44836#L794-39 assume 1 == ~t12_pc~0; 44528#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44522#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45342#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45243#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 44067#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44068#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 45535#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45536#L1312-3 assume !(1 == ~T2_E~0); 45647#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45261#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45262#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44206#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44177#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44178#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44924#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45049#L1352-3 assume !(1 == ~T10_E~0); 45050#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45489#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45640#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45631#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44004#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44005#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44636#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44637#L1392-3 assume !(1 == ~E_6~0); 45352#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45598#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45015#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 44291#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 44292#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44940#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44941#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 44301#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44302#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45168#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 45020#L1787 assume !(0 == start_simulation_~tmp~3#1); 45021#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45544#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44272#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45067#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 45068#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44619#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44620#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 44621#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 44171#L1768-2 [2022-02-21 04:24:36,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:36,558 INFO L85 PathProgramCache]: Analyzing trace with hash -1846000687, now seen corresponding path program 1 times [2022-02-21 04:24:36,558 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:36,558 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014965930] [2022-02-21 04:24:36,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:36,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:36,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:36,581 INFO L290 TraceCheckUtils]: 0: Hoare triple {49031#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {49031#true} is VALID [2022-02-21 04:24:36,582 INFO L290 TraceCheckUtils]: 1: Hoare triple {49031#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {49033#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:36,582 INFO L290 TraceCheckUtils]: 2: Hoare triple {49033#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {49033#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:36,582 INFO L290 TraceCheckUtils]: 3: Hoare triple {49033#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {49033#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:36,583 INFO L290 TraceCheckUtils]: 4: Hoare triple {49033#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {49033#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:36,583 INFO L290 TraceCheckUtils]: 5: Hoare triple {49033#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {49033#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:36,583 INFO L290 TraceCheckUtils]: 6: Hoare triple {49033#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {49033#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:36,584 INFO L290 TraceCheckUtils]: 7: Hoare triple {49033#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {49033#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:36,584 INFO L290 TraceCheckUtils]: 8: Hoare triple {49033#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {49033#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:36,584 INFO L290 TraceCheckUtils]: 9: Hoare triple {49033#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {49033#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:36,585 INFO L290 TraceCheckUtils]: 10: Hoare triple {49033#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {49033#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:36,585 INFO L290 TraceCheckUtils]: 11: Hoare triple {49033#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {49032#false} is VALID [2022-02-21 04:24:36,585 INFO L290 TraceCheckUtils]: 12: Hoare triple {49032#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {49032#false} is VALID [2022-02-21 04:24:36,585 INFO L290 TraceCheckUtils]: 13: Hoare triple {49032#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {49032#false} is VALID [2022-02-21 04:24:36,585 INFO L290 TraceCheckUtils]: 14: Hoare triple {49032#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {49032#false} is VALID [2022-02-21 04:24:36,586 INFO L290 TraceCheckUtils]: 15: Hoare triple {49032#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {49032#false} is VALID [2022-02-21 04:24:36,586 INFO L290 TraceCheckUtils]: 16: Hoare triple {49032#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {49032#false} is VALID [2022-02-21 04:24:36,586 INFO L290 TraceCheckUtils]: 17: Hoare triple {49032#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {49032#false} is VALID [2022-02-21 04:24:36,586 INFO L290 TraceCheckUtils]: 18: Hoare triple {49032#false} assume !(0 == ~M_E~0); {49032#false} is VALID [2022-02-21 04:24:36,586 INFO L290 TraceCheckUtils]: 19: Hoare triple {49032#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {49032#false} is VALID [2022-02-21 04:24:36,586 INFO L290 TraceCheckUtils]: 20: Hoare triple {49032#false} assume !(0 == ~T2_E~0); {49032#false} is VALID [2022-02-21 04:24:36,586 INFO L290 TraceCheckUtils]: 21: Hoare triple {49032#false} assume !(0 == ~T3_E~0); {49032#false} is VALID [2022-02-21 04:24:36,587 INFO L290 TraceCheckUtils]: 22: Hoare triple {49032#false} assume !(0 == ~T4_E~0); {49032#false} is VALID [2022-02-21 04:24:36,587 INFO L290 TraceCheckUtils]: 23: Hoare triple {49032#false} assume !(0 == ~T5_E~0); {49032#false} is VALID [2022-02-21 04:24:36,587 INFO L290 TraceCheckUtils]: 24: Hoare triple {49032#false} assume !(0 == ~T6_E~0); {49032#false} is VALID [2022-02-21 04:24:36,587 INFO L290 TraceCheckUtils]: 25: Hoare triple {49032#false} assume !(0 == ~T7_E~0); {49032#false} is VALID [2022-02-21 04:24:36,587 INFO L290 TraceCheckUtils]: 26: Hoare triple {49032#false} assume !(0 == ~T8_E~0); {49032#false} is VALID [2022-02-21 04:24:36,587 INFO L290 TraceCheckUtils]: 27: Hoare triple {49032#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {49032#false} is VALID [2022-02-21 04:24:36,587 INFO L290 TraceCheckUtils]: 28: Hoare triple {49032#false} assume !(0 == ~T10_E~0); {49032#false} is VALID [2022-02-21 04:24:36,587 INFO L290 TraceCheckUtils]: 29: Hoare triple {49032#false} assume !(0 == ~T11_E~0); {49032#false} is VALID [2022-02-21 04:24:36,588 INFO L290 TraceCheckUtils]: 30: Hoare triple {49032#false} assume !(0 == ~T12_E~0); {49032#false} is VALID [2022-02-21 04:24:36,588 INFO L290 TraceCheckUtils]: 31: Hoare triple {49032#false} assume !(0 == ~E_1~0); {49032#false} is VALID [2022-02-21 04:24:36,588 INFO L290 TraceCheckUtils]: 32: Hoare triple {49032#false} assume !(0 == ~E_2~0); {49032#false} is VALID [2022-02-21 04:24:36,588 INFO L290 TraceCheckUtils]: 33: Hoare triple {49032#false} assume !(0 == ~E_3~0); {49032#false} is VALID [2022-02-21 04:24:36,588 INFO L290 TraceCheckUtils]: 34: Hoare triple {49032#false} assume !(0 == ~E_4~0); {49032#false} is VALID [2022-02-21 04:24:36,588 INFO L290 TraceCheckUtils]: 35: Hoare triple {49032#false} assume 0 == ~E_5~0;~E_5~0 := 1; {49032#false} is VALID [2022-02-21 04:24:36,588 INFO L290 TraceCheckUtils]: 36: Hoare triple {49032#false} assume !(0 == ~E_6~0); {49032#false} is VALID [2022-02-21 04:24:36,589 INFO L290 TraceCheckUtils]: 37: Hoare triple {49032#false} assume !(0 == ~E_7~0); {49032#false} is VALID [2022-02-21 04:24:36,589 INFO L290 TraceCheckUtils]: 38: Hoare triple {49032#false} assume !(0 == ~E_8~0); {49032#false} is VALID [2022-02-21 04:24:36,589 INFO L290 TraceCheckUtils]: 39: Hoare triple {49032#false} assume !(0 == ~E_9~0); {49032#false} is VALID [2022-02-21 04:24:36,589 INFO L290 TraceCheckUtils]: 40: Hoare triple {49032#false} assume !(0 == ~E_10~0); {49032#false} is VALID [2022-02-21 04:24:36,589 INFO L290 TraceCheckUtils]: 41: Hoare triple {49032#false} assume !(0 == ~E_11~0); {49032#false} is VALID [2022-02-21 04:24:36,589 INFO L290 TraceCheckUtils]: 42: Hoare triple {49032#false} assume !(0 == ~E_12~0); {49032#false} is VALID [2022-02-21 04:24:36,589 INFO L290 TraceCheckUtils]: 43: Hoare triple {49032#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {49032#false} is VALID [2022-02-21 04:24:36,589 INFO L290 TraceCheckUtils]: 44: Hoare triple {49032#false} assume 1 == ~m_pc~0; {49032#false} is VALID [2022-02-21 04:24:36,590 INFO L290 TraceCheckUtils]: 45: Hoare triple {49032#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {49032#false} is VALID [2022-02-21 04:24:36,590 INFO L290 TraceCheckUtils]: 46: Hoare triple {49032#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {49032#false} is VALID [2022-02-21 04:24:36,590 INFO L290 TraceCheckUtils]: 47: Hoare triple {49032#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {49032#false} is VALID [2022-02-21 04:24:36,590 INFO L290 TraceCheckUtils]: 48: Hoare triple {49032#false} assume !(0 != activate_threads_~tmp~1#1); {49032#false} is VALID [2022-02-21 04:24:36,590 INFO L290 TraceCheckUtils]: 49: Hoare triple {49032#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {49032#false} is VALID [2022-02-21 04:24:36,590 INFO L290 TraceCheckUtils]: 50: Hoare triple {49032#false} assume 1 == ~t1_pc~0; {49032#false} is VALID [2022-02-21 04:24:36,590 INFO L290 TraceCheckUtils]: 51: Hoare triple {49032#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {49032#false} is VALID [2022-02-21 04:24:36,591 INFO L290 TraceCheckUtils]: 52: Hoare triple {49032#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {49032#false} is VALID [2022-02-21 04:24:36,591 INFO L290 TraceCheckUtils]: 53: Hoare triple {49032#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {49032#false} is VALID [2022-02-21 04:24:36,591 INFO L290 TraceCheckUtils]: 54: Hoare triple {49032#false} assume !(0 != activate_threads_~tmp___0~0#1); {49032#false} is VALID [2022-02-21 04:24:36,591 INFO L290 TraceCheckUtils]: 55: Hoare triple {49032#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {49032#false} is VALID [2022-02-21 04:24:36,591 INFO L290 TraceCheckUtils]: 56: Hoare triple {49032#false} assume !(1 == ~t2_pc~0); {49032#false} is VALID [2022-02-21 04:24:36,591 INFO L290 TraceCheckUtils]: 57: Hoare triple {49032#false} is_transmit2_triggered_~__retres1~2#1 := 0; {49032#false} is VALID [2022-02-21 04:24:36,591 INFO L290 TraceCheckUtils]: 58: Hoare triple {49032#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {49032#false} is VALID [2022-02-21 04:24:36,591 INFO L290 TraceCheckUtils]: 59: Hoare triple {49032#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {49032#false} is VALID [2022-02-21 04:24:36,592 INFO L290 TraceCheckUtils]: 60: Hoare triple {49032#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {49032#false} is VALID [2022-02-21 04:24:36,592 INFO L290 TraceCheckUtils]: 61: Hoare triple {49032#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {49032#false} is VALID [2022-02-21 04:24:36,592 INFO L290 TraceCheckUtils]: 62: Hoare triple {49032#false} assume 1 == ~t3_pc~0; {49032#false} is VALID [2022-02-21 04:24:36,592 INFO L290 TraceCheckUtils]: 63: Hoare triple {49032#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {49032#false} is VALID [2022-02-21 04:24:36,592 INFO L290 TraceCheckUtils]: 64: Hoare triple {49032#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {49032#false} is VALID [2022-02-21 04:24:36,592 INFO L290 TraceCheckUtils]: 65: Hoare triple {49032#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {49032#false} is VALID [2022-02-21 04:24:36,592 INFO L290 TraceCheckUtils]: 66: Hoare triple {49032#false} assume !(0 != activate_threads_~tmp___2~0#1); {49032#false} is VALID [2022-02-21 04:24:36,593 INFO L290 TraceCheckUtils]: 67: Hoare triple {49032#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {49032#false} is VALID [2022-02-21 04:24:36,593 INFO L290 TraceCheckUtils]: 68: Hoare triple {49032#false} assume !(1 == ~t4_pc~0); {49032#false} is VALID [2022-02-21 04:24:36,593 INFO L290 TraceCheckUtils]: 69: Hoare triple {49032#false} is_transmit4_triggered_~__retres1~4#1 := 0; {49032#false} is VALID [2022-02-21 04:24:36,593 INFO L290 TraceCheckUtils]: 70: Hoare triple {49032#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {49032#false} is VALID [2022-02-21 04:24:36,593 INFO L290 TraceCheckUtils]: 71: Hoare triple {49032#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {49032#false} is VALID [2022-02-21 04:24:36,593 INFO L290 TraceCheckUtils]: 72: Hoare triple {49032#false} assume !(0 != activate_threads_~tmp___3~0#1); {49032#false} is VALID [2022-02-21 04:24:36,593 INFO L290 TraceCheckUtils]: 73: Hoare triple {49032#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {49032#false} is VALID [2022-02-21 04:24:36,593 INFO L290 TraceCheckUtils]: 74: Hoare triple {49032#false} assume 1 == ~t5_pc~0; {49032#false} is VALID [2022-02-21 04:24:36,594 INFO L290 TraceCheckUtils]: 75: Hoare triple {49032#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {49032#false} is VALID [2022-02-21 04:24:36,594 INFO L290 TraceCheckUtils]: 76: Hoare triple {49032#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {49032#false} is VALID [2022-02-21 04:24:36,594 INFO L290 TraceCheckUtils]: 77: Hoare triple {49032#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {49032#false} is VALID [2022-02-21 04:24:36,594 INFO L290 TraceCheckUtils]: 78: Hoare triple {49032#false} assume !(0 != activate_threads_~tmp___4~0#1); {49032#false} is VALID [2022-02-21 04:24:36,594 INFO L290 TraceCheckUtils]: 79: Hoare triple {49032#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {49032#false} is VALID [2022-02-21 04:24:36,594 INFO L290 TraceCheckUtils]: 80: Hoare triple {49032#false} assume !(1 == ~t6_pc~0); {49032#false} is VALID [2022-02-21 04:24:36,594 INFO L290 TraceCheckUtils]: 81: Hoare triple {49032#false} is_transmit6_triggered_~__retres1~6#1 := 0; {49032#false} is VALID [2022-02-21 04:24:36,595 INFO L290 TraceCheckUtils]: 82: Hoare triple {49032#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {49032#false} is VALID [2022-02-21 04:24:36,595 INFO L290 TraceCheckUtils]: 83: Hoare triple {49032#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {49032#false} is VALID [2022-02-21 04:24:36,595 INFO L290 TraceCheckUtils]: 84: Hoare triple {49032#false} assume !(0 != activate_threads_~tmp___5~0#1); {49032#false} is VALID [2022-02-21 04:24:36,595 INFO L290 TraceCheckUtils]: 85: Hoare triple {49032#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {49032#false} is VALID [2022-02-21 04:24:36,595 INFO L290 TraceCheckUtils]: 86: Hoare triple {49032#false} assume 1 == ~t7_pc~0; {49032#false} is VALID [2022-02-21 04:24:36,595 INFO L290 TraceCheckUtils]: 87: Hoare triple {49032#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {49032#false} is VALID [2022-02-21 04:24:36,595 INFO L290 TraceCheckUtils]: 88: Hoare triple {49032#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {49032#false} is VALID [2022-02-21 04:24:36,596 INFO L290 TraceCheckUtils]: 89: Hoare triple {49032#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {49032#false} is VALID [2022-02-21 04:24:36,596 INFO L290 TraceCheckUtils]: 90: Hoare triple {49032#false} assume !(0 != activate_threads_~tmp___6~0#1); {49032#false} is VALID [2022-02-21 04:24:36,596 INFO L290 TraceCheckUtils]: 91: Hoare triple {49032#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {49032#false} is VALID [2022-02-21 04:24:36,596 INFO L290 TraceCheckUtils]: 92: Hoare triple {49032#false} assume !(1 == ~t8_pc~0); {49032#false} is VALID [2022-02-21 04:24:36,596 INFO L290 TraceCheckUtils]: 93: Hoare triple {49032#false} is_transmit8_triggered_~__retres1~8#1 := 0; {49032#false} is VALID [2022-02-21 04:24:36,596 INFO L290 TraceCheckUtils]: 94: Hoare triple {49032#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {49032#false} is VALID [2022-02-21 04:24:36,596 INFO L290 TraceCheckUtils]: 95: Hoare triple {49032#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {49032#false} is VALID [2022-02-21 04:24:36,596 INFO L290 TraceCheckUtils]: 96: Hoare triple {49032#false} assume !(0 != activate_threads_~tmp___7~0#1); {49032#false} is VALID [2022-02-21 04:24:36,597 INFO L290 TraceCheckUtils]: 97: Hoare triple {49032#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {49032#false} is VALID [2022-02-21 04:24:36,597 INFO L290 TraceCheckUtils]: 98: Hoare triple {49032#false} assume 1 == ~t9_pc~0; {49032#false} is VALID [2022-02-21 04:24:36,597 INFO L290 TraceCheckUtils]: 99: Hoare triple {49032#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {49032#false} is VALID [2022-02-21 04:24:36,597 INFO L290 TraceCheckUtils]: 100: Hoare triple {49032#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {49032#false} is VALID [2022-02-21 04:24:36,597 INFO L290 TraceCheckUtils]: 101: Hoare triple {49032#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {49032#false} is VALID [2022-02-21 04:24:36,597 INFO L290 TraceCheckUtils]: 102: Hoare triple {49032#false} assume !(0 != activate_threads_~tmp___8~0#1); {49032#false} is VALID [2022-02-21 04:24:36,597 INFO L290 TraceCheckUtils]: 103: Hoare triple {49032#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {49032#false} is VALID [2022-02-21 04:24:36,598 INFO L290 TraceCheckUtils]: 104: Hoare triple {49032#false} assume 1 == ~t10_pc~0; {49032#false} is VALID [2022-02-21 04:24:36,598 INFO L290 TraceCheckUtils]: 105: Hoare triple {49032#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {49032#false} is VALID [2022-02-21 04:24:36,598 INFO L290 TraceCheckUtils]: 106: Hoare triple {49032#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {49032#false} is VALID [2022-02-21 04:24:36,598 INFO L290 TraceCheckUtils]: 107: Hoare triple {49032#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {49032#false} is VALID [2022-02-21 04:24:36,598 INFO L290 TraceCheckUtils]: 108: Hoare triple {49032#false} assume !(0 != activate_threads_~tmp___9~0#1); {49032#false} is VALID [2022-02-21 04:24:36,598 INFO L290 TraceCheckUtils]: 109: Hoare triple {49032#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {49032#false} is VALID [2022-02-21 04:24:36,598 INFO L290 TraceCheckUtils]: 110: Hoare triple {49032#false} assume !(1 == ~t11_pc~0); {49032#false} is VALID [2022-02-21 04:24:36,598 INFO L290 TraceCheckUtils]: 111: Hoare triple {49032#false} is_transmit11_triggered_~__retres1~11#1 := 0; {49032#false} is VALID [2022-02-21 04:24:36,599 INFO L290 TraceCheckUtils]: 112: Hoare triple {49032#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {49032#false} is VALID [2022-02-21 04:24:36,599 INFO L290 TraceCheckUtils]: 113: Hoare triple {49032#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {49032#false} is VALID [2022-02-21 04:24:36,599 INFO L290 TraceCheckUtils]: 114: Hoare triple {49032#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {49032#false} is VALID [2022-02-21 04:24:36,599 INFO L290 TraceCheckUtils]: 115: Hoare triple {49032#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {49032#false} is VALID [2022-02-21 04:24:36,599 INFO L290 TraceCheckUtils]: 116: Hoare triple {49032#false} assume 1 == ~t12_pc~0; {49032#false} is VALID [2022-02-21 04:24:36,599 INFO L290 TraceCheckUtils]: 117: Hoare triple {49032#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {49032#false} is VALID [2022-02-21 04:24:36,599 INFO L290 TraceCheckUtils]: 118: Hoare triple {49032#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {49032#false} is VALID [2022-02-21 04:24:36,599 INFO L290 TraceCheckUtils]: 119: Hoare triple {49032#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {49032#false} is VALID [2022-02-21 04:24:36,600 INFO L290 TraceCheckUtils]: 120: Hoare triple {49032#false} assume !(0 != activate_threads_~tmp___11~0#1); {49032#false} is VALID [2022-02-21 04:24:36,600 INFO L290 TraceCheckUtils]: 121: Hoare triple {49032#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {49032#false} is VALID [2022-02-21 04:24:36,600 INFO L290 TraceCheckUtils]: 122: Hoare triple {49032#false} assume !(1 == ~M_E~0); {49032#false} is VALID [2022-02-21 04:24:36,600 INFO L290 TraceCheckUtils]: 123: Hoare triple {49032#false} assume !(1 == ~T1_E~0); {49032#false} is VALID [2022-02-21 04:24:36,600 INFO L290 TraceCheckUtils]: 124: Hoare triple {49032#false} assume !(1 == ~T2_E~0); {49032#false} is VALID [2022-02-21 04:24:36,600 INFO L290 TraceCheckUtils]: 125: Hoare triple {49032#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {49032#false} is VALID [2022-02-21 04:24:36,600 INFO L290 TraceCheckUtils]: 126: Hoare triple {49032#false} assume !(1 == ~T4_E~0); {49032#false} is VALID [2022-02-21 04:24:36,601 INFO L290 TraceCheckUtils]: 127: Hoare triple {49032#false} assume !(1 == ~T5_E~0); {49032#false} is VALID [2022-02-21 04:24:36,601 INFO L290 TraceCheckUtils]: 128: Hoare triple {49032#false} assume !(1 == ~T6_E~0); {49032#false} is VALID [2022-02-21 04:24:36,601 INFO L290 TraceCheckUtils]: 129: Hoare triple {49032#false} assume !(1 == ~T7_E~0); {49032#false} is VALID [2022-02-21 04:24:36,601 INFO L290 TraceCheckUtils]: 130: Hoare triple {49032#false} assume !(1 == ~T8_E~0); {49032#false} is VALID [2022-02-21 04:24:36,601 INFO L290 TraceCheckUtils]: 131: Hoare triple {49032#false} assume !(1 == ~T9_E~0); {49032#false} is VALID [2022-02-21 04:24:36,601 INFO L290 TraceCheckUtils]: 132: Hoare triple {49032#false} assume !(1 == ~T10_E~0); {49032#false} is VALID [2022-02-21 04:24:36,601 INFO L290 TraceCheckUtils]: 133: Hoare triple {49032#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {49032#false} is VALID [2022-02-21 04:24:36,601 INFO L290 TraceCheckUtils]: 134: Hoare triple {49032#false} assume !(1 == ~T12_E~0); {49032#false} is VALID [2022-02-21 04:24:36,602 INFO L290 TraceCheckUtils]: 135: Hoare triple {49032#false} assume !(1 == ~E_1~0); {49032#false} is VALID [2022-02-21 04:24:36,602 INFO L290 TraceCheckUtils]: 136: Hoare triple {49032#false} assume !(1 == ~E_2~0); {49032#false} is VALID [2022-02-21 04:24:36,602 INFO L290 TraceCheckUtils]: 137: Hoare triple {49032#false} assume !(1 == ~E_3~0); {49032#false} is VALID [2022-02-21 04:24:36,602 INFO L290 TraceCheckUtils]: 138: Hoare triple {49032#false} assume !(1 == ~E_4~0); {49032#false} is VALID [2022-02-21 04:24:36,602 INFO L290 TraceCheckUtils]: 139: Hoare triple {49032#false} assume !(1 == ~E_5~0); {49032#false} is VALID [2022-02-21 04:24:36,602 INFO L290 TraceCheckUtils]: 140: Hoare triple {49032#false} assume !(1 == ~E_6~0); {49032#false} is VALID [2022-02-21 04:24:36,602 INFO L290 TraceCheckUtils]: 141: Hoare triple {49032#false} assume 1 == ~E_7~0;~E_7~0 := 2; {49032#false} is VALID [2022-02-21 04:24:36,603 INFO L290 TraceCheckUtils]: 142: Hoare triple {49032#false} assume !(1 == ~E_8~0); {49032#false} is VALID [2022-02-21 04:24:36,603 INFO L290 TraceCheckUtils]: 143: Hoare triple {49032#false} assume !(1 == ~E_9~0); {49032#false} is VALID [2022-02-21 04:24:36,603 INFO L290 TraceCheckUtils]: 144: Hoare triple {49032#false} assume !(1 == ~E_10~0); {49032#false} is VALID [2022-02-21 04:24:36,603 INFO L290 TraceCheckUtils]: 145: Hoare triple {49032#false} assume !(1 == ~E_11~0); {49032#false} is VALID [2022-02-21 04:24:36,603 INFO L290 TraceCheckUtils]: 146: Hoare triple {49032#false} assume !(1 == ~E_12~0); {49032#false} is VALID [2022-02-21 04:24:36,603 INFO L290 TraceCheckUtils]: 147: Hoare triple {49032#false} assume { :end_inline_reset_delta_events } true; {49032#false} is VALID [2022-02-21 04:24:36,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:36,604 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:36,604 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014965930] [2022-02-21 04:24:36,604 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014965930] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:36,604 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:36,604 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:36,605 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1565334215] [2022-02-21 04:24:36,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:36,605 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:36,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:36,606 INFO L85 PathProgramCache]: Analyzing trace with hash 852354849, now seen corresponding path program 1 times [2022-02-21 04:24:36,606 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:36,606 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937979501] [2022-02-21 04:24:36,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:36,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:36,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:36,634 INFO L290 TraceCheckUtils]: 0: Hoare triple {49034#true} assume !false; {49034#true} is VALID [2022-02-21 04:24:36,635 INFO L290 TraceCheckUtils]: 1: Hoare triple {49034#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {49034#true} is VALID [2022-02-21 04:24:36,635 INFO L290 TraceCheckUtils]: 2: Hoare triple {49034#true} assume !false; {49034#true} is VALID [2022-02-21 04:24:36,635 INFO L290 TraceCheckUtils]: 3: Hoare triple {49034#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {49034#true} is VALID [2022-02-21 04:24:36,635 INFO L290 TraceCheckUtils]: 4: Hoare triple {49034#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {49034#true} is VALID [2022-02-21 04:24:36,635 INFO L290 TraceCheckUtils]: 5: Hoare triple {49034#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {49034#true} is VALID [2022-02-21 04:24:36,636 INFO L290 TraceCheckUtils]: 6: Hoare triple {49034#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {49034#true} is VALID [2022-02-21 04:24:36,636 INFO L290 TraceCheckUtils]: 7: Hoare triple {49034#true} assume !(0 != eval_~tmp~0#1); {49034#true} is VALID [2022-02-21 04:24:36,636 INFO L290 TraceCheckUtils]: 8: Hoare triple {49034#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {49034#true} is VALID [2022-02-21 04:24:36,636 INFO L290 TraceCheckUtils]: 9: Hoare triple {49034#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {49034#true} is VALID [2022-02-21 04:24:36,636 INFO L290 TraceCheckUtils]: 10: Hoare triple {49034#true} assume !(0 == ~M_E~0); {49034#true} is VALID [2022-02-21 04:24:36,636 INFO L290 TraceCheckUtils]: 11: Hoare triple {49034#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {49034#true} is VALID [2022-02-21 04:24:36,636 INFO L290 TraceCheckUtils]: 12: Hoare triple {49034#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,637 INFO L290 TraceCheckUtils]: 13: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,637 INFO L290 TraceCheckUtils]: 14: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,637 INFO L290 TraceCheckUtils]: 15: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,638 INFO L290 TraceCheckUtils]: 16: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,638 INFO L290 TraceCheckUtils]: 17: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,638 INFO L290 TraceCheckUtils]: 18: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,639 INFO L290 TraceCheckUtils]: 19: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,639 INFO L290 TraceCheckUtils]: 20: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,639 INFO L290 TraceCheckUtils]: 21: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,640 INFO L290 TraceCheckUtils]: 22: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,640 INFO L290 TraceCheckUtils]: 23: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,640 INFO L290 TraceCheckUtils]: 24: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,640 INFO L290 TraceCheckUtils]: 25: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,641 INFO L290 TraceCheckUtils]: 26: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,641 INFO L290 TraceCheckUtils]: 27: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,641 INFO L290 TraceCheckUtils]: 28: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,642 INFO L290 TraceCheckUtils]: 29: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,642 INFO L290 TraceCheckUtils]: 30: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,642 INFO L290 TraceCheckUtils]: 31: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,643 INFO L290 TraceCheckUtils]: 32: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,643 INFO L290 TraceCheckUtils]: 33: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,643 INFO L290 TraceCheckUtils]: 34: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,644 INFO L290 TraceCheckUtils]: 35: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,644 INFO L290 TraceCheckUtils]: 36: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,644 INFO L290 TraceCheckUtils]: 37: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,645 INFO L290 TraceCheckUtils]: 38: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,645 INFO L290 TraceCheckUtils]: 39: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,645 INFO L290 TraceCheckUtils]: 40: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,646 INFO L290 TraceCheckUtils]: 41: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,646 INFO L290 TraceCheckUtils]: 42: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,646 INFO L290 TraceCheckUtils]: 43: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,647 INFO L290 TraceCheckUtils]: 44: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,647 INFO L290 TraceCheckUtils]: 45: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,647 INFO L290 TraceCheckUtils]: 46: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,648 INFO L290 TraceCheckUtils]: 47: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,648 INFO L290 TraceCheckUtils]: 48: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,648 INFO L290 TraceCheckUtils]: 49: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,649 INFO L290 TraceCheckUtils]: 50: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,649 INFO L290 TraceCheckUtils]: 51: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,649 INFO L290 TraceCheckUtils]: 52: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,650 INFO L290 TraceCheckUtils]: 53: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,650 INFO L290 TraceCheckUtils]: 54: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,650 INFO L290 TraceCheckUtils]: 55: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,650 INFO L290 TraceCheckUtils]: 56: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,651 INFO L290 TraceCheckUtils]: 57: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,651 INFO L290 TraceCheckUtils]: 58: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,652 INFO L290 TraceCheckUtils]: 59: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,652 INFO L290 TraceCheckUtils]: 60: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,652 INFO L290 TraceCheckUtils]: 61: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,653 INFO L290 TraceCheckUtils]: 62: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,653 INFO L290 TraceCheckUtils]: 63: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,653 INFO L290 TraceCheckUtils]: 64: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,653 INFO L290 TraceCheckUtils]: 65: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,654 INFO L290 TraceCheckUtils]: 66: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,654 INFO L290 TraceCheckUtils]: 67: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,654 INFO L290 TraceCheckUtils]: 68: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,655 INFO L290 TraceCheckUtils]: 69: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,655 INFO L290 TraceCheckUtils]: 70: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,655 INFO L290 TraceCheckUtils]: 71: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,656 INFO L290 TraceCheckUtils]: 72: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,656 INFO L290 TraceCheckUtils]: 73: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,656 INFO L290 TraceCheckUtils]: 74: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,657 INFO L290 TraceCheckUtils]: 75: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,657 INFO L290 TraceCheckUtils]: 76: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,657 INFO L290 TraceCheckUtils]: 77: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,658 INFO L290 TraceCheckUtils]: 78: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,658 INFO L290 TraceCheckUtils]: 79: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,658 INFO L290 TraceCheckUtils]: 80: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,659 INFO L290 TraceCheckUtils]: 81: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,659 INFO L290 TraceCheckUtils]: 82: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,659 INFO L290 TraceCheckUtils]: 83: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,660 INFO L290 TraceCheckUtils]: 84: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,660 INFO L290 TraceCheckUtils]: 85: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,660 INFO L290 TraceCheckUtils]: 86: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,661 INFO L290 TraceCheckUtils]: 87: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,661 INFO L290 TraceCheckUtils]: 88: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,661 INFO L290 TraceCheckUtils]: 89: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,662 INFO L290 TraceCheckUtils]: 90: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,662 INFO L290 TraceCheckUtils]: 91: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,662 INFO L290 TraceCheckUtils]: 92: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,662 INFO L290 TraceCheckUtils]: 93: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,663 INFO L290 TraceCheckUtils]: 94: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,663 INFO L290 TraceCheckUtils]: 95: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,663 INFO L290 TraceCheckUtils]: 96: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,664 INFO L290 TraceCheckUtils]: 97: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,664 INFO L290 TraceCheckUtils]: 98: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,664 INFO L290 TraceCheckUtils]: 99: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,665 INFO L290 TraceCheckUtils]: 100: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,665 INFO L290 TraceCheckUtils]: 101: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,665 INFO L290 TraceCheckUtils]: 102: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,666 INFO L290 TraceCheckUtils]: 103: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,666 INFO L290 TraceCheckUtils]: 104: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,666 INFO L290 TraceCheckUtils]: 105: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,667 INFO L290 TraceCheckUtils]: 106: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,667 INFO L290 TraceCheckUtils]: 107: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,667 INFO L290 TraceCheckUtils]: 108: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t12_pc~0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,668 INFO L290 TraceCheckUtils]: 109: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,668 INFO L290 TraceCheckUtils]: 110: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,668 INFO L290 TraceCheckUtils]: 111: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,669 INFO L290 TraceCheckUtils]: 112: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,669 INFO L290 TraceCheckUtils]: 113: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,669 INFO L290 TraceCheckUtils]: 114: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,670 INFO L290 TraceCheckUtils]: 115: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {49036#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:36,670 INFO L290 TraceCheckUtils]: 116: Hoare triple {49036#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {49035#false} is VALID [2022-02-21 04:24:36,670 INFO L290 TraceCheckUtils]: 117: Hoare triple {49035#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,670 INFO L290 TraceCheckUtils]: 118: Hoare triple {49035#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,670 INFO L290 TraceCheckUtils]: 119: Hoare triple {49035#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,670 INFO L290 TraceCheckUtils]: 120: Hoare triple {49035#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,671 INFO L290 TraceCheckUtils]: 121: Hoare triple {49035#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,671 INFO L290 TraceCheckUtils]: 122: Hoare triple {49035#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,671 INFO L290 TraceCheckUtils]: 123: Hoare triple {49035#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,671 INFO L290 TraceCheckUtils]: 124: Hoare triple {49035#false} assume !(1 == ~T10_E~0); {49035#false} is VALID [2022-02-21 04:24:36,671 INFO L290 TraceCheckUtils]: 125: Hoare triple {49035#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,671 INFO L290 TraceCheckUtils]: 126: Hoare triple {49035#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,671 INFO L290 TraceCheckUtils]: 127: Hoare triple {49035#false} assume 1 == ~E_1~0;~E_1~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,672 INFO L290 TraceCheckUtils]: 128: Hoare triple {49035#false} assume 1 == ~E_2~0;~E_2~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,672 INFO L290 TraceCheckUtils]: 129: Hoare triple {49035#false} assume 1 == ~E_3~0;~E_3~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,672 INFO L290 TraceCheckUtils]: 130: Hoare triple {49035#false} assume 1 == ~E_4~0;~E_4~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,672 INFO L290 TraceCheckUtils]: 131: Hoare triple {49035#false} assume 1 == ~E_5~0;~E_5~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,672 INFO L290 TraceCheckUtils]: 132: Hoare triple {49035#false} assume !(1 == ~E_6~0); {49035#false} is VALID [2022-02-21 04:24:36,672 INFO L290 TraceCheckUtils]: 133: Hoare triple {49035#false} assume 1 == ~E_7~0;~E_7~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,672 INFO L290 TraceCheckUtils]: 134: Hoare triple {49035#false} assume 1 == ~E_8~0;~E_8~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,672 INFO L290 TraceCheckUtils]: 135: Hoare triple {49035#false} assume 1 == ~E_9~0;~E_9~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,673 INFO L290 TraceCheckUtils]: 136: Hoare triple {49035#false} assume 1 == ~E_10~0;~E_10~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,673 INFO L290 TraceCheckUtils]: 137: Hoare triple {49035#false} assume 1 == ~E_11~0;~E_11~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,673 INFO L290 TraceCheckUtils]: 138: Hoare triple {49035#false} assume 1 == ~E_12~0;~E_12~0 := 2; {49035#false} is VALID [2022-02-21 04:24:36,673 INFO L290 TraceCheckUtils]: 139: Hoare triple {49035#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {49035#false} is VALID [2022-02-21 04:24:36,673 INFO L290 TraceCheckUtils]: 140: Hoare triple {49035#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {49035#false} is VALID [2022-02-21 04:24:36,673 INFO L290 TraceCheckUtils]: 141: Hoare triple {49035#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {49035#false} is VALID [2022-02-21 04:24:36,673 INFO L290 TraceCheckUtils]: 142: Hoare triple {49035#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {49035#false} is VALID [2022-02-21 04:24:36,674 INFO L290 TraceCheckUtils]: 143: Hoare triple {49035#false} assume !(0 == start_simulation_~tmp~3#1); {49035#false} is VALID [2022-02-21 04:24:36,674 INFO L290 TraceCheckUtils]: 144: Hoare triple {49035#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {49035#false} is VALID [2022-02-21 04:24:36,674 INFO L290 TraceCheckUtils]: 145: Hoare triple {49035#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {49035#false} is VALID [2022-02-21 04:24:36,674 INFO L290 TraceCheckUtils]: 146: Hoare triple {49035#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {49035#false} is VALID [2022-02-21 04:24:36,674 INFO L290 TraceCheckUtils]: 147: Hoare triple {49035#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {49035#false} is VALID [2022-02-21 04:24:36,674 INFO L290 TraceCheckUtils]: 148: Hoare triple {49035#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {49035#false} is VALID [2022-02-21 04:24:36,674 INFO L290 TraceCheckUtils]: 149: Hoare triple {49035#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {49035#false} is VALID [2022-02-21 04:24:36,674 INFO L290 TraceCheckUtils]: 150: Hoare triple {49035#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {49035#false} is VALID [2022-02-21 04:24:36,675 INFO L290 TraceCheckUtils]: 151: Hoare triple {49035#false} assume !(0 != start_simulation_~tmp___0~1#1); {49035#false} is VALID [2022-02-21 04:24:36,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:36,675 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:36,677 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937979501] [2022-02-21 04:24:36,679 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937979501] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:36,679 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:36,679 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:36,679 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [798394981] [2022-02-21 04:24:36,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:36,680 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:36,680 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:36,681 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:36,681 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:36,681 INFO L87 Difference]: Start difference. First operand 1688 states and 2498 transitions. cyclomatic complexity: 811 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:37,789 INFO L93 Difference]: Finished difference Result 1688 states and 2497 transitions. [2022-02-21 04:24:37,790 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:37,790 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:37,861 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:37,863 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2497 transitions. [2022-02-21 04:24:37,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:38,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2497 transitions. [2022-02-21 04:24:38,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:38,070 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:38,070 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2497 transitions. [2022-02-21 04:24:38,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:38,072 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2022-02-21 04:24:38,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2497 transitions. [2022-02-21 04:24:38,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:38,094 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:38,096 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2497 transitions. Second operand has 1688 states, 1688 states have (on average 1.4792654028436019) internal successors, (2497), 1687 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,097 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2497 transitions. Second operand has 1688 states, 1688 states have (on average 1.4792654028436019) internal successors, (2497), 1687 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,098 INFO L87 Difference]: Start difference. First operand 1688 states and 2497 transitions. Second operand has 1688 states, 1688 states have (on average 1.4792654028436019) internal successors, (2497), 1687 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:38,197 INFO L93 Difference]: Finished difference Result 1688 states and 2497 transitions. [2022-02-21 04:24:38,197 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2497 transitions. [2022-02-21 04:24:38,199 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:38,199 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:38,202 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.4792654028436019) internal successors, (2497), 1687 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2497 transitions. [2022-02-21 04:24:38,203 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.4792654028436019) internal successors, (2497), 1687 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2497 transitions. [2022-02-21 04:24:38,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:38,303 INFO L93 Difference]: Finished difference Result 1688 states and 2497 transitions. [2022-02-21 04:24:38,304 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2497 transitions. [2022-02-21 04:24:38,305 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:38,306 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:38,306 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:38,306 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:38,308 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4792654028436019) internal successors, (2497), 1687 states have internal predecessors, (2497), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2497 transitions. [2022-02-21 04:24:38,408 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2022-02-21 04:24:38,408 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2497 transitions. [2022-02-21 04:24:38,408 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:38,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2497 transitions. [2022-02-21 04:24:38,412 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:38,412 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:38,412 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:38,414 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:38,414 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:38,414 INFO L791 eck$LassoCheckResult]: Stem: 51530#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 51531#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 52382#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51876#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51681#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 51682#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51767#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52072#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52190#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52191#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50979#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50980#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52128#L856-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 51574#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 51575#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 51483#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 51484#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 51871#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51223#L1174 assume !(0 == ~M_E~0); 51224#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51075#L1179-1 assume !(0 == ~T2_E~0); 50977#L1184-1 assume !(0 == ~T3_E~0); 50978#L1189-1 assume !(0 == ~T4_E~0); 51016#L1194-1 assume !(0 == ~T5_E~0); 51118#L1199-1 assume !(0 == ~T6_E~0); 52011#L1204-1 assume !(0 == ~T7_E~0); 51930#L1209-1 assume !(0 == ~T8_E~0); 51931#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 52319#L1219-1 assume !(0 == ~T10_E~0); 52404#L1224-1 assume !(0 == ~T11_E~0); 51342#L1229-1 assume !(0 == ~T12_E~0); 50904#L1234-1 assume !(0 == ~E_1~0); 50905#L1239-1 assume !(0 == ~E_2~0); 50938#L1244-1 assume !(0 == ~E_3~0); 50939#L1249-1 assume !(0 == ~E_4~0); 51598#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 50832#L1259-1 assume !(0 == ~E_6~0); 50787#L1264-1 assume !(0 == ~E_7~0); 50788#L1269-1 assume !(0 == ~E_8~0); 52409#L1274-1 assume !(0 == ~E_9~0); 52344#L1279-1 assume !(0 == ~E_10~0); 51020#L1284-1 assume !(0 == ~E_11~0); 51021#L1289-1 assume !(0 == ~E_12~0); 51650#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51651#L566 assume 1 == ~m_pc~0; 50804#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50805#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51959#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51960#L1455 assume !(0 != activate_threads_~tmp~1#1); 51250#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51251#L585 assume 1 == ~t1_pc~0; 50899#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50900#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51900#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51901#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 52369#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52367#L604 assume !(1 == ~t2_pc~0); 51979#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51980#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51513#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51514#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52153#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52154#L623 assume 1 == ~t3_pc~0; 51428#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50768#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51578#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51579#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 52186#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50801#L642 assume !(1 == ~t4_pc~0); 50802#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51267#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51268#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50875#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 50876#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51991#L661 assume 1 == ~t5_pc~0; 51038#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51039#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51000#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51001#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 52022#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52023#L680 assume !(1 == ~t6_pc~0); 51461#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 51462#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51723#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51724#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 52252#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52365#L699 assume 1 == ~t7_pc~0; 51851#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51852#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51028#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51029#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 51753#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51652#L718 assume !(1 == ~t8_pc~0); 51653#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 51014#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51015#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51058#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 51059#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51190#L737 assume 1 == ~t9_pc~0; 52056#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51326#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51926#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51927#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 51499#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51500#L756 assume 1 == ~t10_pc~0; 52079#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51745#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50731#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50732#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 51307#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51308#L775 assume !(1 == ~t11_pc~0); 51562#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 51563#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51184#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50948#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50949#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51135#L794 assume 1 == ~t12_pc~0; 50975#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50953#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52146#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51101#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 51102#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51581#L1307 assume !(1 == ~M_E~0); 51582#L1307-2 assume !(1 == ~T1_E~0); 51693#L1312-1 assume !(1 == ~T2_E~0); 51612#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51613#L1322-1 assume !(1 == ~T4_E~0); 51316#L1327-1 assume !(1 == ~T5_E~0); 51317#L1332-1 assume !(1 == ~T6_E~0); 51855#L1337-1 assume !(1 == ~T7_E~0); 51817#L1342-1 assume !(1 == ~T8_E~0); 51818#L1347-1 assume !(1 == ~T9_E~0); 52215#L1352-1 assume !(1 == ~T10_E~0); 52088#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 51479#L1362-1 assume !(1 == ~T12_E~0); 51480#L1367-1 assume !(1 == ~E_1~0); 51116#L1372-1 assume !(1 == ~E_2~0); 51117#L1377-1 assume !(1 == ~E_3~0); 51411#L1382-1 assume !(1 == ~E_4~0); 51412#L1387-1 assume !(1 == ~E_5~0); 51981#L1392-1 assume !(1 == ~E_6~0); 51431#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 51432#L1402-1 assume !(1 == ~E_8~0); 51128#L1407-1 assume !(1 == ~E_9~0); 51129#L1412-1 assume !(1 == ~E_10~0); 52144#L1417-1 assume !(1 == ~E_11~0); 52145#L1422-1 assume !(1 == ~E_12~0); 52363#L1427-1 assume { :end_inline_reset_delta_events } true; 50932#L1768-2 [2022-02-21 04:24:38,414 INFO L793 eck$LassoCheckResult]: Loop: 50932#L1768-2 assume !false; 50933#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51671#L1149 assume !false; 52043#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52196#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51322#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51228#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 51229#L976 assume !(0 != eval_~tmp~0#1); 52362#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52372#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52163#L1174-3 assume !(0 == ~M_E~0); 52156#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 51905#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51906#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52089#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51740#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51090#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51091#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51332#L1209-3 assume !(0 == ~T8_E~0); 50752#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50753#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51511#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51512#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 51528#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50940#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50941#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51384#L1249-3 assume !(0 == ~E_4~0); 51843#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 52315#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51957#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50946#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50947#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 52342#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 51509#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51510#L1289-3 assume !(0 == ~E_12~0); 51498#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51174#L566-39 assume 1 == ~m_pc~0; 51175#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51777#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51489#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51490#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52032#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52033#L585-39 assume !(1 == ~t1_pc~0); 51182#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 51183#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51258#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51259#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52065#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51758#L604-39 assume !(1 == ~t2_pc~0); 51760#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 51390#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51391#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51808#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51809#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51373#L623-39 assume 1 == ~t3_pc~0; 50769#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50771#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52049#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51225#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51226#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51997#L642-39 assume 1 == ~t4_pc~0; 51568#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51569#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51097#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51098#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52195#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51146#L661-39 assume !(1 == ~t5_pc~0); 50777#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 50778#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52138#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52139#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 52052#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52053#L680-39 assume 1 == ~t6_pc~0; 50839#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50840#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51982#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51305#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51306#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52320#L699-39 assume 1 == ~t7_pc~0; 51742#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51464#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51465#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52148#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52269#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52267#L718-39 assume 1 == ~t8_pc~0; 51656#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51657#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51589#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51590#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 51892#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51861#L737-39 assume 1 == ~t9_pc~0; 51286#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51287#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51576#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 52343#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52244#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52187#L756-39 assume !(1 == ~t10_pc~0); 51668#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 51669#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51413#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51414#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51546#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50886#L775-39 assume 1 == ~t11_pc~0; 50887#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51539#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51540#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52402#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 51950#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51597#L794-39 assume !(1 == ~t12_pc~0); 51282#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 51283#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52103#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52004#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50828#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50829#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 52296#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52297#L1312-3 assume !(1 == ~T2_E~0); 52408#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52020#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52021#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50967#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50936#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50937#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 51685#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 51810#L1352-3 assume !(1 == ~T10_E~0); 51811#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52250#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52401#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52392#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50765#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50766#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 51397#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 51398#L1392-3 assume !(1 == ~E_6~0); 52113#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 52359#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 51776#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51052#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51053#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 51701#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 51702#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 51062#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51063#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51929#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 51781#L1787 assume !(0 == start_simulation_~tmp~3#1); 51782#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 52305#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 51033#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 51828#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 51829#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51380#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51381#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 51382#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 50932#L1768-2 [2022-02-21 04:24:38,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:38,415 INFO L85 PathProgramCache]: Analyzing trace with hash -1915648561, now seen corresponding path program 1 times [2022-02-21 04:24:38,415 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:38,416 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73310339] [2022-02-21 04:24:38,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:38,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:38,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:38,439 INFO L290 TraceCheckUtils]: 0: Hoare triple {55792#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {55792#true} is VALID [2022-02-21 04:24:38,439 INFO L290 TraceCheckUtils]: 1: Hoare triple {55792#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {55794#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:38,440 INFO L290 TraceCheckUtils]: 2: Hoare triple {55794#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {55794#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:38,440 INFO L290 TraceCheckUtils]: 3: Hoare triple {55794#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {55794#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:38,440 INFO L290 TraceCheckUtils]: 4: Hoare triple {55794#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {55794#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:38,440 INFO L290 TraceCheckUtils]: 5: Hoare triple {55794#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {55794#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:38,441 INFO L290 TraceCheckUtils]: 6: Hoare triple {55794#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {55794#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:38,441 INFO L290 TraceCheckUtils]: 7: Hoare triple {55794#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {55794#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:38,441 INFO L290 TraceCheckUtils]: 8: Hoare triple {55794#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {55794#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:38,442 INFO L290 TraceCheckUtils]: 9: Hoare triple {55794#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {55794#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:38,442 INFO L290 TraceCheckUtils]: 10: Hoare triple {55794#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {55794#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:38,442 INFO L290 TraceCheckUtils]: 11: Hoare triple {55794#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {55794#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:38,443 INFO L290 TraceCheckUtils]: 12: Hoare triple {55794#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {55793#false} is VALID [2022-02-21 04:24:38,443 INFO L290 TraceCheckUtils]: 13: Hoare triple {55793#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {55793#false} is VALID [2022-02-21 04:24:38,443 INFO L290 TraceCheckUtils]: 14: Hoare triple {55793#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {55793#false} is VALID [2022-02-21 04:24:38,443 INFO L290 TraceCheckUtils]: 15: Hoare triple {55793#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {55793#false} is VALID [2022-02-21 04:24:38,443 INFO L290 TraceCheckUtils]: 16: Hoare triple {55793#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {55793#false} is VALID [2022-02-21 04:24:38,443 INFO L290 TraceCheckUtils]: 17: Hoare triple {55793#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {55793#false} is VALID [2022-02-21 04:24:38,443 INFO L290 TraceCheckUtils]: 18: Hoare triple {55793#false} assume !(0 == ~M_E~0); {55793#false} is VALID [2022-02-21 04:24:38,444 INFO L290 TraceCheckUtils]: 19: Hoare triple {55793#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {55793#false} is VALID [2022-02-21 04:24:38,444 INFO L290 TraceCheckUtils]: 20: Hoare triple {55793#false} assume !(0 == ~T2_E~0); {55793#false} is VALID [2022-02-21 04:24:38,444 INFO L290 TraceCheckUtils]: 21: Hoare triple {55793#false} assume !(0 == ~T3_E~0); {55793#false} is VALID [2022-02-21 04:24:38,444 INFO L290 TraceCheckUtils]: 22: Hoare triple {55793#false} assume !(0 == ~T4_E~0); {55793#false} is VALID [2022-02-21 04:24:38,444 INFO L290 TraceCheckUtils]: 23: Hoare triple {55793#false} assume !(0 == ~T5_E~0); {55793#false} is VALID [2022-02-21 04:24:38,444 INFO L290 TraceCheckUtils]: 24: Hoare triple {55793#false} assume !(0 == ~T6_E~0); {55793#false} is VALID [2022-02-21 04:24:38,444 INFO L290 TraceCheckUtils]: 25: Hoare triple {55793#false} assume !(0 == ~T7_E~0); {55793#false} is VALID [2022-02-21 04:24:38,444 INFO L290 TraceCheckUtils]: 26: Hoare triple {55793#false} assume !(0 == ~T8_E~0); {55793#false} is VALID [2022-02-21 04:24:38,445 INFO L290 TraceCheckUtils]: 27: Hoare triple {55793#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {55793#false} is VALID [2022-02-21 04:24:38,445 INFO L290 TraceCheckUtils]: 28: Hoare triple {55793#false} assume !(0 == ~T10_E~0); {55793#false} is VALID [2022-02-21 04:24:38,445 INFO L290 TraceCheckUtils]: 29: Hoare triple {55793#false} assume !(0 == ~T11_E~0); {55793#false} is VALID [2022-02-21 04:24:38,445 INFO L290 TraceCheckUtils]: 30: Hoare triple {55793#false} assume !(0 == ~T12_E~0); {55793#false} is VALID [2022-02-21 04:24:38,445 INFO L290 TraceCheckUtils]: 31: Hoare triple {55793#false} assume !(0 == ~E_1~0); {55793#false} is VALID [2022-02-21 04:24:38,445 INFO L290 TraceCheckUtils]: 32: Hoare triple {55793#false} assume !(0 == ~E_2~0); {55793#false} is VALID [2022-02-21 04:24:38,445 INFO L290 TraceCheckUtils]: 33: Hoare triple {55793#false} assume !(0 == ~E_3~0); {55793#false} is VALID [2022-02-21 04:24:38,446 INFO L290 TraceCheckUtils]: 34: Hoare triple {55793#false} assume !(0 == ~E_4~0); {55793#false} is VALID [2022-02-21 04:24:38,446 INFO L290 TraceCheckUtils]: 35: Hoare triple {55793#false} assume 0 == ~E_5~0;~E_5~0 := 1; {55793#false} is VALID [2022-02-21 04:24:38,446 INFO L290 TraceCheckUtils]: 36: Hoare triple {55793#false} assume !(0 == ~E_6~0); {55793#false} is VALID [2022-02-21 04:24:38,446 INFO L290 TraceCheckUtils]: 37: Hoare triple {55793#false} assume !(0 == ~E_7~0); {55793#false} is VALID [2022-02-21 04:24:38,446 INFO L290 TraceCheckUtils]: 38: Hoare triple {55793#false} assume !(0 == ~E_8~0); {55793#false} is VALID [2022-02-21 04:24:38,446 INFO L290 TraceCheckUtils]: 39: Hoare triple {55793#false} assume !(0 == ~E_9~0); {55793#false} is VALID [2022-02-21 04:24:38,446 INFO L290 TraceCheckUtils]: 40: Hoare triple {55793#false} assume !(0 == ~E_10~0); {55793#false} is VALID [2022-02-21 04:24:38,447 INFO L290 TraceCheckUtils]: 41: Hoare triple {55793#false} assume !(0 == ~E_11~0); {55793#false} is VALID [2022-02-21 04:24:38,447 INFO L290 TraceCheckUtils]: 42: Hoare triple {55793#false} assume !(0 == ~E_12~0); {55793#false} is VALID [2022-02-21 04:24:38,447 INFO L290 TraceCheckUtils]: 43: Hoare triple {55793#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {55793#false} is VALID [2022-02-21 04:24:38,447 INFO L290 TraceCheckUtils]: 44: Hoare triple {55793#false} assume 1 == ~m_pc~0; {55793#false} is VALID [2022-02-21 04:24:38,447 INFO L290 TraceCheckUtils]: 45: Hoare triple {55793#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {55793#false} is VALID [2022-02-21 04:24:38,447 INFO L290 TraceCheckUtils]: 46: Hoare triple {55793#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {55793#false} is VALID [2022-02-21 04:24:38,447 INFO L290 TraceCheckUtils]: 47: Hoare triple {55793#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {55793#false} is VALID [2022-02-21 04:24:38,447 INFO L290 TraceCheckUtils]: 48: Hoare triple {55793#false} assume !(0 != activate_threads_~tmp~1#1); {55793#false} is VALID [2022-02-21 04:24:38,448 INFO L290 TraceCheckUtils]: 49: Hoare triple {55793#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {55793#false} is VALID [2022-02-21 04:24:38,448 INFO L290 TraceCheckUtils]: 50: Hoare triple {55793#false} assume 1 == ~t1_pc~0; {55793#false} is VALID [2022-02-21 04:24:38,448 INFO L290 TraceCheckUtils]: 51: Hoare triple {55793#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {55793#false} is VALID [2022-02-21 04:24:38,448 INFO L290 TraceCheckUtils]: 52: Hoare triple {55793#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {55793#false} is VALID [2022-02-21 04:24:38,448 INFO L290 TraceCheckUtils]: 53: Hoare triple {55793#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {55793#false} is VALID [2022-02-21 04:24:38,448 INFO L290 TraceCheckUtils]: 54: Hoare triple {55793#false} assume !(0 != activate_threads_~tmp___0~0#1); {55793#false} is VALID [2022-02-21 04:24:38,448 INFO L290 TraceCheckUtils]: 55: Hoare triple {55793#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {55793#false} is VALID [2022-02-21 04:24:38,449 INFO L290 TraceCheckUtils]: 56: Hoare triple {55793#false} assume !(1 == ~t2_pc~0); {55793#false} is VALID [2022-02-21 04:24:38,449 INFO L290 TraceCheckUtils]: 57: Hoare triple {55793#false} is_transmit2_triggered_~__retres1~2#1 := 0; {55793#false} is VALID [2022-02-21 04:24:38,449 INFO L290 TraceCheckUtils]: 58: Hoare triple {55793#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {55793#false} is VALID [2022-02-21 04:24:38,449 INFO L290 TraceCheckUtils]: 59: Hoare triple {55793#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {55793#false} is VALID [2022-02-21 04:24:38,449 INFO L290 TraceCheckUtils]: 60: Hoare triple {55793#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {55793#false} is VALID [2022-02-21 04:24:38,449 INFO L290 TraceCheckUtils]: 61: Hoare triple {55793#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {55793#false} is VALID [2022-02-21 04:24:38,449 INFO L290 TraceCheckUtils]: 62: Hoare triple {55793#false} assume 1 == ~t3_pc~0; {55793#false} is VALID [2022-02-21 04:24:38,450 INFO L290 TraceCheckUtils]: 63: Hoare triple {55793#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {55793#false} is VALID [2022-02-21 04:24:38,450 INFO L290 TraceCheckUtils]: 64: Hoare triple {55793#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {55793#false} is VALID [2022-02-21 04:24:38,450 INFO L290 TraceCheckUtils]: 65: Hoare triple {55793#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {55793#false} is VALID [2022-02-21 04:24:38,450 INFO L290 TraceCheckUtils]: 66: Hoare triple {55793#false} assume !(0 != activate_threads_~tmp___2~0#1); {55793#false} is VALID [2022-02-21 04:24:38,450 INFO L290 TraceCheckUtils]: 67: Hoare triple {55793#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {55793#false} is VALID [2022-02-21 04:24:38,450 INFO L290 TraceCheckUtils]: 68: Hoare triple {55793#false} assume !(1 == ~t4_pc~0); {55793#false} is VALID [2022-02-21 04:24:38,450 INFO L290 TraceCheckUtils]: 69: Hoare triple {55793#false} is_transmit4_triggered_~__retres1~4#1 := 0; {55793#false} is VALID [2022-02-21 04:24:38,450 INFO L290 TraceCheckUtils]: 70: Hoare triple {55793#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {55793#false} is VALID [2022-02-21 04:24:38,451 INFO L290 TraceCheckUtils]: 71: Hoare triple {55793#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {55793#false} is VALID [2022-02-21 04:24:38,451 INFO L290 TraceCheckUtils]: 72: Hoare triple {55793#false} assume !(0 != activate_threads_~tmp___3~0#1); {55793#false} is VALID [2022-02-21 04:24:38,451 INFO L290 TraceCheckUtils]: 73: Hoare triple {55793#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {55793#false} is VALID [2022-02-21 04:24:38,451 INFO L290 TraceCheckUtils]: 74: Hoare triple {55793#false} assume 1 == ~t5_pc~0; {55793#false} is VALID [2022-02-21 04:24:38,451 INFO L290 TraceCheckUtils]: 75: Hoare triple {55793#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {55793#false} is VALID [2022-02-21 04:24:38,451 INFO L290 TraceCheckUtils]: 76: Hoare triple {55793#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {55793#false} is VALID [2022-02-21 04:24:38,451 INFO L290 TraceCheckUtils]: 77: Hoare triple {55793#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {55793#false} is VALID [2022-02-21 04:24:38,452 INFO L290 TraceCheckUtils]: 78: Hoare triple {55793#false} assume !(0 != activate_threads_~tmp___4~0#1); {55793#false} is VALID [2022-02-21 04:24:38,452 INFO L290 TraceCheckUtils]: 79: Hoare triple {55793#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {55793#false} is VALID [2022-02-21 04:24:38,452 INFO L290 TraceCheckUtils]: 80: Hoare triple {55793#false} assume !(1 == ~t6_pc~0); {55793#false} is VALID [2022-02-21 04:24:38,452 INFO L290 TraceCheckUtils]: 81: Hoare triple {55793#false} is_transmit6_triggered_~__retres1~6#1 := 0; {55793#false} is VALID [2022-02-21 04:24:38,452 INFO L290 TraceCheckUtils]: 82: Hoare triple {55793#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {55793#false} is VALID [2022-02-21 04:24:38,452 INFO L290 TraceCheckUtils]: 83: Hoare triple {55793#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {55793#false} is VALID [2022-02-21 04:24:38,452 INFO L290 TraceCheckUtils]: 84: Hoare triple {55793#false} assume !(0 != activate_threads_~tmp___5~0#1); {55793#false} is VALID [2022-02-21 04:24:38,453 INFO L290 TraceCheckUtils]: 85: Hoare triple {55793#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {55793#false} is VALID [2022-02-21 04:24:38,453 INFO L290 TraceCheckUtils]: 86: Hoare triple {55793#false} assume 1 == ~t7_pc~0; {55793#false} is VALID [2022-02-21 04:24:38,453 INFO L290 TraceCheckUtils]: 87: Hoare triple {55793#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {55793#false} is VALID [2022-02-21 04:24:38,453 INFO L290 TraceCheckUtils]: 88: Hoare triple {55793#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {55793#false} is VALID [2022-02-21 04:24:38,453 INFO L290 TraceCheckUtils]: 89: Hoare triple {55793#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {55793#false} is VALID [2022-02-21 04:24:38,453 INFO L290 TraceCheckUtils]: 90: Hoare triple {55793#false} assume !(0 != activate_threads_~tmp___6~0#1); {55793#false} is VALID [2022-02-21 04:24:38,453 INFO L290 TraceCheckUtils]: 91: Hoare triple {55793#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {55793#false} is VALID [2022-02-21 04:24:38,453 INFO L290 TraceCheckUtils]: 92: Hoare triple {55793#false} assume !(1 == ~t8_pc~0); {55793#false} is VALID [2022-02-21 04:24:38,454 INFO L290 TraceCheckUtils]: 93: Hoare triple {55793#false} is_transmit8_triggered_~__retres1~8#1 := 0; {55793#false} is VALID [2022-02-21 04:24:38,454 INFO L290 TraceCheckUtils]: 94: Hoare triple {55793#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {55793#false} is VALID [2022-02-21 04:24:38,454 INFO L290 TraceCheckUtils]: 95: Hoare triple {55793#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {55793#false} is VALID [2022-02-21 04:24:38,454 INFO L290 TraceCheckUtils]: 96: Hoare triple {55793#false} assume !(0 != activate_threads_~tmp___7~0#1); {55793#false} is VALID [2022-02-21 04:24:38,454 INFO L290 TraceCheckUtils]: 97: Hoare triple {55793#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {55793#false} is VALID [2022-02-21 04:24:38,454 INFO L290 TraceCheckUtils]: 98: Hoare triple {55793#false} assume 1 == ~t9_pc~0; {55793#false} is VALID [2022-02-21 04:24:38,454 INFO L290 TraceCheckUtils]: 99: Hoare triple {55793#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {55793#false} is VALID [2022-02-21 04:24:38,455 INFO L290 TraceCheckUtils]: 100: Hoare triple {55793#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {55793#false} is VALID [2022-02-21 04:24:38,455 INFO L290 TraceCheckUtils]: 101: Hoare triple {55793#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {55793#false} is VALID [2022-02-21 04:24:38,455 INFO L290 TraceCheckUtils]: 102: Hoare triple {55793#false} assume !(0 != activate_threads_~tmp___8~0#1); {55793#false} is VALID [2022-02-21 04:24:38,455 INFO L290 TraceCheckUtils]: 103: Hoare triple {55793#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {55793#false} is VALID [2022-02-21 04:24:38,455 INFO L290 TraceCheckUtils]: 104: Hoare triple {55793#false} assume 1 == ~t10_pc~0; {55793#false} is VALID [2022-02-21 04:24:38,455 INFO L290 TraceCheckUtils]: 105: Hoare triple {55793#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {55793#false} is VALID [2022-02-21 04:24:38,455 INFO L290 TraceCheckUtils]: 106: Hoare triple {55793#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {55793#false} is VALID [2022-02-21 04:24:38,456 INFO L290 TraceCheckUtils]: 107: Hoare triple {55793#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {55793#false} is VALID [2022-02-21 04:24:38,456 INFO L290 TraceCheckUtils]: 108: Hoare triple {55793#false} assume !(0 != activate_threads_~tmp___9~0#1); {55793#false} is VALID [2022-02-21 04:24:38,456 INFO L290 TraceCheckUtils]: 109: Hoare triple {55793#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {55793#false} is VALID [2022-02-21 04:24:38,456 INFO L290 TraceCheckUtils]: 110: Hoare triple {55793#false} assume !(1 == ~t11_pc~0); {55793#false} is VALID [2022-02-21 04:24:38,456 INFO L290 TraceCheckUtils]: 111: Hoare triple {55793#false} is_transmit11_triggered_~__retres1~11#1 := 0; {55793#false} is VALID [2022-02-21 04:24:38,456 INFO L290 TraceCheckUtils]: 112: Hoare triple {55793#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {55793#false} is VALID [2022-02-21 04:24:38,456 INFO L290 TraceCheckUtils]: 113: Hoare triple {55793#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {55793#false} is VALID [2022-02-21 04:24:38,456 INFO L290 TraceCheckUtils]: 114: Hoare triple {55793#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {55793#false} is VALID [2022-02-21 04:24:38,457 INFO L290 TraceCheckUtils]: 115: Hoare triple {55793#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {55793#false} is VALID [2022-02-21 04:24:38,457 INFO L290 TraceCheckUtils]: 116: Hoare triple {55793#false} assume 1 == ~t12_pc~0; {55793#false} is VALID [2022-02-21 04:24:38,457 INFO L290 TraceCheckUtils]: 117: Hoare triple {55793#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {55793#false} is VALID [2022-02-21 04:24:38,457 INFO L290 TraceCheckUtils]: 118: Hoare triple {55793#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {55793#false} is VALID [2022-02-21 04:24:38,457 INFO L290 TraceCheckUtils]: 119: Hoare triple {55793#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {55793#false} is VALID [2022-02-21 04:24:38,457 INFO L290 TraceCheckUtils]: 120: Hoare triple {55793#false} assume !(0 != activate_threads_~tmp___11~0#1); {55793#false} is VALID [2022-02-21 04:24:38,457 INFO L290 TraceCheckUtils]: 121: Hoare triple {55793#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {55793#false} is VALID [2022-02-21 04:24:38,458 INFO L290 TraceCheckUtils]: 122: Hoare triple {55793#false} assume !(1 == ~M_E~0); {55793#false} is VALID [2022-02-21 04:24:38,458 INFO L290 TraceCheckUtils]: 123: Hoare triple {55793#false} assume !(1 == ~T1_E~0); {55793#false} is VALID [2022-02-21 04:24:38,458 INFO L290 TraceCheckUtils]: 124: Hoare triple {55793#false} assume !(1 == ~T2_E~0); {55793#false} is VALID [2022-02-21 04:24:38,458 INFO L290 TraceCheckUtils]: 125: Hoare triple {55793#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {55793#false} is VALID [2022-02-21 04:24:38,458 INFO L290 TraceCheckUtils]: 126: Hoare triple {55793#false} assume !(1 == ~T4_E~0); {55793#false} is VALID [2022-02-21 04:24:38,458 INFO L290 TraceCheckUtils]: 127: Hoare triple {55793#false} assume !(1 == ~T5_E~0); {55793#false} is VALID [2022-02-21 04:24:38,458 INFO L290 TraceCheckUtils]: 128: Hoare triple {55793#false} assume !(1 == ~T6_E~0); {55793#false} is VALID [2022-02-21 04:24:38,458 INFO L290 TraceCheckUtils]: 129: Hoare triple {55793#false} assume !(1 == ~T7_E~0); {55793#false} is VALID [2022-02-21 04:24:38,459 INFO L290 TraceCheckUtils]: 130: Hoare triple {55793#false} assume !(1 == ~T8_E~0); {55793#false} is VALID [2022-02-21 04:24:38,459 INFO L290 TraceCheckUtils]: 131: Hoare triple {55793#false} assume !(1 == ~T9_E~0); {55793#false} is VALID [2022-02-21 04:24:38,459 INFO L290 TraceCheckUtils]: 132: Hoare triple {55793#false} assume !(1 == ~T10_E~0); {55793#false} is VALID [2022-02-21 04:24:38,459 INFO L290 TraceCheckUtils]: 133: Hoare triple {55793#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {55793#false} is VALID [2022-02-21 04:24:38,459 INFO L290 TraceCheckUtils]: 134: Hoare triple {55793#false} assume !(1 == ~T12_E~0); {55793#false} is VALID [2022-02-21 04:24:38,459 INFO L290 TraceCheckUtils]: 135: Hoare triple {55793#false} assume !(1 == ~E_1~0); {55793#false} is VALID [2022-02-21 04:24:38,459 INFO L290 TraceCheckUtils]: 136: Hoare triple {55793#false} assume !(1 == ~E_2~0); {55793#false} is VALID [2022-02-21 04:24:38,460 INFO L290 TraceCheckUtils]: 137: Hoare triple {55793#false} assume !(1 == ~E_3~0); {55793#false} is VALID [2022-02-21 04:24:38,460 INFO L290 TraceCheckUtils]: 138: Hoare triple {55793#false} assume !(1 == ~E_4~0); {55793#false} is VALID [2022-02-21 04:24:38,460 INFO L290 TraceCheckUtils]: 139: Hoare triple {55793#false} assume !(1 == ~E_5~0); {55793#false} is VALID [2022-02-21 04:24:38,460 INFO L290 TraceCheckUtils]: 140: Hoare triple {55793#false} assume !(1 == ~E_6~0); {55793#false} is VALID [2022-02-21 04:24:38,460 INFO L290 TraceCheckUtils]: 141: Hoare triple {55793#false} assume 1 == ~E_7~0;~E_7~0 := 2; {55793#false} is VALID [2022-02-21 04:24:38,460 INFO L290 TraceCheckUtils]: 142: Hoare triple {55793#false} assume !(1 == ~E_8~0); {55793#false} is VALID [2022-02-21 04:24:38,460 INFO L290 TraceCheckUtils]: 143: Hoare triple {55793#false} assume !(1 == ~E_9~0); {55793#false} is VALID [2022-02-21 04:24:38,461 INFO L290 TraceCheckUtils]: 144: Hoare triple {55793#false} assume !(1 == ~E_10~0); {55793#false} is VALID [2022-02-21 04:24:38,461 INFO L290 TraceCheckUtils]: 145: Hoare triple {55793#false} assume !(1 == ~E_11~0); {55793#false} is VALID [2022-02-21 04:24:38,461 INFO L290 TraceCheckUtils]: 146: Hoare triple {55793#false} assume !(1 == ~E_12~0); {55793#false} is VALID [2022-02-21 04:24:38,461 INFO L290 TraceCheckUtils]: 147: Hoare triple {55793#false} assume { :end_inline_reset_delta_events } true; {55793#false} is VALID [2022-02-21 04:24:38,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:38,462 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:38,462 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73310339] [2022-02-21 04:24:38,462 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [73310339] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:38,462 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:38,462 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:38,462 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744352039] [2022-02-21 04:24:38,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:38,463 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:38,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:38,463 INFO L85 PathProgramCache]: Analyzing trace with hash -212424000, now seen corresponding path program 1 times [2022-02-21 04:24:38,464 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:38,464 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1655506578] [2022-02-21 04:24:38,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:38,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:38,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:38,492 INFO L290 TraceCheckUtils]: 0: Hoare triple {55795#true} assume !false; {55795#true} is VALID [2022-02-21 04:24:38,493 INFO L290 TraceCheckUtils]: 1: Hoare triple {55795#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {55795#true} is VALID [2022-02-21 04:24:38,493 INFO L290 TraceCheckUtils]: 2: Hoare triple {55795#true} assume !false; {55795#true} is VALID [2022-02-21 04:24:38,493 INFO L290 TraceCheckUtils]: 3: Hoare triple {55795#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {55795#true} is VALID [2022-02-21 04:24:38,493 INFO L290 TraceCheckUtils]: 4: Hoare triple {55795#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {55795#true} is VALID [2022-02-21 04:24:38,493 INFO L290 TraceCheckUtils]: 5: Hoare triple {55795#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {55795#true} is VALID [2022-02-21 04:24:38,493 INFO L290 TraceCheckUtils]: 6: Hoare triple {55795#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {55795#true} is VALID [2022-02-21 04:24:38,493 INFO L290 TraceCheckUtils]: 7: Hoare triple {55795#true} assume !(0 != eval_~tmp~0#1); {55795#true} is VALID [2022-02-21 04:24:38,494 INFO L290 TraceCheckUtils]: 8: Hoare triple {55795#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {55795#true} is VALID [2022-02-21 04:24:38,494 INFO L290 TraceCheckUtils]: 9: Hoare triple {55795#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {55795#true} is VALID [2022-02-21 04:24:38,494 INFO L290 TraceCheckUtils]: 10: Hoare triple {55795#true} assume !(0 == ~M_E~0); {55795#true} is VALID [2022-02-21 04:24:38,494 INFO L290 TraceCheckUtils]: 11: Hoare triple {55795#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {55795#true} is VALID [2022-02-21 04:24:38,494 INFO L290 TraceCheckUtils]: 12: Hoare triple {55795#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,495 INFO L290 TraceCheckUtils]: 13: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,495 INFO L290 TraceCheckUtils]: 14: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,495 INFO L290 TraceCheckUtils]: 15: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,496 INFO L290 TraceCheckUtils]: 16: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,496 INFO L290 TraceCheckUtils]: 17: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,496 INFO L290 TraceCheckUtils]: 18: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,497 INFO L290 TraceCheckUtils]: 19: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,497 INFO L290 TraceCheckUtils]: 20: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,497 INFO L290 TraceCheckUtils]: 21: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,497 INFO L290 TraceCheckUtils]: 22: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,498 INFO L290 TraceCheckUtils]: 23: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,498 INFO L290 TraceCheckUtils]: 24: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,498 INFO L290 TraceCheckUtils]: 25: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,499 INFO L290 TraceCheckUtils]: 26: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,499 INFO L290 TraceCheckUtils]: 27: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,499 INFO L290 TraceCheckUtils]: 28: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,500 INFO L290 TraceCheckUtils]: 29: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,500 INFO L290 TraceCheckUtils]: 30: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,500 INFO L290 TraceCheckUtils]: 31: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,501 INFO L290 TraceCheckUtils]: 32: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,501 INFO L290 TraceCheckUtils]: 33: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,501 INFO L290 TraceCheckUtils]: 34: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,501 INFO L290 TraceCheckUtils]: 35: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,502 INFO L290 TraceCheckUtils]: 36: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,502 INFO L290 TraceCheckUtils]: 37: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,502 INFO L290 TraceCheckUtils]: 38: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,503 INFO L290 TraceCheckUtils]: 39: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,503 INFO L290 TraceCheckUtils]: 40: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,503 INFO L290 TraceCheckUtils]: 41: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,504 INFO L290 TraceCheckUtils]: 42: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,504 INFO L290 TraceCheckUtils]: 43: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,504 INFO L290 TraceCheckUtils]: 44: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,505 INFO L290 TraceCheckUtils]: 45: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,505 INFO L290 TraceCheckUtils]: 46: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,505 INFO L290 TraceCheckUtils]: 47: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,505 INFO L290 TraceCheckUtils]: 48: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,506 INFO L290 TraceCheckUtils]: 49: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,506 INFO L290 TraceCheckUtils]: 50: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,506 INFO L290 TraceCheckUtils]: 51: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,507 INFO L290 TraceCheckUtils]: 52: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,507 INFO L290 TraceCheckUtils]: 53: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,507 INFO L290 TraceCheckUtils]: 54: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,508 INFO L290 TraceCheckUtils]: 55: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,508 INFO L290 TraceCheckUtils]: 56: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,508 INFO L290 TraceCheckUtils]: 57: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,508 INFO L290 TraceCheckUtils]: 58: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,509 INFO L290 TraceCheckUtils]: 59: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,509 INFO L290 TraceCheckUtils]: 60: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,509 INFO L290 TraceCheckUtils]: 61: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,510 INFO L290 TraceCheckUtils]: 62: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,510 INFO L290 TraceCheckUtils]: 63: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,510 INFO L290 TraceCheckUtils]: 64: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,511 INFO L290 TraceCheckUtils]: 65: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,511 INFO L290 TraceCheckUtils]: 66: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,511 INFO L290 TraceCheckUtils]: 67: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,511 INFO L290 TraceCheckUtils]: 68: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,512 INFO L290 TraceCheckUtils]: 69: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,512 INFO L290 TraceCheckUtils]: 70: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,512 INFO L290 TraceCheckUtils]: 71: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,513 INFO L290 TraceCheckUtils]: 72: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,513 INFO L290 TraceCheckUtils]: 73: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,513 INFO L290 TraceCheckUtils]: 74: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,514 INFO L290 TraceCheckUtils]: 75: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,514 INFO L290 TraceCheckUtils]: 76: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,514 INFO L290 TraceCheckUtils]: 77: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,514 INFO L290 TraceCheckUtils]: 78: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,515 INFO L290 TraceCheckUtils]: 79: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,515 INFO L290 TraceCheckUtils]: 80: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,515 INFO L290 TraceCheckUtils]: 81: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,516 INFO L290 TraceCheckUtils]: 82: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,516 INFO L290 TraceCheckUtils]: 83: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,516 INFO L290 TraceCheckUtils]: 84: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,517 INFO L290 TraceCheckUtils]: 85: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,517 INFO L290 TraceCheckUtils]: 86: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,517 INFO L290 TraceCheckUtils]: 87: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,518 INFO L290 TraceCheckUtils]: 88: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,518 INFO L290 TraceCheckUtils]: 89: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,518 INFO L290 TraceCheckUtils]: 90: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,518 INFO L290 TraceCheckUtils]: 91: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,519 INFO L290 TraceCheckUtils]: 92: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,519 INFO L290 TraceCheckUtils]: 93: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,519 INFO L290 TraceCheckUtils]: 94: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,520 INFO L290 TraceCheckUtils]: 95: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,520 INFO L290 TraceCheckUtils]: 96: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t10_pc~0); {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,520 INFO L290 TraceCheckUtils]: 97: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,521 INFO L290 TraceCheckUtils]: 98: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,521 INFO L290 TraceCheckUtils]: 99: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,521 INFO L290 TraceCheckUtils]: 100: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,521 INFO L290 TraceCheckUtils]: 101: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,522 INFO L290 TraceCheckUtils]: 102: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,522 INFO L290 TraceCheckUtils]: 103: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,522 INFO L290 TraceCheckUtils]: 104: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,523 INFO L290 TraceCheckUtils]: 105: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,523 INFO L290 TraceCheckUtils]: 106: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,523 INFO L290 TraceCheckUtils]: 107: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,523 INFO L290 TraceCheckUtils]: 108: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t12_pc~0); {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,524 INFO L290 TraceCheckUtils]: 109: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,524 INFO L290 TraceCheckUtils]: 110: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,524 INFO L290 TraceCheckUtils]: 111: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,525 INFO L290 TraceCheckUtils]: 112: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,525 INFO L290 TraceCheckUtils]: 113: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,525 INFO L290 TraceCheckUtils]: 114: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,526 INFO L290 TraceCheckUtils]: 115: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {55797#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:38,526 INFO L290 TraceCheckUtils]: 116: Hoare triple {55797#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {55796#false} is VALID [2022-02-21 04:24:38,526 INFO L290 TraceCheckUtils]: 117: Hoare triple {55796#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,526 INFO L290 TraceCheckUtils]: 118: Hoare triple {55796#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,526 INFO L290 TraceCheckUtils]: 119: Hoare triple {55796#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,526 INFO L290 TraceCheckUtils]: 120: Hoare triple {55796#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,527 INFO L290 TraceCheckUtils]: 121: Hoare triple {55796#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,527 INFO L290 TraceCheckUtils]: 122: Hoare triple {55796#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,527 INFO L290 TraceCheckUtils]: 123: Hoare triple {55796#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,527 INFO L290 TraceCheckUtils]: 124: Hoare triple {55796#false} assume !(1 == ~T10_E~0); {55796#false} is VALID [2022-02-21 04:24:38,527 INFO L290 TraceCheckUtils]: 125: Hoare triple {55796#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,527 INFO L290 TraceCheckUtils]: 126: Hoare triple {55796#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,527 INFO L290 TraceCheckUtils]: 127: Hoare triple {55796#false} assume 1 == ~E_1~0;~E_1~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,528 INFO L290 TraceCheckUtils]: 128: Hoare triple {55796#false} assume 1 == ~E_2~0;~E_2~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,528 INFO L290 TraceCheckUtils]: 129: Hoare triple {55796#false} assume 1 == ~E_3~0;~E_3~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,528 INFO L290 TraceCheckUtils]: 130: Hoare triple {55796#false} assume 1 == ~E_4~0;~E_4~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,528 INFO L290 TraceCheckUtils]: 131: Hoare triple {55796#false} assume 1 == ~E_5~0;~E_5~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,528 INFO L290 TraceCheckUtils]: 132: Hoare triple {55796#false} assume !(1 == ~E_6~0); {55796#false} is VALID [2022-02-21 04:24:38,528 INFO L290 TraceCheckUtils]: 133: Hoare triple {55796#false} assume 1 == ~E_7~0;~E_7~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,528 INFO L290 TraceCheckUtils]: 134: Hoare triple {55796#false} assume 1 == ~E_8~0;~E_8~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,528 INFO L290 TraceCheckUtils]: 135: Hoare triple {55796#false} assume 1 == ~E_9~0;~E_9~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,529 INFO L290 TraceCheckUtils]: 136: Hoare triple {55796#false} assume 1 == ~E_10~0;~E_10~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,529 INFO L290 TraceCheckUtils]: 137: Hoare triple {55796#false} assume 1 == ~E_11~0;~E_11~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,529 INFO L290 TraceCheckUtils]: 138: Hoare triple {55796#false} assume 1 == ~E_12~0;~E_12~0 := 2; {55796#false} is VALID [2022-02-21 04:24:38,529 INFO L290 TraceCheckUtils]: 139: Hoare triple {55796#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {55796#false} is VALID [2022-02-21 04:24:38,529 INFO L290 TraceCheckUtils]: 140: Hoare triple {55796#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {55796#false} is VALID [2022-02-21 04:24:38,529 INFO L290 TraceCheckUtils]: 141: Hoare triple {55796#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {55796#false} is VALID [2022-02-21 04:24:38,529 INFO L290 TraceCheckUtils]: 142: Hoare triple {55796#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {55796#false} is VALID [2022-02-21 04:24:38,530 INFO L290 TraceCheckUtils]: 143: Hoare triple {55796#false} assume !(0 == start_simulation_~tmp~3#1); {55796#false} is VALID [2022-02-21 04:24:38,530 INFO L290 TraceCheckUtils]: 144: Hoare triple {55796#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {55796#false} is VALID [2022-02-21 04:24:38,530 INFO L290 TraceCheckUtils]: 145: Hoare triple {55796#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {55796#false} is VALID [2022-02-21 04:24:38,530 INFO L290 TraceCheckUtils]: 146: Hoare triple {55796#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {55796#false} is VALID [2022-02-21 04:24:38,530 INFO L290 TraceCheckUtils]: 147: Hoare triple {55796#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {55796#false} is VALID [2022-02-21 04:24:38,530 INFO L290 TraceCheckUtils]: 148: Hoare triple {55796#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {55796#false} is VALID [2022-02-21 04:24:38,530 INFO L290 TraceCheckUtils]: 149: Hoare triple {55796#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {55796#false} is VALID [2022-02-21 04:24:38,531 INFO L290 TraceCheckUtils]: 150: Hoare triple {55796#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {55796#false} is VALID [2022-02-21 04:24:38,531 INFO L290 TraceCheckUtils]: 151: Hoare triple {55796#false} assume !(0 != start_simulation_~tmp___0~1#1); {55796#false} is VALID [2022-02-21 04:24:38,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:38,532 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:38,532 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1655506578] [2022-02-21 04:24:38,532 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1655506578] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:38,532 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:38,532 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:38,532 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228346116] [2022-02-21 04:24:38,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:38,533 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:38,533 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:38,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:38,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:38,534 INFO L87 Difference]: Start difference. First operand 1688 states and 2497 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:39,800 INFO L93 Difference]: Finished difference Result 1688 states and 2496 transitions. [2022-02-21 04:24:39,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:39,801 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:39,897 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:39,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2496 transitions. [2022-02-21 04:24:39,996 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:40,057 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2496 transitions. [2022-02-21 04:24:40,057 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:40,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:40,058 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2496 transitions. [2022-02-21 04:24:40,059 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:40,059 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2022-02-21 04:24:40,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2496 transitions. [2022-02-21 04:24:40,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:40,074 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:40,084 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2496 transitions. Second operand has 1688 states, 1688 states have (on average 1.4786729857819905) internal successors, (2496), 1687 states have internal predecessors, (2496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,086 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2496 transitions. Second operand has 1688 states, 1688 states have (on average 1.4786729857819905) internal successors, (2496), 1687 states have internal predecessors, (2496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,087 INFO L87 Difference]: Start difference. First operand 1688 states and 2496 transitions. Second operand has 1688 states, 1688 states have (on average 1.4786729857819905) internal successors, (2496), 1687 states have internal predecessors, (2496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:40,152 INFO L93 Difference]: Finished difference Result 1688 states and 2496 transitions. [2022-02-21 04:24:40,152 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2496 transitions. [2022-02-21 04:24:40,154 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:40,154 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:40,156 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.4786729857819905) internal successors, (2496), 1687 states have internal predecessors, (2496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2496 transitions. [2022-02-21 04:24:40,157 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.4786729857819905) internal successors, (2496), 1687 states have internal predecessors, (2496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2496 transitions. [2022-02-21 04:24:40,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:40,221 INFO L93 Difference]: Finished difference Result 1688 states and 2496 transitions. [2022-02-21 04:24:40,221 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2496 transitions. [2022-02-21 04:24:40,222 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:40,222 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:40,222 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:40,222 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:40,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4786729857819905) internal successors, (2496), 1687 states have internal predecessors, (2496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2496 transitions. [2022-02-21 04:24:40,288 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2022-02-21 04:24:40,288 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2496 transitions. [2022-02-21 04:24:40,288 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:24:40,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2496 transitions. [2022-02-21 04:24:40,291 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:40,292 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:40,292 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:40,293 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:40,293 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:40,293 INFO L791 eck$LassoCheckResult]: Stem: 58289#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 58290#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 59143#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58635#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58442#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 58443#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58528#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58829#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58951#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58952#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 57740#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 57741#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 58889#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58335#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58336#L866-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 58242#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 58243#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 58632#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57984#L1174 assume !(0 == ~M_E~0); 57985#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 57836#L1179-1 assume !(0 == ~T2_E~0); 57738#L1184-1 assume !(0 == ~T3_E~0); 57739#L1189-1 assume !(0 == ~T4_E~0); 57777#L1194-1 assume !(0 == ~T5_E~0); 57877#L1199-1 assume !(0 == ~T6_E~0); 58772#L1204-1 assume !(0 == ~T7_E~0); 58691#L1209-1 assume !(0 == ~T8_E~0); 58692#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 59080#L1219-1 assume !(0 == ~T10_E~0); 59165#L1224-1 assume !(0 == ~T11_E~0); 58102#L1229-1 assume !(0 == ~T12_E~0); 57663#L1234-1 assume !(0 == ~E_1~0); 57664#L1239-1 assume !(0 == ~E_2~0); 57697#L1244-1 assume !(0 == ~E_3~0); 57698#L1249-1 assume !(0 == ~E_4~0); 58359#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 57593#L1259-1 assume !(0 == ~E_6~0); 57548#L1264-1 assume !(0 == ~E_7~0); 57549#L1269-1 assume !(0 == ~E_8~0); 59170#L1274-1 assume !(0 == ~E_9~0); 59105#L1279-1 assume !(0 == ~E_10~0); 57781#L1284-1 assume !(0 == ~E_11~0); 57782#L1289-1 assume !(0 == ~E_12~0); 58411#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58412#L566 assume 1 == ~m_pc~0; 57565#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 57566#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58720#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 58721#L1455 assume !(0 != activate_threads_~tmp~1#1); 58011#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58012#L585 assume 1 == ~t1_pc~0; 57660#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 57661#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58661#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58662#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 59130#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59128#L604 assume !(1 == ~t2_pc~0); 58740#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 58741#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58274#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58275#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58912#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58913#L623 assume 1 == ~t3_pc~0; 58189#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57529#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58339#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58340#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 58947#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57562#L642 assume !(1 == ~t4_pc~0); 57563#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 58028#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58029#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57634#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 57635#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58752#L661 assume 1 == ~t5_pc~0; 57799#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 57800#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57761#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57762#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 58781#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58782#L680 assume !(1 == ~t6_pc~0); 58222#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 58223#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58484#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58485#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 59013#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59126#L699 assume 1 == ~t7_pc~0; 58612#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58613#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57789#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 57790#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 58514#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58413#L718 assume !(1 == ~t8_pc~0); 58414#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 57775#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57776#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57817#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 57818#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57951#L737 assume 1 == ~t9_pc~0; 58816#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58086#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58687#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58688#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 58260#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58261#L756 assume 1 == ~t10_pc~0; 58840#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58506#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57492#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57493#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 58068#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58069#L775 assume !(1 == ~t11_pc~0); 58323#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 58324#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57945#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57709#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 57710#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57896#L794 assume 1 == ~t12_pc~0; 57737#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 57714#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58907#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 57862#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 57863#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58342#L1307 assume !(1 == ~M_E~0); 58343#L1307-2 assume !(1 == ~T1_E~0); 58454#L1312-1 assume !(1 == ~T2_E~0); 58373#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58374#L1322-1 assume !(1 == ~T4_E~0); 58077#L1327-1 assume !(1 == ~T5_E~0); 58078#L1332-1 assume !(1 == ~T6_E~0); 58616#L1337-1 assume !(1 == ~T7_E~0); 58578#L1342-1 assume !(1 == ~T8_E~0); 58579#L1347-1 assume !(1 == ~T9_E~0); 58976#L1352-1 assume !(1 == ~T10_E~0); 58849#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58240#L1362-1 assume !(1 == ~T12_E~0); 58241#L1367-1 assume !(1 == ~E_1~0); 57878#L1372-1 assume !(1 == ~E_2~0); 57879#L1377-1 assume !(1 == ~E_3~0); 58172#L1382-1 assume !(1 == ~E_4~0); 58173#L1387-1 assume !(1 == ~E_5~0); 58742#L1392-1 assume !(1 == ~E_6~0); 58192#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 58193#L1402-1 assume !(1 == ~E_8~0); 57889#L1407-1 assume !(1 == ~E_9~0); 57890#L1412-1 assume !(1 == ~E_10~0); 58905#L1417-1 assume !(1 == ~E_11~0); 58906#L1422-1 assume !(1 == ~E_12~0); 59124#L1427-1 assume { :end_inline_reset_delta_events } true; 57693#L1768-2 [2022-02-21 04:24:40,293 INFO L793 eck$LassoCheckResult]: Loop: 57693#L1768-2 assume !false; 57694#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 58432#L1149 assume !false; 58804#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 58957#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 58083#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 57989#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57990#L976 assume !(0 != eval_~tmp~0#1); 59123#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59133#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58924#L1174-3 assume !(0 == ~M_E~0); 58917#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 58666#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58667#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58851#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58501#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57851#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 57852#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58093#L1209-3 assume !(0 == ~T8_E~0); 57513#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 57514#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58272#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 58273#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 58291#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57701#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57702#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 58145#L1249-3 assume !(0 == ~E_4~0); 58604#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 59076#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 58718#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57707#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57708#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 59103#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 58270#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 58271#L1289-3 assume !(0 == ~E_12~0); 58259#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57935#L566-39 assume 1 == ~m_pc~0; 57936#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58538#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58250#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 58251#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58793#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58794#L585-39 assume !(1 == ~t1_pc~0); 57943#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 57944#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58019#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58020#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58826#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58519#L604-39 assume 1 == ~t2_pc~0; 58520#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 58151#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58152#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58569#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58570#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58134#L623-39 assume 1 == ~t3_pc~0; 57532#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57534#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58810#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57986#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57987#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58758#L642-39 assume 1 == ~t4_pc~0; 58331#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58332#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57858#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57859#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58956#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57909#L661-39 assume !(1 == ~t5_pc~0); 57538#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 57539#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58899#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58900#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58813#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58814#L680-39 assume 1 == ~t6_pc~0; 57602#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 57603#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58743#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58066#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58067#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59081#L699-39 assume 1 == ~t7_pc~0; 58503#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 58225#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58226#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58909#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 59030#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59028#L718-39 assume 1 == ~t8_pc~0; 58418#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58419#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58350#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58351#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 58653#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58622#L737-39 assume 1 == ~t9_pc~0; 58049#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58050#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58337#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59104#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59005#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58948#L756-39 assume 1 == ~t10_pc~0; 58949#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58430#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58174#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58175#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58307#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 57647#L775-39 assume 1 == ~t11_pc~0; 57648#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 58300#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58301#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59163#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58711#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58358#L794-39 assume 1 == ~t12_pc~0; 58052#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58044#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58864#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58765#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 57589#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57590#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 59057#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59058#L1312-3 assume !(1 == ~T2_E~0); 59169#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58783#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58784#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57728#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57699#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57700#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 58446#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 58571#L1352-3 assume !(1 == ~T10_E~0); 58572#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59011#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59162#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59153#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57526#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57527#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58158#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58159#L1392-3 assume !(1 == ~E_6~0); 58874#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59120#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 58537#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 57813#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 57814#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58462#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58463#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 57823#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 57824#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 58690#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 58542#L1787 assume !(0 == start_simulation_~tmp~3#1); 58543#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 59066#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 57794#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 58589#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 58590#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 58141#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 58142#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 58143#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 57693#L1768-2 [2022-02-21 04:24:40,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:40,294 INFO L85 PathProgramCache]: Analyzing trace with hash 1961430033, now seen corresponding path program 1 times [2022-02-21 04:24:40,294 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:40,294 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614240679] [2022-02-21 04:24:40,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:40,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:40,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:40,313 INFO L290 TraceCheckUtils]: 0: Hoare triple {62553#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {62553#true} is VALID [2022-02-21 04:24:40,314 INFO L290 TraceCheckUtils]: 1: Hoare triple {62553#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,314 INFO L290 TraceCheckUtils]: 2: Hoare triple {62555#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,314 INFO L290 TraceCheckUtils]: 3: Hoare triple {62555#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,314 INFO L290 TraceCheckUtils]: 4: Hoare triple {62555#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,315 INFO L290 TraceCheckUtils]: 5: Hoare triple {62555#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,315 INFO L290 TraceCheckUtils]: 6: Hoare triple {62555#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,315 INFO L290 TraceCheckUtils]: 7: Hoare triple {62555#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,316 INFO L290 TraceCheckUtils]: 8: Hoare triple {62555#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,316 INFO L290 TraceCheckUtils]: 9: Hoare triple {62555#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,316 INFO L290 TraceCheckUtils]: 10: Hoare triple {62555#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,316 INFO L290 TraceCheckUtils]: 11: Hoare triple {62555#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,317 INFO L290 TraceCheckUtils]: 12: Hoare triple {62555#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,317 INFO L290 TraceCheckUtils]: 13: Hoare triple {62555#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {62555#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:40,317 INFO L290 TraceCheckUtils]: 14: Hoare triple {62555#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {62554#false} is VALID [2022-02-21 04:24:40,317 INFO L290 TraceCheckUtils]: 15: Hoare triple {62554#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {62554#false} is VALID [2022-02-21 04:24:40,317 INFO L290 TraceCheckUtils]: 16: Hoare triple {62554#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {62554#false} is VALID [2022-02-21 04:24:40,318 INFO L290 TraceCheckUtils]: 17: Hoare triple {62554#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {62554#false} is VALID [2022-02-21 04:24:40,318 INFO L290 TraceCheckUtils]: 18: Hoare triple {62554#false} assume !(0 == ~M_E~0); {62554#false} is VALID [2022-02-21 04:24:40,318 INFO L290 TraceCheckUtils]: 19: Hoare triple {62554#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {62554#false} is VALID [2022-02-21 04:24:40,318 INFO L290 TraceCheckUtils]: 20: Hoare triple {62554#false} assume !(0 == ~T2_E~0); {62554#false} is VALID [2022-02-21 04:24:40,318 INFO L290 TraceCheckUtils]: 21: Hoare triple {62554#false} assume !(0 == ~T3_E~0); {62554#false} is VALID [2022-02-21 04:24:40,318 INFO L290 TraceCheckUtils]: 22: Hoare triple {62554#false} assume !(0 == ~T4_E~0); {62554#false} is VALID [2022-02-21 04:24:40,318 INFO L290 TraceCheckUtils]: 23: Hoare triple {62554#false} assume !(0 == ~T5_E~0); {62554#false} is VALID [2022-02-21 04:24:40,318 INFO L290 TraceCheckUtils]: 24: Hoare triple {62554#false} assume !(0 == ~T6_E~0); {62554#false} is VALID [2022-02-21 04:24:40,319 INFO L290 TraceCheckUtils]: 25: Hoare triple {62554#false} assume !(0 == ~T7_E~0); {62554#false} is VALID [2022-02-21 04:24:40,319 INFO L290 TraceCheckUtils]: 26: Hoare triple {62554#false} assume !(0 == ~T8_E~0); {62554#false} is VALID [2022-02-21 04:24:40,319 INFO L290 TraceCheckUtils]: 27: Hoare triple {62554#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {62554#false} is VALID [2022-02-21 04:24:40,319 INFO L290 TraceCheckUtils]: 28: Hoare triple {62554#false} assume !(0 == ~T10_E~0); {62554#false} is VALID [2022-02-21 04:24:40,319 INFO L290 TraceCheckUtils]: 29: Hoare triple {62554#false} assume !(0 == ~T11_E~0); {62554#false} is VALID [2022-02-21 04:24:40,319 INFO L290 TraceCheckUtils]: 30: Hoare triple {62554#false} assume !(0 == ~T12_E~0); {62554#false} is VALID [2022-02-21 04:24:40,319 INFO L290 TraceCheckUtils]: 31: Hoare triple {62554#false} assume !(0 == ~E_1~0); {62554#false} is VALID [2022-02-21 04:24:40,319 INFO L290 TraceCheckUtils]: 32: Hoare triple {62554#false} assume !(0 == ~E_2~0); {62554#false} is VALID [2022-02-21 04:24:40,319 INFO L290 TraceCheckUtils]: 33: Hoare triple {62554#false} assume !(0 == ~E_3~0); {62554#false} is VALID [2022-02-21 04:24:40,320 INFO L290 TraceCheckUtils]: 34: Hoare triple {62554#false} assume !(0 == ~E_4~0); {62554#false} is VALID [2022-02-21 04:24:40,320 INFO L290 TraceCheckUtils]: 35: Hoare triple {62554#false} assume 0 == ~E_5~0;~E_5~0 := 1; {62554#false} is VALID [2022-02-21 04:24:40,320 INFO L290 TraceCheckUtils]: 36: Hoare triple {62554#false} assume !(0 == ~E_6~0); {62554#false} is VALID [2022-02-21 04:24:40,320 INFO L290 TraceCheckUtils]: 37: Hoare triple {62554#false} assume !(0 == ~E_7~0); {62554#false} is VALID [2022-02-21 04:24:40,320 INFO L290 TraceCheckUtils]: 38: Hoare triple {62554#false} assume !(0 == ~E_8~0); {62554#false} is VALID [2022-02-21 04:24:40,320 INFO L290 TraceCheckUtils]: 39: Hoare triple {62554#false} assume !(0 == ~E_9~0); {62554#false} is VALID [2022-02-21 04:24:40,320 INFO L290 TraceCheckUtils]: 40: Hoare triple {62554#false} assume !(0 == ~E_10~0); {62554#false} is VALID [2022-02-21 04:24:40,320 INFO L290 TraceCheckUtils]: 41: Hoare triple {62554#false} assume !(0 == ~E_11~0); {62554#false} is VALID [2022-02-21 04:24:40,320 INFO L290 TraceCheckUtils]: 42: Hoare triple {62554#false} assume !(0 == ~E_12~0); {62554#false} is VALID [2022-02-21 04:24:40,321 INFO L290 TraceCheckUtils]: 43: Hoare triple {62554#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {62554#false} is VALID [2022-02-21 04:24:40,321 INFO L290 TraceCheckUtils]: 44: Hoare triple {62554#false} assume 1 == ~m_pc~0; {62554#false} is VALID [2022-02-21 04:24:40,321 INFO L290 TraceCheckUtils]: 45: Hoare triple {62554#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {62554#false} is VALID [2022-02-21 04:24:40,321 INFO L290 TraceCheckUtils]: 46: Hoare triple {62554#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {62554#false} is VALID [2022-02-21 04:24:40,321 INFO L290 TraceCheckUtils]: 47: Hoare triple {62554#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {62554#false} is VALID [2022-02-21 04:24:40,321 INFO L290 TraceCheckUtils]: 48: Hoare triple {62554#false} assume !(0 != activate_threads_~tmp~1#1); {62554#false} is VALID [2022-02-21 04:24:40,321 INFO L290 TraceCheckUtils]: 49: Hoare triple {62554#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {62554#false} is VALID [2022-02-21 04:24:40,321 INFO L290 TraceCheckUtils]: 50: Hoare triple {62554#false} assume 1 == ~t1_pc~0; {62554#false} is VALID [2022-02-21 04:24:40,321 INFO L290 TraceCheckUtils]: 51: Hoare triple {62554#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {62554#false} is VALID [2022-02-21 04:24:40,322 INFO L290 TraceCheckUtils]: 52: Hoare triple {62554#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {62554#false} is VALID [2022-02-21 04:24:40,322 INFO L290 TraceCheckUtils]: 53: Hoare triple {62554#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {62554#false} is VALID [2022-02-21 04:24:40,322 INFO L290 TraceCheckUtils]: 54: Hoare triple {62554#false} assume !(0 != activate_threads_~tmp___0~0#1); {62554#false} is VALID [2022-02-21 04:24:40,322 INFO L290 TraceCheckUtils]: 55: Hoare triple {62554#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {62554#false} is VALID [2022-02-21 04:24:40,322 INFO L290 TraceCheckUtils]: 56: Hoare triple {62554#false} assume !(1 == ~t2_pc~0); {62554#false} is VALID [2022-02-21 04:24:40,322 INFO L290 TraceCheckUtils]: 57: Hoare triple {62554#false} is_transmit2_triggered_~__retres1~2#1 := 0; {62554#false} is VALID [2022-02-21 04:24:40,322 INFO L290 TraceCheckUtils]: 58: Hoare triple {62554#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {62554#false} is VALID [2022-02-21 04:24:40,322 INFO L290 TraceCheckUtils]: 59: Hoare triple {62554#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {62554#false} is VALID [2022-02-21 04:24:40,322 INFO L290 TraceCheckUtils]: 60: Hoare triple {62554#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {62554#false} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 61: Hoare triple {62554#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {62554#false} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 62: Hoare triple {62554#false} assume 1 == ~t3_pc~0; {62554#false} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 63: Hoare triple {62554#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {62554#false} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 64: Hoare triple {62554#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {62554#false} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 65: Hoare triple {62554#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {62554#false} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 66: Hoare triple {62554#false} assume !(0 != activate_threads_~tmp___2~0#1); {62554#false} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 67: Hoare triple {62554#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {62554#false} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 68: Hoare triple {62554#false} assume !(1 == ~t4_pc~0); {62554#false} is VALID [2022-02-21 04:24:40,323 INFO L290 TraceCheckUtils]: 69: Hoare triple {62554#false} is_transmit4_triggered_~__retres1~4#1 := 0; {62554#false} is VALID [2022-02-21 04:24:40,324 INFO L290 TraceCheckUtils]: 70: Hoare triple {62554#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {62554#false} is VALID [2022-02-21 04:24:40,324 INFO L290 TraceCheckUtils]: 71: Hoare triple {62554#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {62554#false} is VALID [2022-02-21 04:24:40,324 INFO L290 TraceCheckUtils]: 72: Hoare triple {62554#false} assume !(0 != activate_threads_~tmp___3~0#1); {62554#false} is VALID [2022-02-21 04:24:40,324 INFO L290 TraceCheckUtils]: 73: Hoare triple {62554#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {62554#false} is VALID [2022-02-21 04:24:40,324 INFO L290 TraceCheckUtils]: 74: Hoare triple {62554#false} assume 1 == ~t5_pc~0; {62554#false} is VALID [2022-02-21 04:24:40,324 INFO L290 TraceCheckUtils]: 75: Hoare triple {62554#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {62554#false} is VALID [2022-02-21 04:24:40,324 INFO L290 TraceCheckUtils]: 76: Hoare triple {62554#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {62554#false} is VALID [2022-02-21 04:24:40,324 INFO L290 TraceCheckUtils]: 77: Hoare triple {62554#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {62554#false} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 78: Hoare triple {62554#false} assume !(0 != activate_threads_~tmp___4~0#1); {62554#false} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 79: Hoare triple {62554#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {62554#false} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 80: Hoare triple {62554#false} assume !(1 == ~t6_pc~0); {62554#false} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 81: Hoare triple {62554#false} is_transmit6_triggered_~__retres1~6#1 := 0; {62554#false} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 82: Hoare triple {62554#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {62554#false} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 83: Hoare triple {62554#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {62554#false} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 84: Hoare triple {62554#false} assume !(0 != activate_threads_~tmp___5~0#1); {62554#false} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 85: Hoare triple {62554#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {62554#false} is VALID [2022-02-21 04:24:40,325 INFO L290 TraceCheckUtils]: 86: Hoare triple {62554#false} assume 1 == ~t7_pc~0; {62554#false} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 87: Hoare triple {62554#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {62554#false} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 88: Hoare triple {62554#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {62554#false} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 89: Hoare triple {62554#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {62554#false} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 90: Hoare triple {62554#false} assume !(0 != activate_threads_~tmp___6~0#1); {62554#false} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 91: Hoare triple {62554#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {62554#false} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 92: Hoare triple {62554#false} assume !(1 == ~t8_pc~0); {62554#false} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 93: Hoare triple {62554#false} is_transmit8_triggered_~__retres1~8#1 := 0; {62554#false} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 94: Hoare triple {62554#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {62554#false} is VALID [2022-02-21 04:24:40,326 INFO L290 TraceCheckUtils]: 95: Hoare triple {62554#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {62554#false} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 96: Hoare triple {62554#false} assume !(0 != activate_threads_~tmp___7~0#1); {62554#false} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 97: Hoare triple {62554#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {62554#false} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 98: Hoare triple {62554#false} assume 1 == ~t9_pc~0; {62554#false} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 99: Hoare triple {62554#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {62554#false} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 100: Hoare triple {62554#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {62554#false} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 101: Hoare triple {62554#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {62554#false} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 102: Hoare triple {62554#false} assume !(0 != activate_threads_~tmp___8~0#1); {62554#false} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 103: Hoare triple {62554#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {62554#false} is VALID [2022-02-21 04:24:40,327 INFO L290 TraceCheckUtils]: 104: Hoare triple {62554#false} assume 1 == ~t10_pc~0; {62554#false} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 105: Hoare triple {62554#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {62554#false} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 106: Hoare triple {62554#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {62554#false} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 107: Hoare triple {62554#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {62554#false} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 108: Hoare triple {62554#false} assume !(0 != activate_threads_~tmp___9~0#1); {62554#false} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 109: Hoare triple {62554#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {62554#false} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 110: Hoare triple {62554#false} assume !(1 == ~t11_pc~0); {62554#false} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 111: Hoare triple {62554#false} is_transmit11_triggered_~__retres1~11#1 := 0; {62554#false} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 112: Hoare triple {62554#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {62554#false} is VALID [2022-02-21 04:24:40,328 INFO L290 TraceCheckUtils]: 113: Hoare triple {62554#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {62554#false} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 114: Hoare triple {62554#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {62554#false} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 115: Hoare triple {62554#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {62554#false} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 116: Hoare triple {62554#false} assume 1 == ~t12_pc~0; {62554#false} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 117: Hoare triple {62554#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {62554#false} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 118: Hoare triple {62554#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {62554#false} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 119: Hoare triple {62554#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {62554#false} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 120: Hoare triple {62554#false} assume !(0 != activate_threads_~tmp___11~0#1); {62554#false} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 121: Hoare triple {62554#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {62554#false} is VALID [2022-02-21 04:24:40,329 INFO L290 TraceCheckUtils]: 122: Hoare triple {62554#false} assume !(1 == ~M_E~0); {62554#false} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 123: Hoare triple {62554#false} assume !(1 == ~T1_E~0); {62554#false} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 124: Hoare triple {62554#false} assume !(1 == ~T2_E~0); {62554#false} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 125: Hoare triple {62554#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {62554#false} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 126: Hoare triple {62554#false} assume !(1 == ~T4_E~0); {62554#false} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 127: Hoare triple {62554#false} assume !(1 == ~T5_E~0); {62554#false} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 128: Hoare triple {62554#false} assume !(1 == ~T6_E~0); {62554#false} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 129: Hoare triple {62554#false} assume !(1 == ~T7_E~0); {62554#false} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 130: Hoare triple {62554#false} assume !(1 == ~T8_E~0); {62554#false} is VALID [2022-02-21 04:24:40,330 INFO L290 TraceCheckUtils]: 131: Hoare triple {62554#false} assume !(1 == ~T9_E~0); {62554#false} is VALID [2022-02-21 04:24:40,331 INFO L290 TraceCheckUtils]: 132: Hoare triple {62554#false} assume !(1 == ~T10_E~0); {62554#false} is VALID [2022-02-21 04:24:40,331 INFO L290 TraceCheckUtils]: 133: Hoare triple {62554#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {62554#false} is VALID [2022-02-21 04:24:40,331 INFO L290 TraceCheckUtils]: 134: Hoare triple {62554#false} assume !(1 == ~T12_E~0); {62554#false} is VALID [2022-02-21 04:24:40,331 INFO L290 TraceCheckUtils]: 135: Hoare triple {62554#false} assume !(1 == ~E_1~0); {62554#false} is VALID [2022-02-21 04:24:40,331 INFO L290 TraceCheckUtils]: 136: Hoare triple {62554#false} assume !(1 == ~E_2~0); {62554#false} is VALID [2022-02-21 04:24:40,331 INFO L290 TraceCheckUtils]: 137: Hoare triple {62554#false} assume !(1 == ~E_3~0); {62554#false} is VALID [2022-02-21 04:24:40,331 INFO L290 TraceCheckUtils]: 138: Hoare triple {62554#false} assume !(1 == ~E_4~0); {62554#false} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 139: Hoare triple {62554#false} assume !(1 == ~E_5~0); {62554#false} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 140: Hoare triple {62554#false} assume !(1 == ~E_6~0); {62554#false} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 141: Hoare triple {62554#false} assume 1 == ~E_7~0;~E_7~0 := 2; {62554#false} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 142: Hoare triple {62554#false} assume !(1 == ~E_8~0); {62554#false} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 143: Hoare triple {62554#false} assume !(1 == ~E_9~0); {62554#false} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 144: Hoare triple {62554#false} assume !(1 == ~E_10~0); {62554#false} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 145: Hoare triple {62554#false} assume !(1 == ~E_11~0); {62554#false} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 146: Hoare triple {62554#false} assume !(1 == ~E_12~0); {62554#false} is VALID [2022-02-21 04:24:40,332 INFO L290 TraceCheckUtils]: 147: Hoare triple {62554#false} assume { :end_inline_reset_delta_events } true; {62554#false} is VALID [2022-02-21 04:24:40,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:40,333 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:40,333 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614240679] [2022-02-21 04:24:40,333 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [614240679] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:40,333 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:40,333 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:40,334 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [735188980] [2022-02-21 04:24:40,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:40,334 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:40,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:40,334 INFO L85 PathProgramCache]: Analyzing trace with hash -2002386077, now seen corresponding path program 2 times [2022-02-21 04:24:40,335 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:40,335 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312251961] [2022-02-21 04:24:40,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:40,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:40,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:40,357 INFO L290 TraceCheckUtils]: 0: Hoare triple {62556#true} assume !false; {62556#true} is VALID [2022-02-21 04:24:40,357 INFO L290 TraceCheckUtils]: 1: Hoare triple {62556#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {62556#true} is VALID [2022-02-21 04:24:40,357 INFO L290 TraceCheckUtils]: 2: Hoare triple {62556#true} assume !false; {62556#true} is VALID [2022-02-21 04:24:40,357 INFO L290 TraceCheckUtils]: 3: Hoare triple {62556#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {62556#true} is VALID [2022-02-21 04:24:40,357 INFO L290 TraceCheckUtils]: 4: Hoare triple {62556#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {62556#true} is VALID [2022-02-21 04:24:40,357 INFO L290 TraceCheckUtils]: 5: Hoare triple {62556#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {62556#true} is VALID [2022-02-21 04:24:40,357 INFO L290 TraceCheckUtils]: 6: Hoare triple {62556#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {62556#true} is VALID [2022-02-21 04:24:40,357 INFO L290 TraceCheckUtils]: 7: Hoare triple {62556#true} assume !(0 != eval_~tmp~0#1); {62556#true} is VALID [2022-02-21 04:24:40,358 INFO L290 TraceCheckUtils]: 8: Hoare triple {62556#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {62556#true} is VALID [2022-02-21 04:24:40,358 INFO L290 TraceCheckUtils]: 9: Hoare triple {62556#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {62556#true} is VALID [2022-02-21 04:24:40,358 INFO L290 TraceCheckUtils]: 10: Hoare triple {62556#true} assume !(0 == ~M_E~0); {62556#true} is VALID [2022-02-21 04:24:40,358 INFO L290 TraceCheckUtils]: 11: Hoare triple {62556#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {62556#true} is VALID [2022-02-21 04:24:40,358 INFO L290 TraceCheckUtils]: 12: Hoare triple {62556#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,359 INFO L290 TraceCheckUtils]: 13: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,359 INFO L290 TraceCheckUtils]: 14: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,359 INFO L290 TraceCheckUtils]: 15: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,359 INFO L290 TraceCheckUtils]: 16: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,360 INFO L290 TraceCheckUtils]: 17: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,360 INFO L290 TraceCheckUtils]: 18: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,360 INFO L290 TraceCheckUtils]: 19: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,361 INFO L290 TraceCheckUtils]: 20: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,361 INFO L290 TraceCheckUtils]: 21: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,361 INFO L290 TraceCheckUtils]: 22: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,361 INFO L290 TraceCheckUtils]: 23: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,362 INFO L290 TraceCheckUtils]: 24: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,362 INFO L290 TraceCheckUtils]: 25: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,362 INFO L290 TraceCheckUtils]: 26: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,363 INFO L290 TraceCheckUtils]: 27: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,363 INFO L290 TraceCheckUtils]: 28: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,363 INFO L290 TraceCheckUtils]: 29: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,363 INFO L290 TraceCheckUtils]: 30: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,364 INFO L290 TraceCheckUtils]: 31: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,364 INFO L290 TraceCheckUtils]: 32: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,364 INFO L290 TraceCheckUtils]: 33: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,364 INFO L290 TraceCheckUtils]: 34: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,365 INFO L290 TraceCheckUtils]: 35: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,365 INFO L290 TraceCheckUtils]: 36: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,365 INFO L290 TraceCheckUtils]: 37: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,366 INFO L290 TraceCheckUtils]: 38: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,366 INFO L290 TraceCheckUtils]: 39: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,366 INFO L290 TraceCheckUtils]: 40: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,366 INFO L290 TraceCheckUtils]: 41: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,367 INFO L290 TraceCheckUtils]: 42: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,367 INFO L290 TraceCheckUtils]: 43: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,367 INFO L290 TraceCheckUtils]: 44: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,368 INFO L290 TraceCheckUtils]: 45: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,368 INFO L290 TraceCheckUtils]: 46: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,368 INFO L290 TraceCheckUtils]: 47: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,369 INFO L290 TraceCheckUtils]: 48: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,369 INFO L290 TraceCheckUtils]: 49: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,369 INFO L290 TraceCheckUtils]: 50: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,369 INFO L290 TraceCheckUtils]: 51: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,370 INFO L290 TraceCheckUtils]: 52: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,370 INFO L290 TraceCheckUtils]: 53: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,370 INFO L290 TraceCheckUtils]: 54: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,370 INFO L290 TraceCheckUtils]: 55: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,371 INFO L290 TraceCheckUtils]: 56: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,371 INFO L290 TraceCheckUtils]: 57: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,371 INFO L290 TraceCheckUtils]: 58: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,372 INFO L290 TraceCheckUtils]: 59: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,372 INFO L290 TraceCheckUtils]: 60: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,372 INFO L290 TraceCheckUtils]: 61: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,372 INFO L290 TraceCheckUtils]: 62: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,373 INFO L290 TraceCheckUtils]: 63: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,373 INFO L290 TraceCheckUtils]: 64: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,373 INFO L290 TraceCheckUtils]: 65: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,373 INFO L290 TraceCheckUtils]: 66: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,374 INFO L290 TraceCheckUtils]: 67: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,374 INFO L290 TraceCheckUtils]: 68: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,374 INFO L290 TraceCheckUtils]: 69: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,375 INFO L290 TraceCheckUtils]: 70: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,375 INFO L290 TraceCheckUtils]: 71: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,375 INFO L290 TraceCheckUtils]: 72: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,375 INFO L290 TraceCheckUtils]: 73: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,376 INFO L290 TraceCheckUtils]: 74: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,376 INFO L290 TraceCheckUtils]: 75: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,376 INFO L290 TraceCheckUtils]: 76: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,376 INFO L290 TraceCheckUtils]: 77: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,377 INFO L290 TraceCheckUtils]: 78: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,377 INFO L290 TraceCheckUtils]: 79: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,377 INFO L290 TraceCheckUtils]: 80: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,378 INFO L290 TraceCheckUtils]: 81: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,378 INFO L290 TraceCheckUtils]: 82: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,378 INFO L290 TraceCheckUtils]: 83: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,378 INFO L290 TraceCheckUtils]: 84: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,379 INFO L290 TraceCheckUtils]: 85: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,379 INFO L290 TraceCheckUtils]: 86: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,379 INFO L290 TraceCheckUtils]: 87: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,380 INFO L290 TraceCheckUtils]: 88: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,380 INFO L290 TraceCheckUtils]: 89: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,380 INFO L290 TraceCheckUtils]: 90: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,380 INFO L290 TraceCheckUtils]: 91: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,381 INFO L290 TraceCheckUtils]: 92: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,381 INFO L290 TraceCheckUtils]: 93: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,381 INFO L290 TraceCheckUtils]: 94: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,381 INFO L290 TraceCheckUtils]: 95: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,382 INFO L290 TraceCheckUtils]: 96: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,382 INFO L290 TraceCheckUtils]: 97: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,382 INFO L290 TraceCheckUtils]: 98: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,383 INFO L290 TraceCheckUtils]: 99: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,383 INFO L290 TraceCheckUtils]: 100: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,383 INFO L290 TraceCheckUtils]: 101: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,383 INFO L290 TraceCheckUtils]: 102: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,384 INFO L290 TraceCheckUtils]: 103: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,384 INFO L290 TraceCheckUtils]: 104: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,384 INFO L290 TraceCheckUtils]: 105: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,384 INFO L290 TraceCheckUtils]: 106: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,385 INFO L290 TraceCheckUtils]: 107: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,385 INFO L290 TraceCheckUtils]: 108: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t12_pc~0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,385 INFO L290 TraceCheckUtils]: 109: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,386 INFO L290 TraceCheckUtils]: 110: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,386 INFO L290 TraceCheckUtils]: 111: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,386 INFO L290 TraceCheckUtils]: 112: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,386 INFO L290 TraceCheckUtils]: 113: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,387 INFO L290 TraceCheckUtils]: 114: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,387 INFO L290 TraceCheckUtils]: 115: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {62558#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:40,387 INFO L290 TraceCheckUtils]: 116: Hoare triple {62558#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {62557#false} is VALID [2022-02-21 04:24:40,387 INFO L290 TraceCheckUtils]: 117: Hoare triple {62557#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,388 INFO L290 TraceCheckUtils]: 118: Hoare triple {62557#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,388 INFO L290 TraceCheckUtils]: 119: Hoare triple {62557#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,388 INFO L290 TraceCheckUtils]: 120: Hoare triple {62557#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,388 INFO L290 TraceCheckUtils]: 121: Hoare triple {62557#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,388 INFO L290 TraceCheckUtils]: 122: Hoare triple {62557#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,388 INFO L290 TraceCheckUtils]: 123: Hoare triple {62557#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,388 INFO L290 TraceCheckUtils]: 124: Hoare triple {62557#false} assume !(1 == ~T10_E~0); {62557#false} is VALID [2022-02-21 04:24:40,388 INFO L290 TraceCheckUtils]: 125: Hoare triple {62557#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,388 INFO L290 TraceCheckUtils]: 126: Hoare triple {62557#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,389 INFO L290 TraceCheckUtils]: 127: Hoare triple {62557#false} assume 1 == ~E_1~0;~E_1~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,389 INFO L290 TraceCheckUtils]: 128: Hoare triple {62557#false} assume 1 == ~E_2~0;~E_2~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,389 INFO L290 TraceCheckUtils]: 129: Hoare triple {62557#false} assume 1 == ~E_3~0;~E_3~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,389 INFO L290 TraceCheckUtils]: 130: Hoare triple {62557#false} assume 1 == ~E_4~0;~E_4~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,389 INFO L290 TraceCheckUtils]: 131: Hoare triple {62557#false} assume 1 == ~E_5~0;~E_5~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,389 INFO L290 TraceCheckUtils]: 132: Hoare triple {62557#false} assume !(1 == ~E_6~0); {62557#false} is VALID [2022-02-21 04:24:40,389 INFO L290 TraceCheckUtils]: 133: Hoare triple {62557#false} assume 1 == ~E_7~0;~E_7~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,389 INFO L290 TraceCheckUtils]: 134: Hoare triple {62557#false} assume 1 == ~E_8~0;~E_8~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,389 INFO L290 TraceCheckUtils]: 135: Hoare triple {62557#false} assume 1 == ~E_9~0;~E_9~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,390 INFO L290 TraceCheckUtils]: 136: Hoare triple {62557#false} assume 1 == ~E_10~0;~E_10~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,390 INFO L290 TraceCheckUtils]: 137: Hoare triple {62557#false} assume 1 == ~E_11~0;~E_11~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,390 INFO L290 TraceCheckUtils]: 138: Hoare triple {62557#false} assume 1 == ~E_12~0;~E_12~0 := 2; {62557#false} is VALID [2022-02-21 04:24:40,390 INFO L290 TraceCheckUtils]: 139: Hoare triple {62557#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {62557#false} is VALID [2022-02-21 04:24:40,390 INFO L290 TraceCheckUtils]: 140: Hoare triple {62557#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {62557#false} is VALID [2022-02-21 04:24:40,390 INFO L290 TraceCheckUtils]: 141: Hoare triple {62557#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {62557#false} is VALID [2022-02-21 04:24:40,390 INFO L290 TraceCheckUtils]: 142: Hoare triple {62557#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {62557#false} is VALID [2022-02-21 04:24:40,390 INFO L290 TraceCheckUtils]: 143: Hoare triple {62557#false} assume !(0 == start_simulation_~tmp~3#1); {62557#false} is VALID [2022-02-21 04:24:40,390 INFO L290 TraceCheckUtils]: 144: Hoare triple {62557#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {62557#false} is VALID [2022-02-21 04:24:40,391 INFO L290 TraceCheckUtils]: 145: Hoare triple {62557#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {62557#false} is VALID [2022-02-21 04:24:40,391 INFO L290 TraceCheckUtils]: 146: Hoare triple {62557#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {62557#false} is VALID [2022-02-21 04:24:40,391 INFO L290 TraceCheckUtils]: 147: Hoare triple {62557#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {62557#false} is VALID [2022-02-21 04:24:40,391 INFO L290 TraceCheckUtils]: 148: Hoare triple {62557#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {62557#false} is VALID [2022-02-21 04:24:40,391 INFO L290 TraceCheckUtils]: 149: Hoare triple {62557#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {62557#false} is VALID [2022-02-21 04:24:40,391 INFO L290 TraceCheckUtils]: 150: Hoare triple {62557#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {62557#false} is VALID [2022-02-21 04:24:40,391 INFO L290 TraceCheckUtils]: 151: Hoare triple {62557#false} assume !(0 != start_simulation_~tmp___0~1#1); {62557#false} is VALID [2022-02-21 04:24:40,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:40,392 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:40,392 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312251961] [2022-02-21 04:24:40,392 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312251961] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:40,392 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:40,392 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:40,392 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059583367] [2022-02-21 04:24:40,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:40,393 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:40,393 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:40,393 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:40,393 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:40,394 INFO L87 Difference]: Start difference. First operand 1688 states and 2496 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:41,740 INFO L93 Difference]: Finished difference Result 1688 states and 2495 transitions. [2022-02-21 04:24:41,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:41,741 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,836 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:41,837 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2495 transitions. [2022-02-21 04:24:41,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:42,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2495 transitions. [2022-02-21 04:24:42,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:42,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:42,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2495 transitions. [2022-02-21 04:24:42,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:42,029 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2022-02-21 04:24:42,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2495 transitions. [2022-02-21 04:24:42,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:42,042 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:42,043 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2495 transitions. Second operand has 1688 states, 1688 states have (on average 1.478080568720379) internal successors, (2495), 1687 states have internal predecessors, (2495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,044 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2495 transitions. Second operand has 1688 states, 1688 states have (on average 1.478080568720379) internal successors, (2495), 1687 states have internal predecessors, (2495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,045 INFO L87 Difference]: Start difference. First operand 1688 states and 2495 transitions. Second operand has 1688 states, 1688 states have (on average 1.478080568720379) internal successors, (2495), 1687 states have internal predecessors, (2495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:42,154 INFO L93 Difference]: Finished difference Result 1688 states and 2495 transitions. [2022-02-21 04:24:42,154 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2495 transitions. [2022-02-21 04:24:42,156 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:42,156 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:42,157 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.478080568720379) internal successors, (2495), 1687 states have internal predecessors, (2495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2495 transitions. [2022-02-21 04:24:42,158 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.478080568720379) internal successors, (2495), 1687 states have internal predecessors, (2495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2495 transitions. [2022-02-21 04:24:42,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:42,231 INFO L93 Difference]: Finished difference Result 1688 states and 2495 transitions. [2022-02-21 04:24:42,232 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2495 transitions. [2022-02-21 04:24:42,233 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:42,233 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:42,233 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:42,233 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:42,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.478080568720379) internal successors, (2495), 1687 states have internal predecessors, (2495), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2495 transitions. [2022-02-21 04:24:42,297 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2022-02-21 04:24:42,297 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2495 transitions. [2022-02-21 04:24:42,297 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:24:42,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2495 transitions. [2022-02-21 04:24:42,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:42,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:42,300 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:42,301 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:42,301 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:42,302 INFO L791 eck$LassoCheckResult]: Stem: 65050#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 65051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 65904#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65396#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65203#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 65204#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65289#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65590#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65712#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65713#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 64501#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64502#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65650#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65096#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 65097#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 65003#L871-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 65004#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 65392#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64745#L1174 assume !(0 == ~M_E~0); 64746#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64597#L1179-1 assume !(0 == ~T2_E~0); 64499#L1184-1 assume !(0 == ~T3_E~0); 64500#L1189-1 assume !(0 == ~T4_E~0); 64538#L1194-1 assume !(0 == ~T5_E~0); 64638#L1199-1 assume !(0 == ~T6_E~0); 65533#L1204-1 assume !(0 == ~T7_E~0); 65452#L1209-1 assume !(0 == ~T8_E~0); 65453#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 65841#L1219-1 assume !(0 == ~T10_E~0); 65926#L1224-1 assume !(0 == ~T11_E~0); 64863#L1229-1 assume !(0 == ~T12_E~0); 64424#L1234-1 assume !(0 == ~E_1~0); 64425#L1239-1 assume !(0 == ~E_2~0); 64458#L1244-1 assume !(0 == ~E_3~0); 64459#L1249-1 assume !(0 == ~E_4~0); 65120#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 64354#L1259-1 assume !(0 == ~E_6~0); 64309#L1264-1 assume !(0 == ~E_7~0); 64310#L1269-1 assume !(0 == ~E_8~0); 65931#L1274-1 assume !(0 == ~E_9~0); 65866#L1279-1 assume !(0 == ~E_10~0); 64542#L1284-1 assume !(0 == ~E_11~0); 64543#L1289-1 assume !(0 == ~E_12~0); 65172#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65173#L566 assume 1 == ~m_pc~0; 64326#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 64327#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65481#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 65482#L1455 assume !(0 != activate_threads_~tmp~1#1); 64772#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64773#L585 assume 1 == ~t1_pc~0; 64421#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64422#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65422#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65423#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 65891#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65889#L604 assume !(1 == ~t2_pc~0); 65501#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 65502#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65035#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65036#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65673#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65674#L623 assume 1 == ~t3_pc~0; 64950#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64290#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65100#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65101#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 65708#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64323#L642 assume !(1 == ~t4_pc~0); 64324#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 64789#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64790#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64395#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 64396#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65513#L661 assume 1 == ~t5_pc~0; 64560#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64561#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64522#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64523#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 65542#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65543#L680 assume !(1 == ~t6_pc~0); 64983#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 64984#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65245#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65246#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 65774#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65887#L699 assume 1 == ~t7_pc~0; 65373#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65374#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64550#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64551#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 65275#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65174#L718 assume !(1 == ~t8_pc~0); 65175#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 64536#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64537#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64578#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 64579#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64712#L737 assume 1 == ~t9_pc~0; 65577#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64847#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65448#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65449#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 65021#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65022#L756 assume 1 == ~t10_pc~0; 65601#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 65267#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64253#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64254#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 64829#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64830#L775 assume !(1 == ~t11_pc~0); 65084#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 65085#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64706#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64470#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 64471#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64657#L794 assume 1 == ~t12_pc~0; 64497#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 64475#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65668#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64623#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 64624#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65103#L1307 assume !(1 == ~M_E~0); 65104#L1307-2 assume !(1 == ~T1_E~0); 65215#L1312-1 assume !(1 == ~T2_E~0); 65134#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65135#L1322-1 assume !(1 == ~T4_E~0); 64838#L1327-1 assume !(1 == ~T5_E~0); 64839#L1332-1 assume !(1 == ~T6_E~0); 65377#L1337-1 assume !(1 == ~T7_E~0); 65339#L1342-1 assume !(1 == ~T8_E~0); 65340#L1347-1 assume !(1 == ~T9_E~0); 65737#L1352-1 assume !(1 == ~T10_E~0); 65610#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65001#L1362-1 assume !(1 == ~T12_E~0); 65002#L1367-1 assume !(1 == ~E_1~0); 64639#L1372-1 assume !(1 == ~E_2~0); 64640#L1377-1 assume !(1 == ~E_3~0); 64933#L1382-1 assume !(1 == ~E_4~0); 64934#L1387-1 assume !(1 == ~E_5~0); 65503#L1392-1 assume !(1 == ~E_6~0); 64953#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 64954#L1402-1 assume !(1 == ~E_8~0); 64650#L1407-1 assume !(1 == ~E_9~0); 64651#L1412-1 assume !(1 == ~E_10~0); 65666#L1417-1 assume !(1 == ~E_11~0); 65667#L1422-1 assume !(1 == ~E_12~0); 65885#L1427-1 assume { :end_inline_reset_delta_events } true; 64454#L1768-2 [2022-02-21 04:24:42,302 INFO L793 eck$LassoCheckResult]: Loop: 64454#L1768-2 assume !false; 64455#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65193#L1149 assume !false; 65565#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 65718#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64844#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64750#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 64751#L976 assume !(0 != eval_~tmp~0#1); 65884#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65894#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65685#L1174-3 assume !(0 == ~M_E~0); 65678#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65427#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65428#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65611#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65262#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 64612#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64613#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64854#L1209-3 assume !(0 == ~T8_E~0); 64274#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64275#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 65033#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 65034#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 65052#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64462#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64463#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64906#L1249-3 assume !(0 == ~E_4~0); 65365#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65837#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 65479#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64468#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 64469#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 65864#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 65031#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 65032#L1289-3 assume !(0 == ~E_12~0); 65020#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64696#L566-39 assume 1 == ~m_pc~0; 64697#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 65299#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65011#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 65012#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65554#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65555#L585-39 assume !(1 == ~t1_pc~0); 64704#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 64705#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64780#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64781#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65587#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65280#L604-39 assume 1 == ~t2_pc~0; 65281#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64912#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64913#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65330#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65331#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64895#L623-39 assume 1 == ~t3_pc~0; 64291#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64293#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65571#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64747#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64748#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65519#L642-39 assume 1 == ~t4_pc~0; 65090#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65091#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64619#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64620#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65717#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64668#L661-39 assume !(1 == ~t5_pc~0); 64299#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 64300#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65660#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65661#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65574#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65575#L680-39 assume 1 == ~t6_pc~0; 64361#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64362#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65504#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64827#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64828#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65842#L699-39 assume 1 == ~t7_pc~0; 65264#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64986#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64987#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65670#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 65791#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65789#L718-39 assume 1 == ~t8_pc~0; 65178#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 65179#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65111#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65112#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 65414#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65383#L737-39 assume 1 == ~t9_pc~0; 64808#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64809#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65098#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65865#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65766#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65709#L756-39 assume !(1 == ~t10_pc~0); 65190#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 65191#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64935#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64936#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65068#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64408#L775-39 assume 1 == ~t11_pc~0; 64409#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65061#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65062#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65924#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65472#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65119#L794-39 assume !(1 == ~t12_pc~0); 64804#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 64805#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65625#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65526#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64350#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64351#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 65818#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65819#L1312-3 assume !(1 == ~T2_E~0); 65930#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65544#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65545#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64489#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64460#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64461#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65207#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65332#L1352-3 assume !(1 == ~T10_E~0); 65333#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65772#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 65923#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65914#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 64287#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 64288#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64919#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 64920#L1392-3 assume !(1 == ~E_6~0); 65635#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 65881#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 65298#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 64574#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 64575#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 65223#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 65224#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64584#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64585#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 65451#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 65303#L1787 assume !(0 == start_simulation_~tmp~3#1); 65304#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 65827#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64555#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 65350#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 65351#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64902#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64903#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 64904#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 64454#L1768-2 [2022-02-21 04:24:42,302 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:42,303 INFO L85 PathProgramCache]: Analyzing trace with hash -716096813, now seen corresponding path program 1 times [2022-02-21 04:24:42,303 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:42,303 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584040023] [2022-02-21 04:24:42,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:42,303 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:42,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:42,327 INFO L290 TraceCheckUtils]: 0: Hoare triple {69314#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {69314#true} is VALID [2022-02-21 04:24:42,327 INFO L290 TraceCheckUtils]: 1: Hoare triple {69314#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,327 INFO L290 TraceCheckUtils]: 2: Hoare triple {69316#(= ~t11_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,328 INFO L290 TraceCheckUtils]: 3: Hoare triple {69316#(= ~t11_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,328 INFO L290 TraceCheckUtils]: 4: Hoare triple {69316#(= ~t11_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,328 INFO L290 TraceCheckUtils]: 5: Hoare triple {69316#(= ~t11_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,329 INFO L290 TraceCheckUtils]: 6: Hoare triple {69316#(= ~t11_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,329 INFO L290 TraceCheckUtils]: 7: Hoare triple {69316#(= ~t11_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,329 INFO L290 TraceCheckUtils]: 8: Hoare triple {69316#(= ~t11_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,329 INFO L290 TraceCheckUtils]: 9: Hoare triple {69316#(= ~t11_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,330 INFO L290 TraceCheckUtils]: 10: Hoare triple {69316#(= ~t11_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,330 INFO L290 TraceCheckUtils]: 11: Hoare triple {69316#(= ~t11_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,330 INFO L290 TraceCheckUtils]: 12: Hoare triple {69316#(= ~t11_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,330 INFO L290 TraceCheckUtils]: 13: Hoare triple {69316#(= ~t11_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,331 INFO L290 TraceCheckUtils]: 14: Hoare triple {69316#(= ~t11_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {69316#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:42,331 INFO L290 TraceCheckUtils]: 15: Hoare triple {69316#(= ~t11_i~0 1)} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {69315#false} is VALID [2022-02-21 04:24:42,331 INFO L290 TraceCheckUtils]: 16: Hoare triple {69315#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {69315#false} is VALID [2022-02-21 04:24:42,331 INFO L290 TraceCheckUtils]: 17: Hoare triple {69315#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {69315#false} is VALID [2022-02-21 04:24:42,331 INFO L290 TraceCheckUtils]: 18: Hoare triple {69315#false} assume !(0 == ~M_E~0); {69315#false} is VALID [2022-02-21 04:24:42,331 INFO L290 TraceCheckUtils]: 19: Hoare triple {69315#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {69315#false} is VALID [2022-02-21 04:24:42,332 INFO L290 TraceCheckUtils]: 20: Hoare triple {69315#false} assume !(0 == ~T2_E~0); {69315#false} is VALID [2022-02-21 04:24:42,332 INFO L290 TraceCheckUtils]: 21: Hoare triple {69315#false} assume !(0 == ~T3_E~0); {69315#false} is VALID [2022-02-21 04:24:42,332 INFO L290 TraceCheckUtils]: 22: Hoare triple {69315#false} assume !(0 == ~T4_E~0); {69315#false} is VALID [2022-02-21 04:24:42,332 INFO L290 TraceCheckUtils]: 23: Hoare triple {69315#false} assume !(0 == ~T5_E~0); {69315#false} is VALID [2022-02-21 04:24:42,332 INFO L290 TraceCheckUtils]: 24: Hoare triple {69315#false} assume !(0 == ~T6_E~0); {69315#false} is VALID [2022-02-21 04:24:42,332 INFO L290 TraceCheckUtils]: 25: Hoare triple {69315#false} assume !(0 == ~T7_E~0); {69315#false} is VALID [2022-02-21 04:24:42,332 INFO L290 TraceCheckUtils]: 26: Hoare triple {69315#false} assume !(0 == ~T8_E~0); {69315#false} is VALID [2022-02-21 04:24:42,332 INFO L290 TraceCheckUtils]: 27: Hoare triple {69315#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {69315#false} is VALID [2022-02-21 04:24:42,332 INFO L290 TraceCheckUtils]: 28: Hoare triple {69315#false} assume !(0 == ~T10_E~0); {69315#false} is VALID [2022-02-21 04:24:42,333 INFO L290 TraceCheckUtils]: 29: Hoare triple {69315#false} assume !(0 == ~T11_E~0); {69315#false} is VALID [2022-02-21 04:24:42,333 INFO L290 TraceCheckUtils]: 30: Hoare triple {69315#false} assume !(0 == ~T12_E~0); {69315#false} is VALID [2022-02-21 04:24:42,333 INFO L290 TraceCheckUtils]: 31: Hoare triple {69315#false} assume !(0 == ~E_1~0); {69315#false} is VALID [2022-02-21 04:24:42,333 INFO L290 TraceCheckUtils]: 32: Hoare triple {69315#false} assume !(0 == ~E_2~0); {69315#false} is VALID [2022-02-21 04:24:42,333 INFO L290 TraceCheckUtils]: 33: Hoare triple {69315#false} assume !(0 == ~E_3~0); {69315#false} is VALID [2022-02-21 04:24:42,333 INFO L290 TraceCheckUtils]: 34: Hoare triple {69315#false} assume !(0 == ~E_4~0); {69315#false} is VALID [2022-02-21 04:24:42,333 INFO L290 TraceCheckUtils]: 35: Hoare triple {69315#false} assume 0 == ~E_5~0;~E_5~0 := 1; {69315#false} is VALID [2022-02-21 04:24:42,333 INFO L290 TraceCheckUtils]: 36: Hoare triple {69315#false} assume !(0 == ~E_6~0); {69315#false} is VALID [2022-02-21 04:24:42,333 INFO L290 TraceCheckUtils]: 37: Hoare triple {69315#false} assume !(0 == ~E_7~0); {69315#false} is VALID [2022-02-21 04:24:42,334 INFO L290 TraceCheckUtils]: 38: Hoare triple {69315#false} assume !(0 == ~E_8~0); {69315#false} is VALID [2022-02-21 04:24:42,334 INFO L290 TraceCheckUtils]: 39: Hoare triple {69315#false} assume !(0 == ~E_9~0); {69315#false} is VALID [2022-02-21 04:24:42,334 INFO L290 TraceCheckUtils]: 40: Hoare triple {69315#false} assume !(0 == ~E_10~0); {69315#false} is VALID [2022-02-21 04:24:42,334 INFO L290 TraceCheckUtils]: 41: Hoare triple {69315#false} assume !(0 == ~E_11~0); {69315#false} is VALID [2022-02-21 04:24:42,334 INFO L290 TraceCheckUtils]: 42: Hoare triple {69315#false} assume !(0 == ~E_12~0); {69315#false} is VALID [2022-02-21 04:24:42,334 INFO L290 TraceCheckUtils]: 43: Hoare triple {69315#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {69315#false} is VALID [2022-02-21 04:24:42,334 INFO L290 TraceCheckUtils]: 44: Hoare triple {69315#false} assume 1 == ~m_pc~0; {69315#false} is VALID [2022-02-21 04:24:42,334 INFO L290 TraceCheckUtils]: 45: Hoare triple {69315#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {69315#false} is VALID [2022-02-21 04:24:42,334 INFO L290 TraceCheckUtils]: 46: Hoare triple {69315#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {69315#false} is VALID [2022-02-21 04:24:42,335 INFO L290 TraceCheckUtils]: 47: Hoare triple {69315#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {69315#false} is VALID [2022-02-21 04:24:42,335 INFO L290 TraceCheckUtils]: 48: Hoare triple {69315#false} assume !(0 != activate_threads_~tmp~1#1); {69315#false} is VALID [2022-02-21 04:24:42,335 INFO L290 TraceCheckUtils]: 49: Hoare triple {69315#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {69315#false} is VALID [2022-02-21 04:24:42,335 INFO L290 TraceCheckUtils]: 50: Hoare triple {69315#false} assume 1 == ~t1_pc~0; {69315#false} is VALID [2022-02-21 04:24:42,335 INFO L290 TraceCheckUtils]: 51: Hoare triple {69315#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {69315#false} is VALID [2022-02-21 04:24:42,335 INFO L290 TraceCheckUtils]: 52: Hoare triple {69315#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {69315#false} is VALID [2022-02-21 04:24:42,335 INFO L290 TraceCheckUtils]: 53: Hoare triple {69315#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {69315#false} is VALID [2022-02-21 04:24:42,335 INFO L290 TraceCheckUtils]: 54: Hoare triple {69315#false} assume !(0 != activate_threads_~tmp___0~0#1); {69315#false} is VALID [2022-02-21 04:24:42,335 INFO L290 TraceCheckUtils]: 55: Hoare triple {69315#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {69315#false} is VALID [2022-02-21 04:24:42,336 INFO L290 TraceCheckUtils]: 56: Hoare triple {69315#false} assume !(1 == ~t2_pc~0); {69315#false} is VALID [2022-02-21 04:24:42,336 INFO L290 TraceCheckUtils]: 57: Hoare triple {69315#false} is_transmit2_triggered_~__retres1~2#1 := 0; {69315#false} is VALID [2022-02-21 04:24:42,336 INFO L290 TraceCheckUtils]: 58: Hoare triple {69315#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {69315#false} is VALID [2022-02-21 04:24:42,336 INFO L290 TraceCheckUtils]: 59: Hoare triple {69315#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {69315#false} is VALID [2022-02-21 04:24:42,336 INFO L290 TraceCheckUtils]: 60: Hoare triple {69315#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {69315#false} is VALID [2022-02-21 04:24:42,336 INFO L290 TraceCheckUtils]: 61: Hoare triple {69315#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {69315#false} is VALID [2022-02-21 04:24:42,336 INFO L290 TraceCheckUtils]: 62: Hoare triple {69315#false} assume 1 == ~t3_pc~0; {69315#false} is VALID [2022-02-21 04:24:42,336 INFO L290 TraceCheckUtils]: 63: Hoare triple {69315#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {69315#false} is VALID [2022-02-21 04:24:42,336 INFO L290 TraceCheckUtils]: 64: Hoare triple {69315#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {69315#false} is VALID [2022-02-21 04:24:42,337 INFO L290 TraceCheckUtils]: 65: Hoare triple {69315#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {69315#false} is VALID [2022-02-21 04:24:42,337 INFO L290 TraceCheckUtils]: 66: Hoare triple {69315#false} assume !(0 != activate_threads_~tmp___2~0#1); {69315#false} is VALID [2022-02-21 04:24:42,337 INFO L290 TraceCheckUtils]: 67: Hoare triple {69315#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {69315#false} is VALID [2022-02-21 04:24:42,337 INFO L290 TraceCheckUtils]: 68: Hoare triple {69315#false} assume !(1 == ~t4_pc~0); {69315#false} is VALID [2022-02-21 04:24:42,337 INFO L290 TraceCheckUtils]: 69: Hoare triple {69315#false} is_transmit4_triggered_~__retres1~4#1 := 0; {69315#false} is VALID [2022-02-21 04:24:42,337 INFO L290 TraceCheckUtils]: 70: Hoare triple {69315#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {69315#false} is VALID [2022-02-21 04:24:42,337 INFO L290 TraceCheckUtils]: 71: Hoare triple {69315#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {69315#false} is VALID [2022-02-21 04:24:42,337 INFO L290 TraceCheckUtils]: 72: Hoare triple {69315#false} assume !(0 != activate_threads_~tmp___3~0#1); {69315#false} is VALID [2022-02-21 04:24:42,337 INFO L290 TraceCheckUtils]: 73: Hoare triple {69315#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {69315#false} is VALID [2022-02-21 04:24:42,338 INFO L290 TraceCheckUtils]: 74: Hoare triple {69315#false} assume 1 == ~t5_pc~0; {69315#false} is VALID [2022-02-21 04:24:42,338 INFO L290 TraceCheckUtils]: 75: Hoare triple {69315#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {69315#false} is VALID [2022-02-21 04:24:42,338 INFO L290 TraceCheckUtils]: 76: Hoare triple {69315#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {69315#false} is VALID [2022-02-21 04:24:42,338 INFO L290 TraceCheckUtils]: 77: Hoare triple {69315#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {69315#false} is VALID [2022-02-21 04:24:42,338 INFO L290 TraceCheckUtils]: 78: Hoare triple {69315#false} assume !(0 != activate_threads_~tmp___4~0#1); {69315#false} is VALID [2022-02-21 04:24:42,338 INFO L290 TraceCheckUtils]: 79: Hoare triple {69315#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {69315#false} is VALID [2022-02-21 04:24:42,338 INFO L290 TraceCheckUtils]: 80: Hoare triple {69315#false} assume !(1 == ~t6_pc~0); {69315#false} is VALID [2022-02-21 04:24:42,338 INFO L290 TraceCheckUtils]: 81: Hoare triple {69315#false} is_transmit6_triggered_~__retres1~6#1 := 0; {69315#false} is VALID [2022-02-21 04:24:42,338 INFO L290 TraceCheckUtils]: 82: Hoare triple {69315#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {69315#false} is VALID [2022-02-21 04:24:42,339 INFO L290 TraceCheckUtils]: 83: Hoare triple {69315#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {69315#false} is VALID [2022-02-21 04:24:42,339 INFO L290 TraceCheckUtils]: 84: Hoare triple {69315#false} assume !(0 != activate_threads_~tmp___5~0#1); {69315#false} is VALID [2022-02-21 04:24:42,339 INFO L290 TraceCheckUtils]: 85: Hoare triple {69315#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {69315#false} is VALID [2022-02-21 04:24:42,339 INFO L290 TraceCheckUtils]: 86: Hoare triple {69315#false} assume 1 == ~t7_pc~0; {69315#false} is VALID [2022-02-21 04:24:42,339 INFO L290 TraceCheckUtils]: 87: Hoare triple {69315#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {69315#false} is VALID [2022-02-21 04:24:42,339 INFO L290 TraceCheckUtils]: 88: Hoare triple {69315#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {69315#false} is VALID [2022-02-21 04:24:42,339 INFO L290 TraceCheckUtils]: 89: Hoare triple {69315#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {69315#false} is VALID [2022-02-21 04:24:42,339 INFO L290 TraceCheckUtils]: 90: Hoare triple {69315#false} assume !(0 != activate_threads_~tmp___6~0#1); {69315#false} is VALID [2022-02-21 04:24:42,339 INFO L290 TraceCheckUtils]: 91: Hoare triple {69315#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {69315#false} is VALID [2022-02-21 04:24:42,340 INFO L290 TraceCheckUtils]: 92: Hoare triple {69315#false} assume !(1 == ~t8_pc~0); {69315#false} is VALID [2022-02-21 04:24:42,340 INFO L290 TraceCheckUtils]: 93: Hoare triple {69315#false} is_transmit8_triggered_~__retres1~8#1 := 0; {69315#false} is VALID [2022-02-21 04:24:42,340 INFO L290 TraceCheckUtils]: 94: Hoare triple {69315#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {69315#false} is VALID [2022-02-21 04:24:42,340 INFO L290 TraceCheckUtils]: 95: Hoare triple {69315#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {69315#false} is VALID [2022-02-21 04:24:42,340 INFO L290 TraceCheckUtils]: 96: Hoare triple {69315#false} assume !(0 != activate_threads_~tmp___7~0#1); {69315#false} is VALID [2022-02-21 04:24:42,340 INFO L290 TraceCheckUtils]: 97: Hoare triple {69315#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {69315#false} is VALID [2022-02-21 04:24:42,340 INFO L290 TraceCheckUtils]: 98: Hoare triple {69315#false} assume 1 == ~t9_pc~0; {69315#false} is VALID [2022-02-21 04:24:42,340 INFO L290 TraceCheckUtils]: 99: Hoare triple {69315#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {69315#false} is VALID [2022-02-21 04:24:42,340 INFO L290 TraceCheckUtils]: 100: Hoare triple {69315#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {69315#false} is VALID [2022-02-21 04:24:42,341 INFO L290 TraceCheckUtils]: 101: Hoare triple {69315#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {69315#false} is VALID [2022-02-21 04:24:42,341 INFO L290 TraceCheckUtils]: 102: Hoare triple {69315#false} assume !(0 != activate_threads_~tmp___8~0#1); {69315#false} is VALID [2022-02-21 04:24:42,341 INFO L290 TraceCheckUtils]: 103: Hoare triple {69315#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {69315#false} is VALID [2022-02-21 04:24:42,341 INFO L290 TraceCheckUtils]: 104: Hoare triple {69315#false} assume 1 == ~t10_pc~0; {69315#false} is VALID [2022-02-21 04:24:42,341 INFO L290 TraceCheckUtils]: 105: Hoare triple {69315#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {69315#false} is VALID [2022-02-21 04:24:42,341 INFO L290 TraceCheckUtils]: 106: Hoare triple {69315#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {69315#false} is VALID [2022-02-21 04:24:42,341 INFO L290 TraceCheckUtils]: 107: Hoare triple {69315#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {69315#false} is VALID [2022-02-21 04:24:42,341 INFO L290 TraceCheckUtils]: 108: Hoare triple {69315#false} assume !(0 != activate_threads_~tmp___9~0#1); {69315#false} is VALID [2022-02-21 04:24:42,341 INFO L290 TraceCheckUtils]: 109: Hoare triple {69315#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {69315#false} is VALID [2022-02-21 04:24:42,342 INFO L290 TraceCheckUtils]: 110: Hoare triple {69315#false} assume !(1 == ~t11_pc~0); {69315#false} is VALID [2022-02-21 04:24:42,342 INFO L290 TraceCheckUtils]: 111: Hoare triple {69315#false} is_transmit11_triggered_~__retres1~11#1 := 0; {69315#false} is VALID [2022-02-21 04:24:42,342 INFO L290 TraceCheckUtils]: 112: Hoare triple {69315#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {69315#false} is VALID [2022-02-21 04:24:42,342 INFO L290 TraceCheckUtils]: 113: Hoare triple {69315#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {69315#false} is VALID [2022-02-21 04:24:42,342 INFO L290 TraceCheckUtils]: 114: Hoare triple {69315#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {69315#false} is VALID [2022-02-21 04:24:42,342 INFO L290 TraceCheckUtils]: 115: Hoare triple {69315#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {69315#false} is VALID [2022-02-21 04:24:42,342 INFO L290 TraceCheckUtils]: 116: Hoare triple {69315#false} assume 1 == ~t12_pc~0; {69315#false} is VALID [2022-02-21 04:24:42,342 INFO L290 TraceCheckUtils]: 117: Hoare triple {69315#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {69315#false} is VALID [2022-02-21 04:24:42,342 INFO L290 TraceCheckUtils]: 118: Hoare triple {69315#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {69315#false} is VALID [2022-02-21 04:24:42,343 INFO L290 TraceCheckUtils]: 119: Hoare triple {69315#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {69315#false} is VALID [2022-02-21 04:24:42,343 INFO L290 TraceCheckUtils]: 120: Hoare triple {69315#false} assume !(0 != activate_threads_~tmp___11~0#1); {69315#false} is VALID [2022-02-21 04:24:42,343 INFO L290 TraceCheckUtils]: 121: Hoare triple {69315#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {69315#false} is VALID [2022-02-21 04:24:42,343 INFO L290 TraceCheckUtils]: 122: Hoare triple {69315#false} assume !(1 == ~M_E~0); {69315#false} is VALID [2022-02-21 04:24:42,343 INFO L290 TraceCheckUtils]: 123: Hoare triple {69315#false} assume !(1 == ~T1_E~0); {69315#false} is VALID [2022-02-21 04:24:42,343 INFO L290 TraceCheckUtils]: 124: Hoare triple {69315#false} assume !(1 == ~T2_E~0); {69315#false} is VALID [2022-02-21 04:24:42,343 INFO L290 TraceCheckUtils]: 125: Hoare triple {69315#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {69315#false} is VALID [2022-02-21 04:24:42,343 INFO L290 TraceCheckUtils]: 126: Hoare triple {69315#false} assume !(1 == ~T4_E~0); {69315#false} is VALID [2022-02-21 04:24:42,343 INFO L290 TraceCheckUtils]: 127: Hoare triple {69315#false} assume !(1 == ~T5_E~0); {69315#false} is VALID [2022-02-21 04:24:42,344 INFO L290 TraceCheckUtils]: 128: Hoare triple {69315#false} assume !(1 == ~T6_E~0); {69315#false} is VALID [2022-02-21 04:24:42,344 INFO L290 TraceCheckUtils]: 129: Hoare triple {69315#false} assume !(1 == ~T7_E~0); {69315#false} is VALID [2022-02-21 04:24:42,344 INFO L290 TraceCheckUtils]: 130: Hoare triple {69315#false} assume !(1 == ~T8_E~0); {69315#false} is VALID [2022-02-21 04:24:42,344 INFO L290 TraceCheckUtils]: 131: Hoare triple {69315#false} assume !(1 == ~T9_E~0); {69315#false} is VALID [2022-02-21 04:24:42,344 INFO L290 TraceCheckUtils]: 132: Hoare triple {69315#false} assume !(1 == ~T10_E~0); {69315#false} is VALID [2022-02-21 04:24:42,344 INFO L290 TraceCheckUtils]: 133: Hoare triple {69315#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {69315#false} is VALID [2022-02-21 04:24:42,344 INFO L290 TraceCheckUtils]: 134: Hoare triple {69315#false} assume !(1 == ~T12_E~0); {69315#false} is VALID [2022-02-21 04:24:42,344 INFO L290 TraceCheckUtils]: 135: Hoare triple {69315#false} assume !(1 == ~E_1~0); {69315#false} is VALID [2022-02-21 04:24:42,344 INFO L290 TraceCheckUtils]: 136: Hoare triple {69315#false} assume !(1 == ~E_2~0); {69315#false} is VALID [2022-02-21 04:24:42,345 INFO L290 TraceCheckUtils]: 137: Hoare triple {69315#false} assume !(1 == ~E_3~0); {69315#false} is VALID [2022-02-21 04:24:42,345 INFO L290 TraceCheckUtils]: 138: Hoare triple {69315#false} assume !(1 == ~E_4~0); {69315#false} is VALID [2022-02-21 04:24:42,345 INFO L290 TraceCheckUtils]: 139: Hoare triple {69315#false} assume !(1 == ~E_5~0); {69315#false} is VALID [2022-02-21 04:24:42,345 INFO L290 TraceCheckUtils]: 140: Hoare triple {69315#false} assume !(1 == ~E_6~0); {69315#false} is VALID [2022-02-21 04:24:42,345 INFO L290 TraceCheckUtils]: 141: Hoare triple {69315#false} assume 1 == ~E_7~0;~E_7~0 := 2; {69315#false} is VALID [2022-02-21 04:24:42,345 INFO L290 TraceCheckUtils]: 142: Hoare triple {69315#false} assume !(1 == ~E_8~0); {69315#false} is VALID [2022-02-21 04:24:42,345 INFO L290 TraceCheckUtils]: 143: Hoare triple {69315#false} assume !(1 == ~E_9~0); {69315#false} is VALID [2022-02-21 04:24:42,345 INFO L290 TraceCheckUtils]: 144: Hoare triple {69315#false} assume !(1 == ~E_10~0); {69315#false} is VALID [2022-02-21 04:24:42,345 INFO L290 TraceCheckUtils]: 145: Hoare triple {69315#false} assume !(1 == ~E_11~0); {69315#false} is VALID [2022-02-21 04:24:42,346 INFO L290 TraceCheckUtils]: 146: Hoare triple {69315#false} assume !(1 == ~E_12~0); {69315#false} is VALID [2022-02-21 04:24:42,346 INFO L290 TraceCheckUtils]: 147: Hoare triple {69315#false} assume { :end_inline_reset_delta_events } true; {69315#false} is VALID [2022-02-21 04:24:42,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:42,346 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:42,346 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584040023] [2022-02-21 04:24:42,346 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584040023] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:42,347 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:42,347 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:42,347 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2118364753] [2022-02-21 04:24:42,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:42,348 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:42,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:42,348 INFO L85 PathProgramCache]: Analyzing trace with hash 1025229089, now seen corresponding path program 1 times [2022-02-21 04:24:42,348 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:42,348 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359170198] [2022-02-21 04:24:42,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:42,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:42,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:42,374 INFO L290 TraceCheckUtils]: 0: Hoare triple {69317#true} assume !false; {69317#true} is VALID [2022-02-21 04:24:42,374 INFO L290 TraceCheckUtils]: 1: Hoare triple {69317#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {69317#true} is VALID [2022-02-21 04:24:42,374 INFO L290 TraceCheckUtils]: 2: Hoare triple {69317#true} assume !false; {69317#true} is VALID [2022-02-21 04:24:42,374 INFO L290 TraceCheckUtils]: 3: Hoare triple {69317#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {69317#true} is VALID [2022-02-21 04:24:42,374 INFO L290 TraceCheckUtils]: 4: Hoare triple {69317#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {69317#true} is VALID [2022-02-21 04:24:42,374 INFO L290 TraceCheckUtils]: 5: Hoare triple {69317#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {69317#true} is VALID [2022-02-21 04:24:42,375 INFO L290 TraceCheckUtils]: 6: Hoare triple {69317#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {69317#true} is VALID [2022-02-21 04:24:42,375 INFO L290 TraceCheckUtils]: 7: Hoare triple {69317#true} assume !(0 != eval_~tmp~0#1); {69317#true} is VALID [2022-02-21 04:24:42,375 INFO L290 TraceCheckUtils]: 8: Hoare triple {69317#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {69317#true} is VALID [2022-02-21 04:24:42,375 INFO L290 TraceCheckUtils]: 9: Hoare triple {69317#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {69317#true} is VALID [2022-02-21 04:24:42,375 INFO L290 TraceCheckUtils]: 10: Hoare triple {69317#true} assume !(0 == ~M_E~0); {69317#true} is VALID [2022-02-21 04:24:42,375 INFO L290 TraceCheckUtils]: 11: Hoare triple {69317#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {69317#true} is VALID [2022-02-21 04:24:42,375 INFO L290 TraceCheckUtils]: 12: Hoare triple {69317#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,376 INFO L290 TraceCheckUtils]: 13: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,376 INFO L290 TraceCheckUtils]: 14: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,376 INFO L290 TraceCheckUtils]: 15: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,377 INFO L290 TraceCheckUtils]: 16: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,377 INFO L290 TraceCheckUtils]: 17: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,377 INFO L290 TraceCheckUtils]: 18: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,377 INFO L290 TraceCheckUtils]: 19: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,378 INFO L290 TraceCheckUtils]: 20: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,378 INFO L290 TraceCheckUtils]: 21: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,378 INFO L290 TraceCheckUtils]: 22: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,378 INFO L290 TraceCheckUtils]: 23: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,379 INFO L290 TraceCheckUtils]: 24: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,379 INFO L290 TraceCheckUtils]: 25: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,379 INFO L290 TraceCheckUtils]: 26: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,380 INFO L290 TraceCheckUtils]: 27: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,380 INFO L290 TraceCheckUtils]: 28: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,380 INFO L290 TraceCheckUtils]: 29: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,380 INFO L290 TraceCheckUtils]: 30: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,381 INFO L290 TraceCheckUtils]: 31: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,381 INFO L290 TraceCheckUtils]: 32: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,381 INFO L290 TraceCheckUtils]: 33: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,382 INFO L290 TraceCheckUtils]: 34: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,382 INFO L290 TraceCheckUtils]: 35: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,382 INFO L290 TraceCheckUtils]: 36: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,382 INFO L290 TraceCheckUtils]: 37: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,383 INFO L290 TraceCheckUtils]: 38: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,383 INFO L290 TraceCheckUtils]: 39: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,383 INFO L290 TraceCheckUtils]: 40: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,384 INFO L290 TraceCheckUtils]: 41: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,384 INFO L290 TraceCheckUtils]: 42: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,384 INFO L290 TraceCheckUtils]: 43: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,385 INFO L290 TraceCheckUtils]: 44: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,385 INFO L290 TraceCheckUtils]: 45: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,385 INFO L290 TraceCheckUtils]: 46: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,386 INFO L290 TraceCheckUtils]: 47: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,386 INFO L290 TraceCheckUtils]: 48: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,386 INFO L290 TraceCheckUtils]: 49: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,387 INFO L290 TraceCheckUtils]: 50: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,387 INFO L290 TraceCheckUtils]: 51: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,387 INFO L290 TraceCheckUtils]: 52: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,388 INFO L290 TraceCheckUtils]: 53: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,388 INFO L290 TraceCheckUtils]: 54: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,388 INFO L290 TraceCheckUtils]: 55: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,389 INFO L290 TraceCheckUtils]: 56: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,389 INFO L290 TraceCheckUtils]: 57: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,389 INFO L290 TraceCheckUtils]: 58: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,390 INFO L290 TraceCheckUtils]: 59: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,390 INFO L290 TraceCheckUtils]: 60: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,390 INFO L290 TraceCheckUtils]: 61: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,390 INFO L290 TraceCheckUtils]: 62: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,391 INFO L290 TraceCheckUtils]: 63: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,391 INFO L290 TraceCheckUtils]: 64: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,391 INFO L290 TraceCheckUtils]: 65: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,392 INFO L290 TraceCheckUtils]: 66: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,392 INFO L290 TraceCheckUtils]: 67: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,392 INFO L290 TraceCheckUtils]: 68: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,393 INFO L290 TraceCheckUtils]: 69: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,393 INFO L290 TraceCheckUtils]: 70: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,393 INFO L290 TraceCheckUtils]: 71: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,393 INFO L290 TraceCheckUtils]: 72: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,394 INFO L290 TraceCheckUtils]: 73: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,394 INFO L290 TraceCheckUtils]: 74: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,394 INFO L290 TraceCheckUtils]: 75: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,394 INFO L290 TraceCheckUtils]: 76: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,395 INFO L290 TraceCheckUtils]: 77: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,395 INFO L290 TraceCheckUtils]: 78: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,395 INFO L290 TraceCheckUtils]: 79: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,396 INFO L290 TraceCheckUtils]: 80: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,396 INFO L290 TraceCheckUtils]: 81: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,396 INFO L290 TraceCheckUtils]: 82: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,396 INFO L290 TraceCheckUtils]: 83: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,397 INFO L290 TraceCheckUtils]: 84: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,397 INFO L290 TraceCheckUtils]: 85: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,397 INFO L290 TraceCheckUtils]: 86: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,398 INFO L290 TraceCheckUtils]: 87: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,398 INFO L290 TraceCheckUtils]: 88: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,398 INFO L290 TraceCheckUtils]: 89: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,398 INFO L290 TraceCheckUtils]: 90: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,399 INFO L290 TraceCheckUtils]: 91: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,399 INFO L290 TraceCheckUtils]: 92: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,399 INFO L290 TraceCheckUtils]: 93: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,400 INFO L290 TraceCheckUtils]: 94: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,400 INFO L290 TraceCheckUtils]: 95: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,400 INFO L290 TraceCheckUtils]: 96: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t10_pc~0); {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,400 INFO L290 TraceCheckUtils]: 97: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,401 INFO L290 TraceCheckUtils]: 98: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,401 INFO L290 TraceCheckUtils]: 99: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,401 INFO L290 TraceCheckUtils]: 100: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,401 INFO L290 TraceCheckUtils]: 101: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,402 INFO L290 TraceCheckUtils]: 102: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,402 INFO L290 TraceCheckUtils]: 103: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,402 INFO L290 TraceCheckUtils]: 104: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,403 INFO L290 TraceCheckUtils]: 105: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,403 INFO L290 TraceCheckUtils]: 106: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,403 INFO L290 TraceCheckUtils]: 107: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,403 INFO L290 TraceCheckUtils]: 108: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t12_pc~0); {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,404 INFO L290 TraceCheckUtils]: 109: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,404 INFO L290 TraceCheckUtils]: 110: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,404 INFO L290 TraceCheckUtils]: 111: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,404 INFO L290 TraceCheckUtils]: 112: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,405 INFO L290 TraceCheckUtils]: 113: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,405 INFO L290 TraceCheckUtils]: 114: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,405 INFO L290 TraceCheckUtils]: 115: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {69319#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:42,406 INFO L290 TraceCheckUtils]: 116: Hoare triple {69319#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {69318#false} is VALID [2022-02-21 04:24:42,406 INFO L290 TraceCheckUtils]: 117: Hoare triple {69318#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,406 INFO L290 TraceCheckUtils]: 118: Hoare triple {69318#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,406 INFO L290 TraceCheckUtils]: 119: Hoare triple {69318#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,406 INFO L290 TraceCheckUtils]: 120: Hoare triple {69318#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,406 INFO L290 TraceCheckUtils]: 121: Hoare triple {69318#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,406 INFO L290 TraceCheckUtils]: 122: Hoare triple {69318#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,406 INFO L290 TraceCheckUtils]: 123: Hoare triple {69318#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,407 INFO L290 TraceCheckUtils]: 124: Hoare triple {69318#false} assume !(1 == ~T10_E~0); {69318#false} is VALID [2022-02-21 04:24:42,407 INFO L290 TraceCheckUtils]: 125: Hoare triple {69318#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,407 INFO L290 TraceCheckUtils]: 126: Hoare triple {69318#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,407 INFO L290 TraceCheckUtils]: 127: Hoare triple {69318#false} assume 1 == ~E_1~0;~E_1~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,407 INFO L290 TraceCheckUtils]: 128: Hoare triple {69318#false} assume 1 == ~E_2~0;~E_2~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,407 INFO L290 TraceCheckUtils]: 129: Hoare triple {69318#false} assume 1 == ~E_3~0;~E_3~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,407 INFO L290 TraceCheckUtils]: 130: Hoare triple {69318#false} assume 1 == ~E_4~0;~E_4~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,407 INFO L290 TraceCheckUtils]: 131: Hoare triple {69318#false} assume 1 == ~E_5~0;~E_5~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,414 INFO L290 TraceCheckUtils]: 132: Hoare triple {69318#false} assume !(1 == ~E_6~0); {69318#false} is VALID [2022-02-21 04:24:42,414 INFO L290 TraceCheckUtils]: 133: Hoare triple {69318#false} assume 1 == ~E_7~0;~E_7~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,414 INFO L290 TraceCheckUtils]: 134: Hoare triple {69318#false} assume 1 == ~E_8~0;~E_8~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,414 INFO L290 TraceCheckUtils]: 135: Hoare triple {69318#false} assume 1 == ~E_9~0;~E_9~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,415 INFO L290 TraceCheckUtils]: 136: Hoare triple {69318#false} assume 1 == ~E_10~0;~E_10~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,415 INFO L290 TraceCheckUtils]: 137: Hoare triple {69318#false} assume 1 == ~E_11~0;~E_11~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,415 INFO L290 TraceCheckUtils]: 138: Hoare triple {69318#false} assume 1 == ~E_12~0;~E_12~0 := 2; {69318#false} is VALID [2022-02-21 04:24:42,415 INFO L290 TraceCheckUtils]: 139: Hoare triple {69318#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {69318#false} is VALID [2022-02-21 04:24:42,415 INFO L290 TraceCheckUtils]: 140: Hoare triple {69318#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {69318#false} is VALID [2022-02-21 04:24:42,415 INFO L290 TraceCheckUtils]: 141: Hoare triple {69318#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {69318#false} is VALID [2022-02-21 04:24:42,415 INFO L290 TraceCheckUtils]: 142: Hoare triple {69318#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {69318#false} is VALID [2022-02-21 04:24:42,415 INFO L290 TraceCheckUtils]: 143: Hoare triple {69318#false} assume !(0 == start_simulation_~tmp~3#1); {69318#false} is VALID [2022-02-21 04:24:42,415 INFO L290 TraceCheckUtils]: 144: Hoare triple {69318#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {69318#false} is VALID [2022-02-21 04:24:42,416 INFO L290 TraceCheckUtils]: 145: Hoare triple {69318#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {69318#false} is VALID [2022-02-21 04:24:42,416 INFO L290 TraceCheckUtils]: 146: Hoare triple {69318#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {69318#false} is VALID [2022-02-21 04:24:42,416 INFO L290 TraceCheckUtils]: 147: Hoare triple {69318#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {69318#false} is VALID [2022-02-21 04:24:42,416 INFO L290 TraceCheckUtils]: 148: Hoare triple {69318#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {69318#false} is VALID [2022-02-21 04:24:42,416 INFO L290 TraceCheckUtils]: 149: Hoare triple {69318#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {69318#false} is VALID [2022-02-21 04:24:42,416 INFO L290 TraceCheckUtils]: 150: Hoare triple {69318#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {69318#false} is VALID [2022-02-21 04:24:42,416 INFO L290 TraceCheckUtils]: 151: Hoare triple {69318#false} assume !(0 != start_simulation_~tmp___0~1#1); {69318#false} is VALID [2022-02-21 04:24:42,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:42,417 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:42,417 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1359170198] [2022-02-21 04:24:42,417 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1359170198] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:42,417 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:42,417 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:42,417 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096445663] [2022-02-21 04:24:42,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:42,418 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:42,418 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:42,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:42,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:42,419 INFO L87 Difference]: Start difference. First operand 1688 states and 2495 transitions. cyclomatic complexity: 808 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:43,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:43,706 INFO L93 Difference]: Finished difference Result 1688 states and 2494 transitions. [2022-02-21 04:24:43,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:43,707 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:43,793 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:43,794 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2494 transitions. [2022-02-21 04:24:43,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:44,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2494 transitions. [2022-02-21 04:24:44,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:44,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:44,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2494 transitions. [2022-02-21 04:24:44,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:44,036 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2022-02-21 04:24:44,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2494 transitions. [2022-02-21 04:24:44,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:44,052 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:44,054 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2494 transitions. Second operand has 1688 states, 1688 states have (on average 1.4774881516587677) internal successors, (2494), 1687 states have internal predecessors, (2494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,055 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2494 transitions. Second operand has 1688 states, 1688 states have (on average 1.4774881516587677) internal successors, (2494), 1687 states have internal predecessors, (2494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,056 INFO L87 Difference]: Start difference. First operand 1688 states and 2494 transitions. Second operand has 1688 states, 1688 states have (on average 1.4774881516587677) internal successors, (2494), 1687 states have internal predecessors, (2494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:44,125 INFO L93 Difference]: Finished difference Result 1688 states and 2494 transitions. [2022-02-21 04:24:44,125 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2494 transitions. [2022-02-21 04:24:44,127 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:44,127 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:44,129 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.4774881516587677) internal successors, (2494), 1687 states have internal predecessors, (2494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2494 transitions. [2022-02-21 04:24:44,130 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.4774881516587677) internal successors, (2494), 1687 states have internal predecessors, (2494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2494 transitions. [2022-02-21 04:24:44,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:44,201 INFO L93 Difference]: Finished difference Result 1688 states and 2494 transitions. [2022-02-21 04:24:44,201 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2494 transitions. [2022-02-21 04:24:44,203 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:44,203 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:44,203 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:44,203 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:44,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4774881516587677) internal successors, (2494), 1687 states have internal predecessors, (2494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2494 transitions. [2022-02-21 04:24:44,285 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2022-02-21 04:24:44,285 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2494 transitions. [2022-02-21 04:24:44,286 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:24:44,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2494 transitions. [2022-02-21 04:24:44,289 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:44,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:44,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:44,290 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:44,291 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:44,291 INFO L791 eck$LassoCheckResult]: Stem: 71813#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 71814#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 72665#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 72159#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 71964#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 71965#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 72050#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 72355#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 72473#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 72474#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 71262#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 71263#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 72411#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 71857#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 71858#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 71766#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 71767#L876-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 72154#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 71506#L1174 assume !(0 == ~M_E~0); 71507#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 71358#L1179-1 assume !(0 == ~T2_E~0); 71260#L1184-1 assume !(0 == ~T3_E~0); 71261#L1189-1 assume !(0 == ~T4_E~0); 71299#L1194-1 assume !(0 == ~T5_E~0); 71399#L1199-1 assume !(0 == ~T6_E~0); 72294#L1204-1 assume !(0 == ~T7_E~0); 72213#L1209-1 assume !(0 == ~T8_E~0); 72214#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 72602#L1219-1 assume !(0 == ~T10_E~0); 72687#L1224-1 assume !(0 == ~T11_E~0); 71625#L1229-1 assume !(0 == ~T12_E~0); 71187#L1234-1 assume !(0 == ~E_1~0); 71188#L1239-1 assume !(0 == ~E_2~0); 71221#L1244-1 assume !(0 == ~E_3~0); 71222#L1249-1 assume !(0 == ~E_4~0); 71881#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 71115#L1259-1 assume !(0 == ~E_6~0); 71070#L1264-1 assume !(0 == ~E_7~0); 71071#L1269-1 assume !(0 == ~E_8~0); 72692#L1274-1 assume !(0 == ~E_9~0); 72627#L1279-1 assume !(0 == ~E_10~0); 71303#L1284-1 assume !(0 == ~E_11~0); 71304#L1289-1 assume !(0 == ~E_12~0); 71933#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71934#L566 assume 1 == ~m_pc~0; 71087#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 71088#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72242#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 72243#L1455 assume !(0 != activate_threads_~tmp~1#1); 71533#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71534#L585 assume 1 == ~t1_pc~0; 71182#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 71183#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72183#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 72184#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 72652#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72650#L604 assume !(1 == ~t2_pc~0); 72262#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 72263#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71796#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 71797#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72436#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72437#L623 assume 1 == ~t3_pc~0; 71711#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 71051#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 71861#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 71862#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 72469#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 71084#L642 assume !(1 == ~t4_pc~0); 71085#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 71550#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71551#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71158#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 71159#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 72274#L661 assume 1 == ~t5_pc~0; 71321#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 71322#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71283#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 71284#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 72305#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72306#L680 assume !(1 == ~t6_pc~0); 71744#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 71745#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 72006#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 72007#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 72535#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72648#L699 assume 1 == ~t7_pc~0; 72134#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 72135#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71311#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 71312#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 72036#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 71935#L718 assume !(1 == ~t8_pc~0); 71936#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 71297#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 71298#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 71341#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 71342#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 71473#L737 assume 1 == ~t9_pc~0; 72339#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 71609#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 72209#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 72210#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 71782#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 71783#L756 assume 1 == ~t10_pc~0; 72362#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 72028#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 71014#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71015#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 71590#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 71591#L775 assume !(1 == ~t11_pc~0); 71845#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 71846#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 71470#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 71231#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 71232#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 71418#L794 assume 1 == ~t12_pc~0; 71259#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 71236#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 72429#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 71386#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 71387#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71864#L1307 assume !(1 == ~M_E~0); 71865#L1307-2 assume !(1 == ~T1_E~0); 71976#L1312-1 assume !(1 == ~T2_E~0); 71895#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 71896#L1322-1 assume !(1 == ~T4_E~0); 71599#L1327-1 assume !(1 == ~T5_E~0); 71600#L1332-1 assume !(1 == ~T6_E~0); 72138#L1337-1 assume !(1 == ~T7_E~0); 72100#L1342-1 assume !(1 == ~T8_E~0); 72101#L1347-1 assume !(1 == ~T9_E~0); 72498#L1352-1 assume !(1 == ~T10_E~0); 72371#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 71762#L1362-1 assume !(1 == ~T12_E~0); 71763#L1367-1 assume !(1 == ~E_1~0); 71400#L1372-1 assume !(1 == ~E_2~0); 71401#L1377-1 assume !(1 == ~E_3~0); 71694#L1382-1 assume !(1 == ~E_4~0); 71695#L1387-1 assume !(1 == ~E_5~0); 72264#L1392-1 assume !(1 == ~E_6~0); 71716#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 71717#L1402-1 assume !(1 == ~E_8~0); 71416#L1407-1 assume !(1 == ~E_9~0); 71417#L1412-1 assume !(1 == ~E_10~0); 72427#L1417-1 assume !(1 == ~E_11~0); 72428#L1422-1 assume !(1 == ~E_12~0); 72646#L1427-1 assume { :end_inline_reset_delta_events } true; 71215#L1768-2 [2022-02-21 04:24:44,291 INFO L793 eck$LassoCheckResult]: Loop: 71215#L1768-2 assume !false; 71216#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 71956#L1149 assume !false; 72327#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 72479#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 71605#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 71517#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 71518#L976 assume !(0 != eval_~tmp~0#1); 72645#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72655#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 72446#L1174-3 assume !(0 == ~M_E~0); 72439#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 72188#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 72189#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 72373#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 72023#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 71376#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 71377#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 71615#L1209-3 assume !(0 == ~T8_E~0); 71035#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 71036#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 71794#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 71795#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 71811#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 71223#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 71224#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 71667#L1249-3 assume !(0 == ~E_4~0); 72126#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 72598#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 72240#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 71229#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 71230#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 72625#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 71792#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 71793#L1289-3 assume !(0 == ~E_12~0); 71781#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71457#L566-39 assume !(1 == ~m_pc~0); 71459#L566-41 is_master_triggered_~__retres1~0#1 := 0; 72060#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 71772#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 71773#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72315#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72316#L585-39 assume !(1 == ~t1_pc~0); 71465#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 71466#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 71541#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 71542#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 72348#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72041#L604-39 assume !(1 == ~t2_pc~0); 72043#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 71673#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71674#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 72091#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72092#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71656#L623-39 assume !(1 == ~t3_pc~0); 71053#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 71054#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72332#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 71508#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 71509#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 72280#L642-39 assume 1 == ~t4_pc~0; 71851#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 71852#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71380#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 71381#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 72478#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 71429#L661-39 assume !(1 == ~t5_pc~0); 71060#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 71061#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 72421#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 72422#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 72335#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72336#L680-39 assume 1 == ~t6_pc~0; 71122#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 71123#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 72265#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 71588#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 71589#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72603#L699-39 assume 1 == ~t7_pc~0; 72025#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 71747#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71748#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 72431#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 72552#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 72550#L718-39 assume 1 == ~t8_pc~0; 71939#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 71940#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 71872#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 71873#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 72174#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 72144#L737-39 assume 1 == ~t9_pc~0; 71569#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 71570#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 71859#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 72626#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 72527#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 72470#L756-39 assume 1 == ~t10_pc~0; 72471#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 71952#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 71696#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 71697#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 71829#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 71169#L775-39 assume !(1 == ~t11_pc~0); 71171#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 71822#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 71823#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 72685#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 72233#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 71880#L794-39 assume 1 == ~t12_pc~0; 71572#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 71566#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 72386#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 72287#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 71111#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 71112#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 72579#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 72580#L1312-3 assume !(1 == ~T2_E~0); 72691#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 72303#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 72304#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 71250#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 71219#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 71220#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 71968#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 72093#L1352-3 assume !(1 == ~T10_E~0); 72094#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 72533#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 72684#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 72675#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 71045#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 71046#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 71680#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 71681#L1392-3 assume !(1 == ~E_6~0); 72396#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 72642#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 72059#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 71335#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 71336#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 71984#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 71985#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 71345#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 71346#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 72212#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 72064#L1787 assume !(0 == start_simulation_~tmp~3#1); 72065#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 72588#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 71316#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 72111#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 72112#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 71663#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 71664#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 71665#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 71215#L1768-2 [2022-02-21 04:24:44,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:44,292 INFO L85 PathProgramCache]: Analyzing trace with hash -1079563311, now seen corresponding path program 1 times [2022-02-21 04:24:44,292 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:44,292 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183180032] [2022-02-21 04:24:44,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:44,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:44,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:44,314 INFO L290 TraceCheckUtils]: 0: Hoare triple {76075#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {76075#true} is VALID [2022-02-21 04:24:44,315 INFO L290 TraceCheckUtils]: 1: Hoare triple {76075#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,315 INFO L290 TraceCheckUtils]: 2: Hoare triple {76077#(= ~t12_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,315 INFO L290 TraceCheckUtils]: 3: Hoare triple {76077#(= ~t12_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,316 INFO L290 TraceCheckUtils]: 4: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,337 INFO L290 TraceCheckUtils]: 5: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,337 INFO L290 TraceCheckUtils]: 6: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,337 INFO L290 TraceCheckUtils]: 7: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,338 INFO L290 TraceCheckUtils]: 8: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,338 INFO L290 TraceCheckUtils]: 9: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,338 INFO L290 TraceCheckUtils]: 10: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,339 INFO L290 TraceCheckUtils]: 11: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,339 INFO L290 TraceCheckUtils]: 12: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,339 INFO L290 TraceCheckUtils]: 13: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,340 INFO L290 TraceCheckUtils]: 14: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,340 INFO L290 TraceCheckUtils]: 15: Hoare triple {76077#(= ~t12_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {76077#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:44,340 INFO L290 TraceCheckUtils]: 16: Hoare triple {76077#(= ~t12_i~0 1)} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {76076#false} is VALID [2022-02-21 04:24:44,341 INFO L290 TraceCheckUtils]: 17: Hoare triple {76076#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {76076#false} is VALID [2022-02-21 04:24:44,341 INFO L290 TraceCheckUtils]: 18: Hoare triple {76076#false} assume !(0 == ~M_E~0); {76076#false} is VALID [2022-02-21 04:24:44,341 INFO L290 TraceCheckUtils]: 19: Hoare triple {76076#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {76076#false} is VALID [2022-02-21 04:24:44,341 INFO L290 TraceCheckUtils]: 20: Hoare triple {76076#false} assume !(0 == ~T2_E~0); {76076#false} is VALID [2022-02-21 04:24:44,341 INFO L290 TraceCheckUtils]: 21: Hoare triple {76076#false} assume !(0 == ~T3_E~0); {76076#false} is VALID [2022-02-21 04:24:44,341 INFO L290 TraceCheckUtils]: 22: Hoare triple {76076#false} assume !(0 == ~T4_E~0); {76076#false} is VALID [2022-02-21 04:24:44,341 INFO L290 TraceCheckUtils]: 23: Hoare triple {76076#false} assume !(0 == ~T5_E~0); {76076#false} is VALID [2022-02-21 04:24:44,341 INFO L290 TraceCheckUtils]: 24: Hoare triple {76076#false} assume !(0 == ~T6_E~0); {76076#false} is VALID [2022-02-21 04:24:44,342 INFO L290 TraceCheckUtils]: 25: Hoare triple {76076#false} assume !(0 == ~T7_E~0); {76076#false} is VALID [2022-02-21 04:24:44,342 INFO L290 TraceCheckUtils]: 26: Hoare triple {76076#false} assume !(0 == ~T8_E~0); {76076#false} is VALID [2022-02-21 04:24:44,342 INFO L290 TraceCheckUtils]: 27: Hoare triple {76076#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {76076#false} is VALID [2022-02-21 04:24:44,342 INFO L290 TraceCheckUtils]: 28: Hoare triple {76076#false} assume !(0 == ~T10_E~0); {76076#false} is VALID [2022-02-21 04:24:44,342 INFO L290 TraceCheckUtils]: 29: Hoare triple {76076#false} assume !(0 == ~T11_E~0); {76076#false} is VALID [2022-02-21 04:24:44,342 INFO L290 TraceCheckUtils]: 30: Hoare triple {76076#false} assume !(0 == ~T12_E~0); {76076#false} is VALID [2022-02-21 04:24:44,342 INFO L290 TraceCheckUtils]: 31: Hoare triple {76076#false} assume !(0 == ~E_1~0); {76076#false} is VALID [2022-02-21 04:24:44,343 INFO L290 TraceCheckUtils]: 32: Hoare triple {76076#false} assume !(0 == ~E_2~0); {76076#false} is VALID [2022-02-21 04:24:44,343 INFO L290 TraceCheckUtils]: 33: Hoare triple {76076#false} assume !(0 == ~E_3~0); {76076#false} is VALID [2022-02-21 04:24:44,343 INFO L290 TraceCheckUtils]: 34: Hoare triple {76076#false} assume !(0 == ~E_4~0); {76076#false} is VALID [2022-02-21 04:24:44,343 INFO L290 TraceCheckUtils]: 35: Hoare triple {76076#false} assume 0 == ~E_5~0;~E_5~0 := 1; {76076#false} is VALID [2022-02-21 04:24:44,343 INFO L290 TraceCheckUtils]: 36: Hoare triple {76076#false} assume !(0 == ~E_6~0); {76076#false} is VALID [2022-02-21 04:24:44,343 INFO L290 TraceCheckUtils]: 37: Hoare triple {76076#false} assume !(0 == ~E_7~0); {76076#false} is VALID [2022-02-21 04:24:44,343 INFO L290 TraceCheckUtils]: 38: Hoare triple {76076#false} assume !(0 == ~E_8~0); {76076#false} is VALID [2022-02-21 04:24:44,343 INFO L290 TraceCheckUtils]: 39: Hoare triple {76076#false} assume !(0 == ~E_9~0); {76076#false} is VALID [2022-02-21 04:24:44,344 INFO L290 TraceCheckUtils]: 40: Hoare triple {76076#false} assume !(0 == ~E_10~0); {76076#false} is VALID [2022-02-21 04:24:44,344 INFO L290 TraceCheckUtils]: 41: Hoare triple {76076#false} assume !(0 == ~E_11~0); {76076#false} is VALID [2022-02-21 04:24:44,344 INFO L290 TraceCheckUtils]: 42: Hoare triple {76076#false} assume !(0 == ~E_12~0); {76076#false} is VALID [2022-02-21 04:24:44,344 INFO L290 TraceCheckUtils]: 43: Hoare triple {76076#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {76076#false} is VALID [2022-02-21 04:24:44,344 INFO L290 TraceCheckUtils]: 44: Hoare triple {76076#false} assume 1 == ~m_pc~0; {76076#false} is VALID [2022-02-21 04:24:44,344 INFO L290 TraceCheckUtils]: 45: Hoare triple {76076#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {76076#false} is VALID [2022-02-21 04:24:44,344 INFO L290 TraceCheckUtils]: 46: Hoare triple {76076#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {76076#false} is VALID [2022-02-21 04:24:44,345 INFO L290 TraceCheckUtils]: 47: Hoare triple {76076#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {76076#false} is VALID [2022-02-21 04:24:44,345 INFO L290 TraceCheckUtils]: 48: Hoare triple {76076#false} assume !(0 != activate_threads_~tmp~1#1); {76076#false} is VALID [2022-02-21 04:24:44,345 INFO L290 TraceCheckUtils]: 49: Hoare triple {76076#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {76076#false} is VALID [2022-02-21 04:24:44,345 INFO L290 TraceCheckUtils]: 50: Hoare triple {76076#false} assume 1 == ~t1_pc~0; {76076#false} is VALID [2022-02-21 04:24:44,345 INFO L290 TraceCheckUtils]: 51: Hoare triple {76076#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {76076#false} is VALID [2022-02-21 04:24:44,345 INFO L290 TraceCheckUtils]: 52: Hoare triple {76076#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {76076#false} is VALID [2022-02-21 04:24:44,345 INFO L290 TraceCheckUtils]: 53: Hoare triple {76076#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {76076#false} is VALID [2022-02-21 04:24:44,346 INFO L290 TraceCheckUtils]: 54: Hoare triple {76076#false} assume !(0 != activate_threads_~tmp___0~0#1); {76076#false} is VALID [2022-02-21 04:24:44,346 INFO L290 TraceCheckUtils]: 55: Hoare triple {76076#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {76076#false} is VALID [2022-02-21 04:24:44,346 INFO L290 TraceCheckUtils]: 56: Hoare triple {76076#false} assume !(1 == ~t2_pc~0); {76076#false} is VALID [2022-02-21 04:24:44,346 INFO L290 TraceCheckUtils]: 57: Hoare triple {76076#false} is_transmit2_triggered_~__retres1~2#1 := 0; {76076#false} is VALID [2022-02-21 04:24:44,346 INFO L290 TraceCheckUtils]: 58: Hoare triple {76076#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {76076#false} is VALID [2022-02-21 04:24:44,346 INFO L290 TraceCheckUtils]: 59: Hoare triple {76076#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {76076#false} is VALID [2022-02-21 04:24:44,346 INFO L290 TraceCheckUtils]: 60: Hoare triple {76076#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {76076#false} is VALID [2022-02-21 04:24:44,346 INFO L290 TraceCheckUtils]: 61: Hoare triple {76076#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {76076#false} is VALID [2022-02-21 04:24:44,347 INFO L290 TraceCheckUtils]: 62: Hoare triple {76076#false} assume 1 == ~t3_pc~0; {76076#false} is VALID [2022-02-21 04:24:44,347 INFO L290 TraceCheckUtils]: 63: Hoare triple {76076#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {76076#false} is VALID [2022-02-21 04:24:44,347 INFO L290 TraceCheckUtils]: 64: Hoare triple {76076#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {76076#false} is VALID [2022-02-21 04:24:44,347 INFO L290 TraceCheckUtils]: 65: Hoare triple {76076#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {76076#false} is VALID [2022-02-21 04:24:44,347 INFO L290 TraceCheckUtils]: 66: Hoare triple {76076#false} assume !(0 != activate_threads_~tmp___2~0#1); {76076#false} is VALID [2022-02-21 04:24:44,347 INFO L290 TraceCheckUtils]: 67: Hoare triple {76076#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {76076#false} is VALID [2022-02-21 04:24:44,347 INFO L290 TraceCheckUtils]: 68: Hoare triple {76076#false} assume !(1 == ~t4_pc~0); {76076#false} is VALID [2022-02-21 04:24:44,348 INFO L290 TraceCheckUtils]: 69: Hoare triple {76076#false} is_transmit4_triggered_~__retres1~4#1 := 0; {76076#false} is VALID [2022-02-21 04:24:44,348 INFO L290 TraceCheckUtils]: 70: Hoare triple {76076#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {76076#false} is VALID [2022-02-21 04:24:44,348 INFO L290 TraceCheckUtils]: 71: Hoare triple {76076#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {76076#false} is VALID [2022-02-21 04:24:44,348 INFO L290 TraceCheckUtils]: 72: Hoare triple {76076#false} assume !(0 != activate_threads_~tmp___3~0#1); {76076#false} is VALID [2022-02-21 04:24:44,348 INFO L290 TraceCheckUtils]: 73: Hoare triple {76076#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {76076#false} is VALID [2022-02-21 04:24:44,348 INFO L290 TraceCheckUtils]: 74: Hoare triple {76076#false} assume 1 == ~t5_pc~0; {76076#false} is VALID [2022-02-21 04:24:44,348 INFO L290 TraceCheckUtils]: 75: Hoare triple {76076#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {76076#false} is VALID [2022-02-21 04:24:44,348 INFO L290 TraceCheckUtils]: 76: Hoare triple {76076#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {76076#false} is VALID [2022-02-21 04:24:44,349 INFO L290 TraceCheckUtils]: 77: Hoare triple {76076#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {76076#false} is VALID [2022-02-21 04:24:44,349 INFO L290 TraceCheckUtils]: 78: Hoare triple {76076#false} assume !(0 != activate_threads_~tmp___4~0#1); {76076#false} is VALID [2022-02-21 04:24:44,349 INFO L290 TraceCheckUtils]: 79: Hoare triple {76076#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {76076#false} is VALID [2022-02-21 04:24:44,349 INFO L290 TraceCheckUtils]: 80: Hoare triple {76076#false} assume !(1 == ~t6_pc~0); {76076#false} is VALID [2022-02-21 04:24:44,349 INFO L290 TraceCheckUtils]: 81: Hoare triple {76076#false} is_transmit6_triggered_~__retres1~6#1 := 0; {76076#false} is VALID [2022-02-21 04:24:44,349 INFO L290 TraceCheckUtils]: 82: Hoare triple {76076#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {76076#false} is VALID [2022-02-21 04:24:44,349 INFO L290 TraceCheckUtils]: 83: Hoare triple {76076#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {76076#false} is VALID [2022-02-21 04:24:44,350 INFO L290 TraceCheckUtils]: 84: Hoare triple {76076#false} assume !(0 != activate_threads_~tmp___5~0#1); {76076#false} is VALID [2022-02-21 04:24:44,350 INFO L290 TraceCheckUtils]: 85: Hoare triple {76076#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {76076#false} is VALID [2022-02-21 04:24:44,350 INFO L290 TraceCheckUtils]: 86: Hoare triple {76076#false} assume 1 == ~t7_pc~0; {76076#false} is VALID [2022-02-21 04:24:44,350 INFO L290 TraceCheckUtils]: 87: Hoare triple {76076#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {76076#false} is VALID [2022-02-21 04:24:44,350 INFO L290 TraceCheckUtils]: 88: Hoare triple {76076#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {76076#false} is VALID [2022-02-21 04:24:44,350 INFO L290 TraceCheckUtils]: 89: Hoare triple {76076#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {76076#false} is VALID [2022-02-21 04:24:44,350 INFO L290 TraceCheckUtils]: 90: Hoare triple {76076#false} assume !(0 != activate_threads_~tmp___6~0#1); {76076#false} is VALID [2022-02-21 04:24:44,350 INFO L290 TraceCheckUtils]: 91: Hoare triple {76076#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {76076#false} is VALID [2022-02-21 04:24:44,351 INFO L290 TraceCheckUtils]: 92: Hoare triple {76076#false} assume !(1 == ~t8_pc~0); {76076#false} is VALID [2022-02-21 04:24:44,351 INFO L290 TraceCheckUtils]: 93: Hoare triple {76076#false} is_transmit8_triggered_~__retres1~8#1 := 0; {76076#false} is VALID [2022-02-21 04:24:44,351 INFO L290 TraceCheckUtils]: 94: Hoare triple {76076#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {76076#false} is VALID [2022-02-21 04:24:44,351 INFO L290 TraceCheckUtils]: 95: Hoare triple {76076#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {76076#false} is VALID [2022-02-21 04:24:44,351 INFO L290 TraceCheckUtils]: 96: Hoare triple {76076#false} assume !(0 != activate_threads_~tmp___7~0#1); {76076#false} is VALID [2022-02-21 04:24:44,351 INFO L290 TraceCheckUtils]: 97: Hoare triple {76076#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {76076#false} is VALID [2022-02-21 04:24:44,351 INFO L290 TraceCheckUtils]: 98: Hoare triple {76076#false} assume 1 == ~t9_pc~0; {76076#false} is VALID [2022-02-21 04:24:44,352 INFO L290 TraceCheckUtils]: 99: Hoare triple {76076#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {76076#false} is VALID [2022-02-21 04:24:44,352 INFO L290 TraceCheckUtils]: 100: Hoare triple {76076#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {76076#false} is VALID [2022-02-21 04:24:44,352 INFO L290 TraceCheckUtils]: 101: Hoare triple {76076#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {76076#false} is VALID [2022-02-21 04:24:44,352 INFO L290 TraceCheckUtils]: 102: Hoare triple {76076#false} assume !(0 != activate_threads_~tmp___8~0#1); {76076#false} is VALID [2022-02-21 04:24:44,352 INFO L290 TraceCheckUtils]: 103: Hoare triple {76076#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {76076#false} is VALID [2022-02-21 04:24:44,352 INFO L290 TraceCheckUtils]: 104: Hoare triple {76076#false} assume 1 == ~t10_pc~0; {76076#false} is VALID [2022-02-21 04:24:44,352 INFO L290 TraceCheckUtils]: 105: Hoare triple {76076#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {76076#false} is VALID [2022-02-21 04:24:44,352 INFO L290 TraceCheckUtils]: 106: Hoare triple {76076#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {76076#false} is VALID [2022-02-21 04:24:44,353 INFO L290 TraceCheckUtils]: 107: Hoare triple {76076#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {76076#false} is VALID [2022-02-21 04:24:44,353 INFO L290 TraceCheckUtils]: 108: Hoare triple {76076#false} assume !(0 != activate_threads_~tmp___9~0#1); {76076#false} is VALID [2022-02-21 04:24:44,353 INFO L290 TraceCheckUtils]: 109: Hoare triple {76076#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {76076#false} is VALID [2022-02-21 04:24:44,353 INFO L290 TraceCheckUtils]: 110: Hoare triple {76076#false} assume !(1 == ~t11_pc~0); {76076#false} is VALID [2022-02-21 04:24:44,353 INFO L290 TraceCheckUtils]: 111: Hoare triple {76076#false} is_transmit11_triggered_~__retres1~11#1 := 0; {76076#false} is VALID [2022-02-21 04:24:44,353 INFO L290 TraceCheckUtils]: 112: Hoare triple {76076#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {76076#false} is VALID [2022-02-21 04:24:44,353 INFO L290 TraceCheckUtils]: 113: Hoare triple {76076#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {76076#false} is VALID [2022-02-21 04:24:44,354 INFO L290 TraceCheckUtils]: 114: Hoare triple {76076#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {76076#false} is VALID [2022-02-21 04:24:44,354 INFO L290 TraceCheckUtils]: 115: Hoare triple {76076#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {76076#false} is VALID [2022-02-21 04:24:44,354 INFO L290 TraceCheckUtils]: 116: Hoare triple {76076#false} assume 1 == ~t12_pc~0; {76076#false} is VALID [2022-02-21 04:24:44,354 INFO L290 TraceCheckUtils]: 117: Hoare triple {76076#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {76076#false} is VALID [2022-02-21 04:24:44,354 INFO L290 TraceCheckUtils]: 118: Hoare triple {76076#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {76076#false} is VALID [2022-02-21 04:24:44,354 INFO L290 TraceCheckUtils]: 119: Hoare triple {76076#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {76076#false} is VALID [2022-02-21 04:24:44,354 INFO L290 TraceCheckUtils]: 120: Hoare triple {76076#false} assume !(0 != activate_threads_~tmp___11~0#1); {76076#false} is VALID [2022-02-21 04:24:44,354 INFO L290 TraceCheckUtils]: 121: Hoare triple {76076#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {76076#false} is VALID [2022-02-21 04:24:44,355 INFO L290 TraceCheckUtils]: 122: Hoare triple {76076#false} assume !(1 == ~M_E~0); {76076#false} is VALID [2022-02-21 04:24:44,355 INFO L290 TraceCheckUtils]: 123: Hoare triple {76076#false} assume !(1 == ~T1_E~0); {76076#false} is VALID [2022-02-21 04:24:44,355 INFO L290 TraceCheckUtils]: 124: Hoare triple {76076#false} assume !(1 == ~T2_E~0); {76076#false} is VALID [2022-02-21 04:24:44,355 INFO L290 TraceCheckUtils]: 125: Hoare triple {76076#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {76076#false} is VALID [2022-02-21 04:24:44,355 INFO L290 TraceCheckUtils]: 126: Hoare triple {76076#false} assume !(1 == ~T4_E~0); {76076#false} is VALID [2022-02-21 04:24:44,355 INFO L290 TraceCheckUtils]: 127: Hoare triple {76076#false} assume !(1 == ~T5_E~0); {76076#false} is VALID [2022-02-21 04:24:44,355 INFO L290 TraceCheckUtils]: 128: Hoare triple {76076#false} assume !(1 == ~T6_E~0); {76076#false} is VALID [2022-02-21 04:24:44,356 INFO L290 TraceCheckUtils]: 129: Hoare triple {76076#false} assume !(1 == ~T7_E~0); {76076#false} is VALID [2022-02-21 04:24:44,356 INFO L290 TraceCheckUtils]: 130: Hoare triple {76076#false} assume !(1 == ~T8_E~0); {76076#false} is VALID [2022-02-21 04:24:44,356 INFO L290 TraceCheckUtils]: 131: Hoare triple {76076#false} assume !(1 == ~T9_E~0); {76076#false} is VALID [2022-02-21 04:24:44,356 INFO L290 TraceCheckUtils]: 132: Hoare triple {76076#false} assume !(1 == ~T10_E~0); {76076#false} is VALID [2022-02-21 04:24:44,356 INFO L290 TraceCheckUtils]: 133: Hoare triple {76076#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {76076#false} is VALID [2022-02-21 04:24:44,356 INFO L290 TraceCheckUtils]: 134: Hoare triple {76076#false} assume !(1 == ~T12_E~0); {76076#false} is VALID [2022-02-21 04:24:44,356 INFO L290 TraceCheckUtils]: 135: Hoare triple {76076#false} assume !(1 == ~E_1~0); {76076#false} is VALID [2022-02-21 04:24:44,356 INFO L290 TraceCheckUtils]: 136: Hoare triple {76076#false} assume !(1 == ~E_2~0); {76076#false} is VALID [2022-02-21 04:24:44,357 INFO L290 TraceCheckUtils]: 137: Hoare triple {76076#false} assume !(1 == ~E_3~0); {76076#false} is VALID [2022-02-21 04:24:44,357 INFO L290 TraceCheckUtils]: 138: Hoare triple {76076#false} assume !(1 == ~E_4~0); {76076#false} is VALID [2022-02-21 04:24:44,357 INFO L290 TraceCheckUtils]: 139: Hoare triple {76076#false} assume !(1 == ~E_5~0); {76076#false} is VALID [2022-02-21 04:24:44,357 INFO L290 TraceCheckUtils]: 140: Hoare triple {76076#false} assume !(1 == ~E_6~0); {76076#false} is VALID [2022-02-21 04:24:44,357 INFO L290 TraceCheckUtils]: 141: Hoare triple {76076#false} assume 1 == ~E_7~0;~E_7~0 := 2; {76076#false} is VALID [2022-02-21 04:24:44,357 INFO L290 TraceCheckUtils]: 142: Hoare triple {76076#false} assume !(1 == ~E_8~0); {76076#false} is VALID [2022-02-21 04:24:44,357 INFO L290 TraceCheckUtils]: 143: Hoare triple {76076#false} assume !(1 == ~E_9~0); {76076#false} is VALID [2022-02-21 04:24:44,357 INFO L290 TraceCheckUtils]: 144: Hoare triple {76076#false} assume !(1 == ~E_10~0); {76076#false} is VALID [2022-02-21 04:24:44,358 INFO L290 TraceCheckUtils]: 145: Hoare triple {76076#false} assume !(1 == ~E_11~0); {76076#false} is VALID [2022-02-21 04:24:44,358 INFO L290 TraceCheckUtils]: 146: Hoare triple {76076#false} assume !(1 == ~E_12~0); {76076#false} is VALID [2022-02-21 04:24:44,358 INFO L290 TraceCheckUtils]: 147: Hoare triple {76076#false} assume { :end_inline_reset_delta_events } true; {76076#false} is VALID [2022-02-21 04:24:44,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:44,358 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:44,359 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183180032] [2022-02-21 04:24:44,359 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1183180032] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:44,359 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:44,359 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:44,359 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187657942] [2022-02-21 04:24:44,359 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:44,360 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:44,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:44,360 INFO L85 PathProgramCache]: Analyzing trace with hash -69544993, now seen corresponding path program 1 times [2022-02-21 04:24:44,360 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:44,361 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545123921] [2022-02-21 04:24:44,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:44,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:44,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:44,382 INFO L290 TraceCheckUtils]: 0: Hoare triple {76078#true} assume !false; {76078#true} is VALID [2022-02-21 04:24:44,382 INFO L290 TraceCheckUtils]: 1: Hoare triple {76078#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {76078#true} is VALID [2022-02-21 04:24:44,382 INFO L290 TraceCheckUtils]: 2: Hoare triple {76078#true} assume !false; {76078#true} is VALID [2022-02-21 04:24:44,382 INFO L290 TraceCheckUtils]: 3: Hoare triple {76078#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {76078#true} is VALID [2022-02-21 04:24:44,382 INFO L290 TraceCheckUtils]: 4: Hoare triple {76078#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {76078#true} is VALID [2022-02-21 04:24:44,382 INFO L290 TraceCheckUtils]: 5: Hoare triple {76078#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {76078#true} is VALID [2022-02-21 04:24:44,382 INFO L290 TraceCheckUtils]: 6: Hoare triple {76078#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {76078#true} is VALID [2022-02-21 04:24:44,382 INFO L290 TraceCheckUtils]: 7: Hoare triple {76078#true} assume !(0 != eval_~tmp~0#1); {76078#true} is VALID [2022-02-21 04:24:44,383 INFO L290 TraceCheckUtils]: 8: Hoare triple {76078#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {76078#true} is VALID [2022-02-21 04:24:44,383 INFO L290 TraceCheckUtils]: 9: Hoare triple {76078#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {76078#true} is VALID [2022-02-21 04:24:44,383 INFO L290 TraceCheckUtils]: 10: Hoare triple {76078#true} assume !(0 == ~M_E~0); {76078#true} is VALID [2022-02-21 04:24:44,383 INFO L290 TraceCheckUtils]: 11: Hoare triple {76078#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {76078#true} is VALID [2022-02-21 04:24:44,383 INFO L290 TraceCheckUtils]: 12: Hoare triple {76078#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,383 INFO L290 TraceCheckUtils]: 13: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,384 INFO L290 TraceCheckUtils]: 14: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,384 INFO L290 TraceCheckUtils]: 15: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,384 INFO L290 TraceCheckUtils]: 16: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,385 INFO L290 TraceCheckUtils]: 17: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,385 INFO L290 TraceCheckUtils]: 18: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,385 INFO L290 TraceCheckUtils]: 19: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,385 INFO L290 TraceCheckUtils]: 20: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,386 INFO L290 TraceCheckUtils]: 21: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,386 INFO L290 TraceCheckUtils]: 22: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,386 INFO L290 TraceCheckUtils]: 23: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,386 INFO L290 TraceCheckUtils]: 24: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,387 INFO L290 TraceCheckUtils]: 25: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,387 INFO L290 TraceCheckUtils]: 26: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,387 INFO L290 TraceCheckUtils]: 27: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,388 INFO L290 TraceCheckUtils]: 28: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,388 INFO L290 TraceCheckUtils]: 29: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,388 INFO L290 TraceCheckUtils]: 30: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,389 INFO L290 TraceCheckUtils]: 31: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,389 INFO L290 TraceCheckUtils]: 32: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,389 INFO L290 TraceCheckUtils]: 33: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,390 INFO L290 TraceCheckUtils]: 34: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,390 INFO L290 TraceCheckUtils]: 35: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,390 INFO L290 TraceCheckUtils]: 36: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,391 INFO L290 TraceCheckUtils]: 37: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,391 INFO L290 TraceCheckUtils]: 38: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,391 INFO L290 TraceCheckUtils]: 39: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,392 INFO L290 TraceCheckUtils]: 40: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,392 INFO L290 TraceCheckUtils]: 41: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,392 INFO L290 TraceCheckUtils]: 42: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,393 INFO L290 TraceCheckUtils]: 43: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,393 INFO L290 TraceCheckUtils]: 44: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,393 INFO L290 TraceCheckUtils]: 45: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,394 INFO L290 TraceCheckUtils]: 46: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,394 INFO L290 TraceCheckUtils]: 47: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,394 INFO L290 TraceCheckUtils]: 48: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,395 INFO L290 TraceCheckUtils]: 49: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,395 INFO L290 TraceCheckUtils]: 50: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,396 INFO L290 TraceCheckUtils]: 51: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,396 INFO L290 TraceCheckUtils]: 52: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,396 INFO L290 TraceCheckUtils]: 53: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,397 INFO L290 TraceCheckUtils]: 54: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,397 INFO L290 TraceCheckUtils]: 55: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,397 INFO L290 TraceCheckUtils]: 56: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,398 INFO L290 TraceCheckUtils]: 57: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,398 INFO L290 TraceCheckUtils]: 58: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,398 INFO L290 TraceCheckUtils]: 59: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,398 INFO L290 TraceCheckUtils]: 60: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,399 INFO L290 TraceCheckUtils]: 61: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,399 INFO L290 TraceCheckUtils]: 62: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,399 INFO L290 TraceCheckUtils]: 63: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,400 INFO L290 TraceCheckUtils]: 64: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,400 INFO L290 TraceCheckUtils]: 65: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,400 INFO L290 TraceCheckUtils]: 66: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,401 INFO L290 TraceCheckUtils]: 67: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,401 INFO L290 TraceCheckUtils]: 68: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,401 INFO L290 TraceCheckUtils]: 69: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,402 INFO L290 TraceCheckUtils]: 70: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,402 INFO L290 TraceCheckUtils]: 71: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,402 INFO L290 TraceCheckUtils]: 72: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,403 INFO L290 TraceCheckUtils]: 73: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,403 INFO L290 TraceCheckUtils]: 74: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,403 INFO L290 TraceCheckUtils]: 75: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,404 INFO L290 TraceCheckUtils]: 76: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,404 INFO L290 TraceCheckUtils]: 77: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,404 INFO L290 TraceCheckUtils]: 78: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,405 INFO L290 TraceCheckUtils]: 79: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,405 INFO L290 TraceCheckUtils]: 80: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,405 INFO L290 TraceCheckUtils]: 81: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,406 INFO L290 TraceCheckUtils]: 82: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,406 INFO L290 TraceCheckUtils]: 83: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,406 INFO L290 TraceCheckUtils]: 84: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,407 INFO L290 TraceCheckUtils]: 85: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,407 INFO L290 TraceCheckUtils]: 86: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,407 INFO L290 TraceCheckUtils]: 87: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,408 INFO L290 TraceCheckUtils]: 88: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,408 INFO L290 TraceCheckUtils]: 89: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,408 INFO L290 TraceCheckUtils]: 90: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,409 INFO L290 TraceCheckUtils]: 91: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,409 INFO L290 TraceCheckUtils]: 92: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,409 INFO L290 TraceCheckUtils]: 93: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,410 INFO L290 TraceCheckUtils]: 94: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,410 INFO L290 TraceCheckUtils]: 95: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,410 INFO L290 TraceCheckUtils]: 96: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,411 INFO L290 TraceCheckUtils]: 97: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,411 INFO L290 TraceCheckUtils]: 98: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,411 INFO L290 TraceCheckUtils]: 99: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,411 INFO L290 TraceCheckUtils]: 100: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,412 INFO L290 TraceCheckUtils]: 101: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,412 INFO L290 TraceCheckUtils]: 102: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,412 INFO L290 TraceCheckUtils]: 103: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,413 INFO L290 TraceCheckUtils]: 104: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,413 INFO L290 TraceCheckUtils]: 105: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,413 INFO L290 TraceCheckUtils]: 106: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,414 INFO L290 TraceCheckUtils]: 107: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,414 INFO L290 TraceCheckUtils]: 108: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t12_pc~0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,414 INFO L290 TraceCheckUtils]: 109: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,415 INFO L290 TraceCheckUtils]: 110: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,415 INFO L290 TraceCheckUtils]: 111: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,415 INFO L290 TraceCheckUtils]: 112: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,416 INFO L290 TraceCheckUtils]: 113: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,416 INFO L290 TraceCheckUtils]: 114: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,416 INFO L290 TraceCheckUtils]: 115: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {76080#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:44,417 INFO L290 TraceCheckUtils]: 116: Hoare triple {76080#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {76079#false} is VALID [2022-02-21 04:24:44,417 INFO L290 TraceCheckUtils]: 117: Hoare triple {76079#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,417 INFO L290 TraceCheckUtils]: 118: Hoare triple {76079#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,417 INFO L290 TraceCheckUtils]: 119: Hoare triple {76079#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,417 INFO L290 TraceCheckUtils]: 120: Hoare triple {76079#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,417 INFO L290 TraceCheckUtils]: 121: Hoare triple {76079#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,417 INFO L290 TraceCheckUtils]: 122: Hoare triple {76079#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,418 INFO L290 TraceCheckUtils]: 123: Hoare triple {76079#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,418 INFO L290 TraceCheckUtils]: 124: Hoare triple {76079#false} assume !(1 == ~T10_E~0); {76079#false} is VALID [2022-02-21 04:24:44,418 INFO L290 TraceCheckUtils]: 125: Hoare triple {76079#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,418 INFO L290 TraceCheckUtils]: 126: Hoare triple {76079#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,418 INFO L290 TraceCheckUtils]: 127: Hoare triple {76079#false} assume 1 == ~E_1~0;~E_1~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,418 INFO L290 TraceCheckUtils]: 128: Hoare triple {76079#false} assume 1 == ~E_2~0;~E_2~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,418 INFO L290 TraceCheckUtils]: 129: Hoare triple {76079#false} assume 1 == ~E_3~0;~E_3~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,418 INFO L290 TraceCheckUtils]: 130: Hoare triple {76079#false} assume 1 == ~E_4~0;~E_4~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,419 INFO L290 TraceCheckUtils]: 131: Hoare triple {76079#false} assume 1 == ~E_5~0;~E_5~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,419 INFO L290 TraceCheckUtils]: 132: Hoare triple {76079#false} assume !(1 == ~E_6~0); {76079#false} is VALID [2022-02-21 04:24:44,419 INFO L290 TraceCheckUtils]: 133: Hoare triple {76079#false} assume 1 == ~E_7~0;~E_7~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,421 INFO L290 TraceCheckUtils]: 134: Hoare triple {76079#false} assume 1 == ~E_8~0;~E_8~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,421 INFO L290 TraceCheckUtils]: 135: Hoare triple {76079#false} assume 1 == ~E_9~0;~E_9~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,421 INFO L290 TraceCheckUtils]: 136: Hoare triple {76079#false} assume 1 == ~E_10~0;~E_10~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,421 INFO L290 TraceCheckUtils]: 137: Hoare triple {76079#false} assume 1 == ~E_11~0;~E_11~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,421 INFO L290 TraceCheckUtils]: 138: Hoare triple {76079#false} assume 1 == ~E_12~0;~E_12~0 := 2; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 139: Hoare triple {76079#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 140: Hoare triple {76079#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 141: Hoare triple {76079#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 142: Hoare triple {76079#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 143: Hoare triple {76079#false} assume !(0 == start_simulation_~tmp~3#1); {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 144: Hoare triple {76079#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 145: Hoare triple {76079#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 146: Hoare triple {76079#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 147: Hoare triple {76079#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 148: Hoare triple {76079#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 149: Hoare triple {76079#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 150: Hoare triple {76079#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {76079#false} is VALID [2022-02-21 04:24:44,422 INFO L290 TraceCheckUtils]: 151: Hoare triple {76079#false} assume !(0 != start_simulation_~tmp___0~1#1); {76079#false} is VALID [2022-02-21 04:24:44,426 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:44,427 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:44,427 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545123921] [2022-02-21 04:24:44,427 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545123921] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:44,427 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:44,427 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:44,427 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [427797434] [2022-02-21 04:24:44,427 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:44,427 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:44,427 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:44,428 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:44,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:44,428 INFO L87 Difference]: Start difference. First operand 1688 states and 2494 transitions. cyclomatic complexity: 807 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:45,483 INFO L93 Difference]: Finished difference Result 1688 states and 2493 transitions. [2022-02-21 04:24:45,483 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:45,483 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,620 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:45,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2493 transitions. [2022-02-21 04:24:45,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:45,863 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2493 transitions. [2022-02-21 04:24:45,863 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:45,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:45,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2493 transitions. [2022-02-21 04:24:45,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:45,866 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2022-02-21 04:24:45,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2493 transitions. [2022-02-21 04:24:45,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:45,887 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:45,889 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2493 transitions. Second operand has 1688 states, 1688 states have (on average 1.4768957345971565) internal successors, (2493), 1687 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,891 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2493 transitions. Second operand has 1688 states, 1688 states have (on average 1.4768957345971565) internal successors, (2493), 1687 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,892 INFO L87 Difference]: Start difference. First operand 1688 states and 2493 transitions. Second operand has 1688 states, 1688 states have (on average 1.4768957345971565) internal successors, (2493), 1687 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:45,996 INFO L93 Difference]: Finished difference Result 1688 states and 2493 transitions. [2022-02-21 04:24:45,996 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2493 transitions. [2022-02-21 04:24:45,998 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:45,998 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:46,001 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.4768957345971565) internal successors, (2493), 1687 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2493 transitions. [2022-02-21 04:24:46,003 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.4768957345971565) internal successors, (2493), 1687 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2493 transitions. [2022-02-21 04:24:46,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:46,103 INFO L93 Difference]: Finished difference Result 1688 states and 2493 transitions. [2022-02-21 04:24:46,103 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2493 transitions. [2022-02-21 04:24:46,105 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:46,105 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:46,106 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:46,106 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:46,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4768957345971565) internal successors, (2493), 1687 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:46,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2493 transitions. [2022-02-21 04:24:46,208 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2022-02-21 04:24:46,208 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2493 transitions. [2022-02-21 04:24:46,208 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:24:46,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2493 transitions. [2022-02-21 04:24:46,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:46,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:46,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:46,214 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:46,214 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:46,215 INFO L791 eck$LassoCheckResult]: Stem: 78572#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 78573#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 79426#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 78918#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78725#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 78726#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 78811#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79112#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79234#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 79235#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78023#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 78024#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 79172#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 78618#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 78619#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 78525#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 78526#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 78914#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 78267#L1174 assume !(0 == ~M_E~0); 78268#L1174-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78119#L1179-1 assume !(0 == ~T2_E~0); 78021#L1184-1 assume !(0 == ~T3_E~0); 78022#L1189-1 assume !(0 == ~T4_E~0); 78060#L1194-1 assume !(0 == ~T5_E~0); 78160#L1199-1 assume !(0 == ~T6_E~0); 79055#L1204-1 assume !(0 == ~T7_E~0); 78974#L1209-1 assume !(0 == ~T8_E~0); 78975#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 79363#L1219-1 assume !(0 == ~T10_E~0); 79448#L1224-1 assume !(0 == ~T11_E~0); 78385#L1229-1 assume !(0 == ~T12_E~0); 77946#L1234-1 assume !(0 == ~E_1~0); 77947#L1239-1 assume !(0 == ~E_2~0); 77980#L1244-1 assume !(0 == ~E_3~0); 77981#L1249-1 assume !(0 == ~E_4~0); 78642#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 77876#L1259-1 assume !(0 == ~E_6~0); 77831#L1264-1 assume !(0 == ~E_7~0); 77832#L1269-1 assume !(0 == ~E_8~0); 79453#L1274-1 assume !(0 == ~E_9~0); 79388#L1279-1 assume !(0 == ~E_10~0); 78064#L1284-1 assume !(0 == ~E_11~0); 78065#L1289-1 assume !(0 == ~E_12~0); 78694#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78695#L566 assume 1 == ~m_pc~0; 77848#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 77849#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79003#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 79004#L1455 assume !(0 != activate_threads_~tmp~1#1); 78294#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78295#L585 assume 1 == ~t1_pc~0; 77943#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77944#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78944#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78945#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 79413#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79411#L604 assume !(1 == ~t2_pc~0); 79023#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 79024#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78557#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78558#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79195#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79196#L623 assume 1 == ~t3_pc~0; 78472#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77812#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78622#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78623#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 79230#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77845#L642 assume !(1 == ~t4_pc~0); 77846#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 78311#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78312#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77917#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 77918#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79035#L661 assume 1 == ~t5_pc~0; 78082#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 78083#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78044#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78045#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 79064#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79065#L680 assume !(1 == ~t6_pc~0); 78505#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 78506#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78767#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78768#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 79296#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 79409#L699 assume 1 == ~t7_pc~0; 78895#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 78896#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78072#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78073#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 78797#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78696#L718 assume !(1 == ~t8_pc~0); 78697#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 78058#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78059#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78100#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 78101#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78234#L737 assume 1 == ~t9_pc~0; 79099#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 78369#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78970#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 78971#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 78543#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78544#L756 assume 1 == ~t10_pc~0; 79123#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 78789#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77775#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77776#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 78351#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 78352#L775 assume !(1 == ~t11_pc~0); 78606#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 78607#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78228#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77992#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 77993#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78179#L794 assume 1 == ~t12_pc~0; 78019#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 77997#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 79190#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 78145#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 78146#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78625#L1307 assume !(1 == ~M_E~0); 78626#L1307-2 assume !(1 == ~T1_E~0); 78737#L1312-1 assume !(1 == ~T2_E~0); 78656#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78657#L1322-1 assume !(1 == ~T4_E~0); 78360#L1327-1 assume !(1 == ~T5_E~0); 78361#L1332-1 assume !(1 == ~T6_E~0); 78899#L1337-1 assume !(1 == ~T7_E~0); 78861#L1342-1 assume !(1 == ~T8_E~0); 78862#L1347-1 assume !(1 == ~T9_E~0); 79259#L1352-1 assume !(1 == ~T10_E~0); 79132#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78523#L1362-1 assume !(1 == ~T12_E~0); 78524#L1367-1 assume !(1 == ~E_1~0); 78161#L1372-1 assume !(1 == ~E_2~0); 78162#L1377-1 assume !(1 == ~E_3~0); 78455#L1382-1 assume !(1 == ~E_4~0); 78456#L1387-1 assume !(1 == ~E_5~0); 79025#L1392-1 assume !(1 == ~E_6~0); 78475#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 78476#L1402-1 assume !(1 == ~E_8~0); 78172#L1407-1 assume !(1 == ~E_9~0); 78173#L1412-1 assume !(1 == ~E_10~0); 79188#L1417-1 assume !(1 == ~E_11~0); 79189#L1422-1 assume !(1 == ~E_12~0); 79407#L1427-1 assume { :end_inline_reset_delta_events } true; 77976#L1768-2 [2022-02-21 04:24:46,215 INFO L793 eck$LassoCheckResult]: Loop: 77976#L1768-2 assume !false; 77977#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 78715#L1149 assume !false; 79087#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 79240#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78366#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78272#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 78273#L976 assume !(0 != eval_~tmp~0#1); 79406#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 79416#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 79207#L1174-3 assume !(0 == ~M_E~0); 79200#L1174-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78949#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 78950#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79133#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 78784#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78134#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 78135#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 78376#L1209-3 assume !(0 == ~T8_E~0); 77796#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 77797#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 78555#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 78556#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 78574#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 77984#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 77985#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78428#L1249-3 assume !(0 == ~E_4~0); 78887#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79359#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 79001#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 77990#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 77991#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 79386#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 78553#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 78554#L1289-3 assume !(0 == ~E_12~0); 78542#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78218#L566-39 assume 1 == ~m_pc~0; 78219#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 78821#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78533#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 78534#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 79076#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79077#L585-39 assume 1 == ~t1_pc~0; 79187#L586-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 78227#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78302#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78303#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 79109#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78802#L604-39 assume 1 == ~t2_pc~0; 78803#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78434#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78435#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78852#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 78853#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78417#L623-39 assume 1 == ~t3_pc~0; 77813#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 77815#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79093#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78269#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78270#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79041#L642-39 assume 1 == ~t4_pc~0; 78612#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78613#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78141#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78142#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 79239#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78190#L661-39 assume !(1 == ~t5_pc~0); 77821#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 77822#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79182#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79183#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 79096#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79097#L680-39 assume 1 == ~t6_pc~0; 77883#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77884#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 79026#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78349#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78350#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 79364#L699-39 assume !(1 == ~t7_pc~0); 78787#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 78508#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78509#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 79192#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 79313#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 79311#L718-39 assume 1 == ~t8_pc~0; 78700#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 78701#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78633#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78634#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 78936#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78905#L737-39 assume 1 == ~t9_pc~0; 78330#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 78331#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78620#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 79387#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 79288#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 79231#L756-39 assume 1 == ~t10_pc~0; 79232#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 78713#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78457#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 78458#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 78590#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77930#L775-39 assume 1 == ~t11_pc~0; 77931#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 78583#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 78584#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 79446#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 78994#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 78641#L794-39 assume !(1 == ~t12_pc~0); 78326#L794-41 is_transmit12_triggered_~__retres1~12#1 := 0; 78327#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 79147#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 79048#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 77872#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77873#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 79340#L1307-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 79341#L1312-3 assume !(1 == ~T2_E~0); 79452#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 79066#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 79067#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78011#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77982#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 77983#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 78729#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78854#L1352-3 assume !(1 == ~T10_E~0); 78855#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 79294#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 79445#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 79436#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77809#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77810#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78441#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78442#L1392-3 assume !(1 == ~E_6~0); 79157#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 79403#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 78820#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78096#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 78097#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78745#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 78746#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 78106#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78107#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78973#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 78825#L1787 assume !(0 == start_simulation_~tmp~3#1); 78826#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 79349#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 78077#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 78872#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 78873#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 78424#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 78425#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 78426#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 77976#L1768-2 [2022-02-21 04:24:46,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:46,216 INFO L85 PathProgramCache]: Analyzing trace with hash -1368382701, now seen corresponding path program 1 times [2022-02-21 04:24:46,216 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:46,216 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415294913] [2022-02-21 04:24:46,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:46,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:46,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:46,260 INFO L290 TraceCheckUtils]: 0: Hoare triple {82836#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,261 INFO L290 TraceCheckUtils]: 1: Hoare triple {82838#(<= 2 ~T1_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,261 INFO L290 TraceCheckUtils]: 2: Hoare triple {82838#(<= 2 ~T1_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,262 INFO L290 TraceCheckUtils]: 3: Hoare triple {82838#(<= 2 ~T1_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,262 INFO L290 TraceCheckUtils]: 4: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,262 INFO L290 TraceCheckUtils]: 5: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,263 INFO L290 TraceCheckUtils]: 6: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,263 INFO L290 TraceCheckUtils]: 7: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,263 INFO L290 TraceCheckUtils]: 8: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,264 INFO L290 TraceCheckUtils]: 9: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,264 INFO L290 TraceCheckUtils]: 10: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,264 INFO L290 TraceCheckUtils]: 11: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,265 INFO L290 TraceCheckUtils]: 12: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,265 INFO L290 TraceCheckUtils]: 13: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,265 INFO L290 TraceCheckUtils]: 14: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,266 INFO L290 TraceCheckUtils]: 15: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,266 INFO L290 TraceCheckUtils]: 16: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,266 INFO L290 TraceCheckUtils]: 17: Hoare triple {82838#(<= 2 ~T1_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,266 INFO L290 TraceCheckUtils]: 18: Hoare triple {82838#(<= 2 ~T1_E~0)} assume !(0 == ~M_E~0); {82838#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:24:46,267 INFO L290 TraceCheckUtils]: 19: Hoare triple {82838#(<= 2 ~T1_E~0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {82837#false} is VALID [2022-02-21 04:24:46,267 INFO L290 TraceCheckUtils]: 20: Hoare triple {82837#false} assume !(0 == ~T2_E~0); {82837#false} is VALID [2022-02-21 04:24:46,267 INFO L290 TraceCheckUtils]: 21: Hoare triple {82837#false} assume !(0 == ~T3_E~0); {82837#false} is VALID [2022-02-21 04:24:46,267 INFO L290 TraceCheckUtils]: 22: Hoare triple {82837#false} assume !(0 == ~T4_E~0); {82837#false} is VALID [2022-02-21 04:24:46,267 INFO L290 TraceCheckUtils]: 23: Hoare triple {82837#false} assume !(0 == ~T5_E~0); {82837#false} is VALID [2022-02-21 04:24:46,268 INFO L290 TraceCheckUtils]: 24: Hoare triple {82837#false} assume !(0 == ~T6_E~0); {82837#false} is VALID [2022-02-21 04:24:46,268 INFO L290 TraceCheckUtils]: 25: Hoare triple {82837#false} assume !(0 == ~T7_E~0); {82837#false} is VALID [2022-02-21 04:24:46,268 INFO L290 TraceCheckUtils]: 26: Hoare triple {82837#false} assume !(0 == ~T8_E~0); {82837#false} is VALID [2022-02-21 04:24:46,268 INFO L290 TraceCheckUtils]: 27: Hoare triple {82837#false} assume 0 == ~T9_E~0;~T9_E~0 := 1; {82837#false} is VALID [2022-02-21 04:24:46,268 INFO L290 TraceCheckUtils]: 28: Hoare triple {82837#false} assume !(0 == ~T10_E~0); {82837#false} is VALID [2022-02-21 04:24:46,268 INFO L290 TraceCheckUtils]: 29: Hoare triple {82837#false} assume !(0 == ~T11_E~0); {82837#false} is VALID [2022-02-21 04:24:46,268 INFO L290 TraceCheckUtils]: 30: Hoare triple {82837#false} assume !(0 == ~T12_E~0); {82837#false} is VALID [2022-02-21 04:24:46,268 INFO L290 TraceCheckUtils]: 31: Hoare triple {82837#false} assume !(0 == ~E_1~0); {82837#false} is VALID [2022-02-21 04:24:46,269 INFO L290 TraceCheckUtils]: 32: Hoare triple {82837#false} assume !(0 == ~E_2~0); {82837#false} is VALID [2022-02-21 04:24:46,269 INFO L290 TraceCheckUtils]: 33: Hoare triple {82837#false} assume !(0 == ~E_3~0); {82837#false} is VALID [2022-02-21 04:24:46,269 INFO L290 TraceCheckUtils]: 34: Hoare triple {82837#false} assume !(0 == ~E_4~0); {82837#false} is VALID [2022-02-21 04:24:46,269 INFO L290 TraceCheckUtils]: 35: Hoare triple {82837#false} assume 0 == ~E_5~0;~E_5~0 := 1; {82837#false} is VALID [2022-02-21 04:24:46,269 INFO L290 TraceCheckUtils]: 36: Hoare triple {82837#false} assume !(0 == ~E_6~0); {82837#false} is VALID [2022-02-21 04:24:46,269 INFO L290 TraceCheckUtils]: 37: Hoare triple {82837#false} assume !(0 == ~E_7~0); {82837#false} is VALID [2022-02-21 04:24:46,269 INFO L290 TraceCheckUtils]: 38: Hoare triple {82837#false} assume !(0 == ~E_8~0); {82837#false} is VALID [2022-02-21 04:24:46,270 INFO L290 TraceCheckUtils]: 39: Hoare triple {82837#false} assume !(0 == ~E_9~0); {82837#false} is VALID [2022-02-21 04:24:46,270 INFO L290 TraceCheckUtils]: 40: Hoare triple {82837#false} assume !(0 == ~E_10~0); {82837#false} is VALID [2022-02-21 04:24:46,270 INFO L290 TraceCheckUtils]: 41: Hoare triple {82837#false} assume !(0 == ~E_11~0); {82837#false} is VALID [2022-02-21 04:24:46,270 INFO L290 TraceCheckUtils]: 42: Hoare triple {82837#false} assume !(0 == ~E_12~0); {82837#false} is VALID [2022-02-21 04:24:46,270 INFO L290 TraceCheckUtils]: 43: Hoare triple {82837#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {82837#false} is VALID [2022-02-21 04:24:46,270 INFO L290 TraceCheckUtils]: 44: Hoare triple {82837#false} assume 1 == ~m_pc~0; {82837#false} is VALID [2022-02-21 04:24:46,270 INFO L290 TraceCheckUtils]: 45: Hoare triple {82837#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {82837#false} is VALID [2022-02-21 04:24:46,271 INFO L290 TraceCheckUtils]: 46: Hoare triple {82837#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {82837#false} is VALID [2022-02-21 04:24:46,271 INFO L290 TraceCheckUtils]: 47: Hoare triple {82837#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {82837#false} is VALID [2022-02-21 04:24:46,271 INFO L290 TraceCheckUtils]: 48: Hoare triple {82837#false} assume !(0 != activate_threads_~tmp~1#1); {82837#false} is VALID [2022-02-21 04:24:46,271 INFO L290 TraceCheckUtils]: 49: Hoare triple {82837#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {82837#false} is VALID [2022-02-21 04:24:46,271 INFO L290 TraceCheckUtils]: 50: Hoare triple {82837#false} assume 1 == ~t1_pc~0; {82837#false} is VALID [2022-02-21 04:24:46,271 INFO L290 TraceCheckUtils]: 51: Hoare triple {82837#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {82837#false} is VALID [2022-02-21 04:24:46,271 INFO L290 TraceCheckUtils]: 52: Hoare triple {82837#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {82837#false} is VALID [2022-02-21 04:24:46,272 INFO L290 TraceCheckUtils]: 53: Hoare triple {82837#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {82837#false} is VALID [2022-02-21 04:24:46,272 INFO L290 TraceCheckUtils]: 54: Hoare triple {82837#false} assume !(0 != activate_threads_~tmp___0~0#1); {82837#false} is VALID [2022-02-21 04:24:46,272 INFO L290 TraceCheckUtils]: 55: Hoare triple {82837#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {82837#false} is VALID [2022-02-21 04:24:46,272 INFO L290 TraceCheckUtils]: 56: Hoare triple {82837#false} assume !(1 == ~t2_pc~0); {82837#false} is VALID [2022-02-21 04:24:46,272 INFO L290 TraceCheckUtils]: 57: Hoare triple {82837#false} is_transmit2_triggered_~__retres1~2#1 := 0; {82837#false} is VALID [2022-02-21 04:24:46,272 INFO L290 TraceCheckUtils]: 58: Hoare triple {82837#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {82837#false} is VALID [2022-02-21 04:24:46,272 INFO L290 TraceCheckUtils]: 59: Hoare triple {82837#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {82837#false} is VALID [2022-02-21 04:24:46,272 INFO L290 TraceCheckUtils]: 60: Hoare triple {82837#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {82837#false} is VALID [2022-02-21 04:24:46,273 INFO L290 TraceCheckUtils]: 61: Hoare triple {82837#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {82837#false} is VALID [2022-02-21 04:24:46,273 INFO L290 TraceCheckUtils]: 62: Hoare triple {82837#false} assume 1 == ~t3_pc~0; {82837#false} is VALID [2022-02-21 04:24:46,273 INFO L290 TraceCheckUtils]: 63: Hoare triple {82837#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {82837#false} is VALID [2022-02-21 04:24:46,273 INFO L290 TraceCheckUtils]: 64: Hoare triple {82837#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {82837#false} is VALID [2022-02-21 04:24:46,273 INFO L290 TraceCheckUtils]: 65: Hoare triple {82837#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {82837#false} is VALID [2022-02-21 04:24:46,273 INFO L290 TraceCheckUtils]: 66: Hoare triple {82837#false} assume !(0 != activate_threads_~tmp___2~0#1); {82837#false} is VALID [2022-02-21 04:24:46,273 INFO L290 TraceCheckUtils]: 67: Hoare triple {82837#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {82837#false} is VALID [2022-02-21 04:24:46,274 INFO L290 TraceCheckUtils]: 68: Hoare triple {82837#false} assume !(1 == ~t4_pc~0); {82837#false} is VALID [2022-02-21 04:24:46,274 INFO L290 TraceCheckUtils]: 69: Hoare triple {82837#false} is_transmit4_triggered_~__retres1~4#1 := 0; {82837#false} is VALID [2022-02-21 04:24:46,274 INFO L290 TraceCheckUtils]: 70: Hoare triple {82837#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {82837#false} is VALID [2022-02-21 04:24:46,274 INFO L290 TraceCheckUtils]: 71: Hoare triple {82837#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {82837#false} is VALID [2022-02-21 04:24:46,274 INFO L290 TraceCheckUtils]: 72: Hoare triple {82837#false} assume !(0 != activate_threads_~tmp___3~0#1); {82837#false} is VALID [2022-02-21 04:24:46,274 INFO L290 TraceCheckUtils]: 73: Hoare triple {82837#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {82837#false} is VALID [2022-02-21 04:24:46,274 INFO L290 TraceCheckUtils]: 74: Hoare triple {82837#false} assume 1 == ~t5_pc~0; {82837#false} is VALID [2022-02-21 04:24:46,275 INFO L290 TraceCheckUtils]: 75: Hoare triple {82837#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {82837#false} is VALID [2022-02-21 04:24:46,275 INFO L290 TraceCheckUtils]: 76: Hoare triple {82837#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {82837#false} is VALID [2022-02-21 04:24:46,275 INFO L290 TraceCheckUtils]: 77: Hoare triple {82837#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {82837#false} is VALID [2022-02-21 04:24:46,275 INFO L290 TraceCheckUtils]: 78: Hoare triple {82837#false} assume !(0 != activate_threads_~tmp___4~0#1); {82837#false} is VALID [2022-02-21 04:24:46,275 INFO L290 TraceCheckUtils]: 79: Hoare triple {82837#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {82837#false} is VALID [2022-02-21 04:24:46,275 INFO L290 TraceCheckUtils]: 80: Hoare triple {82837#false} assume !(1 == ~t6_pc~0); {82837#false} is VALID [2022-02-21 04:24:46,275 INFO L290 TraceCheckUtils]: 81: Hoare triple {82837#false} is_transmit6_triggered_~__retres1~6#1 := 0; {82837#false} is VALID [2022-02-21 04:24:46,275 INFO L290 TraceCheckUtils]: 82: Hoare triple {82837#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {82837#false} is VALID [2022-02-21 04:24:46,276 INFO L290 TraceCheckUtils]: 83: Hoare triple {82837#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {82837#false} is VALID [2022-02-21 04:24:46,276 INFO L290 TraceCheckUtils]: 84: Hoare triple {82837#false} assume !(0 != activate_threads_~tmp___5~0#1); {82837#false} is VALID [2022-02-21 04:24:46,276 INFO L290 TraceCheckUtils]: 85: Hoare triple {82837#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {82837#false} is VALID [2022-02-21 04:24:46,276 INFO L290 TraceCheckUtils]: 86: Hoare triple {82837#false} assume 1 == ~t7_pc~0; {82837#false} is VALID [2022-02-21 04:24:46,276 INFO L290 TraceCheckUtils]: 87: Hoare triple {82837#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {82837#false} is VALID [2022-02-21 04:24:46,276 INFO L290 TraceCheckUtils]: 88: Hoare triple {82837#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {82837#false} is VALID [2022-02-21 04:24:46,276 INFO L290 TraceCheckUtils]: 89: Hoare triple {82837#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {82837#false} is VALID [2022-02-21 04:24:46,277 INFO L290 TraceCheckUtils]: 90: Hoare triple {82837#false} assume !(0 != activate_threads_~tmp___6~0#1); {82837#false} is VALID [2022-02-21 04:24:46,277 INFO L290 TraceCheckUtils]: 91: Hoare triple {82837#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {82837#false} is VALID [2022-02-21 04:24:46,277 INFO L290 TraceCheckUtils]: 92: Hoare triple {82837#false} assume !(1 == ~t8_pc~0); {82837#false} is VALID [2022-02-21 04:24:46,277 INFO L290 TraceCheckUtils]: 93: Hoare triple {82837#false} is_transmit8_triggered_~__retres1~8#1 := 0; {82837#false} is VALID [2022-02-21 04:24:46,277 INFO L290 TraceCheckUtils]: 94: Hoare triple {82837#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {82837#false} is VALID [2022-02-21 04:24:46,277 INFO L290 TraceCheckUtils]: 95: Hoare triple {82837#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {82837#false} is VALID [2022-02-21 04:24:46,278 INFO L290 TraceCheckUtils]: 96: Hoare triple {82837#false} assume !(0 != activate_threads_~tmp___7~0#1); {82837#false} is VALID [2022-02-21 04:24:46,278 INFO L290 TraceCheckUtils]: 97: Hoare triple {82837#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {82837#false} is VALID [2022-02-21 04:24:46,278 INFO L290 TraceCheckUtils]: 98: Hoare triple {82837#false} assume 1 == ~t9_pc~0; {82837#false} is VALID [2022-02-21 04:24:46,278 INFO L290 TraceCheckUtils]: 99: Hoare triple {82837#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {82837#false} is VALID [2022-02-21 04:24:46,278 INFO L290 TraceCheckUtils]: 100: Hoare triple {82837#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {82837#false} is VALID [2022-02-21 04:24:46,278 INFO L290 TraceCheckUtils]: 101: Hoare triple {82837#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {82837#false} is VALID [2022-02-21 04:24:46,278 INFO L290 TraceCheckUtils]: 102: Hoare triple {82837#false} assume !(0 != activate_threads_~tmp___8~0#1); {82837#false} is VALID [2022-02-21 04:24:46,278 INFO L290 TraceCheckUtils]: 103: Hoare triple {82837#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {82837#false} is VALID [2022-02-21 04:24:46,279 INFO L290 TraceCheckUtils]: 104: Hoare triple {82837#false} assume 1 == ~t10_pc~0; {82837#false} is VALID [2022-02-21 04:24:46,279 INFO L290 TraceCheckUtils]: 105: Hoare triple {82837#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {82837#false} is VALID [2022-02-21 04:24:46,279 INFO L290 TraceCheckUtils]: 106: Hoare triple {82837#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {82837#false} is VALID [2022-02-21 04:24:46,279 INFO L290 TraceCheckUtils]: 107: Hoare triple {82837#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {82837#false} is VALID [2022-02-21 04:24:46,279 INFO L290 TraceCheckUtils]: 108: Hoare triple {82837#false} assume !(0 != activate_threads_~tmp___9~0#1); {82837#false} is VALID [2022-02-21 04:24:46,279 INFO L290 TraceCheckUtils]: 109: Hoare triple {82837#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {82837#false} is VALID [2022-02-21 04:24:46,279 INFO L290 TraceCheckUtils]: 110: Hoare triple {82837#false} assume !(1 == ~t11_pc~0); {82837#false} is VALID [2022-02-21 04:24:46,280 INFO L290 TraceCheckUtils]: 111: Hoare triple {82837#false} is_transmit11_triggered_~__retres1~11#1 := 0; {82837#false} is VALID [2022-02-21 04:24:46,280 INFO L290 TraceCheckUtils]: 112: Hoare triple {82837#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {82837#false} is VALID [2022-02-21 04:24:46,280 INFO L290 TraceCheckUtils]: 113: Hoare triple {82837#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {82837#false} is VALID [2022-02-21 04:24:46,280 INFO L290 TraceCheckUtils]: 114: Hoare triple {82837#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {82837#false} is VALID [2022-02-21 04:24:46,280 INFO L290 TraceCheckUtils]: 115: Hoare triple {82837#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {82837#false} is VALID [2022-02-21 04:24:46,280 INFO L290 TraceCheckUtils]: 116: Hoare triple {82837#false} assume 1 == ~t12_pc~0; {82837#false} is VALID [2022-02-21 04:24:46,280 INFO L290 TraceCheckUtils]: 117: Hoare triple {82837#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {82837#false} is VALID [2022-02-21 04:24:46,281 INFO L290 TraceCheckUtils]: 118: Hoare triple {82837#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {82837#false} is VALID [2022-02-21 04:24:46,281 INFO L290 TraceCheckUtils]: 119: Hoare triple {82837#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {82837#false} is VALID [2022-02-21 04:24:46,281 INFO L290 TraceCheckUtils]: 120: Hoare triple {82837#false} assume !(0 != activate_threads_~tmp___11~0#1); {82837#false} is VALID [2022-02-21 04:24:46,281 INFO L290 TraceCheckUtils]: 121: Hoare triple {82837#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {82837#false} is VALID [2022-02-21 04:24:46,281 INFO L290 TraceCheckUtils]: 122: Hoare triple {82837#false} assume !(1 == ~M_E~0); {82837#false} is VALID [2022-02-21 04:24:46,281 INFO L290 TraceCheckUtils]: 123: Hoare triple {82837#false} assume !(1 == ~T1_E~0); {82837#false} is VALID [2022-02-21 04:24:46,281 INFO L290 TraceCheckUtils]: 124: Hoare triple {82837#false} assume !(1 == ~T2_E~0); {82837#false} is VALID [2022-02-21 04:24:46,281 INFO L290 TraceCheckUtils]: 125: Hoare triple {82837#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {82837#false} is VALID [2022-02-21 04:24:46,282 INFO L290 TraceCheckUtils]: 126: Hoare triple {82837#false} assume !(1 == ~T4_E~0); {82837#false} is VALID [2022-02-21 04:24:46,282 INFO L290 TraceCheckUtils]: 127: Hoare triple {82837#false} assume !(1 == ~T5_E~0); {82837#false} is VALID [2022-02-21 04:24:46,282 INFO L290 TraceCheckUtils]: 128: Hoare triple {82837#false} assume !(1 == ~T6_E~0); {82837#false} is VALID [2022-02-21 04:24:46,282 INFO L290 TraceCheckUtils]: 129: Hoare triple {82837#false} assume !(1 == ~T7_E~0); {82837#false} is VALID [2022-02-21 04:24:46,282 INFO L290 TraceCheckUtils]: 130: Hoare triple {82837#false} assume !(1 == ~T8_E~0); {82837#false} is VALID [2022-02-21 04:24:46,282 INFO L290 TraceCheckUtils]: 131: Hoare triple {82837#false} assume !(1 == ~T9_E~0); {82837#false} is VALID [2022-02-21 04:24:46,282 INFO L290 TraceCheckUtils]: 132: Hoare triple {82837#false} assume !(1 == ~T10_E~0); {82837#false} is VALID [2022-02-21 04:24:46,283 INFO L290 TraceCheckUtils]: 133: Hoare triple {82837#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {82837#false} is VALID [2022-02-21 04:24:46,283 INFO L290 TraceCheckUtils]: 134: Hoare triple {82837#false} assume !(1 == ~T12_E~0); {82837#false} is VALID [2022-02-21 04:24:46,283 INFO L290 TraceCheckUtils]: 135: Hoare triple {82837#false} assume !(1 == ~E_1~0); {82837#false} is VALID [2022-02-21 04:24:46,283 INFO L290 TraceCheckUtils]: 136: Hoare triple {82837#false} assume !(1 == ~E_2~0); {82837#false} is VALID [2022-02-21 04:24:46,283 INFO L290 TraceCheckUtils]: 137: Hoare triple {82837#false} assume !(1 == ~E_3~0); {82837#false} is VALID [2022-02-21 04:24:46,283 INFO L290 TraceCheckUtils]: 138: Hoare triple {82837#false} assume !(1 == ~E_4~0); {82837#false} is VALID [2022-02-21 04:24:46,284 INFO L290 TraceCheckUtils]: 139: Hoare triple {82837#false} assume !(1 == ~E_5~0); {82837#false} is VALID [2022-02-21 04:24:46,284 INFO L290 TraceCheckUtils]: 140: Hoare triple {82837#false} assume !(1 == ~E_6~0); {82837#false} is VALID [2022-02-21 04:24:46,284 INFO L290 TraceCheckUtils]: 141: Hoare triple {82837#false} assume 1 == ~E_7~0;~E_7~0 := 2; {82837#false} is VALID [2022-02-21 04:24:46,284 INFO L290 TraceCheckUtils]: 142: Hoare triple {82837#false} assume !(1 == ~E_8~0); {82837#false} is VALID [2022-02-21 04:24:46,284 INFO L290 TraceCheckUtils]: 143: Hoare triple {82837#false} assume !(1 == ~E_9~0); {82837#false} is VALID [2022-02-21 04:24:46,285 INFO L290 TraceCheckUtils]: 144: Hoare triple {82837#false} assume !(1 == ~E_10~0); {82837#false} is VALID [2022-02-21 04:24:46,285 INFO L290 TraceCheckUtils]: 145: Hoare triple {82837#false} assume !(1 == ~E_11~0); {82837#false} is VALID [2022-02-21 04:24:46,285 INFO L290 TraceCheckUtils]: 146: Hoare triple {82837#false} assume !(1 == ~E_12~0); {82837#false} is VALID [2022-02-21 04:24:46,285 INFO L290 TraceCheckUtils]: 147: Hoare triple {82837#false} assume { :end_inline_reset_delta_events } true; {82837#false} is VALID [2022-02-21 04:24:46,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:46,286 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:46,286 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415294913] [2022-02-21 04:24:46,286 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415294913] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:46,286 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:46,286 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:46,286 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [11071128] [2022-02-21 04:24:46,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:46,288 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:46,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:46,288 INFO L85 PathProgramCache]: Analyzing trace with hash -1772306174, now seen corresponding path program 1 times [2022-02-21 04:24:46,289 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:46,289 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1747701639] [2022-02-21 04:24:46,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:46,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:46,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:46,331 INFO L290 TraceCheckUtils]: 0: Hoare triple {82839#true} assume !false; {82839#true} is VALID [2022-02-21 04:24:46,331 INFO L290 TraceCheckUtils]: 1: Hoare triple {82839#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {82839#true} is VALID [2022-02-21 04:24:46,331 INFO L290 TraceCheckUtils]: 2: Hoare triple {82839#true} assume !false; {82839#true} is VALID [2022-02-21 04:24:46,332 INFO L290 TraceCheckUtils]: 3: Hoare triple {82839#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {82839#true} is VALID [2022-02-21 04:24:46,332 INFO L290 TraceCheckUtils]: 4: Hoare triple {82839#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {82839#true} is VALID [2022-02-21 04:24:46,332 INFO L290 TraceCheckUtils]: 5: Hoare triple {82839#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {82839#true} is VALID [2022-02-21 04:24:46,332 INFO L290 TraceCheckUtils]: 6: Hoare triple {82839#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {82839#true} is VALID [2022-02-21 04:24:46,332 INFO L290 TraceCheckUtils]: 7: Hoare triple {82839#true} assume !(0 != eval_~tmp~0#1); {82839#true} is VALID [2022-02-21 04:24:46,332 INFO L290 TraceCheckUtils]: 8: Hoare triple {82839#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {82839#true} is VALID [2022-02-21 04:24:46,332 INFO L290 TraceCheckUtils]: 9: Hoare triple {82839#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {82839#true} is VALID [2022-02-21 04:24:46,332 INFO L290 TraceCheckUtils]: 10: Hoare triple {82839#true} assume !(0 == ~M_E~0); {82839#true} is VALID [2022-02-21 04:24:46,333 INFO L290 TraceCheckUtils]: 11: Hoare triple {82839#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {82839#true} is VALID [2022-02-21 04:24:46,333 INFO L290 TraceCheckUtils]: 12: Hoare triple {82839#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,333 INFO L290 TraceCheckUtils]: 13: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,334 INFO L290 TraceCheckUtils]: 14: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,334 INFO L290 TraceCheckUtils]: 15: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,334 INFO L290 TraceCheckUtils]: 16: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,335 INFO L290 TraceCheckUtils]: 17: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,335 INFO L290 TraceCheckUtils]: 18: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,335 INFO L290 TraceCheckUtils]: 19: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,336 INFO L290 TraceCheckUtils]: 20: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,336 INFO L290 TraceCheckUtils]: 21: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,336 INFO L290 TraceCheckUtils]: 22: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,337 INFO L290 TraceCheckUtils]: 23: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,337 INFO L290 TraceCheckUtils]: 24: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,337 INFO L290 TraceCheckUtils]: 25: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,338 INFO L290 TraceCheckUtils]: 26: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,338 INFO L290 TraceCheckUtils]: 27: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,338 INFO L290 TraceCheckUtils]: 28: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,338 INFO L290 TraceCheckUtils]: 29: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,339 INFO L290 TraceCheckUtils]: 30: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,339 INFO L290 TraceCheckUtils]: 31: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,339 INFO L290 TraceCheckUtils]: 32: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,340 INFO L290 TraceCheckUtils]: 33: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,340 INFO L290 TraceCheckUtils]: 34: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,340 INFO L290 TraceCheckUtils]: 35: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,341 INFO L290 TraceCheckUtils]: 36: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,341 INFO L290 TraceCheckUtils]: 37: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,341 INFO L290 TraceCheckUtils]: 38: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,342 INFO L290 TraceCheckUtils]: 39: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,342 INFO L290 TraceCheckUtils]: 40: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,342 INFO L290 TraceCheckUtils]: 41: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,343 INFO L290 TraceCheckUtils]: 42: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,343 INFO L290 TraceCheckUtils]: 43: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,343 INFO L290 TraceCheckUtils]: 44: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,344 INFO L290 TraceCheckUtils]: 45: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,344 INFO L290 TraceCheckUtils]: 46: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,344 INFO L290 TraceCheckUtils]: 47: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,345 INFO L290 TraceCheckUtils]: 48: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,345 INFO L290 TraceCheckUtils]: 49: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,345 INFO L290 TraceCheckUtils]: 50: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,345 INFO L290 TraceCheckUtils]: 51: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,346 INFO L290 TraceCheckUtils]: 52: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,346 INFO L290 TraceCheckUtils]: 53: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,346 INFO L290 TraceCheckUtils]: 54: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,347 INFO L290 TraceCheckUtils]: 55: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,347 INFO L290 TraceCheckUtils]: 56: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,347 INFO L290 TraceCheckUtils]: 57: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,348 INFO L290 TraceCheckUtils]: 58: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,348 INFO L290 TraceCheckUtils]: 59: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,348 INFO L290 TraceCheckUtils]: 60: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,349 INFO L290 TraceCheckUtils]: 61: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,349 INFO L290 TraceCheckUtils]: 62: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,349 INFO L290 TraceCheckUtils]: 63: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,350 INFO L290 TraceCheckUtils]: 64: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,350 INFO L290 TraceCheckUtils]: 65: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,350 INFO L290 TraceCheckUtils]: 66: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,351 INFO L290 TraceCheckUtils]: 67: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,351 INFO L290 TraceCheckUtils]: 68: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,351 INFO L290 TraceCheckUtils]: 69: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,352 INFO L290 TraceCheckUtils]: 70: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,352 INFO L290 TraceCheckUtils]: 71: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,352 INFO L290 TraceCheckUtils]: 72: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,353 INFO L290 TraceCheckUtils]: 73: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,353 INFO L290 TraceCheckUtils]: 74: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,353 INFO L290 TraceCheckUtils]: 75: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,354 INFO L290 TraceCheckUtils]: 76: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,354 INFO L290 TraceCheckUtils]: 77: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,354 INFO L290 TraceCheckUtils]: 78: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,355 INFO L290 TraceCheckUtils]: 79: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,355 INFO L290 TraceCheckUtils]: 80: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,355 INFO L290 TraceCheckUtils]: 81: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,356 INFO L290 TraceCheckUtils]: 82: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,356 INFO L290 TraceCheckUtils]: 83: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,356 INFO L290 TraceCheckUtils]: 84: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,357 INFO L290 TraceCheckUtils]: 85: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,357 INFO L290 TraceCheckUtils]: 86: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,357 INFO L290 TraceCheckUtils]: 87: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,358 INFO L290 TraceCheckUtils]: 88: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,358 INFO L290 TraceCheckUtils]: 89: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,358 INFO L290 TraceCheckUtils]: 90: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,359 INFO L290 TraceCheckUtils]: 91: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,359 INFO L290 TraceCheckUtils]: 92: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,359 INFO L290 TraceCheckUtils]: 93: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,360 INFO L290 TraceCheckUtils]: 94: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,360 INFO L290 TraceCheckUtils]: 95: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,360 INFO L290 TraceCheckUtils]: 96: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,361 INFO L290 TraceCheckUtils]: 97: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,361 INFO L290 TraceCheckUtils]: 98: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,361 INFO L290 TraceCheckUtils]: 99: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,362 INFO L290 TraceCheckUtils]: 100: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,362 INFO L290 TraceCheckUtils]: 101: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,362 INFO L290 TraceCheckUtils]: 102: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,362 INFO L290 TraceCheckUtils]: 103: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,363 INFO L290 TraceCheckUtils]: 104: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,363 INFO L290 TraceCheckUtils]: 105: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,363 INFO L290 TraceCheckUtils]: 106: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,364 INFO L290 TraceCheckUtils]: 107: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,364 INFO L290 TraceCheckUtils]: 108: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t12_pc~0); {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,364 INFO L290 TraceCheckUtils]: 109: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,365 INFO L290 TraceCheckUtils]: 110: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,365 INFO L290 TraceCheckUtils]: 111: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,365 INFO L290 TraceCheckUtils]: 112: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,366 INFO L290 TraceCheckUtils]: 113: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,366 INFO L290 TraceCheckUtils]: 114: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,366 INFO L290 TraceCheckUtils]: 115: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {82841#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:46,367 INFO L290 TraceCheckUtils]: 116: Hoare triple {82841#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {82840#false} is VALID [2022-02-21 04:24:46,367 INFO L290 TraceCheckUtils]: 117: Hoare triple {82840#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,367 INFO L290 TraceCheckUtils]: 118: Hoare triple {82840#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,367 INFO L290 TraceCheckUtils]: 119: Hoare triple {82840#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,367 INFO L290 TraceCheckUtils]: 120: Hoare triple {82840#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,367 INFO L290 TraceCheckUtils]: 121: Hoare triple {82840#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,368 INFO L290 TraceCheckUtils]: 122: Hoare triple {82840#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,368 INFO L290 TraceCheckUtils]: 123: Hoare triple {82840#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,368 INFO L290 TraceCheckUtils]: 124: Hoare triple {82840#false} assume !(1 == ~T10_E~0); {82840#false} is VALID [2022-02-21 04:24:46,368 INFO L290 TraceCheckUtils]: 125: Hoare triple {82840#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,368 INFO L290 TraceCheckUtils]: 126: Hoare triple {82840#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,368 INFO L290 TraceCheckUtils]: 127: Hoare triple {82840#false} assume 1 == ~E_1~0;~E_1~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,368 INFO L290 TraceCheckUtils]: 128: Hoare triple {82840#false} assume 1 == ~E_2~0;~E_2~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,368 INFO L290 TraceCheckUtils]: 129: Hoare triple {82840#false} assume 1 == ~E_3~0;~E_3~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,369 INFO L290 TraceCheckUtils]: 130: Hoare triple {82840#false} assume 1 == ~E_4~0;~E_4~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,369 INFO L290 TraceCheckUtils]: 131: Hoare triple {82840#false} assume 1 == ~E_5~0;~E_5~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,369 INFO L290 TraceCheckUtils]: 132: Hoare triple {82840#false} assume !(1 == ~E_6~0); {82840#false} is VALID [2022-02-21 04:24:46,369 INFO L290 TraceCheckUtils]: 133: Hoare triple {82840#false} assume 1 == ~E_7~0;~E_7~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,369 INFO L290 TraceCheckUtils]: 134: Hoare triple {82840#false} assume 1 == ~E_8~0;~E_8~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,369 INFO L290 TraceCheckUtils]: 135: Hoare triple {82840#false} assume 1 == ~E_9~0;~E_9~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,369 INFO L290 TraceCheckUtils]: 136: Hoare triple {82840#false} assume 1 == ~E_10~0;~E_10~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,370 INFO L290 TraceCheckUtils]: 137: Hoare triple {82840#false} assume 1 == ~E_11~0;~E_11~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,370 INFO L290 TraceCheckUtils]: 138: Hoare triple {82840#false} assume 1 == ~E_12~0;~E_12~0 := 2; {82840#false} is VALID [2022-02-21 04:24:46,370 INFO L290 TraceCheckUtils]: 139: Hoare triple {82840#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {82840#false} is VALID [2022-02-21 04:24:46,370 INFO L290 TraceCheckUtils]: 140: Hoare triple {82840#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {82840#false} is VALID [2022-02-21 04:24:46,370 INFO L290 TraceCheckUtils]: 141: Hoare triple {82840#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {82840#false} is VALID [2022-02-21 04:24:46,370 INFO L290 TraceCheckUtils]: 142: Hoare triple {82840#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {82840#false} is VALID [2022-02-21 04:24:46,370 INFO L290 TraceCheckUtils]: 143: Hoare triple {82840#false} assume !(0 == start_simulation_~tmp~3#1); {82840#false} is VALID [2022-02-21 04:24:46,371 INFO L290 TraceCheckUtils]: 144: Hoare triple {82840#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {82840#false} is VALID [2022-02-21 04:24:46,371 INFO L290 TraceCheckUtils]: 145: Hoare triple {82840#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {82840#false} is VALID [2022-02-21 04:24:46,371 INFO L290 TraceCheckUtils]: 146: Hoare triple {82840#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {82840#false} is VALID [2022-02-21 04:24:46,371 INFO L290 TraceCheckUtils]: 147: Hoare triple {82840#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {82840#false} is VALID [2022-02-21 04:24:46,371 INFO L290 TraceCheckUtils]: 148: Hoare triple {82840#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {82840#false} is VALID [2022-02-21 04:24:46,371 INFO L290 TraceCheckUtils]: 149: Hoare triple {82840#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {82840#false} is VALID [2022-02-21 04:24:46,371 INFO L290 TraceCheckUtils]: 150: Hoare triple {82840#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {82840#false} is VALID [2022-02-21 04:24:46,372 INFO L290 TraceCheckUtils]: 151: Hoare triple {82840#false} assume !(0 != start_simulation_~tmp___0~1#1); {82840#false} is VALID [2022-02-21 04:24:46,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:46,372 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:46,372 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1747701639] [2022-02-21 04:24:46,373 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1747701639] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:46,373 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:46,373 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:46,373 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2110070485] [2022-02-21 04:24:46,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:46,374 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:46,374 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:46,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:46,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:46,375 INFO L87 Difference]: Start difference. First operand 1688 states and 2493 transitions. cyclomatic complexity: 806 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:47,693 INFO L93 Difference]: Finished difference Result 1688 states and 2488 transitions. [2022-02-21 04:24:47,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:47,693 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,750 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:47,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1688 states and 2488 transitions. [2022-02-21 04:24:47,813 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:47,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1688 states to 1688 states and 2488 transitions. [2022-02-21 04:24:47,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1688 [2022-02-21 04:24:47,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1688 [2022-02-21 04:24:47,876 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1688 states and 2488 transitions. [2022-02-21 04:24:47,877 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:47,877 INFO L681 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2022-02-21 04:24:47,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1688 states and 2488 transitions. [2022-02-21 04:24:47,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1688 to 1688. [2022-02-21 04:24:47,892 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:47,894 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1688 states and 2488 transitions. Second operand has 1688 states, 1688 states have (on average 1.4739336492890995) internal successors, (2488), 1687 states have internal predecessors, (2488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,895 INFO L74 IsIncluded]: Start isIncluded. First operand 1688 states and 2488 transitions. Second operand has 1688 states, 1688 states have (on average 1.4739336492890995) internal successors, (2488), 1687 states have internal predecessors, (2488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,896 INFO L87 Difference]: Start difference. First operand 1688 states and 2488 transitions. Second operand has 1688 states, 1688 states have (on average 1.4739336492890995) internal successors, (2488), 1687 states have internal predecessors, (2488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:47,977 INFO L93 Difference]: Finished difference Result 1688 states and 2488 transitions. [2022-02-21 04:24:47,977 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2488 transitions. [2022-02-21 04:24:47,978 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:47,979 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:47,980 INFO L74 IsIncluded]: Start isIncluded. First operand has 1688 states, 1688 states have (on average 1.4739336492890995) internal successors, (2488), 1687 states have internal predecessors, (2488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2488 transitions. [2022-02-21 04:24:47,981 INFO L87 Difference]: Start difference. First operand has 1688 states, 1688 states have (on average 1.4739336492890995) internal successors, (2488), 1687 states have internal predecessors, (2488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1688 states and 2488 transitions. [2022-02-21 04:24:48,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:48,062 INFO L93 Difference]: Finished difference Result 1688 states and 2488 transitions. [2022-02-21 04:24:48,062 INFO L276 IsEmpty]: Start isEmpty. Operand 1688 states and 2488 transitions. [2022-02-21 04:24:48,064 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:48,064 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:48,064 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:48,064 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:48,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1688 states, 1688 states have (on average 1.4739336492890995) internal successors, (2488), 1687 states have internal predecessors, (2488), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:48,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1688 states to 1688 states and 2488 transitions. [2022-02-21 04:24:48,165 INFO L704 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2022-02-21 04:24:48,165 INFO L587 BuchiCegarLoop]: Abstraction has 1688 states and 2488 transitions. [2022-02-21 04:24:48,165 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:24:48,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1688 states and 2488 transitions. [2022-02-21 04:24:48,168 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1527 [2022-02-21 04:24:48,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:48,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:48,171 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:48,171 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:48,171 INFO L791 eck$LassoCheckResult]: Stem: 85333#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 85334#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 86187#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85679#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 85486#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 85487#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85572#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85873#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85995#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 85996#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84784#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 84785#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85933#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85379#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 85380#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 85286#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 85287#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 85675#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85028#L1174 assume !(0 == ~M_E~0); 85029#L1174-2 assume !(0 == ~T1_E~0); 84880#L1179-1 assume !(0 == ~T2_E~0); 84782#L1184-1 assume !(0 == ~T3_E~0); 84783#L1189-1 assume !(0 == ~T4_E~0); 84821#L1194-1 assume !(0 == ~T5_E~0); 84921#L1199-1 assume !(0 == ~T6_E~0); 85816#L1204-1 assume !(0 == ~T7_E~0); 85735#L1209-1 assume !(0 == ~T8_E~0); 85736#L1214-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86124#L1219-1 assume !(0 == ~T10_E~0); 86209#L1224-1 assume !(0 == ~T11_E~0); 85146#L1229-1 assume !(0 == ~T12_E~0); 84707#L1234-1 assume !(0 == ~E_1~0); 84708#L1239-1 assume !(0 == ~E_2~0); 84741#L1244-1 assume !(0 == ~E_3~0); 84742#L1249-1 assume !(0 == ~E_4~0); 85403#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 84637#L1259-1 assume !(0 == ~E_6~0); 84592#L1264-1 assume !(0 == ~E_7~0); 84593#L1269-1 assume !(0 == ~E_8~0); 86214#L1274-1 assume !(0 == ~E_9~0); 86149#L1279-1 assume !(0 == ~E_10~0); 84825#L1284-1 assume !(0 == ~E_11~0); 84826#L1289-1 assume !(0 == ~E_12~0); 85455#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85456#L566 assume 1 == ~m_pc~0; 84609#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 84610#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85764#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 85765#L1455 assume !(0 != activate_threads_~tmp~1#1); 85055#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85056#L585 assume 1 == ~t1_pc~0; 84704#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 84705#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85705#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 85706#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 86174#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86172#L604 assume !(1 == ~t2_pc~0); 85784#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 85785#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85318#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 85319#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 85956#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85957#L623 assume 1 == ~t3_pc~0; 85233#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 84573#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85383#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85384#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 85991#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84606#L642 assume !(1 == ~t4_pc~0); 84607#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 85072#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85073#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84678#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 84679#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85796#L661 assume 1 == ~t5_pc~0; 84843#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 84844#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 84805#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84806#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 85825#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85826#L680 assume !(1 == ~t6_pc~0); 85266#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 85267#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85528#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85529#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 86057#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86170#L699 assume 1 == ~t7_pc~0; 85656#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85657#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84833#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84834#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 85558#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85457#L718 assume !(1 == ~t8_pc~0); 85458#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 84819#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84820#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84861#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 84862#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84995#L737 assume 1 == ~t9_pc~0; 85860#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85130#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85731#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85732#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 85304#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85305#L756 assume 1 == ~t10_pc~0; 85884#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 85550#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 84536#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 84537#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 85112#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85113#L775 assume !(1 == ~t11_pc~0); 85367#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 85368#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 84989#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 84753#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 84754#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84940#L794 assume 1 == ~t12_pc~0; 84780#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 84758#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85951#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 84906#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 84907#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85386#L1307 assume !(1 == ~M_E~0); 85387#L1307-2 assume !(1 == ~T1_E~0); 85498#L1312-1 assume !(1 == ~T2_E~0); 85417#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85418#L1322-1 assume !(1 == ~T4_E~0); 85121#L1327-1 assume !(1 == ~T5_E~0); 85122#L1332-1 assume !(1 == ~T6_E~0); 85660#L1337-1 assume !(1 == ~T7_E~0); 85622#L1342-1 assume !(1 == ~T8_E~0); 85623#L1347-1 assume !(1 == ~T9_E~0); 86020#L1352-1 assume !(1 == ~T10_E~0); 85893#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85284#L1362-1 assume !(1 == ~T12_E~0); 85285#L1367-1 assume !(1 == ~E_1~0); 84922#L1372-1 assume !(1 == ~E_2~0); 84923#L1377-1 assume !(1 == ~E_3~0); 85216#L1382-1 assume !(1 == ~E_4~0); 85217#L1387-1 assume !(1 == ~E_5~0); 85786#L1392-1 assume !(1 == ~E_6~0); 85236#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 85237#L1402-1 assume !(1 == ~E_8~0); 84933#L1407-1 assume !(1 == ~E_9~0); 84934#L1412-1 assume !(1 == ~E_10~0); 85949#L1417-1 assume !(1 == ~E_11~0); 85950#L1422-1 assume !(1 == ~E_12~0); 86168#L1427-1 assume { :end_inline_reset_delta_events } true; 84737#L1768-2 [2022-02-21 04:24:48,171 INFO L793 eck$LassoCheckResult]: Loop: 84737#L1768-2 assume !false; 84738#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85476#L1149 assume !false; 85848#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 86001#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 85127#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 85033#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 85034#L976 assume !(0 != eval_~tmp~0#1); 86167#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 86177#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85968#L1174-3 assume !(0 == ~M_E~0); 85961#L1174-5 assume !(0 == ~T1_E~0); 85710#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 85711#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85894#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85545#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 84895#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 84896#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85137#L1209-3 assume !(0 == ~T8_E~0); 84557#L1214-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 84558#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 85316#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85317#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 85335#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 84745#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 84746#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 85189#L1249-3 assume !(0 == ~E_4~0); 85648#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86120#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 85762#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 84751#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 84752#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 86147#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 85314#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 85315#L1289-3 assume !(0 == ~E_12~0); 85303#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84979#L566-39 assume !(1 == ~m_pc~0); 84981#L566-41 is_master_triggered_~__retres1~0#1 := 0; 85582#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 85294#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 85295#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 85837#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85838#L585-39 assume !(1 == ~t1_pc~0); 84987#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 84988#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85063#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 85064#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 85870#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85563#L604-39 assume !(1 == ~t2_pc~0); 85565#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 85195#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85196#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 85613#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 85614#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85178#L623-39 assume !(1 == ~t3_pc~0); 84575#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 84576#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85854#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85030#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 85031#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85802#L642-39 assume 1 == ~t4_pc~0; 85373#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 85374#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84902#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84903#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 86000#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84951#L661-39 assume !(1 == ~t5_pc~0); 84582#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 84583#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85943#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 85944#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 85857#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85858#L680-39 assume 1 == ~t6_pc~0; 84644#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 84645#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85787#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85110#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 85111#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86125#L699-39 assume 1 == ~t7_pc~0; 85547#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85269#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85270#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85953#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86074#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86072#L718-39 assume 1 == ~t8_pc~0; 85461#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85462#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85394#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85395#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 85697#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85666#L737-39 assume 1 == ~t9_pc~0; 85091#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85092#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85381#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86148#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 86049#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85992#L756-39 assume !(1 == ~t10_pc~0); 85473#L756-41 is_transmit10_triggered_~__retres1~10#1 := 0; 85474#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85218#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 85219#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85351#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84691#L775-39 assume !(1 == ~t11_pc~0); 84693#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 85344#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85345#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86207#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 85755#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85402#L794-39 assume 1 == ~t12_pc~0; 85094#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 85088#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85908#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85809#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 84633#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84634#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 86101#L1307-5 assume !(1 == ~T1_E~0); 86102#L1312-3 assume !(1 == ~T2_E~0); 86213#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 85827#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85828#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 84772#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 84743#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 84744#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 85490#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 85615#L1352-3 assume !(1 == ~T10_E~0); 85616#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86055#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 86206#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86197#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 84570#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 84571#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85202#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85203#L1392-3 assume !(1 == ~E_6~0); 85918#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86164#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85581#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 84857#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 84858#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 85506#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 85507#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 84867#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 84868#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 85734#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 85586#L1787 assume !(0 == start_simulation_~tmp~3#1); 85587#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 86110#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 84838#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 85633#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 85634#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 85185#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 85186#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 85187#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 84737#L1768-2 [2022-02-21 04:24:48,172 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:48,172 INFO L85 PathProgramCache]: Analyzing trace with hash 1978532629, now seen corresponding path program 1 times [2022-02-21 04:24:48,172 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:48,172 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345734773] [2022-02-21 04:24:48,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:48,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:48,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:48,200 INFO L290 TraceCheckUtils]: 0: Hoare triple {89597#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,201 INFO L290 TraceCheckUtils]: 1: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,201 INFO L290 TraceCheckUtils]: 2: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,201 INFO L290 TraceCheckUtils]: 3: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,201 INFO L290 TraceCheckUtils]: 4: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,202 INFO L290 TraceCheckUtils]: 5: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,202 INFO L290 TraceCheckUtils]: 6: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,202 INFO L290 TraceCheckUtils]: 7: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,203 INFO L290 TraceCheckUtils]: 8: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,203 INFO L290 TraceCheckUtils]: 9: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,203 INFO L290 TraceCheckUtils]: 10: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,203 INFO L290 TraceCheckUtils]: 11: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,204 INFO L290 TraceCheckUtils]: 12: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,204 INFO L290 TraceCheckUtils]: 13: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,204 INFO L290 TraceCheckUtils]: 14: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,204 INFO L290 TraceCheckUtils]: 15: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,205 INFO L290 TraceCheckUtils]: 16: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,205 INFO L290 TraceCheckUtils]: 17: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,205 INFO L290 TraceCheckUtils]: 18: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume !(0 == ~M_E~0); {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,206 INFO L290 TraceCheckUtils]: 19: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume !(0 == ~T1_E~0); {89599#(= ~T2_E~0 ~T9_E~0)} is VALID [2022-02-21 04:24:48,206 INFO L290 TraceCheckUtils]: 20: Hoare triple {89599#(= ~T2_E~0 ~T9_E~0)} assume !(0 == ~T2_E~0); {89600#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:24:48,206 INFO L290 TraceCheckUtils]: 21: Hoare triple {89600#(not (= ~T9_E~0 0))} assume !(0 == ~T3_E~0); {89600#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:24:48,207 INFO L290 TraceCheckUtils]: 22: Hoare triple {89600#(not (= ~T9_E~0 0))} assume !(0 == ~T4_E~0); {89600#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:24:48,207 INFO L290 TraceCheckUtils]: 23: Hoare triple {89600#(not (= ~T9_E~0 0))} assume !(0 == ~T5_E~0); {89600#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:24:48,207 INFO L290 TraceCheckUtils]: 24: Hoare triple {89600#(not (= ~T9_E~0 0))} assume !(0 == ~T6_E~0); {89600#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:24:48,208 INFO L290 TraceCheckUtils]: 25: Hoare triple {89600#(not (= ~T9_E~0 0))} assume !(0 == ~T7_E~0); {89600#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:24:48,208 INFO L290 TraceCheckUtils]: 26: Hoare triple {89600#(not (= ~T9_E~0 0))} assume !(0 == ~T8_E~0); {89600#(not (= ~T9_E~0 0))} is VALID [2022-02-21 04:24:48,208 INFO L290 TraceCheckUtils]: 27: Hoare triple {89600#(not (= ~T9_E~0 0))} assume 0 == ~T9_E~0;~T9_E~0 := 1; {89598#false} is VALID [2022-02-21 04:24:48,208 INFO L290 TraceCheckUtils]: 28: Hoare triple {89598#false} assume !(0 == ~T10_E~0); {89598#false} is VALID [2022-02-21 04:24:48,208 INFO L290 TraceCheckUtils]: 29: Hoare triple {89598#false} assume !(0 == ~T11_E~0); {89598#false} is VALID [2022-02-21 04:24:48,209 INFO L290 TraceCheckUtils]: 30: Hoare triple {89598#false} assume !(0 == ~T12_E~0); {89598#false} is VALID [2022-02-21 04:24:48,209 INFO L290 TraceCheckUtils]: 31: Hoare triple {89598#false} assume !(0 == ~E_1~0); {89598#false} is VALID [2022-02-21 04:24:48,209 INFO L290 TraceCheckUtils]: 32: Hoare triple {89598#false} assume !(0 == ~E_2~0); {89598#false} is VALID [2022-02-21 04:24:48,209 INFO L290 TraceCheckUtils]: 33: Hoare triple {89598#false} assume !(0 == ~E_3~0); {89598#false} is VALID [2022-02-21 04:24:48,209 INFO L290 TraceCheckUtils]: 34: Hoare triple {89598#false} assume !(0 == ~E_4~0); {89598#false} is VALID [2022-02-21 04:24:48,209 INFO L290 TraceCheckUtils]: 35: Hoare triple {89598#false} assume 0 == ~E_5~0;~E_5~0 := 1; {89598#false} is VALID [2022-02-21 04:24:48,209 INFO L290 TraceCheckUtils]: 36: Hoare triple {89598#false} assume !(0 == ~E_6~0); {89598#false} is VALID [2022-02-21 04:24:48,209 INFO L290 TraceCheckUtils]: 37: Hoare triple {89598#false} assume !(0 == ~E_7~0); {89598#false} is VALID [2022-02-21 04:24:48,210 INFO L290 TraceCheckUtils]: 38: Hoare triple {89598#false} assume !(0 == ~E_8~0); {89598#false} is VALID [2022-02-21 04:24:48,210 INFO L290 TraceCheckUtils]: 39: Hoare triple {89598#false} assume !(0 == ~E_9~0); {89598#false} is VALID [2022-02-21 04:24:48,210 INFO L290 TraceCheckUtils]: 40: Hoare triple {89598#false} assume !(0 == ~E_10~0); {89598#false} is VALID [2022-02-21 04:24:48,210 INFO L290 TraceCheckUtils]: 41: Hoare triple {89598#false} assume !(0 == ~E_11~0); {89598#false} is VALID [2022-02-21 04:24:48,210 INFO L290 TraceCheckUtils]: 42: Hoare triple {89598#false} assume !(0 == ~E_12~0); {89598#false} is VALID [2022-02-21 04:24:48,210 INFO L290 TraceCheckUtils]: 43: Hoare triple {89598#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {89598#false} is VALID [2022-02-21 04:24:48,210 INFO L290 TraceCheckUtils]: 44: Hoare triple {89598#false} assume 1 == ~m_pc~0; {89598#false} is VALID [2022-02-21 04:24:48,210 INFO L290 TraceCheckUtils]: 45: Hoare triple {89598#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {89598#false} is VALID [2022-02-21 04:24:48,211 INFO L290 TraceCheckUtils]: 46: Hoare triple {89598#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {89598#false} is VALID [2022-02-21 04:24:48,211 INFO L290 TraceCheckUtils]: 47: Hoare triple {89598#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {89598#false} is VALID [2022-02-21 04:24:48,211 INFO L290 TraceCheckUtils]: 48: Hoare triple {89598#false} assume !(0 != activate_threads_~tmp~1#1); {89598#false} is VALID [2022-02-21 04:24:48,211 INFO L290 TraceCheckUtils]: 49: Hoare triple {89598#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {89598#false} is VALID [2022-02-21 04:24:48,211 INFO L290 TraceCheckUtils]: 50: Hoare triple {89598#false} assume 1 == ~t1_pc~0; {89598#false} is VALID [2022-02-21 04:24:48,211 INFO L290 TraceCheckUtils]: 51: Hoare triple {89598#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {89598#false} is VALID [2022-02-21 04:24:48,211 INFO L290 TraceCheckUtils]: 52: Hoare triple {89598#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {89598#false} is VALID [2022-02-21 04:24:48,212 INFO L290 TraceCheckUtils]: 53: Hoare triple {89598#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {89598#false} is VALID [2022-02-21 04:24:48,212 INFO L290 TraceCheckUtils]: 54: Hoare triple {89598#false} assume !(0 != activate_threads_~tmp___0~0#1); {89598#false} is VALID [2022-02-21 04:24:48,212 INFO L290 TraceCheckUtils]: 55: Hoare triple {89598#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {89598#false} is VALID [2022-02-21 04:24:48,212 INFO L290 TraceCheckUtils]: 56: Hoare triple {89598#false} assume !(1 == ~t2_pc~0); {89598#false} is VALID [2022-02-21 04:24:48,212 INFO L290 TraceCheckUtils]: 57: Hoare triple {89598#false} is_transmit2_triggered_~__retres1~2#1 := 0; {89598#false} is VALID [2022-02-21 04:24:48,212 INFO L290 TraceCheckUtils]: 58: Hoare triple {89598#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {89598#false} is VALID [2022-02-21 04:24:48,212 INFO L290 TraceCheckUtils]: 59: Hoare triple {89598#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {89598#false} is VALID [2022-02-21 04:24:48,212 INFO L290 TraceCheckUtils]: 60: Hoare triple {89598#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {89598#false} is VALID [2022-02-21 04:24:48,213 INFO L290 TraceCheckUtils]: 61: Hoare triple {89598#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {89598#false} is VALID [2022-02-21 04:24:48,213 INFO L290 TraceCheckUtils]: 62: Hoare triple {89598#false} assume 1 == ~t3_pc~0; {89598#false} is VALID [2022-02-21 04:24:48,213 INFO L290 TraceCheckUtils]: 63: Hoare triple {89598#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {89598#false} is VALID [2022-02-21 04:24:48,213 INFO L290 TraceCheckUtils]: 64: Hoare triple {89598#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {89598#false} is VALID [2022-02-21 04:24:48,213 INFO L290 TraceCheckUtils]: 65: Hoare triple {89598#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {89598#false} is VALID [2022-02-21 04:24:48,213 INFO L290 TraceCheckUtils]: 66: Hoare triple {89598#false} assume !(0 != activate_threads_~tmp___2~0#1); {89598#false} is VALID [2022-02-21 04:24:48,213 INFO L290 TraceCheckUtils]: 67: Hoare triple {89598#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {89598#false} is VALID [2022-02-21 04:24:48,213 INFO L290 TraceCheckUtils]: 68: Hoare triple {89598#false} assume !(1 == ~t4_pc~0); {89598#false} is VALID [2022-02-21 04:24:48,214 INFO L290 TraceCheckUtils]: 69: Hoare triple {89598#false} is_transmit4_triggered_~__retres1~4#1 := 0; {89598#false} is VALID [2022-02-21 04:24:48,214 INFO L290 TraceCheckUtils]: 70: Hoare triple {89598#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {89598#false} is VALID [2022-02-21 04:24:48,214 INFO L290 TraceCheckUtils]: 71: Hoare triple {89598#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {89598#false} is VALID [2022-02-21 04:24:48,214 INFO L290 TraceCheckUtils]: 72: Hoare triple {89598#false} assume !(0 != activate_threads_~tmp___3~0#1); {89598#false} is VALID [2022-02-21 04:24:48,214 INFO L290 TraceCheckUtils]: 73: Hoare triple {89598#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {89598#false} is VALID [2022-02-21 04:24:48,214 INFO L290 TraceCheckUtils]: 74: Hoare triple {89598#false} assume 1 == ~t5_pc~0; {89598#false} is VALID [2022-02-21 04:24:48,214 INFO L290 TraceCheckUtils]: 75: Hoare triple {89598#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {89598#false} is VALID [2022-02-21 04:24:48,215 INFO L290 TraceCheckUtils]: 76: Hoare triple {89598#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {89598#false} is VALID [2022-02-21 04:24:48,215 INFO L290 TraceCheckUtils]: 77: Hoare triple {89598#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {89598#false} is VALID [2022-02-21 04:24:48,215 INFO L290 TraceCheckUtils]: 78: Hoare triple {89598#false} assume !(0 != activate_threads_~tmp___4~0#1); {89598#false} is VALID [2022-02-21 04:24:48,215 INFO L290 TraceCheckUtils]: 79: Hoare triple {89598#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {89598#false} is VALID [2022-02-21 04:24:48,215 INFO L290 TraceCheckUtils]: 80: Hoare triple {89598#false} assume !(1 == ~t6_pc~0); {89598#false} is VALID [2022-02-21 04:24:48,215 INFO L290 TraceCheckUtils]: 81: Hoare triple {89598#false} is_transmit6_triggered_~__retres1~6#1 := 0; {89598#false} is VALID [2022-02-21 04:24:48,215 INFO L290 TraceCheckUtils]: 82: Hoare triple {89598#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {89598#false} is VALID [2022-02-21 04:24:48,215 INFO L290 TraceCheckUtils]: 83: Hoare triple {89598#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {89598#false} is VALID [2022-02-21 04:24:48,216 INFO L290 TraceCheckUtils]: 84: Hoare triple {89598#false} assume !(0 != activate_threads_~tmp___5~0#1); {89598#false} is VALID [2022-02-21 04:24:48,216 INFO L290 TraceCheckUtils]: 85: Hoare triple {89598#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {89598#false} is VALID [2022-02-21 04:24:48,216 INFO L290 TraceCheckUtils]: 86: Hoare triple {89598#false} assume 1 == ~t7_pc~0; {89598#false} is VALID [2022-02-21 04:24:48,216 INFO L290 TraceCheckUtils]: 87: Hoare triple {89598#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {89598#false} is VALID [2022-02-21 04:24:48,216 INFO L290 TraceCheckUtils]: 88: Hoare triple {89598#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {89598#false} is VALID [2022-02-21 04:24:48,216 INFO L290 TraceCheckUtils]: 89: Hoare triple {89598#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {89598#false} is VALID [2022-02-21 04:24:48,216 INFO L290 TraceCheckUtils]: 90: Hoare triple {89598#false} assume !(0 != activate_threads_~tmp___6~0#1); {89598#false} is VALID [2022-02-21 04:24:48,217 INFO L290 TraceCheckUtils]: 91: Hoare triple {89598#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {89598#false} is VALID [2022-02-21 04:24:48,217 INFO L290 TraceCheckUtils]: 92: Hoare triple {89598#false} assume !(1 == ~t8_pc~0); {89598#false} is VALID [2022-02-21 04:24:48,217 INFO L290 TraceCheckUtils]: 93: Hoare triple {89598#false} is_transmit8_triggered_~__retres1~8#1 := 0; {89598#false} is VALID [2022-02-21 04:24:48,217 INFO L290 TraceCheckUtils]: 94: Hoare triple {89598#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {89598#false} is VALID [2022-02-21 04:24:48,217 INFO L290 TraceCheckUtils]: 95: Hoare triple {89598#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {89598#false} is VALID [2022-02-21 04:24:48,217 INFO L290 TraceCheckUtils]: 96: Hoare triple {89598#false} assume !(0 != activate_threads_~tmp___7~0#1); {89598#false} is VALID [2022-02-21 04:24:48,217 INFO L290 TraceCheckUtils]: 97: Hoare triple {89598#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {89598#false} is VALID [2022-02-21 04:24:48,217 INFO L290 TraceCheckUtils]: 98: Hoare triple {89598#false} assume 1 == ~t9_pc~0; {89598#false} is VALID [2022-02-21 04:24:48,218 INFO L290 TraceCheckUtils]: 99: Hoare triple {89598#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {89598#false} is VALID [2022-02-21 04:24:48,218 INFO L290 TraceCheckUtils]: 100: Hoare triple {89598#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {89598#false} is VALID [2022-02-21 04:24:48,218 INFO L290 TraceCheckUtils]: 101: Hoare triple {89598#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {89598#false} is VALID [2022-02-21 04:24:48,218 INFO L290 TraceCheckUtils]: 102: Hoare triple {89598#false} assume !(0 != activate_threads_~tmp___8~0#1); {89598#false} is VALID [2022-02-21 04:24:48,218 INFO L290 TraceCheckUtils]: 103: Hoare triple {89598#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {89598#false} is VALID [2022-02-21 04:24:48,218 INFO L290 TraceCheckUtils]: 104: Hoare triple {89598#false} assume 1 == ~t10_pc~0; {89598#false} is VALID [2022-02-21 04:24:48,218 INFO L290 TraceCheckUtils]: 105: Hoare triple {89598#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {89598#false} is VALID [2022-02-21 04:24:48,218 INFO L290 TraceCheckUtils]: 106: Hoare triple {89598#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {89598#false} is VALID [2022-02-21 04:24:48,219 INFO L290 TraceCheckUtils]: 107: Hoare triple {89598#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {89598#false} is VALID [2022-02-21 04:24:48,219 INFO L290 TraceCheckUtils]: 108: Hoare triple {89598#false} assume !(0 != activate_threads_~tmp___9~0#1); {89598#false} is VALID [2022-02-21 04:24:48,219 INFO L290 TraceCheckUtils]: 109: Hoare triple {89598#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {89598#false} is VALID [2022-02-21 04:24:48,219 INFO L290 TraceCheckUtils]: 110: Hoare triple {89598#false} assume !(1 == ~t11_pc~0); {89598#false} is VALID [2022-02-21 04:24:48,219 INFO L290 TraceCheckUtils]: 111: Hoare triple {89598#false} is_transmit11_triggered_~__retres1~11#1 := 0; {89598#false} is VALID [2022-02-21 04:24:48,219 INFO L290 TraceCheckUtils]: 112: Hoare triple {89598#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {89598#false} is VALID [2022-02-21 04:24:48,219 INFO L290 TraceCheckUtils]: 113: Hoare triple {89598#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {89598#false} is VALID [2022-02-21 04:24:48,219 INFO L290 TraceCheckUtils]: 114: Hoare triple {89598#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {89598#false} is VALID [2022-02-21 04:24:48,220 INFO L290 TraceCheckUtils]: 115: Hoare triple {89598#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {89598#false} is VALID [2022-02-21 04:24:48,220 INFO L290 TraceCheckUtils]: 116: Hoare triple {89598#false} assume 1 == ~t12_pc~0; {89598#false} is VALID [2022-02-21 04:24:48,220 INFO L290 TraceCheckUtils]: 117: Hoare triple {89598#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {89598#false} is VALID [2022-02-21 04:24:48,220 INFO L290 TraceCheckUtils]: 118: Hoare triple {89598#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {89598#false} is VALID [2022-02-21 04:24:48,220 INFO L290 TraceCheckUtils]: 119: Hoare triple {89598#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {89598#false} is VALID [2022-02-21 04:24:48,220 INFO L290 TraceCheckUtils]: 120: Hoare triple {89598#false} assume !(0 != activate_threads_~tmp___11~0#1); {89598#false} is VALID [2022-02-21 04:24:48,220 INFO L290 TraceCheckUtils]: 121: Hoare triple {89598#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {89598#false} is VALID [2022-02-21 04:24:48,220 INFO L290 TraceCheckUtils]: 122: Hoare triple {89598#false} assume !(1 == ~M_E~0); {89598#false} is VALID [2022-02-21 04:24:48,221 INFO L290 TraceCheckUtils]: 123: Hoare triple {89598#false} assume !(1 == ~T1_E~0); {89598#false} is VALID [2022-02-21 04:24:48,221 INFO L290 TraceCheckUtils]: 124: Hoare triple {89598#false} assume !(1 == ~T2_E~0); {89598#false} is VALID [2022-02-21 04:24:48,221 INFO L290 TraceCheckUtils]: 125: Hoare triple {89598#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {89598#false} is VALID [2022-02-21 04:24:48,221 INFO L290 TraceCheckUtils]: 126: Hoare triple {89598#false} assume !(1 == ~T4_E~0); {89598#false} is VALID [2022-02-21 04:24:48,221 INFO L290 TraceCheckUtils]: 127: Hoare triple {89598#false} assume !(1 == ~T5_E~0); {89598#false} is VALID [2022-02-21 04:24:48,221 INFO L290 TraceCheckUtils]: 128: Hoare triple {89598#false} assume !(1 == ~T6_E~0); {89598#false} is VALID [2022-02-21 04:24:48,221 INFO L290 TraceCheckUtils]: 129: Hoare triple {89598#false} assume !(1 == ~T7_E~0); {89598#false} is VALID [2022-02-21 04:24:48,222 INFO L290 TraceCheckUtils]: 130: Hoare triple {89598#false} assume !(1 == ~T8_E~0); {89598#false} is VALID [2022-02-21 04:24:48,222 INFO L290 TraceCheckUtils]: 131: Hoare triple {89598#false} assume !(1 == ~T9_E~0); {89598#false} is VALID [2022-02-21 04:24:48,222 INFO L290 TraceCheckUtils]: 132: Hoare triple {89598#false} assume !(1 == ~T10_E~0); {89598#false} is VALID [2022-02-21 04:24:48,222 INFO L290 TraceCheckUtils]: 133: Hoare triple {89598#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {89598#false} is VALID [2022-02-21 04:24:48,222 INFO L290 TraceCheckUtils]: 134: Hoare triple {89598#false} assume !(1 == ~T12_E~0); {89598#false} is VALID [2022-02-21 04:24:48,222 INFO L290 TraceCheckUtils]: 135: Hoare triple {89598#false} assume !(1 == ~E_1~0); {89598#false} is VALID [2022-02-21 04:24:48,222 INFO L290 TraceCheckUtils]: 136: Hoare triple {89598#false} assume !(1 == ~E_2~0); {89598#false} is VALID [2022-02-21 04:24:48,222 INFO L290 TraceCheckUtils]: 137: Hoare triple {89598#false} assume !(1 == ~E_3~0); {89598#false} is VALID [2022-02-21 04:24:48,223 INFO L290 TraceCheckUtils]: 138: Hoare triple {89598#false} assume !(1 == ~E_4~0); {89598#false} is VALID [2022-02-21 04:24:48,223 INFO L290 TraceCheckUtils]: 139: Hoare triple {89598#false} assume !(1 == ~E_5~0); {89598#false} is VALID [2022-02-21 04:24:48,223 INFO L290 TraceCheckUtils]: 140: Hoare triple {89598#false} assume !(1 == ~E_6~0); {89598#false} is VALID [2022-02-21 04:24:48,223 INFO L290 TraceCheckUtils]: 141: Hoare triple {89598#false} assume 1 == ~E_7~0;~E_7~0 := 2; {89598#false} is VALID [2022-02-21 04:24:48,223 INFO L290 TraceCheckUtils]: 142: Hoare triple {89598#false} assume !(1 == ~E_8~0); {89598#false} is VALID [2022-02-21 04:24:48,223 INFO L290 TraceCheckUtils]: 143: Hoare triple {89598#false} assume !(1 == ~E_9~0); {89598#false} is VALID [2022-02-21 04:24:48,223 INFO L290 TraceCheckUtils]: 144: Hoare triple {89598#false} assume !(1 == ~E_10~0); {89598#false} is VALID [2022-02-21 04:24:48,223 INFO L290 TraceCheckUtils]: 145: Hoare triple {89598#false} assume !(1 == ~E_11~0); {89598#false} is VALID [2022-02-21 04:24:48,224 INFO L290 TraceCheckUtils]: 146: Hoare triple {89598#false} assume !(1 == ~E_12~0); {89598#false} is VALID [2022-02-21 04:24:48,224 INFO L290 TraceCheckUtils]: 147: Hoare triple {89598#false} assume { :end_inline_reset_delta_events } true; {89598#false} is VALID [2022-02-21 04:24:48,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:48,224 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:48,224 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [345734773] [2022-02-21 04:24:48,225 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [345734773] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:48,225 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:48,225 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:48,225 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1126997877] [2022-02-21 04:24:48,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:48,227 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:48,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:48,227 INFO L85 PathProgramCache]: Analyzing trace with hash 441756546, now seen corresponding path program 1 times [2022-02-21 04:24:48,228 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:48,228 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886936193] [2022-02-21 04:24:48,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:48,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:48,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:48,265 INFO L290 TraceCheckUtils]: 0: Hoare triple {89601#true} assume !false; {89601#true} is VALID [2022-02-21 04:24:48,265 INFO L290 TraceCheckUtils]: 1: Hoare triple {89601#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {89601#true} is VALID [2022-02-21 04:24:48,265 INFO L290 TraceCheckUtils]: 2: Hoare triple {89601#true} assume !false; {89601#true} is VALID [2022-02-21 04:24:48,266 INFO L290 TraceCheckUtils]: 3: Hoare triple {89601#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {89601#true} is VALID [2022-02-21 04:24:48,266 INFO L290 TraceCheckUtils]: 4: Hoare triple {89601#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {89601#true} is VALID [2022-02-21 04:24:48,266 INFO L290 TraceCheckUtils]: 5: Hoare triple {89601#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {89601#true} is VALID [2022-02-21 04:24:48,266 INFO L290 TraceCheckUtils]: 6: Hoare triple {89601#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {89601#true} is VALID [2022-02-21 04:24:48,266 INFO L290 TraceCheckUtils]: 7: Hoare triple {89601#true} assume !(0 != eval_~tmp~0#1); {89601#true} is VALID [2022-02-21 04:24:48,266 INFO L290 TraceCheckUtils]: 8: Hoare triple {89601#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {89601#true} is VALID [2022-02-21 04:24:48,266 INFO L290 TraceCheckUtils]: 9: Hoare triple {89601#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {89601#true} is VALID [2022-02-21 04:24:48,267 INFO L290 TraceCheckUtils]: 10: Hoare triple {89601#true} assume !(0 == ~M_E~0); {89601#true} is VALID [2022-02-21 04:24:48,267 INFO L290 TraceCheckUtils]: 11: Hoare triple {89601#true} assume !(0 == ~T1_E~0); {89601#true} is VALID [2022-02-21 04:24:48,267 INFO L290 TraceCheckUtils]: 12: Hoare triple {89601#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,267 INFO L290 TraceCheckUtils]: 13: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,268 INFO L290 TraceCheckUtils]: 14: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,268 INFO L290 TraceCheckUtils]: 15: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,268 INFO L290 TraceCheckUtils]: 16: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,269 INFO L290 TraceCheckUtils]: 17: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,269 INFO L290 TraceCheckUtils]: 18: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,269 INFO L290 TraceCheckUtils]: 19: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T9_E~0;~T9_E~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,270 INFO L290 TraceCheckUtils]: 20: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,270 INFO L290 TraceCheckUtils]: 21: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,270 INFO L290 TraceCheckUtils]: 22: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,270 INFO L290 TraceCheckUtils]: 23: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,271 INFO L290 TraceCheckUtils]: 24: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,271 INFO L290 TraceCheckUtils]: 25: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,271 INFO L290 TraceCheckUtils]: 26: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,272 INFO L290 TraceCheckUtils]: 27: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,272 INFO L290 TraceCheckUtils]: 28: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,272 INFO L290 TraceCheckUtils]: 29: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,273 INFO L290 TraceCheckUtils]: 30: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,273 INFO L290 TraceCheckUtils]: 31: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,273 INFO L290 TraceCheckUtils]: 32: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,274 INFO L290 TraceCheckUtils]: 33: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,274 INFO L290 TraceCheckUtils]: 34: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,274 INFO L290 TraceCheckUtils]: 35: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,275 INFO L290 TraceCheckUtils]: 36: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,275 INFO L290 TraceCheckUtils]: 37: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,275 INFO L290 TraceCheckUtils]: 38: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,276 INFO L290 TraceCheckUtils]: 39: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,276 INFO L290 TraceCheckUtils]: 40: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,276 INFO L290 TraceCheckUtils]: 41: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,277 INFO L290 TraceCheckUtils]: 42: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,277 INFO L290 TraceCheckUtils]: 43: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,277 INFO L290 TraceCheckUtils]: 44: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,277 INFO L290 TraceCheckUtils]: 45: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,278 INFO L290 TraceCheckUtils]: 46: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,278 INFO L290 TraceCheckUtils]: 47: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,278 INFO L290 TraceCheckUtils]: 48: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,279 INFO L290 TraceCheckUtils]: 49: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,279 INFO L290 TraceCheckUtils]: 50: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,279 INFO L290 TraceCheckUtils]: 51: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,280 INFO L290 TraceCheckUtils]: 52: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,280 INFO L290 TraceCheckUtils]: 53: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,280 INFO L290 TraceCheckUtils]: 54: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,281 INFO L290 TraceCheckUtils]: 55: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,281 INFO L290 TraceCheckUtils]: 56: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,281 INFO L290 TraceCheckUtils]: 57: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,282 INFO L290 TraceCheckUtils]: 58: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,282 INFO L290 TraceCheckUtils]: 59: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,282 INFO L290 TraceCheckUtils]: 60: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,282 INFO L290 TraceCheckUtils]: 61: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,283 INFO L290 TraceCheckUtils]: 62: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,283 INFO L290 TraceCheckUtils]: 63: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,283 INFO L290 TraceCheckUtils]: 64: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,284 INFO L290 TraceCheckUtils]: 65: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,284 INFO L290 TraceCheckUtils]: 66: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,284 INFO L290 TraceCheckUtils]: 67: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,284 INFO L290 TraceCheckUtils]: 68: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,285 INFO L290 TraceCheckUtils]: 69: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,285 INFO L290 TraceCheckUtils]: 70: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,285 INFO L290 TraceCheckUtils]: 71: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,286 INFO L290 TraceCheckUtils]: 72: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,286 INFO L290 TraceCheckUtils]: 73: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,286 INFO L290 TraceCheckUtils]: 74: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,287 INFO L290 TraceCheckUtils]: 75: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,287 INFO L290 TraceCheckUtils]: 76: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,287 INFO L290 TraceCheckUtils]: 77: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,287 INFO L290 TraceCheckUtils]: 78: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,288 INFO L290 TraceCheckUtils]: 79: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,288 INFO L290 TraceCheckUtils]: 80: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,288 INFO L290 TraceCheckUtils]: 81: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,289 INFO L290 TraceCheckUtils]: 82: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,289 INFO L290 TraceCheckUtils]: 83: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,289 INFO L290 TraceCheckUtils]: 84: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,290 INFO L290 TraceCheckUtils]: 85: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,290 INFO L290 TraceCheckUtils]: 86: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,290 INFO L290 TraceCheckUtils]: 87: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,291 INFO L290 TraceCheckUtils]: 88: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,291 INFO L290 TraceCheckUtils]: 89: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,291 INFO L290 TraceCheckUtils]: 90: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,292 INFO L290 TraceCheckUtils]: 91: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,292 INFO L290 TraceCheckUtils]: 92: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,292 INFO L290 TraceCheckUtils]: 93: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,293 INFO L290 TraceCheckUtils]: 94: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,293 INFO L290 TraceCheckUtils]: 95: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,293 INFO L290 TraceCheckUtils]: 96: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t10_pc~0); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,294 INFO L290 TraceCheckUtils]: 97: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,294 INFO L290 TraceCheckUtils]: 98: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,294 INFO L290 TraceCheckUtils]: 99: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,295 INFO L290 TraceCheckUtils]: 100: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,295 INFO L290 TraceCheckUtils]: 101: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,295 INFO L290 TraceCheckUtils]: 102: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,296 INFO L290 TraceCheckUtils]: 103: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,296 INFO L290 TraceCheckUtils]: 104: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,296 INFO L290 TraceCheckUtils]: 105: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,296 INFO L290 TraceCheckUtils]: 106: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,297 INFO L290 TraceCheckUtils]: 107: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,297 INFO L290 TraceCheckUtils]: 108: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t12_pc~0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,297 INFO L290 TraceCheckUtils]: 109: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,298 INFO L290 TraceCheckUtils]: 110: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,298 INFO L290 TraceCheckUtils]: 111: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,298 INFO L290 TraceCheckUtils]: 112: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,299 INFO L290 TraceCheckUtils]: 113: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,299 INFO L290 TraceCheckUtils]: 114: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,299 INFO L290 TraceCheckUtils]: 115: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T1_E~0); {89603#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:48,300 INFO L290 TraceCheckUtils]: 116: Hoare triple {89603#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {89602#false} is VALID [2022-02-21 04:24:48,300 INFO L290 TraceCheckUtils]: 117: Hoare triple {89602#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,300 INFO L290 TraceCheckUtils]: 118: Hoare triple {89602#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,300 INFO L290 TraceCheckUtils]: 119: Hoare triple {89602#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,300 INFO L290 TraceCheckUtils]: 120: Hoare triple {89602#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,300 INFO L290 TraceCheckUtils]: 121: Hoare triple {89602#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,300 INFO L290 TraceCheckUtils]: 122: Hoare triple {89602#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,301 INFO L290 TraceCheckUtils]: 123: Hoare triple {89602#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,301 INFO L290 TraceCheckUtils]: 124: Hoare triple {89602#false} assume !(1 == ~T10_E~0); {89602#false} is VALID [2022-02-21 04:24:48,301 INFO L290 TraceCheckUtils]: 125: Hoare triple {89602#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,301 INFO L290 TraceCheckUtils]: 126: Hoare triple {89602#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,301 INFO L290 TraceCheckUtils]: 127: Hoare triple {89602#false} assume 1 == ~E_1~0;~E_1~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,301 INFO L290 TraceCheckUtils]: 128: Hoare triple {89602#false} assume 1 == ~E_2~0;~E_2~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,301 INFO L290 TraceCheckUtils]: 129: Hoare triple {89602#false} assume 1 == ~E_3~0;~E_3~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,302 INFO L290 TraceCheckUtils]: 130: Hoare triple {89602#false} assume 1 == ~E_4~0;~E_4~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,302 INFO L290 TraceCheckUtils]: 131: Hoare triple {89602#false} assume 1 == ~E_5~0;~E_5~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,302 INFO L290 TraceCheckUtils]: 132: Hoare triple {89602#false} assume !(1 == ~E_6~0); {89602#false} is VALID [2022-02-21 04:24:48,302 INFO L290 TraceCheckUtils]: 133: Hoare triple {89602#false} assume 1 == ~E_7~0;~E_7~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,302 INFO L290 TraceCheckUtils]: 134: Hoare triple {89602#false} assume 1 == ~E_8~0;~E_8~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,302 INFO L290 TraceCheckUtils]: 135: Hoare triple {89602#false} assume 1 == ~E_9~0;~E_9~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,302 INFO L290 TraceCheckUtils]: 136: Hoare triple {89602#false} assume 1 == ~E_10~0;~E_10~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,302 INFO L290 TraceCheckUtils]: 137: Hoare triple {89602#false} assume 1 == ~E_11~0;~E_11~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,303 INFO L290 TraceCheckUtils]: 138: Hoare triple {89602#false} assume 1 == ~E_12~0;~E_12~0 := 2; {89602#false} is VALID [2022-02-21 04:24:48,303 INFO L290 TraceCheckUtils]: 139: Hoare triple {89602#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {89602#false} is VALID [2022-02-21 04:24:48,303 INFO L290 TraceCheckUtils]: 140: Hoare triple {89602#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {89602#false} is VALID [2022-02-21 04:24:48,303 INFO L290 TraceCheckUtils]: 141: Hoare triple {89602#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {89602#false} is VALID [2022-02-21 04:24:48,303 INFO L290 TraceCheckUtils]: 142: Hoare triple {89602#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {89602#false} is VALID [2022-02-21 04:24:48,303 INFO L290 TraceCheckUtils]: 143: Hoare triple {89602#false} assume !(0 == start_simulation_~tmp~3#1); {89602#false} is VALID [2022-02-21 04:24:48,303 INFO L290 TraceCheckUtils]: 144: Hoare triple {89602#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {89602#false} is VALID [2022-02-21 04:24:48,304 INFO L290 TraceCheckUtils]: 145: Hoare triple {89602#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {89602#false} is VALID [2022-02-21 04:24:48,304 INFO L290 TraceCheckUtils]: 146: Hoare triple {89602#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {89602#false} is VALID [2022-02-21 04:24:48,304 INFO L290 TraceCheckUtils]: 147: Hoare triple {89602#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {89602#false} is VALID [2022-02-21 04:24:48,304 INFO L290 TraceCheckUtils]: 148: Hoare triple {89602#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {89602#false} is VALID [2022-02-21 04:24:48,304 INFO L290 TraceCheckUtils]: 149: Hoare triple {89602#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {89602#false} is VALID [2022-02-21 04:24:48,304 INFO L290 TraceCheckUtils]: 150: Hoare triple {89602#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {89602#false} is VALID [2022-02-21 04:24:48,304 INFO L290 TraceCheckUtils]: 151: Hoare triple {89602#false} assume !(0 != start_simulation_~tmp___0~1#1); {89602#false} is VALID [2022-02-21 04:24:48,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:48,305 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:48,305 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886936193] [2022-02-21 04:24:48,305 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886936193] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:48,305 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:48,306 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:48,306 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [161370608] [2022-02-21 04:24:48,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:48,306 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:48,306 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:48,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:48,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:48,307 INFO L87 Difference]: Start difference. First operand 1688 states and 2488 transitions. cyclomatic complexity: 801 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:51,389 INFO L93 Difference]: Finished difference Result 3238 states and 4766 transitions. [2022-02-21 04:24:51,390 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:51,390 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,488 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:51,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3238 states and 4766 transitions. [2022-02-21 04:24:51,787 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3054 [2022-02-21 04:24:52,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3238 states to 3238 states and 4766 transitions. [2022-02-21 04:24:52,112 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3238 [2022-02-21 04:24:52,113 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3238 [2022-02-21 04:24:52,113 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3238 states and 4766 transitions. [2022-02-21 04:24:52,115 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:52,115 INFO L681 BuchiCegarLoop]: Abstraction has 3238 states and 4766 transitions. [2022-02-21 04:24:52,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3238 states and 4766 transitions. [2022-02-21 04:24:52,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3238 to 3238. [2022-02-21 04:24:52,149 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:52,152 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3238 states and 4766 transitions. Second operand has 3238 states, 3238 states have (on average 1.4718962322421247) internal successors, (4766), 3237 states have internal predecessors, (4766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:52,154 INFO L74 IsIncluded]: Start isIncluded. First operand 3238 states and 4766 transitions. Second operand has 3238 states, 3238 states have (on average 1.4718962322421247) internal successors, (4766), 3237 states have internal predecessors, (4766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:52,157 INFO L87 Difference]: Start difference. First operand 3238 states and 4766 transitions. Second operand has 3238 states, 3238 states have (on average 1.4718962322421247) internal successors, (4766), 3237 states have internal predecessors, (4766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:52,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:52,448 INFO L93 Difference]: Finished difference Result 3238 states and 4766 transitions. [2022-02-21 04:24:52,448 INFO L276 IsEmpty]: Start isEmpty. Operand 3238 states and 4766 transitions. [2022-02-21 04:24:52,452 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:52,452 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:52,457 INFO L74 IsIncluded]: Start isIncluded. First operand has 3238 states, 3238 states have (on average 1.4718962322421247) internal successors, (4766), 3237 states have internal predecessors, (4766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3238 states and 4766 transitions. [2022-02-21 04:24:52,462 INFO L87 Difference]: Start difference. First operand has 3238 states, 3238 states have (on average 1.4718962322421247) internal successors, (4766), 3237 states have internal predecessors, (4766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3238 states and 4766 transitions. [2022-02-21 04:24:52,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:52,779 INFO L93 Difference]: Finished difference Result 3238 states and 4766 transitions. [2022-02-21 04:24:52,779 INFO L276 IsEmpty]: Start isEmpty. Operand 3238 states and 4766 transitions. [2022-02-21 04:24:52,782 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:52,782 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:52,783 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:52,783 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:52,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3238 states, 3238 states have (on average 1.4718962322421247) internal successors, (4766), 3237 states have internal predecessors, (4766), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:53,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3238 states to 3238 states and 4766 transitions. [2022-02-21 04:24:53,031 INFO L704 BuchiCegarLoop]: Abstraction has 3238 states and 4766 transitions. [2022-02-21 04:24:53,031 INFO L587 BuchiCegarLoop]: Abstraction has 3238 states and 4766 transitions. [2022-02-21 04:24:53,031 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:24:53,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3238 states and 4766 transitions. [2022-02-21 04:24:53,036 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3054 [2022-02-21 04:24:53,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:53,037 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:53,038 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:53,038 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:53,038 INFO L791 eck$LassoCheckResult]: Stem: 93651#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 93652#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 94530#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94003#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 93802#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 93803#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93888#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94205#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94329#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94330#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 93098#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 93099#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 94266#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 93695#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 93696#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 93602#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 93603#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 93998#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93342#L1174 assume !(0 == ~M_E~0); 93343#L1174-2 assume !(0 == ~T1_E~0); 93194#L1179-1 assume !(0 == ~T2_E~0); 93096#L1184-1 assume !(0 == ~T3_E~0); 93097#L1189-1 assume !(0 == ~T4_E~0); 93135#L1194-1 assume !(0 == ~T5_E~0); 93235#L1199-1 assume !(0 == ~T6_E~0); 94142#L1204-1 assume !(0 == ~T7_E~0); 94059#L1209-1 assume !(0 == ~T8_E~0); 94060#L1214-1 assume !(0 == ~T9_E~0); 94461#L1219-1 assume !(0 == ~T10_E~0); 94562#L1224-1 assume !(0 == ~T11_E~0); 93461#L1229-1 assume !(0 == ~T12_E~0); 93023#L1234-1 assume !(0 == ~E_1~0); 93024#L1239-1 assume !(0 == ~E_2~0); 93057#L1244-1 assume !(0 == ~E_3~0); 93058#L1249-1 assume !(0 == ~E_4~0); 93719#L1254-1 assume 0 == ~E_5~0;~E_5~0 := 1; 92951#L1259-1 assume !(0 == ~E_6~0); 92906#L1264-1 assume !(0 == ~E_7~0); 92907#L1269-1 assume !(0 == ~E_8~0); 94571#L1274-1 assume !(0 == ~E_9~0); 94487#L1279-1 assume !(0 == ~E_10~0); 93139#L1284-1 assume !(0 == ~E_11~0); 93140#L1289-1 assume !(0 == ~E_12~0); 93771#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93772#L566 assume 1 == ~m_pc~0; 92923#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 92924#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94089#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94090#L1455 assume !(0 != activate_threads_~tmp~1#1); 93369#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93370#L585 assume 1 == ~t1_pc~0; 93018#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 93019#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94027#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 94028#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 94513#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94510#L604 assume !(1 == ~t2_pc~0); 94110#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 94111#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 93634#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 93635#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 94291#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94292#L623 assume 1 == ~t3_pc~0; 93547#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 92887#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93699#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 93700#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 94325#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 92920#L642 assume !(1 == ~t4_pc~0); 92921#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 93386#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93387#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 92994#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 92995#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94122#L661 assume 1 == ~t5_pc~0; 93157#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 93158#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 93119#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 93120#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 94153#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94154#L680 assume !(1 == ~t6_pc~0); 93580#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 93581#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 93844#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 93845#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 94392#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94508#L699 assume 1 == ~t7_pc~0; 93977#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 93978#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 93147#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 93148#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 93874#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 93773#L718 assume !(1 == ~t8_pc~0); 93774#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 93133#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 93134#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 93177#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 93178#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 93309#L737 assume 1 == ~t9_pc~0; 94188#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 93445#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94053#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 94054#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 93620#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 93621#L756 assume 1 == ~t10_pc~0; 94213#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 93866#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 92850#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 92851#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 93426#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 93427#L775 assume !(1 == ~t11_pc~0); 93683#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 93684#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 93306#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 93067#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 93068#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 93254#L794 assume 1 == ~t12_pc~0; 93095#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 93072#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 94284#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 93222#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 93223#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93702#L1307 assume !(1 == ~M_E~0); 93703#L1307-2 assume !(1 == ~T1_E~0); 93814#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94529#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94908#L1322-1 assume !(1 == ~T4_E~0); 94906#L1327-1 assume !(1 == ~T5_E~0); 94875#L1332-1 assume !(1 == ~T6_E~0); 94864#L1337-1 assume !(1 == ~T7_E~0); 94863#L1342-1 assume !(1 == ~T8_E~0); 94861#L1347-1 assume !(1 == ~T9_E~0); 94485#L1352-1 assume !(1 == ~T10_E~0); 94858#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94856#L1362-1 assume !(1 == ~T12_E~0); 94854#L1367-1 assume !(1 == ~E_1~0); 94852#L1372-1 assume !(1 == ~E_2~0); 94664#L1377-1 assume !(1 == ~E_3~0); 94650#L1382-1 assume !(1 == ~E_4~0); 94648#L1387-1 assume !(1 == ~E_5~0); 94646#L1392-1 assume !(1 == ~E_6~0); 94644#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 94642#L1402-1 assume !(1 == ~E_8~0); 94641#L1407-1 assume !(1 == ~E_9~0); 94638#L1412-1 assume !(1 == ~E_10~0); 94636#L1417-1 assume !(1 == ~E_11~0); 94627#L1422-1 assume !(1 == ~E_12~0); 94614#L1427-1 assume { :end_inline_reset_delta_events } true; 94610#L1768-2 [2022-02-21 04:24:53,039 INFO L793 eck$LassoCheckResult]: Loop: 94610#L1768-2 assume !false; 94605#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 94602#L1149 assume !false; 94601#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 94593#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 94587#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 94586#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 94584#L976 assume !(0 != eval_~tmp~0#1); 94523#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94524#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 94583#L1174-3 assume !(0 == ~M_E~0); 94582#L1174-5 assume !(0 == ~T1_E~0); 94581#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 94512#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 94224#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 93861#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 93212#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 93213#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 93451#L1209-3 assume !(0 == ~T8_E~0); 92871#L1214-3 assume !(0 == ~T9_E~0); 92872#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 93632#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 93633#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 93649#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 93059#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 93060#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 93503#L1249-3 assume !(0 == ~E_4~0); 93966#L1254-3 assume 0 == ~E_5~0;~E_5~0 := 1; 94457#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 94087#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 93065#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 93066#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 94484#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 93630#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 93631#L1289-3 assume !(0 == ~E_12~0); 93619#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93293#L566-39 assume !(1 == ~m_pc~0); 93295#L566-41 is_master_triggered_~__retres1~0#1 := 0; 93899#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93608#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 93609#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 94163#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94164#L585-39 assume !(1 == ~t1_pc~0); 93301#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 93302#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93377#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 93378#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 94197#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93879#L604-39 assume !(1 == ~t2_pc~0); 93881#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 93509#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 93510#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 93930#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 93931#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 93492#L623-39 assume !(1 == ~t3_pc~0); 92889#L623-41 is_transmit3_triggered_~__retres1~3#1 := 0; 92890#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94181#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 93344#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 93345#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94128#L642-39 assume 1 == ~t4_pc~0; 93689#L643-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 93690#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93216#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 93217#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 94334#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 93265#L661-39 assume !(1 == ~t5_pc~0); 92896#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 92897#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94276#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94277#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 94184#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94185#L680-39 assume !(1 == ~t6_pc~0); 92960#L680-41 is_transmit6_triggered_~__retres1~6#1 := 0; 92959#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94113#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 93424#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 93425#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94462#L699-39 assume 1 == ~t7_pc~0; 93863#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 93583#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 93584#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 94286#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 94410#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94408#L718-39 assume 1 == ~t8_pc~0; 93777#L719-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 93778#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 93710#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 93711#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 94018#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 93987#L737-39 assume 1 == ~t9_pc~0; 93405#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 93406#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 93697#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 94486#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 94384#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 94326#L756-39 assume 1 == ~t10_pc~0; 94327#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 93790#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 93532#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 93533#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 93667#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 93005#L775-39 assume !(1 == ~t11_pc~0); 93007#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 93660#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 93661#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 94560#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 94080#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 93718#L794-39 assume 1 == ~t12_pc~0; 93408#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 93402#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 94239#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 94135#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 92947#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92948#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 94438#L1307-5 assume !(1 == ~T1_E~0); 94439#L1312-3 assume !(1 == ~T2_E~0); 94569#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94151#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94152#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 93086#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 93055#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 93056#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 93806#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 93932#L1352-3 assume !(1 == ~T10_E~0); 93933#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94390#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 94580#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 94546#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 92881#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 92882#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 93516#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 93517#L1392-3 assume !(1 == ~E_6~0); 94250#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 94502#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 93898#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 93171#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 93172#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 93822#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 93823#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 93181#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 93182#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 94058#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 93903#L1787 assume !(0 == start_simulation_~tmp~3#1); 93904#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 94657#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 94649#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 94647#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 94645#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 94643#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 94628#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 94615#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 94610#L1768-2 [2022-02-21 04:24:53,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:53,039 INFO L85 PathProgramCache]: Analyzing trace with hash -1694374055, now seen corresponding path program 1 times [2022-02-21 04:24:53,039 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:53,040 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247138521] [2022-02-21 04:24:53,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:53,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:53,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:53,092 INFO L290 TraceCheckUtils]: 0: Hoare triple {102561#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,092 INFO L290 TraceCheckUtils]: 1: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,092 INFO L290 TraceCheckUtils]: 2: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,093 INFO L290 TraceCheckUtils]: 3: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,093 INFO L290 TraceCheckUtils]: 4: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,093 INFO L290 TraceCheckUtils]: 5: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,094 INFO L290 TraceCheckUtils]: 6: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,094 INFO L290 TraceCheckUtils]: 7: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,094 INFO L290 TraceCheckUtils]: 8: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,094 INFO L290 TraceCheckUtils]: 9: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,095 INFO L290 TraceCheckUtils]: 10: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,095 INFO L290 TraceCheckUtils]: 11: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,095 INFO L290 TraceCheckUtils]: 12: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,095 INFO L290 TraceCheckUtils]: 13: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,096 INFO L290 TraceCheckUtils]: 14: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,096 INFO L290 TraceCheckUtils]: 15: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,096 INFO L290 TraceCheckUtils]: 16: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,096 INFO L290 TraceCheckUtils]: 17: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,097 INFO L290 TraceCheckUtils]: 18: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume !(0 == ~M_E~0); {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,098 INFO L290 TraceCheckUtils]: 19: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume !(0 == ~T1_E~0); {102563#(= ~T2_E~0 ~E_5~0)} is VALID [2022-02-21 04:24:53,098 INFO L290 TraceCheckUtils]: 20: Hoare triple {102563#(= ~T2_E~0 ~E_5~0)} assume !(0 == ~T2_E~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,098 INFO L290 TraceCheckUtils]: 21: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~T3_E~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,099 INFO L290 TraceCheckUtils]: 22: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~T4_E~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,099 INFO L290 TraceCheckUtils]: 23: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~T5_E~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,099 INFO L290 TraceCheckUtils]: 24: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~T6_E~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,099 INFO L290 TraceCheckUtils]: 25: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~T7_E~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,099 INFO L290 TraceCheckUtils]: 26: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~T8_E~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,100 INFO L290 TraceCheckUtils]: 27: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~T9_E~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,100 INFO L290 TraceCheckUtils]: 28: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~T10_E~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,100 INFO L290 TraceCheckUtils]: 29: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~T11_E~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,100 INFO L290 TraceCheckUtils]: 30: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~T12_E~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,101 INFO L290 TraceCheckUtils]: 31: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~E_1~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,101 INFO L290 TraceCheckUtils]: 32: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~E_2~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,101 INFO L290 TraceCheckUtils]: 33: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~E_3~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,101 INFO L290 TraceCheckUtils]: 34: Hoare triple {102564#(not (= ~E_5~0 0))} assume !(0 == ~E_4~0); {102564#(not (= ~E_5~0 0))} is VALID [2022-02-21 04:24:53,102 INFO L290 TraceCheckUtils]: 35: Hoare triple {102564#(not (= ~E_5~0 0))} assume 0 == ~E_5~0;~E_5~0 := 1; {102562#false} is VALID [2022-02-21 04:24:53,102 INFO L290 TraceCheckUtils]: 36: Hoare triple {102562#false} assume !(0 == ~E_6~0); {102562#false} is VALID [2022-02-21 04:24:53,102 INFO L290 TraceCheckUtils]: 37: Hoare triple {102562#false} assume !(0 == ~E_7~0); {102562#false} is VALID [2022-02-21 04:24:53,102 INFO L290 TraceCheckUtils]: 38: Hoare triple {102562#false} assume !(0 == ~E_8~0); {102562#false} is VALID [2022-02-21 04:24:53,102 INFO L290 TraceCheckUtils]: 39: Hoare triple {102562#false} assume !(0 == ~E_9~0); {102562#false} is VALID [2022-02-21 04:24:53,102 INFO L290 TraceCheckUtils]: 40: Hoare triple {102562#false} assume !(0 == ~E_10~0); {102562#false} is VALID [2022-02-21 04:24:53,102 INFO L290 TraceCheckUtils]: 41: Hoare triple {102562#false} assume !(0 == ~E_11~0); {102562#false} is VALID [2022-02-21 04:24:53,102 INFO L290 TraceCheckUtils]: 42: Hoare triple {102562#false} assume !(0 == ~E_12~0); {102562#false} is VALID [2022-02-21 04:24:53,103 INFO L290 TraceCheckUtils]: 43: Hoare triple {102562#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {102562#false} is VALID [2022-02-21 04:24:53,103 INFO L290 TraceCheckUtils]: 44: Hoare triple {102562#false} assume 1 == ~m_pc~0; {102562#false} is VALID [2022-02-21 04:24:53,103 INFO L290 TraceCheckUtils]: 45: Hoare triple {102562#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {102562#false} is VALID [2022-02-21 04:24:53,103 INFO L290 TraceCheckUtils]: 46: Hoare triple {102562#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {102562#false} is VALID [2022-02-21 04:24:53,103 INFO L290 TraceCheckUtils]: 47: Hoare triple {102562#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {102562#false} is VALID [2022-02-21 04:24:53,103 INFO L290 TraceCheckUtils]: 48: Hoare triple {102562#false} assume !(0 != activate_threads_~tmp~1#1); {102562#false} is VALID [2022-02-21 04:24:53,103 INFO L290 TraceCheckUtils]: 49: Hoare triple {102562#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {102562#false} is VALID [2022-02-21 04:24:53,103 INFO L290 TraceCheckUtils]: 50: Hoare triple {102562#false} assume 1 == ~t1_pc~0; {102562#false} is VALID [2022-02-21 04:24:53,103 INFO L290 TraceCheckUtils]: 51: Hoare triple {102562#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {102562#false} is VALID [2022-02-21 04:24:53,104 INFO L290 TraceCheckUtils]: 52: Hoare triple {102562#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {102562#false} is VALID [2022-02-21 04:24:53,104 INFO L290 TraceCheckUtils]: 53: Hoare triple {102562#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {102562#false} is VALID [2022-02-21 04:24:53,104 INFO L290 TraceCheckUtils]: 54: Hoare triple {102562#false} assume !(0 != activate_threads_~tmp___0~0#1); {102562#false} is VALID [2022-02-21 04:24:53,104 INFO L290 TraceCheckUtils]: 55: Hoare triple {102562#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {102562#false} is VALID [2022-02-21 04:24:53,104 INFO L290 TraceCheckUtils]: 56: Hoare triple {102562#false} assume !(1 == ~t2_pc~0); {102562#false} is VALID [2022-02-21 04:24:53,104 INFO L290 TraceCheckUtils]: 57: Hoare triple {102562#false} is_transmit2_triggered_~__retres1~2#1 := 0; {102562#false} is VALID [2022-02-21 04:24:53,104 INFO L290 TraceCheckUtils]: 58: Hoare triple {102562#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {102562#false} is VALID [2022-02-21 04:24:53,104 INFO L290 TraceCheckUtils]: 59: Hoare triple {102562#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {102562#false} is VALID [2022-02-21 04:24:53,104 INFO L290 TraceCheckUtils]: 60: Hoare triple {102562#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {102562#false} is VALID [2022-02-21 04:24:53,105 INFO L290 TraceCheckUtils]: 61: Hoare triple {102562#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {102562#false} is VALID [2022-02-21 04:24:53,105 INFO L290 TraceCheckUtils]: 62: Hoare triple {102562#false} assume 1 == ~t3_pc~0; {102562#false} is VALID [2022-02-21 04:24:53,105 INFO L290 TraceCheckUtils]: 63: Hoare triple {102562#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {102562#false} is VALID [2022-02-21 04:24:53,105 INFO L290 TraceCheckUtils]: 64: Hoare triple {102562#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {102562#false} is VALID [2022-02-21 04:24:53,105 INFO L290 TraceCheckUtils]: 65: Hoare triple {102562#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {102562#false} is VALID [2022-02-21 04:24:53,105 INFO L290 TraceCheckUtils]: 66: Hoare triple {102562#false} assume !(0 != activate_threads_~tmp___2~0#1); {102562#false} is VALID [2022-02-21 04:24:53,105 INFO L290 TraceCheckUtils]: 67: Hoare triple {102562#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {102562#false} is VALID [2022-02-21 04:24:53,105 INFO L290 TraceCheckUtils]: 68: Hoare triple {102562#false} assume !(1 == ~t4_pc~0); {102562#false} is VALID [2022-02-21 04:24:53,105 INFO L290 TraceCheckUtils]: 69: Hoare triple {102562#false} is_transmit4_triggered_~__retres1~4#1 := 0; {102562#false} is VALID [2022-02-21 04:24:53,106 INFO L290 TraceCheckUtils]: 70: Hoare triple {102562#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {102562#false} is VALID [2022-02-21 04:24:53,106 INFO L290 TraceCheckUtils]: 71: Hoare triple {102562#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {102562#false} is VALID [2022-02-21 04:24:53,106 INFO L290 TraceCheckUtils]: 72: Hoare triple {102562#false} assume !(0 != activate_threads_~tmp___3~0#1); {102562#false} is VALID [2022-02-21 04:24:53,106 INFO L290 TraceCheckUtils]: 73: Hoare triple {102562#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {102562#false} is VALID [2022-02-21 04:24:53,106 INFO L290 TraceCheckUtils]: 74: Hoare triple {102562#false} assume 1 == ~t5_pc~0; {102562#false} is VALID [2022-02-21 04:24:53,106 INFO L290 TraceCheckUtils]: 75: Hoare triple {102562#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {102562#false} is VALID [2022-02-21 04:24:53,106 INFO L290 TraceCheckUtils]: 76: Hoare triple {102562#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {102562#false} is VALID [2022-02-21 04:24:53,106 INFO L290 TraceCheckUtils]: 77: Hoare triple {102562#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {102562#false} is VALID [2022-02-21 04:24:53,106 INFO L290 TraceCheckUtils]: 78: Hoare triple {102562#false} assume !(0 != activate_threads_~tmp___4~0#1); {102562#false} is VALID [2022-02-21 04:24:53,106 INFO L290 TraceCheckUtils]: 79: Hoare triple {102562#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {102562#false} is VALID [2022-02-21 04:24:53,107 INFO L290 TraceCheckUtils]: 80: Hoare triple {102562#false} assume !(1 == ~t6_pc~0); {102562#false} is VALID [2022-02-21 04:24:53,107 INFO L290 TraceCheckUtils]: 81: Hoare triple {102562#false} is_transmit6_triggered_~__retres1~6#1 := 0; {102562#false} is VALID [2022-02-21 04:24:53,107 INFO L290 TraceCheckUtils]: 82: Hoare triple {102562#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {102562#false} is VALID [2022-02-21 04:24:53,107 INFO L290 TraceCheckUtils]: 83: Hoare triple {102562#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {102562#false} is VALID [2022-02-21 04:24:53,107 INFO L290 TraceCheckUtils]: 84: Hoare triple {102562#false} assume !(0 != activate_threads_~tmp___5~0#1); {102562#false} is VALID [2022-02-21 04:24:53,107 INFO L290 TraceCheckUtils]: 85: Hoare triple {102562#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {102562#false} is VALID [2022-02-21 04:24:53,107 INFO L290 TraceCheckUtils]: 86: Hoare triple {102562#false} assume 1 == ~t7_pc~0; {102562#false} is VALID [2022-02-21 04:24:53,107 INFO L290 TraceCheckUtils]: 87: Hoare triple {102562#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {102562#false} is VALID [2022-02-21 04:24:53,107 INFO L290 TraceCheckUtils]: 88: Hoare triple {102562#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {102562#false} is VALID [2022-02-21 04:24:53,108 INFO L290 TraceCheckUtils]: 89: Hoare triple {102562#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {102562#false} is VALID [2022-02-21 04:24:53,108 INFO L290 TraceCheckUtils]: 90: Hoare triple {102562#false} assume !(0 != activate_threads_~tmp___6~0#1); {102562#false} is VALID [2022-02-21 04:24:53,108 INFO L290 TraceCheckUtils]: 91: Hoare triple {102562#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {102562#false} is VALID [2022-02-21 04:24:53,108 INFO L290 TraceCheckUtils]: 92: Hoare triple {102562#false} assume !(1 == ~t8_pc~0); {102562#false} is VALID [2022-02-21 04:24:53,108 INFO L290 TraceCheckUtils]: 93: Hoare triple {102562#false} is_transmit8_triggered_~__retres1~8#1 := 0; {102562#false} is VALID [2022-02-21 04:24:53,108 INFO L290 TraceCheckUtils]: 94: Hoare triple {102562#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {102562#false} is VALID [2022-02-21 04:24:53,108 INFO L290 TraceCheckUtils]: 95: Hoare triple {102562#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {102562#false} is VALID [2022-02-21 04:24:53,108 INFO L290 TraceCheckUtils]: 96: Hoare triple {102562#false} assume !(0 != activate_threads_~tmp___7~0#1); {102562#false} is VALID [2022-02-21 04:24:53,108 INFO L290 TraceCheckUtils]: 97: Hoare triple {102562#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {102562#false} is VALID [2022-02-21 04:24:53,109 INFO L290 TraceCheckUtils]: 98: Hoare triple {102562#false} assume 1 == ~t9_pc~0; {102562#false} is VALID [2022-02-21 04:24:53,109 INFO L290 TraceCheckUtils]: 99: Hoare triple {102562#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {102562#false} is VALID [2022-02-21 04:24:53,109 INFO L290 TraceCheckUtils]: 100: Hoare triple {102562#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {102562#false} is VALID [2022-02-21 04:24:53,109 INFO L290 TraceCheckUtils]: 101: Hoare triple {102562#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {102562#false} is VALID [2022-02-21 04:24:53,109 INFO L290 TraceCheckUtils]: 102: Hoare triple {102562#false} assume !(0 != activate_threads_~tmp___8~0#1); {102562#false} is VALID [2022-02-21 04:24:53,109 INFO L290 TraceCheckUtils]: 103: Hoare triple {102562#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {102562#false} is VALID [2022-02-21 04:24:53,109 INFO L290 TraceCheckUtils]: 104: Hoare triple {102562#false} assume 1 == ~t10_pc~0; {102562#false} is VALID [2022-02-21 04:24:53,109 INFO L290 TraceCheckUtils]: 105: Hoare triple {102562#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {102562#false} is VALID [2022-02-21 04:24:53,109 INFO L290 TraceCheckUtils]: 106: Hoare triple {102562#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {102562#false} is VALID [2022-02-21 04:24:53,110 INFO L290 TraceCheckUtils]: 107: Hoare triple {102562#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {102562#false} is VALID [2022-02-21 04:24:53,110 INFO L290 TraceCheckUtils]: 108: Hoare triple {102562#false} assume !(0 != activate_threads_~tmp___9~0#1); {102562#false} is VALID [2022-02-21 04:24:53,110 INFO L290 TraceCheckUtils]: 109: Hoare triple {102562#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {102562#false} is VALID [2022-02-21 04:24:53,110 INFO L290 TraceCheckUtils]: 110: Hoare triple {102562#false} assume !(1 == ~t11_pc~0); {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 111: Hoare triple {102562#false} is_transmit11_triggered_~__retres1~11#1 := 0; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 112: Hoare triple {102562#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 113: Hoare triple {102562#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 114: Hoare triple {102562#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 115: Hoare triple {102562#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 116: Hoare triple {102562#false} assume 1 == ~t12_pc~0; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 117: Hoare triple {102562#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 118: Hoare triple {102562#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 119: Hoare triple {102562#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 120: Hoare triple {102562#false} assume !(0 != activate_threads_~tmp___11~0#1); {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 121: Hoare triple {102562#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 122: Hoare triple {102562#false} assume !(1 == ~M_E~0); {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 123: Hoare triple {102562#false} assume !(1 == ~T1_E~0); {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 124: Hoare triple {102562#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 125: Hoare triple {102562#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 126: Hoare triple {102562#false} assume !(1 == ~T4_E~0); {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 127: Hoare triple {102562#false} assume !(1 == ~T5_E~0); {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 128: Hoare triple {102562#false} assume !(1 == ~T6_E~0); {102562#false} is VALID [2022-02-21 04:24:53,111 INFO L290 TraceCheckUtils]: 129: Hoare triple {102562#false} assume !(1 == ~T7_E~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 130: Hoare triple {102562#false} assume !(1 == ~T8_E~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 131: Hoare triple {102562#false} assume !(1 == ~T9_E~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 132: Hoare triple {102562#false} assume !(1 == ~T10_E~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 133: Hoare triple {102562#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 134: Hoare triple {102562#false} assume !(1 == ~T12_E~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 135: Hoare triple {102562#false} assume !(1 == ~E_1~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 136: Hoare triple {102562#false} assume !(1 == ~E_2~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 137: Hoare triple {102562#false} assume !(1 == ~E_3~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 138: Hoare triple {102562#false} assume !(1 == ~E_4~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 139: Hoare triple {102562#false} assume !(1 == ~E_5~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 140: Hoare triple {102562#false} assume !(1 == ~E_6~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 141: Hoare triple {102562#false} assume 1 == ~E_7~0;~E_7~0 := 2; {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 142: Hoare triple {102562#false} assume !(1 == ~E_8~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 143: Hoare triple {102562#false} assume !(1 == ~E_9~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 144: Hoare triple {102562#false} assume !(1 == ~E_10~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 145: Hoare triple {102562#false} assume !(1 == ~E_11~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 146: Hoare triple {102562#false} assume !(1 == ~E_12~0); {102562#false} is VALID [2022-02-21 04:24:53,112 INFO L290 TraceCheckUtils]: 147: Hoare triple {102562#false} assume { :end_inline_reset_delta_events } true; {102562#false} is VALID [2022-02-21 04:24:53,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:53,114 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:53,114 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247138521] [2022-02-21 04:24:53,114 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [247138521] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:53,114 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:53,114 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:53,114 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1568808567] [2022-02-21 04:24:53,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:53,115 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:53,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:53,115 INFO L85 PathProgramCache]: Analyzing trace with hash 1814400388, now seen corresponding path program 1 times [2022-02-21 04:24:53,115 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:53,115 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [392808963] [2022-02-21 04:24:53,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:53,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:53,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:53,164 INFO L290 TraceCheckUtils]: 0: Hoare triple {102565#true} assume !false; {102565#true} is VALID [2022-02-21 04:24:53,164 INFO L290 TraceCheckUtils]: 1: Hoare triple {102565#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {102565#true} is VALID [2022-02-21 04:24:53,164 INFO L290 TraceCheckUtils]: 2: Hoare triple {102565#true} assume !false; {102565#true} is VALID [2022-02-21 04:24:53,164 INFO L290 TraceCheckUtils]: 3: Hoare triple {102565#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {102565#true} is VALID [2022-02-21 04:24:53,164 INFO L290 TraceCheckUtils]: 4: Hoare triple {102565#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {102565#true} is VALID [2022-02-21 04:24:53,164 INFO L290 TraceCheckUtils]: 5: Hoare triple {102565#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {102565#true} is VALID [2022-02-21 04:24:53,165 INFO L290 TraceCheckUtils]: 6: Hoare triple {102565#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {102565#true} is VALID [2022-02-21 04:24:53,165 INFO L290 TraceCheckUtils]: 7: Hoare triple {102565#true} assume !(0 != eval_~tmp~0#1); {102565#true} is VALID [2022-02-21 04:24:53,165 INFO L290 TraceCheckUtils]: 8: Hoare triple {102565#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {102565#true} is VALID [2022-02-21 04:24:53,165 INFO L290 TraceCheckUtils]: 9: Hoare triple {102565#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {102565#true} is VALID [2022-02-21 04:24:53,165 INFO L290 TraceCheckUtils]: 10: Hoare triple {102565#true} assume !(0 == ~M_E~0); {102565#true} is VALID [2022-02-21 04:24:53,165 INFO L290 TraceCheckUtils]: 11: Hoare triple {102565#true} assume !(0 == ~T1_E~0); {102565#true} is VALID [2022-02-21 04:24:53,166 INFO L290 TraceCheckUtils]: 12: Hoare triple {102565#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,166 INFO L290 TraceCheckUtils]: 13: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,166 INFO L290 TraceCheckUtils]: 14: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,166 INFO L290 TraceCheckUtils]: 15: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,167 INFO L290 TraceCheckUtils]: 16: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,167 INFO L290 TraceCheckUtils]: 17: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,167 INFO L290 TraceCheckUtils]: 18: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,168 INFO L290 TraceCheckUtils]: 19: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T9_E~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,168 INFO L290 TraceCheckUtils]: 20: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,168 INFO L290 TraceCheckUtils]: 21: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,168 INFO L290 TraceCheckUtils]: 22: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,169 INFO L290 TraceCheckUtils]: 23: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,169 INFO L290 TraceCheckUtils]: 24: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,169 INFO L290 TraceCheckUtils]: 25: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,170 INFO L290 TraceCheckUtils]: 26: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,170 INFO L290 TraceCheckUtils]: 27: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,170 INFO L290 TraceCheckUtils]: 28: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,170 INFO L290 TraceCheckUtils]: 29: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,171 INFO L290 TraceCheckUtils]: 30: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,171 INFO L290 TraceCheckUtils]: 31: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,171 INFO L290 TraceCheckUtils]: 32: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,172 INFO L290 TraceCheckUtils]: 33: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,172 INFO L290 TraceCheckUtils]: 34: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,172 INFO L290 TraceCheckUtils]: 35: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,172 INFO L290 TraceCheckUtils]: 36: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,173 INFO L290 TraceCheckUtils]: 37: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,173 INFO L290 TraceCheckUtils]: 38: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,173 INFO L290 TraceCheckUtils]: 39: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,174 INFO L290 TraceCheckUtils]: 40: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,174 INFO L290 TraceCheckUtils]: 41: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,174 INFO L290 TraceCheckUtils]: 42: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,174 INFO L290 TraceCheckUtils]: 43: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,175 INFO L290 TraceCheckUtils]: 44: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,175 INFO L290 TraceCheckUtils]: 45: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,175 INFO L290 TraceCheckUtils]: 46: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,176 INFO L290 TraceCheckUtils]: 47: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,176 INFO L290 TraceCheckUtils]: 48: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,176 INFO L290 TraceCheckUtils]: 49: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,176 INFO L290 TraceCheckUtils]: 50: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,177 INFO L290 TraceCheckUtils]: 51: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,177 INFO L290 TraceCheckUtils]: 52: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,177 INFO L290 TraceCheckUtils]: 53: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,178 INFO L290 TraceCheckUtils]: 54: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,178 INFO L290 TraceCheckUtils]: 55: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,178 INFO L290 TraceCheckUtils]: 56: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,178 INFO L290 TraceCheckUtils]: 57: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,179 INFO L290 TraceCheckUtils]: 58: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,179 INFO L290 TraceCheckUtils]: 59: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,179 INFO L290 TraceCheckUtils]: 60: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,180 INFO L290 TraceCheckUtils]: 61: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,180 INFO L290 TraceCheckUtils]: 62: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,180 INFO L290 TraceCheckUtils]: 63: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,180 INFO L290 TraceCheckUtils]: 64: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,181 INFO L290 TraceCheckUtils]: 65: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,181 INFO L290 TraceCheckUtils]: 66: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,181 INFO L290 TraceCheckUtils]: 67: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,182 INFO L290 TraceCheckUtils]: 68: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,182 INFO L290 TraceCheckUtils]: 69: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,182 INFO L290 TraceCheckUtils]: 70: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,182 INFO L290 TraceCheckUtils]: 71: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,183 INFO L290 TraceCheckUtils]: 72: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,183 INFO L290 TraceCheckUtils]: 73: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,183 INFO L290 TraceCheckUtils]: 74: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,184 INFO L290 TraceCheckUtils]: 75: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,184 INFO L290 TraceCheckUtils]: 76: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,184 INFO L290 TraceCheckUtils]: 77: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,184 INFO L290 TraceCheckUtils]: 78: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,185 INFO L290 TraceCheckUtils]: 79: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,185 INFO L290 TraceCheckUtils]: 80: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,185 INFO L290 TraceCheckUtils]: 81: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,186 INFO L290 TraceCheckUtils]: 82: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,186 INFO L290 TraceCheckUtils]: 83: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,186 INFO L290 TraceCheckUtils]: 84: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t8_pc~0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,186 INFO L290 TraceCheckUtils]: 85: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,187 INFO L290 TraceCheckUtils]: 86: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,187 INFO L290 TraceCheckUtils]: 87: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,187 INFO L290 TraceCheckUtils]: 88: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,188 INFO L290 TraceCheckUtils]: 89: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,188 INFO L290 TraceCheckUtils]: 90: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t9_pc~0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,188 INFO L290 TraceCheckUtils]: 91: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,188 INFO L290 TraceCheckUtils]: 92: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,189 INFO L290 TraceCheckUtils]: 93: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,189 INFO L290 TraceCheckUtils]: 94: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,189 INFO L290 TraceCheckUtils]: 95: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,190 INFO L290 TraceCheckUtils]: 96: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,190 INFO L290 TraceCheckUtils]: 97: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,190 INFO L290 TraceCheckUtils]: 98: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,190 INFO L290 TraceCheckUtils]: 99: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,191 INFO L290 TraceCheckUtils]: 100: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,191 INFO L290 TraceCheckUtils]: 101: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,191 INFO L290 TraceCheckUtils]: 102: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t11_pc~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,192 INFO L290 TraceCheckUtils]: 103: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,192 INFO L290 TraceCheckUtils]: 104: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,192 INFO L290 TraceCheckUtils]: 105: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,192 INFO L290 TraceCheckUtils]: 106: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,193 INFO L290 TraceCheckUtils]: 107: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,193 INFO L290 TraceCheckUtils]: 108: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t12_pc~0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,193 INFO L290 TraceCheckUtils]: 109: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,194 INFO L290 TraceCheckUtils]: 110: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,194 INFO L290 TraceCheckUtils]: 111: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,194 INFO L290 TraceCheckUtils]: 112: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,194 INFO L290 TraceCheckUtils]: 113: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,195 INFO L290 TraceCheckUtils]: 114: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,195 INFO L290 TraceCheckUtils]: 115: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T1_E~0); {102567#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:24:53,195 INFO L290 TraceCheckUtils]: 116: Hoare triple {102567#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {102566#false} is VALID [2022-02-21 04:24:53,195 INFO L290 TraceCheckUtils]: 117: Hoare triple {102566#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,196 INFO L290 TraceCheckUtils]: 118: Hoare triple {102566#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,196 INFO L290 TraceCheckUtils]: 119: Hoare triple {102566#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,196 INFO L290 TraceCheckUtils]: 120: Hoare triple {102566#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,196 INFO L290 TraceCheckUtils]: 121: Hoare triple {102566#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,196 INFO L290 TraceCheckUtils]: 122: Hoare triple {102566#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,196 INFO L290 TraceCheckUtils]: 123: Hoare triple {102566#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,196 INFO L290 TraceCheckUtils]: 124: Hoare triple {102566#false} assume !(1 == ~T10_E~0); {102566#false} is VALID [2022-02-21 04:24:53,196 INFO L290 TraceCheckUtils]: 125: Hoare triple {102566#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,196 INFO L290 TraceCheckUtils]: 126: Hoare triple {102566#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,197 INFO L290 TraceCheckUtils]: 127: Hoare triple {102566#false} assume 1 == ~E_1~0;~E_1~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,197 INFO L290 TraceCheckUtils]: 128: Hoare triple {102566#false} assume 1 == ~E_2~0;~E_2~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,197 INFO L290 TraceCheckUtils]: 129: Hoare triple {102566#false} assume 1 == ~E_3~0;~E_3~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,197 INFO L290 TraceCheckUtils]: 130: Hoare triple {102566#false} assume 1 == ~E_4~0;~E_4~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,197 INFO L290 TraceCheckUtils]: 131: Hoare triple {102566#false} assume 1 == ~E_5~0;~E_5~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,197 INFO L290 TraceCheckUtils]: 132: Hoare triple {102566#false} assume !(1 == ~E_6~0); {102566#false} is VALID [2022-02-21 04:24:53,197 INFO L290 TraceCheckUtils]: 133: Hoare triple {102566#false} assume 1 == ~E_7~0;~E_7~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,197 INFO L290 TraceCheckUtils]: 134: Hoare triple {102566#false} assume 1 == ~E_8~0;~E_8~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,197 INFO L290 TraceCheckUtils]: 135: Hoare triple {102566#false} assume 1 == ~E_9~0;~E_9~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,197 INFO L290 TraceCheckUtils]: 136: Hoare triple {102566#false} assume 1 == ~E_10~0;~E_10~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,198 INFO L290 TraceCheckUtils]: 137: Hoare triple {102566#false} assume 1 == ~E_11~0;~E_11~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,198 INFO L290 TraceCheckUtils]: 138: Hoare triple {102566#false} assume 1 == ~E_12~0;~E_12~0 := 2; {102566#false} is VALID [2022-02-21 04:24:53,198 INFO L290 TraceCheckUtils]: 139: Hoare triple {102566#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {102566#false} is VALID [2022-02-21 04:24:53,198 INFO L290 TraceCheckUtils]: 140: Hoare triple {102566#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {102566#false} is VALID [2022-02-21 04:24:53,198 INFO L290 TraceCheckUtils]: 141: Hoare triple {102566#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {102566#false} is VALID [2022-02-21 04:24:53,198 INFO L290 TraceCheckUtils]: 142: Hoare triple {102566#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {102566#false} is VALID [2022-02-21 04:24:53,198 INFO L290 TraceCheckUtils]: 143: Hoare triple {102566#false} assume !(0 == start_simulation_~tmp~3#1); {102566#false} is VALID [2022-02-21 04:24:53,198 INFO L290 TraceCheckUtils]: 144: Hoare triple {102566#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {102566#false} is VALID [2022-02-21 04:24:53,198 INFO L290 TraceCheckUtils]: 145: Hoare triple {102566#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {102566#false} is VALID [2022-02-21 04:24:53,199 INFO L290 TraceCheckUtils]: 146: Hoare triple {102566#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {102566#false} is VALID [2022-02-21 04:24:53,199 INFO L290 TraceCheckUtils]: 147: Hoare triple {102566#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {102566#false} is VALID [2022-02-21 04:24:53,199 INFO L290 TraceCheckUtils]: 148: Hoare triple {102566#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {102566#false} is VALID [2022-02-21 04:24:53,199 INFO L290 TraceCheckUtils]: 149: Hoare triple {102566#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {102566#false} is VALID [2022-02-21 04:24:53,199 INFO L290 TraceCheckUtils]: 150: Hoare triple {102566#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {102566#false} is VALID [2022-02-21 04:24:53,199 INFO L290 TraceCheckUtils]: 151: Hoare triple {102566#false} assume !(0 != start_simulation_~tmp___0~1#1); {102566#false} is VALID [2022-02-21 04:24:53,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:53,200 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:53,200 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [392808963] [2022-02-21 04:24:53,200 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [392808963] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:53,201 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:53,201 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:53,201 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821382336] [2022-02-21 04:24:53,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:53,201 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:53,201 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:53,202 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:53,202 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:53,202 INFO L87 Difference]: Start difference. First operand 3238 states and 4766 transitions. cyclomatic complexity: 1530 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:57,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:57,131 INFO L93 Difference]: Finished difference Result 6132 states and 9017 transitions. [2022-02-21 04:24:57,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:24:57,131 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:57,224 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:57,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6132 states and 9017 transitions. [2022-02-21 04:24:58,203 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5922 [2022-02-21 04:24:59,135 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6132 states to 6132 states and 9017 transitions. [2022-02-21 04:24:59,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6132 [2022-02-21 04:24:59,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6132 [2022-02-21 04:24:59,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6132 states and 9017 transitions. [2022-02-21 04:24:59,143 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:59,144 INFO L681 BuchiCegarLoop]: Abstraction has 6132 states and 9017 transitions. [2022-02-21 04:24:59,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6132 states and 9017 transitions. [2022-02-21 04:24:59,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6132 to 6130. [2022-02-21 04:24:59,214 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:59,221 INFO L82 GeneralOperation]: Start isEquivalent. First operand 6132 states and 9017 transitions. Second operand has 6130 states, 6130 states have (on average 1.4706362153344208) internal successors, (9015), 6129 states have internal predecessors, (9015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:59,227 INFO L74 IsIncluded]: Start isIncluded. First operand 6132 states and 9017 transitions. Second operand has 6130 states, 6130 states have (on average 1.4706362153344208) internal successors, (9015), 6129 states have internal predecessors, (9015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:59,233 INFO L87 Difference]: Start difference. First operand 6132 states and 9017 transitions. Second operand has 6130 states, 6130 states have (on average 1.4706362153344208) internal successors, (9015), 6129 states have internal predecessors, (9015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:00,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:00,182 INFO L93 Difference]: Finished difference Result 6132 states and 9017 transitions. [2022-02-21 04:25:00,182 INFO L276 IsEmpty]: Start isEmpty. Operand 6132 states and 9017 transitions. [2022-02-21 04:25:00,188 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:00,188 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:00,196 INFO L74 IsIncluded]: Start isIncluded. First operand has 6130 states, 6130 states have (on average 1.4706362153344208) internal successors, (9015), 6129 states have internal predecessors, (9015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6132 states and 9017 transitions. [2022-02-21 04:25:00,204 INFO L87 Difference]: Start difference. First operand has 6130 states, 6130 states have (on average 1.4706362153344208) internal successors, (9015), 6129 states have internal predecessors, (9015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6132 states and 9017 transitions. [2022-02-21 04:25:01,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:01,132 INFO L93 Difference]: Finished difference Result 6132 states and 9017 transitions. [2022-02-21 04:25:01,132 INFO L276 IsEmpty]: Start isEmpty. Operand 6132 states and 9017 transitions. [2022-02-21 04:25:01,138 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:01,140 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:01,140 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:01,140 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:01,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6130 states, 6130 states have (on average 1.4706362153344208) internal successors, (9015), 6129 states have internal predecessors, (9015), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:02,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6130 states to 6130 states and 9015 transitions. [2022-02-21 04:25:02,308 INFO L704 BuchiCegarLoop]: Abstraction has 6130 states and 9015 transitions. [2022-02-21 04:25:02,308 INFO L587 BuchiCegarLoop]: Abstraction has 6130 states and 9015 transitions. [2022-02-21 04:25:02,308 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:25:02,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6130 states and 9015 transitions. [2022-02-21 04:25:02,316 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5922 [2022-02-21 04:25:02,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:02,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:02,318 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:02,318 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:02,318 INFO L791 eck$LassoCheckResult]: Stem: 109512#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 109513#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 110409#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 109868#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 109667#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 109668#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 109755#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 110066#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 110199#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 110200#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 108957#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 108958#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 110131#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 109558#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 109559#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 109465#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 109466#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 109863#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 109203#L1174 assume !(0 == ~M_E~0); 109204#L1174-2 assume !(0 == ~T1_E~0); 109053#L1179-1 assume !(0 == ~T2_E~0); 108955#L1184-1 assume !(0 == ~T3_E~0); 108956#L1189-1 assume !(0 == ~T4_E~0); 108994#L1194-1 assume !(0 == ~T5_E~0); 109094#L1199-1 assume !(0 == ~T6_E~0); 110008#L1204-1 assume !(0 == ~T7_E~0); 109922#L1209-1 assume !(0 == ~T8_E~0); 109923#L1214-1 assume !(0 == ~T9_E~0); 110336#L1219-1 assume !(0 == ~T10_E~0); 110437#L1224-1 assume !(0 == ~T11_E~0); 109324#L1229-1 assume !(0 == ~T12_E~0); 108880#L1234-1 assume !(0 == ~E_1~0); 108881#L1239-1 assume !(0 == ~E_2~0); 108916#L1244-1 assume !(0 == ~E_3~0); 108917#L1249-1 assume !(0 == ~E_4~0); 109582#L1254-1 assume !(0 == ~E_5~0); 108810#L1259-1 assume !(0 == ~E_6~0); 108764#L1264-1 assume !(0 == ~E_7~0); 108765#L1269-1 assume !(0 == ~E_8~0); 110447#L1274-1 assume !(0 == ~E_9~0); 110364#L1279-1 assume !(0 == ~E_10~0); 108998#L1284-1 assume !(0 == ~E_11~0); 108999#L1289-1 assume !(0 == ~E_12~0); 109635#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 109636#L566 assume 1 == ~m_pc~0; 108781#L567 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 108782#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 109953#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 109954#L1455 assume !(0 != activate_threads_~tmp~1#1); 109230#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 109231#L585 assume 1 == ~t1_pc~0; 108877#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 108878#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109892#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 109893#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 110392#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110390#L604 assume !(1 == ~t2_pc~0); 109973#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 109974#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109497#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 109498#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 110160#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110161#L623 assume 1 == ~t3_pc~0; 109412#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 108745#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 109562#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 109563#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 110195#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108778#L642 assume !(1 == ~t4_pc~0); 108779#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 109247#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 109248#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 108851#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 108852#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 109988#L661 assume 1 == ~t5_pc~0; 109016#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 109017#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108978#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 108979#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 110019#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 110020#L680 assume !(1 == ~t6_pc~0); 109445#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 109446#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 109710#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 109711#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 110264#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 110388#L699 assume 1 == ~t7_pc~0; 109843#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 109844#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 109006#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 109007#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 109741#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 109637#L718 assume !(1 == ~t8_pc~0); 109638#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 108992#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 108993#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 109034#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 109035#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 109168#L737 assume 1 == ~t9_pc~0; 110054#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 109308#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 109918#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 109919#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 109483#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 109484#L756 assume 1 == ~t10_pc~0; 110078#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 109733#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 108708#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 108709#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 109290#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 109291#L775 assume !(1 == ~t11_pc~0); 109546#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 109547#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 109162#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 108926#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 108927#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 109113#L794 assume 1 == ~t12_pc~0; 108954#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 108931#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 110152#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 109081#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 109082#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109565#L1307 assume !(1 == ~M_E~0); 109566#L1307-2 assume !(1 == ~T1_E~0); 109680#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 110408#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 109812#L1322-1 assume !(1 == ~T4_E~0); 109299#L1327-1 assume !(1 == ~T5_E~0); 109300#L1332-1 assume !(1 == ~T6_E~0); 109847#L1337-1 assume !(1 == ~T7_E~0); 109807#L1342-1 assume !(1 == ~T8_E~0); 109808#L1347-1 assume !(1 == ~T9_E~0); 110362#L1352-1 assume !(1 == ~T10_E~0); 110698#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 110696#L1362-1 assume !(1 == ~T12_E~0); 110694#L1367-1 assume !(1 == ~E_1~0); 110692#L1372-1 assume !(1 == ~E_2~0); 110690#L1377-1 assume !(1 == ~E_3~0); 109395#L1382-1 assume !(1 == ~E_4~0); 109396#L1387-1 assume !(1 == ~E_5~0); 110536#L1392-1 assume !(1 == ~E_6~0); 110534#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 110532#L1402-1 assume !(1 == ~E_8~0); 110530#L1407-1 assume !(1 == ~E_9~0); 110528#L1412-1 assume !(1 == ~E_10~0); 110527#L1417-1 assume !(1 == ~E_11~0); 110507#L1422-1 assume !(1 == ~E_12~0); 110498#L1427-1 assume { :end_inline_reset_delta_events } true; 110491#L1768-2 [2022-02-21 04:25:02,318 INFO L793 eck$LassoCheckResult]: Loop: 110491#L1768-2 assume !false; 110485#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 110481#L1149 assume !false; 110480#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 110472#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 110466#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 110465#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 110463#L976 assume !(0 != eval_~tmp~0#1); 110462#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 110461#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 110460#L1174-3 assume !(0 == ~M_E~0); 110459#L1174-5 assume !(0 == ~T1_E~0); 110457#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 110458#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 112191#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 112189#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 112187#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 112185#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 112183#L1209-3 assume !(0 == ~T8_E~0); 112181#L1214-3 assume !(0 == ~T9_E~0); 112178#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 112176#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 112174#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 112172#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 112170#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 112168#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 112165#L1249-3 assume !(0 == ~E_4~0); 112163#L1254-3 assume !(0 == ~E_5~0); 112161#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 112159#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 112157#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 112155#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 112152#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 112150#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 112148#L1289-3 assume !(0 == ~E_12~0); 112146#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112144#L566-39 assume 1 == ~m_pc~0; 112141#L567-13 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 112138#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112136#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 112134#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 112132#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112130#L585-39 assume !(1 == ~t1_pc~0); 112128#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 112124#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112122#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 112120#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 112119#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112101#L604-39 assume !(1 == ~t2_pc~0); 112095#L604-41 is_transmit2_triggered_~__retres1~2#1 := 0; 112085#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112084#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 112083#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 112082#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112081#L623-39 assume 1 == ~t3_pc~0; 112080#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 112078#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112077#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 112076#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 112075#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112074#L642-39 assume !(1 == ~t4_pc~0); 112073#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 112071#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112070#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 112069#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 112067#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112065#L661-39 assume 1 == ~t5_pc~0; 112063#L662-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 112060#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112058#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 112056#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 112053#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112052#L680-39 assume 1 == ~t6_pc~0; 112049#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 112047#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112045#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 112043#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 112040#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112039#L699-39 assume 1 == ~t7_pc~0; 112025#L700-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 112022#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112020#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 112017#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 112015#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 112013#L718-39 assume !(1 == ~t8_pc~0); 112009#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 112006#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112004#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 112002#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 112000#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 111997#L737-39 assume !(1 == ~t9_pc~0); 111995#L737-41 is_transmit9_triggered_~__retres1~9#1 := 0; 111992#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 111990#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 111495#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 111492#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 111490#L756-39 assume 1 == ~t10_pc~0; 111488#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 111485#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 111484#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 111483#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 111480#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 111478#L775-39 assume 1 == ~t11_pc~0; 111475#L776-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 111473#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 111471#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 111469#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 111466#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 111464#L794-39 assume 1 == ~t12_pc~0; 111461#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 111458#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 111456#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 111453#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 111451#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111449#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 111447#L1307-5 assume !(1 == ~T1_E~0); 111445#L1312-3 assume !(1 == ~T2_E~0); 110446#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111441#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 111439#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 111437#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 111435#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 111433#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 111431#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 111426#L1352-3 assume !(1 == ~T10_E~0); 111424#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 111422#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 111420#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 111418#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 111416#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 111413#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 111411#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 111407#L1392-3 assume !(1 == ~E_6~0); 111405#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 111403#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 111401#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 111398#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 111396#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 111394#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 111392#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 110685#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 110672#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 110671#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 110669#L1787 assume !(0 == start_simulation_~tmp~3#1); 110665#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 110543#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 110535#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 110533#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 110531#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 110529#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 110508#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 110499#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 110491#L1768-2 [2022-02-21 04:25:02,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:02,319 INFO L85 PathProgramCache]: Analyzing trace with hash 32770907, now seen corresponding path program 1 times [2022-02-21 04:25:02,319 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:02,319 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573781905] [2022-02-21 04:25:02,319 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:02,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:02,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:02,364 INFO L290 TraceCheckUtils]: 0: Hoare triple {127099#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,364 INFO L290 TraceCheckUtils]: 1: Hoare triple {127101#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,364 INFO L290 TraceCheckUtils]: 2: Hoare triple {127101#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,365 INFO L290 TraceCheckUtils]: 3: Hoare triple {127101#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,365 INFO L290 TraceCheckUtils]: 4: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,365 INFO L290 TraceCheckUtils]: 5: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,365 INFO L290 TraceCheckUtils]: 6: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,366 INFO L290 TraceCheckUtils]: 7: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,366 INFO L290 TraceCheckUtils]: 8: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,366 INFO L290 TraceCheckUtils]: 9: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,367 INFO L290 TraceCheckUtils]: 10: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,367 INFO L290 TraceCheckUtils]: 11: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,367 INFO L290 TraceCheckUtils]: 12: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,367 INFO L290 TraceCheckUtils]: 13: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,368 INFO L290 TraceCheckUtils]: 14: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,368 INFO L290 TraceCheckUtils]: 15: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,368 INFO L290 TraceCheckUtils]: 16: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,368 INFO L290 TraceCheckUtils]: 17: Hoare triple {127101#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,369 INFO L290 TraceCheckUtils]: 18: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,369 INFO L290 TraceCheckUtils]: 19: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,369 INFO L290 TraceCheckUtils]: 20: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,369 INFO L290 TraceCheckUtils]: 21: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T3_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,370 INFO L290 TraceCheckUtils]: 22: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T4_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,370 INFO L290 TraceCheckUtils]: 23: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T5_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,370 INFO L290 TraceCheckUtils]: 24: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T6_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,370 INFO L290 TraceCheckUtils]: 25: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T7_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,371 INFO L290 TraceCheckUtils]: 26: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T8_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,371 INFO L290 TraceCheckUtils]: 27: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T9_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,371 INFO L290 TraceCheckUtils]: 28: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T10_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,372 INFO L290 TraceCheckUtils]: 29: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T11_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,372 INFO L290 TraceCheckUtils]: 30: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~T12_E~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,372 INFO L290 TraceCheckUtils]: 31: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,372 INFO L290 TraceCheckUtils]: 32: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,373 INFO L290 TraceCheckUtils]: 33: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_3~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,373 INFO L290 TraceCheckUtils]: 34: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_4~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,373 INFO L290 TraceCheckUtils]: 35: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_5~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,373 INFO L290 TraceCheckUtils]: 36: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_6~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,374 INFO L290 TraceCheckUtils]: 37: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_7~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,374 INFO L290 TraceCheckUtils]: 38: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_8~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,374 INFO L290 TraceCheckUtils]: 39: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_9~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,374 INFO L290 TraceCheckUtils]: 40: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_10~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,375 INFO L290 TraceCheckUtils]: 41: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_11~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,375 INFO L290 TraceCheckUtils]: 42: Hoare triple {127101#(= ~m_pc~0 0)} assume !(0 == ~E_12~0); {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,375 INFO L290 TraceCheckUtils]: 43: Hoare triple {127101#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {127101#(= ~m_pc~0 0)} is VALID [2022-02-21 04:25:02,376 INFO L290 TraceCheckUtils]: 44: Hoare triple {127101#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {127100#false} is VALID [2022-02-21 04:25:02,376 INFO L290 TraceCheckUtils]: 45: Hoare triple {127100#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {127100#false} is VALID [2022-02-21 04:25:02,376 INFO L290 TraceCheckUtils]: 46: Hoare triple {127100#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {127100#false} is VALID [2022-02-21 04:25:02,376 INFO L290 TraceCheckUtils]: 47: Hoare triple {127100#false} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {127100#false} is VALID [2022-02-21 04:25:02,376 INFO L290 TraceCheckUtils]: 48: Hoare triple {127100#false} assume !(0 != activate_threads_~tmp~1#1); {127100#false} is VALID [2022-02-21 04:25:02,376 INFO L290 TraceCheckUtils]: 49: Hoare triple {127100#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {127100#false} is VALID [2022-02-21 04:25:02,376 INFO L290 TraceCheckUtils]: 50: Hoare triple {127100#false} assume 1 == ~t1_pc~0; {127100#false} is VALID [2022-02-21 04:25:02,376 INFO L290 TraceCheckUtils]: 51: Hoare triple {127100#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {127100#false} is VALID [2022-02-21 04:25:02,376 INFO L290 TraceCheckUtils]: 52: Hoare triple {127100#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {127100#false} is VALID [2022-02-21 04:25:02,377 INFO L290 TraceCheckUtils]: 53: Hoare triple {127100#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {127100#false} is VALID [2022-02-21 04:25:02,377 INFO L290 TraceCheckUtils]: 54: Hoare triple {127100#false} assume !(0 != activate_threads_~tmp___0~0#1); {127100#false} is VALID [2022-02-21 04:25:02,377 INFO L290 TraceCheckUtils]: 55: Hoare triple {127100#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {127100#false} is VALID [2022-02-21 04:25:02,377 INFO L290 TraceCheckUtils]: 56: Hoare triple {127100#false} assume !(1 == ~t2_pc~0); {127100#false} is VALID [2022-02-21 04:25:02,377 INFO L290 TraceCheckUtils]: 57: Hoare triple {127100#false} is_transmit2_triggered_~__retres1~2#1 := 0; {127100#false} is VALID [2022-02-21 04:25:02,377 INFO L290 TraceCheckUtils]: 58: Hoare triple {127100#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {127100#false} is VALID [2022-02-21 04:25:02,377 INFO L290 TraceCheckUtils]: 59: Hoare triple {127100#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {127100#false} is VALID [2022-02-21 04:25:02,377 INFO L290 TraceCheckUtils]: 60: Hoare triple {127100#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {127100#false} is VALID [2022-02-21 04:25:02,377 INFO L290 TraceCheckUtils]: 61: Hoare triple {127100#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {127100#false} is VALID [2022-02-21 04:25:02,378 INFO L290 TraceCheckUtils]: 62: Hoare triple {127100#false} assume 1 == ~t3_pc~0; {127100#false} is VALID [2022-02-21 04:25:02,378 INFO L290 TraceCheckUtils]: 63: Hoare triple {127100#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {127100#false} is VALID [2022-02-21 04:25:02,378 INFO L290 TraceCheckUtils]: 64: Hoare triple {127100#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {127100#false} is VALID [2022-02-21 04:25:02,378 INFO L290 TraceCheckUtils]: 65: Hoare triple {127100#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {127100#false} is VALID [2022-02-21 04:25:02,378 INFO L290 TraceCheckUtils]: 66: Hoare triple {127100#false} assume !(0 != activate_threads_~tmp___2~0#1); {127100#false} is VALID [2022-02-21 04:25:02,378 INFO L290 TraceCheckUtils]: 67: Hoare triple {127100#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {127100#false} is VALID [2022-02-21 04:25:02,378 INFO L290 TraceCheckUtils]: 68: Hoare triple {127100#false} assume !(1 == ~t4_pc~0); {127100#false} is VALID [2022-02-21 04:25:02,378 INFO L290 TraceCheckUtils]: 69: Hoare triple {127100#false} is_transmit4_triggered_~__retres1~4#1 := 0; {127100#false} is VALID [2022-02-21 04:25:02,378 INFO L290 TraceCheckUtils]: 70: Hoare triple {127100#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {127100#false} is VALID [2022-02-21 04:25:02,378 INFO L290 TraceCheckUtils]: 71: Hoare triple {127100#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {127100#false} is VALID [2022-02-21 04:25:02,379 INFO L290 TraceCheckUtils]: 72: Hoare triple {127100#false} assume !(0 != activate_threads_~tmp___3~0#1); {127100#false} is VALID [2022-02-21 04:25:02,379 INFO L290 TraceCheckUtils]: 73: Hoare triple {127100#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {127100#false} is VALID [2022-02-21 04:25:02,379 INFO L290 TraceCheckUtils]: 74: Hoare triple {127100#false} assume 1 == ~t5_pc~0; {127100#false} is VALID [2022-02-21 04:25:02,379 INFO L290 TraceCheckUtils]: 75: Hoare triple {127100#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {127100#false} is VALID [2022-02-21 04:25:02,379 INFO L290 TraceCheckUtils]: 76: Hoare triple {127100#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {127100#false} is VALID [2022-02-21 04:25:02,379 INFO L290 TraceCheckUtils]: 77: Hoare triple {127100#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {127100#false} is VALID [2022-02-21 04:25:02,379 INFO L290 TraceCheckUtils]: 78: Hoare triple {127100#false} assume !(0 != activate_threads_~tmp___4~0#1); {127100#false} is VALID [2022-02-21 04:25:02,379 INFO L290 TraceCheckUtils]: 79: Hoare triple {127100#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {127100#false} is VALID [2022-02-21 04:25:02,379 INFO L290 TraceCheckUtils]: 80: Hoare triple {127100#false} assume !(1 == ~t6_pc~0); {127100#false} is VALID [2022-02-21 04:25:02,380 INFO L290 TraceCheckUtils]: 81: Hoare triple {127100#false} is_transmit6_triggered_~__retres1~6#1 := 0; {127100#false} is VALID [2022-02-21 04:25:02,380 INFO L290 TraceCheckUtils]: 82: Hoare triple {127100#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {127100#false} is VALID [2022-02-21 04:25:02,380 INFO L290 TraceCheckUtils]: 83: Hoare triple {127100#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {127100#false} is VALID [2022-02-21 04:25:02,380 INFO L290 TraceCheckUtils]: 84: Hoare triple {127100#false} assume !(0 != activate_threads_~tmp___5~0#1); {127100#false} is VALID [2022-02-21 04:25:02,380 INFO L290 TraceCheckUtils]: 85: Hoare triple {127100#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {127100#false} is VALID [2022-02-21 04:25:02,380 INFO L290 TraceCheckUtils]: 86: Hoare triple {127100#false} assume 1 == ~t7_pc~0; {127100#false} is VALID [2022-02-21 04:25:02,380 INFO L290 TraceCheckUtils]: 87: Hoare triple {127100#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {127100#false} is VALID [2022-02-21 04:25:02,380 INFO L290 TraceCheckUtils]: 88: Hoare triple {127100#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {127100#false} is VALID [2022-02-21 04:25:02,380 INFO L290 TraceCheckUtils]: 89: Hoare triple {127100#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {127100#false} is VALID [2022-02-21 04:25:02,381 INFO L290 TraceCheckUtils]: 90: Hoare triple {127100#false} assume !(0 != activate_threads_~tmp___6~0#1); {127100#false} is VALID [2022-02-21 04:25:02,381 INFO L290 TraceCheckUtils]: 91: Hoare triple {127100#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {127100#false} is VALID [2022-02-21 04:25:02,381 INFO L290 TraceCheckUtils]: 92: Hoare triple {127100#false} assume !(1 == ~t8_pc~0); {127100#false} is VALID [2022-02-21 04:25:02,381 INFO L290 TraceCheckUtils]: 93: Hoare triple {127100#false} is_transmit8_triggered_~__retres1~8#1 := 0; {127100#false} is VALID [2022-02-21 04:25:02,381 INFO L290 TraceCheckUtils]: 94: Hoare triple {127100#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {127100#false} is VALID [2022-02-21 04:25:02,381 INFO L290 TraceCheckUtils]: 95: Hoare triple {127100#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {127100#false} is VALID [2022-02-21 04:25:02,381 INFO L290 TraceCheckUtils]: 96: Hoare triple {127100#false} assume !(0 != activate_threads_~tmp___7~0#1); {127100#false} is VALID [2022-02-21 04:25:02,381 INFO L290 TraceCheckUtils]: 97: Hoare triple {127100#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {127100#false} is VALID [2022-02-21 04:25:02,381 INFO L290 TraceCheckUtils]: 98: Hoare triple {127100#false} assume 1 == ~t9_pc~0; {127100#false} is VALID [2022-02-21 04:25:02,381 INFO L290 TraceCheckUtils]: 99: Hoare triple {127100#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {127100#false} is VALID [2022-02-21 04:25:02,382 INFO L290 TraceCheckUtils]: 100: Hoare triple {127100#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {127100#false} is VALID [2022-02-21 04:25:02,382 INFO L290 TraceCheckUtils]: 101: Hoare triple {127100#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {127100#false} is VALID [2022-02-21 04:25:02,382 INFO L290 TraceCheckUtils]: 102: Hoare triple {127100#false} assume !(0 != activate_threads_~tmp___8~0#1); {127100#false} is VALID [2022-02-21 04:25:02,382 INFO L290 TraceCheckUtils]: 103: Hoare triple {127100#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {127100#false} is VALID [2022-02-21 04:25:02,382 INFO L290 TraceCheckUtils]: 104: Hoare triple {127100#false} assume 1 == ~t10_pc~0; {127100#false} is VALID [2022-02-21 04:25:02,382 INFO L290 TraceCheckUtils]: 105: Hoare triple {127100#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {127100#false} is VALID [2022-02-21 04:25:02,382 INFO L290 TraceCheckUtils]: 106: Hoare triple {127100#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {127100#false} is VALID [2022-02-21 04:25:02,382 INFO L290 TraceCheckUtils]: 107: Hoare triple {127100#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {127100#false} is VALID [2022-02-21 04:25:02,382 INFO L290 TraceCheckUtils]: 108: Hoare triple {127100#false} assume !(0 != activate_threads_~tmp___9~0#1); {127100#false} is VALID [2022-02-21 04:25:02,383 INFO L290 TraceCheckUtils]: 109: Hoare triple {127100#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {127100#false} is VALID [2022-02-21 04:25:02,383 INFO L290 TraceCheckUtils]: 110: Hoare triple {127100#false} assume !(1 == ~t11_pc~0); {127100#false} is VALID [2022-02-21 04:25:02,383 INFO L290 TraceCheckUtils]: 111: Hoare triple {127100#false} is_transmit11_triggered_~__retres1~11#1 := 0; {127100#false} is VALID [2022-02-21 04:25:02,383 INFO L290 TraceCheckUtils]: 112: Hoare triple {127100#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {127100#false} is VALID [2022-02-21 04:25:02,383 INFO L290 TraceCheckUtils]: 113: Hoare triple {127100#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {127100#false} is VALID [2022-02-21 04:25:02,383 INFO L290 TraceCheckUtils]: 114: Hoare triple {127100#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {127100#false} is VALID [2022-02-21 04:25:02,383 INFO L290 TraceCheckUtils]: 115: Hoare triple {127100#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {127100#false} is VALID [2022-02-21 04:25:02,383 INFO L290 TraceCheckUtils]: 116: Hoare triple {127100#false} assume 1 == ~t12_pc~0; {127100#false} is VALID [2022-02-21 04:25:02,383 INFO L290 TraceCheckUtils]: 117: Hoare triple {127100#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {127100#false} is VALID [2022-02-21 04:25:02,384 INFO L290 TraceCheckUtils]: 118: Hoare triple {127100#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {127100#false} is VALID [2022-02-21 04:25:02,384 INFO L290 TraceCheckUtils]: 119: Hoare triple {127100#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {127100#false} is VALID [2022-02-21 04:25:02,384 INFO L290 TraceCheckUtils]: 120: Hoare triple {127100#false} assume !(0 != activate_threads_~tmp___11~0#1); {127100#false} is VALID [2022-02-21 04:25:02,384 INFO L290 TraceCheckUtils]: 121: Hoare triple {127100#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {127100#false} is VALID [2022-02-21 04:25:02,384 INFO L290 TraceCheckUtils]: 122: Hoare triple {127100#false} assume !(1 == ~M_E~0); {127100#false} is VALID [2022-02-21 04:25:02,384 INFO L290 TraceCheckUtils]: 123: Hoare triple {127100#false} assume !(1 == ~T1_E~0); {127100#false} is VALID [2022-02-21 04:25:02,384 INFO L290 TraceCheckUtils]: 124: Hoare triple {127100#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {127100#false} is VALID [2022-02-21 04:25:02,384 INFO L290 TraceCheckUtils]: 125: Hoare triple {127100#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {127100#false} is VALID [2022-02-21 04:25:02,384 INFO L290 TraceCheckUtils]: 126: Hoare triple {127100#false} assume !(1 == ~T4_E~0); {127100#false} is VALID [2022-02-21 04:25:02,384 INFO L290 TraceCheckUtils]: 127: Hoare triple {127100#false} assume !(1 == ~T5_E~0); {127100#false} is VALID [2022-02-21 04:25:02,385 INFO L290 TraceCheckUtils]: 128: Hoare triple {127100#false} assume !(1 == ~T6_E~0); {127100#false} is VALID [2022-02-21 04:25:02,385 INFO L290 TraceCheckUtils]: 129: Hoare triple {127100#false} assume !(1 == ~T7_E~0); {127100#false} is VALID [2022-02-21 04:25:02,385 INFO L290 TraceCheckUtils]: 130: Hoare triple {127100#false} assume !(1 == ~T8_E~0); {127100#false} is VALID [2022-02-21 04:25:02,385 INFO L290 TraceCheckUtils]: 131: Hoare triple {127100#false} assume !(1 == ~T9_E~0); {127100#false} is VALID [2022-02-21 04:25:02,385 INFO L290 TraceCheckUtils]: 132: Hoare triple {127100#false} assume !(1 == ~T10_E~0); {127100#false} is VALID [2022-02-21 04:25:02,385 INFO L290 TraceCheckUtils]: 133: Hoare triple {127100#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {127100#false} is VALID [2022-02-21 04:25:02,385 INFO L290 TraceCheckUtils]: 134: Hoare triple {127100#false} assume !(1 == ~T12_E~0); {127100#false} is VALID [2022-02-21 04:25:02,385 INFO L290 TraceCheckUtils]: 135: Hoare triple {127100#false} assume !(1 == ~E_1~0); {127100#false} is VALID [2022-02-21 04:25:02,385 INFO L290 TraceCheckUtils]: 136: Hoare triple {127100#false} assume !(1 == ~E_2~0); {127100#false} is VALID [2022-02-21 04:25:02,386 INFO L290 TraceCheckUtils]: 137: Hoare triple {127100#false} assume !(1 == ~E_3~0); {127100#false} is VALID [2022-02-21 04:25:02,386 INFO L290 TraceCheckUtils]: 138: Hoare triple {127100#false} assume !(1 == ~E_4~0); {127100#false} is VALID [2022-02-21 04:25:02,386 INFO L290 TraceCheckUtils]: 139: Hoare triple {127100#false} assume !(1 == ~E_5~0); {127100#false} is VALID [2022-02-21 04:25:02,386 INFO L290 TraceCheckUtils]: 140: Hoare triple {127100#false} assume !(1 == ~E_6~0); {127100#false} is VALID [2022-02-21 04:25:02,386 INFO L290 TraceCheckUtils]: 141: Hoare triple {127100#false} assume 1 == ~E_7~0;~E_7~0 := 2; {127100#false} is VALID [2022-02-21 04:25:02,386 INFO L290 TraceCheckUtils]: 142: Hoare triple {127100#false} assume !(1 == ~E_8~0); {127100#false} is VALID [2022-02-21 04:25:02,386 INFO L290 TraceCheckUtils]: 143: Hoare triple {127100#false} assume !(1 == ~E_9~0); {127100#false} is VALID [2022-02-21 04:25:02,386 INFO L290 TraceCheckUtils]: 144: Hoare triple {127100#false} assume !(1 == ~E_10~0); {127100#false} is VALID [2022-02-21 04:25:02,386 INFO L290 TraceCheckUtils]: 145: Hoare triple {127100#false} assume !(1 == ~E_11~0); {127100#false} is VALID [2022-02-21 04:25:02,387 INFO L290 TraceCheckUtils]: 146: Hoare triple {127100#false} assume !(1 == ~E_12~0); {127100#false} is VALID [2022-02-21 04:25:02,387 INFO L290 TraceCheckUtils]: 147: Hoare triple {127100#false} assume { :end_inline_reset_delta_events } true; {127100#false} is VALID [2022-02-21 04:25:02,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:02,387 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:02,387 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573781905] [2022-02-21 04:25:02,387 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573781905] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:02,387 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:02,387 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:25:02,388 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942256535] [2022-02-21 04:25:02,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:02,388 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:02,388 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:02,388 INFO L85 PathProgramCache]: Analyzing trace with hash -1970529464, now seen corresponding path program 1 times [2022-02-21 04:25:02,388 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:02,389 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1540996072] [2022-02-21 04:25:02,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:02,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:02,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:02,414 INFO L290 TraceCheckUtils]: 0: Hoare triple {127102#true} assume !false; {127102#true} is VALID [2022-02-21 04:25:02,414 INFO L290 TraceCheckUtils]: 1: Hoare triple {127102#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {127102#true} is VALID [2022-02-21 04:25:02,414 INFO L290 TraceCheckUtils]: 2: Hoare triple {127102#true} assume !false; {127102#true} is VALID [2022-02-21 04:25:02,414 INFO L290 TraceCheckUtils]: 3: Hoare triple {127102#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {127102#true} is VALID [2022-02-21 04:25:02,415 INFO L290 TraceCheckUtils]: 4: Hoare triple {127102#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {127102#true} is VALID [2022-02-21 04:25:02,415 INFO L290 TraceCheckUtils]: 5: Hoare triple {127102#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {127102#true} is VALID [2022-02-21 04:25:02,415 INFO L290 TraceCheckUtils]: 6: Hoare triple {127102#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {127102#true} is VALID [2022-02-21 04:25:02,415 INFO L290 TraceCheckUtils]: 7: Hoare triple {127102#true} assume !(0 != eval_~tmp~0#1); {127102#true} is VALID [2022-02-21 04:25:02,415 INFO L290 TraceCheckUtils]: 8: Hoare triple {127102#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {127102#true} is VALID [2022-02-21 04:25:02,415 INFO L290 TraceCheckUtils]: 9: Hoare triple {127102#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {127102#true} is VALID [2022-02-21 04:25:02,415 INFO L290 TraceCheckUtils]: 10: Hoare triple {127102#true} assume !(0 == ~M_E~0); {127102#true} is VALID [2022-02-21 04:25:02,415 INFO L290 TraceCheckUtils]: 11: Hoare triple {127102#true} assume !(0 == ~T1_E~0); {127102#true} is VALID [2022-02-21 04:25:02,416 INFO L290 TraceCheckUtils]: 12: Hoare triple {127102#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,416 INFO L290 TraceCheckUtils]: 13: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,416 INFO L290 TraceCheckUtils]: 14: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,416 INFO L290 TraceCheckUtils]: 15: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,417 INFO L290 TraceCheckUtils]: 16: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,417 INFO L290 TraceCheckUtils]: 17: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,417 INFO L290 TraceCheckUtils]: 18: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T8_E~0); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,431 INFO L290 TraceCheckUtils]: 19: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T9_E~0); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,432 INFO L290 TraceCheckUtils]: 20: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,432 INFO L290 TraceCheckUtils]: 21: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,432 INFO L290 TraceCheckUtils]: 22: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,433 INFO L290 TraceCheckUtils]: 23: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,433 INFO L290 TraceCheckUtils]: 24: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,433 INFO L290 TraceCheckUtils]: 25: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,433 INFO L290 TraceCheckUtils]: 26: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_4~0); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,434 INFO L290 TraceCheckUtils]: 27: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_5~0); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,434 INFO L290 TraceCheckUtils]: 28: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,434 INFO L290 TraceCheckUtils]: 29: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,435 INFO L290 TraceCheckUtils]: 30: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,435 INFO L290 TraceCheckUtils]: 31: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,435 INFO L290 TraceCheckUtils]: 32: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,436 INFO L290 TraceCheckUtils]: 33: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,436 INFO L290 TraceCheckUtils]: 34: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_12~0); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,436 INFO L290 TraceCheckUtils]: 35: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,436 INFO L290 TraceCheckUtils]: 36: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,437 INFO L290 TraceCheckUtils]: 37: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,437 INFO L290 TraceCheckUtils]: 38: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,437 INFO L290 TraceCheckUtils]: 39: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,438 INFO L290 TraceCheckUtils]: 40: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,438 INFO L290 TraceCheckUtils]: 41: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,438 INFO L290 TraceCheckUtils]: 42: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,439 INFO L290 TraceCheckUtils]: 43: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,439 INFO L290 TraceCheckUtils]: 44: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,439 INFO L290 TraceCheckUtils]: 45: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,439 INFO L290 TraceCheckUtils]: 46: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,440 INFO L290 TraceCheckUtils]: 47: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,440 INFO L290 TraceCheckUtils]: 48: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,440 INFO L290 TraceCheckUtils]: 49: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,441 INFO L290 TraceCheckUtils]: 50: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,441 INFO L290 TraceCheckUtils]: 51: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,441 INFO L290 TraceCheckUtils]: 52: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,442 INFO L290 TraceCheckUtils]: 53: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,442 INFO L290 TraceCheckUtils]: 54: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,442 INFO L290 TraceCheckUtils]: 55: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,443 INFO L290 TraceCheckUtils]: 56: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,443 INFO L290 TraceCheckUtils]: 57: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,443 INFO L290 TraceCheckUtils]: 58: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,444 INFO L290 TraceCheckUtils]: 59: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,444 INFO L290 TraceCheckUtils]: 60: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,444 INFO L290 TraceCheckUtils]: 61: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,444 INFO L290 TraceCheckUtils]: 62: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,445 INFO L290 TraceCheckUtils]: 63: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,445 INFO L290 TraceCheckUtils]: 64: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,448 INFO L290 TraceCheckUtils]: 65: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,475 INFO L290 TraceCheckUtils]: 66: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,476 INFO L290 TraceCheckUtils]: 67: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,476 INFO L290 TraceCheckUtils]: 68: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,476 INFO L290 TraceCheckUtils]: 69: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,476 INFO L290 TraceCheckUtils]: 70: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,477 INFO L290 TraceCheckUtils]: 71: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,477 INFO L290 TraceCheckUtils]: 72: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,477 INFO L290 TraceCheckUtils]: 73: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,478 INFO L290 TraceCheckUtils]: 74: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,478 INFO L290 TraceCheckUtils]: 75: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,481 INFO L290 TraceCheckUtils]: 76: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,481 INFO L290 TraceCheckUtils]: 77: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,481 INFO L290 TraceCheckUtils]: 78: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,481 INFO L290 TraceCheckUtils]: 79: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,482 INFO L290 TraceCheckUtils]: 80: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,482 INFO L290 TraceCheckUtils]: 81: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,482 INFO L290 TraceCheckUtils]: 82: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,483 INFO L290 TraceCheckUtils]: 83: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,483 INFO L290 TraceCheckUtils]: 84: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t8_pc~0); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,483 INFO L290 TraceCheckUtils]: 85: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,483 INFO L290 TraceCheckUtils]: 86: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,484 INFO L290 TraceCheckUtils]: 87: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,484 INFO L290 TraceCheckUtils]: 88: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___7~0#1); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,484 INFO L290 TraceCheckUtils]: 89: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,484 INFO L290 TraceCheckUtils]: 90: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t9_pc~0); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,485 INFO L290 TraceCheckUtils]: 91: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,485 INFO L290 TraceCheckUtils]: 92: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,485 INFO L290 TraceCheckUtils]: 93: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,485 INFO L290 TraceCheckUtils]: 94: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,486 INFO L290 TraceCheckUtils]: 95: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,486 INFO L290 TraceCheckUtils]: 96: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t10_pc~0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,486 INFO L290 TraceCheckUtils]: 97: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,487 INFO L290 TraceCheckUtils]: 98: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,487 INFO L290 TraceCheckUtils]: 99: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,487 INFO L290 TraceCheckUtils]: 100: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,487 INFO L290 TraceCheckUtils]: 101: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,488 INFO L290 TraceCheckUtils]: 102: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t11_pc~0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,488 INFO L290 TraceCheckUtils]: 103: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,488 INFO L290 TraceCheckUtils]: 104: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,489 INFO L290 TraceCheckUtils]: 105: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,489 INFO L290 TraceCheckUtils]: 106: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,489 INFO L290 TraceCheckUtils]: 107: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,490 INFO L290 TraceCheckUtils]: 108: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t12_pc~0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,490 INFO L290 TraceCheckUtils]: 109: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,490 INFO L290 TraceCheckUtils]: 110: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,490 INFO L290 TraceCheckUtils]: 111: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,491 INFO L290 TraceCheckUtils]: 112: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,491 INFO L290 TraceCheckUtils]: 113: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,491 INFO L290 TraceCheckUtils]: 114: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,492 INFO L290 TraceCheckUtils]: 115: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T1_E~0); {127104#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:25:02,492 INFO L290 TraceCheckUtils]: 116: Hoare triple {127104#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {127103#false} is VALID [2022-02-21 04:25:02,493 INFO L290 TraceCheckUtils]: 117: Hoare triple {127103#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,493 INFO L290 TraceCheckUtils]: 118: Hoare triple {127103#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,493 INFO L290 TraceCheckUtils]: 119: Hoare triple {127103#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,493 INFO L290 TraceCheckUtils]: 120: Hoare triple {127103#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,493 INFO L290 TraceCheckUtils]: 121: Hoare triple {127103#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,493 INFO L290 TraceCheckUtils]: 122: Hoare triple {127103#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,493 INFO L290 TraceCheckUtils]: 123: Hoare triple {127103#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,494 INFO L290 TraceCheckUtils]: 124: Hoare triple {127103#false} assume !(1 == ~T10_E~0); {127103#false} is VALID [2022-02-21 04:25:02,494 INFO L290 TraceCheckUtils]: 125: Hoare triple {127103#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,494 INFO L290 TraceCheckUtils]: 126: Hoare triple {127103#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,494 INFO L290 TraceCheckUtils]: 127: Hoare triple {127103#false} assume 1 == ~E_1~0;~E_1~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,494 INFO L290 TraceCheckUtils]: 128: Hoare triple {127103#false} assume 1 == ~E_2~0;~E_2~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,494 INFO L290 TraceCheckUtils]: 129: Hoare triple {127103#false} assume 1 == ~E_3~0;~E_3~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,494 INFO L290 TraceCheckUtils]: 130: Hoare triple {127103#false} assume 1 == ~E_4~0;~E_4~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,494 INFO L290 TraceCheckUtils]: 131: Hoare triple {127103#false} assume 1 == ~E_5~0;~E_5~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,494 INFO L290 TraceCheckUtils]: 132: Hoare triple {127103#false} assume !(1 == ~E_6~0); {127103#false} is VALID [2022-02-21 04:25:02,494 INFO L290 TraceCheckUtils]: 133: Hoare triple {127103#false} assume 1 == ~E_7~0;~E_7~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,495 INFO L290 TraceCheckUtils]: 134: Hoare triple {127103#false} assume 1 == ~E_8~0;~E_8~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,495 INFO L290 TraceCheckUtils]: 135: Hoare triple {127103#false} assume 1 == ~E_9~0;~E_9~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,495 INFO L290 TraceCheckUtils]: 136: Hoare triple {127103#false} assume 1 == ~E_10~0;~E_10~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,495 INFO L290 TraceCheckUtils]: 137: Hoare triple {127103#false} assume 1 == ~E_11~0;~E_11~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,495 INFO L290 TraceCheckUtils]: 138: Hoare triple {127103#false} assume 1 == ~E_12~0;~E_12~0 := 2; {127103#false} is VALID [2022-02-21 04:25:02,495 INFO L290 TraceCheckUtils]: 139: Hoare triple {127103#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {127103#false} is VALID [2022-02-21 04:25:02,495 INFO L290 TraceCheckUtils]: 140: Hoare triple {127103#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {127103#false} is VALID [2022-02-21 04:25:02,495 INFO L290 TraceCheckUtils]: 141: Hoare triple {127103#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {127103#false} is VALID [2022-02-21 04:25:02,495 INFO L290 TraceCheckUtils]: 142: Hoare triple {127103#false} start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; {127103#false} is VALID [2022-02-21 04:25:02,496 INFO L290 TraceCheckUtils]: 143: Hoare triple {127103#false} assume !(0 == start_simulation_~tmp~3#1); {127103#false} is VALID [2022-02-21 04:25:02,496 INFO L290 TraceCheckUtils]: 144: Hoare triple {127103#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; {127103#false} is VALID [2022-02-21 04:25:02,496 INFO L290 TraceCheckUtils]: 145: Hoare triple {127103#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; {127103#false} is VALID [2022-02-21 04:25:02,496 INFO L290 TraceCheckUtils]: 146: Hoare triple {127103#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; {127103#false} is VALID [2022-02-21 04:25:02,496 INFO L290 TraceCheckUtils]: 147: Hoare triple {127103#false} stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; {127103#false} is VALID [2022-02-21 04:25:02,497 INFO L290 TraceCheckUtils]: 148: Hoare triple {127103#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {127103#false} is VALID [2022-02-21 04:25:02,497 INFO L290 TraceCheckUtils]: 149: Hoare triple {127103#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {127103#false} is VALID [2022-02-21 04:25:02,497 INFO L290 TraceCheckUtils]: 150: Hoare triple {127103#false} start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; {127103#false} is VALID [2022-02-21 04:25:02,497 INFO L290 TraceCheckUtils]: 151: Hoare triple {127103#false} assume !(0 != start_simulation_~tmp___0~1#1); {127103#false} is VALID [2022-02-21 04:25:02,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:02,498 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:02,498 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1540996072] [2022-02-21 04:25:02,498 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1540996072] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:02,498 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:02,498 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:02,499 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869055658] [2022-02-21 04:25:02,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:02,499 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:25:02,499 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:02,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:25:02,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:25:02,500 INFO L87 Difference]: Start difference. First operand 6130 states and 9015 transitions. cyclomatic complexity: 2889 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:08,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:08,258 INFO L93 Difference]: Finished difference Result 11989 states and 17511 transitions. [2022-02-21 04:25:08,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:25:08,258 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:08,390 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 148 edges. 148 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:08,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11989 states and 17511 transitions. [2022-02-21 04:25:12,266 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11778 [2022-02-21 04:25:16,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11989 states to 11989 states and 17511 transitions. [2022-02-21 04:25:16,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11989 [2022-02-21 04:25:16,091 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11989 [2022-02-21 04:25:16,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11989 states and 17511 transitions. [2022-02-21 04:25:16,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:16,100 INFO L681 BuchiCegarLoop]: Abstraction has 11989 states and 17511 transitions. [2022-02-21 04:25:16,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11989 states and 17511 transitions. [2022-02-21 04:25:16,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11989 to 11621. [2022-02-21 04:25:16,212 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:16,230 INFO L82 GeneralOperation]: Start isEquivalent. First operand 11989 states and 17511 transitions. Second operand has 11621 states, 11621 states have (on average 1.4624386885810172) internal successors, (16995), 11620 states have internal predecessors, (16995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:16,245 INFO L74 IsIncluded]: Start isIncluded. First operand 11989 states and 17511 transitions. Second operand has 11621 states, 11621 states have (on average 1.4624386885810172) internal successors, (16995), 11620 states have internal predecessors, (16995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:16,259 INFO L87 Difference]: Start difference. First operand 11989 states and 17511 transitions. Second operand has 11621 states, 11621 states have (on average 1.4624386885810172) internal successors, (16995), 11620 states have internal predecessors, (16995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:19,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:19,904 INFO L93 Difference]: Finished difference Result 11989 states and 17511 transitions. [2022-02-21 04:25:19,904 INFO L276 IsEmpty]: Start isEmpty. Operand 11989 states and 17511 transitions. [2022-02-21 04:25:19,912 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:19,913 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:19,924 INFO L74 IsIncluded]: Start isIncluded. First operand has 11621 states, 11621 states have (on average 1.4624386885810172) internal successors, (16995), 11620 states have internal predecessors, (16995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 11989 states and 17511 transitions. [2022-02-21 04:25:19,935 INFO L87 Difference]: Start difference. First operand has 11621 states, 11621 states have (on average 1.4624386885810172) internal successors, (16995), 11620 states have internal predecessors, (16995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 11989 states and 17511 transitions. [2022-02-21 04:25:23,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:23,487 INFO L93 Difference]: Finished difference Result 11989 states and 17511 transitions. [2022-02-21 04:25:23,487 INFO L276 IsEmpty]: Start isEmpty. Operand 11989 states and 17511 transitions. [2022-02-21 04:25:23,495 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:23,495 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:23,495 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:23,496 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:23,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11621 states, 11621 states have (on average 1.4624386885810172) internal successors, (16995), 11620 states have internal predecessors, (16995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:27,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11621 states to 11621 states and 16995 transitions. [2022-02-21 04:25:27,074 INFO L704 BuchiCegarLoop]: Abstraction has 11621 states and 16995 transitions. [2022-02-21 04:25:27,074 INFO L587 BuchiCegarLoop]: Abstraction has 11621 states and 16995 transitions. [2022-02-21 04:25:27,074 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2022-02-21 04:25:27,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11621 states and 16995 transitions. [2022-02-21 04:25:27,104 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11410 [2022-02-21 04:25:27,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:27,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:27,115 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:27,116 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:27,116 INFO L791 eck$LassoCheckResult]: Stem: 139902#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; 139903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 140864#L1731 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 140262#L814 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 140058#L821 assume 1 == ~m_i~0;~m_st~0 := 0; 140059#L821-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 140146#L826-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 140478#L831-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 140614#L836-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 140615#L841-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 139345#L846-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 139346#L851-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 140540#L856-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 139946#L861-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 139947#L866-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 139853#L871-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 139854#L876-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 140257#L881-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 139587#L1174 assume !(0 == ~M_E~0); 139588#L1174-2 assume !(0 == ~T1_E~0); 139441#L1179-1 assume !(0 == ~T2_E~0); 139343#L1184-1 assume !(0 == ~T3_E~0); 139344#L1189-1 assume !(0 == ~T4_E~0); 139382#L1194-1 assume !(0 == ~T5_E~0); 139482#L1199-1 assume !(0 == ~T6_E~0); 140411#L1204-1 assume !(0 == ~T7_E~0); 140321#L1209-1 assume !(0 == ~T8_E~0); 140322#L1214-1 assume !(0 == ~T9_E~0); 140761#L1219-1 assume !(0 == ~T10_E~0); 140901#L1224-1 assume !(0 == ~T11_E~0); 139707#L1229-1 assume !(0 == ~T12_E~0); 139270#L1234-1 assume !(0 == ~E_1~0); 139271#L1239-1 assume !(0 == ~E_2~0); 139304#L1244-1 assume !(0 == ~E_3~0); 139305#L1249-1 assume !(0 == ~E_4~0); 139971#L1254-1 assume !(0 == ~E_5~0); 139198#L1259-1 assume !(0 == ~E_6~0); 139156#L1264-1 assume !(0 == ~E_7~0); 139157#L1269-1 assume !(0 == ~E_8~0); 140913#L1274-1 assume !(0 == ~E_9~0); 140794#L1279-1 assume !(0 == ~E_10~0); 139386#L1284-1 assume !(0 == ~E_11~0); 139387#L1289-1 assume !(0 == ~E_12~0); 140027#L1294-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 140028#L566 assume !(1 == ~m_pc~0); 140471#L566-2 is_master_triggered_~__retres1~0#1 := 0; 140472#L577 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 140354#L578 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 140355#L1455 assume !(0 != activate_threads_~tmp~1#1); 139614#L1455-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 139615#L585 assume 1 == ~t1_pc~0; 139265#L586 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 139266#L596 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 140286#L597 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 140287#L1463 assume !(0 != activate_threads_~tmp___0~0#1); 140836#L1463-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 140834#L604 assume !(1 == ~t2_pc~0); 140375#L604-2 is_transmit2_triggered_~__retres1~2#1 := 0; 140376#L615 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 139883#L616 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 139884#L1471 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 140568#L1471-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 140569#L623 assume 1 == ~t3_pc~0; 139797#L624 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 139137#L634 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 139950#L635 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 139951#L1479 assume !(0 != activate_threads_~tmp___2~0#1); 140609#L1479-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 139170#L642 assume !(1 == ~t4_pc~0); 139171#L642-2 is_transmit4_triggered_~__retres1~4#1 := 0; 139631#L653 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 139632#L654 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 139241#L1487 assume !(0 != activate_threads_~tmp___3~0#1); 139242#L1487-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 140387#L661 assume 1 == ~t5_pc~0; 139404#L662 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 139405#L672 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 139366#L673 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 139367#L1495 assume !(0 != activate_threads_~tmp___4~0#1); 140422#L1495-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 140423#L680 assume !(1 == ~t6_pc~0); 139831#L680-2 is_transmit6_triggered_~__retres1~6#1 := 0; 139832#L691 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 140101#L692 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 140102#L1503 assume !(0 != activate_threads_~tmp___5~0#1); 140686#L1503-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 140832#L699 assume 1 == ~t7_pc~0; 140235#L700 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 140236#L710 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 139394#L711 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 139395#L1511 assume !(0 != activate_threads_~tmp___6~0#1); 140132#L1511-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 140029#L718 assume !(1 == ~t8_pc~0); 140030#L718-2 is_transmit8_triggered_~__retres1~8#1 := 0; 139380#L729 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 139381#L730 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 139424#L1519 assume !(0 != activate_threads_~tmp___7~0#1); 139425#L1519-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 139554#L737 assume 1 == ~t9_pc~0; 140459#L738 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 139692#L748 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 140317#L749 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 140318#L1527 assume !(0 != activate_threads_~tmp___8~0#1); 139869#L1527-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 139870#L756 assume 1 == ~t10_pc~0; 140488#L757 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 140124#L767 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 139100#L768 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 139101#L1535 assume !(0 != activate_threads_~tmp___9~0#1); 139671#L1535-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 139672#L775 assume !(1 == ~t11_pc~0); 139934#L775-2 is_transmit11_triggered_~__retres1~11#1 := 0; 139935#L786 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 139551#L787 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 139314#L1543 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 139315#L1543-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 139501#L794 assume 1 == ~t12_pc~0; 139342#L795 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 139319#L805 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 140560#L806 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 139469#L1551 assume !(0 != activate_threads_~tmp___11~0#1); 139470#L1551-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 139953#L1307 assume !(1 == ~M_E~0); 139954#L1307-2 assume !(1 == ~T1_E~0); 140070#L1312-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 139987#L1317-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 139988#L1322-1 assume !(1 == ~T4_E~0); 139682#L1327-1 assume !(1 == ~T5_E~0); 139683#L1332-1 assume !(1 == ~T6_E~0); 140843#L1337-1 assume !(1 == ~T7_E~0); 140844#L1342-1 assume !(1 == ~T8_E~0); 140792#L1347-1 assume !(1 == ~T9_E~0); 140644#L1352-1 assume !(1 == ~T10_E~0); 140497#L1357-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 139849#L1362-1 assume !(1 == ~T12_E~0); 139850#L1367-1 assume !(1 == ~E_1~0); 139483#L1372-1 assume !(1 == ~E_2~0); 139484#L1377-1 assume !(1 == ~E_3~0); 139780#L1382-1 assume !(1 == ~E_4~0); 139781#L1387-1 assume !(1 == ~E_5~0); 140377#L1392-1 assume !(1 == ~E_6~0); 139802#L1397-1 assume 1 == ~E_7~0;~E_7~0 := 2; 139803#L1402-1 assume !(1 == ~E_8~0); 139499#L1407-1 assume !(1 == ~E_9~0); 139500#L1412-1 assume !(1 == ~E_10~0); 140558#L1417-1 assume !(1 == ~E_11~0); 140559#L1422-1 assume !(1 == ~E_12~0); 140829#L1427-1 assume { :end_inline_reset_delta_events } true; 139298#L1768-2 [2022-02-21 04:25:27,117 INFO L793 eck$LassoCheckResult]: Loop: 139298#L1768-2 assume !false; 139299#L1769 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 140050#L1149 assume !false; 140446#L972 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 140621#L894 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 139688#L961 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 139592#L962 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 139593#L976 assume !(0 != eval_~tmp~0#1); 140827#L1164 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 140845#L814-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 140581#L1174-3 assume !(0 == ~M_E~0); 140573#L1174-5 assume !(0 == ~T1_E~0); 140574#L1179-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 148937#L1184-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 149433#L1189-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 149432#L1194-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 149431#L1199-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 149430#L1204-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 149429#L1209-3 assume !(0 == ~T8_E~0); 149428#L1214-3 assume !(0 == ~T9_E~0); 149427#L1219-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 149426#L1224-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 149425#L1229-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 149424#L1234-3 assume 0 == ~E_1~0;~E_1~0 := 1; 149423#L1239-3 assume 0 == ~E_2~0;~E_2~0 := 1; 149422#L1244-3 assume 0 == ~E_3~0;~E_3~0 := 1; 149421#L1249-3 assume !(0 == ~E_4~0); 149420#L1254-3 assume !(0 == ~E_5~0); 149419#L1259-3 assume 0 == ~E_6~0;~E_6~0 := 1; 140352#L1264-3 assume 0 == ~E_7~0;~E_7~0 := 1; 139312#L1269-3 assume 0 == ~E_8~0;~E_8~0 := 1; 139313#L1274-3 assume 0 == ~E_9~0;~E_9~0 := 1; 140791#L1279-3 assume 0 == ~E_10~0;~E_10~0 := 1; 139879#L1284-3 assume 0 == ~E_11~0;~E_11~0 := 1; 139880#L1289-3 assume !(0 == ~E_12~0); 139868#L1294-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 139539#L566-39 assume !(1 == ~m_pc~0); 139540#L566-41 is_master_triggered_~__retres1~0#1 := 0; 140157#L577-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 139859#L578-13 activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 139860#L1455-39 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 140432#L1455-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 140433#L585-39 assume !(1 == ~t1_pc~0); 139546#L585-41 is_transmit1_triggered_~__retres1~1#1 := 0; 139547#L596-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 139622#L597-13 activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 139623#L1463-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 140468#L1463-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 140139#L604-39 assume 1 == ~t2_pc~0; 140140#L605-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 139758#L615-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 139759#L616-13 activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 140190#L1471-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 140191#L1471-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 139738#L623-39 assume 1 == ~t3_pc~0; 139138#L624-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 139140#L634-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 140452#L635-13 activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 139589#L1479-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 139590#L1479-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 140393#L642-39 assume !(1 == ~t4_pc~0); 139942#L642-41 is_transmit4_triggered_~__retres1~4#1 := 0; 139941#L653-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 139463#L654-13 activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 139464#L1487-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 140620#L1487-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 139512#L661-39 assume !(1 == ~t5_pc~0); 139146#L661-41 is_transmit5_triggered_~__retres1~5#1 := 0; 139147#L672-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 149328#L673-13 activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 149326#L1495-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 149323#L1495-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 149321#L680-39 assume 1 == ~t6_pc~0; 149318#L681-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 149233#L691-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 149225#L692-13 activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 149224#L1503-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 149223#L1503-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 149222#L699-39 assume !(1 == ~t7_pc~0); 149220#L699-41 is_transmit7_triggered_~__retres1~7#1 := 0; 149219#L710-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 149218#L711-13 activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 149217#L1511-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 149216#L1511-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 149215#L718-39 assume !(1 == ~t8_pc~0); 149214#L718-41 is_transmit8_triggered_~__retres1~8#1 := 0; 149212#L729-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 149211#L730-13 activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 149210#L1519-39 assume !(0 != activate_threads_~tmp___7~0#1); 149209#L1519-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 149208#L737-39 assume 1 == ~t9_pc~0; 149206#L738-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 149205#L748-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 149204#L749-13 activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 140863#L1527-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 140675#L1527-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 140610#L756-39 assume 1 == ~t10_pc~0; 140611#L757-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 140046#L767-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 139782#L768-13 activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 139783#L1535-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 139918#L1535-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 139252#L775-39 assume !(1 == ~t11_pc~0); 139254#L775-41 is_transmit11_triggered_~__retres1~11#1 := 0; 139911#L786-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 139912#L787-13 activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 140899#L1543-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 140345#L1543-41 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 139970#L794-39 assume 1 == ~t12_pc~0; 139653#L795-13 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 139647#L805-13 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 140515#L806-13 activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 140400#L1551-39 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 139194#L1551-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 139195#L1307-3 assume 1 == ~M_E~0;~M_E~0 := 2; 140736#L1307-5 assume !(1 == ~T1_E~0); 140737#L1312-3 assume !(1 == ~T2_E~0); 140912#L1317-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 140420#L1322-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 140421#L1327-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 139331#L1332-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 139302#L1337-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 139303#L1342-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 140062#L1347-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 140188#L1352-3 assume !(1 == ~T10_E~0); 140189#L1357-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 140682#L1362-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 140898#L1367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 140883#L1372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 139134#L1377-3 assume 1 == ~E_3~0;~E_3~0 := 2; 139135#L1382-3 assume 1 == ~E_4~0;~E_4~0 := 2; 139765#L1387-3 assume 1 == ~E_5~0;~E_5~0 := 2; 139766#L1392-3 assume !(1 == ~E_6~0); 140525#L1397-3 assume 1 == ~E_7~0;~E_7~0 := 2; 140819#L1402-3 assume 1 == ~E_8~0;~E_8~0 := 2; 140156#L1407-3 assume 1 == ~E_9~0;~E_9~0 := 2; 139418#L1412-3 assume 1 == ~E_10~0;~E_10~0 := 2; 139419#L1417-3 assume 1 == ~E_11~0;~E_11~0 := 2; 140078#L1422-3 assume 1 == ~E_12~0;~E_12~0 := 2; 140079#L1427-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 139428#L894-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 139429#L961-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 140320#L962-1 start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1; 140161#L1787 assume !(0 == start_simulation_~tmp~3#1); 140162#L1787-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 140746#L894-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 139399#L961-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 140210#L962-2 stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1; 140211#L1742 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 139746#L1749 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 139747#L1750 start_simulation_#t~ret33#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1; 139748#L1800 assume !(0 != start_simulation_~tmp___0~1#1); 139298#L1768-2 [2022-02-21 04:25:27,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:27,118 INFO L85 PathProgramCache]: Analyzing trace with hash -1204882182, now seen corresponding path program 1 times [2022-02-21 04:25:27,118 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:27,118 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2017520905] [2022-02-21 04:25:27,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:27,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:27,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:27,199 INFO L290 TraceCheckUtils]: 0: Hoare triple {174696#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,199 INFO L290 TraceCheckUtils]: 1: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,200 INFO L290 TraceCheckUtils]: 2: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,200 INFO L290 TraceCheckUtils]: 3: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,201 INFO L290 TraceCheckUtils]: 4: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,201 INFO L290 TraceCheckUtils]: 5: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,202 INFO L290 TraceCheckUtils]: 6: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,202 INFO L290 TraceCheckUtils]: 7: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,202 INFO L290 TraceCheckUtils]: 8: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,203 INFO L290 TraceCheckUtils]: 9: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,203 INFO L290 TraceCheckUtils]: 10: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,204 INFO L290 TraceCheckUtils]: 11: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,204 INFO L290 TraceCheckUtils]: 12: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,205 INFO L290 TraceCheckUtils]: 13: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,205 INFO L290 TraceCheckUtils]: 14: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,205 INFO L290 TraceCheckUtils]: 15: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,206 INFO L290 TraceCheckUtils]: 16: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,207 INFO L290 TraceCheckUtils]: 17: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,208 INFO L290 TraceCheckUtils]: 18: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,208 INFO L290 TraceCheckUtils]: 19: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,209 INFO L290 TraceCheckUtils]: 20: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,223 INFO L290 TraceCheckUtils]: 21: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,224 INFO L290 TraceCheckUtils]: 22: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,224 INFO L290 TraceCheckUtils]: 23: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T5_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,225 INFO L290 TraceCheckUtils]: 24: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T6_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,225 INFO L290 TraceCheckUtils]: 25: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T7_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,225 INFO L290 TraceCheckUtils]: 26: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T8_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,226 INFO L290 TraceCheckUtils]: 27: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T9_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,226 INFO L290 TraceCheckUtils]: 28: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T10_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,227 INFO L290 TraceCheckUtils]: 29: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T11_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,227 INFO L290 TraceCheckUtils]: 30: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T12_E~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,228 INFO L290 TraceCheckUtils]: 31: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,228 INFO L290 TraceCheckUtils]: 32: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,228 INFO L290 TraceCheckUtils]: 33: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,229 INFO L290 TraceCheckUtils]: 34: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,229 INFO L290 TraceCheckUtils]: 35: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_5~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,230 INFO L290 TraceCheckUtils]: 36: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_6~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,230 INFO L290 TraceCheckUtils]: 37: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_7~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,230 INFO L290 TraceCheckUtils]: 38: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_8~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,231 INFO L290 TraceCheckUtils]: 39: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_9~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,231 INFO L290 TraceCheckUtils]: 40: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_10~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,232 INFO L290 TraceCheckUtils]: 41: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_11~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,232 INFO L290 TraceCheckUtils]: 42: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_12~0); {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,232 INFO L290 TraceCheckUtils]: 43: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {174698#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:25:27,233 INFO L290 TraceCheckUtils]: 44: Hoare triple {174698#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {174699#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:25:27,233 INFO L290 TraceCheckUtils]: 45: Hoare triple {174699#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {174699#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:25:27,234 INFO L290 TraceCheckUtils]: 46: Hoare triple {174699#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {174699#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:25:27,234 INFO L290 TraceCheckUtils]: 47: Hoare triple {174699#(not (= ~t1_pc~0 1))} activate_threads_#t~ret18#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {174699#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:25:27,234 INFO L290 TraceCheckUtils]: 48: Hoare triple {174699#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {174699#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:25:27,235 INFO L290 TraceCheckUtils]: 49: Hoare triple {174699#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {174699#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:25:27,235 INFO L290 TraceCheckUtils]: 50: Hoare triple {174699#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {174697#false} is VALID [2022-02-21 04:25:27,235 INFO L290 TraceCheckUtils]: 51: Hoare triple {174697#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {174697#false} is VALID [2022-02-21 04:25:27,235 INFO L290 TraceCheckUtils]: 52: Hoare triple {174697#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {174697#false} is VALID [2022-02-21 04:25:27,236 INFO L290 TraceCheckUtils]: 53: Hoare triple {174697#false} activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {174697#false} is VALID [2022-02-21 04:25:27,236 INFO L290 TraceCheckUtils]: 54: Hoare triple {174697#false} assume !(0 != activate_threads_~tmp___0~0#1); {174697#false} is VALID [2022-02-21 04:25:27,236 INFO L290 TraceCheckUtils]: 55: Hoare triple {174697#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {174697#false} is VALID [2022-02-21 04:25:27,236 INFO L290 TraceCheckUtils]: 56: Hoare triple {174697#false} assume !(1 == ~t2_pc~0); {174697#false} is VALID [2022-02-21 04:25:27,236 INFO L290 TraceCheckUtils]: 57: Hoare triple {174697#false} is_transmit2_triggered_~__retres1~2#1 := 0; {174697#false} is VALID [2022-02-21 04:25:27,236 INFO L290 TraceCheckUtils]: 58: Hoare triple {174697#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {174697#false} is VALID [2022-02-21 04:25:27,237 INFO L290 TraceCheckUtils]: 59: Hoare triple {174697#false} activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {174697#false} is VALID [2022-02-21 04:25:27,237 INFO L290 TraceCheckUtils]: 60: Hoare triple {174697#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {174697#false} is VALID [2022-02-21 04:25:27,237 INFO L290 TraceCheckUtils]: 61: Hoare triple {174697#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {174697#false} is VALID [2022-02-21 04:25:27,237 INFO L290 TraceCheckUtils]: 62: Hoare triple {174697#false} assume 1 == ~t3_pc~0; {174697#false} is VALID [2022-02-21 04:25:27,237 INFO L290 TraceCheckUtils]: 63: Hoare triple {174697#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {174697#false} is VALID [2022-02-21 04:25:27,237 INFO L290 TraceCheckUtils]: 64: Hoare triple {174697#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {174697#false} is VALID [2022-02-21 04:25:27,238 INFO L290 TraceCheckUtils]: 65: Hoare triple {174697#false} activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {174697#false} is VALID [2022-02-21 04:25:27,238 INFO L290 TraceCheckUtils]: 66: Hoare triple {174697#false} assume !(0 != activate_threads_~tmp___2~0#1); {174697#false} is VALID [2022-02-21 04:25:27,238 INFO L290 TraceCheckUtils]: 67: Hoare triple {174697#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {174697#false} is VALID [2022-02-21 04:25:27,238 INFO L290 TraceCheckUtils]: 68: Hoare triple {174697#false} assume !(1 == ~t4_pc~0); {174697#false} is VALID [2022-02-21 04:25:27,238 INFO L290 TraceCheckUtils]: 69: Hoare triple {174697#false} is_transmit4_triggered_~__retres1~4#1 := 0; {174697#false} is VALID [2022-02-21 04:25:27,238 INFO L290 TraceCheckUtils]: 70: Hoare triple {174697#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {174697#false} is VALID [2022-02-21 04:25:27,239 INFO L290 TraceCheckUtils]: 71: Hoare triple {174697#false} activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {174697#false} is VALID [2022-02-21 04:25:27,239 INFO L290 TraceCheckUtils]: 72: Hoare triple {174697#false} assume !(0 != activate_threads_~tmp___3~0#1); {174697#false} is VALID [2022-02-21 04:25:27,239 INFO L290 TraceCheckUtils]: 73: Hoare triple {174697#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {174697#false} is VALID [2022-02-21 04:25:27,239 INFO L290 TraceCheckUtils]: 74: Hoare triple {174697#false} assume 1 == ~t5_pc~0; {174697#false} is VALID [2022-02-21 04:25:27,239 INFO L290 TraceCheckUtils]: 75: Hoare triple {174697#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {174697#false} is VALID [2022-02-21 04:25:27,239 INFO L290 TraceCheckUtils]: 76: Hoare triple {174697#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {174697#false} is VALID [2022-02-21 04:25:27,239 INFO L290 TraceCheckUtils]: 77: Hoare triple {174697#false} activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {174697#false} is VALID [2022-02-21 04:25:27,240 INFO L290 TraceCheckUtils]: 78: Hoare triple {174697#false} assume !(0 != activate_threads_~tmp___4~0#1); {174697#false} is VALID [2022-02-21 04:25:27,240 INFO L290 TraceCheckUtils]: 79: Hoare triple {174697#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {174697#false} is VALID [2022-02-21 04:25:27,240 INFO L290 TraceCheckUtils]: 80: Hoare triple {174697#false} assume !(1 == ~t6_pc~0); {174697#false} is VALID [2022-02-21 04:25:27,240 INFO L290 TraceCheckUtils]: 81: Hoare triple {174697#false} is_transmit6_triggered_~__retres1~6#1 := 0; {174697#false} is VALID [2022-02-21 04:25:27,240 INFO L290 TraceCheckUtils]: 82: Hoare triple {174697#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {174697#false} is VALID [2022-02-21 04:25:27,240 INFO L290 TraceCheckUtils]: 83: Hoare triple {174697#false} activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {174697#false} is VALID [2022-02-21 04:25:27,241 INFO L290 TraceCheckUtils]: 84: Hoare triple {174697#false} assume !(0 != activate_threads_~tmp___5~0#1); {174697#false} is VALID [2022-02-21 04:25:27,241 INFO L290 TraceCheckUtils]: 85: Hoare triple {174697#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {174697#false} is VALID [2022-02-21 04:25:27,241 INFO L290 TraceCheckUtils]: 86: Hoare triple {174697#false} assume 1 == ~t7_pc~0; {174697#false} is VALID [2022-02-21 04:25:27,241 INFO L290 TraceCheckUtils]: 87: Hoare triple {174697#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {174697#false} is VALID [2022-02-21 04:25:27,241 INFO L290 TraceCheckUtils]: 88: Hoare triple {174697#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {174697#false} is VALID [2022-02-21 04:25:27,241 INFO L290 TraceCheckUtils]: 89: Hoare triple {174697#false} activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {174697#false} is VALID [2022-02-21 04:25:27,242 INFO L290 TraceCheckUtils]: 90: Hoare triple {174697#false} assume !(0 != activate_threads_~tmp___6~0#1); {174697#false} is VALID [2022-02-21 04:25:27,242 INFO L290 TraceCheckUtils]: 91: Hoare triple {174697#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {174697#false} is VALID [2022-02-21 04:25:27,242 INFO L290 TraceCheckUtils]: 92: Hoare triple {174697#false} assume !(1 == ~t8_pc~0); {174697#false} is VALID [2022-02-21 04:25:27,242 INFO L290 TraceCheckUtils]: 93: Hoare triple {174697#false} is_transmit8_triggered_~__retres1~8#1 := 0; {174697#false} is VALID [2022-02-21 04:25:27,242 INFO L290 TraceCheckUtils]: 94: Hoare triple {174697#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {174697#false} is VALID [2022-02-21 04:25:27,242 INFO L290 TraceCheckUtils]: 95: Hoare triple {174697#false} activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {174697#false} is VALID [2022-02-21 04:25:27,243 INFO L290 TraceCheckUtils]: 96: Hoare triple {174697#false} assume !(0 != activate_threads_~tmp___7~0#1); {174697#false} is VALID [2022-02-21 04:25:27,243 INFO L290 TraceCheckUtils]: 97: Hoare triple {174697#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {174697#false} is VALID [2022-02-21 04:25:27,243 INFO L290 TraceCheckUtils]: 98: Hoare triple {174697#false} assume 1 == ~t9_pc~0; {174697#false} is VALID [2022-02-21 04:25:27,243 INFO L290 TraceCheckUtils]: 99: Hoare triple {174697#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {174697#false} is VALID [2022-02-21 04:25:27,243 INFO L290 TraceCheckUtils]: 100: Hoare triple {174697#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {174697#false} is VALID [2022-02-21 04:25:27,243 INFO L290 TraceCheckUtils]: 101: Hoare triple {174697#false} activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {174697#false} is VALID [2022-02-21 04:25:27,244 INFO L290 TraceCheckUtils]: 102: Hoare triple {174697#false} assume !(0 != activate_threads_~tmp___8~0#1); {174697#false} is VALID [2022-02-21 04:25:27,244 INFO L290 TraceCheckUtils]: 103: Hoare triple {174697#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {174697#false} is VALID [2022-02-21 04:25:27,244 INFO L290 TraceCheckUtils]: 104: Hoare triple {174697#false} assume 1 == ~t10_pc~0; {174697#false} is VALID [2022-02-21 04:25:27,244 INFO L290 TraceCheckUtils]: 105: Hoare triple {174697#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {174697#false} is VALID [2022-02-21 04:25:27,244 INFO L290 TraceCheckUtils]: 106: Hoare triple {174697#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {174697#false} is VALID [2022-02-21 04:25:27,244 INFO L290 TraceCheckUtils]: 107: Hoare triple {174697#false} activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {174697#false} is VALID [2022-02-21 04:25:27,245 INFO L290 TraceCheckUtils]: 108: Hoare triple {174697#false} assume !(0 != activate_threads_~tmp___9~0#1); {174697#false} is VALID [2022-02-21 04:25:27,245 INFO L290 TraceCheckUtils]: 109: Hoare triple {174697#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {174697#false} is VALID [2022-02-21 04:25:27,245 INFO L290 TraceCheckUtils]: 110: Hoare triple {174697#false} assume !(1 == ~t11_pc~0); {174697#false} is VALID [2022-02-21 04:25:27,245 INFO L290 TraceCheckUtils]: 111: Hoare triple {174697#false} is_transmit11_triggered_~__retres1~11#1 := 0; {174697#false} is VALID [2022-02-21 04:25:27,245 INFO L290 TraceCheckUtils]: 112: Hoare triple {174697#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {174697#false} is VALID [2022-02-21 04:25:27,256 INFO L290 TraceCheckUtils]: 113: Hoare triple {174697#false} activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {174697#false} is VALID [2022-02-21 04:25:27,256 INFO L290 TraceCheckUtils]: 114: Hoare triple {174697#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {174697#false} is VALID [2022-02-21 04:25:27,256 INFO L290 TraceCheckUtils]: 115: Hoare triple {174697#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {174697#false} is VALID [2022-02-21 04:25:27,257 INFO L290 TraceCheckUtils]: 116: Hoare triple {174697#false} assume 1 == ~t12_pc~0; {174697#false} is VALID [2022-02-21 04:25:27,257 INFO L290 TraceCheckUtils]: 117: Hoare triple {174697#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {174697#false} is VALID [2022-02-21 04:25:27,257 INFO L290 TraceCheckUtils]: 118: Hoare triple {174697#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {174697#false} is VALID [2022-02-21 04:25:27,257 INFO L290 TraceCheckUtils]: 119: Hoare triple {174697#false} activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {174697#false} is VALID [2022-02-21 04:25:27,257 INFO L290 TraceCheckUtils]: 120: Hoare triple {174697#false} assume !(0 != activate_threads_~tmp___11~0#1); {174697#false} is VALID [2022-02-21 04:25:27,257 INFO L290 TraceCheckUtils]: 121: Hoare triple {174697#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {174697#false} is VALID [2022-02-21 04:25:27,258 INFO L290 TraceCheckUtils]: 122: Hoare triple {174697#false} assume !(1 == ~M_E~0); {174697#false} is VALID [2022-02-21 04:25:27,258 INFO L290 TraceCheckUtils]: 123: Hoare triple {174697#false} assume !(1 == ~T1_E~0); {174697#false} is VALID [2022-02-21 04:25:27,258 INFO L290 TraceCheckUtils]: 124: Hoare triple {174697#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {174697#false} is VALID [2022-02-21 04:25:27,258 INFO L290 TraceCheckUtils]: 125: Hoare triple {174697#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {174697#false} is VALID [2022-02-21 04:25:27,258 INFO L290 TraceCheckUtils]: 126: Hoare triple {174697#false} assume !(1 == ~T4_E~0); {174697#false} is VALID [2022-02-21 04:25:27,258 INFO L290 TraceCheckUtils]: 127: Hoare triple {174697#false} assume !(1 == ~T5_E~0); {174697#false} is VALID [2022-02-21 04:25:27,258 INFO L290 TraceCheckUtils]: 128: Hoare triple {174697#false} assume !(1 == ~T6_E~0); {174697#false} is VALID [2022-02-21 04:25:27,259 INFO L290 TraceCheckUtils]: 129: Hoare triple {174697#false} assume !(1 == ~T7_E~0); {174697#false} is VALID [2022-02-21 04:25:27,259 INFO L290 TraceCheckUtils]: 130: Hoare triple {174697#false} assume !(1 == ~T8_E~0); {174697#false} is VALID [2022-02-21 04:25:27,259 INFO L290 TraceCheckUtils]: 131: Hoare triple {174697#false} assume !(1 == ~T9_E~0); {174697#false} is VALID [2022-02-21 04:25:27,259 INFO L290 TraceCheckUtils]: 132: Hoare triple {174697#false} assume !(1 == ~T10_E~0); {174697#false} is VALID [2022-02-21 04:25:27,259 INFO L290 TraceCheckUtils]: 133: Hoare triple {174697#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {174697#false} is VALID [2022-02-21 04:25:27,259 INFO L290 TraceCheckUtils]: 134: Hoare triple {174697#false} assume !(1 == ~T12_E~0); {174697#false} is VALID [2022-02-21 04:25:27,259 INFO L290 TraceCheckUtils]: 135: Hoare triple {174697#false} assume !(1 == ~E_1~0); {174697#false} is VALID [2022-02-21 04:25:27,260 INFO L290 TraceCheckUtils]: 136: Hoare triple {174697#false} assume !(1 == ~E_2~0); {174697#false} is VALID [2022-02-21 04:25:27,260 INFO L290 TraceCheckUtils]: 137: Hoare triple {174697#false} assume !(1 == ~E_3~0); {174697#false} is VALID [2022-02-21 04:25:27,260 INFO L290 TraceCheckUtils]: 138: Hoare triple {174697#false} assume !(1 == ~E_4~0); {174697#false} is VALID [2022-02-21 04:25:27,260 INFO L290 TraceCheckUtils]: 139: Hoare triple {174697#false} assume !(1 == ~E_5~0); {174697#false} is VALID [2022-02-21 04:25:27,260 INFO L290 TraceCheckUtils]: 140: Hoare triple {174697#false} assume !(1 == ~E_6~0); {174697#false} is VALID [2022-02-21 04:25:27,260 INFO L290 TraceCheckUtils]: 141: Hoare triple {174697#false} assume 1 == ~E_7~0;~E_7~0 := 2; {174697#false} is VALID [2022-02-21 04:25:27,261 INFO L290 TraceCheckUtils]: 142: Hoare triple {174697#false} assume !(1 == ~E_8~0); {174697#false} is VALID [2022-02-21 04:25:27,261 INFO L290 TraceCheckUtils]: 143: Hoare triple {174697#false} assume !(1 == ~E_9~0); {174697#false} is VALID [2022-02-21 04:25:27,261 INFO L290 TraceCheckUtils]: 144: Hoare triple {174697#false} assume !(1 == ~E_10~0); {174697#false} is VALID [2022-02-21 04:25:27,261 INFO L290 TraceCheckUtils]: 145: Hoare triple {174697#false} assume !(1 == ~E_11~0); {174697#false} is VALID [2022-02-21 04:25:27,261 INFO L290 TraceCheckUtils]: 146: Hoare triple {174697#false} assume !(1 == ~E_12~0); {174697#false} is VALID [2022-02-21 04:25:27,261 INFO L290 TraceCheckUtils]: 147: Hoare triple {174697#false} assume { :end_inline_reset_delta_events } true; {174697#false} is VALID [2022-02-21 04:25:27,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:27,262 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:27,262 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2017520905] [2022-02-21 04:25:27,262 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2017520905] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:27,262 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:27,263 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:27,263 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [294480499] [2022-02-21 04:25:27,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:27,263 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:27,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:27,264 INFO L85 PathProgramCache]: Analyzing trace with hash 781162630, now seen corresponding path program 1 times [2022-02-21 04:25:27,264 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:27,264 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391940608] [2022-02-21 04:25:27,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:27,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms