./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.13.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.13.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:24:17,434 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:24:17,436 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:24:17,467 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:24:17,467 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:24:17,468 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:24:17,469 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:24:17,471 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:24:17,472 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:24:17,473 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:24:17,474 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:24:17,475 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:24:17,477 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:24:17,479 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:24:17,481 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:24:17,483 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:24:17,485 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:24:17,490 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:24:17,491 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:24:17,493 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:24:17,494 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:24:17,495 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:24:17,505 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:24:17,506 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:24:17,508 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:24:17,508 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:24:17,509 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:24:17,509 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:24:17,510 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:24:17,511 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:24:17,511 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:24:17,512 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:24:17,513 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:24:17,514 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:24:17,515 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:24:17,516 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:24:17,517 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:24:17,517 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:24:17,517 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:24:17,518 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:24:17,518 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:24:17,519 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:24:17,594 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:24:17,595 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:24:17,595 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:24:17,596 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:24:17,597 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:24:17,597 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:24:17,597 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:24:17,597 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:24:17,598 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:24:17,598 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:24:17,599 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:24:17,599 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:24:17,599 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:24:17,599 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:24:17,599 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:24:17,600 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:24:17,600 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:24:17,600 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:24:17,600 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:24:17,600 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:24:17,601 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:24:17,601 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:24:17,601 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:24:17,601 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:24:17,601 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:24:17,602 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:24:17,602 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:24:17,602 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:24:17,602 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:24:17,602 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:24:17,603 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:24:17,604 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:24:17,604 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 [2022-02-21 04:24:17,830 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:24:17,858 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:24:17,861 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:24:17,862 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:24:17,863 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:24:17,864 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.13.cil.c [2022-02-21 04:24:17,940 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4125c8d87/77c5f84b63c641fd85316ac8c26bd556/FLAG566cead53 [2022-02-21 04:24:18,471 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:24:18,472 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.13.cil.c [2022-02-21 04:24:18,488 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4125c8d87/77c5f84b63c641fd85316ac8c26bd556/FLAG566cead53 [2022-02-21 04:24:18,812 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/4125c8d87/77c5f84b63c641fd85316ac8c26bd556 [2022-02-21 04:24:18,814 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:24:18,815 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:24:18,816 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:18,817 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:24:18,821 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:24:18,822 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:18" (1/1) ... [2022-02-21 04:24:18,823 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@52433869 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:18, skipping insertion in model container [2022-02-21 04:24:18,823 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:24:18" (1/1) ... [2022-02-21 04:24:18,828 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:24:18,864 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:24:19,019 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2022-02-21 04:24:19,278 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:19,295 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:24:19,307 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2022-02-21 04:24:19,398 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:24:19,421 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:24:19,422 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19 WrapperNode [2022-02-21 04:24:19,422 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:24:19,423 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:19,424 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:24:19,424 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:24:19,430 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,456 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,598 INFO L137 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 64, calls inlined = 286, statements flattened = 4413 [2022-02-21 04:24:19,598 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:24:19,599 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:24:19,600 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:24:19,600 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:24:19,607 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,608 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,618 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,619 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,698 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,753 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,764 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,782 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:24:19,784 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:24:19,784 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:24:19,784 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:24:19,786 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (1/1) ... [2022-02-21 04:24:19,792 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:24:19,803 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:24:19,820 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:24:19,848 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:24:19,865 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:24:19,865 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:24:19,866 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:24:19,866 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:24:19,996 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:24:19,997 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:24:22,225 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:24:22,248 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:24:22,249 INFO L299 CfgBuilder]: Removed 17 assume(true) statements. [2022-02-21 04:24:22,252 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:22 BoogieIcfgContainer [2022-02-21 04:24:22,253 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:24:22,254 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:24:22,254 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:24:22,257 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:24:22,258 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:22,258 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:24:18" (1/3) ... [2022-02-21 04:24:22,259 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6d900180 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:22, skipping insertion in model container [2022-02-21 04:24:22,259 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:22,259 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:24:19" (2/3) ... [2022-02-21 04:24:22,259 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6d900180 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:24:22, skipping insertion in model container [2022-02-21 04:24:22,260 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:24:22,260 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:24:22" (3/3) ... [2022-02-21 04:24:22,261 INFO L388 chiAutomizerObserver]: Analyzing ICFG transmitter.13.cil.c [2022-02-21 04:24:22,301 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:24:22,302 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:24:22,302 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:24:22,302 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:24:22,302 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:24:22,302 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:24:22,302 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:24:22,302 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:24:22,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:22,850 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1744 [2022-02-21 04:24:22,850 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:22,850 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:22,872 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,872 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:22,872 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:24:22,878 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:23,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1744 [2022-02-21 04:24:23,231 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:23,231 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:23,240 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,241 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:23,250 INFO L791 eck$LassoCheckResult]: Stem: 461#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1834#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 352#L1855true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 201#L874true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1760#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 1073#L881-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1411#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 272#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1402#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 545#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 439#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 796#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 306#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 554#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 684#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 804#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 834#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 921#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 313#L946-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1815#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 1400#L1258-2true assume !(0 == ~T1_E~0); 490#L1263-1true assume !(0 == ~T2_E~0); 710#L1268-1true assume !(0 == ~T3_E~0); 1366#L1273-1true assume !(0 == ~T4_E~0); 1749#L1278-1true assume !(0 == ~T5_E~0); 1153#L1283-1true assume !(0 == ~T6_E~0); 1781#L1288-1true assume !(0 == ~T7_E~0); 1569#L1293-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1540#L1298-1true assume !(0 == ~T9_E~0); 1384#L1303-1true assume !(0 == ~T10_E~0); 215#L1308-1true assume !(0 == ~T11_E~0); 186#L1313-1true assume !(0 == ~T12_E~0); 1839#L1318-1true assume !(0 == ~T13_E~0); 189#L1323-1true assume !(0 == ~E_1~0); 277#L1328-1true assume !(0 == ~E_2~0); 1790#L1333-1true assume 0 == ~E_3~0;~E_3~0 := 1; 974#L1338-1true assume !(0 == ~E_4~0); 1113#L1343-1true assume !(0 == ~E_5~0); 1651#L1348-1true assume !(0 == ~E_6~0); 1668#L1353-1true assume !(0 == ~E_7~0); 726#L1358-1true assume !(0 == ~E_8~0); 1000#L1363-1true assume !(0 == ~E_9~0); 1062#L1368-1true assume !(0 == ~E_10~0); 105#L1373-1true assume 0 == ~E_11~0;~E_11~0 := 1; 489#L1378-1true assume !(0 == ~E_12~0); 250#L1383-1true assume !(0 == ~E_13~0); 1102#L1388-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 730#L607true assume 1 == ~m_pc~0; 1010#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1109#L618true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1627#L619true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 668#L1560true assume !(0 != activate_threads_~tmp~1#1); 1725#L1560-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 196#L626true assume !(1 == ~t1_pc~0); 1267#L626-2true is_transmit1_triggered_~__retres1~1#1 := 0; 339#L637true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 441#L638true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1908#L1568true assume !(0 != activate_threads_~tmp___0~0#1); 147#L1568-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1337#L645true assume 1 == ~t2_pc~0; 205#L646true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1301#L656true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 584#L657true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1900#L1576true assume !(0 != activate_threads_~tmp___1~0#1); 653#L1576-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1705#L664true assume 1 == ~t3_pc~0; 1634#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66#L675true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1127#L676true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 417#L1584true assume !(0 != activate_threads_~tmp___2~0#1); 1420#L1584-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1628#L683true assume !(1 == ~t4_pc~0); 987#L683-2true is_transmit4_triggered_~__retres1~4#1 := 0; 786#L694true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 811#L695true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1695#L1592true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 932#L1592-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 615#L702true assume 1 == ~t5_pc~0; 1685#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 926#L713true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1344#L714true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1392#L1600true assume !(0 != activate_threads_~tmp___4~0#1); 1238#L1600-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90#L721true assume !(1 == ~t6_pc~0); 77#L721-2true is_transmit6_triggered_~__retres1~6#1 := 0; 161#L732true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 557#L733true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 422#L1608true assume !(0 != activate_threads_~tmp___5~0#1); 1525#L1608-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 868#L740true assume 1 == ~t7_pc~0; 116#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21#L751true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 758#L752true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16#L1616true assume !(0 != activate_threads_~tmp___6~0#1); 763#L1616-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 385#L759true assume !(1 == ~t8_pc~0); 1374#L759-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1844#L770true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 924#L771true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1084#L1624true assume !(0 != activate_threads_~tmp___7~0#1); 1671#L1624-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1568#L778true assume 1 == ~t9_pc~0; 1342#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1274#L789true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73#L790true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36#L1632true assume !(0 != activate_threads_~tmp___8~0#1); 734#L1632-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 203#L797true assume !(1 == ~t10_pc~0); 265#L797-2true is_transmit10_triggered_~__retres1~10#1 := 0; 1307#L808true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1182#L809true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 488#L1640true assume !(0 != activate_threads_~tmp___9~0#1); 697#L1640-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1391#L816true assume 1 == ~t11_pc~0; 57#L817true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 588#L827true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 463#L828true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 427#L1648true assume !(0 != activate_threads_~tmp___10~0#1); 1512#L1648-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 803#L835true assume 1 == ~t12_pc~0; 706#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 151#L846true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 222#L847true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1784#L1656true assume !(0 != activate_threads_~tmp___11~0#1); 527#L1656-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1443#L854true assume !(1 == ~t13_pc~0); 307#L854-2true is_transmit13_triggered_~__retres1~13#1 := 0; 336#L865true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1082#L866true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 160#L1664true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1231#L1664-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1791#L1401true assume !(1 == ~M_E~0); 419#L1401-2true assume !(1 == ~T1_E~0); 1241#L1406-1true assume !(1 == ~T2_E~0); 859#L1411-1true assume !(1 == ~T3_E~0); 1612#L1416-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 595#L1421-1true assume !(1 == ~T5_E~0); 305#L1426-1true assume !(1 == ~T6_E~0); 1015#L1431-1true assume !(1 == ~T7_E~0); 75#L1436-1true assume !(1 == ~T8_E~0); 746#L1441-1true assume !(1 == ~T9_E~0); 483#L1446-1true assume !(1 == ~T10_E~0); 1773#L1451-1true assume !(1 == ~T11_E~0); 1108#L1456-1true assume 1 == ~T12_E~0;~T12_E~0 := 2; 745#L1461-1true assume !(1 == ~T13_E~0); 436#L1466-1true assume !(1 == ~E_1~0); 1768#L1471-1true assume !(1 == ~E_2~0); 1083#L1476-1true assume !(1 == ~E_3~0); 1315#L1481-1true assume !(1 == ~E_4~0); 1593#L1486-1true assume !(1 == ~E_5~0); 225#L1491-1true assume !(1 == ~E_6~0); 42#L1496-1true assume 1 == ~E_7~0;~E_7~0 := 2; 757#L1501-1true assume !(1 == ~E_8~0); 481#L1506-1true assume !(1 == ~E_9~0); 1038#L1511-1true assume !(1 == ~E_10~0); 454#L1516-1true assume !(1 == ~E_11~0); 14#L1521-1true assume !(1 == ~E_12~0); 41#L1526-1true assume !(1 == ~E_13~0); 319#L1531-1true assume { :end_inline_reset_delta_events } true; 1172#L1892-2true [2022-02-21 04:24:23,253 INFO L793 eck$LassoCheckResult]: Loop: 1172#L1892-2true assume !false; 1868#L1893true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1514#L1233true assume !true; 81#L1248true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 805#L874-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1630#L1258-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1899#L1258-5true assume !(0 == ~T1_E~0); 154#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1604#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1619#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1906#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1621#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 267#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1789#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1169#L1298-3true assume !(0 == ~T9_E~0); 1694#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1428#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1168#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 659#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 155#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1302#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1673#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 229#L1338-3true assume !(0 == ~E_4~0); 1056#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1541#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1312#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1353#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 627#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 340#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1885#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 885#L1378-3true assume !(0 == ~E_12~0); 1460#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1100#L1388-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1767#L607-42true assume !(1 == ~m_pc~0); 912#L607-44true is_master_triggered_~__retres1~0#1 := 0; 510#L618-14true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1076#L619-14true activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 349#L1560-42true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 698#L1560-44true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1220#L626-42true assume 1 == ~t1_pc~0; 399#L627-14true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1472#L637-14true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600#L638-14true activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1131#L1568-42true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 171#L1568-44true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1574#L645-42true assume !(1 == ~t2_pc~0); 1024#L645-44true is_transmit2_triggered_~__retres1~2#1 := 0; 1696#L656-14true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1253#L657-14true activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 278#L1576-42true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24#L1576-44true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1662#L664-42true assume 1 == ~t3_pc~0; 457#L665-14true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1624#L675-14true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1475#L676-14true activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 833#L1584-42true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1016#L1584-44true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1788#L683-42true assume !(1 == ~t4_pc~0); 732#L683-44true is_transmit4_triggered_~__retres1~4#1 := 0; 841#L694-14true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1769#L695-14true activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1412#L1592-42true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1904#L1592-44true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1163#L702-42true assume !(1 == ~t5_pc~0); 395#L702-44true is_transmit5_triggered_~__retres1~5#1 := 0; 590#L713-14true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1734#L714-14true activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1288#L1600-42true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33#L1600-44true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114#L721-42true assume !(1 == ~t6_pc~0); 1582#L721-44true is_transmit6_triggered_~__retres1~6#1 := 0; 368#L732-14true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1620#L733-14true activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1588#L1608-42true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 470#L1608-44true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 379#L740-42true assume !(1 == ~t7_pc~0); 236#L740-44true is_transmit7_triggered_~__retres1~7#1 := 0; 561#L751-14true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 560#L752-14true activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 459#L1616-42true assume !(0 != activate_threads_~tmp___6~0#1); 651#L1616-44true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1896#L759-42true assume 1 == ~t8_pc~0; 540#L760-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 493#L770-14true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 674#L771-14true activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 547#L1624-42true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 617#L1624-44true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1175#L778-42true assume !(1 == ~t9_pc~0); 620#L778-44true is_transmit9_triggered_~__retres1~9#1 := 0; 809#L789-14true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1750#L790-14true activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 733#L1632-42true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1613#L1632-44true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 781#L797-42true assume 1 == ~t10_pc~0; 239#L798-14true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 938#L808-14true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1376#L809-14true activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1877#L1640-42true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 810#L1640-44true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1709#L816-42true assume !(1 == ~t11_pc~0); 347#L816-44true is_transmit11_triggered_~__retres1~11#1 := 0; 1852#L827-14true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 285#L828-14true activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 486#L1648-42true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 328#L1648-44true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 587#L835-42true assume 1 == ~t12_pc~0; 846#L836-14true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1244#L846-14true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 314#L847-14true activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1838#L1656-42true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1237#L1656-44true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 950#L854-42true assume 1 == ~t13_pc~0; 1782#L855-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 482#L865-14true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86#L866-14true activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 515#L1664-42true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 435#L1664-44true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1855#L1401-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1094#L1401-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 204#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 136#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1680#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 465#L1421-3true assume !(1 == ~T5_E~0); 1053#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 228#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 293#L1436-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 17#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1145#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1136#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 521#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 309#L1461-3true assume !(1 == ~T13_E~0); 1611#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1817#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 279#L1476-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1687#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 514#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 292#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1482#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 544#L1501-3true assume !(1 == ~E_8~0); 1595#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 882#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 875#L1516-3true assume 1 == ~E_11~0;~E_11~0 := 2; 1719#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 630#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 970#L1531-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1843#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1881#L1031-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 761#L1032-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 494#L1911true assume !(0 == start_simulation_~tmp~3#1); 1305#L1911-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 907#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1025#L1031-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 843#L1032-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 107#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 520#L1873true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 224#L1874true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1349#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 1172#L1892-2true [2022-02-21 04:24:23,259 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:23,259 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 1 times [2022-02-21 04:24:23,268 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:23,269 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1034903569] [2022-02-21 04:24:23,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:23,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:23,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:23,498 INFO L290 TraceCheckUtils]: 0: Hoare triple {1925#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {1925#true} is VALID [2022-02-21 04:24:23,499 INFO L290 TraceCheckUtils]: 1: Hoare triple {1925#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {1927#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:23,500 INFO L290 TraceCheckUtils]: 2: Hoare triple {1927#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1927#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:23,501 INFO L290 TraceCheckUtils]: 3: Hoare triple {1927#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1927#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:23,501 INFO L290 TraceCheckUtils]: 4: Hoare triple {1927#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,502 INFO L290 TraceCheckUtils]: 5: Hoare triple {1926#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1926#false} is VALID [2022-02-21 04:24:23,502 INFO L290 TraceCheckUtils]: 6: Hoare triple {1926#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,502 INFO L290 TraceCheckUtils]: 7: Hoare triple {1926#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,502 INFO L290 TraceCheckUtils]: 8: Hoare triple {1926#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,503 INFO L290 TraceCheckUtils]: 9: Hoare triple {1926#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,503 INFO L290 TraceCheckUtils]: 10: Hoare triple {1926#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,503 INFO L290 TraceCheckUtils]: 11: Hoare triple {1926#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,503 INFO L290 TraceCheckUtils]: 12: Hoare triple {1926#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,504 INFO L290 TraceCheckUtils]: 13: Hoare triple {1926#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {1926#false} is VALID [2022-02-21 04:24:23,504 INFO L290 TraceCheckUtils]: 14: Hoare triple {1926#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,504 INFO L290 TraceCheckUtils]: 15: Hoare triple {1926#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,504 INFO L290 TraceCheckUtils]: 16: Hoare triple {1926#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,505 INFO L290 TraceCheckUtils]: 17: Hoare triple {1926#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,505 INFO L290 TraceCheckUtils]: 18: Hoare triple {1926#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1926#false} is VALID [2022-02-21 04:24:23,505 INFO L290 TraceCheckUtils]: 19: Hoare triple {1926#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1926#false} is VALID [2022-02-21 04:24:23,505 INFO L290 TraceCheckUtils]: 20: Hoare triple {1926#false} assume !(0 == ~T1_E~0); {1926#false} is VALID [2022-02-21 04:24:23,506 INFO L290 TraceCheckUtils]: 21: Hoare triple {1926#false} assume !(0 == ~T2_E~0); {1926#false} is VALID [2022-02-21 04:24:23,506 INFO L290 TraceCheckUtils]: 22: Hoare triple {1926#false} assume !(0 == ~T3_E~0); {1926#false} is VALID [2022-02-21 04:24:23,506 INFO L290 TraceCheckUtils]: 23: Hoare triple {1926#false} assume !(0 == ~T4_E~0); {1926#false} is VALID [2022-02-21 04:24:23,506 INFO L290 TraceCheckUtils]: 24: Hoare triple {1926#false} assume !(0 == ~T5_E~0); {1926#false} is VALID [2022-02-21 04:24:23,507 INFO L290 TraceCheckUtils]: 25: Hoare triple {1926#false} assume !(0 == ~T6_E~0); {1926#false} is VALID [2022-02-21 04:24:23,507 INFO L290 TraceCheckUtils]: 26: Hoare triple {1926#false} assume !(0 == ~T7_E~0); {1926#false} is VALID [2022-02-21 04:24:23,507 INFO L290 TraceCheckUtils]: 27: Hoare triple {1926#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1926#false} is VALID [2022-02-21 04:24:23,507 INFO L290 TraceCheckUtils]: 28: Hoare triple {1926#false} assume !(0 == ~T9_E~0); {1926#false} is VALID [2022-02-21 04:24:23,508 INFO L290 TraceCheckUtils]: 29: Hoare triple {1926#false} assume !(0 == ~T10_E~0); {1926#false} is VALID [2022-02-21 04:24:23,508 INFO L290 TraceCheckUtils]: 30: Hoare triple {1926#false} assume !(0 == ~T11_E~0); {1926#false} is VALID [2022-02-21 04:24:23,508 INFO L290 TraceCheckUtils]: 31: Hoare triple {1926#false} assume !(0 == ~T12_E~0); {1926#false} is VALID [2022-02-21 04:24:23,508 INFO L290 TraceCheckUtils]: 32: Hoare triple {1926#false} assume !(0 == ~T13_E~0); {1926#false} is VALID [2022-02-21 04:24:23,509 INFO L290 TraceCheckUtils]: 33: Hoare triple {1926#false} assume !(0 == ~E_1~0); {1926#false} is VALID [2022-02-21 04:24:23,509 INFO L290 TraceCheckUtils]: 34: Hoare triple {1926#false} assume !(0 == ~E_2~0); {1926#false} is VALID [2022-02-21 04:24:23,509 INFO L290 TraceCheckUtils]: 35: Hoare triple {1926#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1926#false} is VALID [2022-02-21 04:24:23,509 INFO L290 TraceCheckUtils]: 36: Hoare triple {1926#false} assume !(0 == ~E_4~0); {1926#false} is VALID [2022-02-21 04:24:23,510 INFO L290 TraceCheckUtils]: 37: Hoare triple {1926#false} assume !(0 == ~E_5~0); {1926#false} is VALID [2022-02-21 04:24:23,510 INFO L290 TraceCheckUtils]: 38: Hoare triple {1926#false} assume !(0 == ~E_6~0); {1926#false} is VALID [2022-02-21 04:24:23,510 INFO L290 TraceCheckUtils]: 39: Hoare triple {1926#false} assume !(0 == ~E_7~0); {1926#false} is VALID [2022-02-21 04:24:23,510 INFO L290 TraceCheckUtils]: 40: Hoare triple {1926#false} assume !(0 == ~E_8~0); {1926#false} is VALID [2022-02-21 04:24:23,511 INFO L290 TraceCheckUtils]: 41: Hoare triple {1926#false} assume !(0 == ~E_9~0); {1926#false} is VALID [2022-02-21 04:24:23,511 INFO L290 TraceCheckUtils]: 42: Hoare triple {1926#false} assume !(0 == ~E_10~0); {1926#false} is VALID [2022-02-21 04:24:23,511 INFO L290 TraceCheckUtils]: 43: Hoare triple {1926#false} assume 0 == ~E_11~0;~E_11~0 := 1; {1926#false} is VALID [2022-02-21 04:24:23,511 INFO L290 TraceCheckUtils]: 44: Hoare triple {1926#false} assume !(0 == ~E_12~0); {1926#false} is VALID [2022-02-21 04:24:23,512 INFO L290 TraceCheckUtils]: 45: Hoare triple {1926#false} assume !(0 == ~E_13~0); {1926#false} is VALID [2022-02-21 04:24:23,512 INFO L290 TraceCheckUtils]: 46: Hoare triple {1926#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1926#false} is VALID [2022-02-21 04:24:23,512 INFO L290 TraceCheckUtils]: 47: Hoare triple {1926#false} assume 1 == ~m_pc~0; {1926#false} is VALID [2022-02-21 04:24:23,512 INFO L290 TraceCheckUtils]: 48: Hoare triple {1926#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {1926#false} is VALID [2022-02-21 04:24:23,513 INFO L290 TraceCheckUtils]: 49: Hoare triple {1926#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1926#false} is VALID [2022-02-21 04:24:23,513 INFO L290 TraceCheckUtils]: 50: Hoare triple {1926#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1926#false} is VALID [2022-02-21 04:24:23,513 INFO L290 TraceCheckUtils]: 51: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp~1#1); {1926#false} is VALID [2022-02-21 04:24:23,513 INFO L290 TraceCheckUtils]: 52: Hoare triple {1926#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1926#false} is VALID [2022-02-21 04:24:23,514 INFO L290 TraceCheckUtils]: 53: Hoare triple {1926#false} assume !(1 == ~t1_pc~0); {1926#false} is VALID [2022-02-21 04:24:23,514 INFO L290 TraceCheckUtils]: 54: Hoare triple {1926#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1926#false} is VALID [2022-02-21 04:24:23,514 INFO L290 TraceCheckUtils]: 55: Hoare triple {1926#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1926#false} is VALID [2022-02-21 04:24:23,514 INFO L290 TraceCheckUtils]: 56: Hoare triple {1926#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1926#false} is VALID [2022-02-21 04:24:23,515 INFO L290 TraceCheckUtils]: 57: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp___0~0#1); {1926#false} is VALID [2022-02-21 04:24:23,515 INFO L290 TraceCheckUtils]: 58: Hoare triple {1926#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1926#false} is VALID [2022-02-21 04:24:23,515 INFO L290 TraceCheckUtils]: 59: Hoare triple {1926#false} assume 1 == ~t2_pc~0; {1926#false} is VALID [2022-02-21 04:24:23,515 INFO L290 TraceCheckUtils]: 60: Hoare triple {1926#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1926#false} is VALID [2022-02-21 04:24:23,516 INFO L290 TraceCheckUtils]: 61: Hoare triple {1926#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1926#false} is VALID [2022-02-21 04:24:23,516 INFO L290 TraceCheckUtils]: 62: Hoare triple {1926#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1926#false} is VALID [2022-02-21 04:24:23,516 INFO L290 TraceCheckUtils]: 63: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp___1~0#1); {1926#false} is VALID [2022-02-21 04:24:23,516 INFO L290 TraceCheckUtils]: 64: Hoare triple {1926#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1926#false} is VALID [2022-02-21 04:24:23,517 INFO L290 TraceCheckUtils]: 65: Hoare triple {1926#false} assume 1 == ~t3_pc~0; {1926#false} is VALID [2022-02-21 04:24:23,517 INFO L290 TraceCheckUtils]: 66: Hoare triple {1926#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1926#false} is VALID [2022-02-21 04:24:23,517 INFO L290 TraceCheckUtils]: 67: Hoare triple {1926#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1926#false} is VALID [2022-02-21 04:24:23,518 INFO L290 TraceCheckUtils]: 68: Hoare triple {1926#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1926#false} is VALID [2022-02-21 04:24:23,518 INFO L290 TraceCheckUtils]: 69: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp___2~0#1); {1926#false} is VALID [2022-02-21 04:24:23,518 INFO L290 TraceCheckUtils]: 70: Hoare triple {1926#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1926#false} is VALID [2022-02-21 04:24:23,519 INFO L290 TraceCheckUtils]: 71: Hoare triple {1926#false} assume !(1 == ~t4_pc~0); {1926#false} is VALID [2022-02-21 04:24:23,519 INFO L290 TraceCheckUtils]: 72: Hoare triple {1926#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1926#false} is VALID [2022-02-21 04:24:23,519 INFO L290 TraceCheckUtils]: 73: Hoare triple {1926#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1926#false} is VALID [2022-02-21 04:24:23,519 INFO L290 TraceCheckUtils]: 74: Hoare triple {1926#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1926#false} is VALID [2022-02-21 04:24:23,520 INFO L290 TraceCheckUtils]: 75: Hoare triple {1926#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1926#false} is VALID [2022-02-21 04:24:23,520 INFO L290 TraceCheckUtils]: 76: Hoare triple {1926#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1926#false} is VALID [2022-02-21 04:24:23,520 INFO L290 TraceCheckUtils]: 77: Hoare triple {1926#false} assume 1 == ~t5_pc~0; {1926#false} is VALID [2022-02-21 04:24:23,520 INFO L290 TraceCheckUtils]: 78: Hoare triple {1926#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {1926#false} is VALID [2022-02-21 04:24:23,521 INFO L290 TraceCheckUtils]: 79: Hoare triple {1926#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1926#false} is VALID [2022-02-21 04:24:23,521 INFO L290 TraceCheckUtils]: 80: Hoare triple {1926#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1926#false} is VALID [2022-02-21 04:24:23,521 INFO L290 TraceCheckUtils]: 81: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp___4~0#1); {1926#false} is VALID [2022-02-21 04:24:23,521 INFO L290 TraceCheckUtils]: 82: Hoare triple {1926#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1926#false} is VALID [2022-02-21 04:24:23,522 INFO L290 TraceCheckUtils]: 83: Hoare triple {1926#false} assume !(1 == ~t6_pc~0); {1926#false} is VALID [2022-02-21 04:24:23,522 INFO L290 TraceCheckUtils]: 84: Hoare triple {1926#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1926#false} is VALID [2022-02-21 04:24:23,522 INFO L290 TraceCheckUtils]: 85: Hoare triple {1926#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1926#false} is VALID [2022-02-21 04:24:23,522 INFO L290 TraceCheckUtils]: 86: Hoare triple {1926#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1926#false} is VALID [2022-02-21 04:24:23,523 INFO L290 TraceCheckUtils]: 87: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp___5~0#1); {1926#false} is VALID [2022-02-21 04:24:23,523 INFO L290 TraceCheckUtils]: 88: Hoare triple {1926#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1926#false} is VALID [2022-02-21 04:24:23,523 INFO L290 TraceCheckUtils]: 89: Hoare triple {1926#false} assume 1 == ~t7_pc~0; {1926#false} is VALID [2022-02-21 04:24:23,523 INFO L290 TraceCheckUtils]: 90: Hoare triple {1926#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {1926#false} is VALID [2022-02-21 04:24:23,524 INFO L290 TraceCheckUtils]: 91: Hoare triple {1926#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1926#false} is VALID [2022-02-21 04:24:23,524 INFO L290 TraceCheckUtils]: 92: Hoare triple {1926#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1926#false} is VALID [2022-02-21 04:24:23,524 INFO L290 TraceCheckUtils]: 93: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp___6~0#1); {1926#false} is VALID [2022-02-21 04:24:23,524 INFO L290 TraceCheckUtils]: 94: Hoare triple {1926#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1926#false} is VALID [2022-02-21 04:24:23,525 INFO L290 TraceCheckUtils]: 95: Hoare triple {1926#false} assume !(1 == ~t8_pc~0); {1926#false} is VALID [2022-02-21 04:24:23,525 INFO L290 TraceCheckUtils]: 96: Hoare triple {1926#false} is_transmit8_triggered_~__retres1~8#1 := 0; {1926#false} is VALID [2022-02-21 04:24:23,525 INFO L290 TraceCheckUtils]: 97: Hoare triple {1926#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1926#false} is VALID [2022-02-21 04:24:23,525 INFO L290 TraceCheckUtils]: 98: Hoare triple {1926#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1926#false} is VALID [2022-02-21 04:24:23,525 INFO L290 TraceCheckUtils]: 99: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp___7~0#1); {1926#false} is VALID [2022-02-21 04:24:23,526 INFO L290 TraceCheckUtils]: 100: Hoare triple {1926#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1926#false} is VALID [2022-02-21 04:24:23,526 INFO L290 TraceCheckUtils]: 101: Hoare triple {1926#false} assume 1 == ~t9_pc~0; {1926#false} is VALID [2022-02-21 04:24:23,526 INFO L290 TraceCheckUtils]: 102: Hoare triple {1926#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {1926#false} is VALID [2022-02-21 04:24:23,526 INFO L290 TraceCheckUtils]: 103: Hoare triple {1926#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1926#false} is VALID [2022-02-21 04:24:23,527 INFO L290 TraceCheckUtils]: 104: Hoare triple {1926#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1926#false} is VALID [2022-02-21 04:24:23,527 INFO L290 TraceCheckUtils]: 105: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp___8~0#1); {1926#false} is VALID [2022-02-21 04:24:23,527 INFO L290 TraceCheckUtils]: 106: Hoare triple {1926#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1926#false} is VALID [2022-02-21 04:24:23,527 INFO L290 TraceCheckUtils]: 107: Hoare triple {1926#false} assume !(1 == ~t10_pc~0); {1926#false} is VALID [2022-02-21 04:24:23,528 INFO L290 TraceCheckUtils]: 108: Hoare triple {1926#false} is_transmit10_triggered_~__retres1~10#1 := 0; {1926#false} is VALID [2022-02-21 04:24:23,528 INFO L290 TraceCheckUtils]: 109: Hoare triple {1926#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1926#false} is VALID [2022-02-21 04:24:23,528 INFO L290 TraceCheckUtils]: 110: Hoare triple {1926#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1926#false} is VALID [2022-02-21 04:24:23,528 INFO L290 TraceCheckUtils]: 111: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp___9~0#1); {1926#false} is VALID [2022-02-21 04:24:23,529 INFO L290 TraceCheckUtils]: 112: Hoare triple {1926#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1926#false} is VALID [2022-02-21 04:24:23,529 INFO L290 TraceCheckUtils]: 113: Hoare triple {1926#false} assume 1 == ~t11_pc~0; {1926#false} is VALID [2022-02-21 04:24:23,529 INFO L290 TraceCheckUtils]: 114: Hoare triple {1926#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {1926#false} is VALID [2022-02-21 04:24:23,529 INFO L290 TraceCheckUtils]: 115: Hoare triple {1926#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1926#false} is VALID [2022-02-21 04:24:23,530 INFO L290 TraceCheckUtils]: 116: Hoare triple {1926#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {1926#false} is VALID [2022-02-21 04:24:23,530 INFO L290 TraceCheckUtils]: 117: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp___10~0#1); {1926#false} is VALID [2022-02-21 04:24:23,530 INFO L290 TraceCheckUtils]: 118: Hoare triple {1926#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {1926#false} is VALID [2022-02-21 04:24:23,530 INFO L290 TraceCheckUtils]: 119: Hoare triple {1926#false} assume 1 == ~t12_pc~0; {1926#false} is VALID [2022-02-21 04:24:23,531 INFO L290 TraceCheckUtils]: 120: Hoare triple {1926#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {1926#false} is VALID [2022-02-21 04:24:23,531 INFO L290 TraceCheckUtils]: 121: Hoare triple {1926#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {1926#false} is VALID [2022-02-21 04:24:23,531 INFO L290 TraceCheckUtils]: 122: Hoare triple {1926#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {1926#false} is VALID [2022-02-21 04:24:23,531 INFO L290 TraceCheckUtils]: 123: Hoare triple {1926#false} assume !(0 != activate_threads_~tmp___11~0#1); {1926#false} is VALID [2022-02-21 04:24:23,532 INFO L290 TraceCheckUtils]: 124: Hoare triple {1926#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {1926#false} is VALID [2022-02-21 04:24:23,532 INFO L290 TraceCheckUtils]: 125: Hoare triple {1926#false} assume !(1 == ~t13_pc~0); {1926#false} is VALID [2022-02-21 04:24:23,532 INFO L290 TraceCheckUtils]: 126: Hoare triple {1926#false} is_transmit13_triggered_~__retres1~13#1 := 0; {1926#false} is VALID [2022-02-21 04:24:23,532 INFO L290 TraceCheckUtils]: 127: Hoare triple {1926#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {1926#false} is VALID [2022-02-21 04:24:23,533 INFO L290 TraceCheckUtils]: 128: Hoare triple {1926#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {1926#false} is VALID [2022-02-21 04:24:23,533 INFO L290 TraceCheckUtils]: 129: Hoare triple {1926#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {1926#false} is VALID [2022-02-21 04:24:23,533 INFO L290 TraceCheckUtils]: 130: Hoare triple {1926#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1926#false} is VALID [2022-02-21 04:24:23,533 INFO L290 TraceCheckUtils]: 131: Hoare triple {1926#false} assume !(1 == ~M_E~0); {1926#false} is VALID [2022-02-21 04:24:23,533 INFO L290 TraceCheckUtils]: 132: Hoare triple {1926#false} assume !(1 == ~T1_E~0); {1926#false} is VALID [2022-02-21 04:24:23,534 INFO L290 TraceCheckUtils]: 133: Hoare triple {1926#false} assume !(1 == ~T2_E~0); {1926#false} is VALID [2022-02-21 04:24:23,534 INFO L290 TraceCheckUtils]: 134: Hoare triple {1926#false} assume !(1 == ~T3_E~0); {1926#false} is VALID [2022-02-21 04:24:23,534 INFO L290 TraceCheckUtils]: 135: Hoare triple {1926#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,534 INFO L290 TraceCheckUtils]: 136: Hoare triple {1926#false} assume !(1 == ~T5_E~0); {1926#false} is VALID [2022-02-21 04:24:23,535 INFO L290 TraceCheckUtils]: 137: Hoare triple {1926#false} assume !(1 == ~T6_E~0); {1926#false} is VALID [2022-02-21 04:24:23,535 INFO L290 TraceCheckUtils]: 138: Hoare triple {1926#false} assume !(1 == ~T7_E~0); {1926#false} is VALID [2022-02-21 04:24:23,535 INFO L290 TraceCheckUtils]: 139: Hoare triple {1926#false} assume !(1 == ~T8_E~0); {1926#false} is VALID [2022-02-21 04:24:23,535 INFO L290 TraceCheckUtils]: 140: Hoare triple {1926#false} assume !(1 == ~T9_E~0); {1926#false} is VALID [2022-02-21 04:24:23,536 INFO L290 TraceCheckUtils]: 141: Hoare triple {1926#false} assume !(1 == ~T10_E~0); {1926#false} is VALID [2022-02-21 04:24:23,536 INFO L290 TraceCheckUtils]: 142: Hoare triple {1926#false} assume !(1 == ~T11_E~0); {1926#false} is VALID [2022-02-21 04:24:23,536 INFO L290 TraceCheckUtils]: 143: Hoare triple {1926#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,536 INFO L290 TraceCheckUtils]: 144: Hoare triple {1926#false} assume !(1 == ~T13_E~0); {1926#false} is VALID [2022-02-21 04:24:23,536 INFO L290 TraceCheckUtils]: 145: Hoare triple {1926#false} assume !(1 == ~E_1~0); {1926#false} is VALID [2022-02-21 04:24:23,537 INFO L290 TraceCheckUtils]: 146: Hoare triple {1926#false} assume !(1 == ~E_2~0); {1926#false} is VALID [2022-02-21 04:24:23,537 INFO L290 TraceCheckUtils]: 147: Hoare triple {1926#false} assume !(1 == ~E_3~0); {1926#false} is VALID [2022-02-21 04:24:23,537 INFO L290 TraceCheckUtils]: 148: Hoare triple {1926#false} assume !(1 == ~E_4~0); {1926#false} is VALID [2022-02-21 04:24:23,537 INFO L290 TraceCheckUtils]: 149: Hoare triple {1926#false} assume !(1 == ~E_5~0); {1926#false} is VALID [2022-02-21 04:24:23,537 INFO L290 TraceCheckUtils]: 150: Hoare triple {1926#false} assume !(1 == ~E_6~0); {1926#false} is VALID [2022-02-21 04:24:23,538 INFO L290 TraceCheckUtils]: 151: Hoare triple {1926#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1926#false} is VALID [2022-02-21 04:24:23,538 INFO L290 TraceCheckUtils]: 152: Hoare triple {1926#false} assume !(1 == ~E_8~0); {1926#false} is VALID [2022-02-21 04:24:23,538 INFO L290 TraceCheckUtils]: 153: Hoare triple {1926#false} assume !(1 == ~E_9~0); {1926#false} is VALID [2022-02-21 04:24:23,538 INFO L290 TraceCheckUtils]: 154: Hoare triple {1926#false} assume !(1 == ~E_10~0); {1926#false} is VALID [2022-02-21 04:24:23,539 INFO L290 TraceCheckUtils]: 155: Hoare triple {1926#false} assume !(1 == ~E_11~0); {1926#false} is VALID [2022-02-21 04:24:23,539 INFO L290 TraceCheckUtils]: 156: Hoare triple {1926#false} assume !(1 == ~E_12~0); {1926#false} is VALID [2022-02-21 04:24:23,539 INFO L290 TraceCheckUtils]: 157: Hoare triple {1926#false} assume !(1 == ~E_13~0); {1926#false} is VALID [2022-02-21 04:24:23,539 INFO L290 TraceCheckUtils]: 158: Hoare triple {1926#false} assume { :end_inline_reset_delta_events } true; {1926#false} is VALID [2022-02-21 04:24:23,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:23,542 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:23,542 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1034903569] [2022-02-21 04:24:23,543 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1034903569] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:23,543 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:23,543 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:23,544 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [941161582] [2022-02-21 04:24:23,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:23,549 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:23,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:23,550 INFO L85 PathProgramCache]: Analyzing trace with hash -1573044070, now seen corresponding path program 1 times [2022-02-21 04:24:23,550 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:23,551 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [389722673] [2022-02-21 04:24:23,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:23,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:23,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:23,599 INFO L290 TraceCheckUtils]: 0: Hoare triple {1928#true} assume !false; {1928#true} is VALID [2022-02-21 04:24:23,599 INFO L290 TraceCheckUtils]: 1: Hoare triple {1928#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1928#true} is VALID [2022-02-21 04:24:23,600 INFO L290 TraceCheckUtils]: 2: Hoare triple {1928#true} assume !true; {1929#false} is VALID [2022-02-21 04:24:23,600 INFO L290 TraceCheckUtils]: 3: Hoare triple {1929#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1929#false} is VALID [2022-02-21 04:24:23,600 INFO L290 TraceCheckUtils]: 4: Hoare triple {1929#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1929#false} is VALID [2022-02-21 04:24:23,600 INFO L290 TraceCheckUtils]: 5: Hoare triple {1929#false} assume 0 == ~M_E~0;~M_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,601 INFO L290 TraceCheckUtils]: 6: Hoare triple {1929#false} assume !(0 == ~T1_E~0); {1929#false} is VALID [2022-02-21 04:24:23,601 INFO L290 TraceCheckUtils]: 7: Hoare triple {1929#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,601 INFO L290 TraceCheckUtils]: 8: Hoare triple {1929#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,601 INFO L290 TraceCheckUtils]: 9: Hoare triple {1929#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,601 INFO L290 TraceCheckUtils]: 10: Hoare triple {1929#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,602 INFO L290 TraceCheckUtils]: 11: Hoare triple {1929#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,602 INFO L290 TraceCheckUtils]: 12: Hoare triple {1929#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,602 INFO L290 TraceCheckUtils]: 13: Hoare triple {1929#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,602 INFO L290 TraceCheckUtils]: 14: Hoare triple {1929#false} assume !(0 == ~T9_E~0); {1929#false} is VALID [2022-02-21 04:24:23,602 INFO L290 TraceCheckUtils]: 15: Hoare triple {1929#false} assume 0 == ~T10_E~0;~T10_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,603 INFO L290 TraceCheckUtils]: 16: Hoare triple {1929#false} assume 0 == ~T11_E~0;~T11_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,603 INFO L290 TraceCheckUtils]: 17: Hoare triple {1929#false} assume 0 == ~T12_E~0;~T12_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,603 INFO L290 TraceCheckUtils]: 18: Hoare triple {1929#false} assume 0 == ~T13_E~0;~T13_E~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,603 INFO L290 TraceCheckUtils]: 19: Hoare triple {1929#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,604 INFO L290 TraceCheckUtils]: 20: Hoare triple {1929#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,604 INFO L290 TraceCheckUtils]: 21: Hoare triple {1929#false} assume 0 == ~E_3~0;~E_3~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,604 INFO L290 TraceCheckUtils]: 22: Hoare triple {1929#false} assume !(0 == ~E_4~0); {1929#false} is VALID [2022-02-21 04:24:23,604 INFO L290 TraceCheckUtils]: 23: Hoare triple {1929#false} assume 0 == ~E_5~0;~E_5~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,605 INFO L290 TraceCheckUtils]: 24: Hoare triple {1929#false} assume 0 == ~E_6~0;~E_6~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,605 INFO L290 TraceCheckUtils]: 25: Hoare triple {1929#false} assume 0 == ~E_7~0;~E_7~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,605 INFO L290 TraceCheckUtils]: 26: Hoare triple {1929#false} assume 0 == ~E_8~0;~E_8~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,605 INFO L290 TraceCheckUtils]: 27: Hoare triple {1929#false} assume 0 == ~E_9~0;~E_9~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,605 INFO L290 TraceCheckUtils]: 28: Hoare triple {1929#false} assume 0 == ~E_10~0;~E_10~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,606 INFO L290 TraceCheckUtils]: 29: Hoare triple {1929#false} assume 0 == ~E_11~0;~E_11~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,606 INFO L290 TraceCheckUtils]: 30: Hoare triple {1929#false} assume !(0 == ~E_12~0); {1929#false} is VALID [2022-02-21 04:24:23,606 INFO L290 TraceCheckUtils]: 31: Hoare triple {1929#false} assume 0 == ~E_13~0;~E_13~0 := 1; {1929#false} is VALID [2022-02-21 04:24:23,606 INFO L290 TraceCheckUtils]: 32: Hoare triple {1929#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1929#false} is VALID [2022-02-21 04:24:23,606 INFO L290 TraceCheckUtils]: 33: Hoare triple {1929#false} assume !(1 == ~m_pc~0); {1929#false} is VALID [2022-02-21 04:24:23,607 INFO L290 TraceCheckUtils]: 34: Hoare triple {1929#false} is_master_triggered_~__retres1~0#1 := 0; {1929#false} is VALID [2022-02-21 04:24:23,607 INFO L290 TraceCheckUtils]: 35: Hoare triple {1929#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1929#false} is VALID [2022-02-21 04:24:23,607 INFO L290 TraceCheckUtils]: 36: Hoare triple {1929#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {1929#false} is VALID [2022-02-21 04:24:23,607 INFO L290 TraceCheckUtils]: 37: Hoare triple {1929#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,608 INFO L290 TraceCheckUtils]: 38: Hoare triple {1929#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1929#false} is VALID [2022-02-21 04:24:23,608 INFO L290 TraceCheckUtils]: 39: Hoare triple {1929#false} assume 1 == ~t1_pc~0; {1929#false} is VALID [2022-02-21 04:24:23,608 INFO L290 TraceCheckUtils]: 40: Hoare triple {1929#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1929#false} is VALID [2022-02-21 04:24:23,608 INFO L290 TraceCheckUtils]: 41: Hoare triple {1929#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1929#false} is VALID [2022-02-21 04:24:23,609 INFO L290 TraceCheckUtils]: 42: Hoare triple {1929#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {1929#false} is VALID [2022-02-21 04:24:23,609 INFO L290 TraceCheckUtils]: 43: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,609 INFO L290 TraceCheckUtils]: 44: Hoare triple {1929#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1929#false} is VALID [2022-02-21 04:24:23,609 INFO L290 TraceCheckUtils]: 45: Hoare triple {1929#false} assume !(1 == ~t2_pc~0); {1929#false} is VALID [2022-02-21 04:24:23,609 INFO L290 TraceCheckUtils]: 46: Hoare triple {1929#false} is_transmit2_triggered_~__retres1~2#1 := 0; {1929#false} is VALID [2022-02-21 04:24:23,610 INFO L290 TraceCheckUtils]: 47: Hoare triple {1929#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1929#false} is VALID [2022-02-21 04:24:23,610 INFO L290 TraceCheckUtils]: 48: Hoare triple {1929#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {1929#false} is VALID [2022-02-21 04:24:23,610 INFO L290 TraceCheckUtils]: 49: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,610 INFO L290 TraceCheckUtils]: 50: Hoare triple {1929#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1929#false} is VALID [2022-02-21 04:24:23,611 INFO L290 TraceCheckUtils]: 51: Hoare triple {1929#false} assume 1 == ~t3_pc~0; {1929#false} is VALID [2022-02-21 04:24:23,611 INFO L290 TraceCheckUtils]: 52: Hoare triple {1929#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1929#false} is VALID [2022-02-21 04:24:23,611 INFO L290 TraceCheckUtils]: 53: Hoare triple {1929#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1929#false} is VALID [2022-02-21 04:24:23,611 INFO L290 TraceCheckUtils]: 54: Hoare triple {1929#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {1929#false} is VALID [2022-02-21 04:24:23,611 INFO L290 TraceCheckUtils]: 55: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,612 INFO L290 TraceCheckUtils]: 56: Hoare triple {1929#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {1929#false} is VALID [2022-02-21 04:24:23,612 INFO L290 TraceCheckUtils]: 57: Hoare triple {1929#false} assume !(1 == ~t4_pc~0); {1929#false} is VALID [2022-02-21 04:24:23,612 INFO L290 TraceCheckUtils]: 58: Hoare triple {1929#false} is_transmit4_triggered_~__retres1~4#1 := 0; {1929#false} is VALID [2022-02-21 04:24:23,612 INFO L290 TraceCheckUtils]: 59: Hoare triple {1929#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {1929#false} is VALID [2022-02-21 04:24:23,613 INFO L290 TraceCheckUtils]: 60: Hoare triple {1929#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {1929#false} is VALID [2022-02-21 04:24:23,613 INFO L290 TraceCheckUtils]: 61: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,613 INFO L290 TraceCheckUtils]: 62: Hoare triple {1929#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {1929#false} is VALID [2022-02-21 04:24:23,613 INFO L290 TraceCheckUtils]: 63: Hoare triple {1929#false} assume !(1 == ~t5_pc~0); {1929#false} is VALID [2022-02-21 04:24:23,614 INFO L290 TraceCheckUtils]: 64: Hoare triple {1929#false} is_transmit5_triggered_~__retres1~5#1 := 0; {1929#false} is VALID [2022-02-21 04:24:23,614 INFO L290 TraceCheckUtils]: 65: Hoare triple {1929#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {1929#false} is VALID [2022-02-21 04:24:23,614 INFO L290 TraceCheckUtils]: 66: Hoare triple {1929#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {1929#false} is VALID [2022-02-21 04:24:23,614 INFO L290 TraceCheckUtils]: 67: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,614 INFO L290 TraceCheckUtils]: 68: Hoare triple {1929#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {1929#false} is VALID [2022-02-21 04:24:23,615 INFO L290 TraceCheckUtils]: 69: Hoare triple {1929#false} assume !(1 == ~t6_pc~0); {1929#false} is VALID [2022-02-21 04:24:23,615 INFO L290 TraceCheckUtils]: 70: Hoare triple {1929#false} is_transmit6_triggered_~__retres1~6#1 := 0; {1929#false} is VALID [2022-02-21 04:24:23,617 INFO L290 TraceCheckUtils]: 71: Hoare triple {1929#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {1929#false} is VALID [2022-02-21 04:24:23,618 INFO L290 TraceCheckUtils]: 72: Hoare triple {1929#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {1929#false} is VALID [2022-02-21 04:24:23,618 INFO L290 TraceCheckUtils]: 73: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,618 INFO L290 TraceCheckUtils]: 74: Hoare triple {1929#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {1929#false} is VALID [2022-02-21 04:24:23,618 INFO L290 TraceCheckUtils]: 75: Hoare triple {1929#false} assume !(1 == ~t7_pc~0); {1929#false} is VALID [2022-02-21 04:24:23,618 INFO L290 TraceCheckUtils]: 76: Hoare triple {1929#false} is_transmit7_triggered_~__retres1~7#1 := 0; {1929#false} is VALID [2022-02-21 04:24:23,619 INFO L290 TraceCheckUtils]: 77: Hoare triple {1929#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {1929#false} is VALID [2022-02-21 04:24:23,619 INFO L290 TraceCheckUtils]: 78: Hoare triple {1929#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {1929#false} is VALID [2022-02-21 04:24:23,619 INFO L290 TraceCheckUtils]: 79: Hoare triple {1929#false} assume !(0 != activate_threads_~tmp___6~0#1); {1929#false} is VALID [2022-02-21 04:24:23,619 INFO L290 TraceCheckUtils]: 80: Hoare triple {1929#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {1929#false} is VALID [2022-02-21 04:24:23,620 INFO L290 TraceCheckUtils]: 81: Hoare triple {1929#false} assume 1 == ~t8_pc~0; {1929#false} is VALID [2022-02-21 04:24:23,621 INFO L290 TraceCheckUtils]: 82: Hoare triple {1929#false} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {1929#false} is VALID [2022-02-21 04:24:23,622 INFO L290 TraceCheckUtils]: 83: Hoare triple {1929#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {1929#false} is VALID [2022-02-21 04:24:23,622 INFO L290 TraceCheckUtils]: 84: Hoare triple {1929#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {1929#false} is VALID [2022-02-21 04:24:23,622 INFO L290 TraceCheckUtils]: 85: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,622 INFO L290 TraceCheckUtils]: 86: Hoare triple {1929#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {1929#false} is VALID [2022-02-21 04:24:23,622 INFO L290 TraceCheckUtils]: 87: Hoare triple {1929#false} assume !(1 == ~t9_pc~0); {1929#false} is VALID [2022-02-21 04:24:23,623 INFO L290 TraceCheckUtils]: 88: Hoare triple {1929#false} is_transmit9_triggered_~__retres1~9#1 := 0; {1929#false} is VALID [2022-02-21 04:24:23,625 INFO L290 TraceCheckUtils]: 89: Hoare triple {1929#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {1929#false} is VALID [2022-02-21 04:24:23,626 INFO L290 TraceCheckUtils]: 90: Hoare triple {1929#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {1929#false} is VALID [2022-02-21 04:24:23,626 INFO L290 TraceCheckUtils]: 91: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,626 INFO L290 TraceCheckUtils]: 92: Hoare triple {1929#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {1929#false} is VALID [2022-02-21 04:24:23,626 INFO L290 TraceCheckUtils]: 93: Hoare triple {1929#false} assume 1 == ~t10_pc~0; {1929#false} is VALID [2022-02-21 04:24:23,626 INFO L290 TraceCheckUtils]: 94: Hoare triple {1929#false} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {1929#false} is VALID [2022-02-21 04:24:23,627 INFO L290 TraceCheckUtils]: 95: Hoare triple {1929#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {1929#false} is VALID [2022-02-21 04:24:23,627 INFO L290 TraceCheckUtils]: 96: Hoare triple {1929#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {1929#false} is VALID [2022-02-21 04:24:23,627 INFO L290 TraceCheckUtils]: 97: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,627 INFO L290 TraceCheckUtils]: 98: Hoare triple {1929#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {1929#false} is VALID [2022-02-21 04:24:23,628 INFO L290 TraceCheckUtils]: 99: Hoare triple {1929#false} assume !(1 == ~t11_pc~0); {1929#false} is VALID [2022-02-21 04:24:23,628 INFO L290 TraceCheckUtils]: 100: Hoare triple {1929#false} is_transmit11_triggered_~__retres1~11#1 := 0; {1929#false} is VALID [2022-02-21 04:24:23,631 INFO L290 TraceCheckUtils]: 101: Hoare triple {1929#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {1929#false} is VALID [2022-02-21 04:24:23,631 INFO L290 TraceCheckUtils]: 102: Hoare triple {1929#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {1929#false} is VALID [2022-02-21 04:24:23,631 INFO L290 TraceCheckUtils]: 103: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,632 INFO L290 TraceCheckUtils]: 104: Hoare triple {1929#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {1929#false} is VALID [2022-02-21 04:24:23,632 INFO L290 TraceCheckUtils]: 105: Hoare triple {1929#false} assume 1 == ~t12_pc~0; {1929#false} is VALID [2022-02-21 04:24:23,632 INFO L290 TraceCheckUtils]: 106: Hoare triple {1929#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {1929#false} is VALID [2022-02-21 04:24:23,632 INFO L290 TraceCheckUtils]: 107: Hoare triple {1929#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {1929#false} is VALID [2022-02-21 04:24:23,632 INFO L290 TraceCheckUtils]: 108: Hoare triple {1929#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {1929#false} is VALID [2022-02-21 04:24:23,633 INFO L290 TraceCheckUtils]: 109: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,633 INFO L290 TraceCheckUtils]: 110: Hoare triple {1929#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {1929#false} is VALID [2022-02-21 04:24:23,633 INFO L290 TraceCheckUtils]: 111: Hoare triple {1929#false} assume 1 == ~t13_pc~0; {1929#false} is VALID [2022-02-21 04:24:23,633 INFO L290 TraceCheckUtils]: 112: Hoare triple {1929#false} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {1929#false} is VALID [2022-02-21 04:24:23,633 INFO L290 TraceCheckUtils]: 113: Hoare triple {1929#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {1929#false} is VALID [2022-02-21 04:24:23,634 INFO L290 TraceCheckUtils]: 114: Hoare triple {1929#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {1929#false} is VALID [2022-02-21 04:24:23,634 INFO L290 TraceCheckUtils]: 115: Hoare triple {1929#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {1929#false} is VALID [2022-02-21 04:24:23,634 INFO L290 TraceCheckUtils]: 116: Hoare triple {1929#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1929#false} is VALID [2022-02-21 04:24:23,634 INFO L290 TraceCheckUtils]: 117: Hoare triple {1929#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,635 INFO L290 TraceCheckUtils]: 118: Hoare triple {1929#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,635 INFO L290 TraceCheckUtils]: 119: Hoare triple {1929#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,636 INFO L290 TraceCheckUtils]: 120: Hoare triple {1929#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,636 INFO L290 TraceCheckUtils]: 121: Hoare triple {1929#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,636 INFO L290 TraceCheckUtils]: 122: Hoare triple {1929#false} assume !(1 == ~T5_E~0); {1929#false} is VALID [2022-02-21 04:24:23,637 INFO L290 TraceCheckUtils]: 123: Hoare triple {1929#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,637 INFO L290 TraceCheckUtils]: 124: Hoare triple {1929#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,637 INFO L290 TraceCheckUtils]: 125: Hoare triple {1929#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,637 INFO L290 TraceCheckUtils]: 126: Hoare triple {1929#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,637 INFO L290 TraceCheckUtils]: 127: Hoare triple {1929#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,638 INFO L290 TraceCheckUtils]: 128: Hoare triple {1929#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,638 INFO L290 TraceCheckUtils]: 129: Hoare triple {1929#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,638 INFO L290 TraceCheckUtils]: 130: Hoare triple {1929#false} assume !(1 == ~T13_E~0); {1929#false} is VALID [2022-02-21 04:24:23,638 INFO L290 TraceCheckUtils]: 131: Hoare triple {1929#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,638 INFO L290 TraceCheckUtils]: 132: Hoare triple {1929#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,639 INFO L290 TraceCheckUtils]: 133: Hoare triple {1929#false} assume 1 == ~E_3~0;~E_3~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,639 INFO L290 TraceCheckUtils]: 134: Hoare triple {1929#false} assume 1 == ~E_4~0;~E_4~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,639 INFO L290 TraceCheckUtils]: 135: Hoare triple {1929#false} assume 1 == ~E_5~0;~E_5~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,639 INFO L290 TraceCheckUtils]: 136: Hoare triple {1929#false} assume 1 == ~E_6~0;~E_6~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,640 INFO L290 TraceCheckUtils]: 137: Hoare triple {1929#false} assume 1 == ~E_7~0;~E_7~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,640 INFO L290 TraceCheckUtils]: 138: Hoare triple {1929#false} assume !(1 == ~E_8~0); {1929#false} is VALID [2022-02-21 04:24:23,640 INFO L290 TraceCheckUtils]: 139: Hoare triple {1929#false} assume 1 == ~E_9~0;~E_9~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,640 INFO L290 TraceCheckUtils]: 140: Hoare triple {1929#false} assume 1 == ~E_10~0;~E_10~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,641 INFO L290 TraceCheckUtils]: 141: Hoare triple {1929#false} assume 1 == ~E_11~0;~E_11~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,641 INFO L290 TraceCheckUtils]: 142: Hoare triple {1929#false} assume 1 == ~E_12~0;~E_12~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,641 INFO L290 TraceCheckUtils]: 143: Hoare triple {1929#false} assume 1 == ~E_13~0;~E_13~0 := 2; {1929#false} is VALID [2022-02-21 04:24:23,642 INFO L290 TraceCheckUtils]: 144: Hoare triple {1929#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {1929#false} is VALID [2022-02-21 04:24:23,642 INFO L290 TraceCheckUtils]: 145: Hoare triple {1929#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {1929#false} is VALID [2022-02-21 04:24:23,643 INFO L290 TraceCheckUtils]: 146: Hoare triple {1929#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {1929#false} is VALID [2022-02-21 04:24:23,644 INFO L290 TraceCheckUtils]: 147: Hoare triple {1929#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {1929#false} is VALID [2022-02-21 04:24:23,644 INFO L290 TraceCheckUtils]: 148: Hoare triple {1929#false} assume !(0 == start_simulation_~tmp~3#1); {1929#false} is VALID [2022-02-21 04:24:23,644 INFO L290 TraceCheckUtils]: 149: Hoare triple {1929#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {1929#false} is VALID [2022-02-21 04:24:23,644 INFO L290 TraceCheckUtils]: 150: Hoare triple {1929#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {1929#false} is VALID [2022-02-21 04:24:23,645 INFO L290 TraceCheckUtils]: 151: Hoare triple {1929#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {1929#false} is VALID [2022-02-21 04:24:23,645 INFO L290 TraceCheckUtils]: 152: Hoare triple {1929#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {1929#false} is VALID [2022-02-21 04:24:23,645 INFO L290 TraceCheckUtils]: 153: Hoare triple {1929#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1929#false} is VALID [2022-02-21 04:24:23,645 INFO L290 TraceCheckUtils]: 154: Hoare triple {1929#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1929#false} is VALID [2022-02-21 04:24:23,646 INFO L290 TraceCheckUtils]: 155: Hoare triple {1929#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {1929#false} is VALID [2022-02-21 04:24:23,646 INFO L290 TraceCheckUtils]: 156: Hoare triple {1929#false} assume !(0 != start_simulation_~tmp___0~1#1); {1929#false} is VALID [2022-02-21 04:24:23,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:23,647 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:23,647 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [389722673] [2022-02-21 04:24:23,647 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [389722673] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:23,648 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:23,648 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:23,648 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1637124628] [2022-02-21 04:24:23,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:23,650 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:23,650 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:23,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-02-21 04:24:23,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-02-21 04:24:23,682 INFO L87 Difference]: Start difference. First operand has 1921 states, 1920 states have (on average 1.4984375) internal successors, (2877), 1920 states have internal predecessors, (2877), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:24,806 INFO L93 Difference]: Finished difference Result 1920 states and 2841 transitions. [2022-02-21 04:24:24,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-02-21 04:24:24,808 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 2 states, 2 states have (on average 78.5) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:24,936 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 157 edges. 157 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:24,942 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1920 states and 2841 transitions. [2022-02-21 04:24:25,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:25,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1920 states to 1914 states and 2835 transitions. [2022-02-21 04:24:25,220 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:25,222 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:25,223 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2835 transitions. [2022-02-21 04:24:25,228 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:25,228 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-02-21 04:24:25,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2835 transitions. [2022-02-21 04:24:25,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:25,313 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:25,322 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2835 transitions. Second operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,327 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2835 transitions. Second operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,334 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. Second operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:25,463 INFO L93 Difference]: Finished difference Result 1914 states and 2835 transitions. [2022-02-21 04:24:25,464 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2835 transitions. [2022-02-21 04:24:25,470 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:25,470 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:25,475 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2835 transitions. [2022-02-21 04:24:25,480 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2835 transitions. [2022-02-21 04:24:25,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:25,609 INFO L93 Difference]: Finished difference Result 1914 states and 2835 transitions. [2022-02-21 04:24:25,609 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2835 transitions. [2022-02-21 04:24:25,612 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:25,612 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:25,612 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:25,612 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:25,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4811912225705328) internal successors, (2835), 1913 states have internal predecessors, (2835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:25,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2835 transitions. [2022-02-21 04:24:25,764 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-02-21 04:24:25,764 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2835 transitions. [2022-02-21 04:24:25,764 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:24:25,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2835 transitions. [2022-02-21 04:24:25,774 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:25,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:25,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:25,777 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:25,777 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:25,777 INFO L791 eck$LassoCheckResult]: Stem: 4711#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4531#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4247#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4248#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 5424#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5425#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4383#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4384#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4838#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4673#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4674#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4450#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4451#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4849#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5026#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5180#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5217#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4461#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4462#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 5637#L1258-2 assume !(0 == ~T1_E~0); 4756#L1263-1 assume !(0 == ~T2_E~0); 4757#L1268-1 assume !(0 == ~T3_E~0); 5060#L1273-1 assume !(0 == ~T4_E~0); 5619#L1278-1 assume !(0 == ~T5_E~0); 5480#L1283-1 assume !(0 == ~T6_E~0); 5481#L1288-1 assume !(0 == ~T7_E~0); 5717#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5705#L1298-1 assume !(0 == ~T9_E~0); 5631#L1303-1 assume !(0 == ~T10_E~0); 4276#L1308-1 assume !(0 == ~T11_E~0); 4218#L1313-1 assume !(0 == ~T12_E~0); 4219#L1318-1 assume !(0 == ~T13_E~0); 4225#L1323-1 assume !(0 == ~E_1~0); 4226#L1328-1 assume !(0 == ~E_2~0); 4393#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5352#L1338-1 assume !(0 == ~E_4~0); 5353#L1343-1 assume !(0 == ~E_5~0); 5454#L1348-1 assume !(0 == ~E_6~0); 5740#L1353-1 assume !(0 == ~E_7~0); 5079#L1358-1 assume !(0 == ~E_8~0); 5080#L1363-1 assume !(0 == ~E_9~0); 5370#L1368-1 assume !(0 == ~E_10~0); 4055#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 4056#L1378-1 assume !(0 == ~E_12~0); 4342#L1383-1 assume !(0 == ~E_13~0); 4343#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5086#L607 assume 1 == ~m_pc~0; 5087#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4413#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5452#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5006#L1560 assume !(0 != activate_threads_~tmp~1#1); 5007#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4238#L626 assume !(1 == ~t1_pc~0); 4239#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4507#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4508#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4677#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 4138#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4139#L645 assume 1 == ~t2_pc~0; 4255#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4212#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4889#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4890#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 4982#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4983#L664 assume 1 == ~t3_pc~0; 5739#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3979#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3980#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4638#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 4639#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5647#L683 assume !(1 == ~t4_pc~0); 5202#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5154#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5155#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5189#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5313#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4932#L702 assume 1 == ~t5_pc~0; 4933#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4858#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5308#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5606#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 5547#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4027#L721 assume !(1 == ~t6_pc~0); 4001#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4002#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4165#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4647#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 4648#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5249#L740 assume 1 == ~t7_pc~0; 4076#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3889#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3890#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3879#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 3880#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4583#L759 assume !(1 == ~t8_pc~0); 4584#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4613#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5306#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5307#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 5438#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5716#L778 assume 1 == ~t9_pc~0; 5603#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4054#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3994#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3923#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 3924#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4251#L797 assume !(1 == ~t10_pc~0); 4252#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4370#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5504#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4754#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 4755#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5044#L816 assume 1 == ~t11_pc~0; 3959#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3960#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4715#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4654#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 4655#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5179#L835 assume 1 == ~t12_pc~0; 5057#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4123#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4145#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4286#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 4811#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4812#L854 assume !(1 == ~t13_pc~0); 4452#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4453#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4503#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4163#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4164#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5543#L1401 assume !(1 == ~M_E~0); 4642#L1401-2 assume !(1 == ~T1_E~0); 4643#L1406-1 assume !(1 == ~T2_E~0); 5238#L1411-1 assume !(1 == ~T3_E~0); 5239#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4905#L1421-1 assume !(1 == ~T5_E~0); 4448#L1426-1 assume !(1 == ~T6_E~0); 4449#L1431-1 assume !(1 == ~T7_E~0); 3997#L1436-1 assume !(1 == ~T8_E~0); 3998#L1441-1 assume !(1 == ~T9_E~0); 4745#L1446-1 assume !(1 == ~T10_E~0); 4746#L1451-1 assume !(1 == ~T11_E~0); 5451#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5105#L1461-1 assume !(1 == ~T13_E~0); 4666#L1466-1 assume !(1 == ~E_1~0); 4667#L1471-1 assume !(1 == ~E_2~0); 5436#L1476-1 assume !(1 == ~E_3~0); 5437#L1481-1 assume !(1 == ~E_4~0); 5585#L1486-1 assume !(1 == ~E_5~0); 4291#L1491-1 assume !(1 == ~E_6~0); 3931#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 3932#L1501-1 assume !(1 == ~E_8~0); 4743#L1506-1 assume !(1 == ~E_9~0); 4744#L1511-1 assume !(1 == ~E_10~0); 4700#L1516-1 assume !(1 == ~E_11~0); 3875#L1521-1 assume !(1 == ~E_12~0); 3876#L1526-1 assume !(1 == ~E_13~0); 3930#L1531-1 assume { :end_inline_reset_delta_events } true; 4473#L1892-2 [2022-02-21 04:24:25,778 INFO L793 eck$LassoCheckResult]: Loop: 4473#L1892-2 assume !false; 5496#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5694#L1233 assume !false; 5677#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5009#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4989#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5147#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3973#L1046 assume !(0 != eval_~tmp~0#1); 3975#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4009#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5181#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5738#L1258-5 assume !(0 == ~T1_E~0); 4151#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4152#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5730#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5736#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5737#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4375#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4376#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5493#L1298-3 assume !(0 == ~T9_E~0); 5494#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5653#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5492#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4993#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4153#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4154#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5577#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4296#L1338-3 assume !(0 == ~E_4~0); 4297#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5409#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5582#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5583#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4949#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4509#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4510#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5266#L1378-3 assume !(0 == ~E_12~0); 5267#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5448#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5449#L607-42 assume 1 == ~m_pc~0; 5062#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4790#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4791#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4523#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4524#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5045#L626-42 assume !(1 == ~t1_pc~0); 4609#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 4608#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4912#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4913#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4187#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4188#L645-42 assume !(1 == ~t2_pc~0); 5387#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 5388#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5553#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4394#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3901#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3902#L664-42 assume 1 == ~t3_pc~0; 4704#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4429#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5680#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5215#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5216#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5381#L683-42 assume !(1 == ~t4_pc~0); 5089#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 5090#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5222#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5642#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5643#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5487#L702-42 assume !(1 == ~t5_pc~0); 4599#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 4600#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4896#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5569#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3917#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3918#L721-42 assume 1 == ~t6_pc~0; 4071#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4091#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4555#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5722#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4727#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4573#L740-42 assume !(1 == ~t7_pc~0); 4310#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 4311#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4852#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4707#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 4708#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4981#L759-42 assume 1 == ~t8_pc~0; 4830#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4762#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4763#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4841#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4842#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4937#L778-42 assume 1 == ~t9_pc~0; 4774#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4776#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5186#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5091#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5092#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5149#L797-42 assume 1 == ~t10_pc~0; 4316#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4317#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5318#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5627#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5187#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5188#L816-42 assume 1 == ~t11_pc~0; 3865#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3866#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4408#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4409#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4488#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4489#L835-42 assume !(1 == ~t12_pc~0); 4785#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 4786#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4463#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4464#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5546#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5330#L854-42 assume 1 == ~t13_pc~0; 5331#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4407#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4017#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4018#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4664#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4665#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5443#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4254#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4118#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4119#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4718#L1421-3 assume !(1 == ~T5_E~0); 4719#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4294#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4295#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3881#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3882#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5471#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4802#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4455#L1461-3 assume !(1 == ~T13_E~0); 4456#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5733#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4395#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4396#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4796#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4423#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4424#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4836#L1501-3 assume !(1 == ~E_8~0); 4837#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5263#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5253#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5254#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4953#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4954#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5348#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4230#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5123#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4764#L1911 assume !(0 == start_simulation_~tmp~3#1); 4765#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5287#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4354#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5225#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4059#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4060#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4289#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4290#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4473#L1892-2 [2022-02-21 04:24:25,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:25,779 INFO L85 PathProgramCache]: Analyzing trace with hash 517365666, now seen corresponding path program 2 times [2022-02-21 04:24:25,779 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:25,780 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1190925372] [2022-02-21 04:24:25,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:25,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:25,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:25,836 INFO L290 TraceCheckUtils]: 0: Hoare triple {9595#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {9595#true} is VALID [2022-02-21 04:24:25,837 INFO L290 TraceCheckUtils]: 1: Hoare triple {9595#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {9597#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:25,837 INFO L290 TraceCheckUtils]: 2: Hoare triple {9597#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {9597#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:25,837 INFO L290 TraceCheckUtils]: 3: Hoare triple {9597#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {9597#(= ~m_i~0 1)} is VALID [2022-02-21 04:24:25,838 INFO L290 TraceCheckUtils]: 4: Hoare triple {9597#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,838 INFO L290 TraceCheckUtils]: 5: Hoare triple {9596#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {9596#false} is VALID [2022-02-21 04:24:25,838 INFO L290 TraceCheckUtils]: 6: Hoare triple {9596#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,838 INFO L290 TraceCheckUtils]: 7: Hoare triple {9596#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,839 INFO L290 TraceCheckUtils]: 8: Hoare triple {9596#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,839 INFO L290 TraceCheckUtils]: 9: Hoare triple {9596#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,839 INFO L290 TraceCheckUtils]: 10: Hoare triple {9596#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,839 INFO L290 TraceCheckUtils]: 11: Hoare triple {9596#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,839 INFO L290 TraceCheckUtils]: 12: Hoare triple {9596#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,839 INFO L290 TraceCheckUtils]: 13: Hoare triple {9596#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {9596#false} is VALID [2022-02-21 04:24:25,840 INFO L290 TraceCheckUtils]: 14: Hoare triple {9596#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,840 INFO L290 TraceCheckUtils]: 15: Hoare triple {9596#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,840 INFO L290 TraceCheckUtils]: 16: Hoare triple {9596#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,840 INFO L290 TraceCheckUtils]: 17: Hoare triple {9596#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,840 INFO L290 TraceCheckUtils]: 18: Hoare triple {9596#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {9596#false} is VALID [2022-02-21 04:24:25,840 INFO L290 TraceCheckUtils]: 19: Hoare triple {9596#false} assume 0 == ~M_E~0;~M_E~0 := 1; {9596#false} is VALID [2022-02-21 04:24:25,841 INFO L290 TraceCheckUtils]: 20: Hoare triple {9596#false} assume !(0 == ~T1_E~0); {9596#false} is VALID [2022-02-21 04:24:25,841 INFO L290 TraceCheckUtils]: 21: Hoare triple {9596#false} assume !(0 == ~T2_E~0); {9596#false} is VALID [2022-02-21 04:24:25,841 INFO L290 TraceCheckUtils]: 22: Hoare triple {9596#false} assume !(0 == ~T3_E~0); {9596#false} is VALID [2022-02-21 04:24:25,841 INFO L290 TraceCheckUtils]: 23: Hoare triple {9596#false} assume !(0 == ~T4_E~0); {9596#false} is VALID [2022-02-21 04:24:25,841 INFO L290 TraceCheckUtils]: 24: Hoare triple {9596#false} assume !(0 == ~T5_E~0); {9596#false} is VALID [2022-02-21 04:24:25,841 INFO L290 TraceCheckUtils]: 25: Hoare triple {9596#false} assume !(0 == ~T6_E~0); {9596#false} is VALID [2022-02-21 04:24:25,842 INFO L290 TraceCheckUtils]: 26: Hoare triple {9596#false} assume !(0 == ~T7_E~0); {9596#false} is VALID [2022-02-21 04:24:25,842 INFO L290 TraceCheckUtils]: 27: Hoare triple {9596#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {9596#false} is VALID [2022-02-21 04:24:25,842 INFO L290 TraceCheckUtils]: 28: Hoare triple {9596#false} assume !(0 == ~T9_E~0); {9596#false} is VALID [2022-02-21 04:24:25,842 INFO L290 TraceCheckUtils]: 29: Hoare triple {9596#false} assume !(0 == ~T10_E~0); {9596#false} is VALID [2022-02-21 04:24:25,842 INFO L290 TraceCheckUtils]: 30: Hoare triple {9596#false} assume !(0 == ~T11_E~0); {9596#false} is VALID [2022-02-21 04:24:25,842 INFO L290 TraceCheckUtils]: 31: Hoare triple {9596#false} assume !(0 == ~T12_E~0); {9596#false} is VALID [2022-02-21 04:24:25,843 INFO L290 TraceCheckUtils]: 32: Hoare triple {9596#false} assume !(0 == ~T13_E~0); {9596#false} is VALID [2022-02-21 04:24:25,843 INFO L290 TraceCheckUtils]: 33: Hoare triple {9596#false} assume !(0 == ~E_1~0); {9596#false} is VALID [2022-02-21 04:24:25,843 INFO L290 TraceCheckUtils]: 34: Hoare triple {9596#false} assume !(0 == ~E_2~0); {9596#false} is VALID [2022-02-21 04:24:25,843 INFO L290 TraceCheckUtils]: 35: Hoare triple {9596#false} assume 0 == ~E_3~0;~E_3~0 := 1; {9596#false} is VALID [2022-02-21 04:24:25,843 INFO L290 TraceCheckUtils]: 36: Hoare triple {9596#false} assume !(0 == ~E_4~0); {9596#false} is VALID [2022-02-21 04:24:25,844 INFO L290 TraceCheckUtils]: 37: Hoare triple {9596#false} assume !(0 == ~E_5~0); {9596#false} is VALID [2022-02-21 04:24:25,844 INFO L290 TraceCheckUtils]: 38: Hoare triple {9596#false} assume !(0 == ~E_6~0); {9596#false} is VALID [2022-02-21 04:24:25,844 INFO L290 TraceCheckUtils]: 39: Hoare triple {9596#false} assume !(0 == ~E_7~0); {9596#false} is VALID [2022-02-21 04:24:25,844 INFO L290 TraceCheckUtils]: 40: Hoare triple {9596#false} assume !(0 == ~E_8~0); {9596#false} is VALID [2022-02-21 04:24:25,844 INFO L290 TraceCheckUtils]: 41: Hoare triple {9596#false} assume !(0 == ~E_9~0); {9596#false} is VALID [2022-02-21 04:24:25,844 INFO L290 TraceCheckUtils]: 42: Hoare triple {9596#false} assume !(0 == ~E_10~0); {9596#false} is VALID [2022-02-21 04:24:25,845 INFO L290 TraceCheckUtils]: 43: Hoare triple {9596#false} assume 0 == ~E_11~0;~E_11~0 := 1; {9596#false} is VALID [2022-02-21 04:24:25,845 INFO L290 TraceCheckUtils]: 44: Hoare triple {9596#false} assume !(0 == ~E_12~0); {9596#false} is VALID [2022-02-21 04:24:25,845 INFO L290 TraceCheckUtils]: 45: Hoare triple {9596#false} assume !(0 == ~E_13~0); {9596#false} is VALID [2022-02-21 04:24:25,845 INFO L290 TraceCheckUtils]: 46: Hoare triple {9596#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {9596#false} is VALID [2022-02-21 04:24:25,845 INFO L290 TraceCheckUtils]: 47: Hoare triple {9596#false} assume 1 == ~m_pc~0; {9596#false} is VALID [2022-02-21 04:24:25,845 INFO L290 TraceCheckUtils]: 48: Hoare triple {9596#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {9596#false} is VALID [2022-02-21 04:24:25,846 INFO L290 TraceCheckUtils]: 49: Hoare triple {9596#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {9596#false} is VALID [2022-02-21 04:24:25,846 INFO L290 TraceCheckUtils]: 50: Hoare triple {9596#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {9596#false} is VALID [2022-02-21 04:24:25,846 INFO L290 TraceCheckUtils]: 51: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp~1#1); {9596#false} is VALID [2022-02-21 04:24:25,846 INFO L290 TraceCheckUtils]: 52: Hoare triple {9596#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {9596#false} is VALID [2022-02-21 04:24:25,846 INFO L290 TraceCheckUtils]: 53: Hoare triple {9596#false} assume !(1 == ~t1_pc~0); {9596#false} is VALID [2022-02-21 04:24:25,846 INFO L290 TraceCheckUtils]: 54: Hoare triple {9596#false} is_transmit1_triggered_~__retres1~1#1 := 0; {9596#false} is VALID [2022-02-21 04:24:25,847 INFO L290 TraceCheckUtils]: 55: Hoare triple {9596#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {9596#false} is VALID [2022-02-21 04:24:25,847 INFO L290 TraceCheckUtils]: 56: Hoare triple {9596#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {9596#false} is VALID [2022-02-21 04:24:25,847 INFO L290 TraceCheckUtils]: 57: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp___0~0#1); {9596#false} is VALID [2022-02-21 04:24:25,847 INFO L290 TraceCheckUtils]: 58: Hoare triple {9596#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {9596#false} is VALID [2022-02-21 04:24:25,847 INFO L290 TraceCheckUtils]: 59: Hoare triple {9596#false} assume 1 == ~t2_pc~0; {9596#false} is VALID [2022-02-21 04:24:25,848 INFO L290 TraceCheckUtils]: 60: Hoare triple {9596#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {9596#false} is VALID [2022-02-21 04:24:25,848 INFO L290 TraceCheckUtils]: 61: Hoare triple {9596#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {9596#false} is VALID [2022-02-21 04:24:25,848 INFO L290 TraceCheckUtils]: 62: Hoare triple {9596#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {9596#false} is VALID [2022-02-21 04:24:25,848 INFO L290 TraceCheckUtils]: 63: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp___1~0#1); {9596#false} is VALID [2022-02-21 04:24:25,848 INFO L290 TraceCheckUtils]: 64: Hoare triple {9596#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {9596#false} is VALID [2022-02-21 04:24:25,848 INFO L290 TraceCheckUtils]: 65: Hoare triple {9596#false} assume 1 == ~t3_pc~0; {9596#false} is VALID [2022-02-21 04:24:25,849 INFO L290 TraceCheckUtils]: 66: Hoare triple {9596#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {9596#false} is VALID [2022-02-21 04:24:25,849 INFO L290 TraceCheckUtils]: 67: Hoare triple {9596#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {9596#false} is VALID [2022-02-21 04:24:25,849 INFO L290 TraceCheckUtils]: 68: Hoare triple {9596#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {9596#false} is VALID [2022-02-21 04:24:25,849 INFO L290 TraceCheckUtils]: 69: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp___2~0#1); {9596#false} is VALID [2022-02-21 04:24:25,849 INFO L290 TraceCheckUtils]: 70: Hoare triple {9596#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {9596#false} is VALID [2022-02-21 04:24:25,849 INFO L290 TraceCheckUtils]: 71: Hoare triple {9596#false} assume !(1 == ~t4_pc~0); {9596#false} is VALID [2022-02-21 04:24:25,850 INFO L290 TraceCheckUtils]: 72: Hoare triple {9596#false} is_transmit4_triggered_~__retres1~4#1 := 0; {9596#false} is VALID [2022-02-21 04:24:25,850 INFO L290 TraceCheckUtils]: 73: Hoare triple {9596#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {9596#false} is VALID [2022-02-21 04:24:25,850 INFO L290 TraceCheckUtils]: 74: Hoare triple {9596#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {9596#false} is VALID [2022-02-21 04:24:25,850 INFO L290 TraceCheckUtils]: 75: Hoare triple {9596#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {9596#false} is VALID [2022-02-21 04:24:25,850 INFO L290 TraceCheckUtils]: 76: Hoare triple {9596#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {9596#false} is VALID [2022-02-21 04:24:25,850 INFO L290 TraceCheckUtils]: 77: Hoare triple {9596#false} assume 1 == ~t5_pc~0; {9596#false} is VALID [2022-02-21 04:24:25,851 INFO L290 TraceCheckUtils]: 78: Hoare triple {9596#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {9596#false} is VALID [2022-02-21 04:24:25,851 INFO L290 TraceCheckUtils]: 79: Hoare triple {9596#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {9596#false} is VALID [2022-02-21 04:24:25,851 INFO L290 TraceCheckUtils]: 80: Hoare triple {9596#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {9596#false} is VALID [2022-02-21 04:24:25,851 INFO L290 TraceCheckUtils]: 81: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp___4~0#1); {9596#false} is VALID [2022-02-21 04:24:25,851 INFO L290 TraceCheckUtils]: 82: Hoare triple {9596#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {9596#false} is VALID [2022-02-21 04:24:25,851 INFO L290 TraceCheckUtils]: 83: Hoare triple {9596#false} assume !(1 == ~t6_pc~0); {9596#false} is VALID [2022-02-21 04:24:25,852 INFO L290 TraceCheckUtils]: 84: Hoare triple {9596#false} is_transmit6_triggered_~__retres1~6#1 := 0; {9596#false} is VALID [2022-02-21 04:24:25,852 INFO L290 TraceCheckUtils]: 85: Hoare triple {9596#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {9596#false} is VALID [2022-02-21 04:24:25,852 INFO L290 TraceCheckUtils]: 86: Hoare triple {9596#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {9596#false} is VALID [2022-02-21 04:24:25,852 INFO L290 TraceCheckUtils]: 87: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp___5~0#1); {9596#false} is VALID [2022-02-21 04:24:25,852 INFO L290 TraceCheckUtils]: 88: Hoare triple {9596#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {9596#false} is VALID [2022-02-21 04:24:25,853 INFO L290 TraceCheckUtils]: 89: Hoare triple {9596#false} assume 1 == ~t7_pc~0; {9596#false} is VALID [2022-02-21 04:24:25,853 INFO L290 TraceCheckUtils]: 90: Hoare triple {9596#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {9596#false} is VALID [2022-02-21 04:24:25,853 INFO L290 TraceCheckUtils]: 91: Hoare triple {9596#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {9596#false} is VALID [2022-02-21 04:24:25,853 INFO L290 TraceCheckUtils]: 92: Hoare triple {9596#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {9596#false} is VALID [2022-02-21 04:24:25,853 INFO L290 TraceCheckUtils]: 93: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp___6~0#1); {9596#false} is VALID [2022-02-21 04:24:25,853 INFO L290 TraceCheckUtils]: 94: Hoare triple {9596#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {9596#false} is VALID [2022-02-21 04:24:25,854 INFO L290 TraceCheckUtils]: 95: Hoare triple {9596#false} assume !(1 == ~t8_pc~0); {9596#false} is VALID [2022-02-21 04:24:25,854 INFO L290 TraceCheckUtils]: 96: Hoare triple {9596#false} is_transmit8_triggered_~__retres1~8#1 := 0; {9596#false} is VALID [2022-02-21 04:24:25,854 INFO L290 TraceCheckUtils]: 97: Hoare triple {9596#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {9596#false} is VALID [2022-02-21 04:24:25,854 INFO L290 TraceCheckUtils]: 98: Hoare triple {9596#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {9596#false} is VALID [2022-02-21 04:24:25,854 INFO L290 TraceCheckUtils]: 99: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp___7~0#1); {9596#false} is VALID [2022-02-21 04:24:25,854 INFO L290 TraceCheckUtils]: 100: Hoare triple {9596#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {9596#false} is VALID [2022-02-21 04:24:25,855 INFO L290 TraceCheckUtils]: 101: Hoare triple {9596#false} assume 1 == ~t9_pc~0; {9596#false} is VALID [2022-02-21 04:24:25,855 INFO L290 TraceCheckUtils]: 102: Hoare triple {9596#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {9596#false} is VALID [2022-02-21 04:24:25,855 INFO L290 TraceCheckUtils]: 103: Hoare triple {9596#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {9596#false} is VALID [2022-02-21 04:24:25,855 INFO L290 TraceCheckUtils]: 104: Hoare triple {9596#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {9596#false} is VALID [2022-02-21 04:24:25,855 INFO L290 TraceCheckUtils]: 105: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp___8~0#1); {9596#false} is VALID [2022-02-21 04:24:25,855 INFO L290 TraceCheckUtils]: 106: Hoare triple {9596#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {9596#false} is VALID [2022-02-21 04:24:25,856 INFO L290 TraceCheckUtils]: 107: Hoare triple {9596#false} assume !(1 == ~t10_pc~0); {9596#false} is VALID [2022-02-21 04:24:25,856 INFO L290 TraceCheckUtils]: 108: Hoare triple {9596#false} is_transmit10_triggered_~__retres1~10#1 := 0; {9596#false} is VALID [2022-02-21 04:24:25,856 INFO L290 TraceCheckUtils]: 109: Hoare triple {9596#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {9596#false} is VALID [2022-02-21 04:24:25,856 INFO L290 TraceCheckUtils]: 110: Hoare triple {9596#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {9596#false} is VALID [2022-02-21 04:24:25,856 INFO L290 TraceCheckUtils]: 111: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp___9~0#1); {9596#false} is VALID [2022-02-21 04:24:25,857 INFO L290 TraceCheckUtils]: 112: Hoare triple {9596#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {9596#false} is VALID [2022-02-21 04:24:25,857 INFO L290 TraceCheckUtils]: 113: Hoare triple {9596#false} assume 1 == ~t11_pc~0; {9596#false} is VALID [2022-02-21 04:24:25,857 INFO L290 TraceCheckUtils]: 114: Hoare triple {9596#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {9596#false} is VALID [2022-02-21 04:24:25,857 INFO L290 TraceCheckUtils]: 115: Hoare triple {9596#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {9596#false} is VALID [2022-02-21 04:24:25,857 INFO L290 TraceCheckUtils]: 116: Hoare triple {9596#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {9596#false} is VALID [2022-02-21 04:24:25,857 INFO L290 TraceCheckUtils]: 117: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp___10~0#1); {9596#false} is VALID [2022-02-21 04:24:25,857 INFO L290 TraceCheckUtils]: 118: Hoare triple {9596#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {9596#false} is VALID [2022-02-21 04:24:25,858 INFO L290 TraceCheckUtils]: 119: Hoare triple {9596#false} assume 1 == ~t12_pc~0; {9596#false} is VALID [2022-02-21 04:24:25,858 INFO L290 TraceCheckUtils]: 120: Hoare triple {9596#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {9596#false} is VALID [2022-02-21 04:24:25,858 INFO L290 TraceCheckUtils]: 121: Hoare triple {9596#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {9596#false} is VALID [2022-02-21 04:24:25,858 INFO L290 TraceCheckUtils]: 122: Hoare triple {9596#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {9596#false} is VALID [2022-02-21 04:24:25,858 INFO L290 TraceCheckUtils]: 123: Hoare triple {9596#false} assume !(0 != activate_threads_~tmp___11~0#1); {9596#false} is VALID [2022-02-21 04:24:25,858 INFO L290 TraceCheckUtils]: 124: Hoare triple {9596#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {9596#false} is VALID [2022-02-21 04:24:25,859 INFO L290 TraceCheckUtils]: 125: Hoare triple {9596#false} assume !(1 == ~t13_pc~0); {9596#false} is VALID [2022-02-21 04:24:25,859 INFO L290 TraceCheckUtils]: 126: Hoare triple {9596#false} is_transmit13_triggered_~__retres1~13#1 := 0; {9596#false} is VALID [2022-02-21 04:24:25,859 INFO L290 TraceCheckUtils]: 127: Hoare triple {9596#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {9596#false} is VALID [2022-02-21 04:24:25,859 INFO L290 TraceCheckUtils]: 128: Hoare triple {9596#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {9596#false} is VALID [2022-02-21 04:24:25,859 INFO L290 TraceCheckUtils]: 129: Hoare triple {9596#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {9596#false} is VALID [2022-02-21 04:24:25,859 INFO L290 TraceCheckUtils]: 130: Hoare triple {9596#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {9596#false} is VALID [2022-02-21 04:24:25,860 INFO L290 TraceCheckUtils]: 131: Hoare triple {9596#false} assume !(1 == ~M_E~0); {9596#false} is VALID [2022-02-21 04:24:25,860 INFO L290 TraceCheckUtils]: 132: Hoare triple {9596#false} assume !(1 == ~T1_E~0); {9596#false} is VALID [2022-02-21 04:24:25,860 INFO L290 TraceCheckUtils]: 133: Hoare triple {9596#false} assume !(1 == ~T2_E~0); {9596#false} is VALID [2022-02-21 04:24:25,860 INFO L290 TraceCheckUtils]: 134: Hoare triple {9596#false} assume !(1 == ~T3_E~0); {9596#false} is VALID [2022-02-21 04:24:25,860 INFO L290 TraceCheckUtils]: 135: Hoare triple {9596#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,860 INFO L290 TraceCheckUtils]: 136: Hoare triple {9596#false} assume !(1 == ~T5_E~0); {9596#false} is VALID [2022-02-21 04:24:25,861 INFO L290 TraceCheckUtils]: 137: Hoare triple {9596#false} assume !(1 == ~T6_E~0); {9596#false} is VALID [2022-02-21 04:24:25,861 INFO L290 TraceCheckUtils]: 138: Hoare triple {9596#false} assume !(1 == ~T7_E~0); {9596#false} is VALID [2022-02-21 04:24:25,861 INFO L290 TraceCheckUtils]: 139: Hoare triple {9596#false} assume !(1 == ~T8_E~0); {9596#false} is VALID [2022-02-21 04:24:25,861 INFO L290 TraceCheckUtils]: 140: Hoare triple {9596#false} assume !(1 == ~T9_E~0); {9596#false} is VALID [2022-02-21 04:24:25,861 INFO L290 TraceCheckUtils]: 141: Hoare triple {9596#false} assume !(1 == ~T10_E~0); {9596#false} is VALID [2022-02-21 04:24:25,861 INFO L290 TraceCheckUtils]: 142: Hoare triple {9596#false} assume !(1 == ~T11_E~0); {9596#false} is VALID [2022-02-21 04:24:25,862 INFO L290 TraceCheckUtils]: 143: Hoare triple {9596#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,862 INFO L290 TraceCheckUtils]: 144: Hoare triple {9596#false} assume !(1 == ~T13_E~0); {9596#false} is VALID [2022-02-21 04:24:25,862 INFO L290 TraceCheckUtils]: 145: Hoare triple {9596#false} assume !(1 == ~E_1~0); {9596#false} is VALID [2022-02-21 04:24:25,862 INFO L290 TraceCheckUtils]: 146: Hoare triple {9596#false} assume !(1 == ~E_2~0); {9596#false} is VALID [2022-02-21 04:24:25,862 INFO L290 TraceCheckUtils]: 147: Hoare triple {9596#false} assume !(1 == ~E_3~0); {9596#false} is VALID [2022-02-21 04:24:25,862 INFO L290 TraceCheckUtils]: 148: Hoare triple {9596#false} assume !(1 == ~E_4~0); {9596#false} is VALID [2022-02-21 04:24:25,863 INFO L290 TraceCheckUtils]: 149: Hoare triple {9596#false} assume !(1 == ~E_5~0); {9596#false} is VALID [2022-02-21 04:24:25,863 INFO L290 TraceCheckUtils]: 150: Hoare triple {9596#false} assume !(1 == ~E_6~0); {9596#false} is VALID [2022-02-21 04:24:25,863 INFO L290 TraceCheckUtils]: 151: Hoare triple {9596#false} assume 1 == ~E_7~0;~E_7~0 := 2; {9596#false} is VALID [2022-02-21 04:24:25,863 INFO L290 TraceCheckUtils]: 152: Hoare triple {9596#false} assume !(1 == ~E_8~0); {9596#false} is VALID [2022-02-21 04:24:25,863 INFO L290 TraceCheckUtils]: 153: Hoare triple {9596#false} assume !(1 == ~E_9~0); {9596#false} is VALID [2022-02-21 04:24:25,863 INFO L290 TraceCheckUtils]: 154: Hoare triple {9596#false} assume !(1 == ~E_10~0); {9596#false} is VALID [2022-02-21 04:24:25,864 INFO L290 TraceCheckUtils]: 155: Hoare triple {9596#false} assume !(1 == ~E_11~0); {9596#false} is VALID [2022-02-21 04:24:25,864 INFO L290 TraceCheckUtils]: 156: Hoare triple {9596#false} assume !(1 == ~E_12~0); {9596#false} is VALID [2022-02-21 04:24:25,864 INFO L290 TraceCheckUtils]: 157: Hoare triple {9596#false} assume !(1 == ~E_13~0); {9596#false} is VALID [2022-02-21 04:24:25,864 INFO L290 TraceCheckUtils]: 158: Hoare triple {9596#false} assume { :end_inline_reset_delta_events } true; {9596#false} is VALID [2022-02-21 04:24:25,865 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:25,865 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:25,865 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1190925372] [2022-02-21 04:24:25,866 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1190925372] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:25,866 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:25,866 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:25,866 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2027873207] [2022-02-21 04:24:25,866 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:25,867 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:25,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:25,867 INFO L85 PathProgramCache]: Analyzing trace with hash -423565315, now seen corresponding path program 1 times [2022-02-21 04:24:25,868 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:25,868 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346275282] [2022-02-21 04:24:25,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:25,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:25,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:26,038 INFO L290 TraceCheckUtils]: 0: Hoare triple {9598#true} assume !false; {9598#true} is VALID [2022-02-21 04:24:26,039 INFO L290 TraceCheckUtils]: 1: Hoare triple {9598#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {9598#true} is VALID [2022-02-21 04:24:26,039 INFO L290 TraceCheckUtils]: 2: Hoare triple {9598#true} assume !false; {9598#true} is VALID [2022-02-21 04:24:26,039 INFO L290 TraceCheckUtils]: 3: Hoare triple {9598#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {9598#true} is VALID [2022-02-21 04:24:26,039 INFO L290 TraceCheckUtils]: 4: Hoare triple {9598#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {9598#true} is VALID [2022-02-21 04:24:26,039 INFO L290 TraceCheckUtils]: 5: Hoare triple {9598#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {9598#true} is VALID [2022-02-21 04:24:26,040 INFO L290 TraceCheckUtils]: 6: Hoare triple {9598#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {9598#true} is VALID [2022-02-21 04:24:26,040 INFO L290 TraceCheckUtils]: 7: Hoare triple {9598#true} assume !(0 != eval_~tmp~0#1); {9598#true} is VALID [2022-02-21 04:24:26,040 INFO L290 TraceCheckUtils]: 8: Hoare triple {9598#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {9598#true} is VALID [2022-02-21 04:24:26,040 INFO L290 TraceCheckUtils]: 9: Hoare triple {9598#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {9598#true} is VALID [2022-02-21 04:24:26,040 INFO L290 TraceCheckUtils]: 10: Hoare triple {9598#true} assume 0 == ~M_E~0;~M_E~0 := 1; {9598#true} is VALID [2022-02-21 04:24:26,040 INFO L290 TraceCheckUtils]: 11: Hoare triple {9598#true} assume !(0 == ~T1_E~0); {9598#true} is VALID [2022-02-21 04:24:26,041 INFO L290 TraceCheckUtils]: 12: Hoare triple {9598#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {9598#true} is VALID [2022-02-21 04:24:26,042 INFO L290 TraceCheckUtils]: 13: Hoare triple {9598#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {9598#true} is VALID [2022-02-21 04:24:26,042 INFO L290 TraceCheckUtils]: 14: Hoare triple {9598#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {9598#true} is VALID [2022-02-21 04:24:26,043 INFO L290 TraceCheckUtils]: 15: Hoare triple {9598#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,043 INFO L290 TraceCheckUtils]: 16: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,044 INFO L290 TraceCheckUtils]: 17: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,044 INFO L290 TraceCheckUtils]: 18: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,045 INFO L290 TraceCheckUtils]: 19: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,045 INFO L290 TraceCheckUtils]: 20: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,045 INFO L290 TraceCheckUtils]: 21: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,046 INFO L290 TraceCheckUtils]: 22: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,047 INFO L290 TraceCheckUtils]: 23: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,047 INFO L290 TraceCheckUtils]: 24: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,052 INFO L290 TraceCheckUtils]: 25: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,054 INFO L290 TraceCheckUtils]: 26: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,054 INFO L290 TraceCheckUtils]: 27: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,055 INFO L290 TraceCheckUtils]: 28: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,056 INFO L290 TraceCheckUtils]: 29: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,057 INFO L290 TraceCheckUtils]: 30: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,057 INFO L290 TraceCheckUtils]: 31: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,059 INFO L290 TraceCheckUtils]: 32: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,059 INFO L290 TraceCheckUtils]: 33: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,059 INFO L290 TraceCheckUtils]: 34: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,060 INFO L290 TraceCheckUtils]: 35: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,063 INFO L290 TraceCheckUtils]: 36: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,064 INFO L290 TraceCheckUtils]: 37: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,064 INFO L290 TraceCheckUtils]: 38: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,065 INFO L290 TraceCheckUtils]: 39: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,065 INFO L290 TraceCheckUtils]: 40: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,065 INFO L290 TraceCheckUtils]: 41: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,066 INFO L290 TraceCheckUtils]: 42: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,066 INFO L290 TraceCheckUtils]: 43: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,067 INFO L290 TraceCheckUtils]: 44: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,067 INFO L290 TraceCheckUtils]: 45: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,068 INFO L290 TraceCheckUtils]: 46: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,068 INFO L290 TraceCheckUtils]: 47: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,068 INFO L290 TraceCheckUtils]: 48: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,069 INFO L290 TraceCheckUtils]: 49: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,069 INFO L290 TraceCheckUtils]: 50: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,070 INFO L290 TraceCheckUtils]: 51: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,072 INFO L290 TraceCheckUtils]: 52: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,072 INFO L290 TraceCheckUtils]: 53: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,073 INFO L290 TraceCheckUtils]: 54: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,073 INFO L290 TraceCheckUtils]: 55: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,073 INFO L290 TraceCheckUtils]: 56: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,074 INFO L290 TraceCheckUtils]: 57: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,074 INFO L290 TraceCheckUtils]: 58: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,075 INFO L290 TraceCheckUtils]: 59: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,077 INFO L290 TraceCheckUtils]: 60: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,078 INFO L290 TraceCheckUtils]: 61: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,078 INFO L290 TraceCheckUtils]: 62: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,079 INFO L290 TraceCheckUtils]: 63: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,079 INFO L290 TraceCheckUtils]: 64: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,079 INFO L290 TraceCheckUtils]: 65: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,080 INFO L290 TraceCheckUtils]: 66: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,080 INFO L290 TraceCheckUtils]: 67: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,081 INFO L290 TraceCheckUtils]: 68: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,081 INFO L290 TraceCheckUtils]: 69: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,081 INFO L290 TraceCheckUtils]: 70: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,082 INFO L290 TraceCheckUtils]: 71: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,082 INFO L290 TraceCheckUtils]: 72: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,083 INFO L290 TraceCheckUtils]: 73: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,083 INFO L290 TraceCheckUtils]: 74: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,083 INFO L290 TraceCheckUtils]: 75: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,084 INFO L290 TraceCheckUtils]: 76: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,084 INFO L290 TraceCheckUtils]: 77: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,085 INFO L290 TraceCheckUtils]: 78: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,085 INFO L290 TraceCheckUtils]: 79: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,086 INFO L290 TraceCheckUtils]: 80: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t7_pc~0); {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,086 INFO L290 TraceCheckUtils]: 81: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,086 INFO L290 TraceCheckUtils]: 82: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,087 INFO L290 TraceCheckUtils]: 83: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,087 INFO L290 TraceCheckUtils]: 84: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,088 INFO L290 TraceCheckUtils]: 85: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,088 INFO L290 TraceCheckUtils]: 86: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,088 INFO L290 TraceCheckUtils]: 87: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,089 INFO L290 TraceCheckUtils]: 88: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,089 INFO L290 TraceCheckUtils]: 89: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,090 INFO L290 TraceCheckUtils]: 90: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,090 INFO L290 TraceCheckUtils]: 91: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,090 INFO L290 TraceCheckUtils]: 92: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,091 INFO L290 TraceCheckUtils]: 93: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,091 INFO L290 TraceCheckUtils]: 94: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,092 INFO L290 TraceCheckUtils]: 95: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,092 INFO L290 TraceCheckUtils]: 96: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,092 INFO L290 TraceCheckUtils]: 97: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,093 INFO L290 TraceCheckUtils]: 98: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,093 INFO L290 TraceCheckUtils]: 99: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,094 INFO L290 TraceCheckUtils]: 100: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,094 INFO L290 TraceCheckUtils]: 101: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,094 INFO L290 TraceCheckUtils]: 102: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,095 INFO L290 TraceCheckUtils]: 103: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,095 INFO L290 TraceCheckUtils]: 104: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,096 INFO L290 TraceCheckUtils]: 105: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,096 INFO L290 TraceCheckUtils]: 106: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,096 INFO L290 TraceCheckUtils]: 107: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,097 INFO L290 TraceCheckUtils]: 108: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,097 INFO L290 TraceCheckUtils]: 109: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,098 INFO L290 TraceCheckUtils]: 110: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t12_pc~0); {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,098 INFO L290 TraceCheckUtils]: 111: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,098 INFO L290 TraceCheckUtils]: 112: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,099 INFO L290 TraceCheckUtils]: 113: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,099 INFO L290 TraceCheckUtils]: 114: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,100 INFO L290 TraceCheckUtils]: 115: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,100 INFO L290 TraceCheckUtils]: 116: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,100 INFO L290 TraceCheckUtils]: 117: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,101 INFO L290 TraceCheckUtils]: 118: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,101 INFO L290 TraceCheckUtils]: 119: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,102 INFO L290 TraceCheckUtils]: 120: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,102 INFO L290 TraceCheckUtils]: 121: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,103 INFO L290 TraceCheckUtils]: 122: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,103 INFO L290 TraceCheckUtils]: 123: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,103 INFO L290 TraceCheckUtils]: 124: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,104 INFO L290 TraceCheckUtils]: 125: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,104 INFO L290 TraceCheckUtils]: 126: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {9600#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:26,105 INFO L290 TraceCheckUtils]: 127: Hoare triple {9600#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {9599#false} is VALID [2022-02-21 04:24:26,105 INFO L290 TraceCheckUtils]: 128: Hoare triple {9599#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,106 INFO L290 TraceCheckUtils]: 129: Hoare triple {9599#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,106 INFO L290 TraceCheckUtils]: 130: Hoare triple {9599#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,106 INFO L290 TraceCheckUtils]: 131: Hoare triple {9599#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,106 INFO L290 TraceCheckUtils]: 132: Hoare triple {9599#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,106 INFO L290 TraceCheckUtils]: 133: Hoare triple {9599#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,106 INFO L290 TraceCheckUtils]: 134: Hoare triple {9599#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,106 INFO L290 TraceCheckUtils]: 135: Hoare triple {9599#false} assume !(1 == ~T13_E~0); {9599#false} is VALID [2022-02-21 04:24:26,107 INFO L290 TraceCheckUtils]: 136: Hoare triple {9599#false} assume 1 == ~E_1~0;~E_1~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,107 INFO L290 TraceCheckUtils]: 137: Hoare triple {9599#false} assume 1 == ~E_2~0;~E_2~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,107 INFO L290 TraceCheckUtils]: 138: Hoare triple {9599#false} assume 1 == ~E_3~0;~E_3~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,107 INFO L290 TraceCheckUtils]: 139: Hoare triple {9599#false} assume 1 == ~E_4~0;~E_4~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,107 INFO L290 TraceCheckUtils]: 140: Hoare triple {9599#false} assume 1 == ~E_5~0;~E_5~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,107 INFO L290 TraceCheckUtils]: 141: Hoare triple {9599#false} assume 1 == ~E_6~0;~E_6~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,107 INFO L290 TraceCheckUtils]: 142: Hoare triple {9599#false} assume 1 == ~E_7~0;~E_7~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,108 INFO L290 TraceCheckUtils]: 143: Hoare triple {9599#false} assume !(1 == ~E_8~0); {9599#false} is VALID [2022-02-21 04:24:26,108 INFO L290 TraceCheckUtils]: 144: Hoare triple {9599#false} assume 1 == ~E_9~0;~E_9~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,108 INFO L290 TraceCheckUtils]: 145: Hoare triple {9599#false} assume 1 == ~E_10~0;~E_10~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,108 INFO L290 TraceCheckUtils]: 146: Hoare triple {9599#false} assume 1 == ~E_11~0;~E_11~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,108 INFO L290 TraceCheckUtils]: 147: Hoare triple {9599#false} assume 1 == ~E_12~0;~E_12~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,108 INFO L290 TraceCheckUtils]: 148: Hoare triple {9599#false} assume 1 == ~E_13~0;~E_13~0 := 2; {9599#false} is VALID [2022-02-21 04:24:26,108 INFO L290 TraceCheckUtils]: 149: Hoare triple {9599#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {9599#false} is VALID [2022-02-21 04:24:26,109 INFO L290 TraceCheckUtils]: 150: Hoare triple {9599#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {9599#false} is VALID [2022-02-21 04:24:26,109 INFO L290 TraceCheckUtils]: 151: Hoare triple {9599#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {9599#false} is VALID [2022-02-21 04:24:26,109 INFO L290 TraceCheckUtils]: 152: Hoare triple {9599#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {9599#false} is VALID [2022-02-21 04:24:26,109 INFO L290 TraceCheckUtils]: 153: Hoare triple {9599#false} assume !(0 == start_simulation_~tmp~3#1); {9599#false} is VALID [2022-02-21 04:24:26,109 INFO L290 TraceCheckUtils]: 154: Hoare triple {9599#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {9599#false} is VALID [2022-02-21 04:24:26,109 INFO L290 TraceCheckUtils]: 155: Hoare triple {9599#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {9599#false} is VALID [2022-02-21 04:24:26,109 INFO L290 TraceCheckUtils]: 156: Hoare triple {9599#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {9599#false} is VALID [2022-02-21 04:24:26,110 INFO L290 TraceCheckUtils]: 157: Hoare triple {9599#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {9599#false} is VALID [2022-02-21 04:24:26,110 INFO L290 TraceCheckUtils]: 158: Hoare triple {9599#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {9599#false} is VALID [2022-02-21 04:24:26,110 INFO L290 TraceCheckUtils]: 159: Hoare triple {9599#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {9599#false} is VALID [2022-02-21 04:24:26,110 INFO L290 TraceCheckUtils]: 160: Hoare triple {9599#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {9599#false} is VALID [2022-02-21 04:24:26,110 INFO L290 TraceCheckUtils]: 161: Hoare triple {9599#false} assume !(0 != start_simulation_~tmp___0~1#1); {9599#false} is VALID [2022-02-21 04:24:26,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:26,114 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:26,114 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1346275282] [2022-02-21 04:24:26,115 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1346275282] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:26,115 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:26,115 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:26,115 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1087656322] [2022-02-21 04:24:26,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:26,116 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:26,116 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:26,116 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:26,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:26,117 INFO L87 Difference]: Start difference. First operand 1914 states and 2835 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:27,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:27,968 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2022-02-21 04:24:27,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:27,970 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,097 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:28,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,270 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:28,439 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-02-21 04:24:28,440 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:28,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:28,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,444 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:28,444 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-02-21 04:24:28,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:28,471 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:28,479 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2834 transitions. Second operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,484 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2834 transitions. Second operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,488 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. Second operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,657 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2022-02-21 04:24:28,657 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,660 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:28,660 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:28,665 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,668 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:28,826 INFO L93 Difference]: Finished difference Result 1914 states and 2834 transitions. [2022-02-21 04:24:28,826 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,829 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:28,830 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:28,830 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:28,830 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:28,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4806687565308254) internal successors, (2834), 1913 states have internal predecessors, (2834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:28,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2834 transitions. [2022-02-21 04:24:28,979 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-02-21 04:24:28,979 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2834 transitions. [2022-02-21 04:24:28,979 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:24:28,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2834 transitions. [2022-02-21 04:24:28,988 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:28,988 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:28,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:28,990 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:28,990 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:28,991 INFO L791 eck$LassoCheckResult]: Stem: 12376#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 12377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12196#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11912#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11913#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 13089#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13090#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 12048#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12049#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12503#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12338#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12339#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12115#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12116#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12514#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12691#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12845#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12882#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12126#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12127#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 13302#L1258-2 assume !(0 == ~T1_E~0); 12421#L1263-1 assume !(0 == ~T2_E~0); 12422#L1268-1 assume !(0 == ~T3_E~0); 12725#L1273-1 assume !(0 == ~T4_E~0); 13284#L1278-1 assume !(0 == ~T5_E~0); 13145#L1283-1 assume !(0 == ~T6_E~0); 13146#L1288-1 assume !(0 == ~T7_E~0); 13382#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13370#L1298-1 assume !(0 == ~T9_E~0); 13296#L1303-1 assume !(0 == ~T10_E~0); 11941#L1308-1 assume !(0 == ~T11_E~0); 11883#L1313-1 assume !(0 == ~T12_E~0); 11884#L1318-1 assume !(0 == ~T13_E~0); 11890#L1323-1 assume !(0 == ~E_1~0); 11891#L1328-1 assume !(0 == ~E_2~0); 12058#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 13017#L1338-1 assume !(0 == ~E_4~0); 13018#L1343-1 assume !(0 == ~E_5~0); 13119#L1348-1 assume !(0 == ~E_6~0); 13405#L1353-1 assume !(0 == ~E_7~0); 12744#L1358-1 assume !(0 == ~E_8~0); 12745#L1363-1 assume !(0 == ~E_9~0); 13035#L1368-1 assume !(0 == ~E_10~0); 11720#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 11721#L1378-1 assume !(0 == ~E_12~0); 12007#L1383-1 assume !(0 == ~E_13~0); 12008#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12751#L607 assume 1 == ~m_pc~0; 12752#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12078#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13117#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12671#L1560 assume !(0 != activate_threads_~tmp~1#1); 12672#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11903#L626 assume !(1 == ~t1_pc~0); 11904#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12172#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12173#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12342#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 11803#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11804#L645 assume 1 == ~t2_pc~0; 11920#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11877#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12554#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12555#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 12647#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12648#L664 assume 1 == ~t3_pc~0; 13404#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11644#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11645#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12303#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 12304#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13312#L683 assume !(1 == ~t4_pc~0); 12867#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12819#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12820#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12854#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12978#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12597#L702 assume 1 == ~t5_pc~0; 12598#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12523#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12973#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13271#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 13212#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11692#L721 assume !(1 == ~t6_pc~0); 11666#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11667#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11830#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12312#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 12313#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12914#L740 assume 1 == ~t7_pc~0; 11741#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11554#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11555#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11544#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 11545#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12248#L759 assume !(1 == ~t8_pc~0); 12249#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12278#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12971#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12972#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 13103#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13381#L778 assume 1 == ~t9_pc~0; 13268#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11719#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11659#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11588#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 11589#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11916#L797 assume !(1 == ~t10_pc~0); 11917#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12035#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13169#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12419#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 12420#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12709#L816 assume 1 == ~t11_pc~0; 11624#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11625#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12380#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12319#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 12320#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12844#L835 assume 1 == ~t12_pc~0; 12722#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11788#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11810#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11951#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 12476#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12477#L854 assume !(1 == ~t13_pc~0); 12117#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12118#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12168#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11828#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11829#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13208#L1401 assume !(1 == ~M_E~0); 12307#L1401-2 assume !(1 == ~T1_E~0); 12308#L1406-1 assume !(1 == ~T2_E~0); 12903#L1411-1 assume !(1 == ~T3_E~0); 12904#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12570#L1421-1 assume !(1 == ~T5_E~0); 12113#L1426-1 assume !(1 == ~T6_E~0); 12114#L1431-1 assume !(1 == ~T7_E~0); 11662#L1436-1 assume !(1 == ~T8_E~0); 11663#L1441-1 assume !(1 == ~T9_E~0); 12410#L1446-1 assume !(1 == ~T10_E~0); 12411#L1451-1 assume !(1 == ~T11_E~0); 13116#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12770#L1461-1 assume !(1 == ~T13_E~0); 12331#L1466-1 assume !(1 == ~E_1~0); 12332#L1471-1 assume !(1 == ~E_2~0); 13101#L1476-1 assume !(1 == ~E_3~0); 13102#L1481-1 assume !(1 == ~E_4~0); 13250#L1486-1 assume !(1 == ~E_5~0); 11956#L1491-1 assume !(1 == ~E_6~0); 11596#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 11597#L1501-1 assume !(1 == ~E_8~0); 12408#L1506-1 assume !(1 == ~E_9~0); 12409#L1511-1 assume !(1 == ~E_10~0); 12365#L1516-1 assume !(1 == ~E_11~0); 11540#L1521-1 assume !(1 == ~E_12~0); 11541#L1526-1 assume !(1 == ~E_13~0); 11595#L1531-1 assume { :end_inline_reset_delta_events } true; 12138#L1892-2 [2022-02-21 04:24:28,991 INFO L793 eck$LassoCheckResult]: Loop: 12138#L1892-2 assume !false; 13161#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13359#L1233 assume !false; 13342#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12674#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12654#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12812#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11638#L1046 assume !(0 != eval_~tmp~0#1); 11640#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11674#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12846#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13403#L1258-5 assume !(0 == ~T1_E~0); 11816#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11817#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13395#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13401#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13402#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12040#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12041#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13158#L1298-3 assume !(0 == ~T9_E~0); 13159#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13318#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13157#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12658#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11818#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11819#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13242#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11961#L1338-3 assume !(0 == ~E_4~0); 11962#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13074#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13247#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13248#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12614#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12174#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12175#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12931#L1378-3 assume !(0 == ~E_12~0); 12932#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 13113#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13114#L607-42 assume 1 == ~m_pc~0; 12727#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12455#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12456#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12188#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12189#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12710#L626-42 assume 1 == ~t1_pc~0; 12272#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12273#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12577#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12578#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11852#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11853#L645-42 assume !(1 == ~t2_pc~0); 13052#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 13053#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13218#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12059#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11566#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11567#L664-42 assume 1 == ~t3_pc~0; 12369#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12094#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13345#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12880#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12881#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13046#L683-42 assume !(1 == ~t4_pc~0); 12754#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 12755#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12887#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13307#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13308#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13152#L702-42 assume 1 == ~t5_pc~0; 12640#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12265#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12561#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13234#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11582#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11583#L721-42 assume 1 == ~t6_pc~0; 11736#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11756#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12220#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13387#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12392#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12238#L740-42 assume !(1 == ~t7_pc~0); 11975#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 11976#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12517#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12372#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 12373#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12646#L759-42 assume !(1 == ~t8_pc~0); 12496#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 12427#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12428#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12506#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12507#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12602#L778-42 assume 1 == ~t9_pc~0; 12439#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12441#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12851#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12756#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12757#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12814#L797-42 assume 1 == ~t10_pc~0; 11981#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11982#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12983#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13292#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12852#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12853#L816-42 assume 1 == ~t11_pc~0; 11530#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11531#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12073#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12074#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12153#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12154#L835-42 assume !(1 == ~t12_pc~0); 12450#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 12451#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12128#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12129#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13211#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12995#L854-42 assume 1 == ~t13_pc~0; 12996#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12072#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 11682#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11683#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12329#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12330#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13108#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11919#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11783#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11784#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12383#L1421-3 assume !(1 == ~T5_E~0); 12384#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11959#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11960#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11546#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11547#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13136#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12467#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12120#L1461-3 assume !(1 == ~T13_E~0); 12121#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13398#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12060#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12061#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12461#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12088#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12089#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12501#L1501-3 assume !(1 == ~E_8~0); 12502#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12928#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12918#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12919#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12618#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12619#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13013#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11895#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12788#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12429#L1911 assume !(0 == start_simulation_~tmp~3#1); 12430#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12952#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12019#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12890#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11724#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11725#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11954#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11955#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12138#L1892-2 [2022-02-21 04:24:28,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:28,992 INFO L85 PathProgramCache]: Analyzing trace with hash -2008130016, now seen corresponding path program 1 times [2022-02-21 04:24:28,992 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:28,992 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62724233] [2022-02-21 04:24:28,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:28,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:29,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:29,030 INFO L290 TraceCheckUtils]: 0: Hoare triple {17260#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {17260#true} is VALID [2022-02-21 04:24:29,030 INFO L290 TraceCheckUtils]: 1: Hoare triple {17260#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {17262#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:29,031 INFO L290 TraceCheckUtils]: 2: Hoare triple {17262#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {17262#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:29,039 INFO L290 TraceCheckUtils]: 3: Hoare triple {17262#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {17262#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:29,040 INFO L290 TraceCheckUtils]: 4: Hoare triple {17262#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {17262#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:29,040 INFO L290 TraceCheckUtils]: 5: Hoare triple {17262#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {17262#(= ~t2_i~0 1)} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 6: Hoare triple {17262#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 7: Hoare triple {17261#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 8: Hoare triple {17261#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 9: Hoare triple {17261#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 10: Hoare triple {17261#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 11: Hoare triple {17261#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,041 INFO L290 TraceCheckUtils]: 12: Hoare triple {17261#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 13: Hoare triple {17261#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {17261#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 14: Hoare triple {17261#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 15: Hoare triple {17261#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 16: Hoare triple {17261#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 17: Hoare triple {17261#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,042 INFO L290 TraceCheckUtils]: 18: Hoare triple {17261#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {17261#false} is VALID [2022-02-21 04:24:29,043 INFO L290 TraceCheckUtils]: 19: Hoare triple {17261#false} assume 0 == ~M_E~0;~M_E~0 := 1; {17261#false} is VALID [2022-02-21 04:24:29,043 INFO L290 TraceCheckUtils]: 20: Hoare triple {17261#false} assume !(0 == ~T1_E~0); {17261#false} is VALID [2022-02-21 04:24:29,043 INFO L290 TraceCheckUtils]: 21: Hoare triple {17261#false} assume !(0 == ~T2_E~0); {17261#false} is VALID [2022-02-21 04:24:29,043 INFO L290 TraceCheckUtils]: 22: Hoare triple {17261#false} assume !(0 == ~T3_E~0); {17261#false} is VALID [2022-02-21 04:24:29,043 INFO L290 TraceCheckUtils]: 23: Hoare triple {17261#false} assume !(0 == ~T4_E~0); {17261#false} is VALID [2022-02-21 04:24:29,043 INFO L290 TraceCheckUtils]: 24: Hoare triple {17261#false} assume !(0 == ~T5_E~0); {17261#false} is VALID [2022-02-21 04:24:29,043 INFO L290 TraceCheckUtils]: 25: Hoare triple {17261#false} assume !(0 == ~T6_E~0); {17261#false} is VALID [2022-02-21 04:24:29,044 INFO L290 TraceCheckUtils]: 26: Hoare triple {17261#false} assume !(0 == ~T7_E~0); {17261#false} is VALID [2022-02-21 04:24:29,044 INFO L290 TraceCheckUtils]: 27: Hoare triple {17261#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {17261#false} is VALID [2022-02-21 04:24:29,044 INFO L290 TraceCheckUtils]: 28: Hoare triple {17261#false} assume !(0 == ~T9_E~0); {17261#false} is VALID [2022-02-21 04:24:29,044 INFO L290 TraceCheckUtils]: 29: Hoare triple {17261#false} assume !(0 == ~T10_E~0); {17261#false} is VALID [2022-02-21 04:24:29,044 INFO L290 TraceCheckUtils]: 30: Hoare triple {17261#false} assume !(0 == ~T11_E~0); {17261#false} is VALID [2022-02-21 04:24:29,044 INFO L290 TraceCheckUtils]: 31: Hoare triple {17261#false} assume !(0 == ~T12_E~0); {17261#false} is VALID [2022-02-21 04:24:29,044 INFO L290 TraceCheckUtils]: 32: Hoare triple {17261#false} assume !(0 == ~T13_E~0); {17261#false} is VALID [2022-02-21 04:24:29,045 INFO L290 TraceCheckUtils]: 33: Hoare triple {17261#false} assume !(0 == ~E_1~0); {17261#false} is VALID [2022-02-21 04:24:29,045 INFO L290 TraceCheckUtils]: 34: Hoare triple {17261#false} assume !(0 == ~E_2~0); {17261#false} is VALID [2022-02-21 04:24:29,045 INFO L290 TraceCheckUtils]: 35: Hoare triple {17261#false} assume 0 == ~E_3~0;~E_3~0 := 1; {17261#false} is VALID [2022-02-21 04:24:29,045 INFO L290 TraceCheckUtils]: 36: Hoare triple {17261#false} assume !(0 == ~E_4~0); {17261#false} is VALID [2022-02-21 04:24:29,045 INFO L290 TraceCheckUtils]: 37: Hoare triple {17261#false} assume !(0 == ~E_5~0); {17261#false} is VALID [2022-02-21 04:24:29,045 INFO L290 TraceCheckUtils]: 38: Hoare triple {17261#false} assume !(0 == ~E_6~0); {17261#false} is VALID [2022-02-21 04:24:29,045 INFO L290 TraceCheckUtils]: 39: Hoare triple {17261#false} assume !(0 == ~E_7~0); {17261#false} is VALID [2022-02-21 04:24:29,046 INFO L290 TraceCheckUtils]: 40: Hoare triple {17261#false} assume !(0 == ~E_8~0); {17261#false} is VALID [2022-02-21 04:24:29,046 INFO L290 TraceCheckUtils]: 41: Hoare triple {17261#false} assume !(0 == ~E_9~0); {17261#false} is VALID [2022-02-21 04:24:29,046 INFO L290 TraceCheckUtils]: 42: Hoare triple {17261#false} assume !(0 == ~E_10~0); {17261#false} is VALID [2022-02-21 04:24:29,046 INFO L290 TraceCheckUtils]: 43: Hoare triple {17261#false} assume 0 == ~E_11~0;~E_11~0 := 1; {17261#false} is VALID [2022-02-21 04:24:29,046 INFO L290 TraceCheckUtils]: 44: Hoare triple {17261#false} assume !(0 == ~E_12~0); {17261#false} is VALID [2022-02-21 04:24:29,046 INFO L290 TraceCheckUtils]: 45: Hoare triple {17261#false} assume !(0 == ~E_13~0); {17261#false} is VALID [2022-02-21 04:24:29,046 INFO L290 TraceCheckUtils]: 46: Hoare triple {17261#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17261#false} is VALID [2022-02-21 04:24:29,046 INFO L290 TraceCheckUtils]: 47: Hoare triple {17261#false} assume 1 == ~m_pc~0; {17261#false} is VALID [2022-02-21 04:24:29,047 INFO L290 TraceCheckUtils]: 48: Hoare triple {17261#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {17261#false} is VALID [2022-02-21 04:24:29,047 INFO L290 TraceCheckUtils]: 49: Hoare triple {17261#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17261#false} is VALID [2022-02-21 04:24:29,047 INFO L290 TraceCheckUtils]: 50: Hoare triple {17261#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17261#false} is VALID [2022-02-21 04:24:29,047 INFO L290 TraceCheckUtils]: 51: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp~1#1); {17261#false} is VALID [2022-02-21 04:24:29,047 INFO L290 TraceCheckUtils]: 52: Hoare triple {17261#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17261#false} is VALID [2022-02-21 04:24:29,047 INFO L290 TraceCheckUtils]: 53: Hoare triple {17261#false} assume !(1 == ~t1_pc~0); {17261#false} is VALID [2022-02-21 04:24:29,048 INFO L290 TraceCheckUtils]: 54: Hoare triple {17261#false} is_transmit1_triggered_~__retres1~1#1 := 0; {17261#false} is VALID [2022-02-21 04:24:29,048 INFO L290 TraceCheckUtils]: 55: Hoare triple {17261#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17261#false} is VALID [2022-02-21 04:24:29,048 INFO L290 TraceCheckUtils]: 56: Hoare triple {17261#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17261#false} is VALID [2022-02-21 04:24:29,048 INFO L290 TraceCheckUtils]: 57: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp___0~0#1); {17261#false} is VALID [2022-02-21 04:24:29,048 INFO L290 TraceCheckUtils]: 58: Hoare triple {17261#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17261#false} is VALID [2022-02-21 04:24:29,048 INFO L290 TraceCheckUtils]: 59: Hoare triple {17261#false} assume 1 == ~t2_pc~0; {17261#false} is VALID [2022-02-21 04:24:29,048 INFO L290 TraceCheckUtils]: 60: Hoare triple {17261#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {17261#false} is VALID [2022-02-21 04:24:29,049 INFO L290 TraceCheckUtils]: 61: Hoare triple {17261#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17261#false} is VALID [2022-02-21 04:24:29,049 INFO L290 TraceCheckUtils]: 62: Hoare triple {17261#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17261#false} is VALID [2022-02-21 04:24:29,049 INFO L290 TraceCheckUtils]: 63: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp___1~0#1); {17261#false} is VALID [2022-02-21 04:24:29,049 INFO L290 TraceCheckUtils]: 64: Hoare triple {17261#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17261#false} is VALID [2022-02-21 04:24:29,049 INFO L290 TraceCheckUtils]: 65: Hoare triple {17261#false} assume 1 == ~t3_pc~0; {17261#false} is VALID [2022-02-21 04:24:29,049 INFO L290 TraceCheckUtils]: 66: Hoare triple {17261#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17261#false} is VALID [2022-02-21 04:24:29,049 INFO L290 TraceCheckUtils]: 67: Hoare triple {17261#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17261#false} is VALID [2022-02-21 04:24:29,050 INFO L290 TraceCheckUtils]: 68: Hoare triple {17261#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17261#false} is VALID [2022-02-21 04:24:29,050 INFO L290 TraceCheckUtils]: 69: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp___2~0#1); {17261#false} is VALID [2022-02-21 04:24:29,050 INFO L290 TraceCheckUtils]: 70: Hoare triple {17261#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17261#false} is VALID [2022-02-21 04:24:29,050 INFO L290 TraceCheckUtils]: 71: Hoare triple {17261#false} assume !(1 == ~t4_pc~0); {17261#false} is VALID [2022-02-21 04:24:29,050 INFO L290 TraceCheckUtils]: 72: Hoare triple {17261#false} is_transmit4_triggered_~__retres1~4#1 := 0; {17261#false} is VALID [2022-02-21 04:24:29,050 INFO L290 TraceCheckUtils]: 73: Hoare triple {17261#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17261#false} is VALID [2022-02-21 04:24:29,050 INFO L290 TraceCheckUtils]: 74: Hoare triple {17261#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {17261#false} is VALID [2022-02-21 04:24:29,051 INFO L290 TraceCheckUtils]: 75: Hoare triple {17261#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17261#false} is VALID [2022-02-21 04:24:29,053 INFO L290 TraceCheckUtils]: 76: Hoare triple {17261#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17261#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 77: Hoare triple {17261#false} assume 1 == ~t5_pc~0; {17261#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 78: Hoare triple {17261#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17261#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 79: Hoare triple {17261#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17261#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 80: Hoare triple {17261#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {17261#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 81: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp___4~0#1); {17261#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 82: Hoare triple {17261#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17261#false} is VALID [2022-02-21 04:24:29,054 INFO L290 TraceCheckUtils]: 83: Hoare triple {17261#false} assume !(1 == ~t6_pc~0); {17261#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 84: Hoare triple {17261#false} is_transmit6_triggered_~__retres1~6#1 := 0; {17261#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 85: Hoare triple {17261#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17261#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 86: Hoare triple {17261#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {17261#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 87: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp___5~0#1); {17261#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 88: Hoare triple {17261#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17261#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 89: Hoare triple {17261#false} assume 1 == ~t7_pc~0; {17261#false} is VALID [2022-02-21 04:24:29,055 INFO L290 TraceCheckUtils]: 90: Hoare triple {17261#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {17261#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 91: Hoare triple {17261#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17261#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 92: Hoare triple {17261#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {17261#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 93: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp___6~0#1); {17261#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 94: Hoare triple {17261#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {17261#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 95: Hoare triple {17261#false} assume !(1 == ~t8_pc~0); {17261#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 96: Hoare triple {17261#false} is_transmit8_triggered_~__retres1~8#1 := 0; {17261#false} is VALID [2022-02-21 04:24:29,056 INFO L290 TraceCheckUtils]: 97: Hoare triple {17261#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {17261#false} is VALID [2022-02-21 04:24:29,057 INFO L290 TraceCheckUtils]: 98: Hoare triple {17261#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {17261#false} is VALID [2022-02-21 04:24:29,057 INFO L290 TraceCheckUtils]: 99: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp___7~0#1); {17261#false} is VALID [2022-02-21 04:24:29,057 INFO L290 TraceCheckUtils]: 100: Hoare triple {17261#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {17261#false} is VALID [2022-02-21 04:24:29,057 INFO L290 TraceCheckUtils]: 101: Hoare triple {17261#false} assume 1 == ~t9_pc~0; {17261#false} is VALID [2022-02-21 04:24:29,067 INFO L290 TraceCheckUtils]: 102: Hoare triple {17261#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {17261#false} is VALID [2022-02-21 04:24:29,067 INFO L290 TraceCheckUtils]: 103: Hoare triple {17261#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {17261#false} is VALID [2022-02-21 04:24:29,067 INFO L290 TraceCheckUtils]: 104: Hoare triple {17261#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {17261#false} is VALID [2022-02-21 04:24:29,068 INFO L290 TraceCheckUtils]: 105: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp___8~0#1); {17261#false} is VALID [2022-02-21 04:24:29,068 INFO L290 TraceCheckUtils]: 106: Hoare triple {17261#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {17261#false} is VALID [2022-02-21 04:24:29,068 INFO L290 TraceCheckUtils]: 107: Hoare triple {17261#false} assume !(1 == ~t10_pc~0); {17261#false} is VALID [2022-02-21 04:24:29,068 INFO L290 TraceCheckUtils]: 108: Hoare triple {17261#false} is_transmit10_triggered_~__retres1~10#1 := 0; {17261#false} is VALID [2022-02-21 04:24:29,068 INFO L290 TraceCheckUtils]: 109: Hoare triple {17261#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {17261#false} is VALID [2022-02-21 04:24:29,068 INFO L290 TraceCheckUtils]: 110: Hoare triple {17261#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {17261#false} is VALID [2022-02-21 04:24:29,068 INFO L290 TraceCheckUtils]: 111: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp___9~0#1); {17261#false} is VALID [2022-02-21 04:24:29,069 INFO L290 TraceCheckUtils]: 112: Hoare triple {17261#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {17261#false} is VALID [2022-02-21 04:24:29,069 INFO L290 TraceCheckUtils]: 113: Hoare triple {17261#false} assume 1 == ~t11_pc~0; {17261#false} is VALID [2022-02-21 04:24:29,069 INFO L290 TraceCheckUtils]: 114: Hoare triple {17261#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {17261#false} is VALID [2022-02-21 04:24:29,069 INFO L290 TraceCheckUtils]: 115: Hoare triple {17261#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {17261#false} is VALID [2022-02-21 04:24:29,069 INFO L290 TraceCheckUtils]: 116: Hoare triple {17261#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {17261#false} is VALID [2022-02-21 04:24:29,069 INFO L290 TraceCheckUtils]: 117: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp___10~0#1); {17261#false} is VALID [2022-02-21 04:24:29,069 INFO L290 TraceCheckUtils]: 118: Hoare triple {17261#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {17261#false} is VALID [2022-02-21 04:24:29,070 INFO L290 TraceCheckUtils]: 119: Hoare triple {17261#false} assume 1 == ~t12_pc~0; {17261#false} is VALID [2022-02-21 04:24:29,070 INFO L290 TraceCheckUtils]: 120: Hoare triple {17261#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {17261#false} is VALID [2022-02-21 04:24:29,070 INFO L290 TraceCheckUtils]: 121: Hoare triple {17261#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {17261#false} is VALID [2022-02-21 04:24:29,070 INFO L290 TraceCheckUtils]: 122: Hoare triple {17261#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {17261#false} is VALID [2022-02-21 04:24:29,070 INFO L290 TraceCheckUtils]: 123: Hoare triple {17261#false} assume !(0 != activate_threads_~tmp___11~0#1); {17261#false} is VALID [2022-02-21 04:24:29,070 INFO L290 TraceCheckUtils]: 124: Hoare triple {17261#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {17261#false} is VALID [2022-02-21 04:24:29,070 INFO L290 TraceCheckUtils]: 125: Hoare triple {17261#false} assume !(1 == ~t13_pc~0); {17261#false} is VALID [2022-02-21 04:24:29,071 INFO L290 TraceCheckUtils]: 126: Hoare triple {17261#false} is_transmit13_triggered_~__retres1~13#1 := 0; {17261#false} is VALID [2022-02-21 04:24:29,071 INFO L290 TraceCheckUtils]: 127: Hoare triple {17261#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {17261#false} is VALID [2022-02-21 04:24:29,071 INFO L290 TraceCheckUtils]: 128: Hoare triple {17261#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {17261#false} is VALID [2022-02-21 04:24:29,071 INFO L290 TraceCheckUtils]: 129: Hoare triple {17261#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {17261#false} is VALID [2022-02-21 04:24:29,071 INFO L290 TraceCheckUtils]: 130: Hoare triple {17261#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17261#false} is VALID [2022-02-21 04:24:29,071 INFO L290 TraceCheckUtils]: 131: Hoare triple {17261#false} assume !(1 == ~M_E~0); {17261#false} is VALID [2022-02-21 04:24:29,071 INFO L290 TraceCheckUtils]: 132: Hoare triple {17261#false} assume !(1 == ~T1_E~0); {17261#false} is VALID [2022-02-21 04:24:29,072 INFO L290 TraceCheckUtils]: 133: Hoare triple {17261#false} assume !(1 == ~T2_E~0); {17261#false} is VALID [2022-02-21 04:24:29,072 INFO L290 TraceCheckUtils]: 134: Hoare triple {17261#false} assume !(1 == ~T3_E~0); {17261#false} is VALID [2022-02-21 04:24:29,072 INFO L290 TraceCheckUtils]: 135: Hoare triple {17261#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,072 INFO L290 TraceCheckUtils]: 136: Hoare triple {17261#false} assume !(1 == ~T5_E~0); {17261#false} is VALID [2022-02-21 04:24:29,072 INFO L290 TraceCheckUtils]: 137: Hoare triple {17261#false} assume !(1 == ~T6_E~0); {17261#false} is VALID [2022-02-21 04:24:29,072 INFO L290 TraceCheckUtils]: 138: Hoare triple {17261#false} assume !(1 == ~T7_E~0); {17261#false} is VALID [2022-02-21 04:24:29,073 INFO L290 TraceCheckUtils]: 139: Hoare triple {17261#false} assume !(1 == ~T8_E~0); {17261#false} is VALID [2022-02-21 04:24:29,073 INFO L290 TraceCheckUtils]: 140: Hoare triple {17261#false} assume !(1 == ~T9_E~0); {17261#false} is VALID [2022-02-21 04:24:29,073 INFO L290 TraceCheckUtils]: 141: Hoare triple {17261#false} assume !(1 == ~T10_E~0); {17261#false} is VALID [2022-02-21 04:24:29,073 INFO L290 TraceCheckUtils]: 142: Hoare triple {17261#false} assume !(1 == ~T11_E~0); {17261#false} is VALID [2022-02-21 04:24:29,073 INFO L290 TraceCheckUtils]: 143: Hoare triple {17261#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,073 INFO L290 TraceCheckUtils]: 144: Hoare triple {17261#false} assume !(1 == ~T13_E~0); {17261#false} is VALID [2022-02-21 04:24:29,073 INFO L290 TraceCheckUtils]: 145: Hoare triple {17261#false} assume !(1 == ~E_1~0); {17261#false} is VALID [2022-02-21 04:24:29,073 INFO L290 TraceCheckUtils]: 146: Hoare triple {17261#false} assume !(1 == ~E_2~0); {17261#false} is VALID [2022-02-21 04:24:29,074 INFO L290 TraceCheckUtils]: 147: Hoare triple {17261#false} assume !(1 == ~E_3~0); {17261#false} is VALID [2022-02-21 04:24:29,074 INFO L290 TraceCheckUtils]: 148: Hoare triple {17261#false} assume !(1 == ~E_4~0); {17261#false} is VALID [2022-02-21 04:24:29,074 INFO L290 TraceCheckUtils]: 149: Hoare triple {17261#false} assume !(1 == ~E_5~0); {17261#false} is VALID [2022-02-21 04:24:29,074 INFO L290 TraceCheckUtils]: 150: Hoare triple {17261#false} assume !(1 == ~E_6~0); {17261#false} is VALID [2022-02-21 04:24:29,074 INFO L290 TraceCheckUtils]: 151: Hoare triple {17261#false} assume 1 == ~E_7~0;~E_7~0 := 2; {17261#false} is VALID [2022-02-21 04:24:29,074 INFO L290 TraceCheckUtils]: 152: Hoare triple {17261#false} assume !(1 == ~E_8~0); {17261#false} is VALID [2022-02-21 04:24:29,074 INFO L290 TraceCheckUtils]: 153: Hoare triple {17261#false} assume !(1 == ~E_9~0); {17261#false} is VALID [2022-02-21 04:24:29,075 INFO L290 TraceCheckUtils]: 154: Hoare triple {17261#false} assume !(1 == ~E_10~0); {17261#false} is VALID [2022-02-21 04:24:29,075 INFO L290 TraceCheckUtils]: 155: Hoare triple {17261#false} assume !(1 == ~E_11~0); {17261#false} is VALID [2022-02-21 04:24:29,075 INFO L290 TraceCheckUtils]: 156: Hoare triple {17261#false} assume !(1 == ~E_12~0); {17261#false} is VALID [2022-02-21 04:24:29,075 INFO L290 TraceCheckUtils]: 157: Hoare triple {17261#false} assume !(1 == ~E_13~0); {17261#false} is VALID [2022-02-21 04:24:29,075 INFO L290 TraceCheckUtils]: 158: Hoare triple {17261#false} assume { :end_inline_reset_delta_events } true; {17261#false} is VALID [2022-02-21 04:24:29,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:29,076 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:29,076 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62724233] [2022-02-21 04:24:29,076 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [62724233] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:29,076 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:29,077 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:29,077 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556409183] [2022-02-21 04:24:29,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:29,077 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:29,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:29,078 INFO L85 PathProgramCache]: Analyzing trace with hash 259811934, now seen corresponding path program 1 times [2022-02-21 04:24:29,078 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:29,078 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842659287] [2022-02-21 04:24:29,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:29,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:29,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:29,161 INFO L290 TraceCheckUtils]: 0: Hoare triple {17263#true} assume !false; {17263#true} is VALID [2022-02-21 04:24:29,161 INFO L290 TraceCheckUtils]: 1: Hoare triple {17263#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {17263#true} is VALID [2022-02-21 04:24:29,161 INFO L290 TraceCheckUtils]: 2: Hoare triple {17263#true} assume !false; {17263#true} is VALID [2022-02-21 04:24:29,161 INFO L290 TraceCheckUtils]: 3: Hoare triple {17263#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {17263#true} is VALID [2022-02-21 04:24:29,162 INFO L290 TraceCheckUtils]: 4: Hoare triple {17263#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {17263#true} is VALID [2022-02-21 04:24:29,162 INFO L290 TraceCheckUtils]: 5: Hoare triple {17263#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {17263#true} is VALID [2022-02-21 04:24:29,162 INFO L290 TraceCheckUtils]: 6: Hoare triple {17263#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {17263#true} is VALID [2022-02-21 04:24:29,162 INFO L290 TraceCheckUtils]: 7: Hoare triple {17263#true} assume !(0 != eval_~tmp~0#1); {17263#true} is VALID [2022-02-21 04:24:29,162 INFO L290 TraceCheckUtils]: 8: Hoare triple {17263#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {17263#true} is VALID [2022-02-21 04:24:29,162 INFO L290 TraceCheckUtils]: 9: Hoare triple {17263#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {17263#true} is VALID [2022-02-21 04:24:29,162 INFO L290 TraceCheckUtils]: 10: Hoare triple {17263#true} assume 0 == ~M_E~0;~M_E~0 := 1; {17263#true} is VALID [2022-02-21 04:24:29,163 INFO L290 TraceCheckUtils]: 11: Hoare triple {17263#true} assume !(0 == ~T1_E~0); {17263#true} is VALID [2022-02-21 04:24:29,163 INFO L290 TraceCheckUtils]: 12: Hoare triple {17263#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {17263#true} is VALID [2022-02-21 04:24:29,163 INFO L290 TraceCheckUtils]: 13: Hoare triple {17263#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {17263#true} is VALID [2022-02-21 04:24:29,163 INFO L290 TraceCheckUtils]: 14: Hoare triple {17263#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {17263#true} is VALID [2022-02-21 04:24:29,163 INFO L290 TraceCheckUtils]: 15: Hoare triple {17263#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,164 INFO L290 TraceCheckUtils]: 16: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,164 INFO L290 TraceCheckUtils]: 17: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,165 INFO L290 TraceCheckUtils]: 18: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,165 INFO L290 TraceCheckUtils]: 19: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,165 INFO L290 TraceCheckUtils]: 20: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,166 INFO L290 TraceCheckUtils]: 21: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,166 INFO L290 TraceCheckUtils]: 22: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,167 INFO L290 TraceCheckUtils]: 23: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,167 INFO L290 TraceCheckUtils]: 24: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,167 INFO L290 TraceCheckUtils]: 25: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,168 INFO L290 TraceCheckUtils]: 26: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,168 INFO L290 TraceCheckUtils]: 27: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,169 INFO L290 TraceCheckUtils]: 28: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,169 INFO L290 TraceCheckUtils]: 29: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,169 INFO L290 TraceCheckUtils]: 30: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,170 INFO L290 TraceCheckUtils]: 31: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,174 INFO L290 TraceCheckUtils]: 32: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,174 INFO L290 TraceCheckUtils]: 33: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,174 INFO L290 TraceCheckUtils]: 34: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,175 INFO L290 TraceCheckUtils]: 35: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,175 INFO L290 TraceCheckUtils]: 36: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,176 INFO L290 TraceCheckUtils]: 37: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,176 INFO L290 TraceCheckUtils]: 38: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,176 INFO L290 TraceCheckUtils]: 39: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,177 INFO L290 TraceCheckUtils]: 40: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,177 INFO L290 TraceCheckUtils]: 41: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,177 INFO L290 TraceCheckUtils]: 42: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,178 INFO L290 TraceCheckUtils]: 43: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,178 INFO L290 TraceCheckUtils]: 44: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,179 INFO L290 TraceCheckUtils]: 45: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,179 INFO L290 TraceCheckUtils]: 46: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,179 INFO L290 TraceCheckUtils]: 47: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,180 INFO L290 TraceCheckUtils]: 48: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,180 INFO L290 TraceCheckUtils]: 49: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,181 INFO L290 TraceCheckUtils]: 50: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,181 INFO L290 TraceCheckUtils]: 51: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,181 INFO L290 TraceCheckUtils]: 52: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,182 INFO L290 TraceCheckUtils]: 53: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,182 INFO L290 TraceCheckUtils]: 54: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,183 INFO L290 TraceCheckUtils]: 55: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,183 INFO L290 TraceCheckUtils]: 56: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,183 INFO L290 TraceCheckUtils]: 57: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,184 INFO L290 TraceCheckUtils]: 58: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,184 INFO L290 TraceCheckUtils]: 59: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,185 INFO L290 TraceCheckUtils]: 60: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,185 INFO L290 TraceCheckUtils]: 61: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,185 INFO L290 TraceCheckUtils]: 62: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,186 INFO L290 TraceCheckUtils]: 63: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,186 INFO L290 TraceCheckUtils]: 64: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,186 INFO L290 TraceCheckUtils]: 65: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,187 INFO L290 TraceCheckUtils]: 66: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,187 INFO L290 TraceCheckUtils]: 67: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 68: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 69: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,188 INFO L290 TraceCheckUtils]: 70: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,189 INFO L290 TraceCheckUtils]: 71: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,189 INFO L290 TraceCheckUtils]: 72: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,190 INFO L290 TraceCheckUtils]: 73: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,190 INFO L290 TraceCheckUtils]: 74: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,190 INFO L290 TraceCheckUtils]: 75: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,191 INFO L290 TraceCheckUtils]: 76: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,191 INFO L290 TraceCheckUtils]: 77: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,192 INFO L290 TraceCheckUtils]: 78: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,192 INFO L290 TraceCheckUtils]: 79: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,192 INFO L290 TraceCheckUtils]: 80: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t7_pc~0); {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,193 INFO L290 TraceCheckUtils]: 81: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,193 INFO L290 TraceCheckUtils]: 82: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,194 INFO L290 TraceCheckUtils]: 83: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,194 INFO L290 TraceCheckUtils]: 84: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,194 INFO L290 TraceCheckUtils]: 85: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,195 INFO L290 TraceCheckUtils]: 86: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,195 INFO L290 TraceCheckUtils]: 87: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,196 INFO L290 TraceCheckUtils]: 88: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,196 INFO L290 TraceCheckUtils]: 89: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,196 INFO L290 TraceCheckUtils]: 90: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,197 INFO L290 TraceCheckUtils]: 91: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,197 INFO L290 TraceCheckUtils]: 92: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,197 INFO L290 TraceCheckUtils]: 93: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,198 INFO L290 TraceCheckUtils]: 94: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,198 INFO L290 TraceCheckUtils]: 95: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,199 INFO L290 TraceCheckUtils]: 96: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,199 INFO L290 TraceCheckUtils]: 97: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,199 INFO L290 TraceCheckUtils]: 98: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,200 INFO L290 TraceCheckUtils]: 99: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,200 INFO L290 TraceCheckUtils]: 100: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,200 INFO L290 TraceCheckUtils]: 101: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,201 INFO L290 TraceCheckUtils]: 102: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,201 INFO L290 TraceCheckUtils]: 103: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,202 INFO L290 TraceCheckUtils]: 104: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,202 INFO L290 TraceCheckUtils]: 105: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,202 INFO L290 TraceCheckUtils]: 106: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,203 INFO L290 TraceCheckUtils]: 107: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,203 INFO L290 TraceCheckUtils]: 108: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,204 INFO L290 TraceCheckUtils]: 109: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,204 INFO L290 TraceCheckUtils]: 110: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t12_pc~0); {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,204 INFO L290 TraceCheckUtils]: 111: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,205 INFO L290 TraceCheckUtils]: 112: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,205 INFO L290 TraceCheckUtils]: 113: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,205 INFO L290 TraceCheckUtils]: 114: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,206 INFO L290 TraceCheckUtils]: 115: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,206 INFO L290 TraceCheckUtils]: 116: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,207 INFO L290 TraceCheckUtils]: 117: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,207 INFO L290 TraceCheckUtils]: 118: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,207 INFO L290 TraceCheckUtils]: 119: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,208 INFO L290 TraceCheckUtils]: 120: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,208 INFO L290 TraceCheckUtils]: 121: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,209 INFO L290 TraceCheckUtils]: 122: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,209 INFO L290 TraceCheckUtils]: 123: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,209 INFO L290 TraceCheckUtils]: 124: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,210 INFO L290 TraceCheckUtils]: 125: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,210 INFO L290 TraceCheckUtils]: 126: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17265#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:29,210 INFO L290 TraceCheckUtils]: 127: Hoare triple {17265#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {17264#false} is VALID [2022-02-21 04:24:29,211 INFO L290 TraceCheckUtils]: 128: Hoare triple {17264#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,211 INFO L290 TraceCheckUtils]: 129: Hoare triple {17264#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,211 INFO L290 TraceCheckUtils]: 130: Hoare triple {17264#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,211 INFO L290 TraceCheckUtils]: 131: Hoare triple {17264#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,211 INFO L290 TraceCheckUtils]: 132: Hoare triple {17264#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,211 INFO L290 TraceCheckUtils]: 133: Hoare triple {17264#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,211 INFO L290 TraceCheckUtils]: 134: Hoare triple {17264#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,212 INFO L290 TraceCheckUtils]: 135: Hoare triple {17264#false} assume !(1 == ~T13_E~0); {17264#false} is VALID [2022-02-21 04:24:29,212 INFO L290 TraceCheckUtils]: 136: Hoare triple {17264#false} assume 1 == ~E_1~0;~E_1~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,212 INFO L290 TraceCheckUtils]: 137: Hoare triple {17264#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,212 INFO L290 TraceCheckUtils]: 138: Hoare triple {17264#false} assume 1 == ~E_3~0;~E_3~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,212 INFO L290 TraceCheckUtils]: 139: Hoare triple {17264#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,212 INFO L290 TraceCheckUtils]: 140: Hoare triple {17264#false} assume 1 == ~E_5~0;~E_5~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,212 INFO L290 TraceCheckUtils]: 141: Hoare triple {17264#false} assume 1 == ~E_6~0;~E_6~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,212 INFO L290 TraceCheckUtils]: 142: Hoare triple {17264#false} assume 1 == ~E_7~0;~E_7~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,213 INFO L290 TraceCheckUtils]: 143: Hoare triple {17264#false} assume !(1 == ~E_8~0); {17264#false} is VALID [2022-02-21 04:24:29,213 INFO L290 TraceCheckUtils]: 144: Hoare triple {17264#false} assume 1 == ~E_9~0;~E_9~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,213 INFO L290 TraceCheckUtils]: 145: Hoare triple {17264#false} assume 1 == ~E_10~0;~E_10~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,213 INFO L290 TraceCheckUtils]: 146: Hoare triple {17264#false} assume 1 == ~E_11~0;~E_11~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,213 INFO L290 TraceCheckUtils]: 147: Hoare triple {17264#false} assume 1 == ~E_12~0;~E_12~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,213 INFO L290 TraceCheckUtils]: 148: Hoare triple {17264#false} assume 1 == ~E_13~0;~E_13~0 := 2; {17264#false} is VALID [2022-02-21 04:24:29,213 INFO L290 TraceCheckUtils]: 149: Hoare triple {17264#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {17264#false} is VALID [2022-02-21 04:24:29,214 INFO L290 TraceCheckUtils]: 150: Hoare triple {17264#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {17264#false} is VALID [2022-02-21 04:24:29,214 INFO L290 TraceCheckUtils]: 151: Hoare triple {17264#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {17264#false} is VALID [2022-02-21 04:24:29,214 INFO L290 TraceCheckUtils]: 152: Hoare triple {17264#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {17264#false} is VALID [2022-02-21 04:24:29,214 INFO L290 TraceCheckUtils]: 153: Hoare triple {17264#false} assume !(0 == start_simulation_~tmp~3#1); {17264#false} is VALID [2022-02-21 04:24:29,214 INFO L290 TraceCheckUtils]: 154: Hoare triple {17264#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {17264#false} is VALID [2022-02-21 04:24:29,214 INFO L290 TraceCheckUtils]: 155: Hoare triple {17264#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {17264#false} is VALID [2022-02-21 04:24:29,214 INFO L290 TraceCheckUtils]: 156: Hoare triple {17264#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {17264#false} is VALID [2022-02-21 04:24:29,215 INFO L290 TraceCheckUtils]: 157: Hoare triple {17264#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {17264#false} is VALID [2022-02-21 04:24:29,215 INFO L290 TraceCheckUtils]: 158: Hoare triple {17264#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {17264#false} is VALID [2022-02-21 04:24:29,215 INFO L290 TraceCheckUtils]: 159: Hoare triple {17264#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {17264#false} is VALID [2022-02-21 04:24:29,215 INFO L290 TraceCheckUtils]: 160: Hoare triple {17264#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {17264#false} is VALID [2022-02-21 04:24:29,215 INFO L290 TraceCheckUtils]: 161: Hoare triple {17264#false} assume !(0 != start_simulation_~tmp___0~1#1); {17264#false} is VALID [2022-02-21 04:24:29,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:29,216 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:29,216 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842659287] [2022-02-21 04:24:29,216 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842659287] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:29,216 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:29,217 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:29,217 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1631640539] [2022-02-21 04:24:29,217 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:29,217 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:29,217 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:29,218 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:29,218 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:29,218 INFO L87 Difference]: Start difference. First operand 1914 states and 2834 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:30,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:30,941 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2022-02-21 04:24:30,941 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:30,941 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,068 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:31,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,211 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:31,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-02-21 04:24:31,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:31,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:31,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,349 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:31,349 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-02-21 04:24:31,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:31,374 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:31,384 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2833 transitions. Second operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,388 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2833 transitions. Second operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,390 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. Second operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:31,486 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2022-02-21 04:24:31,486 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,489 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:31,489 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:31,492 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,494 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:31,617 INFO L93 Difference]: Finished difference Result 1914 states and 2833 transitions. [2022-02-21 04:24:31,617 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,620 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:31,620 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:31,620 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:31,620 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:31,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.480146290491118) internal successors, (2833), 1913 states have internal predecessors, (2833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:31,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2833 transitions. [2022-02-21 04:24:31,751 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-02-21 04:24:31,752 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2833 transitions. [2022-02-21 04:24:31,752 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:24:31,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2833 transitions. [2022-02-21 04:24:31,760 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:31,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:31,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:31,762 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:31,762 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:31,762 INFO L791 eck$LassoCheckResult]: Stem: 20041#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 20042#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 19861#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19577#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19578#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20754#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20755#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19713#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 19714#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 20168#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 20003#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20004#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19780#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19781#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20179#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20356#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20510#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20547#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19791#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19792#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 20967#L1258-2 assume !(0 == ~T1_E~0); 20086#L1263-1 assume !(0 == ~T2_E~0); 20087#L1268-1 assume !(0 == ~T3_E~0); 20390#L1273-1 assume !(0 == ~T4_E~0); 20949#L1278-1 assume !(0 == ~T5_E~0); 20810#L1283-1 assume !(0 == ~T6_E~0); 20811#L1288-1 assume !(0 == ~T7_E~0); 21047#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21035#L1298-1 assume !(0 == ~T9_E~0); 20961#L1303-1 assume !(0 == ~T10_E~0); 19606#L1308-1 assume !(0 == ~T11_E~0); 19548#L1313-1 assume !(0 == ~T12_E~0); 19549#L1318-1 assume !(0 == ~T13_E~0); 19555#L1323-1 assume !(0 == ~E_1~0); 19556#L1328-1 assume !(0 == ~E_2~0); 19723#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 20682#L1338-1 assume !(0 == ~E_4~0); 20683#L1343-1 assume !(0 == ~E_5~0); 20784#L1348-1 assume !(0 == ~E_6~0); 21070#L1353-1 assume !(0 == ~E_7~0); 20409#L1358-1 assume !(0 == ~E_8~0); 20410#L1363-1 assume !(0 == ~E_9~0); 20700#L1368-1 assume !(0 == ~E_10~0); 19385#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 19386#L1378-1 assume !(0 == ~E_12~0); 19672#L1383-1 assume !(0 == ~E_13~0); 19673#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20416#L607 assume 1 == ~m_pc~0; 20417#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19743#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20782#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20336#L1560 assume !(0 != activate_threads_~tmp~1#1); 20337#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19568#L626 assume !(1 == ~t1_pc~0); 19569#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 19837#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19838#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20007#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 19468#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19469#L645 assume 1 == ~t2_pc~0; 19585#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19542#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20219#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20220#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 20312#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20313#L664 assume 1 == ~t3_pc~0; 21069#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19309#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19310#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19968#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 19969#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20977#L683 assume !(1 == ~t4_pc~0); 20532#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20484#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20485#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20519#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20643#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20262#L702 assume 1 == ~t5_pc~0; 20263#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20188#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20638#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20936#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 20877#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19357#L721 assume !(1 == ~t6_pc~0); 19331#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19332#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19495#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19977#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 19978#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20579#L740 assume 1 == ~t7_pc~0; 19406#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19219#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19220#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19209#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 19210#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19913#L759 assume !(1 == ~t8_pc~0); 19914#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19943#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20636#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20637#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 20768#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21046#L778 assume 1 == ~t9_pc~0; 20933#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19384#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19324#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19253#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 19254#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19581#L797 assume !(1 == ~t10_pc~0); 19582#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19700#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20834#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20084#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 20085#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20374#L816 assume 1 == ~t11_pc~0; 19289#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19290#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20045#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19984#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 19985#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20509#L835 assume 1 == ~t12_pc~0; 20387#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 19453#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19475#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19616#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 20141#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20142#L854 assume !(1 == ~t13_pc~0); 19782#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 19783#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19833#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19493#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19494#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20873#L1401 assume !(1 == ~M_E~0); 19972#L1401-2 assume !(1 == ~T1_E~0); 19973#L1406-1 assume !(1 == ~T2_E~0); 20568#L1411-1 assume !(1 == ~T3_E~0); 20569#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20235#L1421-1 assume !(1 == ~T5_E~0); 19778#L1426-1 assume !(1 == ~T6_E~0); 19779#L1431-1 assume !(1 == ~T7_E~0); 19327#L1436-1 assume !(1 == ~T8_E~0); 19328#L1441-1 assume !(1 == ~T9_E~0); 20075#L1446-1 assume !(1 == ~T10_E~0); 20076#L1451-1 assume !(1 == ~T11_E~0); 20781#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20435#L1461-1 assume !(1 == ~T13_E~0); 19996#L1466-1 assume !(1 == ~E_1~0); 19997#L1471-1 assume !(1 == ~E_2~0); 20766#L1476-1 assume !(1 == ~E_3~0); 20767#L1481-1 assume !(1 == ~E_4~0); 20915#L1486-1 assume !(1 == ~E_5~0); 19621#L1491-1 assume !(1 == ~E_6~0); 19261#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 19262#L1501-1 assume !(1 == ~E_8~0); 20073#L1506-1 assume !(1 == ~E_9~0); 20074#L1511-1 assume !(1 == ~E_10~0); 20030#L1516-1 assume !(1 == ~E_11~0); 19205#L1521-1 assume !(1 == ~E_12~0); 19206#L1526-1 assume !(1 == ~E_13~0); 19260#L1531-1 assume { :end_inline_reset_delta_events } true; 19803#L1892-2 [2022-02-21 04:24:31,763 INFO L793 eck$LassoCheckResult]: Loop: 19803#L1892-2 assume !false; 20826#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21024#L1233 assume !false; 21007#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20339#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20319#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20477#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19303#L1046 assume !(0 != eval_~tmp~0#1); 19305#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19339#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20511#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21068#L1258-5 assume !(0 == ~T1_E~0); 19481#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19482#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21060#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21066#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21067#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19705#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19706#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20823#L1298-3 assume !(0 == ~T9_E~0); 20824#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20983#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20822#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20323#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19483#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19484#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20907#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19626#L1338-3 assume !(0 == ~E_4~0); 19627#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20739#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20912#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20913#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20279#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19839#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19840#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20596#L1378-3 assume !(0 == ~E_12~0); 20597#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20778#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20779#L607-42 assume 1 == ~m_pc~0; 20392#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 20120#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20121#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19853#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19854#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20375#L626-42 assume 1 == ~t1_pc~0; 19937#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19938#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20242#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20243#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19517#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19518#L645-42 assume 1 == ~t2_pc~0; 20976#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20718#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20883#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19724#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19231#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19232#L664-42 assume 1 == ~t3_pc~0; 20034#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19759#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21010#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20545#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20546#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20711#L683-42 assume !(1 == ~t4_pc~0); 20419#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 20420#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20552#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20972#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20973#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20817#L702-42 assume 1 == ~t5_pc~0; 20305#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19930#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20226#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20899#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19247#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19248#L721-42 assume 1 == ~t6_pc~0; 19401#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19421#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19885#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21052#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20057#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19903#L740-42 assume 1 == ~t7_pc~0; 19904#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19641#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20182#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20037#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 20038#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20311#L759-42 assume 1 == ~t8_pc~0; 20160#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20092#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20093#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20171#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20172#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20267#L778-42 assume 1 == ~t9_pc~0; 20104#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20106#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20516#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20421#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20422#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20479#L797-42 assume !(1 == ~t10_pc~0); 19648#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 19647#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20648#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20957#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20517#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20518#L816-42 assume 1 == ~t11_pc~0; 19195#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19196#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19738#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19739#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19818#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19819#L835-42 assume !(1 == ~t12_pc~0); 20115#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 20116#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19793#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19794#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20876#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20660#L854-42 assume 1 == ~t13_pc~0; 20661#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 19737#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 19347#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19348#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 19994#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19995#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20773#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19584#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19448#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19449#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20048#L1421-3 assume !(1 == ~T5_E~0); 20049#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19624#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19625#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19211#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19212#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20801#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20132#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19785#L1461-3 assume !(1 == ~T13_E~0); 19786#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21063#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19725#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19726#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20126#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19753#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19754#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20166#L1501-3 assume !(1 == ~E_8~0); 20167#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20593#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20583#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20584#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20283#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20284#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20678#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19560#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20453#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 20094#L1911 assume !(0 == start_simulation_~tmp~3#1); 20095#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20617#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 19684#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20555#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19389#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19390#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19619#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19620#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19803#L1892-2 [2022-02-21 04:24:31,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:31,764 INFO L85 PathProgramCache]: Analyzing trace with hash -602938338, now seen corresponding path program 1 times [2022-02-21 04:24:31,764 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:31,764 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [952040436] [2022-02-21 04:24:31,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:31,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:31,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:31,814 INFO L290 TraceCheckUtils]: 0: Hoare triple {24925#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {24925#true} is VALID [2022-02-21 04:24:31,815 INFO L290 TraceCheckUtils]: 1: Hoare triple {24925#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {24927#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,815 INFO L290 TraceCheckUtils]: 2: Hoare triple {24927#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {24927#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,815 INFO L290 TraceCheckUtils]: 3: Hoare triple {24927#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {24927#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,816 INFO L290 TraceCheckUtils]: 4: Hoare triple {24927#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {24927#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,816 INFO L290 TraceCheckUtils]: 5: Hoare triple {24927#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {24927#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,816 INFO L290 TraceCheckUtils]: 6: Hoare triple {24927#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {24927#(= ~t3_i~0 1)} is VALID [2022-02-21 04:24:31,817 INFO L290 TraceCheckUtils]: 7: Hoare triple {24927#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,817 INFO L290 TraceCheckUtils]: 8: Hoare triple {24926#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,817 INFO L290 TraceCheckUtils]: 9: Hoare triple {24926#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,817 INFO L290 TraceCheckUtils]: 10: Hoare triple {24926#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,817 INFO L290 TraceCheckUtils]: 11: Hoare triple {24926#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,817 INFO L290 TraceCheckUtils]: 12: Hoare triple {24926#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,818 INFO L290 TraceCheckUtils]: 13: Hoare triple {24926#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {24926#false} is VALID [2022-02-21 04:24:31,818 INFO L290 TraceCheckUtils]: 14: Hoare triple {24926#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,818 INFO L290 TraceCheckUtils]: 15: Hoare triple {24926#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,818 INFO L290 TraceCheckUtils]: 16: Hoare triple {24926#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,818 INFO L290 TraceCheckUtils]: 17: Hoare triple {24926#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,818 INFO L290 TraceCheckUtils]: 18: Hoare triple {24926#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {24926#false} is VALID [2022-02-21 04:24:31,818 INFO L290 TraceCheckUtils]: 19: Hoare triple {24926#false} assume 0 == ~M_E~0;~M_E~0 := 1; {24926#false} is VALID [2022-02-21 04:24:31,819 INFO L290 TraceCheckUtils]: 20: Hoare triple {24926#false} assume !(0 == ~T1_E~0); {24926#false} is VALID [2022-02-21 04:24:31,819 INFO L290 TraceCheckUtils]: 21: Hoare triple {24926#false} assume !(0 == ~T2_E~0); {24926#false} is VALID [2022-02-21 04:24:31,819 INFO L290 TraceCheckUtils]: 22: Hoare triple {24926#false} assume !(0 == ~T3_E~0); {24926#false} is VALID [2022-02-21 04:24:31,819 INFO L290 TraceCheckUtils]: 23: Hoare triple {24926#false} assume !(0 == ~T4_E~0); {24926#false} is VALID [2022-02-21 04:24:31,819 INFO L290 TraceCheckUtils]: 24: Hoare triple {24926#false} assume !(0 == ~T5_E~0); {24926#false} is VALID [2022-02-21 04:24:31,819 INFO L290 TraceCheckUtils]: 25: Hoare triple {24926#false} assume !(0 == ~T6_E~0); {24926#false} is VALID [2022-02-21 04:24:31,819 INFO L290 TraceCheckUtils]: 26: Hoare triple {24926#false} assume !(0 == ~T7_E~0); {24926#false} is VALID [2022-02-21 04:24:31,820 INFO L290 TraceCheckUtils]: 27: Hoare triple {24926#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {24926#false} is VALID [2022-02-21 04:24:31,820 INFO L290 TraceCheckUtils]: 28: Hoare triple {24926#false} assume !(0 == ~T9_E~0); {24926#false} is VALID [2022-02-21 04:24:31,820 INFO L290 TraceCheckUtils]: 29: Hoare triple {24926#false} assume !(0 == ~T10_E~0); {24926#false} is VALID [2022-02-21 04:24:31,820 INFO L290 TraceCheckUtils]: 30: Hoare triple {24926#false} assume !(0 == ~T11_E~0); {24926#false} is VALID [2022-02-21 04:24:31,820 INFO L290 TraceCheckUtils]: 31: Hoare triple {24926#false} assume !(0 == ~T12_E~0); {24926#false} is VALID [2022-02-21 04:24:31,820 INFO L290 TraceCheckUtils]: 32: Hoare triple {24926#false} assume !(0 == ~T13_E~0); {24926#false} is VALID [2022-02-21 04:24:31,820 INFO L290 TraceCheckUtils]: 33: Hoare triple {24926#false} assume !(0 == ~E_1~0); {24926#false} is VALID [2022-02-21 04:24:31,821 INFO L290 TraceCheckUtils]: 34: Hoare triple {24926#false} assume !(0 == ~E_2~0); {24926#false} is VALID [2022-02-21 04:24:31,821 INFO L290 TraceCheckUtils]: 35: Hoare triple {24926#false} assume 0 == ~E_3~0;~E_3~0 := 1; {24926#false} is VALID [2022-02-21 04:24:31,821 INFO L290 TraceCheckUtils]: 36: Hoare triple {24926#false} assume !(0 == ~E_4~0); {24926#false} is VALID [2022-02-21 04:24:31,821 INFO L290 TraceCheckUtils]: 37: Hoare triple {24926#false} assume !(0 == ~E_5~0); {24926#false} is VALID [2022-02-21 04:24:31,821 INFO L290 TraceCheckUtils]: 38: Hoare triple {24926#false} assume !(0 == ~E_6~0); {24926#false} is VALID [2022-02-21 04:24:31,821 INFO L290 TraceCheckUtils]: 39: Hoare triple {24926#false} assume !(0 == ~E_7~0); {24926#false} is VALID [2022-02-21 04:24:31,821 INFO L290 TraceCheckUtils]: 40: Hoare triple {24926#false} assume !(0 == ~E_8~0); {24926#false} is VALID [2022-02-21 04:24:31,822 INFO L290 TraceCheckUtils]: 41: Hoare triple {24926#false} assume !(0 == ~E_9~0); {24926#false} is VALID [2022-02-21 04:24:31,822 INFO L290 TraceCheckUtils]: 42: Hoare triple {24926#false} assume !(0 == ~E_10~0); {24926#false} is VALID [2022-02-21 04:24:31,822 INFO L290 TraceCheckUtils]: 43: Hoare triple {24926#false} assume 0 == ~E_11~0;~E_11~0 := 1; {24926#false} is VALID [2022-02-21 04:24:31,822 INFO L290 TraceCheckUtils]: 44: Hoare triple {24926#false} assume !(0 == ~E_12~0); {24926#false} is VALID [2022-02-21 04:24:31,822 INFO L290 TraceCheckUtils]: 45: Hoare triple {24926#false} assume !(0 == ~E_13~0); {24926#false} is VALID [2022-02-21 04:24:31,822 INFO L290 TraceCheckUtils]: 46: Hoare triple {24926#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24926#false} is VALID [2022-02-21 04:24:31,822 INFO L290 TraceCheckUtils]: 47: Hoare triple {24926#false} assume 1 == ~m_pc~0; {24926#false} is VALID [2022-02-21 04:24:31,823 INFO L290 TraceCheckUtils]: 48: Hoare triple {24926#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {24926#false} is VALID [2022-02-21 04:24:31,823 INFO L290 TraceCheckUtils]: 49: Hoare triple {24926#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24926#false} is VALID [2022-02-21 04:24:31,823 INFO L290 TraceCheckUtils]: 50: Hoare triple {24926#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24926#false} is VALID [2022-02-21 04:24:31,823 INFO L290 TraceCheckUtils]: 51: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp~1#1); {24926#false} is VALID [2022-02-21 04:24:31,823 INFO L290 TraceCheckUtils]: 52: Hoare triple {24926#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24926#false} is VALID [2022-02-21 04:24:31,823 INFO L290 TraceCheckUtils]: 53: Hoare triple {24926#false} assume !(1 == ~t1_pc~0); {24926#false} is VALID [2022-02-21 04:24:31,824 INFO L290 TraceCheckUtils]: 54: Hoare triple {24926#false} is_transmit1_triggered_~__retres1~1#1 := 0; {24926#false} is VALID [2022-02-21 04:24:31,824 INFO L290 TraceCheckUtils]: 55: Hoare triple {24926#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24926#false} is VALID [2022-02-21 04:24:31,824 INFO L290 TraceCheckUtils]: 56: Hoare triple {24926#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24926#false} is VALID [2022-02-21 04:24:31,824 INFO L290 TraceCheckUtils]: 57: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp___0~0#1); {24926#false} is VALID [2022-02-21 04:24:31,825 INFO L290 TraceCheckUtils]: 58: Hoare triple {24926#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24926#false} is VALID [2022-02-21 04:24:31,825 INFO L290 TraceCheckUtils]: 59: Hoare triple {24926#false} assume 1 == ~t2_pc~0; {24926#false} is VALID [2022-02-21 04:24:31,825 INFO L290 TraceCheckUtils]: 60: Hoare triple {24926#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {24926#false} is VALID [2022-02-21 04:24:31,825 INFO L290 TraceCheckUtils]: 61: Hoare triple {24926#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24926#false} is VALID [2022-02-21 04:24:31,826 INFO L290 TraceCheckUtils]: 62: Hoare triple {24926#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24926#false} is VALID [2022-02-21 04:24:31,826 INFO L290 TraceCheckUtils]: 63: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp___1~0#1); {24926#false} is VALID [2022-02-21 04:24:31,826 INFO L290 TraceCheckUtils]: 64: Hoare triple {24926#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24926#false} is VALID [2022-02-21 04:24:31,826 INFO L290 TraceCheckUtils]: 65: Hoare triple {24926#false} assume 1 == ~t3_pc~0; {24926#false} is VALID [2022-02-21 04:24:31,826 INFO L290 TraceCheckUtils]: 66: Hoare triple {24926#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {24926#false} is VALID [2022-02-21 04:24:31,826 INFO L290 TraceCheckUtils]: 67: Hoare triple {24926#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24926#false} is VALID [2022-02-21 04:24:31,826 INFO L290 TraceCheckUtils]: 68: Hoare triple {24926#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {24926#false} is VALID [2022-02-21 04:24:31,827 INFO L290 TraceCheckUtils]: 69: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp___2~0#1); {24926#false} is VALID [2022-02-21 04:24:31,827 INFO L290 TraceCheckUtils]: 70: Hoare triple {24926#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24926#false} is VALID [2022-02-21 04:24:31,827 INFO L290 TraceCheckUtils]: 71: Hoare triple {24926#false} assume !(1 == ~t4_pc~0); {24926#false} is VALID [2022-02-21 04:24:31,827 INFO L290 TraceCheckUtils]: 72: Hoare triple {24926#false} is_transmit4_triggered_~__retres1~4#1 := 0; {24926#false} is VALID [2022-02-21 04:24:31,827 INFO L290 TraceCheckUtils]: 73: Hoare triple {24926#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24926#false} is VALID [2022-02-21 04:24:31,827 INFO L290 TraceCheckUtils]: 74: Hoare triple {24926#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {24926#false} is VALID [2022-02-21 04:24:31,827 INFO L290 TraceCheckUtils]: 75: Hoare triple {24926#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {24926#false} is VALID [2022-02-21 04:24:31,828 INFO L290 TraceCheckUtils]: 76: Hoare triple {24926#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24926#false} is VALID [2022-02-21 04:24:31,828 INFO L290 TraceCheckUtils]: 77: Hoare triple {24926#false} assume 1 == ~t5_pc~0; {24926#false} is VALID [2022-02-21 04:24:31,828 INFO L290 TraceCheckUtils]: 78: Hoare triple {24926#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {24926#false} is VALID [2022-02-21 04:24:31,828 INFO L290 TraceCheckUtils]: 79: Hoare triple {24926#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24926#false} is VALID [2022-02-21 04:24:31,828 INFO L290 TraceCheckUtils]: 80: Hoare triple {24926#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {24926#false} is VALID [2022-02-21 04:24:31,828 INFO L290 TraceCheckUtils]: 81: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp___4~0#1); {24926#false} is VALID [2022-02-21 04:24:31,828 INFO L290 TraceCheckUtils]: 82: Hoare triple {24926#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24926#false} is VALID [2022-02-21 04:24:31,829 INFO L290 TraceCheckUtils]: 83: Hoare triple {24926#false} assume !(1 == ~t6_pc~0); {24926#false} is VALID [2022-02-21 04:24:31,829 INFO L290 TraceCheckUtils]: 84: Hoare triple {24926#false} is_transmit6_triggered_~__retres1~6#1 := 0; {24926#false} is VALID [2022-02-21 04:24:31,829 INFO L290 TraceCheckUtils]: 85: Hoare triple {24926#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24926#false} is VALID [2022-02-21 04:24:31,829 INFO L290 TraceCheckUtils]: 86: Hoare triple {24926#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {24926#false} is VALID [2022-02-21 04:24:31,829 INFO L290 TraceCheckUtils]: 87: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp___5~0#1); {24926#false} is VALID [2022-02-21 04:24:31,829 INFO L290 TraceCheckUtils]: 88: Hoare triple {24926#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24926#false} is VALID [2022-02-21 04:24:31,829 INFO L290 TraceCheckUtils]: 89: Hoare triple {24926#false} assume 1 == ~t7_pc~0; {24926#false} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 90: Hoare triple {24926#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {24926#false} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 91: Hoare triple {24926#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24926#false} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 92: Hoare triple {24926#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {24926#false} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 93: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp___6~0#1); {24926#false} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 94: Hoare triple {24926#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {24926#false} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 95: Hoare triple {24926#false} assume !(1 == ~t8_pc~0); {24926#false} is VALID [2022-02-21 04:24:31,830 INFO L290 TraceCheckUtils]: 96: Hoare triple {24926#false} is_transmit8_triggered_~__retres1~8#1 := 0; {24926#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 97: Hoare triple {24926#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {24926#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 98: Hoare triple {24926#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {24926#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 99: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp___7~0#1); {24926#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 100: Hoare triple {24926#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {24926#false} is VALID [2022-02-21 04:24:31,831 INFO L290 TraceCheckUtils]: 101: Hoare triple {24926#false} assume 1 == ~t9_pc~0; {24926#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 102: Hoare triple {24926#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {24926#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 103: Hoare triple {24926#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {24926#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 104: Hoare triple {24926#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {24926#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 105: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp___8~0#1); {24926#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 106: Hoare triple {24926#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {24926#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 107: Hoare triple {24926#false} assume !(1 == ~t10_pc~0); {24926#false} is VALID [2022-02-21 04:24:31,833 INFO L290 TraceCheckUtils]: 108: Hoare triple {24926#false} is_transmit10_triggered_~__retres1~10#1 := 0; {24926#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 109: Hoare triple {24926#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {24926#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 110: Hoare triple {24926#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {24926#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 111: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp___9~0#1); {24926#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 112: Hoare triple {24926#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {24926#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 113: Hoare triple {24926#false} assume 1 == ~t11_pc~0; {24926#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 114: Hoare triple {24926#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {24926#false} is VALID [2022-02-21 04:24:31,834 INFO L290 TraceCheckUtils]: 115: Hoare triple {24926#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {24926#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 116: Hoare triple {24926#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {24926#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 117: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp___10~0#1); {24926#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 118: Hoare triple {24926#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {24926#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 119: Hoare triple {24926#false} assume 1 == ~t12_pc~0; {24926#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 120: Hoare triple {24926#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {24926#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 121: Hoare triple {24926#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {24926#false} is VALID [2022-02-21 04:24:31,835 INFO L290 TraceCheckUtils]: 122: Hoare triple {24926#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {24926#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 123: Hoare triple {24926#false} assume !(0 != activate_threads_~tmp___11~0#1); {24926#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 124: Hoare triple {24926#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {24926#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 125: Hoare triple {24926#false} assume !(1 == ~t13_pc~0); {24926#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 126: Hoare triple {24926#false} is_transmit13_triggered_~__retres1~13#1 := 0; {24926#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 127: Hoare triple {24926#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {24926#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 128: Hoare triple {24926#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {24926#false} is VALID [2022-02-21 04:24:31,836 INFO L290 TraceCheckUtils]: 129: Hoare triple {24926#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {24926#false} is VALID [2022-02-21 04:24:31,837 INFO L290 TraceCheckUtils]: 130: Hoare triple {24926#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24926#false} is VALID [2022-02-21 04:24:31,837 INFO L290 TraceCheckUtils]: 131: Hoare triple {24926#false} assume !(1 == ~M_E~0); {24926#false} is VALID [2022-02-21 04:24:31,837 INFO L290 TraceCheckUtils]: 132: Hoare triple {24926#false} assume !(1 == ~T1_E~0); {24926#false} is VALID [2022-02-21 04:24:31,837 INFO L290 TraceCheckUtils]: 133: Hoare triple {24926#false} assume !(1 == ~T2_E~0); {24926#false} is VALID [2022-02-21 04:24:31,837 INFO L290 TraceCheckUtils]: 134: Hoare triple {24926#false} assume !(1 == ~T3_E~0); {24926#false} is VALID [2022-02-21 04:24:31,837 INFO L290 TraceCheckUtils]: 135: Hoare triple {24926#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,837 INFO L290 TraceCheckUtils]: 136: Hoare triple {24926#false} assume !(1 == ~T5_E~0); {24926#false} is VALID [2022-02-21 04:24:31,838 INFO L290 TraceCheckUtils]: 137: Hoare triple {24926#false} assume !(1 == ~T6_E~0); {24926#false} is VALID [2022-02-21 04:24:31,838 INFO L290 TraceCheckUtils]: 138: Hoare triple {24926#false} assume !(1 == ~T7_E~0); {24926#false} is VALID [2022-02-21 04:24:31,838 INFO L290 TraceCheckUtils]: 139: Hoare triple {24926#false} assume !(1 == ~T8_E~0); {24926#false} is VALID [2022-02-21 04:24:31,838 INFO L290 TraceCheckUtils]: 140: Hoare triple {24926#false} assume !(1 == ~T9_E~0); {24926#false} is VALID [2022-02-21 04:24:31,838 INFO L290 TraceCheckUtils]: 141: Hoare triple {24926#false} assume !(1 == ~T10_E~0); {24926#false} is VALID [2022-02-21 04:24:31,838 INFO L290 TraceCheckUtils]: 142: Hoare triple {24926#false} assume !(1 == ~T11_E~0); {24926#false} is VALID [2022-02-21 04:24:31,838 INFO L290 TraceCheckUtils]: 143: Hoare triple {24926#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,839 INFO L290 TraceCheckUtils]: 144: Hoare triple {24926#false} assume !(1 == ~T13_E~0); {24926#false} is VALID [2022-02-21 04:24:31,839 INFO L290 TraceCheckUtils]: 145: Hoare triple {24926#false} assume !(1 == ~E_1~0); {24926#false} is VALID [2022-02-21 04:24:31,839 INFO L290 TraceCheckUtils]: 146: Hoare triple {24926#false} assume !(1 == ~E_2~0); {24926#false} is VALID [2022-02-21 04:24:31,839 INFO L290 TraceCheckUtils]: 147: Hoare triple {24926#false} assume !(1 == ~E_3~0); {24926#false} is VALID [2022-02-21 04:24:31,839 INFO L290 TraceCheckUtils]: 148: Hoare triple {24926#false} assume !(1 == ~E_4~0); {24926#false} is VALID [2022-02-21 04:24:31,839 INFO L290 TraceCheckUtils]: 149: Hoare triple {24926#false} assume !(1 == ~E_5~0); {24926#false} is VALID [2022-02-21 04:24:31,839 INFO L290 TraceCheckUtils]: 150: Hoare triple {24926#false} assume !(1 == ~E_6~0); {24926#false} is VALID [2022-02-21 04:24:31,840 INFO L290 TraceCheckUtils]: 151: Hoare triple {24926#false} assume 1 == ~E_7~0;~E_7~0 := 2; {24926#false} is VALID [2022-02-21 04:24:31,840 INFO L290 TraceCheckUtils]: 152: Hoare triple {24926#false} assume !(1 == ~E_8~0); {24926#false} is VALID [2022-02-21 04:24:31,840 INFO L290 TraceCheckUtils]: 153: Hoare triple {24926#false} assume !(1 == ~E_9~0); {24926#false} is VALID [2022-02-21 04:24:31,840 INFO L290 TraceCheckUtils]: 154: Hoare triple {24926#false} assume !(1 == ~E_10~0); {24926#false} is VALID [2022-02-21 04:24:31,840 INFO L290 TraceCheckUtils]: 155: Hoare triple {24926#false} assume !(1 == ~E_11~0); {24926#false} is VALID [2022-02-21 04:24:31,840 INFO L290 TraceCheckUtils]: 156: Hoare triple {24926#false} assume !(1 == ~E_12~0); {24926#false} is VALID [2022-02-21 04:24:31,840 INFO L290 TraceCheckUtils]: 157: Hoare triple {24926#false} assume !(1 == ~E_13~0); {24926#false} is VALID [2022-02-21 04:24:31,841 INFO L290 TraceCheckUtils]: 158: Hoare triple {24926#false} assume { :end_inline_reset_delta_events } true; {24926#false} is VALID [2022-02-21 04:24:31,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:31,841 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:31,841 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [952040436] [2022-02-21 04:24:31,842 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [952040436] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:31,842 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:31,842 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:31,843 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336968673] [2022-02-21 04:24:31,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:31,843 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:31,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:31,844 INFO L85 PathProgramCache]: Analyzing trace with hash 1867815776, now seen corresponding path program 1 times [2022-02-21 04:24:31,844 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:31,847 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346874902] [2022-02-21 04:24:31,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:31,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:31,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:31,920 INFO L290 TraceCheckUtils]: 0: Hoare triple {24928#true} assume !false; {24928#true} is VALID [2022-02-21 04:24:31,921 INFO L290 TraceCheckUtils]: 1: Hoare triple {24928#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {24928#true} is VALID [2022-02-21 04:24:31,921 INFO L290 TraceCheckUtils]: 2: Hoare triple {24928#true} assume !false; {24928#true} is VALID [2022-02-21 04:24:31,921 INFO L290 TraceCheckUtils]: 3: Hoare triple {24928#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {24928#true} is VALID [2022-02-21 04:24:31,921 INFO L290 TraceCheckUtils]: 4: Hoare triple {24928#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {24928#true} is VALID [2022-02-21 04:24:31,921 INFO L290 TraceCheckUtils]: 5: Hoare triple {24928#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {24928#true} is VALID [2022-02-21 04:24:31,922 INFO L290 TraceCheckUtils]: 6: Hoare triple {24928#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {24928#true} is VALID [2022-02-21 04:24:31,922 INFO L290 TraceCheckUtils]: 7: Hoare triple {24928#true} assume !(0 != eval_~tmp~0#1); {24928#true} is VALID [2022-02-21 04:24:31,922 INFO L290 TraceCheckUtils]: 8: Hoare triple {24928#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {24928#true} is VALID [2022-02-21 04:24:31,922 INFO L290 TraceCheckUtils]: 9: Hoare triple {24928#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {24928#true} is VALID [2022-02-21 04:24:31,922 INFO L290 TraceCheckUtils]: 10: Hoare triple {24928#true} assume 0 == ~M_E~0;~M_E~0 := 1; {24928#true} is VALID [2022-02-21 04:24:31,922 INFO L290 TraceCheckUtils]: 11: Hoare triple {24928#true} assume !(0 == ~T1_E~0); {24928#true} is VALID [2022-02-21 04:24:31,922 INFO L290 TraceCheckUtils]: 12: Hoare triple {24928#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {24928#true} is VALID [2022-02-21 04:24:31,923 INFO L290 TraceCheckUtils]: 13: Hoare triple {24928#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {24928#true} is VALID [2022-02-21 04:24:31,923 INFO L290 TraceCheckUtils]: 14: Hoare triple {24928#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {24928#true} is VALID [2022-02-21 04:24:31,923 INFO L290 TraceCheckUtils]: 15: Hoare triple {24928#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,924 INFO L290 TraceCheckUtils]: 16: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,924 INFO L290 TraceCheckUtils]: 17: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,924 INFO L290 TraceCheckUtils]: 18: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,925 INFO L290 TraceCheckUtils]: 19: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,925 INFO L290 TraceCheckUtils]: 20: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,926 INFO L290 TraceCheckUtils]: 21: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,926 INFO L290 TraceCheckUtils]: 22: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,926 INFO L290 TraceCheckUtils]: 23: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,927 INFO L290 TraceCheckUtils]: 24: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,927 INFO L290 TraceCheckUtils]: 25: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,928 INFO L290 TraceCheckUtils]: 26: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,928 INFO L290 TraceCheckUtils]: 27: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,928 INFO L290 TraceCheckUtils]: 28: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,929 INFO L290 TraceCheckUtils]: 29: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,929 INFO L290 TraceCheckUtils]: 30: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,930 INFO L290 TraceCheckUtils]: 31: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,930 INFO L290 TraceCheckUtils]: 32: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,930 INFO L290 TraceCheckUtils]: 33: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,931 INFO L290 TraceCheckUtils]: 34: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,931 INFO L290 TraceCheckUtils]: 35: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,931 INFO L290 TraceCheckUtils]: 36: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,932 INFO L290 TraceCheckUtils]: 37: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,932 INFO L290 TraceCheckUtils]: 38: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,933 INFO L290 TraceCheckUtils]: 39: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,933 INFO L290 TraceCheckUtils]: 40: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,933 INFO L290 TraceCheckUtils]: 41: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,934 INFO L290 TraceCheckUtils]: 42: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,934 INFO L290 TraceCheckUtils]: 43: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,935 INFO L290 TraceCheckUtils]: 44: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,935 INFO L290 TraceCheckUtils]: 45: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,935 INFO L290 TraceCheckUtils]: 46: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,936 INFO L290 TraceCheckUtils]: 47: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,936 INFO L290 TraceCheckUtils]: 48: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,937 INFO L290 TraceCheckUtils]: 49: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,937 INFO L290 TraceCheckUtils]: 50: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,937 INFO L290 TraceCheckUtils]: 51: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,938 INFO L290 TraceCheckUtils]: 52: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,938 INFO L290 TraceCheckUtils]: 53: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,939 INFO L290 TraceCheckUtils]: 54: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,939 INFO L290 TraceCheckUtils]: 55: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,939 INFO L290 TraceCheckUtils]: 56: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,940 INFO L290 TraceCheckUtils]: 57: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,940 INFO L290 TraceCheckUtils]: 58: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,941 INFO L290 TraceCheckUtils]: 59: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,941 INFO L290 TraceCheckUtils]: 60: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,941 INFO L290 TraceCheckUtils]: 61: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,942 INFO L290 TraceCheckUtils]: 62: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,942 INFO L290 TraceCheckUtils]: 63: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,942 INFO L290 TraceCheckUtils]: 64: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,943 INFO L290 TraceCheckUtils]: 65: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,943 INFO L290 TraceCheckUtils]: 66: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,944 INFO L290 TraceCheckUtils]: 67: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,944 INFO L290 TraceCheckUtils]: 68: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,944 INFO L290 TraceCheckUtils]: 69: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,945 INFO L290 TraceCheckUtils]: 70: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,945 INFO L290 TraceCheckUtils]: 71: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,946 INFO L290 TraceCheckUtils]: 72: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,946 INFO L290 TraceCheckUtils]: 73: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,946 INFO L290 TraceCheckUtils]: 74: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,947 INFO L290 TraceCheckUtils]: 75: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,947 INFO L290 TraceCheckUtils]: 76: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,948 INFO L290 TraceCheckUtils]: 77: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,948 INFO L290 TraceCheckUtils]: 78: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,948 INFO L290 TraceCheckUtils]: 79: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,949 INFO L290 TraceCheckUtils]: 80: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,949 INFO L290 TraceCheckUtils]: 81: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,950 INFO L290 TraceCheckUtils]: 82: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,950 INFO L290 TraceCheckUtils]: 83: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,950 INFO L290 TraceCheckUtils]: 84: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,951 INFO L290 TraceCheckUtils]: 85: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,951 INFO L290 TraceCheckUtils]: 86: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,952 INFO L290 TraceCheckUtils]: 87: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,952 INFO L290 TraceCheckUtils]: 88: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,952 INFO L290 TraceCheckUtils]: 89: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,953 INFO L290 TraceCheckUtils]: 90: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,953 INFO L290 TraceCheckUtils]: 91: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,954 INFO L290 TraceCheckUtils]: 92: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,954 INFO L290 TraceCheckUtils]: 93: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,954 INFO L290 TraceCheckUtils]: 94: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,955 INFO L290 TraceCheckUtils]: 95: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,955 INFO L290 TraceCheckUtils]: 96: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,956 INFO L290 TraceCheckUtils]: 97: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,956 INFO L290 TraceCheckUtils]: 98: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,956 INFO L290 TraceCheckUtils]: 99: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,957 INFO L290 TraceCheckUtils]: 100: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,957 INFO L290 TraceCheckUtils]: 101: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,958 INFO L290 TraceCheckUtils]: 102: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,958 INFO L290 TraceCheckUtils]: 103: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,958 INFO L290 TraceCheckUtils]: 104: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,959 INFO L290 TraceCheckUtils]: 105: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,959 INFO L290 TraceCheckUtils]: 106: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,960 INFO L290 TraceCheckUtils]: 107: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,960 INFO L290 TraceCheckUtils]: 108: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,960 INFO L290 TraceCheckUtils]: 109: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,961 INFO L290 TraceCheckUtils]: 110: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t12_pc~0); {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,961 INFO L290 TraceCheckUtils]: 111: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,962 INFO L290 TraceCheckUtils]: 112: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,962 INFO L290 TraceCheckUtils]: 113: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,962 INFO L290 TraceCheckUtils]: 114: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,963 INFO L290 TraceCheckUtils]: 115: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,963 INFO L290 TraceCheckUtils]: 116: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,964 INFO L290 TraceCheckUtils]: 117: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,964 INFO L290 TraceCheckUtils]: 118: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,964 INFO L290 TraceCheckUtils]: 119: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,969 INFO L290 TraceCheckUtils]: 120: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,969 INFO L290 TraceCheckUtils]: 121: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,970 INFO L290 TraceCheckUtils]: 122: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,970 INFO L290 TraceCheckUtils]: 123: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,970 INFO L290 TraceCheckUtils]: 124: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,971 INFO L290 TraceCheckUtils]: 125: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,971 INFO L290 TraceCheckUtils]: 126: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {24930#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:31,972 INFO L290 TraceCheckUtils]: 127: Hoare triple {24930#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {24929#false} is VALID [2022-02-21 04:24:31,972 INFO L290 TraceCheckUtils]: 128: Hoare triple {24929#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,972 INFO L290 TraceCheckUtils]: 129: Hoare triple {24929#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,972 INFO L290 TraceCheckUtils]: 130: Hoare triple {24929#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,972 INFO L290 TraceCheckUtils]: 131: Hoare triple {24929#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,972 INFO L290 TraceCheckUtils]: 132: Hoare triple {24929#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,973 INFO L290 TraceCheckUtils]: 133: Hoare triple {24929#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,973 INFO L290 TraceCheckUtils]: 134: Hoare triple {24929#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,973 INFO L290 TraceCheckUtils]: 135: Hoare triple {24929#false} assume !(1 == ~T13_E~0); {24929#false} is VALID [2022-02-21 04:24:31,973 INFO L290 TraceCheckUtils]: 136: Hoare triple {24929#false} assume 1 == ~E_1~0;~E_1~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,973 INFO L290 TraceCheckUtils]: 137: Hoare triple {24929#false} assume 1 == ~E_2~0;~E_2~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,973 INFO L290 TraceCheckUtils]: 138: Hoare triple {24929#false} assume 1 == ~E_3~0;~E_3~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,973 INFO L290 TraceCheckUtils]: 139: Hoare triple {24929#false} assume 1 == ~E_4~0;~E_4~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,973 INFO L290 TraceCheckUtils]: 140: Hoare triple {24929#false} assume 1 == ~E_5~0;~E_5~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,974 INFO L290 TraceCheckUtils]: 141: Hoare triple {24929#false} assume 1 == ~E_6~0;~E_6~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,974 INFO L290 TraceCheckUtils]: 142: Hoare triple {24929#false} assume 1 == ~E_7~0;~E_7~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,974 INFO L290 TraceCheckUtils]: 143: Hoare triple {24929#false} assume !(1 == ~E_8~0); {24929#false} is VALID [2022-02-21 04:24:31,974 INFO L290 TraceCheckUtils]: 144: Hoare triple {24929#false} assume 1 == ~E_9~0;~E_9~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,974 INFO L290 TraceCheckUtils]: 145: Hoare triple {24929#false} assume 1 == ~E_10~0;~E_10~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,974 INFO L290 TraceCheckUtils]: 146: Hoare triple {24929#false} assume 1 == ~E_11~0;~E_11~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,975 INFO L290 TraceCheckUtils]: 147: Hoare triple {24929#false} assume 1 == ~E_12~0;~E_12~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,975 INFO L290 TraceCheckUtils]: 148: Hoare triple {24929#false} assume 1 == ~E_13~0;~E_13~0 := 2; {24929#false} is VALID [2022-02-21 04:24:31,975 INFO L290 TraceCheckUtils]: 149: Hoare triple {24929#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {24929#false} is VALID [2022-02-21 04:24:31,975 INFO L290 TraceCheckUtils]: 150: Hoare triple {24929#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {24929#false} is VALID [2022-02-21 04:24:31,975 INFO L290 TraceCheckUtils]: 151: Hoare triple {24929#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {24929#false} is VALID [2022-02-21 04:24:31,975 INFO L290 TraceCheckUtils]: 152: Hoare triple {24929#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {24929#false} is VALID [2022-02-21 04:24:31,975 INFO L290 TraceCheckUtils]: 153: Hoare triple {24929#false} assume !(0 == start_simulation_~tmp~3#1); {24929#false} is VALID [2022-02-21 04:24:31,976 INFO L290 TraceCheckUtils]: 154: Hoare triple {24929#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {24929#false} is VALID [2022-02-21 04:24:31,976 INFO L290 TraceCheckUtils]: 155: Hoare triple {24929#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {24929#false} is VALID [2022-02-21 04:24:31,976 INFO L290 TraceCheckUtils]: 156: Hoare triple {24929#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {24929#false} is VALID [2022-02-21 04:24:31,976 INFO L290 TraceCheckUtils]: 157: Hoare triple {24929#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {24929#false} is VALID [2022-02-21 04:24:31,976 INFO L290 TraceCheckUtils]: 158: Hoare triple {24929#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {24929#false} is VALID [2022-02-21 04:24:31,976 INFO L290 TraceCheckUtils]: 159: Hoare triple {24929#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {24929#false} is VALID [2022-02-21 04:24:31,976 INFO L290 TraceCheckUtils]: 160: Hoare triple {24929#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {24929#false} is VALID [2022-02-21 04:24:31,977 INFO L290 TraceCheckUtils]: 161: Hoare triple {24929#false} assume !(0 != start_simulation_~tmp___0~1#1); {24929#false} is VALID [2022-02-21 04:24:31,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:31,978 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:31,978 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1346874902] [2022-02-21 04:24:31,978 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1346874902] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:31,978 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:31,978 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:31,979 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1346874199] [2022-02-21 04:24:31,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:31,979 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:31,979 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:31,980 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:31,980 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:31,980 INFO L87 Difference]: Start difference. First operand 1914 states and 2833 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:33,642 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2022-02-21 04:24:33,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:33,642 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,737 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:33,738 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:33,827 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:33,949 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-02-21 04:24:33,949 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:33,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:33,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:33,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:33,953 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-02-21 04:24:33,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:33,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:33,978 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:33,981 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2832 transitions. Second operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,983 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2832 transitions. Second operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:33,985 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. Second operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:34,094 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2022-02-21 04:24:34,094 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:34,097 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:34,097 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:34,100 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2832 transitions. [2022-02-21 04:24:34,103 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2832 transitions. [2022-02-21 04:24:34,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:34,229 INFO L93 Difference]: Finished difference Result 1914 states and 2832 transitions. [2022-02-21 04:24:34,229 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:34,231 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:34,231 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:34,231 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:34,231 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:34,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4796238244514106) internal successors, (2832), 1913 states have internal predecessors, (2832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:34,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2832 transitions. [2022-02-21 04:24:34,355 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-02-21 04:24:34,355 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2832 transitions. [2022-02-21 04:24:34,355 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:24:34,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2832 transitions. [2022-02-21 04:24:34,362 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:34,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:34,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:34,364 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:34,364 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:34,365 INFO L791 eck$LassoCheckResult]: Stem: 27706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 27526#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27242#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27243#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28419#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28420#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27378#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27379#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 27833#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 27668#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 27669#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27445#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27446#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27844#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28021#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28175#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28212#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27456#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27457#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28632#L1258-2 assume !(0 == ~T1_E~0); 27751#L1263-1 assume !(0 == ~T2_E~0); 27752#L1268-1 assume !(0 == ~T3_E~0); 28055#L1273-1 assume !(0 == ~T4_E~0); 28614#L1278-1 assume !(0 == ~T5_E~0); 28475#L1283-1 assume !(0 == ~T6_E~0); 28476#L1288-1 assume !(0 == ~T7_E~0); 28712#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28700#L1298-1 assume !(0 == ~T9_E~0); 28626#L1303-1 assume !(0 == ~T10_E~0); 27271#L1308-1 assume !(0 == ~T11_E~0); 27213#L1313-1 assume !(0 == ~T12_E~0); 27214#L1318-1 assume !(0 == ~T13_E~0); 27220#L1323-1 assume !(0 == ~E_1~0); 27221#L1328-1 assume !(0 == ~E_2~0); 27388#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 28347#L1338-1 assume !(0 == ~E_4~0); 28348#L1343-1 assume !(0 == ~E_5~0); 28449#L1348-1 assume !(0 == ~E_6~0); 28735#L1353-1 assume !(0 == ~E_7~0); 28074#L1358-1 assume !(0 == ~E_8~0); 28075#L1363-1 assume !(0 == ~E_9~0); 28365#L1368-1 assume !(0 == ~E_10~0); 27050#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 27051#L1378-1 assume !(0 == ~E_12~0); 27337#L1383-1 assume !(0 == ~E_13~0); 27338#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28081#L607 assume 1 == ~m_pc~0; 28082#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27408#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28447#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28001#L1560 assume !(0 != activate_threads_~tmp~1#1); 28002#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27233#L626 assume !(1 == ~t1_pc~0); 27234#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 27502#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27503#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27672#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 27133#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27134#L645 assume 1 == ~t2_pc~0; 27250#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27207#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27884#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27885#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 27977#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27978#L664 assume 1 == ~t3_pc~0; 28734#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26974#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26975#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27633#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 27634#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28642#L683 assume !(1 == ~t4_pc~0); 28197#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28149#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28150#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28184#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28308#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27927#L702 assume 1 == ~t5_pc~0; 27928#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27853#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28303#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28601#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 28542#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27022#L721 assume !(1 == ~t6_pc~0); 26996#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 26997#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27160#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27642#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 27643#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28244#L740 assume 1 == ~t7_pc~0; 27071#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26884#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26885#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26874#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 26875#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27578#L759 assume !(1 == ~t8_pc~0); 27579#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 27608#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28301#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28302#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 28433#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28711#L778 assume 1 == ~t9_pc~0; 28598#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27049#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26989#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26918#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 26919#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27246#L797 assume !(1 == ~t10_pc~0); 27247#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 27365#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28499#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27749#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 27750#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28039#L816 assume 1 == ~t11_pc~0; 26954#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26955#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27710#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27649#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 27650#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28174#L835 assume 1 == ~t12_pc~0; 28052#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27118#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27140#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27281#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 27806#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 27807#L854 assume !(1 == ~t13_pc~0); 27447#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 27448#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27498#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27158#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27159#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28538#L1401 assume !(1 == ~M_E~0); 27637#L1401-2 assume !(1 == ~T1_E~0); 27638#L1406-1 assume !(1 == ~T2_E~0); 28233#L1411-1 assume !(1 == ~T3_E~0); 28234#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27900#L1421-1 assume !(1 == ~T5_E~0); 27443#L1426-1 assume !(1 == ~T6_E~0); 27444#L1431-1 assume !(1 == ~T7_E~0); 26992#L1436-1 assume !(1 == ~T8_E~0); 26993#L1441-1 assume !(1 == ~T9_E~0); 27740#L1446-1 assume !(1 == ~T10_E~0); 27741#L1451-1 assume !(1 == ~T11_E~0); 28446#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28100#L1461-1 assume !(1 == ~T13_E~0); 27661#L1466-1 assume !(1 == ~E_1~0); 27662#L1471-1 assume !(1 == ~E_2~0); 28431#L1476-1 assume !(1 == ~E_3~0); 28432#L1481-1 assume !(1 == ~E_4~0); 28580#L1486-1 assume !(1 == ~E_5~0); 27286#L1491-1 assume !(1 == ~E_6~0); 26926#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 26927#L1501-1 assume !(1 == ~E_8~0); 27738#L1506-1 assume !(1 == ~E_9~0); 27739#L1511-1 assume !(1 == ~E_10~0); 27695#L1516-1 assume !(1 == ~E_11~0); 26870#L1521-1 assume !(1 == ~E_12~0); 26871#L1526-1 assume !(1 == ~E_13~0); 26925#L1531-1 assume { :end_inline_reset_delta_events } true; 27468#L1892-2 [2022-02-21 04:24:34,365 INFO L793 eck$LassoCheckResult]: Loop: 27468#L1892-2 assume !false; 28491#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28689#L1233 assume !false; 28672#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28004#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27984#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28142#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 26968#L1046 assume !(0 != eval_~tmp~0#1); 26970#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27004#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28176#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28733#L1258-5 assume !(0 == ~T1_E~0); 27146#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27147#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28725#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28731#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28732#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27370#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27371#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28488#L1298-3 assume !(0 == ~T9_E~0); 28489#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28648#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28487#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 27988#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 27148#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27149#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28572#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27291#L1338-3 assume !(0 == ~E_4~0); 27292#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 28404#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28577#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28578#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27944#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27504#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27505#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28261#L1378-3 assume !(0 == ~E_12~0); 28262#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28443#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28444#L607-42 assume 1 == ~m_pc~0; 28057#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27785#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27786#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27518#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27519#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28040#L626-42 assume 1 == ~t1_pc~0; 27602#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27603#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27907#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27908#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27182#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27183#L645-42 assume 1 == ~t2_pc~0; 28641#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28383#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28548#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27389#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26896#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26897#L664-42 assume 1 == ~t3_pc~0; 27699#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27424#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28675#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28210#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28211#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28376#L683-42 assume !(1 == ~t4_pc~0); 28084#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 28085#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28217#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28637#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28638#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28482#L702-42 assume 1 == ~t5_pc~0; 27970#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27595#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27891#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28564#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26912#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26913#L721-42 assume 1 == ~t6_pc~0; 27066#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27086#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27550#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28717#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27722#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27568#L740-42 assume 1 == ~t7_pc~0; 27569#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27306#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27847#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27702#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 27703#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27976#L759-42 assume 1 == ~t8_pc~0; 27825#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27757#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27758#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27836#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27837#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27932#L778-42 assume 1 == ~t9_pc~0; 27769#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27771#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28181#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28086#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28087#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28144#L797-42 assume !(1 == ~t10_pc~0); 27313#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 27312#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28313#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28622#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28182#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28183#L816-42 assume 1 == ~t11_pc~0; 26860#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26861#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27403#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27404#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27483#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27484#L835-42 assume 1 == ~t12_pc~0; 27888#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27781#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27458#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27459#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28541#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28325#L854-42 assume 1 == ~t13_pc~0; 28326#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 27402#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 27012#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27013#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27659#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27660#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28438#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27249#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27113#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27114#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27713#L1421-3 assume !(1 == ~T5_E~0); 27714#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27289#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27290#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26876#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26877#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28466#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27797#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 27450#L1461-3 assume !(1 == ~T13_E~0); 27451#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28728#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27390#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27391#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27791#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27418#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27419#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27831#L1501-3 assume !(1 == ~E_8~0); 27832#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28258#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28248#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28249#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 27948#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 27949#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28343#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27225#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28118#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 27759#L1911 assume !(0 == start_simulation_~tmp~3#1); 27760#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28282#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 27349#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28220#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 27054#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27055#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27284#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 27285#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27468#L1892-2 [2022-02-21 04:24:34,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:34,366 INFO L85 PathProgramCache]: Analyzing trace with hash 1797695072, now seen corresponding path program 1 times [2022-02-21 04:24:34,366 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:34,366 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64840025] [2022-02-21 04:24:34,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:34,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:34,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:34,395 INFO L290 TraceCheckUtils]: 0: Hoare triple {32590#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {32590#true} is VALID [2022-02-21 04:24:34,396 INFO L290 TraceCheckUtils]: 1: Hoare triple {32590#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {32592#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:34,396 INFO L290 TraceCheckUtils]: 2: Hoare triple {32592#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {32592#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:34,396 INFO L290 TraceCheckUtils]: 3: Hoare triple {32592#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {32592#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:34,397 INFO L290 TraceCheckUtils]: 4: Hoare triple {32592#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {32592#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:34,397 INFO L290 TraceCheckUtils]: 5: Hoare triple {32592#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {32592#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:34,397 INFO L290 TraceCheckUtils]: 6: Hoare triple {32592#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {32592#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:34,398 INFO L290 TraceCheckUtils]: 7: Hoare triple {32592#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {32592#(= ~t4_i~0 1)} is VALID [2022-02-21 04:24:34,398 INFO L290 TraceCheckUtils]: 8: Hoare triple {32592#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,398 INFO L290 TraceCheckUtils]: 9: Hoare triple {32591#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,398 INFO L290 TraceCheckUtils]: 10: Hoare triple {32591#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,398 INFO L290 TraceCheckUtils]: 11: Hoare triple {32591#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,399 INFO L290 TraceCheckUtils]: 12: Hoare triple {32591#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,399 INFO L290 TraceCheckUtils]: 13: Hoare triple {32591#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {32591#false} is VALID [2022-02-21 04:24:34,399 INFO L290 TraceCheckUtils]: 14: Hoare triple {32591#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,399 INFO L290 TraceCheckUtils]: 15: Hoare triple {32591#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,399 INFO L290 TraceCheckUtils]: 16: Hoare triple {32591#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,399 INFO L290 TraceCheckUtils]: 17: Hoare triple {32591#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,399 INFO L290 TraceCheckUtils]: 18: Hoare triple {32591#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {32591#false} is VALID [2022-02-21 04:24:34,400 INFO L290 TraceCheckUtils]: 19: Hoare triple {32591#false} assume 0 == ~M_E~0;~M_E~0 := 1; {32591#false} is VALID [2022-02-21 04:24:34,400 INFO L290 TraceCheckUtils]: 20: Hoare triple {32591#false} assume !(0 == ~T1_E~0); {32591#false} is VALID [2022-02-21 04:24:34,400 INFO L290 TraceCheckUtils]: 21: Hoare triple {32591#false} assume !(0 == ~T2_E~0); {32591#false} is VALID [2022-02-21 04:24:34,400 INFO L290 TraceCheckUtils]: 22: Hoare triple {32591#false} assume !(0 == ~T3_E~0); {32591#false} is VALID [2022-02-21 04:24:34,400 INFO L290 TraceCheckUtils]: 23: Hoare triple {32591#false} assume !(0 == ~T4_E~0); {32591#false} is VALID [2022-02-21 04:24:34,400 INFO L290 TraceCheckUtils]: 24: Hoare triple {32591#false} assume !(0 == ~T5_E~0); {32591#false} is VALID [2022-02-21 04:24:34,400 INFO L290 TraceCheckUtils]: 25: Hoare triple {32591#false} assume !(0 == ~T6_E~0); {32591#false} is VALID [2022-02-21 04:24:34,401 INFO L290 TraceCheckUtils]: 26: Hoare triple {32591#false} assume !(0 == ~T7_E~0); {32591#false} is VALID [2022-02-21 04:24:34,401 INFO L290 TraceCheckUtils]: 27: Hoare triple {32591#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {32591#false} is VALID [2022-02-21 04:24:34,401 INFO L290 TraceCheckUtils]: 28: Hoare triple {32591#false} assume !(0 == ~T9_E~0); {32591#false} is VALID [2022-02-21 04:24:34,401 INFO L290 TraceCheckUtils]: 29: Hoare triple {32591#false} assume !(0 == ~T10_E~0); {32591#false} is VALID [2022-02-21 04:24:34,401 INFO L290 TraceCheckUtils]: 30: Hoare triple {32591#false} assume !(0 == ~T11_E~0); {32591#false} is VALID [2022-02-21 04:24:34,401 INFO L290 TraceCheckUtils]: 31: Hoare triple {32591#false} assume !(0 == ~T12_E~0); {32591#false} is VALID [2022-02-21 04:24:34,401 INFO L290 TraceCheckUtils]: 32: Hoare triple {32591#false} assume !(0 == ~T13_E~0); {32591#false} is VALID [2022-02-21 04:24:34,402 INFO L290 TraceCheckUtils]: 33: Hoare triple {32591#false} assume !(0 == ~E_1~0); {32591#false} is VALID [2022-02-21 04:24:34,402 INFO L290 TraceCheckUtils]: 34: Hoare triple {32591#false} assume !(0 == ~E_2~0); {32591#false} is VALID [2022-02-21 04:24:34,402 INFO L290 TraceCheckUtils]: 35: Hoare triple {32591#false} assume 0 == ~E_3~0;~E_3~0 := 1; {32591#false} is VALID [2022-02-21 04:24:34,402 INFO L290 TraceCheckUtils]: 36: Hoare triple {32591#false} assume !(0 == ~E_4~0); {32591#false} is VALID [2022-02-21 04:24:34,402 INFO L290 TraceCheckUtils]: 37: Hoare triple {32591#false} assume !(0 == ~E_5~0); {32591#false} is VALID [2022-02-21 04:24:34,402 INFO L290 TraceCheckUtils]: 38: Hoare triple {32591#false} assume !(0 == ~E_6~0); {32591#false} is VALID [2022-02-21 04:24:34,402 INFO L290 TraceCheckUtils]: 39: Hoare triple {32591#false} assume !(0 == ~E_7~0); {32591#false} is VALID [2022-02-21 04:24:34,403 INFO L290 TraceCheckUtils]: 40: Hoare triple {32591#false} assume !(0 == ~E_8~0); {32591#false} is VALID [2022-02-21 04:24:34,403 INFO L290 TraceCheckUtils]: 41: Hoare triple {32591#false} assume !(0 == ~E_9~0); {32591#false} is VALID [2022-02-21 04:24:34,403 INFO L290 TraceCheckUtils]: 42: Hoare triple {32591#false} assume !(0 == ~E_10~0); {32591#false} is VALID [2022-02-21 04:24:34,403 INFO L290 TraceCheckUtils]: 43: Hoare triple {32591#false} assume 0 == ~E_11~0;~E_11~0 := 1; {32591#false} is VALID [2022-02-21 04:24:34,403 INFO L290 TraceCheckUtils]: 44: Hoare triple {32591#false} assume !(0 == ~E_12~0); {32591#false} is VALID [2022-02-21 04:24:34,403 INFO L290 TraceCheckUtils]: 45: Hoare triple {32591#false} assume !(0 == ~E_13~0); {32591#false} is VALID [2022-02-21 04:24:34,403 INFO L290 TraceCheckUtils]: 46: Hoare triple {32591#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {32591#false} is VALID [2022-02-21 04:24:34,404 INFO L290 TraceCheckUtils]: 47: Hoare triple {32591#false} assume 1 == ~m_pc~0; {32591#false} is VALID [2022-02-21 04:24:34,404 INFO L290 TraceCheckUtils]: 48: Hoare triple {32591#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {32591#false} is VALID [2022-02-21 04:24:34,404 INFO L290 TraceCheckUtils]: 49: Hoare triple {32591#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {32591#false} is VALID [2022-02-21 04:24:34,404 INFO L290 TraceCheckUtils]: 50: Hoare triple {32591#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {32591#false} is VALID [2022-02-21 04:24:34,404 INFO L290 TraceCheckUtils]: 51: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp~1#1); {32591#false} is VALID [2022-02-21 04:24:34,404 INFO L290 TraceCheckUtils]: 52: Hoare triple {32591#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {32591#false} is VALID [2022-02-21 04:24:34,404 INFO L290 TraceCheckUtils]: 53: Hoare triple {32591#false} assume !(1 == ~t1_pc~0); {32591#false} is VALID [2022-02-21 04:24:34,404 INFO L290 TraceCheckUtils]: 54: Hoare triple {32591#false} is_transmit1_triggered_~__retres1~1#1 := 0; {32591#false} is VALID [2022-02-21 04:24:34,405 INFO L290 TraceCheckUtils]: 55: Hoare triple {32591#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {32591#false} is VALID [2022-02-21 04:24:34,405 INFO L290 TraceCheckUtils]: 56: Hoare triple {32591#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {32591#false} is VALID [2022-02-21 04:24:34,405 INFO L290 TraceCheckUtils]: 57: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp___0~0#1); {32591#false} is VALID [2022-02-21 04:24:34,405 INFO L290 TraceCheckUtils]: 58: Hoare triple {32591#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {32591#false} is VALID [2022-02-21 04:24:34,405 INFO L290 TraceCheckUtils]: 59: Hoare triple {32591#false} assume 1 == ~t2_pc~0; {32591#false} is VALID [2022-02-21 04:24:34,405 INFO L290 TraceCheckUtils]: 60: Hoare triple {32591#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {32591#false} is VALID [2022-02-21 04:24:34,405 INFO L290 TraceCheckUtils]: 61: Hoare triple {32591#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {32591#false} is VALID [2022-02-21 04:24:34,406 INFO L290 TraceCheckUtils]: 62: Hoare triple {32591#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {32591#false} is VALID [2022-02-21 04:24:34,406 INFO L290 TraceCheckUtils]: 63: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp___1~0#1); {32591#false} is VALID [2022-02-21 04:24:34,406 INFO L290 TraceCheckUtils]: 64: Hoare triple {32591#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {32591#false} is VALID [2022-02-21 04:24:34,406 INFO L290 TraceCheckUtils]: 65: Hoare triple {32591#false} assume 1 == ~t3_pc~0; {32591#false} is VALID [2022-02-21 04:24:34,406 INFO L290 TraceCheckUtils]: 66: Hoare triple {32591#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {32591#false} is VALID [2022-02-21 04:24:34,406 INFO L290 TraceCheckUtils]: 67: Hoare triple {32591#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {32591#false} is VALID [2022-02-21 04:24:34,406 INFO L290 TraceCheckUtils]: 68: Hoare triple {32591#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {32591#false} is VALID [2022-02-21 04:24:34,407 INFO L290 TraceCheckUtils]: 69: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp___2~0#1); {32591#false} is VALID [2022-02-21 04:24:34,407 INFO L290 TraceCheckUtils]: 70: Hoare triple {32591#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {32591#false} is VALID [2022-02-21 04:24:34,407 INFO L290 TraceCheckUtils]: 71: Hoare triple {32591#false} assume !(1 == ~t4_pc~0); {32591#false} is VALID [2022-02-21 04:24:34,407 INFO L290 TraceCheckUtils]: 72: Hoare triple {32591#false} is_transmit4_triggered_~__retres1~4#1 := 0; {32591#false} is VALID [2022-02-21 04:24:34,407 INFO L290 TraceCheckUtils]: 73: Hoare triple {32591#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {32591#false} is VALID [2022-02-21 04:24:34,407 INFO L290 TraceCheckUtils]: 74: Hoare triple {32591#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {32591#false} is VALID [2022-02-21 04:24:34,407 INFO L290 TraceCheckUtils]: 75: Hoare triple {32591#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {32591#false} is VALID [2022-02-21 04:24:34,408 INFO L290 TraceCheckUtils]: 76: Hoare triple {32591#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {32591#false} is VALID [2022-02-21 04:24:34,408 INFO L290 TraceCheckUtils]: 77: Hoare triple {32591#false} assume 1 == ~t5_pc~0; {32591#false} is VALID [2022-02-21 04:24:34,408 INFO L290 TraceCheckUtils]: 78: Hoare triple {32591#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {32591#false} is VALID [2022-02-21 04:24:34,408 INFO L290 TraceCheckUtils]: 79: Hoare triple {32591#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {32591#false} is VALID [2022-02-21 04:24:34,408 INFO L290 TraceCheckUtils]: 80: Hoare triple {32591#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {32591#false} is VALID [2022-02-21 04:24:34,408 INFO L290 TraceCheckUtils]: 81: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp___4~0#1); {32591#false} is VALID [2022-02-21 04:24:34,408 INFO L290 TraceCheckUtils]: 82: Hoare triple {32591#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {32591#false} is VALID [2022-02-21 04:24:34,409 INFO L290 TraceCheckUtils]: 83: Hoare triple {32591#false} assume !(1 == ~t6_pc~0); {32591#false} is VALID [2022-02-21 04:24:34,409 INFO L290 TraceCheckUtils]: 84: Hoare triple {32591#false} is_transmit6_triggered_~__retres1~6#1 := 0; {32591#false} is VALID [2022-02-21 04:24:34,409 INFO L290 TraceCheckUtils]: 85: Hoare triple {32591#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {32591#false} is VALID [2022-02-21 04:24:34,409 INFO L290 TraceCheckUtils]: 86: Hoare triple {32591#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {32591#false} is VALID [2022-02-21 04:24:34,409 INFO L290 TraceCheckUtils]: 87: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp___5~0#1); {32591#false} is VALID [2022-02-21 04:24:34,409 INFO L290 TraceCheckUtils]: 88: Hoare triple {32591#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {32591#false} is VALID [2022-02-21 04:24:34,409 INFO L290 TraceCheckUtils]: 89: Hoare triple {32591#false} assume 1 == ~t7_pc~0; {32591#false} is VALID [2022-02-21 04:24:34,410 INFO L290 TraceCheckUtils]: 90: Hoare triple {32591#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {32591#false} is VALID [2022-02-21 04:24:34,410 INFO L290 TraceCheckUtils]: 91: Hoare triple {32591#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {32591#false} is VALID [2022-02-21 04:24:34,410 INFO L290 TraceCheckUtils]: 92: Hoare triple {32591#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {32591#false} is VALID [2022-02-21 04:24:34,410 INFO L290 TraceCheckUtils]: 93: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp___6~0#1); {32591#false} is VALID [2022-02-21 04:24:34,410 INFO L290 TraceCheckUtils]: 94: Hoare triple {32591#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {32591#false} is VALID [2022-02-21 04:24:34,410 INFO L290 TraceCheckUtils]: 95: Hoare triple {32591#false} assume !(1 == ~t8_pc~0); {32591#false} is VALID [2022-02-21 04:24:34,410 INFO L290 TraceCheckUtils]: 96: Hoare triple {32591#false} is_transmit8_triggered_~__retres1~8#1 := 0; {32591#false} is VALID [2022-02-21 04:24:34,411 INFO L290 TraceCheckUtils]: 97: Hoare triple {32591#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {32591#false} is VALID [2022-02-21 04:24:34,411 INFO L290 TraceCheckUtils]: 98: Hoare triple {32591#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {32591#false} is VALID [2022-02-21 04:24:34,411 INFO L290 TraceCheckUtils]: 99: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp___7~0#1); {32591#false} is VALID [2022-02-21 04:24:34,411 INFO L290 TraceCheckUtils]: 100: Hoare triple {32591#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {32591#false} is VALID [2022-02-21 04:24:34,411 INFO L290 TraceCheckUtils]: 101: Hoare triple {32591#false} assume 1 == ~t9_pc~0; {32591#false} is VALID [2022-02-21 04:24:34,411 INFO L290 TraceCheckUtils]: 102: Hoare triple {32591#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {32591#false} is VALID [2022-02-21 04:24:34,411 INFO L290 TraceCheckUtils]: 103: Hoare triple {32591#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {32591#false} is VALID [2022-02-21 04:24:34,412 INFO L290 TraceCheckUtils]: 104: Hoare triple {32591#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {32591#false} is VALID [2022-02-21 04:24:34,412 INFO L290 TraceCheckUtils]: 105: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp___8~0#1); {32591#false} is VALID [2022-02-21 04:24:34,412 INFO L290 TraceCheckUtils]: 106: Hoare triple {32591#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {32591#false} is VALID [2022-02-21 04:24:34,412 INFO L290 TraceCheckUtils]: 107: Hoare triple {32591#false} assume !(1 == ~t10_pc~0); {32591#false} is VALID [2022-02-21 04:24:34,412 INFO L290 TraceCheckUtils]: 108: Hoare triple {32591#false} is_transmit10_triggered_~__retres1~10#1 := 0; {32591#false} is VALID [2022-02-21 04:24:34,412 INFO L290 TraceCheckUtils]: 109: Hoare triple {32591#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {32591#false} is VALID [2022-02-21 04:24:34,412 INFO L290 TraceCheckUtils]: 110: Hoare triple {32591#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {32591#false} is VALID [2022-02-21 04:24:34,412 INFO L290 TraceCheckUtils]: 111: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp___9~0#1); {32591#false} is VALID [2022-02-21 04:24:34,413 INFO L290 TraceCheckUtils]: 112: Hoare triple {32591#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {32591#false} is VALID [2022-02-21 04:24:34,413 INFO L290 TraceCheckUtils]: 113: Hoare triple {32591#false} assume 1 == ~t11_pc~0; {32591#false} is VALID [2022-02-21 04:24:34,413 INFO L290 TraceCheckUtils]: 114: Hoare triple {32591#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {32591#false} is VALID [2022-02-21 04:24:34,413 INFO L290 TraceCheckUtils]: 115: Hoare triple {32591#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {32591#false} is VALID [2022-02-21 04:24:34,413 INFO L290 TraceCheckUtils]: 116: Hoare triple {32591#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {32591#false} is VALID [2022-02-21 04:24:34,413 INFO L290 TraceCheckUtils]: 117: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp___10~0#1); {32591#false} is VALID [2022-02-21 04:24:34,413 INFO L290 TraceCheckUtils]: 118: Hoare triple {32591#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {32591#false} is VALID [2022-02-21 04:24:34,414 INFO L290 TraceCheckUtils]: 119: Hoare triple {32591#false} assume 1 == ~t12_pc~0; {32591#false} is VALID [2022-02-21 04:24:34,414 INFO L290 TraceCheckUtils]: 120: Hoare triple {32591#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {32591#false} is VALID [2022-02-21 04:24:34,414 INFO L290 TraceCheckUtils]: 121: Hoare triple {32591#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {32591#false} is VALID [2022-02-21 04:24:34,414 INFO L290 TraceCheckUtils]: 122: Hoare triple {32591#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {32591#false} is VALID [2022-02-21 04:24:34,414 INFO L290 TraceCheckUtils]: 123: Hoare triple {32591#false} assume !(0 != activate_threads_~tmp___11~0#1); {32591#false} is VALID [2022-02-21 04:24:34,414 INFO L290 TraceCheckUtils]: 124: Hoare triple {32591#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {32591#false} is VALID [2022-02-21 04:24:34,414 INFO L290 TraceCheckUtils]: 125: Hoare triple {32591#false} assume !(1 == ~t13_pc~0); {32591#false} is VALID [2022-02-21 04:24:34,415 INFO L290 TraceCheckUtils]: 126: Hoare triple {32591#false} is_transmit13_triggered_~__retres1~13#1 := 0; {32591#false} is VALID [2022-02-21 04:24:34,415 INFO L290 TraceCheckUtils]: 127: Hoare triple {32591#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {32591#false} is VALID [2022-02-21 04:24:34,415 INFO L290 TraceCheckUtils]: 128: Hoare triple {32591#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {32591#false} is VALID [2022-02-21 04:24:34,415 INFO L290 TraceCheckUtils]: 129: Hoare triple {32591#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {32591#false} is VALID [2022-02-21 04:24:34,415 INFO L290 TraceCheckUtils]: 130: Hoare triple {32591#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {32591#false} is VALID [2022-02-21 04:24:34,415 INFO L290 TraceCheckUtils]: 131: Hoare triple {32591#false} assume !(1 == ~M_E~0); {32591#false} is VALID [2022-02-21 04:24:34,415 INFO L290 TraceCheckUtils]: 132: Hoare triple {32591#false} assume !(1 == ~T1_E~0); {32591#false} is VALID [2022-02-21 04:24:34,416 INFO L290 TraceCheckUtils]: 133: Hoare triple {32591#false} assume !(1 == ~T2_E~0); {32591#false} is VALID [2022-02-21 04:24:34,416 INFO L290 TraceCheckUtils]: 134: Hoare triple {32591#false} assume !(1 == ~T3_E~0); {32591#false} is VALID [2022-02-21 04:24:34,416 INFO L290 TraceCheckUtils]: 135: Hoare triple {32591#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,416 INFO L290 TraceCheckUtils]: 136: Hoare triple {32591#false} assume !(1 == ~T5_E~0); {32591#false} is VALID [2022-02-21 04:24:34,416 INFO L290 TraceCheckUtils]: 137: Hoare triple {32591#false} assume !(1 == ~T6_E~0); {32591#false} is VALID [2022-02-21 04:24:34,416 INFO L290 TraceCheckUtils]: 138: Hoare triple {32591#false} assume !(1 == ~T7_E~0); {32591#false} is VALID [2022-02-21 04:24:34,416 INFO L290 TraceCheckUtils]: 139: Hoare triple {32591#false} assume !(1 == ~T8_E~0); {32591#false} is VALID [2022-02-21 04:24:34,417 INFO L290 TraceCheckUtils]: 140: Hoare triple {32591#false} assume !(1 == ~T9_E~0); {32591#false} is VALID [2022-02-21 04:24:34,417 INFO L290 TraceCheckUtils]: 141: Hoare triple {32591#false} assume !(1 == ~T10_E~0); {32591#false} is VALID [2022-02-21 04:24:34,417 INFO L290 TraceCheckUtils]: 142: Hoare triple {32591#false} assume !(1 == ~T11_E~0); {32591#false} is VALID [2022-02-21 04:24:34,417 INFO L290 TraceCheckUtils]: 143: Hoare triple {32591#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,417 INFO L290 TraceCheckUtils]: 144: Hoare triple {32591#false} assume !(1 == ~T13_E~0); {32591#false} is VALID [2022-02-21 04:24:34,417 INFO L290 TraceCheckUtils]: 145: Hoare triple {32591#false} assume !(1 == ~E_1~0); {32591#false} is VALID [2022-02-21 04:24:34,417 INFO L290 TraceCheckUtils]: 146: Hoare triple {32591#false} assume !(1 == ~E_2~0); {32591#false} is VALID [2022-02-21 04:24:34,418 INFO L290 TraceCheckUtils]: 147: Hoare triple {32591#false} assume !(1 == ~E_3~0); {32591#false} is VALID [2022-02-21 04:24:34,418 INFO L290 TraceCheckUtils]: 148: Hoare triple {32591#false} assume !(1 == ~E_4~0); {32591#false} is VALID [2022-02-21 04:24:34,418 INFO L290 TraceCheckUtils]: 149: Hoare triple {32591#false} assume !(1 == ~E_5~0); {32591#false} is VALID [2022-02-21 04:24:34,418 INFO L290 TraceCheckUtils]: 150: Hoare triple {32591#false} assume !(1 == ~E_6~0); {32591#false} is VALID [2022-02-21 04:24:34,418 INFO L290 TraceCheckUtils]: 151: Hoare triple {32591#false} assume 1 == ~E_7~0;~E_7~0 := 2; {32591#false} is VALID [2022-02-21 04:24:34,418 INFO L290 TraceCheckUtils]: 152: Hoare triple {32591#false} assume !(1 == ~E_8~0); {32591#false} is VALID [2022-02-21 04:24:34,418 INFO L290 TraceCheckUtils]: 153: Hoare triple {32591#false} assume !(1 == ~E_9~0); {32591#false} is VALID [2022-02-21 04:24:34,418 INFO L290 TraceCheckUtils]: 154: Hoare triple {32591#false} assume !(1 == ~E_10~0); {32591#false} is VALID [2022-02-21 04:24:34,419 INFO L290 TraceCheckUtils]: 155: Hoare triple {32591#false} assume !(1 == ~E_11~0); {32591#false} is VALID [2022-02-21 04:24:34,419 INFO L290 TraceCheckUtils]: 156: Hoare triple {32591#false} assume !(1 == ~E_12~0); {32591#false} is VALID [2022-02-21 04:24:34,419 INFO L290 TraceCheckUtils]: 157: Hoare triple {32591#false} assume !(1 == ~E_13~0); {32591#false} is VALID [2022-02-21 04:24:34,419 INFO L290 TraceCheckUtils]: 158: Hoare triple {32591#false} assume { :end_inline_reset_delta_events } true; {32591#false} is VALID [2022-02-21 04:24:34,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:34,420 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:34,420 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64840025] [2022-02-21 04:24:34,420 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [64840025] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:34,420 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:34,420 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:34,421 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812440712] [2022-02-21 04:24:34,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:34,421 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:34,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:34,422 INFO L85 PathProgramCache]: Analyzing trace with hash -1725583295, now seen corresponding path program 1 times [2022-02-21 04:24:34,422 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:34,422 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480805133] [2022-02-21 04:24:34,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:34,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:34,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:34,470 INFO L290 TraceCheckUtils]: 0: Hoare triple {32593#true} assume !false; {32593#true} is VALID [2022-02-21 04:24:34,470 INFO L290 TraceCheckUtils]: 1: Hoare triple {32593#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {32593#true} is VALID [2022-02-21 04:24:34,470 INFO L290 TraceCheckUtils]: 2: Hoare triple {32593#true} assume !false; {32593#true} is VALID [2022-02-21 04:24:34,470 INFO L290 TraceCheckUtils]: 3: Hoare triple {32593#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {32593#true} is VALID [2022-02-21 04:24:34,470 INFO L290 TraceCheckUtils]: 4: Hoare triple {32593#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {32593#true} is VALID [2022-02-21 04:24:34,470 INFO L290 TraceCheckUtils]: 5: Hoare triple {32593#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {32593#true} is VALID [2022-02-21 04:24:34,471 INFO L290 TraceCheckUtils]: 6: Hoare triple {32593#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {32593#true} is VALID [2022-02-21 04:24:34,471 INFO L290 TraceCheckUtils]: 7: Hoare triple {32593#true} assume !(0 != eval_~tmp~0#1); {32593#true} is VALID [2022-02-21 04:24:34,471 INFO L290 TraceCheckUtils]: 8: Hoare triple {32593#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {32593#true} is VALID [2022-02-21 04:24:34,471 INFO L290 TraceCheckUtils]: 9: Hoare triple {32593#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {32593#true} is VALID [2022-02-21 04:24:34,471 INFO L290 TraceCheckUtils]: 10: Hoare triple {32593#true} assume 0 == ~M_E~0;~M_E~0 := 1; {32593#true} is VALID [2022-02-21 04:24:34,471 INFO L290 TraceCheckUtils]: 11: Hoare triple {32593#true} assume !(0 == ~T1_E~0); {32593#true} is VALID [2022-02-21 04:24:34,483 INFO L290 TraceCheckUtils]: 12: Hoare triple {32593#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {32593#true} is VALID [2022-02-21 04:24:34,484 INFO L290 TraceCheckUtils]: 13: Hoare triple {32593#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {32593#true} is VALID [2022-02-21 04:24:34,484 INFO L290 TraceCheckUtils]: 14: Hoare triple {32593#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {32593#true} is VALID [2022-02-21 04:24:34,485 INFO L290 TraceCheckUtils]: 15: Hoare triple {32593#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,485 INFO L290 TraceCheckUtils]: 16: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,485 INFO L290 TraceCheckUtils]: 17: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,486 INFO L290 TraceCheckUtils]: 18: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,486 INFO L290 TraceCheckUtils]: 19: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,487 INFO L290 TraceCheckUtils]: 20: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,487 INFO L290 TraceCheckUtils]: 21: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,487 INFO L290 TraceCheckUtils]: 22: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,488 INFO L290 TraceCheckUtils]: 23: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,488 INFO L290 TraceCheckUtils]: 24: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,498 INFO L290 TraceCheckUtils]: 25: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,499 INFO L290 TraceCheckUtils]: 26: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,499 INFO L290 TraceCheckUtils]: 27: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,500 INFO L290 TraceCheckUtils]: 28: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,500 INFO L290 TraceCheckUtils]: 29: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,500 INFO L290 TraceCheckUtils]: 30: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,501 INFO L290 TraceCheckUtils]: 31: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,501 INFO L290 TraceCheckUtils]: 32: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,501 INFO L290 TraceCheckUtils]: 33: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,502 INFO L290 TraceCheckUtils]: 34: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,502 INFO L290 TraceCheckUtils]: 35: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,502 INFO L290 TraceCheckUtils]: 36: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,503 INFO L290 TraceCheckUtils]: 37: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,503 INFO L290 TraceCheckUtils]: 38: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,504 INFO L290 TraceCheckUtils]: 39: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,504 INFO L290 TraceCheckUtils]: 40: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,504 INFO L290 TraceCheckUtils]: 41: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,505 INFO L290 TraceCheckUtils]: 42: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,505 INFO L290 TraceCheckUtils]: 43: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,505 INFO L290 TraceCheckUtils]: 44: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,506 INFO L290 TraceCheckUtils]: 45: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,506 INFO L290 TraceCheckUtils]: 46: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,506 INFO L290 TraceCheckUtils]: 47: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,507 INFO L290 TraceCheckUtils]: 48: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,507 INFO L290 TraceCheckUtils]: 49: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,508 INFO L290 TraceCheckUtils]: 50: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,508 INFO L290 TraceCheckUtils]: 51: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,508 INFO L290 TraceCheckUtils]: 52: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 53: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 54: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,509 INFO L290 TraceCheckUtils]: 55: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 56: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 57: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,510 INFO L290 TraceCheckUtils]: 58: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,511 INFO L290 TraceCheckUtils]: 59: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,511 INFO L290 TraceCheckUtils]: 60: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,512 INFO L290 TraceCheckUtils]: 61: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,512 INFO L290 TraceCheckUtils]: 62: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,512 INFO L290 TraceCheckUtils]: 63: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,513 INFO L290 TraceCheckUtils]: 64: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,513 INFO L290 TraceCheckUtils]: 65: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,513 INFO L290 TraceCheckUtils]: 66: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,514 INFO L290 TraceCheckUtils]: 67: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,514 INFO L290 TraceCheckUtils]: 68: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,515 INFO L290 TraceCheckUtils]: 69: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,515 INFO L290 TraceCheckUtils]: 70: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,515 INFO L290 TraceCheckUtils]: 71: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,516 INFO L290 TraceCheckUtils]: 72: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,516 INFO L290 TraceCheckUtils]: 73: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,516 INFO L290 TraceCheckUtils]: 74: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,517 INFO L290 TraceCheckUtils]: 75: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,517 INFO L290 TraceCheckUtils]: 76: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,517 INFO L290 TraceCheckUtils]: 77: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,518 INFO L290 TraceCheckUtils]: 78: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,518 INFO L290 TraceCheckUtils]: 79: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,519 INFO L290 TraceCheckUtils]: 80: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,519 INFO L290 TraceCheckUtils]: 81: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,519 INFO L290 TraceCheckUtils]: 82: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,520 INFO L290 TraceCheckUtils]: 83: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,520 INFO L290 TraceCheckUtils]: 84: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,520 INFO L290 TraceCheckUtils]: 85: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,521 INFO L290 TraceCheckUtils]: 86: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,521 INFO L290 TraceCheckUtils]: 87: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,521 INFO L290 TraceCheckUtils]: 88: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,522 INFO L290 TraceCheckUtils]: 89: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,522 INFO L290 TraceCheckUtils]: 90: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,523 INFO L290 TraceCheckUtils]: 91: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,523 INFO L290 TraceCheckUtils]: 92: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,523 INFO L290 TraceCheckUtils]: 93: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,524 INFO L290 TraceCheckUtils]: 94: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,524 INFO L290 TraceCheckUtils]: 95: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,524 INFO L290 TraceCheckUtils]: 96: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,525 INFO L290 TraceCheckUtils]: 97: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,525 INFO L290 TraceCheckUtils]: 98: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,525 INFO L290 TraceCheckUtils]: 99: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,526 INFO L290 TraceCheckUtils]: 100: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,526 INFO L290 TraceCheckUtils]: 101: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,527 INFO L290 TraceCheckUtils]: 102: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,527 INFO L290 TraceCheckUtils]: 103: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,527 INFO L290 TraceCheckUtils]: 104: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,528 INFO L290 TraceCheckUtils]: 105: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,528 INFO L290 TraceCheckUtils]: 106: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,528 INFO L290 TraceCheckUtils]: 107: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,529 INFO L290 TraceCheckUtils]: 108: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,529 INFO L290 TraceCheckUtils]: 109: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,529 INFO L290 TraceCheckUtils]: 110: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,530 INFO L290 TraceCheckUtils]: 111: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,530 INFO L290 TraceCheckUtils]: 112: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,530 INFO L290 TraceCheckUtils]: 113: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,531 INFO L290 TraceCheckUtils]: 114: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,531 INFO L290 TraceCheckUtils]: 115: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,532 INFO L290 TraceCheckUtils]: 116: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,532 INFO L290 TraceCheckUtils]: 117: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,532 INFO L290 TraceCheckUtils]: 118: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,533 INFO L290 TraceCheckUtils]: 119: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,533 INFO L290 TraceCheckUtils]: 120: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,533 INFO L290 TraceCheckUtils]: 121: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,534 INFO L290 TraceCheckUtils]: 122: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,534 INFO L290 TraceCheckUtils]: 123: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,534 INFO L290 TraceCheckUtils]: 124: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,535 INFO L290 TraceCheckUtils]: 125: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,535 INFO L290 TraceCheckUtils]: 126: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {32595#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:34,536 INFO L290 TraceCheckUtils]: 127: Hoare triple {32595#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {32594#false} is VALID [2022-02-21 04:24:34,536 INFO L290 TraceCheckUtils]: 128: Hoare triple {32594#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,536 INFO L290 TraceCheckUtils]: 129: Hoare triple {32594#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,536 INFO L290 TraceCheckUtils]: 130: Hoare triple {32594#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,536 INFO L290 TraceCheckUtils]: 131: Hoare triple {32594#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,536 INFO L290 TraceCheckUtils]: 132: Hoare triple {32594#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,536 INFO L290 TraceCheckUtils]: 133: Hoare triple {32594#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,537 INFO L290 TraceCheckUtils]: 134: Hoare triple {32594#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,537 INFO L290 TraceCheckUtils]: 135: Hoare triple {32594#false} assume !(1 == ~T13_E~0); {32594#false} is VALID [2022-02-21 04:24:34,537 INFO L290 TraceCheckUtils]: 136: Hoare triple {32594#false} assume 1 == ~E_1~0;~E_1~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,537 INFO L290 TraceCheckUtils]: 137: Hoare triple {32594#false} assume 1 == ~E_2~0;~E_2~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,537 INFO L290 TraceCheckUtils]: 138: Hoare triple {32594#false} assume 1 == ~E_3~0;~E_3~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,537 INFO L290 TraceCheckUtils]: 139: Hoare triple {32594#false} assume 1 == ~E_4~0;~E_4~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,537 INFO L290 TraceCheckUtils]: 140: Hoare triple {32594#false} assume 1 == ~E_5~0;~E_5~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,538 INFO L290 TraceCheckUtils]: 141: Hoare triple {32594#false} assume 1 == ~E_6~0;~E_6~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,538 INFO L290 TraceCheckUtils]: 142: Hoare triple {32594#false} assume 1 == ~E_7~0;~E_7~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,538 INFO L290 TraceCheckUtils]: 143: Hoare triple {32594#false} assume !(1 == ~E_8~0); {32594#false} is VALID [2022-02-21 04:24:34,538 INFO L290 TraceCheckUtils]: 144: Hoare triple {32594#false} assume 1 == ~E_9~0;~E_9~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,538 INFO L290 TraceCheckUtils]: 145: Hoare triple {32594#false} assume 1 == ~E_10~0;~E_10~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,538 INFO L290 TraceCheckUtils]: 146: Hoare triple {32594#false} assume 1 == ~E_11~0;~E_11~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,538 INFO L290 TraceCheckUtils]: 147: Hoare triple {32594#false} assume 1 == ~E_12~0;~E_12~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,539 INFO L290 TraceCheckUtils]: 148: Hoare triple {32594#false} assume 1 == ~E_13~0;~E_13~0 := 2; {32594#false} is VALID [2022-02-21 04:24:34,539 INFO L290 TraceCheckUtils]: 149: Hoare triple {32594#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {32594#false} is VALID [2022-02-21 04:24:34,539 INFO L290 TraceCheckUtils]: 150: Hoare triple {32594#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {32594#false} is VALID [2022-02-21 04:24:34,539 INFO L290 TraceCheckUtils]: 151: Hoare triple {32594#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {32594#false} is VALID [2022-02-21 04:24:34,539 INFO L290 TraceCheckUtils]: 152: Hoare triple {32594#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {32594#false} is VALID [2022-02-21 04:24:34,539 INFO L290 TraceCheckUtils]: 153: Hoare triple {32594#false} assume !(0 == start_simulation_~tmp~3#1); {32594#false} is VALID [2022-02-21 04:24:34,539 INFO L290 TraceCheckUtils]: 154: Hoare triple {32594#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {32594#false} is VALID [2022-02-21 04:24:34,540 INFO L290 TraceCheckUtils]: 155: Hoare triple {32594#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {32594#false} is VALID [2022-02-21 04:24:34,540 INFO L290 TraceCheckUtils]: 156: Hoare triple {32594#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {32594#false} is VALID [2022-02-21 04:24:34,540 INFO L290 TraceCheckUtils]: 157: Hoare triple {32594#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {32594#false} is VALID [2022-02-21 04:24:34,540 INFO L290 TraceCheckUtils]: 158: Hoare triple {32594#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {32594#false} is VALID [2022-02-21 04:24:34,540 INFO L290 TraceCheckUtils]: 159: Hoare triple {32594#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {32594#false} is VALID [2022-02-21 04:24:34,540 INFO L290 TraceCheckUtils]: 160: Hoare triple {32594#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {32594#false} is VALID [2022-02-21 04:24:34,540 INFO L290 TraceCheckUtils]: 161: Hoare triple {32594#false} assume !(0 != start_simulation_~tmp___0~1#1); {32594#false} is VALID [2022-02-21 04:24:34,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:34,541 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:34,541 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480805133] [2022-02-21 04:24:34,541 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [480805133] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:34,542 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:34,542 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:34,542 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624892387] [2022-02-21 04:24:34,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:34,542 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:34,543 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:34,544 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:34,544 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:34,544 INFO L87 Difference]: Start difference. First operand 1914 states and 2832 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:35,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:35,982 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2022-02-21 04:24:35,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:35,983 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,100 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:36,100 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:36,195 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:36,296 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-02-21 04:24:36,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:36,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:36,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:36,300 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:36,300 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-02-21 04:24:36,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:36,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:36,326 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:36,329 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2831 transitions. Second operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,331 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2831 transitions. Second operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,333 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. Second operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:36,455 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2022-02-21 04:24:36,455 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:36,457 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:36,457 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:36,461 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2831 transitions. [2022-02-21 04:24:36,464 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2831 transitions. [2022-02-21 04:24:36,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:36,594 INFO L93 Difference]: Finished difference Result 1914 states and 2831 transitions. [2022-02-21 04:24:36,594 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:36,596 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:36,597 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:36,597 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:36,597 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:36,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4791013584117032) internal successors, (2831), 1913 states have internal predecessors, (2831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:36,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2831 transitions. [2022-02-21 04:24:36,719 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-02-21 04:24:36,719 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2831 transitions. [2022-02-21 04:24:36,719 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:24:36,720 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2831 transitions. [2022-02-21 04:24:36,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:36,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:36,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:36,732 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:36,732 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:36,733 INFO L791 eck$LassoCheckResult]: Stem: 35371#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 35372#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35191#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34907#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34908#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36084#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36085#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35043#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35044#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35502#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 35333#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 35334#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 35110#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 35111#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35509#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 35686#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35841#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35877#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35123#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35124#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36297#L1258-2 assume !(0 == ~T1_E~0); 35416#L1263-1 assume !(0 == ~T2_E~0); 35417#L1268-1 assume !(0 == ~T3_E~0); 35720#L1273-1 assume !(0 == ~T4_E~0); 36279#L1278-1 assume !(0 == ~T5_E~0); 36140#L1283-1 assume !(0 == ~T6_E~0); 36141#L1288-1 assume !(0 == ~T7_E~0); 36378#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36365#L1298-1 assume !(0 == ~T9_E~0); 36291#L1303-1 assume !(0 == ~T10_E~0); 34936#L1308-1 assume !(0 == ~T11_E~0); 34881#L1313-1 assume !(0 == ~T12_E~0); 34882#L1318-1 assume !(0 == ~T13_E~0); 34887#L1323-1 assume !(0 == ~E_1~0); 34888#L1328-1 assume !(0 == ~E_2~0); 35053#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 36012#L1338-1 assume !(0 == ~E_4~0); 36013#L1343-1 assume !(0 == ~E_5~0); 36114#L1348-1 assume !(0 == ~E_6~0); 36400#L1353-1 assume !(0 == ~E_7~0); 35739#L1358-1 assume !(0 == ~E_8~0); 35740#L1363-1 assume !(0 == ~E_9~0); 36031#L1368-1 assume !(0 == ~E_10~0); 34715#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 34716#L1378-1 assume !(0 == ~E_12~0); 35004#L1383-1 assume !(0 == ~E_13~0); 35005#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35746#L607 assume 1 == ~m_pc~0; 35747#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35073#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36112#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35666#L1560 assume !(0 != activate_threads_~tmp~1#1); 35667#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34898#L626 assume !(1 == ~t1_pc~0); 34899#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 35169#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35170#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35339#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 34801#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34802#L645 assume 1 == ~t2_pc~0; 34915#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34872#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35552#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35553#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 35642#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35643#L664 assume 1 == ~t3_pc~0; 36399#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34643#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34644#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35298#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 35299#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36307#L683 assume !(1 == ~t4_pc~0); 35862#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 35814#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35815#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35849#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35973#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35596#L702 assume 1 == ~t5_pc~0; 35597#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35519#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35968#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36267#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 36208#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34687#L721 assume !(1 == ~t6_pc~0); 34661#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 34662#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34825#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35307#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 35308#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35909#L740 assume 1 == ~t7_pc~0; 34736#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34549#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34550#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34539#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 34540#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35244#L759 assume !(1 == ~t8_pc~0); 35245#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35273#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35966#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35967#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 36098#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36376#L778 assume 1 == ~t9_pc~0; 36265#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34714#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34654#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34583#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 34584#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34912#L797 assume !(1 == ~t10_pc~0); 34913#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35030#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36164#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35414#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 35415#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35704#L816 assume 1 == ~t11_pc~0; 34619#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34620#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35377#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35314#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 35315#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35839#L835 assume 1 == ~t12_pc~0; 35717#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34783#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34805#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34946#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 35471#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35472#L854 assume !(1 == ~t13_pc~0); 35112#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 35113#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35165#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34823#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34824#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36203#L1401 assume !(1 == ~M_E~0); 35302#L1401-2 assume !(1 == ~T1_E~0); 35303#L1406-1 assume !(1 == ~T2_E~0); 35898#L1411-1 assume !(1 == ~T3_E~0); 35899#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35565#L1421-1 assume !(1 == ~T5_E~0); 35108#L1426-1 assume !(1 == ~T6_E~0); 35109#L1431-1 assume !(1 == ~T7_E~0); 34657#L1436-1 assume !(1 == ~T8_E~0); 34658#L1441-1 assume !(1 == ~T9_E~0); 35407#L1446-1 assume !(1 == ~T10_E~0); 35408#L1451-1 assume !(1 == ~T11_E~0); 36111#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35765#L1461-1 assume !(1 == ~T13_E~0); 35326#L1466-1 assume !(1 == ~E_1~0); 35327#L1471-1 assume !(1 == ~E_2~0); 36096#L1476-1 assume !(1 == ~E_3~0); 36097#L1481-1 assume !(1 == ~E_4~0); 36245#L1486-1 assume !(1 == ~E_5~0); 34953#L1491-1 assume !(1 == ~E_6~0); 34591#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 34592#L1501-1 assume !(1 == ~E_8~0); 35403#L1506-1 assume !(1 == ~E_9~0); 35404#L1511-1 assume !(1 == ~E_10~0); 35360#L1516-1 assume !(1 == ~E_11~0); 34537#L1521-1 assume !(1 == ~E_12~0); 34538#L1526-1 assume !(1 == ~E_13~0); 34590#L1531-1 assume { :end_inline_reset_delta_events } true; 35133#L1892-2 [2022-02-21 04:24:36,733 INFO L793 eck$LassoCheckResult]: Loop: 35133#L1892-2 assume !false; 36156#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36354#L1233 assume !false; 36337#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35669#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35649#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35807#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34633#L1046 assume !(0 != eval_~tmp~0#1); 34635#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34669#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35840#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 36398#L1258-5 assume !(0 == ~T1_E~0); 34811#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34812#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36390#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36396#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36397#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35035#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35036#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36153#L1298-3 assume !(0 == ~T9_E~0); 36154#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36313#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36152#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35653#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34813#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34814#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36237#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34956#L1338-3 assume !(0 == ~E_4~0); 34957#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36069#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 36242#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36243#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35609#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35167#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35168#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35926#L1378-3 assume !(0 == ~E_12~0); 35927#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36108#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36109#L607-42 assume 1 == ~m_pc~0; 35722#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35450#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35451#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35183#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35184#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35705#L626-42 assume 1 == ~t1_pc~0; 35267#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35268#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35572#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35573#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34847#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34848#L645-42 assume 1 == ~t2_pc~0; 36306#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36048#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36213#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35054#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34561#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34562#L664-42 assume !(1 == ~t3_pc~0); 35088#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 35089#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36340#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35875#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35876#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36041#L683-42 assume !(1 == ~t4_pc~0); 35749#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 35750#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35882#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36302#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36303#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36147#L702-42 assume 1 == ~t5_pc~0; 35635#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35260#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35556#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36229#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34577#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34578#L721-42 assume 1 == ~t6_pc~0; 34731#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34751#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35215#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36382#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35387#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35233#L740-42 assume 1 == ~t7_pc~0; 35234#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34971#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35512#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35367#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 35368#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35641#L759-42 assume 1 == ~t8_pc~0; 35490#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35422#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35423#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35500#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35501#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35595#L778-42 assume 1 == ~t9_pc~0; 35434#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35436#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35846#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35751#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35752#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35809#L797-42 assume 1 == ~t10_pc~0; 34976#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34977#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35978#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36287#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35847#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35848#L816-42 assume 1 == ~t11_pc~0; 34525#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34526#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35068#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35069#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35148#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35149#L835-42 assume !(1 == ~t12_pc~0); 35445#L835-44 is_transmit12_triggered_~__retres1~12#1 := 0; 35446#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35121#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35122#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 36206#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35990#L854-42 assume 1 == ~t13_pc~0; 35991#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 35067#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34677#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34678#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35324#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35325#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 36103#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34911#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34778#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34779#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35378#L1421-3 assume !(1 == ~T5_E~0); 35379#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34954#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34955#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 34541#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34542#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36131#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35462#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35115#L1461-3 assume !(1 == ~T13_E~0); 35116#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36393#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35055#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35056#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35456#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35083#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35084#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35496#L1501-3 assume !(1 == ~E_8~0); 35497#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35923#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35913#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35914#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35613#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35614#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36008#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 34890#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35783#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35424#L1911 assume !(0 == start_simulation_~tmp~3#1); 35425#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 35947#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35014#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35885#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34719#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34720#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34949#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 34950#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35133#L1892-2 [2022-02-21 04:24:36,734 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:36,734 INFO L85 PathProgramCache]: Analyzing trace with hash 351114206, now seen corresponding path program 1 times [2022-02-21 04:24:36,734 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:36,734 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453775947] [2022-02-21 04:24:36,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:36,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:36,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:36,760 INFO L290 TraceCheckUtils]: 0: Hoare triple {40255#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {40255#true} is VALID [2022-02-21 04:24:36,760 INFO L290 TraceCheckUtils]: 1: Hoare triple {40255#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {40257#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:36,761 INFO L290 TraceCheckUtils]: 2: Hoare triple {40257#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {40257#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:36,761 INFO L290 TraceCheckUtils]: 3: Hoare triple {40257#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {40257#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:36,761 INFO L290 TraceCheckUtils]: 4: Hoare triple {40257#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {40257#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:36,762 INFO L290 TraceCheckUtils]: 5: Hoare triple {40257#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {40257#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:36,762 INFO L290 TraceCheckUtils]: 6: Hoare triple {40257#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {40257#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:36,762 INFO L290 TraceCheckUtils]: 7: Hoare triple {40257#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {40257#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:36,763 INFO L290 TraceCheckUtils]: 8: Hoare triple {40257#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {40257#(= ~t5_i~0 1)} is VALID [2022-02-21 04:24:36,763 INFO L290 TraceCheckUtils]: 9: Hoare triple {40257#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {40256#false} is VALID [2022-02-21 04:24:36,763 INFO L290 TraceCheckUtils]: 10: Hoare triple {40256#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {40256#false} is VALID [2022-02-21 04:24:36,763 INFO L290 TraceCheckUtils]: 11: Hoare triple {40256#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {40256#false} is VALID [2022-02-21 04:24:36,764 INFO L290 TraceCheckUtils]: 12: Hoare triple {40256#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {40256#false} is VALID [2022-02-21 04:24:36,764 INFO L290 TraceCheckUtils]: 13: Hoare triple {40256#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {40256#false} is VALID [2022-02-21 04:24:36,764 INFO L290 TraceCheckUtils]: 14: Hoare triple {40256#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {40256#false} is VALID [2022-02-21 04:24:36,764 INFO L290 TraceCheckUtils]: 15: Hoare triple {40256#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {40256#false} is VALID [2022-02-21 04:24:36,764 INFO L290 TraceCheckUtils]: 16: Hoare triple {40256#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {40256#false} is VALID [2022-02-21 04:24:36,764 INFO L290 TraceCheckUtils]: 17: Hoare triple {40256#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {40256#false} is VALID [2022-02-21 04:24:36,764 INFO L290 TraceCheckUtils]: 18: Hoare triple {40256#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {40256#false} is VALID [2022-02-21 04:24:36,765 INFO L290 TraceCheckUtils]: 19: Hoare triple {40256#false} assume 0 == ~M_E~0;~M_E~0 := 1; {40256#false} is VALID [2022-02-21 04:24:36,765 INFO L290 TraceCheckUtils]: 20: Hoare triple {40256#false} assume !(0 == ~T1_E~0); {40256#false} is VALID [2022-02-21 04:24:36,765 INFO L290 TraceCheckUtils]: 21: Hoare triple {40256#false} assume !(0 == ~T2_E~0); {40256#false} is VALID [2022-02-21 04:24:36,765 INFO L290 TraceCheckUtils]: 22: Hoare triple {40256#false} assume !(0 == ~T3_E~0); {40256#false} is VALID [2022-02-21 04:24:36,765 INFO L290 TraceCheckUtils]: 23: Hoare triple {40256#false} assume !(0 == ~T4_E~0); {40256#false} is VALID [2022-02-21 04:24:36,765 INFO L290 TraceCheckUtils]: 24: Hoare triple {40256#false} assume !(0 == ~T5_E~0); {40256#false} is VALID [2022-02-21 04:24:36,765 INFO L290 TraceCheckUtils]: 25: Hoare triple {40256#false} assume !(0 == ~T6_E~0); {40256#false} is VALID [2022-02-21 04:24:36,766 INFO L290 TraceCheckUtils]: 26: Hoare triple {40256#false} assume !(0 == ~T7_E~0); {40256#false} is VALID [2022-02-21 04:24:36,766 INFO L290 TraceCheckUtils]: 27: Hoare triple {40256#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {40256#false} is VALID [2022-02-21 04:24:36,766 INFO L290 TraceCheckUtils]: 28: Hoare triple {40256#false} assume !(0 == ~T9_E~0); {40256#false} is VALID [2022-02-21 04:24:36,766 INFO L290 TraceCheckUtils]: 29: Hoare triple {40256#false} assume !(0 == ~T10_E~0); {40256#false} is VALID [2022-02-21 04:24:36,766 INFO L290 TraceCheckUtils]: 30: Hoare triple {40256#false} assume !(0 == ~T11_E~0); {40256#false} is VALID [2022-02-21 04:24:36,766 INFO L290 TraceCheckUtils]: 31: Hoare triple {40256#false} assume !(0 == ~T12_E~0); {40256#false} is VALID [2022-02-21 04:24:36,766 INFO L290 TraceCheckUtils]: 32: Hoare triple {40256#false} assume !(0 == ~T13_E~0); {40256#false} is VALID [2022-02-21 04:24:36,767 INFO L290 TraceCheckUtils]: 33: Hoare triple {40256#false} assume !(0 == ~E_1~0); {40256#false} is VALID [2022-02-21 04:24:36,767 INFO L290 TraceCheckUtils]: 34: Hoare triple {40256#false} assume !(0 == ~E_2~0); {40256#false} is VALID [2022-02-21 04:24:36,767 INFO L290 TraceCheckUtils]: 35: Hoare triple {40256#false} assume 0 == ~E_3~0;~E_3~0 := 1; {40256#false} is VALID [2022-02-21 04:24:36,767 INFO L290 TraceCheckUtils]: 36: Hoare triple {40256#false} assume !(0 == ~E_4~0); {40256#false} is VALID [2022-02-21 04:24:36,767 INFO L290 TraceCheckUtils]: 37: Hoare triple {40256#false} assume !(0 == ~E_5~0); {40256#false} is VALID [2022-02-21 04:24:36,767 INFO L290 TraceCheckUtils]: 38: Hoare triple {40256#false} assume !(0 == ~E_6~0); {40256#false} is VALID [2022-02-21 04:24:36,767 INFO L290 TraceCheckUtils]: 39: Hoare triple {40256#false} assume !(0 == ~E_7~0); {40256#false} is VALID [2022-02-21 04:24:36,768 INFO L290 TraceCheckUtils]: 40: Hoare triple {40256#false} assume !(0 == ~E_8~0); {40256#false} is VALID [2022-02-21 04:24:36,768 INFO L290 TraceCheckUtils]: 41: Hoare triple {40256#false} assume !(0 == ~E_9~0); {40256#false} is VALID [2022-02-21 04:24:36,768 INFO L290 TraceCheckUtils]: 42: Hoare triple {40256#false} assume !(0 == ~E_10~0); {40256#false} is VALID [2022-02-21 04:24:36,768 INFO L290 TraceCheckUtils]: 43: Hoare triple {40256#false} assume 0 == ~E_11~0;~E_11~0 := 1; {40256#false} is VALID [2022-02-21 04:24:36,768 INFO L290 TraceCheckUtils]: 44: Hoare triple {40256#false} assume !(0 == ~E_12~0); {40256#false} is VALID [2022-02-21 04:24:36,768 INFO L290 TraceCheckUtils]: 45: Hoare triple {40256#false} assume !(0 == ~E_13~0); {40256#false} is VALID [2022-02-21 04:24:36,768 INFO L290 TraceCheckUtils]: 46: Hoare triple {40256#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {40256#false} is VALID [2022-02-21 04:24:36,769 INFO L290 TraceCheckUtils]: 47: Hoare triple {40256#false} assume 1 == ~m_pc~0; {40256#false} is VALID [2022-02-21 04:24:36,769 INFO L290 TraceCheckUtils]: 48: Hoare triple {40256#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {40256#false} is VALID [2022-02-21 04:24:36,769 INFO L290 TraceCheckUtils]: 49: Hoare triple {40256#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {40256#false} is VALID [2022-02-21 04:24:36,769 INFO L290 TraceCheckUtils]: 50: Hoare triple {40256#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {40256#false} is VALID [2022-02-21 04:24:36,769 INFO L290 TraceCheckUtils]: 51: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp~1#1); {40256#false} is VALID [2022-02-21 04:24:36,769 INFO L290 TraceCheckUtils]: 52: Hoare triple {40256#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {40256#false} is VALID [2022-02-21 04:24:36,769 INFO L290 TraceCheckUtils]: 53: Hoare triple {40256#false} assume !(1 == ~t1_pc~0); {40256#false} is VALID [2022-02-21 04:24:36,770 INFO L290 TraceCheckUtils]: 54: Hoare triple {40256#false} is_transmit1_triggered_~__retres1~1#1 := 0; {40256#false} is VALID [2022-02-21 04:24:36,770 INFO L290 TraceCheckUtils]: 55: Hoare triple {40256#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {40256#false} is VALID [2022-02-21 04:24:36,770 INFO L290 TraceCheckUtils]: 56: Hoare triple {40256#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {40256#false} is VALID [2022-02-21 04:24:36,770 INFO L290 TraceCheckUtils]: 57: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp___0~0#1); {40256#false} is VALID [2022-02-21 04:24:36,770 INFO L290 TraceCheckUtils]: 58: Hoare triple {40256#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {40256#false} is VALID [2022-02-21 04:24:36,770 INFO L290 TraceCheckUtils]: 59: Hoare triple {40256#false} assume 1 == ~t2_pc~0; {40256#false} is VALID [2022-02-21 04:24:36,770 INFO L290 TraceCheckUtils]: 60: Hoare triple {40256#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {40256#false} is VALID [2022-02-21 04:24:36,771 INFO L290 TraceCheckUtils]: 61: Hoare triple {40256#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {40256#false} is VALID [2022-02-21 04:24:36,771 INFO L290 TraceCheckUtils]: 62: Hoare triple {40256#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {40256#false} is VALID [2022-02-21 04:24:36,771 INFO L290 TraceCheckUtils]: 63: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp___1~0#1); {40256#false} is VALID [2022-02-21 04:24:36,771 INFO L290 TraceCheckUtils]: 64: Hoare triple {40256#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {40256#false} is VALID [2022-02-21 04:24:36,771 INFO L290 TraceCheckUtils]: 65: Hoare triple {40256#false} assume 1 == ~t3_pc~0; {40256#false} is VALID [2022-02-21 04:24:36,771 INFO L290 TraceCheckUtils]: 66: Hoare triple {40256#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {40256#false} is VALID [2022-02-21 04:24:36,771 INFO L290 TraceCheckUtils]: 67: Hoare triple {40256#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {40256#false} is VALID [2022-02-21 04:24:36,772 INFO L290 TraceCheckUtils]: 68: Hoare triple {40256#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {40256#false} is VALID [2022-02-21 04:24:36,772 INFO L290 TraceCheckUtils]: 69: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp___2~0#1); {40256#false} is VALID [2022-02-21 04:24:36,772 INFO L290 TraceCheckUtils]: 70: Hoare triple {40256#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {40256#false} is VALID [2022-02-21 04:24:36,772 INFO L290 TraceCheckUtils]: 71: Hoare triple {40256#false} assume !(1 == ~t4_pc~0); {40256#false} is VALID [2022-02-21 04:24:36,772 INFO L290 TraceCheckUtils]: 72: Hoare triple {40256#false} is_transmit4_triggered_~__retres1~4#1 := 0; {40256#false} is VALID [2022-02-21 04:24:36,772 INFO L290 TraceCheckUtils]: 73: Hoare triple {40256#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {40256#false} is VALID [2022-02-21 04:24:36,772 INFO L290 TraceCheckUtils]: 74: Hoare triple {40256#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {40256#false} is VALID [2022-02-21 04:24:36,773 INFO L290 TraceCheckUtils]: 75: Hoare triple {40256#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {40256#false} is VALID [2022-02-21 04:24:36,773 INFO L290 TraceCheckUtils]: 76: Hoare triple {40256#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {40256#false} is VALID [2022-02-21 04:24:36,773 INFO L290 TraceCheckUtils]: 77: Hoare triple {40256#false} assume 1 == ~t5_pc~0; {40256#false} is VALID [2022-02-21 04:24:36,773 INFO L290 TraceCheckUtils]: 78: Hoare triple {40256#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {40256#false} is VALID [2022-02-21 04:24:36,773 INFO L290 TraceCheckUtils]: 79: Hoare triple {40256#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {40256#false} is VALID [2022-02-21 04:24:36,773 INFO L290 TraceCheckUtils]: 80: Hoare triple {40256#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {40256#false} is VALID [2022-02-21 04:24:36,773 INFO L290 TraceCheckUtils]: 81: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp___4~0#1); {40256#false} is VALID [2022-02-21 04:24:36,774 INFO L290 TraceCheckUtils]: 82: Hoare triple {40256#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {40256#false} is VALID [2022-02-21 04:24:36,774 INFO L290 TraceCheckUtils]: 83: Hoare triple {40256#false} assume !(1 == ~t6_pc~0); {40256#false} is VALID [2022-02-21 04:24:36,774 INFO L290 TraceCheckUtils]: 84: Hoare triple {40256#false} is_transmit6_triggered_~__retres1~6#1 := 0; {40256#false} is VALID [2022-02-21 04:24:36,774 INFO L290 TraceCheckUtils]: 85: Hoare triple {40256#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {40256#false} is VALID [2022-02-21 04:24:36,774 INFO L290 TraceCheckUtils]: 86: Hoare triple {40256#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {40256#false} is VALID [2022-02-21 04:24:36,774 INFO L290 TraceCheckUtils]: 87: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp___5~0#1); {40256#false} is VALID [2022-02-21 04:24:36,774 INFO L290 TraceCheckUtils]: 88: Hoare triple {40256#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {40256#false} is VALID [2022-02-21 04:24:36,775 INFO L290 TraceCheckUtils]: 89: Hoare triple {40256#false} assume 1 == ~t7_pc~0; {40256#false} is VALID [2022-02-21 04:24:36,775 INFO L290 TraceCheckUtils]: 90: Hoare triple {40256#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {40256#false} is VALID [2022-02-21 04:24:36,775 INFO L290 TraceCheckUtils]: 91: Hoare triple {40256#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {40256#false} is VALID [2022-02-21 04:24:36,775 INFO L290 TraceCheckUtils]: 92: Hoare triple {40256#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {40256#false} is VALID [2022-02-21 04:24:36,775 INFO L290 TraceCheckUtils]: 93: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp___6~0#1); {40256#false} is VALID [2022-02-21 04:24:36,775 INFO L290 TraceCheckUtils]: 94: Hoare triple {40256#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {40256#false} is VALID [2022-02-21 04:24:36,775 INFO L290 TraceCheckUtils]: 95: Hoare triple {40256#false} assume !(1 == ~t8_pc~0); {40256#false} is VALID [2022-02-21 04:24:36,776 INFO L290 TraceCheckUtils]: 96: Hoare triple {40256#false} is_transmit8_triggered_~__retres1~8#1 := 0; {40256#false} is VALID [2022-02-21 04:24:36,776 INFO L290 TraceCheckUtils]: 97: Hoare triple {40256#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {40256#false} is VALID [2022-02-21 04:24:36,776 INFO L290 TraceCheckUtils]: 98: Hoare triple {40256#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {40256#false} is VALID [2022-02-21 04:24:36,776 INFO L290 TraceCheckUtils]: 99: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp___7~0#1); {40256#false} is VALID [2022-02-21 04:24:36,776 INFO L290 TraceCheckUtils]: 100: Hoare triple {40256#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {40256#false} is VALID [2022-02-21 04:24:36,776 INFO L290 TraceCheckUtils]: 101: Hoare triple {40256#false} assume 1 == ~t9_pc~0; {40256#false} is VALID [2022-02-21 04:24:36,777 INFO L290 TraceCheckUtils]: 102: Hoare triple {40256#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {40256#false} is VALID [2022-02-21 04:24:36,777 INFO L290 TraceCheckUtils]: 103: Hoare triple {40256#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {40256#false} is VALID [2022-02-21 04:24:36,777 INFO L290 TraceCheckUtils]: 104: Hoare triple {40256#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {40256#false} is VALID [2022-02-21 04:24:36,777 INFO L290 TraceCheckUtils]: 105: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp___8~0#1); {40256#false} is VALID [2022-02-21 04:24:36,777 INFO L290 TraceCheckUtils]: 106: Hoare triple {40256#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {40256#false} is VALID [2022-02-21 04:24:36,777 INFO L290 TraceCheckUtils]: 107: Hoare triple {40256#false} assume !(1 == ~t10_pc~0); {40256#false} is VALID [2022-02-21 04:24:36,777 INFO L290 TraceCheckUtils]: 108: Hoare triple {40256#false} is_transmit10_triggered_~__retres1~10#1 := 0; {40256#false} is VALID [2022-02-21 04:24:36,778 INFO L290 TraceCheckUtils]: 109: Hoare triple {40256#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {40256#false} is VALID [2022-02-21 04:24:36,778 INFO L290 TraceCheckUtils]: 110: Hoare triple {40256#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {40256#false} is VALID [2022-02-21 04:24:36,778 INFO L290 TraceCheckUtils]: 111: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp___9~0#1); {40256#false} is VALID [2022-02-21 04:24:36,778 INFO L290 TraceCheckUtils]: 112: Hoare triple {40256#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {40256#false} is VALID [2022-02-21 04:24:36,778 INFO L290 TraceCheckUtils]: 113: Hoare triple {40256#false} assume 1 == ~t11_pc~0; {40256#false} is VALID [2022-02-21 04:24:36,778 INFO L290 TraceCheckUtils]: 114: Hoare triple {40256#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {40256#false} is VALID [2022-02-21 04:24:36,778 INFO L290 TraceCheckUtils]: 115: Hoare triple {40256#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {40256#false} is VALID [2022-02-21 04:24:36,778 INFO L290 TraceCheckUtils]: 116: Hoare triple {40256#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {40256#false} is VALID [2022-02-21 04:24:36,779 INFO L290 TraceCheckUtils]: 117: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp___10~0#1); {40256#false} is VALID [2022-02-21 04:24:36,779 INFO L290 TraceCheckUtils]: 118: Hoare triple {40256#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {40256#false} is VALID [2022-02-21 04:24:36,779 INFO L290 TraceCheckUtils]: 119: Hoare triple {40256#false} assume 1 == ~t12_pc~0; {40256#false} is VALID [2022-02-21 04:24:36,779 INFO L290 TraceCheckUtils]: 120: Hoare triple {40256#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {40256#false} is VALID [2022-02-21 04:24:36,779 INFO L290 TraceCheckUtils]: 121: Hoare triple {40256#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {40256#false} is VALID [2022-02-21 04:24:36,779 INFO L290 TraceCheckUtils]: 122: Hoare triple {40256#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {40256#false} is VALID [2022-02-21 04:24:36,779 INFO L290 TraceCheckUtils]: 123: Hoare triple {40256#false} assume !(0 != activate_threads_~tmp___11~0#1); {40256#false} is VALID [2022-02-21 04:24:36,780 INFO L290 TraceCheckUtils]: 124: Hoare triple {40256#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {40256#false} is VALID [2022-02-21 04:24:36,780 INFO L290 TraceCheckUtils]: 125: Hoare triple {40256#false} assume !(1 == ~t13_pc~0); {40256#false} is VALID [2022-02-21 04:24:36,780 INFO L290 TraceCheckUtils]: 126: Hoare triple {40256#false} is_transmit13_triggered_~__retres1~13#1 := 0; {40256#false} is VALID [2022-02-21 04:24:36,780 INFO L290 TraceCheckUtils]: 127: Hoare triple {40256#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {40256#false} is VALID [2022-02-21 04:24:36,780 INFO L290 TraceCheckUtils]: 128: Hoare triple {40256#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {40256#false} is VALID [2022-02-21 04:24:36,780 INFO L290 TraceCheckUtils]: 129: Hoare triple {40256#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {40256#false} is VALID [2022-02-21 04:24:36,780 INFO L290 TraceCheckUtils]: 130: Hoare triple {40256#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {40256#false} is VALID [2022-02-21 04:24:36,781 INFO L290 TraceCheckUtils]: 131: Hoare triple {40256#false} assume !(1 == ~M_E~0); {40256#false} is VALID [2022-02-21 04:24:36,781 INFO L290 TraceCheckUtils]: 132: Hoare triple {40256#false} assume !(1 == ~T1_E~0); {40256#false} is VALID [2022-02-21 04:24:36,781 INFO L290 TraceCheckUtils]: 133: Hoare triple {40256#false} assume !(1 == ~T2_E~0); {40256#false} is VALID [2022-02-21 04:24:36,781 INFO L290 TraceCheckUtils]: 134: Hoare triple {40256#false} assume !(1 == ~T3_E~0); {40256#false} is VALID [2022-02-21 04:24:36,781 INFO L290 TraceCheckUtils]: 135: Hoare triple {40256#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {40256#false} is VALID [2022-02-21 04:24:36,781 INFO L290 TraceCheckUtils]: 136: Hoare triple {40256#false} assume !(1 == ~T5_E~0); {40256#false} is VALID [2022-02-21 04:24:36,781 INFO L290 TraceCheckUtils]: 137: Hoare triple {40256#false} assume !(1 == ~T6_E~0); {40256#false} is VALID [2022-02-21 04:24:36,782 INFO L290 TraceCheckUtils]: 138: Hoare triple {40256#false} assume !(1 == ~T7_E~0); {40256#false} is VALID [2022-02-21 04:24:36,782 INFO L290 TraceCheckUtils]: 139: Hoare triple {40256#false} assume !(1 == ~T8_E~0); {40256#false} is VALID [2022-02-21 04:24:36,782 INFO L290 TraceCheckUtils]: 140: Hoare triple {40256#false} assume !(1 == ~T9_E~0); {40256#false} is VALID [2022-02-21 04:24:36,782 INFO L290 TraceCheckUtils]: 141: Hoare triple {40256#false} assume !(1 == ~T10_E~0); {40256#false} is VALID [2022-02-21 04:24:36,782 INFO L290 TraceCheckUtils]: 142: Hoare triple {40256#false} assume !(1 == ~T11_E~0); {40256#false} is VALID [2022-02-21 04:24:36,782 INFO L290 TraceCheckUtils]: 143: Hoare triple {40256#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {40256#false} is VALID [2022-02-21 04:24:36,782 INFO L290 TraceCheckUtils]: 144: Hoare triple {40256#false} assume !(1 == ~T13_E~0); {40256#false} is VALID [2022-02-21 04:24:36,783 INFO L290 TraceCheckUtils]: 145: Hoare triple {40256#false} assume !(1 == ~E_1~0); {40256#false} is VALID [2022-02-21 04:24:36,783 INFO L290 TraceCheckUtils]: 146: Hoare triple {40256#false} assume !(1 == ~E_2~0); {40256#false} is VALID [2022-02-21 04:24:36,783 INFO L290 TraceCheckUtils]: 147: Hoare triple {40256#false} assume !(1 == ~E_3~0); {40256#false} is VALID [2022-02-21 04:24:36,783 INFO L290 TraceCheckUtils]: 148: Hoare triple {40256#false} assume !(1 == ~E_4~0); {40256#false} is VALID [2022-02-21 04:24:36,783 INFO L290 TraceCheckUtils]: 149: Hoare triple {40256#false} assume !(1 == ~E_5~0); {40256#false} is VALID [2022-02-21 04:24:36,783 INFO L290 TraceCheckUtils]: 150: Hoare triple {40256#false} assume !(1 == ~E_6~0); {40256#false} is VALID [2022-02-21 04:24:36,783 INFO L290 TraceCheckUtils]: 151: Hoare triple {40256#false} assume 1 == ~E_7~0;~E_7~0 := 2; {40256#false} is VALID [2022-02-21 04:24:36,784 INFO L290 TraceCheckUtils]: 152: Hoare triple {40256#false} assume !(1 == ~E_8~0); {40256#false} is VALID [2022-02-21 04:24:36,784 INFO L290 TraceCheckUtils]: 153: Hoare triple {40256#false} assume !(1 == ~E_9~0); {40256#false} is VALID [2022-02-21 04:24:36,784 INFO L290 TraceCheckUtils]: 154: Hoare triple {40256#false} assume !(1 == ~E_10~0); {40256#false} is VALID [2022-02-21 04:24:36,784 INFO L290 TraceCheckUtils]: 155: Hoare triple {40256#false} assume !(1 == ~E_11~0); {40256#false} is VALID [2022-02-21 04:24:36,784 INFO L290 TraceCheckUtils]: 156: Hoare triple {40256#false} assume !(1 == ~E_12~0); {40256#false} is VALID [2022-02-21 04:24:36,784 INFO L290 TraceCheckUtils]: 157: Hoare triple {40256#false} assume !(1 == ~E_13~0); {40256#false} is VALID [2022-02-21 04:24:36,784 INFO L290 TraceCheckUtils]: 158: Hoare triple {40256#false} assume { :end_inline_reset_delta_events } true; {40256#false} is VALID [2022-02-21 04:24:36,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:36,785 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:36,785 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453775947] [2022-02-21 04:24:36,785 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [453775947] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:36,786 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:36,786 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:36,786 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357932432] [2022-02-21 04:24:36,786 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:36,786 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:36,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:36,787 INFO L85 PathProgramCache]: Analyzing trace with hash 1484219552, now seen corresponding path program 1 times [2022-02-21 04:24:36,787 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:36,787 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [890892913] [2022-02-21 04:24:36,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:36,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:36,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:36,822 INFO L290 TraceCheckUtils]: 0: Hoare triple {40258#true} assume !false; {40258#true} is VALID [2022-02-21 04:24:36,823 INFO L290 TraceCheckUtils]: 1: Hoare triple {40258#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {40258#true} is VALID [2022-02-21 04:24:36,823 INFO L290 TraceCheckUtils]: 2: Hoare triple {40258#true} assume !false; {40258#true} is VALID [2022-02-21 04:24:36,823 INFO L290 TraceCheckUtils]: 3: Hoare triple {40258#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {40258#true} is VALID [2022-02-21 04:24:36,823 INFO L290 TraceCheckUtils]: 4: Hoare triple {40258#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {40258#true} is VALID [2022-02-21 04:24:36,823 INFO L290 TraceCheckUtils]: 5: Hoare triple {40258#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {40258#true} is VALID [2022-02-21 04:24:36,823 INFO L290 TraceCheckUtils]: 6: Hoare triple {40258#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {40258#true} is VALID [2022-02-21 04:24:36,824 INFO L290 TraceCheckUtils]: 7: Hoare triple {40258#true} assume !(0 != eval_~tmp~0#1); {40258#true} is VALID [2022-02-21 04:24:36,824 INFO L290 TraceCheckUtils]: 8: Hoare triple {40258#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {40258#true} is VALID [2022-02-21 04:24:36,824 INFO L290 TraceCheckUtils]: 9: Hoare triple {40258#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {40258#true} is VALID [2022-02-21 04:24:36,824 INFO L290 TraceCheckUtils]: 10: Hoare triple {40258#true} assume 0 == ~M_E~0;~M_E~0 := 1; {40258#true} is VALID [2022-02-21 04:24:36,824 INFO L290 TraceCheckUtils]: 11: Hoare triple {40258#true} assume !(0 == ~T1_E~0); {40258#true} is VALID [2022-02-21 04:24:36,824 INFO L290 TraceCheckUtils]: 12: Hoare triple {40258#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {40258#true} is VALID [2022-02-21 04:24:36,824 INFO L290 TraceCheckUtils]: 13: Hoare triple {40258#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {40258#true} is VALID [2022-02-21 04:24:36,825 INFO L290 TraceCheckUtils]: 14: Hoare triple {40258#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {40258#true} is VALID [2022-02-21 04:24:36,825 INFO L290 TraceCheckUtils]: 15: Hoare triple {40258#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,825 INFO L290 TraceCheckUtils]: 16: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,826 INFO L290 TraceCheckUtils]: 17: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,826 INFO L290 TraceCheckUtils]: 18: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,827 INFO L290 TraceCheckUtils]: 19: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,827 INFO L290 TraceCheckUtils]: 20: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,827 INFO L290 TraceCheckUtils]: 21: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,828 INFO L290 TraceCheckUtils]: 22: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,828 INFO L290 TraceCheckUtils]: 23: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,828 INFO L290 TraceCheckUtils]: 24: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,829 INFO L290 TraceCheckUtils]: 25: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,829 INFO L290 TraceCheckUtils]: 26: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,830 INFO L290 TraceCheckUtils]: 27: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,830 INFO L290 TraceCheckUtils]: 28: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,830 INFO L290 TraceCheckUtils]: 29: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,831 INFO L290 TraceCheckUtils]: 30: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,831 INFO L290 TraceCheckUtils]: 31: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,831 INFO L290 TraceCheckUtils]: 32: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,832 INFO L290 TraceCheckUtils]: 33: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,832 INFO L290 TraceCheckUtils]: 34: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,833 INFO L290 TraceCheckUtils]: 35: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,833 INFO L290 TraceCheckUtils]: 36: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,833 INFO L290 TraceCheckUtils]: 37: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,834 INFO L290 TraceCheckUtils]: 38: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,834 INFO L290 TraceCheckUtils]: 39: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,834 INFO L290 TraceCheckUtils]: 40: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,835 INFO L290 TraceCheckUtils]: 41: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,835 INFO L290 TraceCheckUtils]: 42: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,836 INFO L290 TraceCheckUtils]: 43: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,836 INFO L290 TraceCheckUtils]: 44: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,836 INFO L290 TraceCheckUtils]: 45: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,837 INFO L290 TraceCheckUtils]: 46: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,837 INFO L290 TraceCheckUtils]: 47: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,837 INFO L290 TraceCheckUtils]: 48: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,838 INFO L290 TraceCheckUtils]: 49: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,838 INFO L290 TraceCheckUtils]: 50: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,838 INFO L290 TraceCheckUtils]: 51: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,839 INFO L290 TraceCheckUtils]: 52: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,839 INFO L290 TraceCheckUtils]: 53: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,840 INFO L290 TraceCheckUtils]: 54: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,840 INFO L290 TraceCheckUtils]: 55: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,840 INFO L290 TraceCheckUtils]: 56: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,841 INFO L290 TraceCheckUtils]: 57: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,841 INFO L290 TraceCheckUtils]: 58: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,841 INFO L290 TraceCheckUtils]: 59: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,842 INFO L290 TraceCheckUtils]: 60: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,842 INFO L290 TraceCheckUtils]: 61: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,843 INFO L290 TraceCheckUtils]: 62: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,843 INFO L290 TraceCheckUtils]: 63: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,843 INFO L290 TraceCheckUtils]: 64: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,844 INFO L290 TraceCheckUtils]: 65: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,844 INFO L290 TraceCheckUtils]: 66: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,844 INFO L290 TraceCheckUtils]: 67: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,845 INFO L290 TraceCheckUtils]: 68: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,845 INFO L290 TraceCheckUtils]: 69: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,846 INFO L290 TraceCheckUtils]: 70: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,846 INFO L290 TraceCheckUtils]: 71: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,846 INFO L290 TraceCheckUtils]: 72: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,847 INFO L290 TraceCheckUtils]: 73: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,847 INFO L290 TraceCheckUtils]: 74: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,847 INFO L290 TraceCheckUtils]: 75: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,848 INFO L290 TraceCheckUtils]: 76: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,848 INFO L290 TraceCheckUtils]: 77: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,848 INFO L290 TraceCheckUtils]: 78: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,849 INFO L290 TraceCheckUtils]: 79: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,849 INFO L290 TraceCheckUtils]: 80: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,850 INFO L290 TraceCheckUtils]: 81: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,850 INFO L290 TraceCheckUtils]: 82: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,850 INFO L290 TraceCheckUtils]: 83: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,851 INFO L290 TraceCheckUtils]: 84: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,851 INFO L290 TraceCheckUtils]: 85: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,851 INFO L290 TraceCheckUtils]: 86: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,852 INFO L290 TraceCheckUtils]: 87: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,852 INFO L290 TraceCheckUtils]: 88: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,853 INFO L290 TraceCheckUtils]: 89: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,853 INFO L290 TraceCheckUtils]: 90: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,853 INFO L290 TraceCheckUtils]: 91: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,854 INFO L290 TraceCheckUtils]: 92: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,854 INFO L290 TraceCheckUtils]: 93: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,854 INFO L290 TraceCheckUtils]: 94: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,855 INFO L290 TraceCheckUtils]: 95: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,855 INFO L290 TraceCheckUtils]: 96: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,855 INFO L290 TraceCheckUtils]: 97: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,856 INFO L290 TraceCheckUtils]: 98: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,856 INFO L290 TraceCheckUtils]: 99: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,857 INFO L290 TraceCheckUtils]: 100: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,857 INFO L290 TraceCheckUtils]: 101: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,857 INFO L290 TraceCheckUtils]: 102: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,858 INFO L290 TraceCheckUtils]: 103: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,858 INFO L290 TraceCheckUtils]: 104: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,858 INFO L290 TraceCheckUtils]: 105: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,859 INFO L290 TraceCheckUtils]: 106: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,859 INFO L290 TraceCheckUtils]: 107: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,860 INFO L290 TraceCheckUtils]: 108: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,860 INFO L290 TraceCheckUtils]: 109: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,860 INFO L290 TraceCheckUtils]: 110: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t12_pc~0); {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,861 INFO L290 TraceCheckUtils]: 111: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_~__retres1~12#1 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,861 INFO L290 TraceCheckUtils]: 112: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,861 INFO L290 TraceCheckUtils]: 113: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,862 INFO L290 TraceCheckUtils]: 114: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,862 INFO L290 TraceCheckUtils]: 115: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,862 INFO L290 TraceCheckUtils]: 116: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,863 INFO L290 TraceCheckUtils]: 117: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,863 INFO L290 TraceCheckUtils]: 118: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,864 INFO L290 TraceCheckUtils]: 119: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,864 INFO L290 TraceCheckUtils]: 120: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,864 INFO L290 TraceCheckUtils]: 121: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,865 INFO L290 TraceCheckUtils]: 122: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,865 INFO L290 TraceCheckUtils]: 123: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,865 INFO L290 TraceCheckUtils]: 124: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,866 INFO L290 TraceCheckUtils]: 125: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,866 INFO L290 TraceCheckUtils]: 126: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {40260#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:36,867 INFO L290 TraceCheckUtils]: 127: Hoare triple {40260#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {40259#false} is VALID [2022-02-21 04:24:36,867 INFO L290 TraceCheckUtils]: 128: Hoare triple {40259#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,867 INFO L290 TraceCheckUtils]: 129: Hoare triple {40259#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,867 INFO L290 TraceCheckUtils]: 130: Hoare triple {40259#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,867 INFO L290 TraceCheckUtils]: 131: Hoare triple {40259#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,867 INFO L290 TraceCheckUtils]: 132: Hoare triple {40259#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,868 INFO L290 TraceCheckUtils]: 133: Hoare triple {40259#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,868 INFO L290 TraceCheckUtils]: 134: Hoare triple {40259#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,868 INFO L290 TraceCheckUtils]: 135: Hoare triple {40259#false} assume !(1 == ~T13_E~0); {40259#false} is VALID [2022-02-21 04:24:36,868 INFO L290 TraceCheckUtils]: 136: Hoare triple {40259#false} assume 1 == ~E_1~0;~E_1~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,868 INFO L290 TraceCheckUtils]: 137: Hoare triple {40259#false} assume 1 == ~E_2~0;~E_2~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,868 INFO L290 TraceCheckUtils]: 138: Hoare triple {40259#false} assume 1 == ~E_3~0;~E_3~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,868 INFO L290 TraceCheckUtils]: 139: Hoare triple {40259#false} assume 1 == ~E_4~0;~E_4~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,868 INFO L290 TraceCheckUtils]: 140: Hoare triple {40259#false} assume 1 == ~E_5~0;~E_5~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,869 INFO L290 TraceCheckUtils]: 141: Hoare triple {40259#false} assume 1 == ~E_6~0;~E_6~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,869 INFO L290 TraceCheckUtils]: 142: Hoare triple {40259#false} assume 1 == ~E_7~0;~E_7~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,869 INFO L290 TraceCheckUtils]: 143: Hoare triple {40259#false} assume !(1 == ~E_8~0); {40259#false} is VALID [2022-02-21 04:24:36,869 INFO L290 TraceCheckUtils]: 144: Hoare triple {40259#false} assume 1 == ~E_9~0;~E_9~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,869 INFO L290 TraceCheckUtils]: 145: Hoare triple {40259#false} assume 1 == ~E_10~0;~E_10~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,869 INFO L290 TraceCheckUtils]: 146: Hoare triple {40259#false} assume 1 == ~E_11~0;~E_11~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,869 INFO L290 TraceCheckUtils]: 147: Hoare triple {40259#false} assume 1 == ~E_12~0;~E_12~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,870 INFO L290 TraceCheckUtils]: 148: Hoare triple {40259#false} assume 1 == ~E_13~0;~E_13~0 := 2; {40259#false} is VALID [2022-02-21 04:24:36,870 INFO L290 TraceCheckUtils]: 149: Hoare triple {40259#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {40259#false} is VALID [2022-02-21 04:24:36,870 INFO L290 TraceCheckUtils]: 150: Hoare triple {40259#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {40259#false} is VALID [2022-02-21 04:24:36,870 INFO L290 TraceCheckUtils]: 151: Hoare triple {40259#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {40259#false} is VALID [2022-02-21 04:24:36,870 INFO L290 TraceCheckUtils]: 152: Hoare triple {40259#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {40259#false} is VALID [2022-02-21 04:24:36,870 INFO L290 TraceCheckUtils]: 153: Hoare triple {40259#false} assume !(0 == start_simulation_~tmp~3#1); {40259#false} is VALID [2022-02-21 04:24:36,871 INFO L290 TraceCheckUtils]: 154: Hoare triple {40259#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {40259#false} is VALID [2022-02-21 04:24:36,871 INFO L290 TraceCheckUtils]: 155: Hoare triple {40259#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {40259#false} is VALID [2022-02-21 04:24:36,871 INFO L290 TraceCheckUtils]: 156: Hoare triple {40259#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {40259#false} is VALID [2022-02-21 04:24:36,871 INFO L290 TraceCheckUtils]: 157: Hoare triple {40259#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {40259#false} is VALID [2022-02-21 04:24:36,871 INFO L290 TraceCheckUtils]: 158: Hoare triple {40259#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {40259#false} is VALID [2022-02-21 04:24:36,871 INFO L290 TraceCheckUtils]: 159: Hoare triple {40259#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {40259#false} is VALID [2022-02-21 04:24:36,871 INFO L290 TraceCheckUtils]: 160: Hoare triple {40259#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {40259#false} is VALID [2022-02-21 04:24:36,872 INFO L290 TraceCheckUtils]: 161: Hoare triple {40259#false} assume !(0 != start_simulation_~tmp___0~1#1); {40259#false} is VALID [2022-02-21 04:24:36,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:36,872 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:36,873 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [890892913] [2022-02-21 04:24:36,873 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [890892913] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:36,873 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:36,873 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:36,873 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415141634] [2022-02-21 04:24:36,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:36,874 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:36,874 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:36,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:36,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:36,875 INFO L87 Difference]: Start difference. First operand 1914 states and 2831 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:38,238 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2022-02-21 04:24:38,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:38,238 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,331 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:38,332 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:38,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:38,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-02-21 04:24:38,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:38,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:38,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:38,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:38,540 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-02-21 04:24:38,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:38,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:38,578 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:38,581 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2830 transitions. Second operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,582 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2830 transitions. Second operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,584 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. Second operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:38,673 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2022-02-21 04:24:38,673 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:38,675 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:38,675 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:38,677 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2830 transitions. [2022-02-21 04:24:38,678 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2830 transitions. [2022-02-21 04:24:38,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:38,804 INFO L93 Difference]: Finished difference Result 1914 states and 2830 transitions. [2022-02-21 04:24:38,804 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:38,806 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:38,806 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:38,806 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:38,806 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:38,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4785788923719958) internal successors, (2830), 1913 states have internal predecessors, (2830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:38,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2830 transitions. [2022-02-21 04:24:38,931 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-02-21 04:24:38,931 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2830 transitions. [2022-02-21 04:24:38,931 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:24:38,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2830 transitions. [2022-02-21 04:24:38,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:38,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:38,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:38,938 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:38,938 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:38,938 INFO L791 eck$LassoCheckResult]: Stem: 43036#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 43037#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42856#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42572#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42573#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 43749#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43750#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42708#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42709#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43167#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42998#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 42999#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 42775#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 42776#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43174#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 43351#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 43505#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43542#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42788#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42789#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 43962#L1258-2 assume !(0 == ~T1_E~0); 43081#L1263-1 assume !(0 == ~T2_E~0); 43082#L1268-1 assume !(0 == ~T3_E~0); 43385#L1273-1 assume !(0 == ~T4_E~0); 43944#L1278-1 assume !(0 == ~T5_E~0); 43805#L1283-1 assume !(0 == ~T6_E~0); 43806#L1288-1 assume !(0 == ~T7_E~0); 44042#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44030#L1298-1 assume !(0 == ~T9_E~0); 43956#L1303-1 assume !(0 == ~T10_E~0); 42601#L1308-1 assume !(0 == ~T11_E~0); 42543#L1313-1 assume !(0 == ~T12_E~0); 42544#L1318-1 assume !(0 == ~T13_E~0); 42552#L1323-1 assume !(0 == ~E_1~0); 42553#L1328-1 assume !(0 == ~E_2~0); 42718#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 43677#L1338-1 assume !(0 == ~E_4~0); 43678#L1343-1 assume !(0 == ~E_5~0); 43779#L1348-1 assume !(0 == ~E_6~0); 44065#L1353-1 assume !(0 == ~E_7~0); 43404#L1358-1 assume !(0 == ~E_8~0); 43405#L1363-1 assume !(0 == ~E_9~0); 43695#L1368-1 assume !(0 == ~E_10~0); 42380#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 42381#L1378-1 assume !(0 == ~E_12~0); 42669#L1383-1 assume !(0 == ~E_13~0); 42670#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43411#L607 assume 1 == ~m_pc~0; 43412#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42738#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43777#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43331#L1560 assume !(0 != activate_threads_~tmp~1#1); 43332#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42563#L626 assume !(1 == ~t1_pc~0); 42564#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 42832#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42833#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43004#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 42465#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42466#L645 assume 1 == ~t2_pc~0; 42580#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42537#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43217#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43218#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 43307#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43308#L664 assume 1 == ~t3_pc~0; 44064#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42308#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42309#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42963#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 42964#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43972#L683 assume !(1 == ~t4_pc~0); 43527#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43479#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43480#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43514#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43638#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43261#L702 assume 1 == ~t5_pc~0; 43262#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43184#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43633#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43932#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 43873#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42352#L721 assume !(1 == ~t6_pc~0); 42326#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 42327#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42490#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42972#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 42973#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43574#L740 assume 1 == ~t7_pc~0; 42401#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42214#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42215#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42204#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 42205#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42909#L759 assume !(1 == ~t8_pc~0); 42910#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 42938#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43631#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43632#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 43763#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44041#L778 assume 1 == ~t9_pc~0; 43928#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42379#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42319#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42248#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 42249#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42577#L797 assume !(1 == ~t10_pc~0); 42578#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42695#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43829#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43079#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 43080#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43369#L816 assume 1 == ~t11_pc~0; 42284#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42285#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43042#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42979#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 42980#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43504#L835 assume 1 == ~t12_pc~0; 43382#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42448#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42470#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42611#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 43136#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43137#L854 assume !(1 == ~t13_pc~0); 42777#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 42778#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42828#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42488#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42489#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43868#L1401 assume !(1 == ~M_E~0); 42967#L1401-2 assume !(1 == ~T1_E~0); 42968#L1406-1 assume !(1 == ~T2_E~0); 43563#L1411-1 assume !(1 == ~T3_E~0); 43564#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43230#L1421-1 assume !(1 == ~T5_E~0); 42773#L1426-1 assume !(1 == ~T6_E~0); 42774#L1431-1 assume !(1 == ~T7_E~0); 42322#L1436-1 assume !(1 == ~T8_E~0); 42323#L1441-1 assume !(1 == ~T9_E~0); 43072#L1446-1 assume !(1 == ~T10_E~0); 43073#L1451-1 assume !(1 == ~T11_E~0); 43776#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43430#L1461-1 assume !(1 == ~T13_E~0); 42991#L1466-1 assume !(1 == ~E_1~0); 42992#L1471-1 assume !(1 == ~E_2~0); 43761#L1476-1 assume !(1 == ~E_3~0); 43762#L1481-1 assume !(1 == ~E_4~0); 43910#L1486-1 assume !(1 == ~E_5~0); 42616#L1491-1 assume !(1 == ~E_6~0); 42256#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 42257#L1501-1 assume !(1 == ~E_8~0); 43068#L1506-1 assume !(1 == ~E_9~0); 43069#L1511-1 assume !(1 == ~E_10~0); 43025#L1516-1 assume !(1 == ~E_11~0); 42202#L1521-1 assume !(1 == ~E_12~0); 42203#L1526-1 assume !(1 == ~E_13~0); 42255#L1531-1 assume { :end_inline_reset_delta_events } true; 42798#L1892-2 [2022-02-21 04:24:38,939 INFO L793 eck$LassoCheckResult]: Loop: 42798#L1892-2 assume !false; 43821#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44019#L1233 assume !false; 44002#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43334#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43314#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43472#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 42298#L1046 assume !(0 != eval_~tmp~0#1); 42300#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42334#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43506#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44063#L1258-5 assume !(0 == ~T1_E~0); 42478#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42479#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44055#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44061#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44062#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42702#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42703#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43818#L1298-3 assume !(0 == ~T9_E~0); 43819#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 43978#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43817#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 43318#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42480#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42481#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43902#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42621#L1338-3 assume !(0 == ~E_4~0); 42622#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43734#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43908#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43909#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43276#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42834#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42835#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 43591#L1378-3 assume !(0 == ~E_12~0); 43592#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 43773#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43774#L607-42 assume 1 == ~m_pc~0; 43389#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43115#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43116#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42848#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42849#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43370#L626-42 assume 1 == ~t1_pc~0; 42932#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42933#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43237#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43238#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42512#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42513#L645-42 assume 1 == ~t2_pc~0; 43971#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43712#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43878#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42719#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42226#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42227#L664-42 assume !(1 == ~t3_pc~0); 42753#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 42754#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44005#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43540#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43541#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43706#L683-42 assume !(1 == ~t4_pc~0); 43414#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 43415#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43546#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43967#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43968#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43812#L702-42 assume 1 == ~t5_pc~0; 43300#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42925#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43221#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43894#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42242#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42243#L721-42 assume 1 == ~t6_pc~0; 42396#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42416#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42880#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44047#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43052#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42898#L740-42 assume 1 == ~t7_pc~0; 42899#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42636#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43177#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43032#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 43033#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43306#L759-42 assume 1 == ~t8_pc~0; 43155#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43087#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43088#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43165#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 43166#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43260#L778-42 assume 1 == ~t9_pc~0; 43099#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43101#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43510#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 43416#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 43417#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43474#L797-42 assume 1 == ~t10_pc~0; 42641#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42642#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43643#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43952#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43512#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43513#L816-42 assume !(1 == ~t11_pc~0); 42192#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 42191#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42733#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42734#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42813#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42814#L835-42 assume 1 == ~t12_pc~0; 43216#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 43108#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42786#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42787#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43871#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43655#L854-42 assume 1 == ~t13_pc~0; 43656#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42730#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42342#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42343#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42989#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42990#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43768#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42576#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42443#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42444#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43043#L1421-3 assume !(1 == ~T5_E~0); 43044#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42619#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42620#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42206#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42207#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43796#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43127#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42780#L1461-3 assume !(1 == ~T13_E~0); 42781#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44058#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42720#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42721#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 43121#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42748#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42749#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43160#L1501-3 assume !(1 == ~E_8~0); 43161#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43588#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 43578#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43579#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 43278#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 43279#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43673#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42555#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43448#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 43089#L1911 assume !(0 == start_simulation_~tmp~3#1); 43090#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43612#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42679#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43550#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 42384#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42385#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42614#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 42615#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 42798#L1892-2 [2022-02-21 04:24:38,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:38,940 INFO L85 PathProgramCache]: Analyzing trace with hash 1274281632, now seen corresponding path program 1 times [2022-02-21 04:24:38,940 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:38,940 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449752738] [2022-02-21 04:24:38,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:38,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:38,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:38,978 INFO L290 TraceCheckUtils]: 0: Hoare triple {47920#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {47920#true} is VALID [2022-02-21 04:24:38,978 INFO L290 TraceCheckUtils]: 1: Hoare triple {47920#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {47922#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:38,979 INFO L290 TraceCheckUtils]: 2: Hoare triple {47922#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {47922#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:38,979 INFO L290 TraceCheckUtils]: 3: Hoare triple {47922#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {47922#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:38,979 INFO L290 TraceCheckUtils]: 4: Hoare triple {47922#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {47922#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:38,980 INFO L290 TraceCheckUtils]: 5: Hoare triple {47922#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {47922#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:38,980 INFO L290 TraceCheckUtils]: 6: Hoare triple {47922#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {47922#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:38,980 INFO L290 TraceCheckUtils]: 7: Hoare triple {47922#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {47922#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:38,981 INFO L290 TraceCheckUtils]: 8: Hoare triple {47922#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {47922#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:38,981 INFO L290 TraceCheckUtils]: 9: Hoare triple {47922#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {47922#(= ~t6_i~0 1)} is VALID [2022-02-21 04:24:38,981 INFO L290 TraceCheckUtils]: 10: Hoare triple {47922#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {47921#false} is VALID [2022-02-21 04:24:38,982 INFO L290 TraceCheckUtils]: 11: Hoare triple {47921#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {47921#false} is VALID [2022-02-21 04:24:38,982 INFO L290 TraceCheckUtils]: 12: Hoare triple {47921#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {47921#false} is VALID [2022-02-21 04:24:38,982 INFO L290 TraceCheckUtils]: 13: Hoare triple {47921#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {47921#false} is VALID [2022-02-21 04:24:38,982 INFO L290 TraceCheckUtils]: 14: Hoare triple {47921#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {47921#false} is VALID [2022-02-21 04:24:38,982 INFO L290 TraceCheckUtils]: 15: Hoare triple {47921#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {47921#false} is VALID [2022-02-21 04:24:38,982 INFO L290 TraceCheckUtils]: 16: Hoare triple {47921#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {47921#false} is VALID [2022-02-21 04:24:38,982 INFO L290 TraceCheckUtils]: 17: Hoare triple {47921#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {47921#false} is VALID [2022-02-21 04:24:38,983 INFO L290 TraceCheckUtils]: 18: Hoare triple {47921#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {47921#false} is VALID [2022-02-21 04:24:38,983 INFO L290 TraceCheckUtils]: 19: Hoare triple {47921#false} assume 0 == ~M_E~0;~M_E~0 := 1; {47921#false} is VALID [2022-02-21 04:24:38,983 INFO L290 TraceCheckUtils]: 20: Hoare triple {47921#false} assume !(0 == ~T1_E~0); {47921#false} is VALID [2022-02-21 04:24:38,983 INFO L290 TraceCheckUtils]: 21: Hoare triple {47921#false} assume !(0 == ~T2_E~0); {47921#false} is VALID [2022-02-21 04:24:38,983 INFO L290 TraceCheckUtils]: 22: Hoare triple {47921#false} assume !(0 == ~T3_E~0); {47921#false} is VALID [2022-02-21 04:24:38,983 INFO L290 TraceCheckUtils]: 23: Hoare triple {47921#false} assume !(0 == ~T4_E~0); {47921#false} is VALID [2022-02-21 04:24:38,983 INFO L290 TraceCheckUtils]: 24: Hoare triple {47921#false} assume !(0 == ~T5_E~0); {47921#false} is VALID [2022-02-21 04:24:38,984 INFO L290 TraceCheckUtils]: 25: Hoare triple {47921#false} assume !(0 == ~T6_E~0); {47921#false} is VALID [2022-02-21 04:24:38,984 INFO L290 TraceCheckUtils]: 26: Hoare triple {47921#false} assume !(0 == ~T7_E~0); {47921#false} is VALID [2022-02-21 04:24:38,984 INFO L290 TraceCheckUtils]: 27: Hoare triple {47921#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {47921#false} is VALID [2022-02-21 04:24:38,984 INFO L290 TraceCheckUtils]: 28: Hoare triple {47921#false} assume !(0 == ~T9_E~0); {47921#false} is VALID [2022-02-21 04:24:38,984 INFO L290 TraceCheckUtils]: 29: Hoare triple {47921#false} assume !(0 == ~T10_E~0); {47921#false} is VALID [2022-02-21 04:24:38,984 INFO L290 TraceCheckUtils]: 30: Hoare triple {47921#false} assume !(0 == ~T11_E~0); {47921#false} is VALID [2022-02-21 04:24:38,984 INFO L290 TraceCheckUtils]: 31: Hoare triple {47921#false} assume !(0 == ~T12_E~0); {47921#false} is VALID [2022-02-21 04:24:38,985 INFO L290 TraceCheckUtils]: 32: Hoare triple {47921#false} assume !(0 == ~T13_E~0); {47921#false} is VALID [2022-02-21 04:24:38,985 INFO L290 TraceCheckUtils]: 33: Hoare triple {47921#false} assume !(0 == ~E_1~0); {47921#false} is VALID [2022-02-21 04:24:38,985 INFO L290 TraceCheckUtils]: 34: Hoare triple {47921#false} assume !(0 == ~E_2~0); {47921#false} is VALID [2022-02-21 04:24:38,985 INFO L290 TraceCheckUtils]: 35: Hoare triple {47921#false} assume 0 == ~E_3~0;~E_3~0 := 1; {47921#false} is VALID [2022-02-21 04:24:38,985 INFO L290 TraceCheckUtils]: 36: Hoare triple {47921#false} assume !(0 == ~E_4~0); {47921#false} is VALID [2022-02-21 04:24:38,985 INFO L290 TraceCheckUtils]: 37: Hoare triple {47921#false} assume !(0 == ~E_5~0); {47921#false} is VALID [2022-02-21 04:24:38,985 INFO L290 TraceCheckUtils]: 38: Hoare triple {47921#false} assume !(0 == ~E_6~0); {47921#false} is VALID [2022-02-21 04:24:38,986 INFO L290 TraceCheckUtils]: 39: Hoare triple {47921#false} assume !(0 == ~E_7~0); {47921#false} is VALID [2022-02-21 04:24:38,986 INFO L290 TraceCheckUtils]: 40: Hoare triple {47921#false} assume !(0 == ~E_8~0); {47921#false} is VALID [2022-02-21 04:24:38,986 INFO L290 TraceCheckUtils]: 41: Hoare triple {47921#false} assume !(0 == ~E_9~0); {47921#false} is VALID [2022-02-21 04:24:38,986 INFO L290 TraceCheckUtils]: 42: Hoare triple {47921#false} assume !(0 == ~E_10~0); {47921#false} is VALID [2022-02-21 04:24:38,986 INFO L290 TraceCheckUtils]: 43: Hoare triple {47921#false} assume 0 == ~E_11~0;~E_11~0 := 1; {47921#false} is VALID [2022-02-21 04:24:38,986 INFO L290 TraceCheckUtils]: 44: Hoare triple {47921#false} assume !(0 == ~E_12~0); {47921#false} is VALID [2022-02-21 04:24:38,986 INFO L290 TraceCheckUtils]: 45: Hoare triple {47921#false} assume !(0 == ~E_13~0); {47921#false} is VALID [2022-02-21 04:24:38,987 INFO L290 TraceCheckUtils]: 46: Hoare triple {47921#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {47921#false} is VALID [2022-02-21 04:24:38,987 INFO L290 TraceCheckUtils]: 47: Hoare triple {47921#false} assume 1 == ~m_pc~0; {47921#false} is VALID [2022-02-21 04:24:38,987 INFO L290 TraceCheckUtils]: 48: Hoare triple {47921#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {47921#false} is VALID [2022-02-21 04:24:38,987 INFO L290 TraceCheckUtils]: 49: Hoare triple {47921#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {47921#false} is VALID [2022-02-21 04:24:38,987 INFO L290 TraceCheckUtils]: 50: Hoare triple {47921#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {47921#false} is VALID [2022-02-21 04:24:38,988 INFO L290 TraceCheckUtils]: 51: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp~1#1); {47921#false} is VALID [2022-02-21 04:24:38,989 INFO L290 TraceCheckUtils]: 52: Hoare triple {47921#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {47921#false} is VALID [2022-02-21 04:24:38,989 INFO L290 TraceCheckUtils]: 53: Hoare triple {47921#false} assume !(1 == ~t1_pc~0); {47921#false} is VALID [2022-02-21 04:24:38,989 INFO L290 TraceCheckUtils]: 54: Hoare triple {47921#false} is_transmit1_triggered_~__retres1~1#1 := 0; {47921#false} is VALID [2022-02-21 04:24:38,989 INFO L290 TraceCheckUtils]: 55: Hoare triple {47921#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {47921#false} is VALID [2022-02-21 04:24:38,989 INFO L290 TraceCheckUtils]: 56: Hoare triple {47921#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {47921#false} is VALID [2022-02-21 04:24:38,989 INFO L290 TraceCheckUtils]: 57: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp___0~0#1); {47921#false} is VALID [2022-02-21 04:24:38,989 INFO L290 TraceCheckUtils]: 58: Hoare triple {47921#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {47921#false} is VALID [2022-02-21 04:24:38,990 INFO L290 TraceCheckUtils]: 59: Hoare triple {47921#false} assume 1 == ~t2_pc~0; {47921#false} is VALID [2022-02-21 04:24:38,990 INFO L290 TraceCheckUtils]: 60: Hoare triple {47921#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {47921#false} is VALID [2022-02-21 04:24:38,990 INFO L290 TraceCheckUtils]: 61: Hoare triple {47921#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {47921#false} is VALID [2022-02-21 04:24:38,990 INFO L290 TraceCheckUtils]: 62: Hoare triple {47921#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {47921#false} is VALID [2022-02-21 04:24:38,990 INFO L290 TraceCheckUtils]: 63: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp___1~0#1); {47921#false} is VALID [2022-02-21 04:24:38,990 INFO L290 TraceCheckUtils]: 64: Hoare triple {47921#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {47921#false} is VALID [2022-02-21 04:24:38,990 INFO L290 TraceCheckUtils]: 65: Hoare triple {47921#false} assume 1 == ~t3_pc~0; {47921#false} is VALID [2022-02-21 04:24:38,991 INFO L290 TraceCheckUtils]: 66: Hoare triple {47921#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {47921#false} is VALID [2022-02-21 04:24:38,991 INFO L290 TraceCheckUtils]: 67: Hoare triple {47921#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {47921#false} is VALID [2022-02-21 04:24:38,991 INFO L290 TraceCheckUtils]: 68: Hoare triple {47921#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {47921#false} is VALID [2022-02-21 04:24:38,991 INFO L290 TraceCheckUtils]: 69: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp___2~0#1); {47921#false} is VALID [2022-02-21 04:24:38,991 INFO L290 TraceCheckUtils]: 70: Hoare triple {47921#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {47921#false} is VALID [2022-02-21 04:24:38,991 INFO L290 TraceCheckUtils]: 71: Hoare triple {47921#false} assume !(1 == ~t4_pc~0); {47921#false} is VALID [2022-02-21 04:24:38,991 INFO L290 TraceCheckUtils]: 72: Hoare triple {47921#false} is_transmit4_triggered_~__retres1~4#1 := 0; {47921#false} is VALID [2022-02-21 04:24:38,992 INFO L290 TraceCheckUtils]: 73: Hoare triple {47921#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {47921#false} is VALID [2022-02-21 04:24:38,992 INFO L290 TraceCheckUtils]: 74: Hoare triple {47921#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {47921#false} is VALID [2022-02-21 04:24:38,992 INFO L290 TraceCheckUtils]: 75: Hoare triple {47921#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {47921#false} is VALID [2022-02-21 04:24:38,992 INFO L290 TraceCheckUtils]: 76: Hoare triple {47921#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {47921#false} is VALID [2022-02-21 04:24:38,992 INFO L290 TraceCheckUtils]: 77: Hoare triple {47921#false} assume 1 == ~t5_pc~0; {47921#false} is VALID [2022-02-21 04:24:38,992 INFO L290 TraceCheckUtils]: 78: Hoare triple {47921#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {47921#false} is VALID [2022-02-21 04:24:38,992 INFO L290 TraceCheckUtils]: 79: Hoare triple {47921#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {47921#false} is VALID [2022-02-21 04:24:38,993 INFO L290 TraceCheckUtils]: 80: Hoare triple {47921#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {47921#false} is VALID [2022-02-21 04:24:38,993 INFO L290 TraceCheckUtils]: 81: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp___4~0#1); {47921#false} is VALID [2022-02-21 04:24:38,993 INFO L290 TraceCheckUtils]: 82: Hoare triple {47921#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {47921#false} is VALID [2022-02-21 04:24:38,993 INFO L290 TraceCheckUtils]: 83: Hoare triple {47921#false} assume !(1 == ~t6_pc~0); {47921#false} is VALID [2022-02-21 04:24:38,993 INFO L290 TraceCheckUtils]: 84: Hoare triple {47921#false} is_transmit6_triggered_~__retres1~6#1 := 0; {47921#false} is VALID [2022-02-21 04:24:38,993 INFO L290 TraceCheckUtils]: 85: Hoare triple {47921#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {47921#false} is VALID [2022-02-21 04:24:38,993 INFO L290 TraceCheckUtils]: 86: Hoare triple {47921#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {47921#false} is VALID [2022-02-21 04:24:38,994 INFO L290 TraceCheckUtils]: 87: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp___5~0#1); {47921#false} is VALID [2022-02-21 04:24:38,994 INFO L290 TraceCheckUtils]: 88: Hoare triple {47921#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {47921#false} is VALID [2022-02-21 04:24:38,994 INFO L290 TraceCheckUtils]: 89: Hoare triple {47921#false} assume 1 == ~t7_pc~0; {47921#false} is VALID [2022-02-21 04:24:38,994 INFO L290 TraceCheckUtils]: 90: Hoare triple {47921#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {47921#false} is VALID [2022-02-21 04:24:38,994 INFO L290 TraceCheckUtils]: 91: Hoare triple {47921#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {47921#false} is VALID [2022-02-21 04:24:38,994 INFO L290 TraceCheckUtils]: 92: Hoare triple {47921#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {47921#false} is VALID [2022-02-21 04:24:38,994 INFO L290 TraceCheckUtils]: 93: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp___6~0#1); {47921#false} is VALID [2022-02-21 04:24:38,995 INFO L290 TraceCheckUtils]: 94: Hoare triple {47921#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {47921#false} is VALID [2022-02-21 04:24:38,995 INFO L290 TraceCheckUtils]: 95: Hoare triple {47921#false} assume !(1 == ~t8_pc~0); {47921#false} is VALID [2022-02-21 04:24:38,995 INFO L290 TraceCheckUtils]: 96: Hoare triple {47921#false} is_transmit8_triggered_~__retres1~8#1 := 0; {47921#false} is VALID [2022-02-21 04:24:38,995 INFO L290 TraceCheckUtils]: 97: Hoare triple {47921#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {47921#false} is VALID [2022-02-21 04:24:38,995 INFO L290 TraceCheckUtils]: 98: Hoare triple {47921#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {47921#false} is VALID [2022-02-21 04:24:38,995 INFO L290 TraceCheckUtils]: 99: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp___7~0#1); {47921#false} is VALID [2022-02-21 04:24:38,995 INFO L290 TraceCheckUtils]: 100: Hoare triple {47921#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {47921#false} is VALID [2022-02-21 04:24:38,996 INFO L290 TraceCheckUtils]: 101: Hoare triple {47921#false} assume 1 == ~t9_pc~0; {47921#false} is VALID [2022-02-21 04:24:38,996 INFO L290 TraceCheckUtils]: 102: Hoare triple {47921#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {47921#false} is VALID [2022-02-21 04:24:38,996 INFO L290 TraceCheckUtils]: 103: Hoare triple {47921#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {47921#false} is VALID [2022-02-21 04:24:38,996 INFO L290 TraceCheckUtils]: 104: Hoare triple {47921#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {47921#false} is VALID [2022-02-21 04:24:38,996 INFO L290 TraceCheckUtils]: 105: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp___8~0#1); {47921#false} is VALID [2022-02-21 04:24:38,996 INFO L290 TraceCheckUtils]: 106: Hoare triple {47921#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {47921#false} is VALID [2022-02-21 04:24:38,996 INFO L290 TraceCheckUtils]: 107: Hoare triple {47921#false} assume !(1 == ~t10_pc~0); {47921#false} is VALID [2022-02-21 04:24:38,997 INFO L290 TraceCheckUtils]: 108: Hoare triple {47921#false} is_transmit10_triggered_~__retres1~10#1 := 0; {47921#false} is VALID [2022-02-21 04:24:38,997 INFO L290 TraceCheckUtils]: 109: Hoare triple {47921#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {47921#false} is VALID [2022-02-21 04:24:38,997 INFO L290 TraceCheckUtils]: 110: Hoare triple {47921#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {47921#false} is VALID [2022-02-21 04:24:38,997 INFO L290 TraceCheckUtils]: 111: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp___9~0#1); {47921#false} is VALID [2022-02-21 04:24:38,997 INFO L290 TraceCheckUtils]: 112: Hoare triple {47921#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {47921#false} is VALID [2022-02-21 04:24:38,997 INFO L290 TraceCheckUtils]: 113: Hoare triple {47921#false} assume 1 == ~t11_pc~0; {47921#false} is VALID [2022-02-21 04:24:38,997 INFO L290 TraceCheckUtils]: 114: Hoare triple {47921#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {47921#false} is VALID [2022-02-21 04:24:38,998 INFO L290 TraceCheckUtils]: 115: Hoare triple {47921#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {47921#false} is VALID [2022-02-21 04:24:38,998 INFO L290 TraceCheckUtils]: 116: Hoare triple {47921#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {47921#false} is VALID [2022-02-21 04:24:38,998 INFO L290 TraceCheckUtils]: 117: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp___10~0#1); {47921#false} is VALID [2022-02-21 04:24:38,998 INFO L290 TraceCheckUtils]: 118: Hoare triple {47921#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {47921#false} is VALID [2022-02-21 04:24:38,998 INFO L290 TraceCheckUtils]: 119: Hoare triple {47921#false} assume 1 == ~t12_pc~0; {47921#false} is VALID [2022-02-21 04:24:38,998 INFO L290 TraceCheckUtils]: 120: Hoare triple {47921#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {47921#false} is VALID [2022-02-21 04:24:38,999 INFO L290 TraceCheckUtils]: 121: Hoare triple {47921#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {47921#false} is VALID [2022-02-21 04:24:38,999 INFO L290 TraceCheckUtils]: 122: Hoare triple {47921#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {47921#false} is VALID [2022-02-21 04:24:38,999 INFO L290 TraceCheckUtils]: 123: Hoare triple {47921#false} assume !(0 != activate_threads_~tmp___11~0#1); {47921#false} is VALID [2022-02-21 04:24:38,999 INFO L290 TraceCheckUtils]: 124: Hoare triple {47921#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {47921#false} is VALID [2022-02-21 04:24:38,999 INFO L290 TraceCheckUtils]: 125: Hoare triple {47921#false} assume !(1 == ~t13_pc~0); {47921#false} is VALID [2022-02-21 04:24:38,999 INFO L290 TraceCheckUtils]: 126: Hoare triple {47921#false} is_transmit13_triggered_~__retres1~13#1 := 0; {47921#false} is VALID [2022-02-21 04:24:38,999 INFO L290 TraceCheckUtils]: 127: Hoare triple {47921#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {47921#false} is VALID [2022-02-21 04:24:39,000 INFO L290 TraceCheckUtils]: 128: Hoare triple {47921#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {47921#false} is VALID [2022-02-21 04:24:39,000 INFO L290 TraceCheckUtils]: 129: Hoare triple {47921#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {47921#false} is VALID [2022-02-21 04:24:39,000 INFO L290 TraceCheckUtils]: 130: Hoare triple {47921#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {47921#false} is VALID [2022-02-21 04:24:39,000 INFO L290 TraceCheckUtils]: 131: Hoare triple {47921#false} assume !(1 == ~M_E~0); {47921#false} is VALID [2022-02-21 04:24:39,000 INFO L290 TraceCheckUtils]: 132: Hoare triple {47921#false} assume !(1 == ~T1_E~0); {47921#false} is VALID [2022-02-21 04:24:39,000 INFO L290 TraceCheckUtils]: 133: Hoare triple {47921#false} assume !(1 == ~T2_E~0); {47921#false} is VALID [2022-02-21 04:24:39,000 INFO L290 TraceCheckUtils]: 134: Hoare triple {47921#false} assume !(1 == ~T3_E~0); {47921#false} is VALID [2022-02-21 04:24:39,001 INFO L290 TraceCheckUtils]: 135: Hoare triple {47921#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {47921#false} is VALID [2022-02-21 04:24:39,001 INFO L290 TraceCheckUtils]: 136: Hoare triple {47921#false} assume !(1 == ~T5_E~0); {47921#false} is VALID [2022-02-21 04:24:39,001 INFO L290 TraceCheckUtils]: 137: Hoare triple {47921#false} assume !(1 == ~T6_E~0); {47921#false} is VALID [2022-02-21 04:24:39,001 INFO L290 TraceCheckUtils]: 138: Hoare triple {47921#false} assume !(1 == ~T7_E~0); {47921#false} is VALID [2022-02-21 04:24:39,001 INFO L290 TraceCheckUtils]: 139: Hoare triple {47921#false} assume !(1 == ~T8_E~0); {47921#false} is VALID [2022-02-21 04:24:39,001 INFO L290 TraceCheckUtils]: 140: Hoare triple {47921#false} assume !(1 == ~T9_E~0); {47921#false} is VALID [2022-02-21 04:24:39,001 INFO L290 TraceCheckUtils]: 141: Hoare triple {47921#false} assume !(1 == ~T10_E~0); {47921#false} is VALID [2022-02-21 04:24:39,002 INFO L290 TraceCheckUtils]: 142: Hoare triple {47921#false} assume !(1 == ~T11_E~0); {47921#false} is VALID [2022-02-21 04:24:39,002 INFO L290 TraceCheckUtils]: 143: Hoare triple {47921#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {47921#false} is VALID [2022-02-21 04:24:39,002 INFO L290 TraceCheckUtils]: 144: Hoare triple {47921#false} assume !(1 == ~T13_E~0); {47921#false} is VALID [2022-02-21 04:24:39,002 INFO L290 TraceCheckUtils]: 145: Hoare triple {47921#false} assume !(1 == ~E_1~0); {47921#false} is VALID [2022-02-21 04:24:39,002 INFO L290 TraceCheckUtils]: 146: Hoare triple {47921#false} assume !(1 == ~E_2~0); {47921#false} is VALID [2022-02-21 04:24:39,002 INFO L290 TraceCheckUtils]: 147: Hoare triple {47921#false} assume !(1 == ~E_3~0); {47921#false} is VALID [2022-02-21 04:24:39,002 INFO L290 TraceCheckUtils]: 148: Hoare triple {47921#false} assume !(1 == ~E_4~0); {47921#false} is VALID [2022-02-21 04:24:39,003 INFO L290 TraceCheckUtils]: 149: Hoare triple {47921#false} assume !(1 == ~E_5~0); {47921#false} is VALID [2022-02-21 04:24:39,003 INFO L290 TraceCheckUtils]: 150: Hoare triple {47921#false} assume !(1 == ~E_6~0); {47921#false} is VALID [2022-02-21 04:24:39,003 INFO L290 TraceCheckUtils]: 151: Hoare triple {47921#false} assume 1 == ~E_7~0;~E_7~0 := 2; {47921#false} is VALID [2022-02-21 04:24:39,003 INFO L290 TraceCheckUtils]: 152: Hoare triple {47921#false} assume !(1 == ~E_8~0); {47921#false} is VALID [2022-02-21 04:24:39,003 INFO L290 TraceCheckUtils]: 153: Hoare triple {47921#false} assume !(1 == ~E_9~0); {47921#false} is VALID [2022-02-21 04:24:39,003 INFO L290 TraceCheckUtils]: 154: Hoare triple {47921#false} assume !(1 == ~E_10~0); {47921#false} is VALID [2022-02-21 04:24:39,003 INFO L290 TraceCheckUtils]: 155: Hoare triple {47921#false} assume !(1 == ~E_11~0); {47921#false} is VALID [2022-02-21 04:24:39,004 INFO L290 TraceCheckUtils]: 156: Hoare triple {47921#false} assume !(1 == ~E_12~0); {47921#false} is VALID [2022-02-21 04:24:39,004 INFO L290 TraceCheckUtils]: 157: Hoare triple {47921#false} assume !(1 == ~E_13~0); {47921#false} is VALID [2022-02-21 04:24:39,004 INFO L290 TraceCheckUtils]: 158: Hoare triple {47921#false} assume { :end_inline_reset_delta_events } true; {47921#false} is VALID [2022-02-21 04:24:39,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:39,005 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:39,005 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1449752738] [2022-02-21 04:24:39,005 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1449752738] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:39,005 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:39,005 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:39,005 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864533250] [2022-02-21 04:24:39,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:39,006 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:39,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:39,007 INFO L85 PathProgramCache]: Analyzing trace with hash 1044140384, now seen corresponding path program 1 times [2022-02-21 04:24:39,007 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:39,007 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277683863] [2022-02-21 04:24:39,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:39,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:39,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:39,057 INFO L290 TraceCheckUtils]: 0: Hoare triple {47923#true} assume !false; {47923#true} is VALID [2022-02-21 04:24:39,063 INFO L290 TraceCheckUtils]: 1: Hoare triple {47923#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {47923#true} is VALID [2022-02-21 04:24:39,063 INFO L290 TraceCheckUtils]: 2: Hoare triple {47923#true} assume !false; {47923#true} is VALID [2022-02-21 04:24:39,063 INFO L290 TraceCheckUtils]: 3: Hoare triple {47923#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {47923#true} is VALID [2022-02-21 04:24:39,063 INFO L290 TraceCheckUtils]: 4: Hoare triple {47923#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {47923#true} is VALID [2022-02-21 04:24:39,063 INFO L290 TraceCheckUtils]: 5: Hoare triple {47923#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {47923#true} is VALID [2022-02-21 04:24:39,064 INFO L290 TraceCheckUtils]: 6: Hoare triple {47923#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {47923#true} is VALID [2022-02-21 04:24:39,064 INFO L290 TraceCheckUtils]: 7: Hoare triple {47923#true} assume !(0 != eval_~tmp~0#1); {47923#true} is VALID [2022-02-21 04:24:39,064 INFO L290 TraceCheckUtils]: 8: Hoare triple {47923#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {47923#true} is VALID [2022-02-21 04:24:39,064 INFO L290 TraceCheckUtils]: 9: Hoare triple {47923#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {47923#true} is VALID [2022-02-21 04:24:39,064 INFO L290 TraceCheckUtils]: 10: Hoare triple {47923#true} assume 0 == ~M_E~0;~M_E~0 := 1; {47923#true} is VALID [2022-02-21 04:24:39,064 INFO L290 TraceCheckUtils]: 11: Hoare triple {47923#true} assume !(0 == ~T1_E~0); {47923#true} is VALID [2022-02-21 04:24:39,064 INFO L290 TraceCheckUtils]: 12: Hoare triple {47923#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {47923#true} is VALID [2022-02-21 04:24:39,065 INFO L290 TraceCheckUtils]: 13: Hoare triple {47923#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {47923#true} is VALID [2022-02-21 04:24:39,065 INFO L290 TraceCheckUtils]: 14: Hoare triple {47923#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {47923#true} is VALID [2022-02-21 04:24:39,065 INFO L290 TraceCheckUtils]: 15: Hoare triple {47923#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,066 INFO L290 TraceCheckUtils]: 16: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,066 INFO L290 TraceCheckUtils]: 17: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,066 INFO L290 TraceCheckUtils]: 18: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,067 INFO L290 TraceCheckUtils]: 19: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,067 INFO L290 TraceCheckUtils]: 20: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,068 INFO L290 TraceCheckUtils]: 21: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,068 INFO L290 TraceCheckUtils]: 22: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,068 INFO L290 TraceCheckUtils]: 23: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,069 INFO L290 TraceCheckUtils]: 24: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,069 INFO L290 TraceCheckUtils]: 25: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,070 INFO L290 TraceCheckUtils]: 26: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,070 INFO L290 TraceCheckUtils]: 27: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,070 INFO L290 TraceCheckUtils]: 28: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,071 INFO L290 TraceCheckUtils]: 29: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,071 INFO L290 TraceCheckUtils]: 30: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,071 INFO L290 TraceCheckUtils]: 31: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,072 INFO L290 TraceCheckUtils]: 32: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,072 INFO L290 TraceCheckUtils]: 33: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,073 INFO L290 TraceCheckUtils]: 34: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,073 INFO L290 TraceCheckUtils]: 35: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,073 INFO L290 TraceCheckUtils]: 36: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,074 INFO L290 TraceCheckUtils]: 37: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,074 INFO L290 TraceCheckUtils]: 38: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,075 INFO L290 TraceCheckUtils]: 39: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,075 INFO L290 TraceCheckUtils]: 40: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,075 INFO L290 TraceCheckUtils]: 41: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,076 INFO L290 TraceCheckUtils]: 42: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,076 INFO L290 TraceCheckUtils]: 43: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,076 INFO L290 TraceCheckUtils]: 44: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,077 INFO L290 TraceCheckUtils]: 45: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,077 INFO L290 TraceCheckUtils]: 46: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,078 INFO L290 TraceCheckUtils]: 47: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,078 INFO L290 TraceCheckUtils]: 48: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,078 INFO L290 TraceCheckUtils]: 49: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,079 INFO L290 TraceCheckUtils]: 50: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t2_pc~0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,079 INFO L290 TraceCheckUtils]: 51: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,079 INFO L290 TraceCheckUtils]: 52: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,080 INFO L290 TraceCheckUtils]: 53: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,080 INFO L290 TraceCheckUtils]: 54: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,081 INFO L290 TraceCheckUtils]: 55: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,081 INFO L290 TraceCheckUtils]: 56: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,081 INFO L290 TraceCheckUtils]: 57: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,082 INFO L290 TraceCheckUtils]: 58: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,082 INFO L290 TraceCheckUtils]: 59: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,083 INFO L290 TraceCheckUtils]: 60: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,083 INFO L290 TraceCheckUtils]: 61: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,083 INFO L290 TraceCheckUtils]: 62: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,084 INFO L290 TraceCheckUtils]: 63: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,084 INFO L290 TraceCheckUtils]: 64: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,084 INFO L290 TraceCheckUtils]: 65: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,085 INFO L290 TraceCheckUtils]: 66: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,085 INFO L290 TraceCheckUtils]: 67: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,086 INFO L290 TraceCheckUtils]: 68: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,086 INFO L290 TraceCheckUtils]: 69: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,086 INFO L290 TraceCheckUtils]: 70: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,087 INFO L290 TraceCheckUtils]: 71: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,087 INFO L290 TraceCheckUtils]: 72: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,088 INFO L290 TraceCheckUtils]: 73: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,088 INFO L290 TraceCheckUtils]: 74: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,088 INFO L290 TraceCheckUtils]: 75: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,089 INFO L290 TraceCheckUtils]: 76: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,089 INFO L290 TraceCheckUtils]: 77: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,090 INFO L290 TraceCheckUtils]: 78: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,090 INFO L290 TraceCheckUtils]: 79: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,090 INFO L290 TraceCheckUtils]: 80: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,091 INFO L290 TraceCheckUtils]: 81: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,091 INFO L290 TraceCheckUtils]: 82: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,091 INFO L290 TraceCheckUtils]: 83: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,092 INFO L290 TraceCheckUtils]: 84: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,092 INFO L290 TraceCheckUtils]: 85: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,093 INFO L290 TraceCheckUtils]: 86: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,093 INFO L290 TraceCheckUtils]: 87: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,093 INFO L290 TraceCheckUtils]: 88: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,094 INFO L290 TraceCheckUtils]: 89: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,094 INFO L290 TraceCheckUtils]: 90: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,094 INFO L290 TraceCheckUtils]: 91: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,095 INFO L290 TraceCheckUtils]: 92: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,095 INFO L290 TraceCheckUtils]: 93: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,096 INFO L290 TraceCheckUtils]: 94: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,096 INFO L290 TraceCheckUtils]: 95: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,096 INFO L290 TraceCheckUtils]: 96: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,097 INFO L290 TraceCheckUtils]: 97: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,097 INFO L290 TraceCheckUtils]: 98: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,098 INFO L290 TraceCheckUtils]: 99: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,098 INFO L290 TraceCheckUtils]: 100: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,098 INFO L290 TraceCheckUtils]: 101: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,099 INFO L290 TraceCheckUtils]: 102: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,099 INFO L290 TraceCheckUtils]: 103: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,099 INFO L290 TraceCheckUtils]: 104: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,100 INFO L290 TraceCheckUtils]: 105: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,100 INFO L290 TraceCheckUtils]: 106: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,101 INFO L290 TraceCheckUtils]: 107: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,101 INFO L290 TraceCheckUtils]: 108: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,101 INFO L290 TraceCheckUtils]: 109: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,102 INFO L290 TraceCheckUtils]: 110: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,102 INFO L290 TraceCheckUtils]: 111: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,103 INFO L290 TraceCheckUtils]: 112: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,103 INFO L290 TraceCheckUtils]: 113: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,103 INFO L290 TraceCheckUtils]: 114: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,104 INFO L290 TraceCheckUtils]: 115: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,104 INFO L290 TraceCheckUtils]: 116: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,104 INFO L290 TraceCheckUtils]: 117: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,105 INFO L290 TraceCheckUtils]: 118: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,105 INFO L290 TraceCheckUtils]: 119: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,106 INFO L290 TraceCheckUtils]: 120: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,106 INFO L290 TraceCheckUtils]: 121: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,106 INFO L290 TraceCheckUtils]: 122: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,107 INFO L290 TraceCheckUtils]: 123: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,107 INFO L290 TraceCheckUtils]: 124: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,107 INFO L290 TraceCheckUtils]: 125: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,108 INFO L290 TraceCheckUtils]: 126: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {47925#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:39,108 INFO L290 TraceCheckUtils]: 127: Hoare triple {47925#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {47924#false} is VALID [2022-02-21 04:24:39,108 INFO L290 TraceCheckUtils]: 128: Hoare triple {47924#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,109 INFO L290 TraceCheckUtils]: 129: Hoare triple {47924#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,109 INFO L290 TraceCheckUtils]: 130: Hoare triple {47924#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,109 INFO L290 TraceCheckUtils]: 131: Hoare triple {47924#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,109 INFO L290 TraceCheckUtils]: 132: Hoare triple {47924#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,109 INFO L290 TraceCheckUtils]: 133: Hoare triple {47924#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,109 INFO L290 TraceCheckUtils]: 134: Hoare triple {47924#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,109 INFO L290 TraceCheckUtils]: 135: Hoare triple {47924#false} assume !(1 == ~T13_E~0); {47924#false} is VALID [2022-02-21 04:24:39,110 INFO L290 TraceCheckUtils]: 136: Hoare triple {47924#false} assume 1 == ~E_1~0;~E_1~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,110 INFO L290 TraceCheckUtils]: 137: Hoare triple {47924#false} assume 1 == ~E_2~0;~E_2~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,110 INFO L290 TraceCheckUtils]: 138: Hoare triple {47924#false} assume 1 == ~E_3~0;~E_3~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,110 INFO L290 TraceCheckUtils]: 139: Hoare triple {47924#false} assume 1 == ~E_4~0;~E_4~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,110 INFO L290 TraceCheckUtils]: 140: Hoare triple {47924#false} assume 1 == ~E_5~0;~E_5~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,110 INFO L290 TraceCheckUtils]: 141: Hoare triple {47924#false} assume 1 == ~E_6~0;~E_6~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,110 INFO L290 TraceCheckUtils]: 142: Hoare triple {47924#false} assume 1 == ~E_7~0;~E_7~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,111 INFO L290 TraceCheckUtils]: 143: Hoare triple {47924#false} assume !(1 == ~E_8~0); {47924#false} is VALID [2022-02-21 04:24:39,111 INFO L290 TraceCheckUtils]: 144: Hoare triple {47924#false} assume 1 == ~E_9~0;~E_9~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,111 INFO L290 TraceCheckUtils]: 145: Hoare triple {47924#false} assume 1 == ~E_10~0;~E_10~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,111 INFO L290 TraceCheckUtils]: 146: Hoare triple {47924#false} assume 1 == ~E_11~0;~E_11~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,111 INFO L290 TraceCheckUtils]: 147: Hoare triple {47924#false} assume 1 == ~E_12~0;~E_12~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,111 INFO L290 TraceCheckUtils]: 148: Hoare triple {47924#false} assume 1 == ~E_13~0;~E_13~0 := 2; {47924#false} is VALID [2022-02-21 04:24:39,111 INFO L290 TraceCheckUtils]: 149: Hoare triple {47924#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {47924#false} is VALID [2022-02-21 04:24:39,112 INFO L290 TraceCheckUtils]: 150: Hoare triple {47924#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {47924#false} is VALID [2022-02-21 04:24:39,112 INFO L290 TraceCheckUtils]: 151: Hoare triple {47924#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {47924#false} is VALID [2022-02-21 04:24:39,112 INFO L290 TraceCheckUtils]: 152: Hoare triple {47924#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {47924#false} is VALID [2022-02-21 04:24:39,112 INFO L290 TraceCheckUtils]: 153: Hoare triple {47924#false} assume !(0 == start_simulation_~tmp~3#1); {47924#false} is VALID [2022-02-21 04:24:39,112 INFO L290 TraceCheckUtils]: 154: Hoare triple {47924#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {47924#false} is VALID [2022-02-21 04:24:39,112 INFO L290 TraceCheckUtils]: 155: Hoare triple {47924#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {47924#false} is VALID [2022-02-21 04:24:39,112 INFO L290 TraceCheckUtils]: 156: Hoare triple {47924#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {47924#false} is VALID [2022-02-21 04:24:39,113 INFO L290 TraceCheckUtils]: 157: Hoare triple {47924#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {47924#false} is VALID [2022-02-21 04:24:39,113 INFO L290 TraceCheckUtils]: 158: Hoare triple {47924#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {47924#false} is VALID [2022-02-21 04:24:39,113 INFO L290 TraceCheckUtils]: 159: Hoare triple {47924#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {47924#false} is VALID [2022-02-21 04:24:39,113 INFO L290 TraceCheckUtils]: 160: Hoare triple {47924#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {47924#false} is VALID [2022-02-21 04:24:39,113 INFO L290 TraceCheckUtils]: 161: Hoare triple {47924#false} assume !(0 != start_simulation_~tmp___0~1#1); {47924#false} is VALID [2022-02-21 04:24:39,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:39,114 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:39,115 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277683863] [2022-02-21 04:24:39,115 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277683863] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:39,116 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:39,116 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:39,116 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1087729491] [2022-02-21 04:24:39,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:39,116 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:39,117 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:39,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:39,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:39,118 INFO L87 Difference]: Start difference. First operand 1914 states and 2830 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:40,454 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2022-02-21 04:24:40,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:40,454 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,560 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:40,560 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:40,638 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:40,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-02-21 04:24:40,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:40,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:40,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:40,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:40,729 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-02-21 04:24:40,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:40,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:40,750 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:40,753 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2829 transitions. Second operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,755 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2829 transitions. Second operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,757 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. Second operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:40,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:40,859 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2022-02-21 04:24:40,859 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:40,861 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:40,861 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:40,863 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2829 transitions. [2022-02-21 04:24:40,865 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2829 transitions. [2022-02-21 04:24:40,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:40,947 INFO L93 Difference]: Finished difference Result 1914 states and 2829 transitions. [2022-02-21 04:24:40,947 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:40,948 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:40,948 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:40,948 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:40,948 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:40,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4780564263322884) internal successors, (2829), 1913 states have internal predecessors, (2829), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:41,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2829 transitions. [2022-02-21 04:24:41,033 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-02-21 04:24:41,033 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2829 transitions. [2022-02-21 04:24:41,033 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:24:41,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2829 transitions. [2022-02-21 04:24:41,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:41,036 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:41,036 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:41,038 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:41,038 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:41,038 INFO L791 eck$LassoCheckResult]: Stem: 50701#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 50702#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50521#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50237#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50238#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 51414#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51415#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50373#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50374#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50830#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50663#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50664#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 50440#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 50441#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50839#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 51016#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 51170#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 51207#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 50453#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50454#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 51627#L1258-2 assume !(0 == ~T1_E~0); 50746#L1263-1 assume !(0 == ~T2_E~0); 50747#L1268-1 assume !(0 == ~T3_E~0); 51050#L1273-1 assume !(0 == ~T4_E~0); 51609#L1278-1 assume !(0 == ~T5_E~0); 51470#L1283-1 assume !(0 == ~T6_E~0); 51471#L1288-1 assume !(0 == ~T7_E~0); 51707#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51695#L1298-1 assume !(0 == ~T9_E~0); 51621#L1303-1 assume !(0 == ~T10_E~0); 50266#L1308-1 assume !(0 == ~T11_E~0); 50208#L1313-1 assume !(0 == ~T12_E~0); 50209#L1318-1 assume !(0 == ~T13_E~0); 50217#L1323-1 assume !(0 == ~E_1~0); 50218#L1328-1 assume !(0 == ~E_2~0); 50383#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 51342#L1338-1 assume !(0 == ~E_4~0); 51343#L1343-1 assume !(0 == ~E_5~0); 51444#L1348-1 assume !(0 == ~E_6~0); 51730#L1353-1 assume !(0 == ~E_7~0); 51069#L1358-1 assume !(0 == ~E_8~0); 51070#L1363-1 assume !(0 == ~E_9~0); 51360#L1368-1 assume !(0 == ~E_10~0); 50045#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 50046#L1378-1 assume !(0 == ~E_12~0); 50334#L1383-1 assume !(0 == ~E_13~0); 50335#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51076#L607 assume 1 == ~m_pc~0; 51077#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50403#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51442#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50996#L1560 assume !(0 != activate_threads_~tmp~1#1); 50997#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50228#L626 assume !(1 == ~t1_pc~0); 50229#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 50497#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50498#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50667#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 50128#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50129#L645 assume 1 == ~t2_pc~0; 50245#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50202#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50882#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50883#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 50972#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50973#L664 assume 1 == ~t3_pc~0; 51729#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49969#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49970#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50628#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 50629#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51637#L683 assume !(1 == ~t4_pc~0); 51192#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 51144#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51145#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51179#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51303#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50923#L702 assume 1 == ~t5_pc~0; 50924#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50848#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51298#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51597#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 51538#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50017#L721 assume !(1 == ~t6_pc~0); 49991#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 49992#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50155#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50637#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 50638#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51239#L740 assume 1 == ~t7_pc~0; 50066#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49879#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49880#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49869#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 49870#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50574#L759 assume !(1 == ~t8_pc~0); 50575#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 50603#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51296#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51297#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 51428#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51706#L778 assume 1 == ~t9_pc~0; 51593#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50044#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49984#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 49913#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 49914#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50242#L797 assume !(1 == ~t10_pc~0); 50243#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 50360#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51494#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50744#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 50745#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51034#L816 assume 1 == ~t11_pc~0; 49949#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49950#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50707#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50644#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 50645#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51169#L835 assume 1 == ~t12_pc~0; 51047#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50113#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50135#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50276#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 50801#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50802#L854 assume !(1 == ~t13_pc~0); 50442#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 50443#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50493#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50153#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50154#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51533#L1401 assume !(1 == ~M_E~0); 50632#L1401-2 assume !(1 == ~T1_E~0); 50633#L1406-1 assume !(1 == ~T2_E~0); 51228#L1411-1 assume !(1 == ~T3_E~0); 51229#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50895#L1421-1 assume !(1 == ~T5_E~0); 50438#L1426-1 assume !(1 == ~T6_E~0); 50439#L1431-1 assume !(1 == ~T7_E~0); 49987#L1436-1 assume !(1 == ~T8_E~0); 49988#L1441-1 assume !(1 == ~T9_E~0); 50737#L1446-1 assume !(1 == ~T10_E~0); 50738#L1451-1 assume !(1 == ~T11_E~0); 51441#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 51095#L1461-1 assume !(1 == ~T13_E~0); 50656#L1466-1 assume !(1 == ~E_1~0); 50657#L1471-1 assume !(1 == ~E_2~0); 51426#L1476-1 assume !(1 == ~E_3~0); 51427#L1481-1 assume !(1 == ~E_4~0); 51575#L1486-1 assume !(1 == ~E_5~0); 50281#L1491-1 assume !(1 == ~E_6~0); 49921#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 49922#L1501-1 assume !(1 == ~E_8~0); 50733#L1506-1 assume !(1 == ~E_9~0); 50734#L1511-1 assume !(1 == ~E_10~0); 50690#L1516-1 assume !(1 == ~E_11~0); 49865#L1521-1 assume !(1 == ~E_12~0); 49866#L1526-1 assume !(1 == ~E_13~0); 49920#L1531-1 assume { :end_inline_reset_delta_events } true; 50463#L1892-2 [2022-02-21 04:24:41,038 INFO L793 eck$LassoCheckResult]: Loop: 50463#L1892-2 assume !false; 51486#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51684#L1233 assume !false; 51667#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50999#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50979#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51137#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 49963#L1046 assume !(0 != eval_~tmp~0#1); 49965#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49999#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51171#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 51728#L1258-5 assume !(0 == ~T1_E~0); 50141#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50142#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51720#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51726#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51727#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50365#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50366#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51483#L1298-3 assume !(0 == ~T9_E~0); 51484#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51643#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51482#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 50983#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50143#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 50144#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 51567#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50286#L1338-3 assume !(0 == ~E_4~0); 50287#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 51399#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 51573#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 51574#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50941#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 50499#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 50500#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51256#L1378-3 assume !(0 == ~E_12~0); 51257#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 51438#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51439#L607-42 assume 1 == ~m_pc~0; 51054#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 50780#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50781#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 50513#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50514#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51038#L626-42 assume 1 == ~t1_pc~0; 50600#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50601#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50902#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50903#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50177#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50178#L645-42 assume !(1 == ~t2_pc~0); 51377#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 51378#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51543#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50384#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49891#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49892#L664-42 assume !(1 == ~t3_pc~0); 50419#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 50420#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51670#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51205#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51206#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51371#L683-42 assume 1 == ~t4_pc~0; 51736#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51082#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51212#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51632#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51633#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51480#L702-42 assume 1 == ~t5_pc~0; 50968#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 50590#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50888#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51559#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49907#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49908#L721-42 assume 1 == ~t6_pc~0; 50060#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50081#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50545#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51712#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50717#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50561#L740-42 assume 1 == ~t7_pc~0; 50562#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50298#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50842#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50697#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 50698#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50971#L759-42 assume 1 == ~t8_pc~0; 50820#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50752#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50753#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50828#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50829#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50922#L778-42 assume 1 == ~t9_pc~0; 50764#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50766#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51174#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51078#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51079#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51139#L797-42 assume 1 == ~t10_pc~0; 50306#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50307#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51308#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51617#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51177#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51178#L816-42 assume !(1 == ~t11_pc~0); 49857#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 49856#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50398#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50399#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50478#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50479#L835-42 assume 1 == ~t12_pc~0; 50881#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50773#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50451#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50452#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51536#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51320#L854-42 assume 1 == ~t13_pc~0; 51321#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50395#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50007#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50008#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50654#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50655#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 51433#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50241#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50108#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50109#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50708#L1421-3 assume !(1 == ~T5_E~0); 50709#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50284#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50285#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49871#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49872#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 51461#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50792#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50445#L1461-3 assume !(1 == ~T13_E~0); 50446#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 51723#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 50385#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50386#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50786#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 50413#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50414#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50825#L1501-3 assume !(1 == ~E_8~0); 50826#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 51253#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 51242#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 51243#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50943#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50944#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51338#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50220#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51113#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 50754#L1911 assume !(0 == start_simulation_~tmp~3#1); 50755#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51277#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50344#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51215#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 50049#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50050#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50279#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 50280#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 50463#L1892-2 [2022-02-21 04:24:41,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:41,039 INFO L85 PathProgramCache]: Analyzing trace with hash 888419230, now seen corresponding path program 1 times [2022-02-21 04:24:41,040 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:41,040 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609114849] [2022-02-21 04:24:41,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:41,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:41,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:41,065 INFO L290 TraceCheckUtils]: 0: Hoare triple {55585#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {55585#true} is VALID [2022-02-21 04:24:41,066 INFO L290 TraceCheckUtils]: 1: Hoare triple {55585#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {55587#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:41,066 INFO L290 TraceCheckUtils]: 2: Hoare triple {55587#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {55587#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:41,067 INFO L290 TraceCheckUtils]: 3: Hoare triple {55587#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {55587#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:41,067 INFO L290 TraceCheckUtils]: 4: Hoare triple {55587#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {55587#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:41,067 INFO L290 TraceCheckUtils]: 5: Hoare triple {55587#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {55587#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:41,068 INFO L290 TraceCheckUtils]: 6: Hoare triple {55587#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {55587#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:41,068 INFO L290 TraceCheckUtils]: 7: Hoare triple {55587#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {55587#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:41,068 INFO L290 TraceCheckUtils]: 8: Hoare triple {55587#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {55587#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:41,068 INFO L290 TraceCheckUtils]: 9: Hoare triple {55587#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {55587#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:41,069 INFO L290 TraceCheckUtils]: 10: Hoare triple {55587#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {55587#(= ~t7_i~0 1)} is VALID [2022-02-21 04:24:41,069 INFO L290 TraceCheckUtils]: 11: Hoare triple {55587#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {55586#false} is VALID [2022-02-21 04:24:41,069 INFO L290 TraceCheckUtils]: 12: Hoare triple {55586#false} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {55586#false} is VALID [2022-02-21 04:24:41,069 INFO L290 TraceCheckUtils]: 13: Hoare triple {55586#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {55586#false} is VALID [2022-02-21 04:24:41,070 INFO L290 TraceCheckUtils]: 14: Hoare triple {55586#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {55586#false} is VALID [2022-02-21 04:24:41,070 INFO L290 TraceCheckUtils]: 15: Hoare triple {55586#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {55586#false} is VALID [2022-02-21 04:24:41,070 INFO L290 TraceCheckUtils]: 16: Hoare triple {55586#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {55586#false} is VALID [2022-02-21 04:24:41,070 INFO L290 TraceCheckUtils]: 17: Hoare triple {55586#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {55586#false} is VALID [2022-02-21 04:24:41,070 INFO L290 TraceCheckUtils]: 18: Hoare triple {55586#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {55586#false} is VALID [2022-02-21 04:24:41,070 INFO L290 TraceCheckUtils]: 19: Hoare triple {55586#false} assume 0 == ~M_E~0;~M_E~0 := 1; {55586#false} is VALID [2022-02-21 04:24:41,070 INFO L290 TraceCheckUtils]: 20: Hoare triple {55586#false} assume !(0 == ~T1_E~0); {55586#false} is VALID [2022-02-21 04:24:41,071 INFO L290 TraceCheckUtils]: 21: Hoare triple {55586#false} assume !(0 == ~T2_E~0); {55586#false} is VALID [2022-02-21 04:24:41,071 INFO L290 TraceCheckUtils]: 22: Hoare triple {55586#false} assume !(0 == ~T3_E~0); {55586#false} is VALID [2022-02-21 04:24:41,071 INFO L290 TraceCheckUtils]: 23: Hoare triple {55586#false} assume !(0 == ~T4_E~0); {55586#false} is VALID [2022-02-21 04:24:41,071 INFO L290 TraceCheckUtils]: 24: Hoare triple {55586#false} assume !(0 == ~T5_E~0); {55586#false} is VALID [2022-02-21 04:24:41,071 INFO L290 TraceCheckUtils]: 25: Hoare triple {55586#false} assume !(0 == ~T6_E~0); {55586#false} is VALID [2022-02-21 04:24:41,071 INFO L290 TraceCheckUtils]: 26: Hoare triple {55586#false} assume !(0 == ~T7_E~0); {55586#false} is VALID [2022-02-21 04:24:41,071 INFO L290 TraceCheckUtils]: 27: Hoare triple {55586#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {55586#false} is VALID [2022-02-21 04:24:41,072 INFO L290 TraceCheckUtils]: 28: Hoare triple {55586#false} assume !(0 == ~T9_E~0); {55586#false} is VALID [2022-02-21 04:24:41,072 INFO L290 TraceCheckUtils]: 29: Hoare triple {55586#false} assume !(0 == ~T10_E~0); {55586#false} is VALID [2022-02-21 04:24:41,072 INFO L290 TraceCheckUtils]: 30: Hoare triple {55586#false} assume !(0 == ~T11_E~0); {55586#false} is VALID [2022-02-21 04:24:41,072 INFO L290 TraceCheckUtils]: 31: Hoare triple {55586#false} assume !(0 == ~T12_E~0); {55586#false} is VALID [2022-02-21 04:24:41,072 INFO L290 TraceCheckUtils]: 32: Hoare triple {55586#false} assume !(0 == ~T13_E~0); {55586#false} is VALID [2022-02-21 04:24:41,072 INFO L290 TraceCheckUtils]: 33: Hoare triple {55586#false} assume !(0 == ~E_1~0); {55586#false} is VALID [2022-02-21 04:24:41,072 INFO L290 TraceCheckUtils]: 34: Hoare triple {55586#false} assume !(0 == ~E_2~0); {55586#false} is VALID [2022-02-21 04:24:41,073 INFO L290 TraceCheckUtils]: 35: Hoare triple {55586#false} assume 0 == ~E_3~0;~E_3~0 := 1; {55586#false} is VALID [2022-02-21 04:24:41,073 INFO L290 TraceCheckUtils]: 36: Hoare triple {55586#false} assume !(0 == ~E_4~0); {55586#false} is VALID [2022-02-21 04:24:41,073 INFO L290 TraceCheckUtils]: 37: Hoare triple {55586#false} assume !(0 == ~E_5~0); {55586#false} is VALID [2022-02-21 04:24:41,073 INFO L290 TraceCheckUtils]: 38: Hoare triple {55586#false} assume !(0 == ~E_6~0); {55586#false} is VALID [2022-02-21 04:24:41,073 INFO L290 TraceCheckUtils]: 39: Hoare triple {55586#false} assume !(0 == ~E_7~0); {55586#false} is VALID [2022-02-21 04:24:41,073 INFO L290 TraceCheckUtils]: 40: Hoare triple {55586#false} assume !(0 == ~E_8~0); {55586#false} is VALID [2022-02-21 04:24:41,073 INFO L290 TraceCheckUtils]: 41: Hoare triple {55586#false} assume !(0 == ~E_9~0); {55586#false} is VALID [2022-02-21 04:24:41,074 INFO L290 TraceCheckUtils]: 42: Hoare triple {55586#false} assume !(0 == ~E_10~0); {55586#false} is VALID [2022-02-21 04:24:41,074 INFO L290 TraceCheckUtils]: 43: Hoare triple {55586#false} assume 0 == ~E_11~0;~E_11~0 := 1; {55586#false} is VALID [2022-02-21 04:24:41,074 INFO L290 TraceCheckUtils]: 44: Hoare triple {55586#false} assume !(0 == ~E_12~0); {55586#false} is VALID [2022-02-21 04:24:41,074 INFO L290 TraceCheckUtils]: 45: Hoare triple {55586#false} assume !(0 == ~E_13~0); {55586#false} is VALID [2022-02-21 04:24:41,074 INFO L290 TraceCheckUtils]: 46: Hoare triple {55586#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {55586#false} is VALID [2022-02-21 04:24:41,074 INFO L290 TraceCheckUtils]: 47: Hoare triple {55586#false} assume 1 == ~m_pc~0; {55586#false} is VALID [2022-02-21 04:24:41,074 INFO L290 TraceCheckUtils]: 48: Hoare triple {55586#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {55586#false} is VALID [2022-02-21 04:24:41,075 INFO L290 TraceCheckUtils]: 49: Hoare triple {55586#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {55586#false} is VALID [2022-02-21 04:24:41,075 INFO L290 TraceCheckUtils]: 50: Hoare triple {55586#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {55586#false} is VALID [2022-02-21 04:24:41,075 INFO L290 TraceCheckUtils]: 51: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp~1#1); {55586#false} is VALID [2022-02-21 04:24:41,075 INFO L290 TraceCheckUtils]: 52: Hoare triple {55586#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {55586#false} is VALID [2022-02-21 04:24:41,075 INFO L290 TraceCheckUtils]: 53: Hoare triple {55586#false} assume !(1 == ~t1_pc~0); {55586#false} is VALID [2022-02-21 04:24:41,075 INFO L290 TraceCheckUtils]: 54: Hoare triple {55586#false} is_transmit1_triggered_~__retres1~1#1 := 0; {55586#false} is VALID [2022-02-21 04:24:41,075 INFO L290 TraceCheckUtils]: 55: Hoare triple {55586#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {55586#false} is VALID [2022-02-21 04:24:41,076 INFO L290 TraceCheckUtils]: 56: Hoare triple {55586#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {55586#false} is VALID [2022-02-21 04:24:41,076 INFO L290 TraceCheckUtils]: 57: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp___0~0#1); {55586#false} is VALID [2022-02-21 04:24:41,076 INFO L290 TraceCheckUtils]: 58: Hoare triple {55586#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {55586#false} is VALID [2022-02-21 04:24:41,076 INFO L290 TraceCheckUtils]: 59: Hoare triple {55586#false} assume 1 == ~t2_pc~0; {55586#false} is VALID [2022-02-21 04:24:41,076 INFO L290 TraceCheckUtils]: 60: Hoare triple {55586#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {55586#false} is VALID [2022-02-21 04:24:41,076 INFO L290 TraceCheckUtils]: 61: Hoare triple {55586#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {55586#false} is VALID [2022-02-21 04:24:41,076 INFO L290 TraceCheckUtils]: 62: Hoare triple {55586#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {55586#false} is VALID [2022-02-21 04:24:41,077 INFO L290 TraceCheckUtils]: 63: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp___1~0#1); {55586#false} is VALID [2022-02-21 04:24:41,077 INFO L290 TraceCheckUtils]: 64: Hoare triple {55586#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {55586#false} is VALID [2022-02-21 04:24:41,077 INFO L290 TraceCheckUtils]: 65: Hoare triple {55586#false} assume 1 == ~t3_pc~0; {55586#false} is VALID [2022-02-21 04:24:41,077 INFO L290 TraceCheckUtils]: 66: Hoare triple {55586#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {55586#false} is VALID [2022-02-21 04:24:41,077 INFO L290 TraceCheckUtils]: 67: Hoare triple {55586#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {55586#false} is VALID [2022-02-21 04:24:41,077 INFO L290 TraceCheckUtils]: 68: Hoare triple {55586#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {55586#false} is VALID [2022-02-21 04:24:41,077 INFO L290 TraceCheckUtils]: 69: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp___2~0#1); {55586#false} is VALID [2022-02-21 04:24:41,078 INFO L290 TraceCheckUtils]: 70: Hoare triple {55586#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {55586#false} is VALID [2022-02-21 04:24:41,078 INFO L290 TraceCheckUtils]: 71: Hoare triple {55586#false} assume !(1 == ~t4_pc~0); {55586#false} is VALID [2022-02-21 04:24:41,078 INFO L290 TraceCheckUtils]: 72: Hoare triple {55586#false} is_transmit4_triggered_~__retres1~4#1 := 0; {55586#false} is VALID [2022-02-21 04:24:41,078 INFO L290 TraceCheckUtils]: 73: Hoare triple {55586#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {55586#false} is VALID [2022-02-21 04:24:41,078 INFO L290 TraceCheckUtils]: 74: Hoare triple {55586#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {55586#false} is VALID [2022-02-21 04:24:41,078 INFO L290 TraceCheckUtils]: 75: Hoare triple {55586#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {55586#false} is VALID [2022-02-21 04:24:41,078 INFO L290 TraceCheckUtils]: 76: Hoare triple {55586#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {55586#false} is VALID [2022-02-21 04:24:41,079 INFO L290 TraceCheckUtils]: 77: Hoare triple {55586#false} assume 1 == ~t5_pc~0; {55586#false} is VALID [2022-02-21 04:24:41,079 INFO L290 TraceCheckUtils]: 78: Hoare triple {55586#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {55586#false} is VALID [2022-02-21 04:24:41,079 INFO L290 TraceCheckUtils]: 79: Hoare triple {55586#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {55586#false} is VALID [2022-02-21 04:24:41,079 INFO L290 TraceCheckUtils]: 80: Hoare triple {55586#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {55586#false} is VALID [2022-02-21 04:24:41,079 INFO L290 TraceCheckUtils]: 81: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp___4~0#1); {55586#false} is VALID [2022-02-21 04:24:41,079 INFO L290 TraceCheckUtils]: 82: Hoare triple {55586#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {55586#false} is VALID [2022-02-21 04:24:41,079 INFO L290 TraceCheckUtils]: 83: Hoare triple {55586#false} assume !(1 == ~t6_pc~0); {55586#false} is VALID [2022-02-21 04:24:41,080 INFO L290 TraceCheckUtils]: 84: Hoare triple {55586#false} is_transmit6_triggered_~__retres1~6#1 := 0; {55586#false} is VALID [2022-02-21 04:24:41,080 INFO L290 TraceCheckUtils]: 85: Hoare triple {55586#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {55586#false} is VALID [2022-02-21 04:24:41,080 INFO L290 TraceCheckUtils]: 86: Hoare triple {55586#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {55586#false} is VALID [2022-02-21 04:24:41,080 INFO L290 TraceCheckUtils]: 87: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp___5~0#1); {55586#false} is VALID [2022-02-21 04:24:41,080 INFO L290 TraceCheckUtils]: 88: Hoare triple {55586#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {55586#false} is VALID [2022-02-21 04:24:41,080 INFO L290 TraceCheckUtils]: 89: Hoare triple {55586#false} assume 1 == ~t7_pc~0; {55586#false} is VALID [2022-02-21 04:24:41,080 INFO L290 TraceCheckUtils]: 90: Hoare triple {55586#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {55586#false} is VALID [2022-02-21 04:24:41,081 INFO L290 TraceCheckUtils]: 91: Hoare triple {55586#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {55586#false} is VALID [2022-02-21 04:24:41,081 INFO L290 TraceCheckUtils]: 92: Hoare triple {55586#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {55586#false} is VALID [2022-02-21 04:24:41,081 INFO L290 TraceCheckUtils]: 93: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp___6~0#1); {55586#false} is VALID [2022-02-21 04:24:41,081 INFO L290 TraceCheckUtils]: 94: Hoare triple {55586#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {55586#false} is VALID [2022-02-21 04:24:41,081 INFO L290 TraceCheckUtils]: 95: Hoare triple {55586#false} assume !(1 == ~t8_pc~0); {55586#false} is VALID [2022-02-21 04:24:41,081 INFO L290 TraceCheckUtils]: 96: Hoare triple {55586#false} is_transmit8_triggered_~__retres1~8#1 := 0; {55586#false} is VALID [2022-02-21 04:24:41,081 INFO L290 TraceCheckUtils]: 97: Hoare triple {55586#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {55586#false} is VALID [2022-02-21 04:24:41,082 INFO L290 TraceCheckUtils]: 98: Hoare triple {55586#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {55586#false} is VALID [2022-02-21 04:24:41,082 INFO L290 TraceCheckUtils]: 99: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp___7~0#1); {55586#false} is VALID [2022-02-21 04:24:41,082 INFO L290 TraceCheckUtils]: 100: Hoare triple {55586#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {55586#false} is VALID [2022-02-21 04:24:41,082 INFO L290 TraceCheckUtils]: 101: Hoare triple {55586#false} assume 1 == ~t9_pc~0; {55586#false} is VALID [2022-02-21 04:24:41,082 INFO L290 TraceCheckUtils]: 102: Hoare triple {55586#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {55586#false} is VALID [2022-02-21 04:24:41,082 INFO L290 TraceCheckUtils]: 103: Hoare triple {55586#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {55586#false} is VALID [2022-02-21 04:24:41,082 INFO L290 TraceCheckUtils]: 104: Hoare triple {55586#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {55586#false} is VALID [2022-02-21 04:24:41,083 INFO L290 TraceCheckUtils]: 105: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp___8~0#1); {55586#false} is VALID [2022-02-21 04:24:41,083 INFO L290 TraceCheckUtils]: 106: Hoare triple {55586#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {55586#false} is VALID [2022-02-21 04:24:41,083 INFO L290 TraceCheckUtils]: 107: Hoare triple {55586#false} assume !(1 == ~t10_pc~0); {55586#false} is VALID [2022-02-21 04:24:41,083 INFO L290 TraceCheckUtils]: 108: Hoare triple {55586#false} is_transmit10_triggered_~__retres1~10#1 := 0; {55586#false} is VALID [2022-02-21 04:24:41,083 INFO L290 TraceCheckUtils]: 109: Hoare triple {55586#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {55586#false} is VALID [2022-02-21 04:24:41,083 INFO L290 TraceCheckUtils]: 110: Hoare triple {55586#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {55586#false} is VALID [2022-02-21 04:24:41,083 INFO L290 TraceCheckUtils]: 111: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp___9~0#1); {55586#false} is VALID [2022-02-21 04:24:41,084 INFO L290 TraceCheckUtils]: 112: Hoare triple {55586#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {55586#false} is VALID [2022-02-21 04:24:41,084 INFO L290 TraceCheckUtils]: 113: Hoare triple {55586#false} assume 1 == ~t11_pc~0; {55586#false} is VALID [2022-02-21 04:24:41,084 INFO L290 TraceCheckUtils]: 114: Hoare triple {55586#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {55586#false} is VALID [2022-02-21 04:24:41,084 INFO L290 TraceCheckUtils]: 115: Hoare triple {55586#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {55586#false} is VALID [2022-02-21 04:24:41,084 INFO L290 TraceCheckUtils]: 116: Hoare triple {55586#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {55586#false} is VALID [2022-02-21 04:24:41,084 INFO L290 TraceCheckUtils]: 117: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp___10~0#1); {55586#false} is VALID [2022-02-21 04:24:41,084 INFO L290 TraceCheckUtils]: 118: Hoare triple {55586#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {55586#false} is VALID [2022-02-21 04:24:41,085 INFO L290 TraceCheckUtils]: 119: Hoare triple {55586#false} assume 1 == ~t12_pc~0; {55586#false} is VALID [2022-02-21 04:24:41,085 INFO L290 TraceCheckUtils]: 120: Hoare triple {55586#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {55586#false} is VALID [2022-02-21 04:24:41,085 INFO L290 TraceCheckUtils]: 121: Hoare triple {55586#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {55586#false} is VALID [2022-02-21 04:24:41,085 INFO L290 TraceCheckUtils]: 122: Hoare triple {55586#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {55586#false} is VALID [2022-02-21 04:24:41,085 INFO L290 TraceCheckUtils]: 123: Hoare triple {55586#false} assume !(0 != activate_threads_~tmp___11~0#1); {55586#false} is VALID [2022-02-21 04:24:41,085 INFO L290 TraceCheckUtils]: 124: Hoare triple {55586#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {55586#false} is VALID [2022-02-21 04:24:41,085 INFO L290 TraceCheckUtils]: 125: Hoare triple {55586#false} assume !(1 == ~t13_pc~0); {55586#false} is VALID [2022-02-21 04:24:41,086 INFO L290 TraceCheckUtils]: 126: Hoare triple {55586#false} is_transmit13_triggered_~__retres1~13#1 := 0; {55586#false} is VALID [2022-02-21 04:24:41,086 INFO L290 TraceCheckUtils]: 127: Hoare triple {55586#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {55586#false} is VALID [2022-02-21 04:24:41,086 INFO L290 TraceCheckUtils]: 128: Hoare triple {55586#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {55586#false} is VALID [2022-02-21 04:24:41,086 INFO L290 TraceCheckUtils]: 129: Hoare triple {55586#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {55586#false} is VALID [2022-02-21 04:24:41,086 INFO L290 TraceCheckUtils]: 130: Hoare triple {55586#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {55586#false} is VALID [2022-02-21 04:24:41,086 INFO L290 TraceCheckUtils]: 131: Hoare triple {55586#false} assume !(1 == ~M_E~0); {55586#false} is VALID [2022-02-21 04:24:41,086 INFO L290 TraceCheckUtils]: 132: Hoare triple {55586#false} assume !(1 == ~T1_E~0); {55586#false} is VALID [2022-02-21 04:24:41,087 INFO L290 TraceCheckUtils]: 133: Hoare triple {55586#false} assume !(1 == ~T2_E~0); {55586#false} is VALID [2022-02-21 04:24:41,087 INFO L290 TraceCheckUtils]: 134: Hoare triple {55586#false} assume !(1 == ~T3_E~0); {55586#false} is VALID [2022-02-21 04:24:41,087 INFO L290 TraceCheckUtils]: 135: Hoare triple {55586#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {55586#false} is VALID [2022-02-21 04:24:41,087 INFO L290 TraceCheckUtils]: 136: Hoare triple {55586#false} assume !(1 == ~T5_E~0); {55586#false} is VALID [2022-02-21 04:24:41,087 INFO L290 TraceCheckUtils]: 137: Hoare triple {55586#false} assume !(1 == ~T6_E~0); {55586#false} is VALID [2022-02-21 04:24:41,087 INFO L290 TraceCheckUtils]: 138: Hoare triple {55586#false} assume !(1 == ~T7_E~0); {55586#false} is VALID [2022-02-21 04:24:41,087 INFO L290 TraceCheckUtils]: 139: Hoare triple {55586#false} assume !(1 == ~T8_E~0); {55586#false} is VALID [2022-02-21 04:24:41,088 INFO L290 TraceCheckUtils]: 140: Hoare triple {55586#false} assume !(1 == ~T9_E~0); {55586#false} is VALID [2022-02-21 04:24:41,088 INFO L290 TraceCheckUtils]: 141: Hoare triple {55586#false} assume !(1 == ~T10_E~0); {55586#false} is VALID [2022-02-21 04:24:41,088 INFO L290 TraceCheckUtils]: 142: Hoare triple {55586#false} assume !(1 == ~T11_E~0); {55586#false} is VALID [2022-02-21 04:24:41,088 INFO L290 TraceCheckUtils]: 143: Hoare triple {55586#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {55586#false} is VALID [2022-02-21 04:24:41,088 INFO L290 TraceCheckUtils]: 144: Hoare triple {55586#false} assume !(1 == ~T13_E~0); {55586#false} is VALID [2022-02-21 04:24:41,088 INFO L290 TraceCheckUtils]: 145: Hoare triple {55586#false} assume !(1 == ~E_1~0); {55586#false} is VALID [2022-02-21 04:24:41,088 INFO L290 TraceCheckUtils]: 146: Hoare triple {55586#false} assume !(1 == ~E_2~0); {55586#false} is VALID [2022-02-21 04:24:41,089 INFO L290 TraceCheckUtils]: 147: Hoare triple {55586#false} assume !(1 == ~E_3~0); {55586#false} is VALID [2022-02-21 04:24:41,089 INFO L290 TraceCheckUtils]: 148: Hoare triple {55586#false} assume !(1 == ~E_4~0); {55586#false} is VALID [2022-02-21 04:24:41,089 INFO L290 TraceCheckUtils]: 149: Hoare triple {55586#false} assume !(1 == ~E_5~0); {55586#false} is VALID [2022-02-21 04:24:41,089 INFO L290 TraceCheckUtils]: 150: Hoare triple {55586#false} assume !(1 == ~E_6~0); {55586#false} is VALID [2022-02-21 04:24:41,089 INFO L290 TraceCheckUtils]: 151: Hoare triple {55586#false} assume 1 == ~E_7~0;~E_7~0 := 2; {55586#false} is VALID [2022-02-21 04:24:41,089 INFO L290 TraceCheckUtils]: 152: Hoare triple {55586#false} assume !(1 == ~E_8~0); {55586#false} is VALID [2022-02-21 04:24:41,089 INFO L290 TraceCheckUtils]: 153: Hoare triple {55586#false} assume !(1 == ~E_9~0); {55586#false} is VALID [2022-02-21 04:24:41,090 INFO L290 TraceCheckUtils]: 154: Hoare triple {55586#false} assume !(1 == ~E_10~0); {55586#false} is VALID [2022-02-21 04:24:41,090 INFO L290 TraceCheckUtils]: 155: Hoare triple {55586#false} assume !(1 == ~E_11~0); {55586#false} is VALID [2022-02-21 04:24:41,090 INFO L290 TraceCheckUtils]: 156: Hoare triple {55586#false} assume !(1 == ~E_12~0); {55586#false} is VALID [2022-02-21 04:24:41,090 INFO L290 TraceCheckUtils]: 157: Hoare triple {55586#false} assume !(1 == ~E_13~0); {55586#false} is VALID [2022-02-21 04:24:41,090 INFO L290 TraceCheckUtils]: 158: Hoare triple {55586#false} assume { :end_inline_reset_delta_events } true; {55586#false} is VALID [2022-02-21 04:24:41,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:41,091 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:41,091 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1609114849] [2022-02-21 04:24:41,091 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1609114849] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:41,091 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:41,091 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:41,092 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56370721] [2022-02-21 04:24:41,092 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:41,092 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:41,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:41,093 INFO L85 PathProgramCache]: Analyzing trace with hash -1245144352, now seen corresponding path program 1 times [2022-02-21 04:24:41,093 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:41,093 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014006063] [2022-02-21 04:24:41,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:41,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:41,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:41,128 INFO L290 TraceCheckUtils]: 0: Hoare triple {55588#true} assume !false; {55588#true} is VALID [2022-02-21 04:24:41,128 INFO L290 TraceCheckUtils]: 1: Hoare triple {55588#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {55588#true} is VALID [2022-02-21 04:24:41,128 INFO L290 TraceCheckUtils]: 2: Hoare triple {55588#true} assume !false; {55588#true} is VALID [2022-02-21 04:24:41,128 INFO L290 TraceCheckUtils]: 3: Hoare triple {55588#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {55588#true} is VALID [2022-02-21 04:24:41,129 INFO L290 TraceCheckUtils]: 4: Hoare triple {55588#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {55588#true} is VALID [2022-02-21 04:24:41,129 INFO L290 TraceCheckUtils]: 5: Hoare triple {55588#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {55588#true} is VALID [2022-02-21 04:24:41,129 INFO L290 TraceCheckUtils]: 6: Hoare triple {55588#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {55588#true} is VALID [2022-02-21 04:24:41,129 INFO L290 TraceCheckUtils]: 7: Hoare triple {55588#true} assume !(0 != eval_~tmp~0#1); {55588#true} is VALID [2022-02-21 04:24:41,129 INFO L290 TraceCheckUtils]: 8: Hoare triple {55588#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {55588#true} is VALID [2022-02-21 04:24:41,129 INFO L290 TraceCheckUtils]: 9: Hoare triple {55588#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {55588#true} is VALID [2022-02-21 04:24:41,130 INFO L290 TraceCheckUtils]: 10: Hoare triple {55588#true} assume 0 == ~M_E~0;~M_E~0 := 1; {55588#true} is VALID [2022-02-21 04:24:41,130 INFO L290 TraceCheckUtils]: 11: Hoare triple {55588#true} assume !(0 == ~T1_E~0); {55588#true} is VALID [2022-02-21 04:24:41,130 INFO L290 TraceCheckUtils]: 12: Hoare triple {55588#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {55588#true} is VALID [2022-02-21 04:24:41,130 INFO L290 TraceCheckUtils]: 13: Hoare triple {55588#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {55588#true} is VALID [2022-02-21 04:24:41,130 INFO L290 TraceCheckUtils]: 14: Hoare triple {55588#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {55588#true} is VALID [2022-02-21 04:24:41,131 INFO L290 TraceCheckUtils]: 15: Hoare triple {55588#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,131 INFO L290 TraceCheckUtils]: 16: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,131 INFO L290 TraceCheckUtils]: 17: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,132 INFO L290 TraceCheckUtils]: 18: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,132 INFO L290 TraceCheckUtils]: 19: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,132 INFO L290 TraceCheckUtils]: 20: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,133 INFO L290 TraceCheckUtils]: 21: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,133 INFO L290 TraceCheckUtils]: 22: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,133 INFO L290 TraceCheckUtils]: 23: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,134 INFO L290 TraceCheckUtils]: 24: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,134 INFO L290 TraceCheckUtils]: 25: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,135 INFO L290 TraceCheckUtils]: 26: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,135 INFO L290 TraceCheckUtils]: 27: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,135 INFO L290 TraceCheckUtils]: 28: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,136 INFO L290 TraceCheckUtils]: 29: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,136 INFO L290 TraceCheckUtils]: 30: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,136 INFO L290 TraceCheckUtils]: 31: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,137 INFO L290 TraceCheckUtils]: 32: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,137 INFO L290 TraceCheckUtils]: 33: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,138 INFO L290 TraceCheckUtils]: 34: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,138 INFO L290 TraceCheckUtils]: 35: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,138 INFO L290 TraceCheckUtils]: 36: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,139 INFO L290 TraceCheckUtils]: 37: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,139 INFO L290 TraceCheckUtils]: 38: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,139 INFO L290 TraceCheckUtils]: 39: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,140 INFO L290 TraceCheckUtils]: 40: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,140 INFO L290 TraceCheckUtils]: 41: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,141 INFO L290 TraceCheckUtils]: 42: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,141 INFO L290 TraceCheckUtils]: 43: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,141 INFO L290 TraceCheckUtils]: 44: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,142 INFO L290 TraceCheckUtils]: 45: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,142 INFO L290 TraceCheckUtils]: 46: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,142 INFO L290 TraceCheckUtils]: 47: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,143 INFO L290 TraceCheckUtils]: 48: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,143 INFO L290 TraceCheckUtils]: 49: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,144 INFO L290 TraceCheckUtils]: 50: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,144 INFO L290 TraceCheckUtils]: 51: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,144 INFO L290 TraceCheckUtils]: 52: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,145 INFO L290 TraceCheckUtils]: 53: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,145 INFO L290 TraceCheckUtils]: 54: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,146 INFO L290 TraceCheckUtils]: 55: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,146 INFO L290 TraceCheckUtils]: 56: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,146 INFO L290 TraceCheckUtils]: 57: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,147 INFO L290 TraceCheckUtils]: 58: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,147 INFO L290 TraceCheckUtils]: 59: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,148 INFO L290 TraceCheckUtils]: 60: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,148 INFO L290 TraceCheckUtils]: 61: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,148 INFO L290 TraceCheckUtils]: 62: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,149 INFO L290 TraceCheckUtils]: 63: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,149 INFO L290 TraceCheckUtils]: 64: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,149 INFO L290 TraceCheckUtils]: 65: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,150 INFO L290 TraceCheckUtils]: 66: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,150 INFO L290 TraceCheckUtils]: 67: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,150 INFO L290 TraceCheckUtils]: 68: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,151 INFO L290 TraceCheckUtils]: 69: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,151 INFO L290 TraceCheckUtils]: 70: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,152 INFO L290 TraceCheckUtils]: 71: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,152 INFO L290 TraceCheckUtils]: 72: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,152 INFO L290 TraceCheckUtils]: 73: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,153 INFO L290 TraceCheckUtils]: 74: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,153 INFO L290 TraceCheckUtils]: 75: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,153 INFO L290 TraceCheckUtils]: 76: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,154 INFO L290 TraceCheckUtils]: 77: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,154 INFO L290 TraceCheckUtils]: 78: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,155 INFO L290 TraceCheckUtils]: 79: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,155 INFO L290 TraceCheckUtils]: 80: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,155 INFO L290 TraceCheckUtils]: 81: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,156 INFO L290 TraceCheckUtils]: 82: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,156 INFO L290 TraceCheckUtils]: 83: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,156 INFO L290 TraceCheckUtils]: 84: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,157 INFO L290 TraceCheckUtils]: 85: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,157 INFO L290 TraceCheckUtils]: 86: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,158 INFO L290 TraceCheckUtils]: 87: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,158 INFO L290 TraceCheckUtils]: 88: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,158 INFO L290 TraceCheckUtils]: 89: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,159 INFO L290 TraceCheckUtils]: 90: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,159 INFO L290 TraceCheckUtils]: 91: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,159 INFO L290 TraceCheckUtils]: 92: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,160 INFO L290 TraceCheckUtils]: 93: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,160 INFO L290 TraceCheckUtils]: 94: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,160 INFO L290 TraceCheckUtils]: 95: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,161 INFO L290 TraceCheckUtils]: 96: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,161 INFO L290 TraceCheckUtils]: 97: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,162 INFO L290 TraceCheckUtils]: 98: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,162 INFO L290 TraceCheckUtils]: 99: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,162 INFO L290 TraceCheckUtils]: 100: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,163 INFO L290 TraceCheckUtils]: 101: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,163 INFO L290 TraceCheckUtils]: 102: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,163 INFO L290 TraceCheckUtils]: 103: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,164 INFO L290 TraceCheckUtils]: 104: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,164 INFO L290 TraceCheckUtils]: 105: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,165 INFO L290 TraceCheckUtils]: 106: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,165 INFO L290 TraceCheckUtils]: 107: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,165 INFO L290 TraceCheckUtils]: 108: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,166 INFO L290 TraceCheckUtils]: 109: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,166 INFO L290 TraceCheckUtils]: 110: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,166 INFO L290 TraceCheckUtils]: 111: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,167 INFO L290 TraceCheckUtils]: 112: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,167 INFO L290 TraceCheckUtils]: 113: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,168 INFO L290 TraceCheckUtils]: 114: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,168 INFO L290 TraceCheckUtils]: 115: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,168 INFO L290 TraceCheckUtils]: 116: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,169 INFO L290 TraceCheckUtils]: 117: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,169 INFO L290 TraceCheckUtils]: 118: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,169 INFO L290 TraceCheckUtils]: 119: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,170 INFO L290 TraceCheckUtils]: 120: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,170 INFO L290 TraceCheckUtils]: 121: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,170 INFO L290 TraceCheckUtils]: 122: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,171 INFO L290 TraceCheckUtils]: 123: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,171 INFO L290 TraceCheckUtils]: 124: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,172 INFO L290 TraceCheckUtils]: 125: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,172 INFO L290 TraceCheckUtils]: 126: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {55590#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:41,172 INFO L290 TraceCheckUtils]: 127: Hoare triple {55590#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {55589#false} is VALID [2022-02-21 04:24:41,172 INFO L290 TraceCheckUtils]: 128: Hoare triple {55589#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,173 INFO L290 TraceCheckUtils]: 129: Hoare triple {55589#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,173 INFO L290 TraceCheckUtils]: 130: Hoare triple {55589#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,173 INFO L290 TraceCheckUtils]: 131: Hoare triple {55589#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,173 INFO L290 TraceCheckUtils]: 132: Hoare triple {55589#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,173 INFO L290 TraceCheckUtils]: 133: Hoare triple {55589#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,173 INFO L290 TraceCheckUtils]: 134: Hoare triple {55589#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,173 INFO L290 TraceCheckUtils]: 135: Hoare triple {55589#false} assume !(1 == ~T13_E~0); {55589#false} is VALID [2022-02-21 04:24:41,174 INFO L290 TraceCheckUtils]: 136: Hoare triple {55589#false} assume 1 == ~E_1~0;~E_1~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,174 INFO L290 TraceCheckUtils]: 137: Hoare triple {55589#false} assume 1 == ~E_2~0;~E_2~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,174 INFO L290 TraceCheckUtils]: 138: Hoare triple {55589#false} assume 1 == ~E_3~0;~E_3~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,174 INFO L290 TraceCheckUtils]: 139: Hoare triple {55589#false} assume 1 == ~E_4~0;~E_4~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,174 INFO L290 TraceCheckUtils]: 140: Hoare triple {55589#false} assume 1 == ~E_5~0;~E_5~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,174 INFO L290 TraceCheckUtils]: 141: Hoare triple {55589#false} assume 1 == ~E_6~0;~E_6~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,174 INFO L290 TraceCheckUtils]: 142: Hoare triple {55589#false} assume 1 == ~E_7~0;~E_7~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,175 INFO L290 TraceCheckUtils]: 143: Hoare triple {55589#false} assume !(1 == ~E_8~0); {55589#false} is VALID [2022-02-21 04:24:41,175 INFO L290 TraceCheckUtils]: 144: Hoare triple {55589#false} assume 1 == ~E_9~0;~E_9~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,175 INFO L290 TraceCheckUtils]: 145: Hoare triple {55589#false} assume 1 == ~E_10~0;~E_10~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,175 INFO L290 TraceCheckUtils]: 146: Hoare triple {55589#false} assume 1 == ~E_11~0;~E_11~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,175 INFO L290 TraceCheckUtils]: 147: Hoare triple {55589#false} assume 1 == ~E_12~0;~E_12~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,175 INFO L290 TraceCheckUtils]: 148: Hoare triple {55589#false} assume 1 == ~E_13~0;~E_13~0 := 2; {55589#false} is VALID [2022-02-21 04:24:41,175 INFO L290 TraceCheckUtils]: 149: Hoare triple {55589#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {55589#false} is VALID [2022-02-21 04:24:41,176 INFO L290 TraceCheckUtils]: 150: Hoare triple {55589#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {55589#false} is VALID [2022-02-21 04:24:41,176 INFO L290 TraceCheckUtils]: 151: Hoare triple {55589#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {55589#false} is VALID [2022-02-21 04:24:41,176 INFO L290 TraceCheckUtils]: 152: Hoare triple {55589#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {55589#false} is VALID [2022-02-21 04:24:41,176 INFO L290 TraceCheckUtils]: 153: Hoare triple {55589#false} assume !(0 == start_simulation_~tmp~3#1); {55589#false} is VALID [2022-02-21 04:24:41,176 INFO L290 TraceCheckUtils]: 154: Hoare triple {55589#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {55589#false} is VALID [2022-02-21 04:24:41,176 INFO L290 TraceCheckUtils]: 155: Hoare triple {55589#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {55589#false} is VALID [2022-02-21 04:24:41,176 INFO L290 TraceCheckUtils]: 156: Hoare triple {55589#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {55589#false} is VALID [2022-02-21 04:24:41,177 INFO L290 TraceCheckUtils]: 157: Hoare triple {55589#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {55589#false} is VALID [2022-02-21 04:24:41,177 INFO L290 TraceCheckUtils]: 158: Hoare triple {55589#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {55589#false} is VALID [2022-02-21 04:24:41,177 INFO L290 TraceCheckUtils]: 159: Hoare triple {55589#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {55589#false} is VALID [2022-02-21 04:24:41,177 INFO L290 TraceCheckUtils]: 160: Hoare triple {55589#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {55589#false} is VALID [2022-02-21 04:24:41,177 INFO L290 TraceCheckUtils]: 161: Hoare triple {55589#false} assume !(0 != start_simulation_~tmp___0~1#1); {55589#false} is VALID [2022-02-21 04:24:41,178 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:41,178 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:41,178 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014006063] [2022-02-21 04:24:41,178 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014006063] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:41,178 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:41,179 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:41,179 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027638732] [2022-02-21 04:24:41,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:41,179 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:41,179 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:41,180 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:41,180 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:41,180 INFO L87 Difference]: Start difference. First operand 1914 states and 2829 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:42,499 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2022-02-21 04:24:42,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:42,499 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,591 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:42,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:42,672 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:42,770 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-02-21 04:24:42,770 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:42,771 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:42,771 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:42,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:42,772 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-02-21 04:24:42,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:42,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:42,793 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:42,795 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2828 transitions. Second operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,797 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2828 transitions. Second operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,798 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. Second operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:42,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:42,891 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2022-02-21 04:24:42,891 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:42,892 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:42,892 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:42,894 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2828 transitions. [2022-02-21 04:24:42,896 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2828 transitions. [2022-02-21 04:24:42,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:42,971 INFO L93 Difference]: Finished difference Result 1914 states and 2828 transitions. [2022-02-21 04:24:42,971 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:42,972 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:42,972 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:42,972 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:42,973 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:42,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.477533960292581) internal successors, (2828), 1913 states have internal predecessors, (2828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:43,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2828 transitions. [2022-02-21 04:24:43,050 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-02-21 04:24:43,050 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2828 transitions. [2022-02-21 04:24:43,050 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:24:43,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2828 transitions. [2022-02-21 04:24:43,054 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:43,055 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:43,055 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:43,056 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:43,057 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:43,057 INFO L791 eck$LassoCheckResult]: Stem: 58366#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 58367#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 58186#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 57902#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57903#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 59079#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59080#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58038#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58039#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58493#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58328#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58329#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 58105#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 58106#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58504#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 58681#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 58835#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 58872#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 58116#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58117#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 59292#L1258-2 assume !(0 == ~T1_E~0); 58411#L1263-1 assume !(0 == ~T2_E~0); 58412#L1268-1 assume !(0 == ~T3_E~0); 58715#L1273-1 assume !(0 == ~T4_E~0); 59274#L1278-1 assume !(0 == ~T5_E~0); 59135#L1283-1 assume !(0 == ~T6_E~0); 59136#L1288-1 assume !(0 == ~T7_E~0); 59372#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59360#L1298-1 assume !(0 == ~T9_E~0); 59286#L1303-1 assume !(0 == ~T10_E~0); 57931#L1308-1 assume !(0 == ~T11_E~0); 57873#L1313-1 assume !(0 == ~T12_E~0); 57874#L1318-1 assume !(0 == ~T13_E~0); 57880#L1323-1 assume !(0 == ~E_1~0); 57881#L1328-1 assume !(0 == ~E_2~0); 58048#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 59007#L1338-1 assume !(0 == ~E_4~0); 59008#L1343-1 assume !(0 == ~E_5~0); 59109#L1348-1 assume !(0 == ~E_6~0); 59395#L1353-1 assume !(0 == ~E_7~0); 58734#L1358-1 assume !(0 == ~E_8~0); 58735#L1363-1 assume !(0 == ~E_9~0); 59025#L1368-1 assume !(0 == ~E_10~0); 57710#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 57711#L1378-1 assume !(0 == ~E_12~0); 57997#L1383-1 assume !(0 == ~E_13~0); 57998#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58741#L607 assume 1 == ~m_pc~0; 58742#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 58068#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59107#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58661#L1560 assume !(0 != activate_threads_~tmp~1#1); 58662#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57893#L626 assume !(1 == ~t1_pc~0); 57894#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 58162#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58163#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58332#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 57793#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57794#L645 assume 1 == ~t2_pc~0; 57910#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 57867#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58544#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58545#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 58637#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58638#L664 assume 1 == ~t3_pc~0; 59394#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57634#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57635#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58293#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 58294#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59302#L683 assume !(1 == ~t4_pc~0); 58857#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 58809#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58810#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58844#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58968#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58587#L702 assume 1 == ~t5_pc~0; 58588#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58513#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58963#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59261#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 59202#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57682#L721 assume !(1 == ~t6_pc~0); 57656#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 57657#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57820#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 58302#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 58303#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58904#L740 assume 1 == ~t7_pc~0; 57731#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57544#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57545#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57534#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 57535#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58238#L759 assume !(1 == ~t8_pc~0); 58239#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 58268#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58961#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58962#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 59093#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59371#L778 assume 1 == ~t9_pc~0; 59258#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 57709#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57649#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57578#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 57579#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57906#L797 assume !(1 == ~t10_pc~0); 57907#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58025#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59159#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58409#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 58410#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58699#L816 assume 1 == ~t11_pc~0; 57614#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57615#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58370#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58309#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 58310#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58834#L835 assume 1 == ~t12_pc~0; 58712#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 57778#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57800#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 57941#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 58466#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58467#L854 assume !(1 == ~t13_pc~0); 58107#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 58108#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 58158#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57818#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 57819#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59198#L1401 assume !(1 == ~M_E~0); 58297#L1401-2 assume !(1 == ~T1_E~0); 58298#L1406-1 assume !(1 == ~T2_E~0); 58893#L1411-1 assume !(1 == ~T3_E~0); 58894#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58560#L1421-1 assume !(1 == ~T5_E~0); 58103#L1426-1 assume !(1 == ~T6_E~0); 58104#L1431-1 assume !(1 == ~T7_E~0); 57652#L1436-1 assume !(1 == ~T8_E~0); 57653#L1441-1 assume !(1 == ~T9_E~0); 58400#L1446-1 assume !(1 == ~T10_E~0); 58401#L1451-1 assume !(1 == ~T11_E~0); 59106#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58760#L1461-1 assume !(1 == ~T13_E~0); 58321#L1466-1 assume !(1 == ~E_1~0); 58322#L1471-1 assume !(1 == ~E_2~0); 59091#L1476-1 assume !(1 == ~E_3~0); 59092#L1481-1 assume !(1 == ~E_4~0); 59240#L1486-1 assume !(1 == ~E_5~0); 57946#L1491-1 assume !(1 == ~E_6~0); 57586#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 57587#L1501-1 assume !(1 == ~E_8~0); 58398#L1506-1 assume !(1 == ~E_9~0); 58399#L1511-1 assume !(1 == ~E_10~0); 58355#L1516-1 assume !(1 == ~E_11~0); 57530#L1521-1 assume !(1 == ~E_12~0); 57531#L1526-1 assume !(1 == ~E_13~0); 57585#L1531-1 assume { :end_inline_reset_delta_events } true; 58128#L1892-2 [2022-02-21 04:24:43,057 INFO L793 eck$LassoCheckResult]: Loop: 58128#L1892-2 assume !false; 59151#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59349#L1233 assume !false; 59332#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58664#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58644#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58802#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57628#L1046 assume !(0 != eval_~tmp~0#1); 57630#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57664#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58836#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 59393#L1258-5 assume !(0 == ~T1_E~0); 57806#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57807#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59385#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59391#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59392#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 58030#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 58031#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59148#L1298-3 assume !(0 == ~T9_E~0); 59149#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 59308#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 59147#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 58648#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 57808#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57809#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59232#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57951#L1338-3 assume !(0 == ~E_4~0); 57952#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 59064#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59237#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 59238#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 58604#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 58164#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 58165#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 58921#L1378-3 assume !(0 == ~E_12~0); 58922#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 59103#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59104#L607-42 assume !(1 == ~m_pc~0); 58720#L607-44 is_master_triggered_~__retres1~0#1 := 0; 58445#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58446#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 58178#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58179#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58700#L626-42 assume 1 == ~t1_pc~0; 58265#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 58266#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58567#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 58568#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57842#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57843#L645-42 assume !(1 == ~t2_pc~0); 59042#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 59043#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59208#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 58049#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57556#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57557#L664-42 assume !(1 == ~t3_pc~0); 58083#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 58084#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59335#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58870#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58871#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59036#L683-42 assume !(1 == ~t4_pc~0); 58744#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 58745#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58877#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59297#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 59298#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59143#L702-42 assume 1 == ~t5_pc~0; 58633#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 58255#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58551#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59224#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57572#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57573#L721-42 assume 1 == ~t6_pc~0; 57726#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 57749#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58210#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59377#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58382#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58228#L740-42 assume 1 == ~t7_pc~0; 58229#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57966#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 58507#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58362#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 58363#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 58636#L759-42 assume 1 == ~t8_pc~0; 58487#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 58417#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58418#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 58496#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58497#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 58592#L778-42 assume 1 == ~t9_pc~0; 58432#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 58434#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 58841#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58746#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 58747#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58804#L797-42 assume 1 == ~t10_pc~0; 57974#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 57975#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 58973#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59282#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 58842#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 58843#L816-42 assume 1 == ~t11_pc~0; 57523#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57524#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 58065#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 58066#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 58143#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 58144#L835-42 assume 1 == ~t12_pc~0; 58548#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58441#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58118#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 58119#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 59201#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 58985#L854-42 assume 1 == ~t13_pc~0; 58986#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 58062#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 57672#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57673#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 58319#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58320#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 59098#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57909#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57775#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57776#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58373#L1421-3 assume !(1 == ~T5_E~0); 58374#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57949#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57950#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57536#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57537#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59127#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58457#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58110#L1461-3 assume !(1 == ~T13_E~0); 58111#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59388#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58050#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58051#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 58451#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58078#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 58079#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 58491#L1501-3 assume !(1 == ~E_8~0); 58492#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 58918#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 58908#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 58909#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 58608#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 58609#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59005#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 57885#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58780#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 58419#L1911 assume !(0 == start_simulation_~tmp~3#1); 58420#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58942#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58009#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58880#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 57714#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57715#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57944#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 57945#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 58128#L1892-2 [2022-02-21 04:24:43,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:43,058 INFO L85 PathProgramCache]: Analyzing trace with hash 1153066720, now seen corresponding path program 1 times [2022-02-21 04:24:43,058 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:43,059 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883716914] [2022-02-21 04:24:43,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:43,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:43,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:43,088 INFO L290 TraceCheckUtils]: 0: Hoare triple {63250#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {63250#true} is VALID [2022-02-21 04:24:43,089 INFO L290 TraceCheckUtils]: 1: Hoare triple {63250#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {63252#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:43,089 INFO L290 TraceCheckUtils]: 2: Hoare triple {63252#(= ~t8_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {63252#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:43,089 INFO L290 TraceCheckUtils]: 3: Hoare triple {63252#(= ~t8_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {63252#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:43,090 INFO L290 TraceCheckUtils]: 4: Hoare triple {63252#(= ~t8_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {63252#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:43,090 INFO L290 TraceCheckUtils]: 5: Hoare triple {63252#(= ~t8_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {63252#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:43,090 INFO L290 TraceCheckUtils]: 6: Hoare triple {63252#(= ~t8_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {63252#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:43,091 INFO L290 TraceCheckUtils]: 7: Hoare triple {63252#(= ~t8_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {63252#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:43,091 INFO L290 TraceCheckUtils]: 8: Hoare triple {63252#(= ~t8_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {63252#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:43,091 INFO L290 TraceCheckUtils]: 9: Hoare triple {63252#(= ~t8_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {63252#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:43,092 INFO L290 TraceCheckUtils]: 10: Hoare triple {63252#(= ~t8_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {63252#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:43,092 INFO L290 TraceCheckUtils]: 11: Hoare triple {63252#(= ~t8_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {63252#(= ~t8_i~0 1)} is VALID [2022-02-21 04:24:43,092 INFO L290 TraceCheckUtils]: 12: Hoare triple {63252#(= ~t8_i~0 1)} assume !(1 == ~t8_i~0);~t8_st~0 := 2; {63251#false} is VALID [2022-02-21 04:24:43,093 INFO L290 TraceCheckUtils]: 13: Hoare triple {63251#false} assume 1 == ~t9_i~0;~t9_st~0 := 0; {63251#false} is VALID [2022-02-21 04:24:43,093 INFO L290 TraceCheckUtils]: 14: Hoare triple {63251#false} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {63251#false} is VALID [2022-02-21 04:24:43,093 INFO L290 TraceCheckUtils]: 15: Hoare triple {63251#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {63251#false} is VALID [2022-02-21 04:24:43,093 INFO L290 TraceCheckUtils]: 16: Hoare triple {63251#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {63251#false} is VALID [2022-02-21 04:24:43,093 INFO L290 TraceCheckUtils]: 17: Hoare triple {63251#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {63251#false} is VALID [2022-02-21 04:24:43,093 INFO L290 TraceCheckUtils]: 18: Hoare triple {63251#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {63251#false} is VALID [2022-02-21 04:24:43,094 INFO L290 TraceCheckUtils]: 19: Hoare triple {63251#false} assume 0 == ~M_E~0;~M_E~0 := 1; {63251#false} is VALID [2022-02-21 04:24:43,094 INFO L290 TraceCheckUtils]: 20: Hoare triple {63251#false} assume !(0 == ~T1_E~0); {63251#false} is VALID [2022-02-21 04:24:43,094 INFO L290 TraceCheckUtils]: 21: Hoare triple {63251#false} assume !(0 == ~T2_E~0); {63251#false} is VALID [2022-02-21 04:24:43,094 INFO L290 TraceCheckUtils]: 22: Hoare triple {63251#false} assume !(0 == ~T3_E~0); {63251#false} is VALID [2022-02-21 04:24:43,094 INFO L290 TraceCheckUtils]: 23: Hoare triple {63251#false} assume !(0 == ~T4_E~0); {63251#false} is VALID [2022-02-21 04:24:43,094 INFO L290 TraceCheckUtils]: 24: Hoare triple {63251#false} assume !(0 == ~T5_E~0); {63251#false} is VALID [2022-02-21 04:24:43,094 INFO L290 TraceCheckUtils]: 25: Hoare triple {63251#false} assume !(0 == ~T6_E~0); {63251#false} is VALID [2022-02-21 04:24:43,095 INFO L290 TraceCheckUtils]: 26: Hoare triple {63251#false} assume !(0 == ~T7_E~0); {63251#false} is VALID [2022-02-21 04:24:43,095 INFO L290 TraceCheckUtils]: 27: Hoare triple {63251#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {63251#false} is VALID [2022-02-21 04:24:43,095 INFO L290 TraceCheckUtils]: 28: Hoare triple {63251#false} assume !(0 == ~T9_E~0); {63251#false} is VALID [2022-02-21 04:24:43,095 INFO L290 TraceCheckUtils]: 29: Hoare triple {63251#false} assume !(0 == ~T10_E~0); {63251#false} is VALID [2022-02-21 04:24:43,095 INFO L290 TraceCheckUtils]: 30: Hoare triple {63251#false} assume !(0 == ~T11_E~0); {63251#false} is VALID [2022-02-21 04:24:43,095 INFO L290 TraceCheckUtils]: 31: Hoare triple {63251#false} assume !(0 == ~T12_E~0); {63251#false} is VALID [2022-02-21 04:24:43,095 INFO L290 TraceCheckUtils]: 32: Hoare triple {63251#false} assume !(0 == ~T13_E~0); {63251#false} is VALID [2022-02-21 04:24:43,096 INFO L290 TraceCheckUtils]: 33: Hoare triple {63251#false} assume !(0 == ~E_1~0); {63251#false} is VALID [2022-02-21 04:24:43,096 INFO L290 TraceCheckUtils]: 34: Hoare triple {63251#false} assume !(0 == ~E_2~0); {63251#false} is VALID [2022-02-21 04:24:43,096 INFO L290 TraceCheckUtils]: 35: Hoare triple {63251#false} assume 0 == ~E_3~0;~E_3~0 := 1; {63251#false} is VALID [2022-02-21 04:24:43,096 INFO L290 TraceCheckUtils]: 36: Hoare triple {63251#false} assume !(0 == ~E_4~0); {63251#false} is VALID [2022-02-21 04:24:43,096 INFO L290 TraceCheckUtils]: 37: Hoare triple {63251#false} assume !(0 == ~E_5~0); {63251#false} is VALID [2022-02-21 04:24:43,096 INFO L290 TraceCheckUtils]: 38: Hoare triple {63251#false} assume !(0 == ~E_6~0); {63251#false} is VALID [2022-02-21 04:24:43,096 INFO L290 TraceCheckUtils]: 39: Hoare triple {63251#false} assume !(0 == ~E_7~0); {63251#false} is VALID [2022-02-21 04:24:43,097 INFO L290 TraceCheckUtils]: 40: Hoare triple {63251#false} assume !(0 == ~E_8~0); {63251#false} is VALID [2022-02-21 04:24:43,097 INFO L290 TraceCheckUtils]: 41: Hoare triple {63251#false} assume !(0 == ~E_9~0); {63251#false} is VALID [2022-02-21 04:24:43,097 INFO L290 TraceCheckUtils]: 42: Hoare triple {63251#false} assume !(0 == ~E_10~0); {63251#false} is VALID [2022-02-21 04:24:43,097 INFO L290 TraceCheckUtils]: 43: Hoare triple {63251#false} assume 0 == ~E_11~0;~E_11~0 := 1; {63251#false} is VALID [2022-02-21 04:24:43,097 INFO L290 TraceCheckUtils]: 44: Hoare triple {63251#false} assume !(0 == ~E_12~0); {63251#false} is VALID [2022-02-21 04:24:43,097 INFO L290 TraceCheckUtils]: 45: Hoare triple {63251#false} assume !(0 == ~E_13~0); {63251#false} is VALID [2022-02-21 04:24:43,097 INFO L290 TraceCheckUtils]: 46: Hoare triple {63251#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {63251#false} is VALID [2022-02-21 04:24:43,098 INFO L290 TraceCheckUtils]: 47: Hoare triple {63251#false} assume 1 == ~m_pc~0; {63251#false} is VALID [2022-02-21 04:24:43,098 INFO L290 TraceCheckUtils]: 48: Hoare triple {63251#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {63251#false} is VALID [2022-02-21 04:24:43,098 INFO L290 TraceCheckUtils]: 49: Hoare triple {63251#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {63251#false} is VALID [2022-02-21 04:24:43,098 INFO L290 TraceCheckUtils]: 50: Hoare triple {63251#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {63251#false} is VALID [2022-02-21 04:24:43,098 INFO L290 TraceCheckUtils]: 51: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp~1#1); {63251#false} is VALID [2022-02-21 04:24:43,098 INFO L290 TraceCheckUtils]: 52: Hoare triple {63251#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {63251#false} is VALID [2022-02-21 04:24:43,098 INFO L290 TraceCheckUtils]: 53: Hoare triple {63251#false} assume !(1 == ~t1_pc~0); {63251#false} is VALID [2022-02-21 04:24:43,099 INFO L290 TraceCheckUtils]: 54: Hoare triple {63251#false} is_transmit1_triggered_~__retres1~1#1 := 0; {63251#false} is VALID [2022-02-21 04:24:43,099 INFO L290 TraceCheckUtils]: 55: Hoare triple {63251#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {63251#false} is VALID [2022-02-21 04:24:43,099 INFO L290 TraceCheckUtils]: 56: Hoare triple {63251#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {63251#false} is VALID [2022-02-21 04:24:43,099 INFO L290 TraceCheckUtils]: 57: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp___0~0#1); {63251#false} is VALID [2022-02-21 04:24:43,099 INFO L290 TraceCheckUtils]: 58: Hoare triple {63251#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {63251#false} is VALID [2022-02-21 04:24:43,099 INFO L290 TraceCheckUtils]: 59: Hoare triple {63251#false} assume 1 == ~t2_pc~0; {63251#false} is VALID [2022-02-21 04:24:43,099 INFO L290 TraceCheckUtils]: 60: Hoare triple {63251#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {63251#false} is VALID [2022-02-21 04:24:43,100 INFO L290 TraceCheckUtils]: 61: Hoare triple {63251#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {63251#false} is VALID [2022-02-21 04:24:43,100 INFO L290 TraceCheckUtils]: 62: Hoare triple {63251#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {63251#false} is VALID [2022-02-21 04:24:43,100 INFO L290 TraceCheckUtils]: 63: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp___1~0#1); {63251#false} is VALID [2022-02-21 04:24:43,100 INFO L290 TraceCheckUtils]: 64: Hoare triple {63251#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {63251#false} is VALID [2022-02-21 04:24:43,100 INFO L290 TraceCheckUtils]: 65: Hoare triple {63251#false} assume 1 == ~t3_pc~0; {63251#false} is VALID [2022-02-21 04:24:43,100 INFO L290 TraceCheckUtils]: 66: Hoare triple {63251#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {63251#false} is VALID [2022-02-21 04:24:43,100 INFO L290 TraceCheckUtils]: 67: Hoare triple {63251#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {63251#false} is VALID [2022-02-21 04:24:43,101 INFO L290 TraceCheckUtils]: 68: Hoare triple {63251#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {63251#false} is VALID [2022-02-21 04:24:43,101 INFO L290 TraceCheckUtils]: 69: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp___2~0#1); {63251#false} is VALID [2022-02-21 04:24:43,101 INFO L290 TraceCheckUtils]: 70: Hoare triple {63251#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {63251#false} is VALID [2022-02-21 04:24:43,101 INFO L290 TraceCheckUtils]: 71: Hoare triple {63251#false} assume !(1 == ~t4_pc~0); {63251#false} is VALID [2022-02-21 04:24:43,101 INFO L290 TraceCheckUtils]: 72: Hoare triple {63251#false} is_transmit4_triggered_~__retres1~4#1 := 0; {63251#false} is VALID [2022-02-21 04:24:43,101 INFO L290 TraceCheckUtils]: 73: Hoare triple {63251#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {63251#false} is VALID [2022-02-21 04:24:43,101 INFO L290 TraceCheckUtils]: 74: Hoare triple {63251#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {63251#false} is VALID [2022-02-21 04:24:43,102 INFO L290 TraceCheckUtils]: 75: Hoare triple {63251#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {63251#false} is VALID [2022-02-21 04:24:43,102 INFO L290 TraceCheckUtils]: 76: Hoare triple {63251#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {63251#false} is VALID [2022-02-21 04:24:43,102 INFO L290 TraceCheckUtils]: 77: Hoare triple {63251#false} assume 1 == ~t5_pc~0; {63251#false} is VALID [2022-02-21 04:24:43,102 INFO L290 TraceCheckUtils]: 78: Hoare triple {63251#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {63251#false} is VALID [2022-02-21 04:24:43,102 INFO L290 TraceCheckUtils]: 79: Hoare triple {63251#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {63251#false} is VALID [2022-02-21 04:24:43,102 INFO L290 TraceCheckUtils]: 80: Hoare triple {63251#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {63251#false} is VALID [2022-02-21 04:24:43,102 INFO L290 TraceCheckUtils]: 81: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp___4~0#1); {63251#false} is VALID [2022-02-21 04:24:43,103 INFO L290 TraceCheckUtils]: 82: Hoare triple {63251#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {63251#false} is VALID [2022-02-21 04:24:43,103 INFO L290 TraceCheckUtils]: 83: Hoare triple {63251#false} assume !(1 == ~t6_pc~0); {63251#false} is VALID [2022-02-21 04:24:43,103 INFO L290 TraceCheckUtils]: 84: Hoare triple {63251#false} is_transmit6_triggered_~__retres1~6#1 := 0; {63251#false} is VALID [2022-02-21 04:24:43,103 INFO L290 TraceCheckUtils]: 85: Hoare triple {63251#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {63251#false} is VALID [2022-02-21 04:24:43,103 INFO L290 TraceCheckUtils]: 86: Hoare triple {63251#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {63251#false} is VALID [2022-02-21 04:24:43,103 INFO L290 TraceCheckUtils]: 87: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp___5~0#1); {63251#false} is VALID [2022-02-21 04:24:43,103 INFO L290 TraceCheckUtils]: 88: Hoare triple {63251#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {63251#false} is VALID [2022-02-21 04:24:43,104 INFO L290 TraceCheckUtils]: 89: Hoare triple {63251#false} assume 1 == ~t7_pc~0; {63251#false} is VALID [2022-02-21 04:24:43,104 INFO L290 TraceCheckUtils]: 90: Hoare triple {63251#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {63251#false} is VALID [2022-02-21 04:24:43,104 INFO L290 TraceCheckUtils]: 91: Hoare triple {63251#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {63251#false} is VALID [2022-02-21 04:24:43,104 INFO L290 TraceCheckUtils]: 92: Hoare triple {63251#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {63251#false} is VALID [2022-02-21 04:24:43,104 INFO L290 TraceCheckUtils]: 93: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp___6~0#1); {63251#false} is VALID [2022-02-21 04:24:43,104 INFO L290 TraceCheckUtils]: 94: Hoare triple {63251#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {63251#false} is VALID [2022-02-21 04:24:43,104 INFO L290 TraceCheckUtils]: 95: Hoare triple {63251#false} assume !(1 == ~t8_pc~0); {63251#false} is VALID [2022-02-21 04:24:43,105 INFO L290 TraceCheckUtils]: 96: Hoare triple {63251#false} is_transmit8_triggered_~__retres1~8#1 := 0; {63251#false} is VALID [2022-02-21 04:24:43,105 INFO L290 TraceCheckUtils]: 97: Hoare triple {63251#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {63251#false} is VALID [2022-02-21 04:24:43,105 INFO L290 TraceCheckUtils]: 98: Hoare triple {63251#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {63251#false} is VALID [2022-02-21 04:24:43,105 INFO L290 TraceCheckUtils]: 99: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp___7~0#1); {63251#false} is VALID [2022-02-21 04:24:43,105 INFO L290 TraceCheckUtils]: 100: Hoare triple {63251#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {63251#false} is VALID [2022-02-21 04:24:43,105 INFO L290 TraceCheckUtils]: 101: Hoare triple {63251#false} assume 1 == ~t9_pc~0; {63251#false} is VALID [2022-02-21 04:24:43,105 INFO L290 TraceCheckUtils]: 102: Hoare triple {63251#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {63251#false} is VALID [2022-02-21 04:24:43,106 INFO L290 TraceCheckUtils]: 103: Hoare triple {63251#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {63251#false} is VALID [2022-02-21 04:24:43,106 INFO L290 TraceCheckUtils]: 104: Hoare triple {63251#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {63251#false} is VALID [2022-02-21 04:24:43,106 INFO L290 TraceCheckUtils]: 105: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp___8~0#1); {63251#false} is VALID [2022-02-21 04:24:43,106 INFO L290 TraceCheckUtils]: 106: Hoare triple {63251#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {63251#false} is VALID [2022-02-21 04:24:43,106 INFO L290 TraceCheckUtils]: 107: Hoare triple {63251#false} assume !(1 == ~t10_pc~0); {63251#false} is VALID [2022-02-21 04:24:43,106 INFO L290 TraceCheckUtils]: 108: Hoare triple {63251#false} is_transmit10_triggered_~__retres1~10#1 := 0; {63251#false} is VALID [2022-02-21 04:24:43,106 INFO L290 TraceCheckUtils]: 109: Hoare triple {63251#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {63251#false} is VALID [2022-02-21 04:24:43,107 INFO L290 TraceCheckUtils]: 110: Hoare triple {63251#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {63251#false} is VALID [2022-02-21 04:24:43,107 INFO L290 TraceCheckUtils]: 111: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp___9~0#1); {63251#false} is VALID [2022-02-21 04:24:43,107 INFO L290 TraceCheckUtils]: 112: Hoare triple {63251#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {63251#false} is VALID [2022-02-21 04:24:43,107 INFO L290 TraceCheckUtils]: 113: Hoare triple {63251#false} assume 1 == ~t11_pc~0; {63251#false} is VALID [2022-02-21 04:24:43,107 INFO L290 TraceCheckUtils]: 114: Hoare triple {63251#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {63251#false} is VALID [2022-02-21 04:24:43,107 INFO L290 TraceCheckUtils]: 115: Hoare triple {63251#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {63251#false} is VALID [2022-02-21 04:24:43,108 INFO L290 TraceCheckUtils]: 116: Hoare triple {63251#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {63251#false} is VALID [2022-02-21 04:24:43,108 INFO L290 TraceCheckUtils]: 117: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp___10~0#1); {63251#false} is VALID [2022-02-21 04:24:43,108 INFO L290 TraceCheckUtils]: 118: Hoare triple {63251#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {63251#false} is VALID [2022-02-21 04:24:43,108 INFO L290 TraceCheckUtils]: 119: Hoare triple {63251#false} assume 1 == ~t12_pc~0; {63251#false} is VALID [2022-02-21 04:24:43,108 INFO L290 TraceCheckUtils]: 120: Hoare triple {63251#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {63251#false} is VALID [2022-02-21 04:24:43,108 INFO L290 TraceCheckUtils]: 121: Hoare triple {63251#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {63251#false} is VALID [2022-02-21 04:24:43,108 INFO L290 TraceCheckUtils]: 122: Hoare triple {63251#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {63251#false} is VALID [2022-02-21 04:24:43,109 INFO L290 TraceCheckUtils]: 123: Hoare triple {63251#false} assume !(0 != activate_threads_~tmp___11~0#1); {63251#false} is VALID [2022-02-21 04:24:43,109 INFO L290 TraceCheckUtils]: 124: Hoare triple {63251#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {63251#false} is VALID [2022-02-21 04:24:43,109 INFO L290 TraceCheckUtils]: 125: Hoare triple {63251#false} assume !(1 == ~t13_pc~0); {63251#false} is VALID [2022-02-21 04:24:43,109 INFO L290 TraceCheckUtils]: 126: Hoare triple {63251#false} is_transmit13_triggered_~__retres1~13#1 := 0; {63251#false} is VALID [2022-02-21 04:24:43,109 INFO L290 TraceCheckUtils]: 127: Hoare triple {63251#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {63251#false} is VALID [2022-02-21 04:24:43,109 INFO L290 TraceCheckUtils]: 128: Hoare triple {63251#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {63251#false} is VALID [2022-02-21 04:24:43,109 INFO L290 TraceCheckUtils]: 129: Hoare triple {63251#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {63251#false} is VALID [2022-02-21 04:24:43,110 INFO L290 TraceCheckUtils]: 130: Hoare triple {63251#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {63251#false} is VALID [2022-02-21 04:24:43,110 INFO L290 TraceCheckUtils]: 131: Hoare triple {63251#false} assume !(1 == ~M_E~0); {63251#false} is VALID [2022-02-21 04:24:43,110 INFO L290 TraceCheckUtils]: 132: Hoare triple {63251#false} assume !(1 == ~T1_E~0); {63251#false} is VALID [2022-02-21 04:24:43,110 INFO L290 TraceCheckUtils]: 133: Hoare triple {63251#false} assume !(1 == ~T2_E~0); {63251#false} is VALID [2022-02-21 04:24:43,110 INFO L290 TraceCheckUtils]: 134: Hoare triple {63251#false} assume !(1 == ~T3_E~0); {63251#false} is VALID [2022-02-21 04:24:43,110 INFO L290 TraceCheckUtils]: 135: Hoare triple {63251#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {63251#false} is VALID [2022-02-21 04:24:43,110 INFO L290 TraceCheckUtils]: 136: Hoare triple {63251#false} assume !(1 == ~T5_E~0); {63251#false} is VALID [2022-02-21 04:24:43,110 INFO L290 TraceCheckUtils]: 137: Hoare triple {63251#false} assume !(1 == ~T6_E~0); {63251#false} is VALID [2022-02-21 04:24:43,111 INFO L290 TraceCheckUtils]: 138: Hoare triple {63251#false} assume !(1 == ~T7_E~0); {63251#false} is VALID [2022-02-21 04:24:43,111 INFO L290 TraceCheckUtils]: 139: Hoare triple {63251#false} assume !(1 == ~T8_E~0); {63251#false} is VALID [2022-02-21 04:24:43,111 INFO L290 TraceCheckUtils]: 140: Hoare triple {63251#false} assume !(1 == ~T9_E~0); {63251#false} is VALID [2022-02-21 04:24:43,111 INFO L290 TraceCheckUtils]: 141: Hoare triple {63251#false} assume !(1 == ~T10_E~0); {63251#false} is VALID [2022-02-21 04:24:43,111 INFO L290 TraceCheckUtils]: 142: Hoare triple {63251#false} assume !(1 == ~T11_E~0); {63251#false} is VALID [2022-02-21 04:24:43,111 INFO L290 TraceCheckUtils]: 143: Hoare triple {63251#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {63251#false} is VALID [2022-02-21 04:24:43,112 INFO L290 TraceCheckUtils]: 144: Hoare triple {63251#false} assume !(1 == ~T13_E~0); {63251#false} is VALID [2022-02-21 04:24:43,112 INFO L290 TraceCheckUtils]: 145: Hoare triple {63251#false} assume !(1 == ~E_1~0); {63251#false} is VALID [2022-02-21 04:24:43,112 INFO L290 TraceCheckUtils]: 146: Hoare triple {63251#false} assume !(1 == ~E_2~0); {63251#false} is VALID [2022-02-21 04:24:43,112 INFO L290 TraceCheckUtils]: 147: Hoare triple {63251#false} assume !(1 == ~E_3~0); {63251#false} is VALID [2022-02-21 04:24:43,112 INFO L290 TraceCheckUtils]: 148: Hoare triple {63251#false} assume !(1 == ~E_4~0); {63251#false} is VALID [2022-02-21 04:24:43,112 INFO L290 TraceCheckUtils]: 149: Hoare triple {63251#false} assume !(1 == ~E_5~0); {63251#false} is VALID [2022-02-21 04:24:43,112 INFO L290 TraceCheckUtils]: 150: Hoare triple {63251#false} assume !(1 == ~E_6~0); {63251#false} is VALID [2022-02-21 04:24:43,113 INFO L290 TraceCheckUtils]: 151: Hoare triple {63251#false} assume 1 == ~E_7~0;~E_7~0 := 2; {63251#false} is VALID [2022-02-21 04:24:43,113 INFO L290 TraceCheckUtils]: 152: Hoare triple {63251#false} assume !(1 == ~E_8~0); {63251#false} is VALID [2022-02-21 04:24:43,113 INFO L290 TraceCheckUtils]: 153: Hoare triple {63251#false} assume !(1 == ~E_9~0); {63251#false} is VALID [2022-02-21 04:24:43,113 INFO L290 TraceCheckUtils]: 154: Hoare triple {63251#false} assume !(1 == ~E_10~0); {63251#false} is VALID [2022-02-21 04:24:43,113 INFO L290 TraceCheckUtils]: 155: Hoare triple {63251#false} assume !(1 == ~E_11~0); {63251#false} is VALID [2022-02-21 04:24:43,113 INFO L290 TraceCheckUtils]: 156: Hoare triple {63251#false} assume !(1 == ~E_12~0); {63251#false} is VALID [2022-02-21 04:24:43,113 INFO L290 TraceCheckUtils]: 157: Hoare triple {63251#false} assume !(1 == ~E_13~0); {63251#false} is VALID [2022-02-21 04:24:43,114 INFO L290 TraceCheckUtils]: 158: Hoare triple {63251#false} assume { :end_inline_reset_delta_events } true; {63251#false} is VALID [2022-02-21 04:24:43,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:43,114 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:43,114 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883716914] [2022-02-21 04:24:43,114 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1883716914] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:43,115 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:43,115 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:43,115 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940669688] [2022-02-21 04:24:43,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:43,116 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:43,116 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:43,116 INFO L85 PathProgramCache]: Analyzing trace with hash 498612287, now seen corresponding path program 1 times [2022-02-21 04:24:43,116 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:43,116 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589638304] [2022-02-21 04:24:43,117 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:43,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:43,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:43,150 INFO L290 TraceCheckUtils]: 0: Hoare triple {63253#true} assume !false; {63253#true} is VALID [2022-02-21 04:24:43,150 INFO L290 TraceCheckUtils]: 1: Hoare triple {63253#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {63253#true} is VALID [2022-02-21 04:24:43,151 INFO L290 TraceCheckUtils]: 2: Hoare triple {63253#true} assume !false; {63253#true} is VALID [2022-02-21 04:24:43,151 INFO L290 TraceCheckUtils]: 3: Hoare triple {63253#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {63253#true} is VALID [2022-02-21 04:24:43,151 INFO L290 TraceCheckUtils]: 4: Hoare triple {63253#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {63253#true} is VALID [2022-02-21 04:24:43,151 INFO L290 TraceCheckUtils]: 5: Hoare triple {63253#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {63253#true} is VALID [2022-02-21 04:24:43,151 INFO L290 TraceCheckUtils]: 6: Hoare triple {63253#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {63253#true} is VALID [2022-02-21 04:24:43,151 INFO L290 TraceCheckUtils]: 7: Hoare triple {63253#true} assume !(0 != eval_~tmp~0#1); {63253#true} is VALID [2022-02-21 04:24:43,152 INFO L290 TraceCheckUtils]: 8: Hoare triple {63253#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {63253#true} is VALID [2022-02-21 04:24:43,152 INFO L290 TraceCheckUtils]: 9: Hoare triple {63253#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {63253#true} is VALID [2022-02-21 04:24:43,152 INFO L290 TraceCheckUtils]: 10: Hoare triple {63253#true} assume 0 == ~M_E~0;~M_E~0 := 1; {63253#true} is VALID [2022-02-21 04:24:43,152 INFO L290 TraceCheckUtils]: 11: Hoare triple {63253#true} assume !(0 == ~T1_E~0); {63253#true} is VALID [2022-02-21 04:24:43,152 INFO L290 TraceCheckUtils]: 12: Hoare triple {63253#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {63253#true} is VALID [2022-02-21 04:24:43,152 INFO L290 TraceCheckUtils]: 13: Hoare triple {63253#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {63253#true} is VALID [2022-02-21 04:24:43,152 INFO L290 TraceCheckUtils]: 14: Hoare triple {63253#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {63253#true} is VALID [2022-02-21 04:24:43,153 INFO L290 TraceCheckUtils]: 15: Hoare triple {63253#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,153 INFO L290 TraceCheckUtils]: 16: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,154 INFO L290 TraceCheckUtils]: 17: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,154 INFO L290 TraceCheckUtils]: 18: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,154 INFO L290 TraceCheckUtils]: 19: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,155 INFO L290 TraceCheckUtils]: 20: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,155 INFO L290 TraceCheckUtils]: 21: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,156 INFO L290 TraceCheckUtils]: 22: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,156 INFO L290 TraceCheckUtils]: 23: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,156 INFO L290 TraceCheckUtils]: 24: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,157 INFO L290 TraceCheckUtils]: 25: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,157 INFO L290 TraceCheckUtils]: 26: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,157 INFO L290 TraceCheckUtils]: 27: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,158 INFO L290 TraceCheckUtils]: 28: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,158 INFO L290 TraceCheckUtils]: 29: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,159 INFO L290 TraceCheckUtils]: 30: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,159 INFO L290 TraceCheckUtils]: 31: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,159 INFO L290 TraceCheckUtils]: 32: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,160 INFO L290 TraceCheckUtils]: 33: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,160 INFO L290 TraceCheckUtils]: 34: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,161 INFO L290 TraceCheckUtils]: 35: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,161 INFO L290 TraceCheckUtils]: 36: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,161 INFO L290 TraceCheckUtils]: 37: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,162 INFO L290 TraceCheckUtils]: 38: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,162 INFO L290 TraceCheckUtils]: 39: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,162 INFO L290 TraceCheckUtils]: 40: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,163 INFO L290 TraceCheckUtils]: 41: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,163 INFO L290 TraceCheckUtils]: 42: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,164 INFO L290 TraceCheckUtils]: 43: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,164 INFO L290 TraceCheckUtils]: 44: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,165 INFO L290 TraceCheckUtils]: 45: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,165 INFO L290 TraceCheckUtils]: 46: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,165 INFO L290 TraceCheckUtils]: 47: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,166 INFO L290 TraceCheckUtils]: 48: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,166 INFO L290 TraceCheckUtils]: 49: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,166 INFO L290 TraceCheckUtils]: 50: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,167 INFO L290 TraceCheckUtils]: 51: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,167 INFO L290 TraceCheckUtils]: 52: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,168 INFO L290 TraceCheckUtils]: 53: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,168 INFO L290 TraceCheckUtils]: 54: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,168 INFO L290 TraceCheckUtils]: 55: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,169 INFO L290 TraceCheckUtils]: 56: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,169 INFO L290 TraceCheckUtils]: 57: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,170 INFO L290 TraceCheckUtils]: 58: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,170 INFO L290 TraceCheckUtils]: 59: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,170 INFO L290 TraceCheckUtils]: 60: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,171 INFO L290 TraceCheckUtils]: 61: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,171 INFO L290 TraceCheckUtils]: 62: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,171 INFO L290 TraceCheckUtils]: 63: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,172 INFO L290 TraceCheckUtils]: 64: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,172 INFO L290 TraceCheckUtils]: 65: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,173 INFO L290 TraceCheckUtils]: 66: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,173 INFO L290 TraceCheckUtils]: 67: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,173 INFO L290 TraceCheckUtils]: 68: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,174 INFO L290 TraceCheckUtils]: 69: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,174 INFO L290 TraceCheckUtils]: 70: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,174 INFO L290 TraceCheckUtils]: 71: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,175 INFO L290 TraceCheckUtils]: 72: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,175 INFO L290 TraceCheckUtils]: 73: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,176 INFO L290 TraceCheckUtils]: 74: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,176 INFO L290 TraceCheckUtils]: 75: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,176 INFO L290 TraceCheckUtils]: 76: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,177 INFO L290 TraceCheckUtils]: 77: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,177 INFO L290 TraceCheckUtils]: 78: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,177 INFO L290 TraceCheckUtils]: 79: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,178 INFO L290 TraceCheckUtils]: 80: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,178 INFO L290 TraceCheckUtils]: 81: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,179 INFO L290 TraceCheckUtils]: 82: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,179 INFO L290 TraceCheckUtils]: 83: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,179 INFO L290 TraceCheckUtils]: 84: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,180 INFO L290 TraceCheckUtils]: 85: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,180 INFO L290 TraceCheckUtils]: 86: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,181 INFO L290 TraceCheckUtils]: 87: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,181 INFO L290 TraceCheckUtils]: 88: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,181 INFO L290 TraceCheckUtils]: 89: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,182 INFO L290 TraceCheckUtils]: 90: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,182 INFO L290 TraceCheckUtils]: 91: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,182 INFO L290 TraceCheckUtils]: 92: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,183 INFO L290 TraceCheckUtils]: 93: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,183 INFO L290 TraceCheckUtils]: 94: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,184 INFO L290 TraceCheckUtils]: 95: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,184 INFO L290 TraceCheckUtils]: 96: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,184 INFO L290 TraceCheckUtils]: 97: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,185 INFO L290 TraceCheckUtils]: 98: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,185 INFO L290 TraceCheckUtils]: 99: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,186 INFO L290 TraceCheckUtils]: 100: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,186 INFO L290 TraceCheckUtils]: 101: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,186 INFO L290 TraceCheckUtils]: 102: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,187 INFO L290 TraceCheckUtils]: 103: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,187 INFO L290 TraceCheckUtils]: 104: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,188 INFO L290 TraceCheckUtils]: 105: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,188 INFO L290 TraceCheckUtils]: 106: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,188 INFO L290 TraceCheckUtils]: 107: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,189 INFO L290 TraceCheckUtils]: 108: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,189 INFO L290 TraceCheckUtils]: 109: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,189 INFO L290 TraceCheckUtils]: 110: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,190 INFO L290 TraceCheckUtils]: 111: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,190 INFO L290 TraceCheckUtils]: 112: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,191 INFO L290 TraceCheckUtils]: 113: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,191 INFO L290 TraceCheckUtils]: 114: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,191 INFO L290 TraceCheckUtils]: 115: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,192 INFO L290 TraceCheckUtils]: 116: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,192 INFO L290 TraceCheckUtils]: 117: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,193 INFO L290 TraceCheckUtils]: 118: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,193 INFO L290 TraceCheckUtils]: 119: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,193 INFO L290 TraceCheckUtils]: 120: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,194 INFO L290 TraceCheckUtils]: 121: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,194 INFO L290 TraceCheckUtils]: 122: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,195 INFO L290 TraceCheckUtils]: 123: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,195 INFO L290 TraceCheckUtils]: 124: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,195 INFO L290 TraceCheckUtils]: 125: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,196 INFO L290 TraceCheckUtils]: 126: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {63255#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:43,196 INFO L290 TraceCheckUtils]: 127: Hoare triple {63255#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {63254#false} is VALID [2022-02-21 04:24:43,196 INFO L290 TraceCheckUtils]: 128: Hoare triple {63254#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,196 INFO L290 TraceCheckUtils]: 129: Hoare triple {63254#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,196 INFO L290 TraceCheckUtils]: 130: Hoare triple {63254#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,197 INFO L290 TraceCheckUtils]: 131: Hoare triple {63254#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,197 INFO L290 TraceCheckUtils]: 132: Hoare triple {63254#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,197 INFO L290 TraceCheckUtils]: 133: Hoare triple {63254#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,197 INFO L290 TraceCheckUtils]: 134: Hoare triple {63254#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,197 INFO L290 TraceCheckUtils]: 135: Hoare triple {63254#false} assume !(1 == ~T13_E~0); {63254#false} is VALID [2022-02-21 04:24:43,197 INFO L290 TraceCheckUtils]: 136: Hoare triple {63254#false} assume 1 == ~E_1~0;~E_1~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,197 INFO L290 TraceCheckUtils]: 137: Hoare triple {63254#false} assume 1 == ~E_2~0;~E_2~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,198 INFO L290 TraceCheckUtils]: 138: Hoare triple {63254#false} assume 1 == ~E_3~0;~E_3~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,198 INFO L290 TraceCheckUtils]: 139: Hoare triple {63254#false} assume 1 == ~E_4~0;~E_4~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,198 INFO L290 TraceCheckUtils]: 140: Hoare triple {63254#false} assume 1 == ~E_5~0;~E_5~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,198 INFO L290 TraceCheckUtils]: 141: Hoare triple {63254#false} assume 1 == ~E_6~0;~E_6~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,198 INFO L290 TraceCheckUtils]: 142: Hoare triple {63254#false} assume 1 == ~E_7~0;~E_7~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,198 INFO L290 TraceCheckUtils]: 143: Hoare triple {63254#false} assume !(1 == ~E_8~0); {63254#false} is VALID [2022-02-21 04:24:43,198 INFO L290 TraceCheckUtils]: 144: Hoare triple {63254#false} assume 1 == ~E_9~0;~E_9~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,199 INFO L290 TraceCheckUtils]: 145: Hoare triple {63254#false} assume 1 == ~E_10~0;~E_10~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,199 INFO L290 TraceCheckUtils]: 146: Hoare triple {63254#false} assume 1 == ~E_11~0;~E_11~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,199 INFO L290 TraceCheckUtils]: 147: Hoare triple {63254#false} assume 1 == ~E_12~0;~E_12~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,199 INFO L290 TraceCheckUtils]: 148: Hoare triple {63254#false} assume 1 == ~E_13~0;~E_13~0 := 2; {63254#false} is VALID [2022-02-21 04:24:43,199 INFO L290 TraceCheckUtils]: 149: Hoare triple {63254#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {63254#false} is VALID [2022-02-21 04:24:43,199 INFO L290 TraceCheckUtils]: 150: Hoare triple {63254#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {63254#false} is VALID [2022-02-21 04:24:43,200 INFO L290 TraceCheckUtils]: 151: Hoare triple {63254#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {63254#false} is VALID [2022-02-21 04:24:43,200 INFO L290 TraceCheckUtils]: 152: Hoare triple {63254#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {63254#false} is VALID [2022-02-21 04:24:43,200 INFO L290 TraceCheckUtils]: 153: Hoare triple {63254#false} assume !(0 == start_simulation_~tmp~3#1); {63254#false} is VALID [2022-02-21 04:24:43,200 INFO L290 TraceCheckUtils]: 154: Hoare triple {63254#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {63254#false} is VALID [2022-02-21 04:24:43,200 INFO L290 TraceCheckUtils]: 155: Hoare triple {63254#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {63254#false} is VALID [2022-02-21 04:24:43,200 INFO L290 TraceCheckUtils]: 156: Hoare triple {63254#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {63254#false} is VALID [2022-02-21 04:24:43,200 INFO L290 TraceCheckUtils]: 157: Hoare triple {63254#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {63254#false} is VALID [2022-02-21 04:24:43,201 INFO L290 TraceCheckUtils]: 158: Hoare triple {63254#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {63254#false} is VALID [2022-02-21 04:24:43,201 INFO L290 TraceCheckUtils]: 159: Hoare triple {63254#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {63254#false} is VALID [2022-02-21 04:24:43,201 INFO L290 TraceCheckUtils]: 160: Hoare triple {63254#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {63254#false} is VALID [2022-02-21 04:24:43,201 INFO L290 TraceCheckUtils]: 161: Hoare triple {63254#false} assume !(0 != start_simulation_~tmp___0~1#1); {63254#false} is VALID [2022-02-21 04:24:43,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:43,202 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:43,202 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589638304] [2022-02-21 04:24:43,202 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1589638304] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:43,202 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:43,202 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:43,202 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1650616690] [2022-02-21 04:24:43,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:43,203 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:43,203 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:43,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:43,204 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:43,204 INFO L87 Difference]: Start difference. First operand 1914 states and 2828 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:44,571 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2022-02-21 04:24:44,571 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:44,572 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,663 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:44,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:44,756 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:44,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-02-21 04:24:44,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:44,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:44,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:44,856 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:44,856 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-02-21 04:24:44,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:44,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:44,877 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:44,879 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2827 transitions. Second operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,880 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2827 transitions. Second operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,882 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. Second operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:44,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:44,968 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2022-02-21 04:24:44,968 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:44,969 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:44,969 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:44,971 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2827 transitions. [2022-02-21 04:24:44,972 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2827 transitions. [2022-02-21 04:24:45,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:45,046 INFO L93 Difference]: Finished difference Result 1914 states and 2827 transitions. [2022-02-21 04:24:45,046 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:45,048 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:45,048 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:45,048 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:45,048 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:45,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4770114942528736) internal successors, (2827), 1913 states have internal predecessors, (2827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:45,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2827 transitions. [2022-02-21 04:24:45,134 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-02-21 04:24:45,134 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2827 transitions. [2022-02-21 04:24:45,134 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:24:45,134 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2827 transitions. [2022-02-21 04:24:45,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:45,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:45,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:45,140 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:45,140 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:45,140 INFO L791 eck$LassoCheckResult]: Stem: 66031#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66032#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 65851#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65567#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65568#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 66744#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 66745#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65703#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65704#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66158#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65993#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65994#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65770#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65771#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 66169#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 66346#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 66500#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 66537#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 65781#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65782#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 66957#L1258-2 assume !(0 == ~T1_E~0); 66076#L1263-1 assume !(0 == ~T2_E~0); 66077#L1268-1 assume !(0 == ~T3_E~0); 66380#L1273-1 assume !(0 == ~T4_E~0); 66939#L1278-1 assume !(0 == ~T5_E~0); 66800#L1283-1 assume !(0 == ~T6_E~0); 66801#L1288-1 assume !(0 == ~T7_E~0); 67037#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67025#L1298-1 assume !(0 == ~T9_E~0); 66951#L1303-1 assume !(0 == ~T10_E~0); 65596#L1308-1 assume !(0 == ~T11_E~0); 65538#L1313-1 assume !(0 == ~T12_E~0); 65539#L1318-1 assume !(0 == ~T13_E~0); 65545#L1323-1 assume !(0 == ~E_1~0); 65546#L1328-1 assume !(0 == ~E_2~0); 65713#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 66672#L1338-1 assume !(0 == ~E_4~0); 66673#L1343-1 assume !(0 == ~E_5~0); 66774#L1348-1 assume !(0 == ~E_6~0); 67060#L1353-1 assume !(0 == ~E_7~0); 66399#L1358-1 assume !(0 == ~E_8~0); 66400#L1363-1 assume !(0 == ~E_9~0); 66690#L1368-1 assume !(0 == ~E_10~0); 65375#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 65376#L1378-1 assume !(0 == ~E_12~0); 65662#L1383-1 assume !(0 == ~E_13~0); 65663#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66406#L607 assume 1 == ~m_pc~0; 66407#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 65733#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66772#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66326#L1560 assume !(0 != activate_threads_~tmp~1#1); 66327#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65558#L626 assume !(1 == ~t1_pc~0); 65559#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65827#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65828#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65997#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 65458#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65459#L645 assume 1 == ~t2_pc~0; 65575#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65532#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66209#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66210#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 66302#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66303#L664 assume 1 == ~t3_pc~0; 67059#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65299#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65300#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65958#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 65959#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66967#L683 assume !(1 == ~t4_pc~0); 66522#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 66474#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66475#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66509#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66633#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66252#L702 assume 1 == ~t5_pc~0; 66253#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66178#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66628#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66926#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 66867#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65347#L721 assume !(1 == ~t6_pc~0); 65321#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 65322#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65485#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65967#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 65968#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66569#L740 assume 1 == ~t7_pc~0; 65396#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65209#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65210#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65199#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 65200#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 65903#L759 assume !(1 == ~t8_pc~0); 65904#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 65933#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66626#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66627#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 66758#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 67036#L778 assume 1 == ~t9_pc~0; 66923#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 65374#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65314#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65243#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 65244#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65571#L797 assume !(1 == ~t10_pc~0); 65572#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 65690#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66824#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66074#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 66075#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66364#L816 assume 1 == ~t11_pc~0; 65279#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65280#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66035#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65974#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 65975#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 66499#L835 assume 1 == ~t12_pc~0; 66377#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 65443#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65465#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65606#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 66131#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 66132#L854 assume !(1 == ~t13_pc~0); 65772#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 65773#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 65823#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 65483#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 65484#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66863#L1401 assume !(1 == ~M_E~0); 65962#L1401-2 assume !(1 == ~T1_E~0); 65963#L1406-1 assume !(1 == ~T2_E~0); 66558#L1411-1 assume !(1 == ~T3_E~0); 66559#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66225#L1421-1 assume !(1 == ~T5_E~0); 65768#L1426-1 assume !(1 == ~T6_E~0); 65769#L1431-1 assume !(1 == ~T7_E~0); 65317#L1436-1 assume !(1 == ~T8_E~0); 65318#L1441-1 assume !(1 == ~T9_E~0); 66065#L1446-1 assume !(1 == ~T10_E~0); 66066#L1451-1 assume !(1 == ~T11_E~0); 66771#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 66425#L1461-1 assume !(1 == ~T13_E~0); 65986#L1466-1 assume !(1 == ~E_1~0); 65987#L1471-1 assume !(1 == ~E_2~0); 66756#L1476-1 assume !(1 == ~E_3~0); 66757#L1481-1 assume !(1 == ~E_4~0); 66905#L1486-1 assume !(1 == ~E_5~0); 65611#L1491-1 assume !(1 == ~E_6~0); 65251#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 65252#L1501-1 assume !(1 == ~E_8~0); 66063#L1506-1 assume !(1 == ~E_9~0); 66064#L1511-1 assume !(1 == ~E_10~0); 66020#L1516-1 assume !(1 == ~E_11~0); 65195#L1521-1 assume !(1 == ~E_12~0); 65196#L1526-1 assume !(1 == ~E_13~0); 65250#L1531-1 assume { :end_inline_reset_delta_events } true; 65793#L1892-2 [2022-02-21 04:24:45,141 INFO L793 eck$LassoCheckResult]: Loop: 65793#L1892-2 assume !false; 66816#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 67014#L1233 assume !false; 66997#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 66329#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 66309#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 66467#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 65293#L1046 assume !(0 != eval_~tmp~0#1); 65295#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65329#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66501#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 67058#L1258-5 assume !(0 == ~T1_E~0); 65471#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65472#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67050#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67056#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67057#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65695#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 65696#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 66813#L1298-3 assume !(0 == ~T9_E~0); 66814#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 66973#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 66812#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 66313#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 65473#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 65474#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66897#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65616#L1338-3 assume !(0 == ~E_4~0); 65617#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 66729#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 66902#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 66903#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 66269#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 65829#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 65830#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 66586#L1378-3 assume !(0 == ~E_12~0); 66587#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 66768#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66769#L607-42 assume !(1 == ~m_pc~0); 66383#L607-44 is_master_triggered_~__retres1~0#1 := 0; 66110#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66111#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65843#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65844#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66365#L626-42 assume 1 == ~t1_pc~0; 65927#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65928#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66232#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 66233#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65507#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65508#L645-42 assume !(1 == ~t2_pc~0); 66707#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 66708#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66873#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65714#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65221#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65222#L664-42 assume !(1 == ~t3_pc~0); 65748#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 65749#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67000#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66535#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66536#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66701#L683-42 assume !(1 == ~t4_pc~0); 66409#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 66410#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66542#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66962#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66963#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66807#L702-42 assume 1 == ~t5_pc~0; 66295#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65920#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66216#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 66889#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65237#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65238#L721-42 assume !(1 == ~t6_pc~0); 65392#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 65411#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65875#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 67042#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66047#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65893#L740-42 assume 1 == ~t7_pc~0; 65894#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65631#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66172#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66027#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 66028#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66301#L759-42 assume !(1 == ~t8_pc~0); 66151#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 66082#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 66083#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66161#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66162#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66257#L778-42 assume !(1 == ~t9_pc~0); 66095#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 66096#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66506#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66411#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 66412#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66469#L797-42 assume 1 == ~t10_pc~0; 65636#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 65637#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66638#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 66947#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 66507#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66508#L816-42 assume 1 == ~t11_pc~0; 65185#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65186#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65728#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65729#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65808#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65809#L835-42 assume 1 == ~t12_pc~0; 66213#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 66106#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65783#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65784#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 66866#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 66650#L854-42 assume 1 == ~t13_pc~0; 66651#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 65727#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 65337#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 65338#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 65984#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65985#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 66763#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65574#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65438#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65439#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66038#L1421-3 assume !(1 == ~T5_E~0); 66039#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65614#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65615#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65201#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65202#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 66791#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 66122#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 65775#L1461-3 assume !(1 == ~T13_E~0); 65776#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67053#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65715#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65716#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66116#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65743#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65744#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 66156#L1501-3 assume !(1 == ~E_8~0); 66157#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 66583#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 66573#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 66574#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 66273#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 66274#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 66668#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 65550#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 66443#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 66084#L1911 assume !(0 == start_simulation_~tmp~3#1); 66085#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 66607#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 65674#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 66545#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 65379#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65380#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65609#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 65610#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 65793#L1892-2 [2022-02-21 04:24:45,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:45,141 INFO L85 PathProgramCache]: Analyzing trace with hash -778058914, now seen corresponding path program 1 times [2022-02-21 04:24:45,142 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:45,142 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068165569] [2022-02-21 04:24:45,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:45,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:45,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:45,167 INFO L290 TraceCheckUtils]: 0: Hoare triple {70915#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {70915#true} is VALID [2022-02-21 04:24:45,168 INFO L290 TraceCheckUtils]: 1: Hoare triple {70915#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,168 INFO L290 TraceCheckUtils]: 2: Hoare triple {70917#(= ~t10_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,169 INFO L290 TraceCheckUtils]: 3: Hoare triple {70917#(= ~t10_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,169 INFO L290 TraceCheckUtils]: 4: Hoare triple {70917#(= ~t10_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,169 INFO L290 TraceCheckUtils]: 5: Hoare triple {70917#(= ~t10_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,170 INFO L290 TraceCheckUtils]: 6: Hoare triple {70917#(= ~t10_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,170 INFO L290 TraceCheckUtils]: 7: Hoare triple {70917#(= ~t10_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,170 INFO L290 TraceCheckUtils]: 8: Hoare triple {70917#(= ~t10_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,171 INFO L290 TraceCheckUtils]: 9: Hoare triple {70917#(= ~t10_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,171 INFO L290 TraceCheckUtils]: 10: Hoare triple {70917#(= ~t10_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,171 INFO L290 TraceCheckUtils]: 11: Hoare triple {70917#(= ~t10_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,172 INFO L290 TraceCheckUtils]: 12: Hoare triple {70917#(= ~t10_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,172 INFO L290 TraceCheckUtils]: 13: Hoare triple {70917#(= ~t10_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {70917#(= ~t10_i~0 1)} is VALID [2022-02-21 04:24:45,172 INFO L290 TraceCheckUtils]: 14: Hoare triple {70917#(= ~t10_i~0 1)} assume !(1 == ~t10_i~0);~t10_st~0 := 2; {70916#false} is VALID [2022-02-21 04:24:45,172 INFO L290 TraceCheckUtils]: 15: Hoare triple {70916#false} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {70916#false} is VALID [2022-02-21 04:24:45,172 INFO L290 TraceCheckUtils]: 16: Hoare triple {70916#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {70916#false} is VALID [2022-02-21 04:24:45,173 INFO L290 TraceCheckUtils]: 17: Hoare triple {70916#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {70916#false} is VALID [2022-02-21 04:24:45,173 INFO L290 TraceCheckUtils]: 18: Hoare triple {70916#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {70916#false} is VALID [2022-02-21 04:24:45,173 INFO L290 TraceCheckUtils]: 19: Hoare triple {70916#false} assume 0 == ~M_E~0;~M_E~0 := 1; {70916#false} is VALID [2022-02-21 04:24:45,173 INFO L290 TraceCheckUtils]: 20: Hoare triple {70916#false} assume !(0 == ~T1_E~0); {70916#false} is VALID [2022-02-21 04:24:45,173 INFO L290 TraceCheckUtils]: 21: Hoare triple {70916#false} assume !(0 == ~T2_E~0); {70916#false} is VALID [2022-02-21 04:24:45,173 INFO L290 TraceCheckUtils]: 22: Hoare triple {70916#false} assume !(0 == ~T3_E~0); {70916#false} is VALID [2022-02-21 04:24:45,173 INFO L290 TraceCheckUtils]: 23: Hoare triple {70916#false} assume !(0 == ~T4_E~0); {70916#false} is VALID [2022-02-21 04:24:45,174 INFO L290 TraceCheckUtils]: 24: Hoare triple {70916#false} assume !(0 == ~T5_E~0); {70916#false} is VALID [2022-02-21 04:24:45,174 INFO L290 TraceCheckUtils]: 25: Hoare triple {70916#false} assume !(0 == ~T6_E~0); {70916#false} is VALID [2022-02-21 04:24:45,174 INFO L290 TraceCheckUtils]: 26: Hoare triple {70916#false} assume !(0 == ~T7_E~0); {70916#false} is VALID [2022-02-21 04:24:45,174 INFO L290 TraceCheckUtils]: 27: Hoare triple {70916#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {70916#false} is VALID [2022-02-21 04:24:45,174 INFO L290 TraceCheckUtils]: 28: Hoare triple {70916#false} assume !(0 == ~T9_E~0); {70916#false} is VALID [2022-02-21 04:24:45,174 INFO L290 TraceCheckUtils]: 29: Hoare triple {70916#false} assume !(0 == ~T10_E~0); {70916#false} is VALID [2022-02-21 04:24:45,174 INFO L290 TraceCheckUtils]: 30: Hoare triple {70916#false} assume !(0 == ~T11_E~0); {70916#false} is VALID [2022-02-21 04:24:45,175 INFO L290 TraceCheckUtils]: 31: Hoare triple {70916#false} assume !(0 == ~T12_E~0); {70916#false} is VALID [2022-02-21 04:24:45,175 INFO L290 TraceCheckUtils]: 32: Hoare triple {70916#false} assume !(0 == ~T13_E~0); {70916#false} is VALID [2022-02-21 04:24:45,175 INFO L290 TraceCheckUtils]: 33: Hoare triple {70916#false} assume !(0 == ~E_1~0); {70916#false} is VALID [2022-02-21 04:24:45,175 INFO L290 TraceCheckUtils]: 34: Hoare triple {70916#false} assume !(0 == ~E_2~0); {70916#false} is VALID [2022-02-21 04:24:45,175 INFO L290 TraceCheckUtils]: 35: Hoare triple {70916#false} assume 0 == ~E_3~0;~E_3~0 := 1; {70916#false} is VALID [2022-02-21 04:24:45,175 INFO L290 TraceCheckUtils]: 36: Hoare triple {70916#false} assume !(0 == ~E_4~0); {70916#false} is VALID [2022-02-21 04:24:45,175 INFO L290 TraceCheckUtils]: 37: Hoare triple {70916#false} assume !(0 == ~E_5~0); {70916#false} is VALID [2022-02-21 04:24:45,176 INFO L290 TraceCheckUtils]: 38: Hoare triple {70916#false} assume !(0 == ~E_6~0); {70916#false} is VALID [2022-02-21 04:24:45,176 INFO L290 TraceCheckUtils]: 39: Hoare triple {70916#false} assume !(0 == ~E_7~0); {70916#false} is VALID [2022-02-21 04:24:45,176 INFO L290 TraceCheckUtils]: 40: Hoare triple {70916#false} assume !(0 == ~E_8~0); {70916#false} is VALID [2022-02-21 04:24:45,176 INFO L290 TraceCheckUtils]: 41: Hoare triple {70916#false} assume !(0 == ~E_9~0); {70916#false} is VALID [2022-02-21 04:24:45,176 INFO L290 TraceCheckUtils]: 42: Hoare triple {70916#false} assume !(0 == ~E_10~0); {70916#false} is VALID [2022-02-21 04:24:45,176 INFO L290 TraceCheckUtils]: 43: Hoare triple {70916#false} assume 0 == ~E_11~0;~E_11~0 := 1; {70916#false} is VALID [2022-02-21 04:24:45,177 INFO L290 TraceCheckUtils]: 44: Hoare triple {70916#false} assume !(0 == ~E_12~0); {70916#false} is VALID [2022-02-21 04:24:45,177 INFO L290 TraceCheckUtils]: 45: Hoare triple {70916#false} assume !(0 == ~E_13~0); {70916#false} is VALID [2022-02-21 04:24:45,177 INFO L290 TraceCheckUtils]: 46: Hoare triple {70916#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {70916#false} is VALID [2022-02-21 04:24:45,177 INFO L290 TraceCheckUtils]: 47: Hoare triple {70916#false} assume 1 == ~m_pc~0; {70916#false} is VALID [2022-02-21 04:24:45,177 INFO L290 TraceCheckUtils]: 48: Hoare triple {70916#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {70916#false} is VALID [2022-02-21 04:24:45,177 INFO L290 TraceCheckUtils]: 49: Hoare triple {70916#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {70916#false} is VALID [2022-02-21 04:24:45,177 INFO L290 TraceCheckUtils]: 50: Hoare triple {70916#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {70916#false} is VALID [2022-02-21 04:24:45,178 INFO L290 TraceCheckUtils]: 51: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp~1#1); {70916#false} is VALID [2022-02-21 04:24:45,178 INFO L290 TraceCheckUtils]: 52: Hoare triple {70916#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {70916#false} is VALID [2022-02-21 04:24:45,178 INFO L290 TraceCheckUtils]: 53: Hoare triple {70916#false} assume !(1 == ~t1_pc~0); {70916#false} is VALID [2022-02-21 04:24:45,178 INFO L290 TraceCheckUtils]: 54: Hoare triple {70916#false} is_transmit1_triggered_~__retres1~1#1 := 0; {70916#false} is VALID [2022-02-21 04:24:45,178 INFO L290 TraceCheckUtils]: 55: Hoare triple {70916#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {70916#false} is VALID [2022-02-21 04:24:45,178 INFO L290 TraceCheckUtils]: 56: Hoare triple {70916#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {70916#false} is VALID [2022-02-21 04:24:45,178 INFO L290 TraceCheckUtils]: 57: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp___0~0#1); {70916#false} is VALID [2022-02-21 04:24:45,179 INFO L290 TraceCheckUtils]: 58: Hoare triple {70916#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {70916#false} is VALID [2022-02-21 04:24:45,179 INFO L290 TraceCheckUtils]: 59: Hoare triple {70916#false} assume 1 == ~t2_pc~0; {70916#false} is VALID [2022-02-21 04:24:45,179 INFO L290 TraceCheckUtils]: 60: Hoare triple {70916#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {70916#false} is VALID [2022-02-21 04:24:45,179 INFO L290 TraceCheckUtils]: 61: Hoare triple {70916#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {70916#false} is VALID [2022-02-21 04:24:45,179 INFO L290 TraceCheckUtils]: 62: Hoare triple {70916#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {70916#false} is VALID [2022-02-21 04:24:45,179 INFO L290 TraceCheckUtils]: 63: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp___1~0#1); {70916#false} is VALID [2022-02-21 04:24:45,179 INFO L290 TraceCheckUtils]: 64: Hoare triple {70916#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {70916#false} is VALID [2022-02-21 04:24:45,180 INFO L290 TraceCheckUtils]: 65: Hoare triple {70916#false} assume 1 == ~t3_pc~0; {70916#false} is VALID [2022-02-21 04:24:45,180 INFO L290 TraceCheckUtils]: 66: Hoare triple {70916#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {70916#false} is VALID [2022-02-21 04:24:45,180 INFO L290 TraceCheckUtils]: 67: Hoare triple {70916#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {70916#false} is VALID [2022-02-21 04:24:45,180 INFO L290 TraceCheckUtils]: 68: Hoare triple {70916#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {70916#false} is VALID [2022-02-21 04:24:45,180 INFO L290 TraceCheckUtils]: 69: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp___2~0#1); {70916#false} is VALID [2022-02-21 04:24:45,180 INFO L290 TraceCheckUtils]: 70: Hoare triple {70916#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {70916#false} is VALID [2022-02-21 04:24:45,180 INFO L290 TraceCheckUtils]: 71: Hoare triple {70916#false} assume !(1 == ~t4_pc~0); {70916#false} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 72: Hoare triple {70916#false} is_transmit4_triggered_~__retres1~4#1 := 0; {70916#false} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 73: Hoare triple {70916#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {70916#false} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 74: Hoare triple {70916#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {70916#false} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 75: Hoare triple {70916#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {70916#false} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 76: Hoare triple {70916#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {70916#false} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 77: Hoare triple {70916#false} assume 1 == ~t5_pc~0; {70916#false} is VALID [2022-02-21 04:24:45,181 INFO L290 TraceCheckUtils]: 78: Hoare triple {70916#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {70916#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 79: Hoare triple {70916#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {70916#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 80: Hoare triple {70916#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {70916#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 81: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp___4~0#1); {70916#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 82: Hoare triple {70916#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {70916#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 83: Hoare triple {70916#false} assume !(1 == ~t6_pc~0); {70916#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 84: Hoare triple {70916#false} is_transmit6_triggered_~__retres1~6#1 := 0; {70916#false} is VALID [2022-02-21 04:24:45,182 INFO L290 TraceCheckUtils]: 85: Hoare triple {70916#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {70916#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 86: Hoare triple {70916#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {70916#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 87: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp___5~0#1); {70916#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 88: Hoare triple {70916#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {70916#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 89: Hoare triple {70916#false} assume 1 == ~t7_pc~0; {70916#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 90: Hoare triple {70916#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {70916#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 91: Hoare triple {70916#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {70916#false} is VALID [2022-02-21 04:24:45,183 INFO L290 TraceCheckUtils]: 92: Hoare triple {70916#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {70916#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 93: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp___6~0#1); {70916#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 94: Hoare triple {70916#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {70916#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 95: Hoare triple {70916#false} assume !(1 == ~t8_pc~0); {70916#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 96: Hoare triple {70916#false} is_transmit8_triggered_~__retres1~8#1 := 0; {70916#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 97: Hoare triple {70916#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {70916#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 98: Hoare triple {70916#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {70916#false} is VALID [2022-02-21 04:24:45,184 INFO L290 TraceCheckUtils]: 99: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp___7~0#1); {70916#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 100: Hoare triple {70916#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {70916#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 101: Hoare triple {70916#false} assume 1 == ~t9_pc~0; {70916#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 102: Hoare triple {70916#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {70916#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 103: Hoare triple {70916#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {70916#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 104: Hoare triple {70916#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {70916#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 105: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp___8~0#1); {70916#false} is VALID [2022-02-21 04:24:45,185 INFO L290 TraceCheckUtils]: 106: Hoare triple {70916#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {70916#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 107: Hoare triple {70916#false} assume !(1 == ~t10_pc~0); {70916#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 108: Hoare triple {70916#false} is_transmit10_triggered_~__retres1~10#1 := 0; {70916#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 109: Hoare triple {70916#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {70916#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 110: Hoare triple {70916#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {70916#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 111: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp___9~0#1); {70916#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 112: Hoare triple {70916#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {70916#false} is VALID [2022-02-21 04:24:45,186 INFO L290 TraceCheckUtils]: 113: Hoare triple {70916#false} assume 1 == ~t11_pc~0; {70916#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 114: Hoare triple {70916#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {70916#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 115: Hoare triple {70916#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {70916#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 116: Hoare triple {70916#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {70916#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 117: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp___10~0#1); {70916#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 118: Hoare triple {70916#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {70916#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 119: Hoare triple {70916#false} assume 1 == ~t12_pc~0; {70916#false} is VALID [2022-02-21 04:24:45,187 INFO L290 TraceCheckUtils]: 120: Hoare triple {70916#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {70916#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 121: Hoare triple {70916#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {70916#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 122: Hoare triple {70916#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {70916#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 123: Hoare triple {70916#false} assume !(0 != activate_threads_~tmp___11~0#1); {70916#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 124: Hoare triple {70916#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {70916#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 125: Hoare triple {70916#false} assume !(1 == ~t13_pc~0); {70916#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 126: Hoare triple {70916#false} is_transmit13_triggered_~__retres1~13#1 := 0; {70916#false} is VALID [2022-02-21 04:24:45,188 INFO L290 TraceCheckUtils]: 127: Hoare triple {70916#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {70916#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 128: Hoare triple {70916#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {70916#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 129: Hoare triple {70916#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {70916#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 130: Hoare triple {70916#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {70916#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 131: Hoare triple {70916#false} assume !(1 == ~M_E~0); {70916#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 132: Hoare triple {70916#false} assume !(1 == ~T1_E~0); {70916#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 133: Hoare triple {70916#false} assume !(1 == ~T2_E~0); {70916#false} is VALID [2022-02-21 04:24:45,189 INFO L290 TraceCheckUtils]: 134: Hoare triple {70916#false} assume !(1 == ~T3_E~0); {70916#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 135: Hoare triple {70916#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {70916#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 136: Hoare triple {70916#false} assume !(1 == ~T5_E~0); {70916#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 137: Hoare triple {70916#false} assume !(1 == ~T6_E~0); {70916#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 138: Hoare triple {70916#false} assume !(1 == ~T7_E~0); {70916#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 139: Hoare triple {70916#false} assume !(1 == ~T8_E~0); {70916#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 140: Hoare triple {70916#false} assume !(1 == ~T9_E~0); {70916#false} is VALID [2022-02-21 04:24:45,190 INFO L290 TraceCheckUtils]: 141: Hoare triple {70916#false} assume !(1 == ~T10_E~0); {70916#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 142: Hoare triple {70916#false} assume !(1 == ~T11_E~0); {70916#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 143: Hoare triple {70916#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {70916#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 144: Hoare triple {70916#false} assume !(1 == ~T13_E~0); {70916#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 145: Hoare triple {70916#false} assume !(1 == ~E_1~0); {70916#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 146: Hoare triple {70916#false} assume !(1 == ~E_2~0); {70916#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 147: Hoare triple {70916#false} assume !(1 == ~E_3~0); {70916#false} is VALID [2022-02-21 04:24:45,191 INFO L290 TraceCheckUtils]: 148: Hoare triple {70916#false} assume !(1 == ~E_4~0); {70916#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 149: Hoare triple {70916#false} assume !(1 == ~E_5~0); {70916#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 150: Hoare triple {70916#false} assume !(1 == ~E_6~0); {70916#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 151: Hoare triple {70916#false} assume 1 == ~E_7~0;~E_7~0 := 2; {70916#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 152: Hoare triple {70916#false} assume !(1 == ~E_8~0); {70916#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 153: Hoare triple {70916#false} assume !(1 == ~E_9~0); {70916#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 154: Hoare triple {70916#false} assume !(1 == ~E_10~0); {70916#false} is VALID [2022-02-21 04:24:45,192 INFO L290 TraceCheckUtils]: 155: Hoare triple {70916#false} assume !(1 == ~E_11~0); {70916#false} is VALID [2022-02-21 04:24:45,193 INFO L290 TraceCheckUtils]: 156: Hoare triple {70916#false} assume !(1 == ~E_12~0); {70916#false} is VALID [2022-02-21 04:24:45,193 INFO L290 TraceCheckUtils]: 157: Hoare triple {70916#false} assume !(1 == ~E_13~0); {70916#false} is VALID [2022-02-21 04:24:45,193 INFO L290 TraceCheckUtils]: 158: Hoare triple {70916#false} assume { :end_inline_reset_delta_events } true; {70916#false} is VALID [2022-02-21 04:24:45,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:45,193 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:45,194 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2068165569] [2022-02-21 04:24:45,194 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2068165569] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:45,194 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:45,194 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:45,194 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705507762] [2022-02-21 04:24:45,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:45,195 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:45,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:45,195 INFO L85 PathProgramCache]: Analyzing trace with hash -1608286372, now seen corresponding path program 1 times [2022-02-21 04:24:45,195 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:45,196 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079598124] [2022-02-21 04:24:45,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:45,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:45,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:45,229 INFO L290 TraceCheckUtils]: 0: Hoare triple {70918#true} assume !false; {70918#true} is VALID [2022-02-21 04:24:45,229 INFO L290 TraceCheckUtils]: 1: Hoare triple {70918#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {70918#true} is VALID [2022-02-21 04:24:45,255 INFO L290 TraceCheckUtils]: 2: Hoare triple {70918#true} assume !false; {70918#true} is VALID [2022-02-21 04:24:45,255 INFO L290 TraceCheckUtils]: 3: Hoare triple {70918#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {70918#true} is VALID [2022-02-21 04:24:45,255 INFO L290 TraceCheckUtils]: 4: Hoare triple {70918#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {70918#true} is VALID [2022-02-21 04:24:45,255 INFO L290 TraceCheckUtils]: 5: Hoare triple {70918#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {70918#true} is VALID [2022-02-21 04:24:45,255 INFO L290 TraceCheckUtils]: 6: Hoare triple {70918#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {70918#true} is VALID [2022-02-21 04:24:45,255 INFO L290 TraceCheckUtils]: 7: Hoare triple {70918#true} assume !(0 != eval_~tmp~0#1); {70918#true} is VALID [2022-02-21 04:24:45,256 INFO L290 TraceCheckUtils]: 8: Hoare triple {70918#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {70918#true} is VALID [2022-02-21 04:24:45,256 INFO L290 TraceCheckUtils]: 9: Hoare triple {70918#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {70918#true} is VALID [2022-02-21 04:24:45,256 INFO L290 TraceCheckUtils]: 10: Hoare triple {70918#true} assume 0 == ~M_E~0;~M_E~0 := 1; {70918#true} is VALID [2022-02-21 04:24:45,256 INFO L290 TraceCheckUtils]: 11: Hoare triple {70918#true} assume !(0 == ~T1_E~0); {70918#true} is VALID [2022-02-21 04:24:45,256 INFO L290 TraceCheckUtils]: 12: Hoare triple {70918#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {70918#true} is VALID [2022-02-21 04:24:45,256 INFO L290 TraceCheckUtils]: 13: Hoare triple {70918#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {70918#true} is VALID [2022-02-21 04:24:45,256 INFO L290 TraceCheckUtils]: 14: Hoare triple {70918#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {70918#true} is VALID [2022-02-21 04:24:45,257 INFO L290 TraceCheckUtils]: 15: Hoare triple {70918#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,257 INFO L290 TraceCheckUtils]: 16: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,258 INFO L290 TraceCheckUtils]: 17: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,258 INFO L290 TraceCheckUtils]: 18: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,258 INFO L290 TraceCheckUtils]: 19: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,259 INFO L290 TraceCheckUtils]: 20: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,259 INFO L290 TraceCheckUtils]: 21: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,260 INFO L290 TraceCheckUtils]: 22: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,260 INFO L290 TraceCheckUtils]: 23: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,260 INFO L290 TraceCheckUtils]: 24: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,261 INFO L290 TraceCheckUtils]: 25: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,261 INFO L290 TraceCheckUtils]: 26: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,261 INFO L290 TraceCheckUtils]: 27: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,262 INFO L290 TraceCheckUtils]: 28: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,262 INFO L290 TraceCheckUtils]: 29: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,262 INFO L290 TraceCheckUtils]: 30: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,263 INFO L290 TraceCheckUtils]: 31: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,263 INFO L290 TraceCheckUtils]: 32: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,264 INFO L290 TraceCheckUtils]: 33: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,264 INFO L290 TraceCheckUtils]: 34: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,264 INFO L290 TraceCheckUtils]: 35: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,265 INFO L290 TraceCheckUtils]: 36: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,265 INFO L290 TraceCheckUtils]: 37: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,266 INFO L290 TraceCheckUtils]: 38: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,266 INFO L290 TraceCheckUtils]: 39: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,266 INFO L290 TraceCheckUtils]: 40: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,267 INFO L290 TraceCheckUtils]: 41: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,267 INFO L290 TraceCheckUtils]: 42: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,267 INFO L290 TraceCheckUtils]: 43: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,268 INFO L290 TraceCheckUtils]: 44: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,268 INFO L290 TraceCheckUtils]: 45: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,269 INFO L290 TraceCheckUtils]: 46: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,269 INFO L290 TraceCheckUtils]: 47: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,269 INFO L290 TraceCheckUtils]: 48: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,270 INFO L290 TraceCheckUtils]: 49: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,270 INFO L290 TraceCheckUtils]: 50: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,271 INFO L290 TraceCheckUtils]: 51: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,271 INFO L290 TraceCheckUtils]: 52: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,271 INFO L290 TraceCheckUtils]: 53: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,272 INFO L290 TraceCheckUtils]: 54: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,272 INFO L290 TraceCheckUtils]: 55: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,272 INFO L290 TraceCheckUtils]: 56: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,273 INFO L290 TraceCheckUtils]: 57: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,273 INFO L290 TraceCheckUtils]: 58: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,274 INFO L290 TraceCheckUtils]: 59: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,274 INFO L290 TraceCheckUtils]: 60: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,274 INFO L290 TraceCheckUtils]: 61: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,275 INFO L290 TraceCheckUtils]: 62: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,275 INFO L290 TraceCheckUtils]: 63: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,275 INFO L290 TraceCheckUtils]: 64: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,276 INFO L290 TraceCheckUtils]: 65: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,276 INFO L290 TraceCheckUtils]: 66: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,276 INFO L290 TraceCheckUtils]: 67: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,277 INFO L290 TraceCheckUtils]: 68: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,277 INFO L290 TraceCheckUtils]: 69: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,278 INFO L290 TraceCheckUtils]: 70: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,278 INFO L290 TraceCheckUtils]: 71: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,278 INFO L290 TraceCheckUtils]: 72: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,279 INFO L290 TraceCheckUtils]: 73: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,279 INFO L290 TraceCheckUtils]: 74: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,279 INFO L290 TraceCheckUtils]: 75: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,280 INFO L290 TraceCheckUtils]: 76: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,280 INFO L290 TraceCheckUtils]: 77: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,280 INFO L290 TraceCheckUtils]: 78: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,281 INFO L290 TraceCheckUtils]: 79: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,281 INFO L290 TraceCheckUtils]: 80: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,282 INFO L290 TraceCheckUtils]: 81: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,282 INFO L290 TraceCheckUtils]: 82: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,282 INFO L290 TraceCheckUtils]: 83: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,283 INFO L290 TraceCheckUtils]: 84: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,283 INFO L290 TraceCheckUtils]: 85: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,283 INFO L290 TraceCheckUtils]: 86: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,284 INFO L290 TraceCheckUtils]: 87: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,284 INFO L290 TraceCheckUtils]: 88: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,284 INFO L290 TraceCheckUtils]: 89: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,285 INFO L290 TraceCheckUtils]: 90: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,285 INFO L290 TraceCheckUtils]: 91: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,286 INFO L290 TraceCheckUtils]: 92: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,286 INFO L290 TraceCheckUtils]: 93: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,286 INFO L290 TraceCheckUtils]: 94: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,287 INFO L290 TraceCheckUtils]: 95: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,287 INFO L290 TraceCheckUtils]: 96: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,287 INFO L290 TraceCheckUtils]: 97: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,288 INFO L290 TraceCheckUtils]: 98: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,288 INFO L290 TraceCheckUtils]: 99: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,289 INFO L290 TraceCheckUtils]: 100: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,289 INFO L290 TraceCheckUtils]: 101: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,289 INFO L290 TraceCheckUtils]: 102: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,290 INFO L290 TraceCheckUtils]: 103: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,290 INFO L290 TraceCheckUtils]: 104: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,290 INFO L290 TraceCheckUtils]: 105: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,291 INFO L290 TraceCheckUtils]: 106: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,291 INFO L290 TraceCheckUtils]: 107: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,292 INFO L290 TraceCheckUtils]: 108: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,292 INFO L290 TraceCheckUtils]: 109: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,292 INFO L290 TraceCheckUtils]: 110: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,293 INFO L290 TraceCheckUtils]: 111: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,293 INFO L290 TraceCheckUtils]: 112: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,293 INFO L290 TraceCheckUtils]: 113: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,294 INFO L290 TraceCheckUtils]: 114: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,294 INFO L290 TraceCheckUtils]: 115: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,294 INFO L290 TraceCheckUtils]: 116: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,295 INFO L290 TraceCheckUtils]: 117: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,295 INFO L290 TraceCheckUtils]: 118: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,296 INFO L290 TraceCheckUtils]: 119: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,296 INFO L290 TraceCheckUtils]: 120: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,296 INFO L290 TraceCheckUtils]: 121: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,297 INFO L290 TraceCheckUtils]: 122: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,297 INFO L290 TraceCheckUtils]: 123: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,297 INFO L290 TraceCheckUtils]: 124: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,298 INFO L290 TraceCheckUtils]: 125: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,298 INFO L290 TraceCheckUtils]: 126: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {70920#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 127: Hoare triple {70920#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {70919#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 128: Hoare triple {70919#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 129: Hoare triple {70919#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 130: Hoare triple {70919#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 131: Hoare triple {70919#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 132: Hoare triple {70919#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,299 INFO L290 TraceCheckUtils]: 133: Hoare triple {70919#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 134: Hoare triple {70919#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 135: Hoare triple {70919#false} assume !(1 == ~T13_E~0); {70919#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 136: Hoare triple {70919#false} assume 1 == ~E_1~0;~E_1~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 137: Hoare triple {70919#false} assume 1 == ~E_2~0;~E_2~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 138: Hoare triple {70919#false} assume 1 == ~E_3~0;~E_3~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 139: Hoare triple {70919#false} assume 1 == ~E_4~0;~E_4~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,300 INFO L290 TraceCheckUtils]: 140: Hoare triple {70919#false} assume 1 == ~E_5~0;~E_5~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 141: Hoare triple {70919#false} assume 1 == ~E_6~0;~E_6~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 142: Hoare triple {70919#false} assume 1 == ~E_7~0;~E_7~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 143: Hoare triple {70919#false} assume !(1 == ~E_8~0); {70919#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 144: Hoare triple {70919#false} assume 1 == ~E_9~0;~E_9~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 145: Hoare triple {70919#false} assume 1 == ~E_10~0;~E_10~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 146: Hoare triple {70919#false} assume 1 == ~E_11~0;~E_11~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 147: Hoare triple {70919#false} assume 1 == ~E_12~0;~E_12~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,301 INFO L290 TraceCheckUtils]: 148: Hoare triple {70919#false} assume 1 == ~E_13~0;~E_13~0 := 2; {70919#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 149: Hoare triple {70919#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {70919#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 150: Hoare triple {70919#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {70919#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 151: Hoare triple {70919#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {70919#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 152: Hoare triple {70919#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {70919#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 153: Hoare triple {70919#false} assume !(0 == start_simulation_~tmp~3#1); {70919#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 154: Hoare triple {70919#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {70919#false} is VALID [2022-02-21 04:24:45,302 INFO L290 TraceCheckUtils]: 155: Hoare triple {70919#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {70919#false} is VALID [2022-02-21 04:24:45,303 INFO L290 TraceCheckUtils]: 156: Hoare triple {70919#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {70919#false} is VALID [2022-02-21 04:24:45,303 INFO L290 TraceCheckUtils]: 157: Hoare triple {70919#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {70919#false} is VALID [2022-02-21 04:24:45,303 INFO L290 TraceCheckUtils]: 158: Hoare triple {70919#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {70919#false} is VALID [2022-02-21 04:24:45,303 INFO L290 TraceCheckUtils]: 159: Hoare triple {70919#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {70919#false} is VALID [2022-02-21 04:24:45,303 INFO L290 TraceCheckUtils]: 160: Hoare triple {70919#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {70919#false} is VALID [2022-02-21 04:24:45,303 INFO L290 TraceCheckUtils]: 161: Hoare triple {70919#false} assume !(0 != start_simulation_~tmp___0~1#1); {70919#false} is VALID [2022-02-21 04:24:45,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:45,304 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:45,304 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079598124] [2022-02-21 04:24:45,304 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079598124] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:45,305 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:45,305 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:45,305 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1424605910] [2022-02-21 04:24:45,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:45,305 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:45,306 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:45,306 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:45,306 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:45,306 INFO L87 Difference]: Start difference. First operand 1914 states and 2827 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:46,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:46,699 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2022-02-21 04:24:46,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:46,699 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:46,817 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:46,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:46,924 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:47,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-02-21 04:24:47,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:47,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:47,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:47,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:47,018 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-02-21 04:24:47,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:47,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:47,038 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:47,040 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2826 transitions. Second operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,042 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2826 transitions. Second operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,043 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. Second operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:47,133 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2022-02-21 04:24:47,133 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:47,135 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:47,135 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:47,137 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2826 transitions. [2022-02-21 04:24:47,138 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2826 transitions. [2022-02-21 04:24:47,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:47,212 INFO L93 Difference]: Finished difference Result 1914 states and 2826 transitions. [2022-02-21 04:24:47,212 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:47,214 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:47,214 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:47,214 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:47,214 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:47,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4764890282131662) internal successors, (2826), 1913 states have internal predecessors, (2826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:47,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2826 transitions. [2022-02-21 04:24:47,321 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-02-21 04:24:47,321 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2826 transitions. [2022-02-21 04:24:47,321 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:24:47,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2826 transitions. [2022-02-21 04:24:47,324 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:47,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:47,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:47,326 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:47,326 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:47,327 INFO L791 eck$LassoCheckResult]: Stem: 73696#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 73697#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 73516#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 73232#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73233#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 74409#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74410#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73368#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73369#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73823#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 73658#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 73659#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 73435#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 73436#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 73834#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 74011#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 74165#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 74202#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 73446#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73447#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 74622#L1258-2 assume !(0 == ~T1_E~0); 73741#L1263-1 assume !(0 == ~T2_E~0); 73742#L1268-1 assume !(0 == ~T3_E~0); 74045#L1273-1 assume !(0 == ~T4_E~0); 74604#L1278-1 assume !(0 == ~T5_E~0); 74465#L1283-1 assume !(0 == ~T6_E~0); 74466#L1288-1 assume !(0 == ~T7_E~0); 74702#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 74690#L1298-1 assume !(0 == ~T9_E~0); 74616#L1303-1 assume !(0 == ~T10_E~0); 73261#L1308-1 assume !(0 == ~T11_E~0); 73203#L1313-1 assume !(0 == ~T12_E~0); 73204#L1318-1 assume !(0 == ~T13_E~0); 73210#L1323-1 assume !(0 == ~E_1~0); 73211#L1328-1 assume !(0 == ~E_2~0); 73378#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 74337#L1338-1 assume !(0 == ~E_4~0); 74338#L1343-1 assume !(0 == ~E_5~0); 74439#L1348-1 assume !(0 == ~E_6~0); 74725#L1353-1 assume !(0 == ~E_7~0); 74064#L1358-1 assume !(0 == ~E_8~0); 74065#L1363-1 assume !(0 == ~E_9~0); 74355#L1368-1 assume !(0 == ~E_10~0); 73040#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 73041#L1378-1 assume !(0 == ~E_12~0); 73327#L1383-1 assume !(0 == ~E_13~0); 73328#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74071#L607 assume 1 == ~m_pc~0; 74072#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 73398#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74437#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73991#L1560 assume !(0 != activate_threads_~tmp~1#1); 73992#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73223#L626 assume !(1 == ~t1_pc~0); 73224#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 73492#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73493#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73662#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 73123#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73124#L645 assume 1 == ~t2_pc~0; 73240#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 73197#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73874#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73875#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 73967#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 73968#L664 assume 1 == ~t3_pc~0; 74724#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 72964#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72965#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73623#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 73624#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74632#L683 assume !(1 == ~t4_pc~0); 74187#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 74139#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74140#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74174#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74298#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73917#L702 assume 1 == ~t5_pc~0; 73918#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73843#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74293#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74591#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 74532#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73012#L721 assume !(1 == ~t6_pc~0); 72986#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 72987#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73150#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 73632#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 73633#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74234#L740 assume 1 == ~t7_pc~0; 73061#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 72874#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72875#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 72864#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 72865#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73568#L759 assume !(1 == ~t8_pc~0); 73569#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 73598#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74291#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74292#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 74423#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 74701#L778 assume 1 == ~t9_pc~0; 74588#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 73039#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 72979#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 72908#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 72909#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 73236#L797 assume !(1 == ~t10_pc~0); 73237#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 73355#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74489#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 73739#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 73740#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74029#L816 assume 1 == ~t11_pc~0; 72944#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 72945#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 73700#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 73639#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 73640#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 74164#L835 assume 1 == ~t12_pc~0; 74042#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 73108#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 73130#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 73271#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 73796#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 73797#L854 assume !(1 == ~t13_pc~0); 73437#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 73438#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 73488#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 73148#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 73149#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74528#L1401 assume !(1 == ~M_E~0); 73627#L1401-2 assume !(1 == ~T1_E~0); 73628#L1406-1 assume !(1 == ~T2_E~0); 74223#L1411-1 assume !(1 == ~T3_E~0); 74224#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73890#L1421-1 assume !(1 == ~T5_E~0); 73433#L1426-1 assume !(1 == ~T6_E~0); 73434#L1431-1 assume !(1 == ~T7_E~0); 72982#L1436-1 assume !(1 == ~T8_E~0); 72983#L1441-1 assume !(1 == ~T9_E~0); 73730#L1446-1 assume !(1 == ~T10_E~0); 73731#L1451-1 assume !(1 == ~T11_E~0); 74436#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 74090#L1461-1 assume !(1 == ~T13_E~0); 73651#L1466-1 assume !(1 == ~E_1~0); 73652#L1471-1 assume !(1 == ~E_2~0); 74421#L1476-1 assume !(1 == ~E_3~0); 74422#L1481-1 assume !(1 == ~E_4~0); 74570#L1486-1 assume !(1 == ~E_5~0); 73276#L1491-1 assume !(1 == ~E_6~0); 72916#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 72917#L1501-1 assume !(1 == ~E_8~0); 73728#L1506-1 assume !(1 == ~E_9~0); 73729#L1511-1 assume !(1 == ~E_10~0); 73685#L1516-1 assume !(1 == ~E_11~0); 72860#L1521-1 assume !(1 == ~E_12~0); 72861#L1526-1 assume !(1 == ~E_13~0); 72915#L1531-1 assume { :end_inline_reset_delta_events } true; 73458#L1892-2 [2022-02-21 04:24:47,327 INFO L793 eck$LassoCheckResult]: Loop: 73458#L1892-2 assume !false; 74481#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74679#L1233 assume !false; 74662#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 73994#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73974#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74132#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 72958#L1046 assume !(0 != eval_~tmp~0#1); 72960#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72994#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74166#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 74723#L1258-5 assume !(0 == ~T1_E~0); 73136#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 73137#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 74715#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 74721#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 74722#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 73360#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 73361#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 74478#L1298-3 assume !(0 == ~T9_E~0); 74479#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 74638#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 74477#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 73978#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 73138#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 73139#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 74562#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 73281#L1338-3 assume !(0 == ~E_4~0); 73282#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 74394#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 74567#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 74568#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 73934#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 73494#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 73495#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 74251#L1378-3 assume !(0 == ~E_12~0); 74252#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 74433#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74434#L607-42 assume !(1 == ~m_pc~0); 74048#L607-44 is_master_triggered_~__retres1~0#1 := 0; 73775#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73776#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73508#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 73509#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74030#L626-42 assume 1 == ~t1_pc~0; 73592#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 73593#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73897#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73898#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 73172#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73173#L645-42 assume !(1 == ~t2_pc~0); 74372#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 74373#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74538#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 73379#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 72886#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72887#L664-42 assume !(1 == ~t3_pc~0); 73413#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 73414#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74665#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74200#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74201#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74366#L683-42 assume 1 == ~t4_pc~0; 74731#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 74075#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74207#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74627#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74628#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74472#L702-42 assume !(1 == ~t5_pc~0); 73584#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 73585#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73881#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74554#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 72902#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72903#L721-42 assume !(1 == ~t6_pc~0); 73057#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 73076#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73540#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 74707#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 73712#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73558#L740-42 assume 1 == ~t7_pc~0; 73559#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 73296#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 73837#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 73692#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 73693#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73966#L759-42 assume 1 == ~t8_pc~0; 73815#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 73747#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 73748#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 73826#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 73827#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 73922#L778-42 assume !(1 == ~t9_pc~0); 73760#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 73761#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74171#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 74076#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 74077#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74134#L797-42 assume 1 == ~t10_pc~0; 73301#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 73302#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74303#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 74612#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 74172#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74173#L816-42 assume 1 == ~t11_pc~0; 72850#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 72851#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 73393#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 73394#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 73473#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 73474#L835-42 assume 1 == ~t12_pc~0; 73878#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 73771#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 73448#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 73449#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 74531#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 74315#L854-42 assume 1 == ~t13_pc~0; 74316#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 73392#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 73002#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 73003#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 73649#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73650#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 74428#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73239#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73103#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 73104#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73703#L1421-3 assume !(1 == ~T5_E~0); 73704#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 73279#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 73280#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 72866#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 72867#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 74456#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 73787#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 73440#L1461-3 assume !(1 == ~T13_E~0); 73441#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 74718#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 73380#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 73381#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 73781#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 73408#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 73409#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 73821#L1501-3 assume !(1 == ~E_8~0); 73822#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 74248#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 74238#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 74239#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 73938#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 73939#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74333#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73215#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74108#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 73749#L1911 assume !(0 == start_simulation_~tmp~3#1); 73750#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74272#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73339#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74210#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 73044#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 73045#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73274#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 73275#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 73458#L1892-2 [2022-02-21 04:24:47,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:47,328 INFO L85 PathProgramCache]: Analyzing trace with hash 1619928924, now seen corresponding path program 1 times [2022-02-21 04:24:47,328 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:47,329 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892566661] [2022-02-21 04:24:47,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:47,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:47,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:47,361 INFO L290 TraceCheckUtils]: 0: Hoare triple {78580#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {78580#true} is VALID [2022-02-21 04:24:47,361 INFO L290 TraceCheckUtils]: 1: Hoare triple {78580#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,362 INFO L290 TraceCheckUtils]: 2: Hoare triple {78582#(= ~t11_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,362 INFO L290 TraceCheckUtils]: 3: Hoare triple {78582#(= ~t11_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,362 INFO L290 TraceCheckUtils]: 4: Hoare triple {78582#(= ~t11_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,363 INFO L290 TraceCheckUtils]: 5: Hoare triple {78582#(= ~t11_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,363 INFO L290 TraceCheckUtils]: 6: Hoare triple {78582#(= ~t11_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,364 INFO L290 TraceCheckUtils]: 7: Hoare triple {78582#(= ~t11_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,364 INFO L290 TraceCheckUtils]: 8: Hoare triple {78582#(= ~t11_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,364 INFO L290 TraceCheckUtils]: 9: Hoare triple {78582#(= ~t11_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,365 INFO L290 TraceCheckUtils]: 10: Hoare triple {78582#(= ~t11_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,365 INFO L290 TraceCheckUtils]: 11: Hoare triple {78582#(= ~t11_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,365 INFO L290 TraceCheckUtils]: 12: Hoare triple {78582#(= ~t11_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,366 INFO L290 TraceCheckUtils]: 13: Hoare triple {78582#(= ~t11_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,366 INFO L290 TraceCheckUtils]: 14: Hoare triple {78582#(= ~t11_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {78582#(= ~t11_i~0 1)} is VALID [2022-02-21 04:24:47,366 INFO L290 TraceCheckUtils]: 15: Hoare triple {78582#(= ~t11_i~0 1)} assume !(1 == ~t11_i~0);~t11_st~0 := 2; {78581#false} is VALID [2022-02-21 04:24:47,366 INFO L290 TraceCheckUtils]: 16: Hoare triple {78581#false} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {78581#false} is VALID [2022-02-21 04:24:47,367 INFO L290 TraceCheckUtils]: 17: Hoare triple {78581#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {78581#false} is VALID [2022-02-21 04:24:47,367 INFO L290 TraceCheckUtils]: 18: Hoare triple {78581#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {78581#false} is VALID [2022-02-21 04:24:47,367 INFO L290 TraceCheckUtils]: 19: Hoare triple {78581#false} assume 0 == ~M_E~0;~M_E~0 := 1; {78581#false} is VALID [2022-02-21 04:24:47,367 INFO L290 TraceCheckUtils]: 20: Hoare triple {78581#false} assume !(0 == ~T1_E~0); {78581#false} is VALID [2022-02-21 04:24:47,367 INFO L290 TraceCheckUtils]: 21: Hoare triple {78581#false} assume !(0 == ~T2_E~0); {78581#false} is VALID [2022-02-21 04:24:47,367 INFO L290 TraceCheckUtils]: 22: Hoare triple {78581#false} assume !(0 == ~T3_E~0); {78581#false} is VALID [2022-02-21 04:24:47,367 INFO L290 TraceCheckUtils]: 23: Hoare triple {78581#false} assume !(0 == ~T4_E~0); {78581#false} is VALID [2022-02-21 04:24:47,368 INFO L290 TraceCheckUtils]: 24: Hoare triple {78581#false} assume !(0 == ~T5_E~0); {78581#false} is VALID [2022-02-21 04:24:47,368 INFO L290 TraceCheckUtils]: 25: Hoare triple {78581#false} assume !(0 == ~T6_E~0); {78581#false} is VALID [2022-02-21 04:24:47,368 INFO L290 TraceCheckUtils]: 26: Hoare triple {78581#false} assume !(0 == ~T7_E~0); {78581#false} is VALID [2022-02-21 04:24:47,368 INFO L290 TraceCheckUtils]: 27: Hoare triple {78581#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {78581#false} is VALID [2022-02-21 04:24:47,368 INFO L290 TraceCheckUtils]: 28: Hoare triple {78581#false} assume !(0 == ~T9_E~0); {78581#false} is VALID [2022-02-21 04:24:47,368 INFO L290 TraceCheckUtils]: 29: Hoare triple {78581#false} assume !(0 == ~T10_E~0); {78581#false} is VALID [2022-02-21 04:24:47,368 INFO L290 TraceCheckUtils]: 30: Hoare triple {78581#false} assume !(0 == ~T11_E~0); {78581#false} is VALID [2022-02-21 04:24:47,369 INFO L290 TraceCheckUtils]: 31: Hoare triple {78581#false} assume !(0 == ~T12_E~0); {78581#false} is VALID [2022-02-21 04:24:47,369 INFO L290 TraceCheckUtils]: 32: Hoare triple {78581#false} assume !(0 == ~T13_E~0); {78581#false} is VALID [2022-02-21 04:24:47,369 INFO L290 TraceCheckUtils]: 33: Hoare triple {78581#false} assume !(0 == ~E_1~0); {78581#false} is VALID [2022-02-21 04:24:47,369 INFO L290 TraceCheckUtils]: 34: Hoare triple {78581#false} assume !(0 == ~E_2~0); {78581#false} is VALID [2022-02-21 04:24:47,369 INFO L290 TraceCheckUtils]: 35: Hoare triple {78581#false} assume 0 == ~E_3~0;~E_3~0 := 1; {78581#false} is VALID [2022-02-21 04:24:47,369 INFO L290 TraceCheckUtils]: 36: Hoare triple {78581#false} assume !(0 == ~E_4~0); {78581#false} is VALID [2022-02-21 04:24:47,369 INFO L290 TraceCheckUtils]: 37: Hoare triple {78581#false} assume !(0 == ~E_5~0); {78581#false} is VALID [2022-02-21 04:24:47,370 INFO L290 TraceCheckUtils]: 38: Hoare triple {78581#false} assume !(0 == ~E_6~0); {78581#false} is VALID [2022-02-21 04:24:47,370 INFO L290 TraceCheckUtils]: 39: Hoare triple {78581#false} assume !(0 == ~E_7~0); {78581#false} is VALID [2022-02-21 04:24:47,370 INFO L290 TraceCheckUtils]: 40: Hoare triple {78581#false} assume !(0 == ~E_8~0); {78581#false} is VALID [2022-02-21 04:24:47,370 INFO L290 TraceCheckUtils]: 41: Hoare triple {78581#false} assume !(0 == ~E_9~0); {78581#false} is VALID [2022-02-21 04:24:47,370 INFO L290 TraceCheckUtils]: 42: Hoare triple {78581#false} assume !(0 == ~E_10~0); {78581#false} is VALID [2022-02-21 04:24:47,370 INFO L290 TraceCheckUtils]: 43: Hoare triple {78581#false} assume 0 == ~E_11~0;~E_11~0 := 1; {78581#false} is VALID [2022-02-21 04:24:47,370 INFO L290 TraceCheckUtils]: 44: Hoare triple {78581#false} assume !(0 == ~E_12~0); {78581#false} is VALID [2022-02-21 04:24:47,371 INFO L290 TraceCheckUtils]: 45: Hoare triple {78581#false} assume !(0 == ~E_13~0); {78581#false} is VALID [2022-02-21 04:24:47,371 INFO L290 TraceCheckUtils]: 46: Hoare triple {78581#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {78581#false} is VALID [2022-02-21 04:24:47,371 INFO L290 TraceCheckUtils]: 47: Hoare triple {78581#false} assume 1 == ~m_pc~0; {78581#false} is VALID [2022-02-21 04:24:47,371 INFO L290 TraceCheckUtils]: 48: Hoare triple {78581#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {78581#false} is VALID [2022-02-21 04:24:47,371 INFO L290 TraceCheckUtils]: 49: Hoare triple {78581#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {78581#false} is VALID [2022-02-21 04:24:47,371 INFO L290 TraceCheckUtils]: 50: Hoare triple {78581#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {78581#false} is VALID [2022-02-21 04:24:47,371 INFO L290 TraceCheckUtils]: 51: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp~1#1); {78581#false} is VALID [2022-02-21 04:24:47,372 INFO L290 TraceCheckUtils]: 52: Hoare triple {78581#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {78581#false} is VALID [2022-02-21 04:24:47,372 INFO L290 TraceCheckUtils]: 53: Hoare triple {78581#false} assume !(1 == ~t1_pc~0); {78581#false} is VALID [2022-02-21 04:24:47,372 INFO L290 TraceCheckUtils]: 54: Hoare triple {78581#false} is_transmit1_triggered_~__retres1~1#1 := 0; {78581#false} is VALID [2022-02-21 04:24:47,372 INFO L290 TraceCheckUtils]: 55: Hoare triple {78581#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {78581#false} is VALID [2022-02-21 04:24:47,372 INFO L290 TraceCheckUtils]: 56: Hoare triple {78581#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {78581#false} is VALID [2022-02-21 04:24:47,372 INFO L290 TraceCheckUtils]: 57: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp___0~0#1); {78581#false} is VALID [2022-02-21 04:24:47,372 INFO L290 TraceCheckUtils]: 58: Hoare triple {78581#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {78581#false} is VALID [2022-02-21 04:24:47,373 INFO L290 TraceCheckUtils]: 59: Hoare triple {78581#false} assume 1 == ~t2_pc~0; {78581#false} is VALID [2022-02-21 04:24:47,373 INFO L290 TraceCheckUtils]: 60: Hoare triple {78581#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {78581#false} is VALID [2022-02-21 04:24:47,373 INFO L290 TraceCheckUtils]: 61: Hoare triple {78581#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {78581#false} is VALID [2022-02-21 04:24:47,373 INFO L290 TraceCheckUtils]: 62: Hoare triple {78581#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {78581#false} is VALID [2022-02-21 04:24:47,373 INFO L290 TraceCheckUtils]: 63: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp___1~0#1); {78581#false} is VALID [2022-02-21 04:24:47,373 INFO L290 TraceCheckUtils]: 64: Hoare triple {78581#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {78581#false} is VALID [2022-02-21 04:24:47,373 INFO L290 TraceCheckUtils]: 65: Hoare triple {78581#false} assume 1 == ~t3_pc~0; {78581#false} is VALID [2022-02-21 04:24:47,374 INFO L290 TraceCheckUtils]: 66: Hoare triple {78581#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {78581#false} is VALID [2022-02-21 04:24:47,374 INFO L290 TraceCheckUtils]: 67: Hoare triple {78581#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {78581#false} is VALID [2022-02-21 04:24:47,374 INFO L290 TraceCheckUtils]: 68: Hoare triple {78581#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {78581#false} is VALID [2022-02-21 04:24:47,374 INFO L290 TraceCheckUtils]: 69: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp___2~0#1); {78581#false} is VALID [2022-02-21 04:24:47,374 INFO L290 TraceCheckUtils]: 70: Hoare triple {78581#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {78581#false} is VALID [2022-02-21 04:24:47,374 INFO L290 TraceCheckUtils]: 71: Hoare triple {78581#false} assume !(1 == ~t4_pc~0); {78581#false} is VALID [2022-02-21 04:24:47,374 INFO L290 TraceCheckUtils]: 72: Hoare triple {78581#false} is_transmit4_triggered_~__retres1~4#1 := 0; {78581#false} is VALID [2022-02-21 04:24:47,375 INFO L290 TraceCheckUtils]: 73: Hoare triple {78581#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {78581#false} is VALID [2022-02-21 04:24:47,375 INFO L290 TraceCheckUtils]: 74: Hoare triple {78581#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {78581#false} is VALID [2022-02-21 04:24:47,375 INFO L290 TraceCheckUtils]: 75: Hoare triple {78581#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {78581#false} is VALID [2022-02-21 04:24:47,375 INFO L290 TraceCheckUtils]: 76: Hoare triple {78581#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {78581#false} is VALID [2022-02-21 04:24:47,375 INFO L290 TraceCheckUtils]: 77: Hoare triple {78581#false} assume 1 == ~t5_pc~0; {78581#false} is VALID [2022-02-21 04:24:47,375 INFO L290 TraceCheckUtils]: 78: Hoare triple {78581#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {78581#false} is VALID [2022-02-21 04:24:47,375 INFO L290 TraceCheckUtils]: 79: Hoare triple {78581#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {78581#false} is VALID [2022-02-21 04:24:47,376 INFO L290 TraceCheckUtils]: 80: Hoare triple {78581#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {78581#false} is VALID [2022-02-21 04:24:47,376 INFO L290 TraceCheckUtils]: 81: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp___4~0#1); {78581#false} is VALID [2022-02-21 04:24:47,376 INFO L290 TraceCheckUtils]: 82: Hoare triple {78581#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {78581#false} is VALID [2022-02-21 04:24:47,376 INFO L290 TraceCheckUtils]: 83: Hoare triple {78581#false} assume !(1 == ~t6_pc~0); {78581#false} is VALID [2022-02-21 04:24:47,376 INFO L290 TraceCheckUtils]: 84: Hoare triple {78581#false} is_transmit6_triggered_~__retres1~6#1 := 0; {78581#false} is VALID [2022-02-21 04:24:47,376 INFO L290 TraceCheckUtils]: 85: Hoare triple {78581#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {78581#false} is VALID [2022-02-21 04:24:47,376 INFO L290 TraceCheckUtils]: 86: Hoare triple {78581#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {78581#false} is VALID [2022-02-21 04:24:47,377 INFO L290 TraceCheckUtils]: 87: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp___5~0#1); {78581#false} is VALID [2022-02-21 04:24:47,377 INFO L290 TraceCheckUtils]: 88: Hoare triple {78581#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {78581#false} is VALID [2022-02-21 04:24:47,377 INFO L290 TraceCheckUtils]: 89: Hoare triple {78581#false} assume 1 == ~t7_pc~0; {78581#false} is VALID [2022-02-21 04:24:47,377 INFO L290 TraceCheckUtils]: 90: Hoare triple {78581#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {78581#false} is VALID [2022-02-21 04:24:47,377 INFO L290 TraceCheckUtils]: 91: Hoare triple {78581#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {78581#false} is VALID [2022-02-21 04:24:47,377 INFO L290 TraceCheckUtils]: 92: Hoare triple {78581#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {78581#false} is VALID [2022-02-21 04:24:47,377 INFO L290 TraceCheckUtils]: 93: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp___6~0#1); {78581#false} is VALID [2022-02-21 04:24:47,378 INFO L290 TraceCheckUtils]: 94: Hoare triple {78581#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {78581#false} is VALID [2022-02-21 04:24:47,378 INFO L290 TraceCheckUtils]: 95: Hoare triple {78581#false} assume !(1 == ~t8_pc~0); {78581#false} is VALID [2022-02-21 04:24:47,378 INFO L290 TraceCheckUtils]: 96: Hoare triple {78581#false} is_transmit8_triggered_~__retres1~8#1 := 0; {78581#false} is VALID [2022-02-21 04:24:47,378 INFO L290 TraceCheckUtils]: 97: Hoare triple {78581#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {78581#false} is VALID [2022-02-21 04:24:47,378 INFO L290 TraceCheckUtils]: 98: Hoare triple {78581#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {78581#false} is VALID [2022-02-21 04:24:47,378 INFO L290 TraceCheckUtils]: 99: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp___7~0#1); {78581#false} is VALID [2022-02-21 04:24:47,378 INFO L290 TraceCheckUtils]: 100: Hoare triple {78581#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {78581#false} is VALID [2022-02-21 04:24:47,378 INFO L290 TraceCheckUtils]: 101: Hoare triple {78581#false} assume 1 == ~t9_pc~0; {78581#false} is VALID [2022-02-21 04:24:47,379 INFO L290 TraceCheckUtils]: 102: Hoare triple {78581#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {78581#false} is VALID [2022-02-21 04:24:47,379 INFO L290 TraceCheckUtils]: 103: Hoare triple {78581#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {78581#false} is VALID [2022-02-21 04:24:47,379 INFO L290 TraceCheckUtils]: 104: Hoare triple {78581#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {78581#false} is VALID [2022-02-21 04:24:47,379 INFO L290 TraceCheckUtils]: 105: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp___8~0#1); {78581#false} is VALID [2022-02-21 04:24:47,379 INFO L290 TraceCheckUtils]: 106: Hoare triple {78581#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {78581#false} is VALID [2022-02-21 04:24:47,379 INFO L290 TraceCheckUtils]: 107: Hoare triple {78581#false} assume !(1 == ~t10_pc~0); {78581#false} is VALID [2022-02-21 04:24:47,379 INFO L290 TraceCheckUtils]: 108: Hoare triple {78581#false} is_transmit10_triggered_~__retres1~10#1 := 0; {78581#false} is VALID [2022-02-21 04:24:47,380 INFO L290 TraceCheckUtils]: 109: Hoare triple {78581#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {78581#false} is VALID [2022-02-21 04:24:47,380 INFO L290 TraceCheckUtils]: 110: Hoare triple {78581#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {78581#false} is VALID [2022-02-21 04:24:47,380 INFO L290 TraceCheckUtils]: 111: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp___9~0#1); {78581#false} is VALID [2022-02-21 04:24:47,380 INFO L290 TraceCheckUtils]: 112: Hoare triple {78581#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {78581#false} is VALID [2022-02-21 04:24:47,380 INFO L290 TraceCheckUtils]: 113: Hoare triple {78581#false} assume 1 == ~t11_pc~0; {78581#false} is VALID [2022-02-21 04:24:47,380 INFO L290 TraceCheckUtils]: 114: Hoare triple {78581#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {78581#false} is VALID [2022-02-21 04:24:47,380 INFO L290 TraceCheckUtils]: 115: Hoare triple {78581#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {78581#false} is VALID [2022-02-21 04:24:47,381 INFO L290 TraceCheckUtils]: 116: Hoare triple {78581#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {78581#false} is VALID [2022-02-21 04:24:47,381 INFO L290 TraceCheckUtils]: 117: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp___10~0#1); {78581#false} is VALID [2022-02-21 04:24:47,381 INFO L290 TraceCheckUtils]: 118: Hoare triple {78581#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {78581#false} is VALID [2022-02-21 04:24:47,381 INFO L290 TraceCheckUtils]: 119: Hoare triple {78581#false} assume 1 == ~t12_pc~0; {78581#false} is VALID [2022-02-21 04:24:47,381 INFO L290 TraceCheckUtils]: 120: Hoare triple {78581#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {78581#false} is VALID [2022-02-21 04:24:47,381 INFO L290 TraceCheckUtils]: 121: Hoare triple {78581#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {78581#false} is VALID [2022-02-21 04:24:47,381 INFO L290 TraceCheckUtils]: 122: Hoare triple {78581#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {78581#false} is VALID [2022-02-21 04:24:47,382 INFO L290 TraceCheckUtils]: 123: Hoare triple {78581#false} assume !(0 != activate_threads_~tmp___11~0#1); {78581#false} is VALID [2022-02-21 04:24:47,382 INFO L290 TraceCheckUtils]: 124: Hoare triple {78581#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {78581#false} is VALID [2022-02-21 04:24:47,382 INFO L290 TraceCheckUtils]: 125: Hoare triple {78581#false} assume !(1 == ~t13_pc~0); {78581#false} is VALID [2022-02-21 04:24:47,382 INFO L290 TraceCheckUtils]: 126: Hoare triple {78581#false} is_transmit13_triggered_~__retres1~13#1 := 0; {78581#false} is VALID [2022-02-21 04:24:47,382 INFO L290 TraceCheckUtils]: 127: Hoare triple {78581#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {78581#false} is VALID [2022-02-21 04:24:47,382 INFO L290 TraceCheckUtils]: 128: Hoare triple {78581#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {78581#false} is VALID [2022-02-21 04:24:47,382 INFO L290 TraceCheckUtils]: 129: Hoare triple {78581#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {78581#false} is VALID [2022-02-21 04:24:47,383 INFO L290 TraceCheckUtils]: 130: Hoare triple {78581#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {78581#false} is VALID [2022-02-21 04:24:47,383 INFO L290 TraceCheckUtils]: 131: Hoare triple {78581#false} assume !(1 == ~M_E~0); {78581#false} is VALID [2022-02-21 04:24:47,383 INFO L290 TraceCheckUtils]: 132: Hoare triple {78581#false} assume !(1 == ~T1_E~0); {78581#false} is VALID [2022-02-21 04:24:47,383 INFO L290 TraceCheckUtils]: 133: Hoare triple {78581#false} assume !(1 == ~T2_E~0); {78581#false} is VALID [2022-02-21 04:24:47,383 INFO L290 TraceCheckUtils]: 134: Hoare triple {78581#false} assume !(1 == ~T3_E~0); {78581#false} is VALID [2022-02-21 04:24:47,383 INFO L290 TraceCheckUtils]: 135: Hoare triple {78581#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {78581#false} is VALID [2022-02-21 04:24:47,383 INFO L290 TraceCheckUtils]: 136: Hoare triple {78581#false} assume !(1 == ~T5_E~0); {78581#false} is VALID [2022-02-21 04:24:47,383 INFO L290 TraceCheckUtils]: 137: Hoare triple {78581#false} assume !(1 == ~T6_E~0); {78581#false} is VALID [2022-02-21 04:24:47,384 INFO L290 TraceCheckUtils]: 138: Hoare triple {78581#false} assume !(1 == ~T7_E~0); {78581#false} is VALID [2022-02-21 04:24:47,384 INFO L290 TraceCheckUtils]: 139: Hoare triple {78581#false} assume !(1 == ~T8_E~0); {78581#false} is VALID [2022-02-21 04:24:47,384 INFO L290 TraceCheckUtils]: 140: Hoare triple {78581#false} assume !(1 == ~T9_E~0); {78581#false} is VALID [2022-02-21 04:24:47,384 INFO L290 TraceCheckUtils]: 141: Hoare triple {78581#false} assume !(1 == ~T10_E~0); {78581#false} is VALID [2022-02-21 04:24:47,384 INFO L290 TraceCheckUtils]: 142: Hoare triple {78581#false} assume !(1 == ~T11_E~0); {78581#false} is VALID [2022-02-21 04:24:47,384 INFO L290 TraceCheckUtils]: 143: Hoare triple {78581#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {78581#false} is VALID [2022-02-21 04:24:47,384 INFO L290 TraceCheckUtils]: 144: Hoare triple {78581#false} assume !(1 == ~T13_E~0); {78581#false} is VALID [2022-02-21 04:24:47,385 INFO L290 TraceCheckUtils]: 145: Hoare triple {78581#false} assume !(1 == ~E_1~0); {78581#false} is VALID [2022-02-21 04:24:47,385 INFO L290 TraceCheckUtils]: 146: Hoare triple {78581#false} assume !(1 == ~E_2~0); {78581#false} is VALID [2022-02-21 04:24:47,385 INFO L290 TraceCheckUtils]: 147: Hoare triple {78581#false} assume !(1 == ~E_3~0); {78581#false} is VALID [2022-02-21 04:24:47,385 INFO L290 TraceCheckUtils]: 148: Hoare triple {78581#false} assume !(1 == ~E_4~0); {78581#false} is VALID [2022-02-21 04:24:47,385 INFO L290 TraceCheckUtils]: 149: Hoare triple {78581#false} assume !(1 == ~E_5~0); {78581#false} is VALID [2022-02-21 04:24:47,385 INFO L290 TraceCheckUtils]: 150: Hoare triple {78581#false} assume !(1 == ~E_6~0); {78581#false} is VALID [2022-02-21 04:24:47,385 INFO L290 TraceCheckUtils]: 151: Hoare triple {78581#false} assume 1 == ~E_7~0;~E_7~0 := 2; {78581#false} is VALID [2022-02-21 04:24:47,386 INFO L290 TraceCheckUtils]: 152: Hoare triple {78581#false} assume !(1 == ~E_8~0); {78581#false} is VALID [2022-02-21 04:24:47,386 INFO L290 TraceCheckUtils]: 153: Hoare triple {78581#false} assume !(1 == ~E_9~0); {78581#false} is VALID [2022-02-21 04:24:47,386 INFO L290 TraceCheckUtils]: 154: Hoare triple {78581#false} assume !(1 == ~E_10~0); {78581#false} is VALID [2022-02-21 04:24:47,386 INFO L290 TraceCheckUtils]: 155: Hoare triple {78581#false} assume !(1 == ~E_11~0); {78581#false} is VALID [2022-02-21 04:24:47,386 INFO L290 TraceCheckUtils]: 156: Hoare triple {78581#false} assume !(1 == ~E_12~0); {78581#false} is VALID [2022-02-21 04:24:47,386 INFO L290 TraceCheckUtils]: 157: Hoare triple {78581#false} assume !(1 == ~E_13~0); {78581#false} is VALID [2022-02-21 04:24:47,386 INFO L290 TraceCheckUtils]: 158: Hoare triple {78581#false} assume { :end_inline_reset_delta_events } true; {78581#false} is VALID [2022-02-21 04:24:47,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:47,387 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:47,387 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892566661] [2022-02-21 04:24:47,387 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1892566661] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:47,388 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:47,388 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:47,388 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1664401221] [2022-02-21 04:24:47,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:47,388 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:47,389 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:47,389 INFO L85 PathProgramCache]: Analyzing trace with hash -411351939, now seen corresponding path program 1 times [2022-02-21 04:24:47,389 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:47,389 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077820171] [2022-02-21 04:24:47,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:47,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:47,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:47,426 INFO L290 TraceCheckUtils]: 0: Hoare triple {78583#true} assume !false; {78583#true} is VALID [2022-02-21 04:24:47,426 INFO L290 TraceCheckUtils]: 1: Hoare triple {78583#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {78583#true} is VALID [2022-02-21 04:24:47,426 INFO L290 TraceCheckUtils]: 2: Hoare triple {78583#true} assume !false; {78583#true} is VALID [2022-02-21 04:24:47,426 INFO L290 TraceCheckUtils]: 3: Hoare triple {78583#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {78583#true} is VALID [2022-02-21 04:24:47,427 INFO L290 TraceCheckUtils]: 4: Hoare triple {78583#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {78583#true} is VALID [2022-02-21 04:24:47,427 INFO L290 TraceCheckUtils]: 5: Hoare triple {78583#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {78583#true} is VALID [2022-02-21 04:24:47,427 INFO L290 TraceCheckUtils]: 6: Hoare triple {78583#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {78583#true} is VALID [2022-02-21 04:24:47,427 INFO L290 TraceCheckUtils]: 7: Hoare triple {78583#true} assume !(0 != eval_~tmp~0#1); {78583#true} is VALID [2022-02-21 04:24:47,427 INFO L290 TraceCheckUtils]: 8: Hoare triple {78583#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {78583#true} is VALID [2022-02-21 04:24:47,427 INFO L290 TraceCheckUtils]: 9: Hoare triple {78583#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {78583#true} is VALID [2022-02-21 04:24:47,427 INFO L290 TraceCheckUtils]: 10: Hoare triple {78583#true} assume 0 == ~M_E~0;~M_E~0 := 1; {78583#true} is VALID [2022-02-21 04:24:47,428 INFO L290 TraceCheckUtils]: 11: Hoare triple {78583#true} assume !(0 == ~T1_E~0); {78583#true} is VALID [2022-02-21 04:24:47,428 INFO L290 TraceCheckUtils]: 12: Hoare triple {78583#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {78583#true} is VALID [2022-02-21 04:24:47,428 INFO L290 TraceCheckUtils]: 13: Hoare triple {78583#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {78583#true} is VALID [2022-02-21 04:24:47,428 INFO L290 TraceCheckUtils]: 14: Hoare triple {78583#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {78583#true} is VALID [2022-02-21 04:24:47,428 INFO L290 TraceCheckUtils]: 15: Hoare triple {78583#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,429 INFO L290 TraceCheckUtils]: 16: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,429 INFO L290 TraceCheckUtils]: 17: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,430 INFO L290 TraceCheckUtils]: 18: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,430 INFO L290 TraceCheckUtils]: 19: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,430 INFO L290 TraceCheckUtils]: 20: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,431 INFO L290 TraceCheckUtils]: 21: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,431 INFO L290 TraceCheckUtils]: 22: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,431 INFO L290 TraceCheckUtils]: 23: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,432 INFO L290 TraceCheckUtils]: 24: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,432 INFO L290 TraceCheckUtils]: 25: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,433 INFO L290 TraceCheckUtils]: 26: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,433 INFO L290 TraceCheckUtils]: 27: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,433 INFO L290 TraceCheckUtils]: 28: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,434 INFO L290 TraceCheckUtils]: 29: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,434 INFO L290 TraceCheckUtils]: 30: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,435 INFO L290 TraceCheckUtils]: 31: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,435 INFO L290 TraceCheckUtils]: 32: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,435 INFO L290 TraceCheckUtils]: 33: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,436 INFO L290 TraceCheckUtils]: 34: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,436 INFO L290 TraceCheckUtils]: 35: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,437 INFO L290 TraceCheckUtils]: 36: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,437 INFO L290 TraceCheckUtils]: 37: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,437 INFO L290 TraceCheckUtils]: 38: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,438 INFO L290 TraceCheckUtils]: 39: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,438 INFO L290 TraceCheckUtils]: 40: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,439 INFO L290 TraceCheckUtils]: 41: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,439 INFO L290 TraceCheckUtils]: 42: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,439 INFO L290 TraceCheckUtils]: 43: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,440 INFO L290 TraceCheckUtils]: 44: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,440 INFO L290 TraceCheckUtils]: 45: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,440 INFO L290 TraceCheckUtils]: 46: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,441 INFO L290 TraceCheckUtils]: 47: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,441 INFO L290 TraceCheckUtils]: 48: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,442 INFO L290 TraceCheckUtils]: 49: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,442 INFO L290 TraceCheckUtils]: 50: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,442 INFO L290 TraceCheckUtils]: 51: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,443 INFO L290 TraceCheckUtils]: 52: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,443 INFO L290 TraceCheckUtils]: 53: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,443 INFO L290 TraceCheckUtils]: 54: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,444 INFO L290 TraceCheckUtils]: 55: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,444 INFO L290 TraceCheckUtils]: 56: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,445 INFO L290 TraceCheckUtils]: 57: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,445 INFO L290 TraceCheckUtils]: 58: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,445 INFO L290 TraceCheckUtils]: 59: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,446 INFO L290 TraceCheckUtils]: 60: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,446 INFO L290 TraceCheckUtils]: 61: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,447 INFO L290 TraceCheckUtils]: 62: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,447 INFO L290 TraceCheckUtils]: 63: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,447 INFO L290 TraceCheckUtils]: 64: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,448 INFO L290 TraceCheckUtils]: 65: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,448 INFO L290 TraceCheckUtils]: 66: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,448 INFO L290 TraceCheckUtils]: 67: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,449 INFO L290 TraceCheckUtils]: 68: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,449 INFO L290 TraceCheckUtils]: 69: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,450 INFO L290 TraceCheckUtils]: 70: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,450 INFO L290 TraceCheckUtils]: 71: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,450 INFO L290 TraceCheckUtils]: 72: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,451 INFO L290 TraceCheckUtils]: 73: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,451 INFO L290 TraceCheckUtils]: 74: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,452 INFO L290 TraceCheckUtils]: 75: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,452 INFO L290 TraceCheckUtils]: 76: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,452 INFO L290 TraceCheckUtils]: 77: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,453 INFO L290 TraceCheckUtils]: 78: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,453 INFO L290 TraceCheckUtils]: 79: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,453 INFO L290 TraceCheckUtils]: 80: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,454 INFO L290 TraceCheckUtils]: 81: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,454 INFO L290 TraceCheckUtils]: 82: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,455 INFO L290 TraceCheckUtils]: 83: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,455 INFO L290 TraceCheckUtils]: 84: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,455 INFO L290 TraceCheckUtils]: 85: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,456 INFO L290 TraceCheckUtils]: 86: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,456 INFO L290 TraceCheckUtils]: 87: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,456 INFO L290 TraceCheckUtils]: 88: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,457 INFO L290 TraceCheckUtils]: 89: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,457 INFO L290 TraceCheckUtils]: 90: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,458 INFO L290 TraceCheckUtils]: 91: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,458 INFO L290 TraceCheckUtils]: 92: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,458 INFO L290 TraceCheckUtils]: 93: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,459 INFO L290 TraceCheckUtils]: 94: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,459 INFO L290 TraceCheckUtils]: 95: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,459 INFO L290 TraceCheckUtils]: 96: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,460 INFO L290 TraceCheckUtils]: 97: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,460 INFO L290 TraceCheckUtils]: 98: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,461 INFO L290 TraceCheckUtils]: 99: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,461 INFO L290 TraceCheckUtils]: 100: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,461 INFO L290 TraceCheckUtils]: 101: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,462 INFO L290 TraceCheckUtils]: 102: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,462 INFO L290 TraceCheckUtils]: 103: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,463 INFO L290 TraceCheckUtils]: 104: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,463 INFO L290 TraceCheckUtils]: 105: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,463 INFO L290 TraceCheckUtils]: 106: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,464 INFO L290 TraceCheckUtils]: 107: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,464 INFO L290 TraceCheckUtils]: 108: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,464 INFO L290 TraceCheckUtils]: 109: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,465 INFO L290 TraceCheckUtils]: 110: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,465 INFO L290 TraceCheckUtils]: 111: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,466 INFO L290 TraceCheckUtils]: 112: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,466 INFO L290 TraceCheckUtils]: 113: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,466 INFO L290 TraceCheckUtils]: 114: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,467 INFO L290 TraceCheckUtils]: 115: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,467 INFO L290 TraceCheckUtils]: 116: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,468 INFO L290 TraceCheckUtils]: 117: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,468 INFO L290 TraceCheckUtils]: 118: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,469 INFO L290 TraceCheckUtils]: 119: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,469 INFO L290 TraceCheckUtils]: 120: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,469 INFO L290 TraceCheckUtils]: 121: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,470 INFO L290 TraceCheckUtils]: 122: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,470 INFO L290 TraceCheckUtils]: 123: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,471 INFO L290 TraceCheckUtils]: 124: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,471 INFO L290 TraceCheckUtils]: 125: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,471 INFO L290 TraceCheckUtils]: 126: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {78585#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:47,472 INFO L290 TraceCheckUtils]: 127: Hoare triple {78585#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {78584#false} is VALID [2022-02-21 04:24:47,472 INFO L290 TraceCheckUtils]: 128: Hoare triple {78584#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,472 INFO L290 TraceCheckUtils]: 129: Hoare triple {78584#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,472 INFO L290 TraceCheckUtils]: 130: Hoare triple {78584#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,472 INFO L290 TraceCheckUtils]: 131: Hoare triple {78584#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,472 INFO L290 TraceCheckUtils]: 132: Hoare triple {78584#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,473 INFO L290 TraceCheckUtils]: 133: Hoare triple {78584#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,473 INFO L290 TraceCheckUtils]: 134: Hoare triple {78584#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,473 INFO L290 TraceCheckUtils]: 135: Hoare triple {78584#false} assume !(1 == ~T13_E~0); {78584#false} is VALID [2022-02-21 04:24:47,473 INFO L290 TraceCheckUtils]: 136: Hoare triple {78584#false} assume 1 == ~E_1~0;~E_1~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,473 INFO L290 TraceCheckUtils]: 137: Hoare triple {78584#false} assume 1 == ~E_2~0;~E_2~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,473 INFO L290 TraceCheckUtils]: 138: Hoare triple {78584#false} assume 1 == ~E_3~0;~E_3~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,473 INFO L290 TraceCheckUtils]: 139: Hoare triple {78584#false} assume 1 == ~E_4~0;~E_4~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,474 INFO L290 TraceCheckUtils]: 140: Hoare triple {78584#false} assume 1 == ~E_5~0;~E_5~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,474 INFO L290 TraceCheckUtils]: 141: Hoare triple {78584#false} assume 1 == ~E_6~0;~E_6~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,474 INFO L290 TraceCheckUtils]: 142: Hoare triple {78584#false} assume 1 == ~E_7~0;~E_7~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,474 INFO L290 TraceCheckUtils]: 143: Hoare triple {78584#false} assume !(1 == ~E_8~0); {78584#false} is VALID [2022-02-21 04:24:47,474 INFO L290 TraceCheckUtils]: 144: Hoare triple {78584#false} assume 1 == ~E_9~0;~E_9~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,474 INFO L290 TraceCheckUtils]: 145: Hoare triple {78584#false} assume 1 == ~E_10~0;~E_10~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,474 INFO L290 TraceCheckUtils]: 146: Hoare triple {78584#false} assume 1 == ~E_11~0;~E_11~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,475 INFO L290 TraceCheckUtils]: 147: Hoare triple {78584#false} assume 1 == ~E_12~0;~E_12~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,475 INFO L290 TraceCheckUtils]: 148: Hoare triple {78584#false} assume 1 == ~E_13~0;~E_13~0 := 2; {78584#false} is VALID [2022-02-21 04:24:47,475 INFO L290 TraceCheckUtils]: 149: Hoare triple {78584#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {78584#false} is VALID [2022-02-21 04:24:47,475 INFO L290 TraceCheckUtils]: 150: Hoare triple {78584#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {78584#false} is VALID [2022-02-21 04:24:47,475 INFO L290 TraceCheckUtils]: 151: Hoare triple {78584#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {78584#false} is VALID [2022-02-21 04:24:47,475 INFO L290 TraceCheckUtils]: 152: Hoare triple {78584#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {78584#false} is VALID [2022-02-21 04:24:47,475 INFO L290 TraceCheckUtils]: 153: Hoare triple {78584#false} assume !(0 == start_simulation_~tmp~3#1); {78584#false} is VALID [2022-02-21 04:24:47,476 INFO L290 TraceCheckUtils]: 154: Hoare triple {78584#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {78584#false} is VALID [2022-02-21 04:24:47,476 INFO L290 TraceCheckUtils]: 155: Hoare triple {78584#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {78584#false} is VALID [2022-02-21 04:24:47,476 INFO L290 TraceCheckUtils]: 156: Hoare triple {78584#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {78584#false} is VALID [2022-02-21 04:24:47,476 INFO L290 TraceCheckUtils]: 157: Hoare triple {78584#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {78584#false} is VALID [2022-02-21 04:24:47,476 INFO L290 TraceCheckUtils]: 158: Hoare triple {78584#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {78584#false} is VALID [2022-02-21 04:24:47,476 INFO L290 TraceCheckUtils]: 159: Hoare triple {78584#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {78584#false} is VALID [2022-02-21 04:24:47,476 INFO L290 TraceCheckUtils]: 160: Hoare triple {78584#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {78584#false} is VALID [2022-02-21 04:24:47,477 INFO L290 TraceCheckUtils]: 161: Hoare triple {78584#false} assume !(0 != start_simulation_~tmp___0~1#1); {78584#false} is VALID [2022-02-21 04:24:47,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:47,477 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:47,477 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2077820171] [2022-02-21 04:24:47,478 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2077820171] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:47,478 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:47,478 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:47,478 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848934645] [2022-02-21 04:24:47,478 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:47,479 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:47,479 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:47,479 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:47,479 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:47,479 INFO L87 Difference]: Start difference. First operand 1914 states and 2826 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:48,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:48,839 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2022-02-21 04:24:48,839 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:48,839 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:48,963 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:48,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:49,046 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:49,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-02-21 04:24:49,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:49,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:49,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:49,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:49,131 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-02-21 04:24:49,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:49,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:49,148 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:49,150 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2825 transitions. Second operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,152 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2825 transitions. Second operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,153 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. Second operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:49,257 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2022-02-21 04:24:49,257 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:49,258 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:49,258 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:49,260 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2825 transitions. [2022-02-21 04:24:49,261 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2825 transitions. [2022-02-21 04:24:49,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:49,336 INFO L93 Difference]: Finished difference Result 1914 states and 2825 transitions. [2022-02-21 04:24:49,336 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:49,337 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:49,337 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:49,337 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:49,337 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:49,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4759665621734588) internal successors, (2825), 1913 states have internal predecessors, (2825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:49,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2825 transitions. [2022-02-21 04:24:49,413 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-02-21 04:24:49,413 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2825 transitions. [2022-02-21 04:24:49,413 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:24:49,413 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2825 transitions. [2022-02-21 04:24:49,416 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:49,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:49,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:49,417 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:49,417 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:49,417 INFO L791 eck$LassoCheckResult]: Stem: 81361#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 81362#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 81181#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 80897#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 80898#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 82074#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82075#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81033#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81034#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81488#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81323#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 81324#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 81100#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 81101#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 81499#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 81676#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 81830#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 81867#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 81111#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81112#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 82287#L1258-2 assume !(0 == ~T1_E~0); 81406#L1263-1 assume !(0 == ~T2_E~0); 81407#L1268-1 assume !(0 == ~T3_E~0); 81710#L1273-1 assume !(0 == ~T4_E~0); 82269#L1278-1 assume !(0 == ~T5_E~0); 82130#L1283-1 assume !(0 == ~T6_E~0); 82131#L1288-1 assume !(0 == ~T7_E~0); 82367#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 82355#L1298-1 assume !(0 == ~T9_E~0); 82281#L1303-1 assume !(0 == ~T10_E~0); 80926#L1308-1 assume !(0 == ~T11_E~0); 80868#L1313-1 assume !(0 == ~T12_E~0); 80869#L1318-1 assume !(0 == ~T13_E~0); 80875#L1323-1 assume !(0 == ~E_1~0); 80876#L1328-1 assume !(0 == ~E_2~0); 81043#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 82002#L1338-1 assume !(0 == ~E_4~0); 82003#L1343-1 assume !(0 == ~E_5~0); 82104#L1348-1 assume !(0 == ~E_6~0); 82390#L1353-1 assume !(0 == ~E_7~0); 81729#L1358-1 assume !(0 == ~E_8~0); 81730#L1363-1 assume !(0 == ~E_9~0); 82020#L1368-1 assume !(0 == ~E_10~0); 80705#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 80706#L1378-1 assume !(0 == ~E_12~0); 80992#L1383-1 assume !(0 == ~E_13~0); 80993#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81736#L607 assume 1 == ~m_pc~0; 81737#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 81063#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82102#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81656#L1560 assume !(0 != activate_threads_~tmp~1#1); 81657#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80888#L626 assume !(1 == ~t1_pc~0); 80889#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81157#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81158#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81327#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 80788#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80789#L645 assume 1 == ~t2_pc~0; 80905#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 80862#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81539#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81540#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 81632#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81633#L664 assume 1 == ~t3_pc~0; 82389#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 80629#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80630#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81288#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 81289#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82297#L683 assume !(1 == ~t4_pc~0); 81852#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81804#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81805#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 81839#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81963#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81582#L702 assume 1 == ~t5_pc~0; 81583#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 81508#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81958#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82256#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 82197#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80677#L721 assume !(1 == ~t6_pc~0); 80651#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 80652#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80815#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 81297#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 81298#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81899#L740 assume 1 == ~t7_pc~0; 80726#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 80539#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 80540#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 80529#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 80530#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81233#L759 assume !(1 == ~t8_pc~0); 81234#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 81263#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 81956#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 81957#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 82088#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82366#L778 assume 1 == ~t9_pc~0; 82253#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 80704#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 80644#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 80573#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 80574#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 80901#L797 assume !(1 == ~t10_pc~0); 80902#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 81020#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82154#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 81404#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 81405#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 81694#L816 assume 1 == ~t11_pc~0; 80609#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80610#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81365#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81304#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 81305#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81829#L835 assume 1 == ~t12_pc~0; 81707#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 80773#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 80795#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 80936#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 81461#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 81462#L854 assume !(1 == ~t13_pc~0); 81102#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 81103#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 81153#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 80813#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 80814#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82193#L1401 assume !(1 == ~M_E~0); 81292#L1401-2 assume !(1 == ~T1_E~0); 81293#L1406-1 assume !(1 == ~T2_E~0); 81888#L1411-1 assume !(1 == ~T3_E~0); 81889#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81555#L1421-1 assume !(1 == ~T5_E~0); 81098#L1426-1 assume !(1 == ~T6_E~0); 81099#L1431-1 assume !(1 == ~T7_E~0); 80647#L1436-1 assume !(1 == ~T8_E~0); 80648#L1441-1 assume !(1 == ~T9_E~0); 81395#L1446-1 assume !(1 == ~T10_E~0); 81396#L1451-1 assume !(1 == ~T11_E~0); 82101#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 81755#L1461-1 assume !(1 == ~T13_E~0); 81316#L1466-1 assume !(1 == ~E_1~0); 81317#L1471-1 assume !(1 == ~E_2~0); 82086#L1476-1 assume !(1 == ~E_3~0); 82087#L1481-1 assume !(1 == ~E_4~0); 82235#L1486-1 assume !(1 == ~E_5~0); 80941#L1491-1 assume !(1 == ~E_6~0); 80581#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 80582#L1501-1 assume !(1 == ~E_8~0); 81393#L1506-1 assume !(1 == ~E_9~0); 81394#L1511-1 assume !(1 == ~E_10~0); 81350#L1516-1 assume !(1 == ~E_11~0); 80525#L1521-1 assume !(1 == ~E_12~0); 80526#L1526-1 assume !(1 == ~E_13~0); 80580#L1531-1 assume { :end_inline_reset_delta_events } true; 81123#L1892-2 [2022-02-21 04:24:49,417 INFO L793 eck$LassoCheckResult]: Loop: 81123#L1892-2 assume !false; 82146#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82344#L1233 assume !false; 82327#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 81659#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 81639#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 81797#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 80623#L1046 assume !(0 != eval_~tmp~0#1); 80625#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 80659#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 81831#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 82388#L1258-5 assume !(0 == ~T1_E~0); 80801#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 80802#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 82380#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 82386#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 82387#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81025#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 81026#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 82143#L1298-3 assume !(0 == ~T9_E~0); 82144#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 82303#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 82142#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 81643#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 80803#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 80804#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 82227#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 80946#L1338-3 assume !(0 == ~E_4~0); 80947#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 82059#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 82232#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 82233#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 81599#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 81159#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 81160#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 81916#L1378-3 assume !(0 == ~E_12~0); 81917#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 82098#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82099#L607-42 assume !(1 == ~m_pc~0); 81713#L607-44 is_master_triggered_~__retres1~0#1 := 0; 81440#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81441#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81173#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 81174#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81695#L626-42 assume 1 == ~t1_pc~0; 81257#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 81258#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81562#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81563#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 80837#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 80838#L645-42 assume !(1 == ~t2_pc~0); 82037#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 82038#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82203#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 81044#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80551#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80552#L664-42 assume !(1 == ~t3_pc~0); 81078#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 81079#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82330#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 81865#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 81866#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82031#L683-42 assume !(1 == ~t4_pc~0); 81739#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 81740#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81872#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82292#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82293#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82137#L702-42 assume !(1 == ~t5_pc~0); 81249#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 81250#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81546#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82219#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 80567#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80568#L721-42 assume 1 == ~t6_pc~0; 80721#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 80741#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 81205#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82372#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 81377#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81223#L740-42 assume !(1 == ~t7_pc~0); 80960#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 80961#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81502#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 81357#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 81358#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 81631#L759-42 assume !(1 == ~t8_pc~0); 81481#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 81412#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 81413#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 81491#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 81492#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 81587#L778-42 assume !(1 == ~t9_pc~0); 81425#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 81426#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 81836#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 81741#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 81742#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 81799#L797-42 assume 1 == ~t10_pc~0; 80966#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 80967#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 81968#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 82277#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 81837#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 81838#L816-42 assume 1 == ~t11_pc~0; 80515#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 80516#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 81058#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 81059#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 81138#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81139#L835-42 assume 1 == ~t12_pc~0; 81543#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 81436#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 81113#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 81114#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 82196#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 81980#L854-42 assume !(1 == ~t13_pc~0); 81056#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 81057#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 80667#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 80668#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 81314#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81315#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 82093#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 80904#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80768#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 80769#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 81368#L1421-3 assume !(1 == ~T5_E~0); 81369#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 80944#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 80945#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 80531#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 80532#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 82121#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 81452#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 81105#L1461-3 assume !(1 == ~T13_E~0); 81106#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 82383#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81045#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81046#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81446#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 81073#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 81074#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 81486#L1501-3 assume !(1 == ~E_8~0); 81487#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 81913#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 81903#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 81904#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 81603#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 81604#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 81998#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 80880#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 81773#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 81414#L1911 assume !(0 == start_simulation_~tmp~3#1); 81415#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 81937#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 81004#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 81875#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 80709#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 80710#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 80939#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 80940#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 81123#L1892-2 [2022-02-21 04:24:49,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:49,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1281641374, now seen corresponding path program 1 times [2022-02-21 04:24:49,418 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:49,418 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110300019] [2022-02-21 04:24:49,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:49,418 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:49,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:49,442 INFO L290 TraceCheckUtils]: 0: Hoare triple {86245#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {86245#true} is VALID [2022-02-21 04:24:49,443 INFO L290 TraceCheckUtils]: 1: Hoare triple {86245#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,443 INFO L290 TraceCheckUtils]: 2: Hoare triple {86247#(= ~t12_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,443 INFO L290 TraceCheckUtils]: 3: Hoare triple {86247#(= ~t12_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,444 INFO L290 TraceCheckUtils]: 4: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,444 INFO L290 TraceCheckUtils]: 5: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,444 INFO L290 TraceCheckUtils]: 6: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,445 INFO L290 TraceCheckUtils]: 7: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,445 INFO L290 TraceCheckUtils]: 8: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,445 INFO L290 TraceCheckUtils]: 9: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,445 INFO L290 TraceCheckUtils]: 10: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,446 INFO L290 TraceCheckUtils]: 11: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,446 INFO L290 TraceCheckUtils]: 12: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,446 INFO L290 TraceCheckUtils]: 13: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,447 INFO L290 TraceCheckUtils]: 14: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,447 INFO L290 TraceCheckUtils]: 15: Hoare triple {86247#(= ~t12_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {86247#(= ~t12_i~0 1)} is VALID [2022-02-21 04:24:49,447 INFO L290 TraceCheckUtils]: 16: Hoare triple {86247#(= ~t12_i~0 1)} assume !(1 == ~t12_i~0);~t12_st~0 := 2; {86246#false} is VALID [2022-02-21 04:24:49,447 INFO L290 TraceCheckUtils]: 17: Hoare triple {86246#false} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {86246#false} is VALID [2022-02-21 04:24:49,447 INFO L290 TraceCheckUtils]: 18: Hoare triple {86246#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {86246#false} is VALID [2022-02-21 04:24:49,447 INFO L290 TraceCheckUtils]: 19: Hoare triple {86246#false} assume 0 == ~M_E~0;~M_E~0 := 1; {86246#false} is VALID [2022-02-21 04:24:49,447 INFO L290 TraceCheckUtils]: 20: Hoare triple {86246#false} assume !(0 == ~T1_E~0); {86246#false} is VALID [2022-02-21 04:24:49,448 INFO L290 TraceCheckUtils]: 21: Hoare triple {86246#false} assume !(0 == ~T2_E~0); {86246#false} is VALID [2022-02-21 04:24:49,448 INFO L290 TraceCheckUtils]: 22: Hoare triple {86246#false} assume !(0 == ~T3_E~0); {86246#false} is VALID [2022-02-21 04:24:49,448 INFO L290 TraceCheckUtils]: 23: Hoare triple {86246#false} assume !(0 == ~T4_E~0); {86246#false} is VALID [2022-02-21 04:24:49,448 INFO L290 TraceCheckUtils]: 24: Hoare triple {86246#false} assume !(0 == ~T5_E~0); {86246#false} is VALID [2022-02-21 04:24:49,448 INFO L290 TraceCheckUtils]: 25: Hoare triple {86246#false} assume !(0 == ~T6_E~0); {86246#false} is VALID [2022-02-21 04:24:49,448 INFO L290 TraceCheckUtils]: 26: Hoare triple {86246#false} assume !(0 == ~T7_E~0); {86246#false} is VALID [2022-02-21 04:24:49,448 INFO L290 TraceCheckUtils]: 27: Hoare triple {86246#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {86246#false} is VALID [2022-02-21 04:24:49,448 INFO L290 TraceCheckUtils]: 28: Hoare triple {86246#false} assume !(0 == ~T9_E~0); {86246#false} is VALID [2022-02-21 04:24:49,448 INFO L290 TraceCheckUtils]: 29: Hoare triple {86246#false} assume !(0 == ~T10_E~0); {86246#false} is VALID [2022-02-21 04:24:49,448 INFO L290 TraceCheckUtils]: 30: Hoare triple {86246#false} assume !(0 == ~T11_E~0); {86246#false} is VALID [2022-02-21 04:24:49,449 INFO L290 TraceCheckUtils]: 31: Hoare triple {86246#false} assume !(0 == ~T12_E~0); {86246#false} is VALID [2022-02-21 04:24:49,449 INFO L290 TraceCheckUtils]: 32: Hoare triple {86246#false} assume !(0 == ~T13_E~0); {86246#false} is VALID [2022-02-21 04:24:49,449 INFO L290 TraceCheckUtils]: 33: Hoare triple {86246#false} assume !(0 == ~E_1~0); {86246#false} is VALID [2022-02-21 04:24:49,449 INFO L290 TraceCheckUtils]: 34: Hoare triple {86246#false} assume !(0 == ~E_2~0); {86246#false} is VALID [2022-02-21 04:24:49,449 INFO L290 TraceCheckUtils]: 35: Hoare triple {86246#false} assume 0 == ~E_3~0;~E_3~0 := 1; {86246#false} is VALID [2022-02-21 04:24:49,449 INFO L290 TraceCheckUtils]: 36: Hoare triple {86246#false} assume !(0 == ~E_4~0); {86246#false} is VALID [2022-02-21 04:24:49,449 INFO L290 TraceCheckUtils]: 37: Hoare triple {86246#false} assume !(0 == ~E_5~0); {86246#false} is VALID [2022-02-21 04:24:49,449 INFO L290 TraceCheckUtils]: 38: Hoare triple {86246#false} assume !(0 == ~E_6~0); {86246#false} is VALID [2022-02-21 04:24:49,449 INFO L290 TraceCheckUtils]: 39: Hoare triple {86246#false} assume !(0 == ~E_7~0); {86246#false} is VALID [2022-02-21 04:24:49,449 INFO L290 TraceCheckUtils]: 40: Hoare triple {86246#false} assume !(0 == ~E_8~0); {86246#false} is VALID [2022-02-21 04:24:49,450 INFO L290 TraceCheckUtils]: 41: Hoare triple {86246#false} assume !(0 == ~E_9~0); {86246#false} is VALID [2022-02-21 04:24:49,450 INFO L290 TraceCheckUtils]: 42: Hoare triple {86246#false} assume !(0 == ~E_10~0); {86246#false} is VALID [2022-02-21 04:24:49,450 INFO L290 TraceCheckUtils]: 43: Hoare triple {86246#false} assume 0 == ~E_11~0;~E_11~0 := 1; {86246#false} is VALID [2022-02-21 04:24:49,450 INFO L290 TraceCheckUtils]: 44: Hoare triple {86246#false} assume !(0 == ~E_12~0); {86246#false} is VALID [2022-02-21 04:24:49,450 INFO L290 TraceCheckUtils]: 45: Hoare triple {86246#false} assume !(0 == ~E_13~0); {86246#false} is VALID [2022-02-21 04:24:49,450 INFO L290 TraceCheckUtils]: 46: Hoare triple {86246#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {86246#false} is VALID [2022-02-21 04:24:49,450 INFO L290 TraceCheckUtils]: 47: Hoare triple {86246#false} assume 1 == ~m_pc~0; {86246#false} is VALID [2022-02-21 04:24:49,450 INFO L290 TraceCheckUtils]: 48: Hoare triple {86246#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {86246#false} is VALID [2022-02-21 04:24:49,450 INFO L290 TraceCheckUtils]: 49: Hoare triple {86246#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {86246#false} is VALID [2022-02-21 04:24:49,450 INFO L290 TraceCheckUtils]: 50: Hoare triple {86246#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {86246#false} is VALID [2022-02-21 04:24:49,451 INFO L290 TraceCheckUtils]: 51: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp~1#1); {86246#false} is VALID [2022-02-21 04:24:49,451 INFO L290 TraceCheckUtils]: 52: Hoare triple {86246#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {86246#false} is VALID [2022-02-21 04:24:49,451 INFO L290 TraceCheckUtils]: 53: Hoare triple {86246#false} assume !(1 == ~t1_pc~0); {86246#false} is VALID [2022-02-21 04:24:49,451 INFO L290 TraceCheckUtils]: 54: Hoare triple {86246#false} is_transmit1_triggered_~__retres1~1#1 := 0; {86246#false} is VALID [2022-02-21 04:24:49,451 INFO L290 TraceCheckUtils]: 55: Hoare triple {86246#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {86246#false} is VALID [2022-02-21 04:24:49,451 INFO L290 TraceCheckUtils]: 56: Hoare triple {86246#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {86246#false} is VALID [2022-02-21 04:24:49,451 INFO L290 TraceCheckUtils]: 57: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp___0~0#1); {86246#false} is VALID [2022-02-21 04:24:49,451 INFO L290 TraceCheckUtils]: 58: Hoare triple {86246#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {86246#false} is VALID [2022-02-21 04:24:49,451 INFO L290 TraceCheckUtils]: 59: Hoare triple {86246#false} assume 1 == ~t2_pc~0; {86246#false} is VALID [2022-02-21 04:24:49,451 INFO L290 TraceCheckUtils]: 60: Hoare triple {86246#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {86246#false} is VALID [2022-02-21 04:24:49,452 INFO L290 TraceCheckUtils]: 61: Hoare triple {86246#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {86246#false} is VALID [2022-02-21 04:24:49,452 INFO L290 TraceCheckUtils]: 62: Hoare triple {86246#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {86246#false} is VALID [2022-02-21 04:24:49,452 INFO L290 TraceCheckUtils]: 63: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp___1~0#1); {86246#false} is VALID [2022-02-21 04:24:49,452 INFO L290 TraceCheckUtils]: 64: Hoare triple {86246#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {86246#false} is VALID [2022-02-21 04:24:49,452 INFO L290 TraceCheckUtils]: 65: Hoare triple {86246#false} assume 1 == ~t3_pc~0; {86246#false} is VALID [2022-02-21 04:24:49,452 INFO L290 TraceCheckUtils]: 66: Hoare triple {86246#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {86246#false} is VALID [2022-02-21 04:24:49,452 INFO L290 TraceCheckUtils]: 67: Hoare triple {86246#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {86246#false} is VALID [2022-02-21 04:24:49,452 INFO L290 TraceCheckUtils]: 68: Hoare triple {86246#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {86246#false} is VALID [2022-02-21 04:24:49,452 INFO L290 TraceCheckUtils]: 69: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp___2~0#1); {86246#false} is VALID [2022-02-21 04:24:49,452 INFO L290 TraceCheckUtils]: 70: Hoare triple {86246#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {86246#false} is VALID [2022-02-21 04:24:49,453 INFO L290 TraceCheckUtils]: 71: Hoare triple {86246#false} assume !(1 == ~t4_pc~0); {86246#false} is VALID [2022-02-21 04:24:49,453 INFO L290 TraceCheckUtils]: 72: Hoare triple {86246#false} is_transmit4_triggered_~__retres1~4#1 := 0; {86246#false} is VALID [2022-02-21 04:24:49,453 INFO L290 TraceCheckUtils]: 73: Hoare triple {86246#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {86246#false} is VALID [2022-02-21 04:24:49,453 INFO L290 TraceCheckUtils]: 74: Hoare triple {86246#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {86246#false} is VALID [2022-02-21 04:24:49,453 INFO L290 TraceCheckUtils]: 75: Hoare triple {86246#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {86246#false} is VALID [2022-02-21 04:24:49,453 INFO L290 TraceCheckUtils]: 76: Hoare triple {86246#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {86246#false} is VALID [2022-02-21 04:24:49,453 INFO L290 TraceCheckUtils]: 77: Hoare triple {86246#false} assume 1 == ~t5_pc~0; {86246#false} is VALID [2022-02-21 04:24:49,453 INFO L290 TraceCheckUtils]: 78: Hoare triple {86246#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {86246#false} is VALID [2022-02-21 04:24:49,453 INFO L290 TraceCheckUtils]: 79: Hoare triple {86246#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {86246#false} is VALID [2022-02-21 04:24:49,453 INFO L290 TraceCheckUtils]: 80: Hoare triple {86246#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {86246#false} is VALID [2022-02-21 04:24:49,454 INFO L290 TraceCheckUtils]: 81: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp___4~0#1); {86246#false} is VALID [2022-02-21 04:24:49,454 INFO L290 TraceCheckUtils]: 82: Hoare triple {86246#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {86246#false} is VALID [2022-02-21 04:24:49,454 INFO L290 TraceCheckUtils]: 83: Hoare triple {86246#false} assume !(1 == ~t6_pc~0); {86246#false} is VALID [2022-02-21 04:24:49,454 INFO L290 TraceCheckUtils]: 84: Hoare triple {86246#false} is_transmit6_triggered_~__retres1~6#1 := 0; {86246#false} is VALID [2022-02-21 04:24:49,454 INFO L290 TraceCheckUtils]: 85: Hoare triple {86246#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {86246#false} is VALID [2022-02-21 04:24:49,454 INFO L290 TraceCheckUtils]: 86: Hoare triple {86246#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {86246#false} is VALID [2022-02-21 04:24:49,454 INFO L290 TraceCheckUtils]: 87: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp___5~0#1); {86246#false} is VALID [2022-02-21 04:24:49,454 INFO L290 TraceCheckUtils]: 88: Hoare triple {86246#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {86246#false} is VALID [2022-02-21 04:24:49,454 INFO L290 TraceCheckUtils]: 89: Hoare triple {86246#false} assume 1 == ~t7_pc~0; {86246#false} is VALID [2022-02-21 04:24:49,454 INFO L290 TraceCheckUtils]: 90: Hoare triple {86246#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {86246#false} is VALID [2022-02-21 04:24:49,455 INFO L290 TraceCheckUtils]: 91: Hoare triple {86246#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {86246#false} is VALID [2022-02-21 04:24:49,455 INFO L290 TraceCheckUtils]: 92: Hoare triple {86246#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {86246#false} is VALID [2022-02-21 04:24:49,455 INFO L290 TraceCheckUtils]: 93: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp___6~0#1); {86246#false} is VALID [2022-02-21 04:24:49,455 INFO L290 TraceCheckUtils]: 94: Hoare triple {86246#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {86246#false} is VALID [2022-02-21 04:24:49,455 INFO L290 TraceCheckUtils]: 95: Hoare triple {86246#false} assume !(1 == ~t8_pc~0); {86246#false} is VALID [2022-02-21 04:24:49,455 INFO L290 TraceCheckUtils]: 96: Hoare triple {86246#false} is_transmit8_triggered_~__retres1~8#1 := 0; {86246#false} is VALID [2022-02-21 04:24:49,455 INFO L290 TraceCheckUtils]: 97: Hoare triple {86246#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {86246#false} is VALID [2022-02-21 04:24:49,455 INFO L290 TraceCheckUtils]: 98: Hoare triple {86246#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {86246#false} is VALID [2022-02-21 04:24:49,455 INFO L290 TraceCheckUtils]: 99: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp___7~0#1); {86246#false} is VALID [2022-02-21 04:24:49,455 INFO L290 TraceCheckUtils]: 100: Hoare triple {86246#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {86246#false} is VALID [2022-02-21 04:24:49,456 INFO L290 TraceCheckUtils]: 101: Hoare triple {86246#false} assume 1 == ~t9_pc~0; {86246#false} is VALID [2022-02-21 04:24:49,456 INFO L290 TraceCheckUtils]: 102: Hoare triple {86246#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {86246#false} is VALID [2022-02-21 04:24:49,456 INFO L290 TraceCheckUtils]: 103: Hoare triple {86246#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {86246#false} is VALID [2022-02-21 04:24:49,456 INFO L290 TraceCheckUtils]: 104: Hoare triple {86246#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {86246#false} is VALID [2022-02-21 04:24:49,456 INFO L290 TraceCheckUtils]: 105: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp___8~0#1); {86246#false} is VALID [2022-02-21 04:24:49,456 INFO L290 TraceCheckUtils]: 106: Hoare triple {86246#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {86246#false} is VALID [2022-02-21 04:24:49,456 INFO L290 TraceCheckUtils]: 107: Hoare triple {86246#false} assume !(1 == ~t10_pc~0); {86246#false} is VALID [2022-02-21 04:24:49,456 INFO L290 TraceCheckUtils]: 108: Hoare triple {86246#false} is_transmit10_triggered_~__retres1~10#1 := 0; {86246#false} is VALID [2022-02-21 04:24:49,456 INFO L290 TraceCheckUtils]: 109: Hoare triple {86246#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {86246#false} is VALID [2022-02-21 04:24:49,456 INFO L290 TraceCheckUtils]: 110: Hoare triple {86246#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {86246#false} is VALID [2022-02-21 04:24:49,456 INFO L290 TraceCheckUtils]: 111: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp___9~0#1); {86246#false} is VALID [2022-02-21 04:24:49,457 INFO L290 TraceCheckUtils]: 112: Hoare triple {86246#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {86246#false} is VALID [2022-02-21 04:24:49,457 INFO L290 TraceCheckUtils]: 113: Hoare triple {86246#false} assume 1 == ~t11_pc~0; {86246#false} is VALID [2022-02-21 04:24:49,457 INFO L290 TraceCheckUtils]: 114: Hoare triple {86246#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {86246#false} is VALID [2022-02-21 04:24:49,457 INFO L290 TraceCheckUtils]: 115: Hoare triple {86246#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {86246#false} is VALID [2022-02-21 04:24:49,457 INFO L290 TraceCheckUtils]: 116: Hoare triple {86246#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {86246#false} is VALID [2022-02-21 04:24:49,457 INFO L290 TraceCheckUtils]: 117: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp___10~0#1); {86246#false} is VALID [2022-02-21 04:24:49,457 INFO L290 TraceCheckUtils]: 118: Hoare triple {86246#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {86246#false} is VALID [2022-02-21 04:24:49,457 INFO L290 TraceCheckUtils]: 119: Hoare triple {86246#false} assume 1 == ~t12_pc~0; {86246#false} is VALID [2022-02-21 04:24:49,457 INFO L290 TraceCheckUtils]: 120: Hoare triple {86246#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {86246#false} is VALID [2022-02-21 04:24:49,457 INFO L290 TraceCheckUtils]: 121: Hoare triple {86246#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {86246#false} is VALID [2022-02-21 04:24:49,458 INFO L290 TraceCheckUtils]: 122: Hoare triple {86246#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {86246#false} is VALID [2022-02-21 04:24:49,458 INFO L290 TraceCheckUtils]: 123: Hoare triple {86246#false} assume !(0 != activate_threads_~tmp___11~0#1); {86246#false} is VALID [2022-02-21 04:24:49,458 INFO L290 TraceCheckUtils]: 124: Hoare triple {86246#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {86246#false} is VALID [2022-02-21 04:24:49,458 INFO L290 TraceCheckUtils]: 125: Hoare triple {86246#false} assume !(1 == ~t13_pc~0); {86246#false} is VALID [2022-02-21 04:24:49,458 INFO L290 TraceCheckUtils]: 126: Hoare triple {86246#false} is_transmit13_triggered_~__retres1~13#1 := 0; {86246#false} is VALID [2022-02-21 04:24:49,458 INFO L290 TraceCheckUtils]: 127: Hoare triple {86246#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {86246#false} is VALID [2022-02-21 04:24:49,458 INFO L290 TraceCheckUtils]: 128: Hoare triple {86246#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {86246#false} is VALID [2022-02-21 04:24:49,458 INFO L290 TraceCheckUtils]: 129: Hoare triple {86246#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {86246#false} is VALID [2022-02-21 04:24:49,458 INFO L290 TraceCheckUtils]: 130: Hoare triple {86246#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {86246#false} is VALID [2022-02-21 04:24:49,458 INFO L290 TraceCheckUtils]: 131: Hoare triple {86246#false} assume !(1 == ~M_E~0); {86246#false} is VALID [2022-02-21 04:24:49,459 INFO L290 TraceCheckUtils]: 132: Hoare triple {86246#false} assume !(1 == ~T1_E~0); {86246#false} is VALID [2022-02-21 04:24:49,459 INFO L290 TraceCheckUtils]: 133: Hoare triple {86246#false} assume !(1 == ~T2_E~0); {86246#false} is VALID [2022-02-21 04:24:49,459 INFO L290 TraceCheckUtils]: 134: Hoare triple {86246#false} assume !(1 == ~T3_E~0); {86246#false} is VALID [2022-02-21 04:24:49,459 INFO L290 TraceCheckUtils]: 135: Hoare triple {86246#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {86246#false} is VALID [2022-02-21 04:24:49,459 INFO L290 TraceCheckUtils]: 136: Hoare triple {86246#false} assume !(1 == ~T5_E~0); {86246#false} is VALID [2022-02-21 04:24:49,459 INFO L290 TraceCheckUtils]: 137: Hoare triple {86246#false} assume !(1 == ~T6_E~0); {86246#false} is VALID [2022-02-21 04:24:49,459 INFO L290 TraceCheckUtils]: 138: Hoare triple {86246#false} assume !(1 == ~T7_E~0); {86246#false} is VALID [2022-02-21 04:24:49,459 INFO L290 TraceCheckUtils]: 139: Hoare triple {86246#false} assume !(1 == ~T8_E~0); {86246#false} is VALID [2022-02-21 04:24:49,459 INFO L290 TraceCheckUtils]: 140: Hoare triple {86246#false} assume !(1 == ~T9_E~0); {86246#false} is VALID [2022-02-21 04:24:49,459 INFO L290 TraceCheckUtils]: 141: Hoare triple {86246#false} assume !(1 == ~T10_E~0); {86246#false} is VALID [2022-02-21 04:24:49,459 INFO L290 TraceCheckUtils]: 142: Hoare triple {86246#false} assume !(1 == ~T11_E~0); {86246#false} is VALID [2022-02-21 04:24:49,460 INFO L290 TraceCheckUtils]: 143: Hoare triple {86246#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {86246#false} is VALID [2022-02-21 04:24:49,460 INFO L290 TraceCheckUtils]: 144: Hoare triple {86246#false} assume !(1 == ~T13_E~0); {86246#false} is VALID [2022-02-21 04:24:49,460 INFO L290 TraceCheckUtils]: 145: Hoare triple {86246#false} assume !(1 == ~E_1~0); {86246#false} is VALID [2022-02-21 04:24:49,460 INFO L290 TraceCheckUtils]: 146: Hoare triple {86246#false} assume !(1 == ~E_2~0); {86246#false} is VALID [2022-02-21 04:24:49,460 INFO L290 TraceCheckUtils]: 147: Hoare triple {86246#false} assume !(1 == ~E_3~0); {86246#false} is VALID [2022-02-21 04:24:49,460 INFO L290 TraceCheckUtils]: 148: Hoare triple {86246#false} assume !(1 == ~E_4~0); {86246#false} is VALID [2022-02-21 04:24:49,460 INFO L290 TraceCheckUtils]: 149: Hoare triple {86246#false} assume !(1 == ~E_5~0); {86246#false} is VALID [2022-02-21 04:24:49,460 INFO L290 TraceCheckUtils]: 150: Hoare triple {86246#false} assume !(1 == ~E_6~0); {86246#false} is VALID [2022-02-21 04:24:49,460 INFO L290 TraceCheckUtils]: 151: Hoare triple {86246#false} assume 1 == ~E_7~0;~E_7~0 := 2; {86246#false} is VALID [2022-02-21 04:24:49,460 INFO L290 TraceCheckUtils]: 152: Hoare triple {86246#false} assume !(1 == ~E_8~0); {86246#false} is VALID [2022-02-21 04:24:49,461 INFO L290 TraceCheckUtils]: 153: Hoare triple {86246#false} assume !(1 == ~E_9~0); {86246#false} is VALID [2022-02-21 04:24:49,461 INFO L290 TraceCheckUtils]: 154: Hoare triple {86246#false} assume !(1 == ~E_10~0); {86246#false} is VALID [2022-02-21 04:24:49,461 INFO L290 TraceCheckUtils]: 155: Hoare triple {86246#false} assume !(1 == ~E_11~0); {86246#false} is VALID [2022-02-21 04:24:49,461 INFO L290 TraceCheckUtils]: 156: Hoare triple {86246#false} assume !(1 == ~E_12~0); {86246#false} is VALID [2022-02-21 04:24:49,461 INFO L290 TraceCheckUtils]: 157: Hoare triple {86246#false} assume !(1 == ~E_13~0); {86246#false} is VALID [2022-02-21 04:24:49,461 INFO L290 TraceCheckUtils]: 158: Hoare triple {86246#false} assume { :end_inline_reset_delta_events } true; {86246#false} is VALID [2022-02-21 04:24:49,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:49,462 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:49,462 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2110300019] [2022-02-21 04:24:49,462 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2110300019] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:49,462 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:49,462 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:49,462 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484964859] [2022-02-21 04:24:49,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:49,463 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:49,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:49,463 INFO L85 PathProgramCache]: Analyzing trace with hash -1535351462, now seen corresponding path program 1 times [2022-02-21 04:24:49,463 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:49,463 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685607461] [2022-02-21 04:24:49,463 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:49,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:49,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:49,495 INFO L290 TraceCheckUtils]: 0: Hoare triple {86248#true} assume !false; {86248#true} is VALID [2022-02-21 04:24:49,495 INFO L290 TraceCheckUtils]: 1: Hoare triple {86248#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {86248#true} is VALID [2022-02-21 04:24:49,495 INFO L290 TraceCheckUtils]: 2: Hoare triple {86248#true} assume !false; {86248#true} is VALID [2022-02-21 04:24:49,496 INFO L290 TraceCheckUtils]: 3: Hoare triple {86248#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {86248#true} is VALID [2022-02-21 04:24:49,496 INFO L290 TraceCheckUtils]: 4: Hoare triple {86248#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {86248#true} is VALID [2022-02-21 04:24:49,496 INFO L290 TraceCheckUtils]: 5: Hoare triple {86248#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {86248#true} is VALID [2022-02-21 04:24:49,496 INFO L290 TraceCheckUtils]: 6: Hoare triple {86248#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {86248#true} is VALID [2022-02-21 04:24:49,496 INFO L290 TraceCheckUtils]: 7: Hoare triple {86248#true} assume !(0 != eval_~tmp~0#1); {86248#true} is VALID [2022-02-21 04:24:49,496 INFO L290 TraceCheckUtils]: 8: Hoare triple {86248#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {86248#true} is VALID [2022-02-21 04:24:49,496 INFO L290 TraceCheckUtils]: 9: Hoare triple {86248#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {86248#true} is VALID [2022-02-21 04:24:49,496 INFO L290 TraceCheckUtils]: 10: Hoare triple {86248#true} assume 0 == ~M_E~0;~M_E~0 := 1; {86248#true} is VALID [2022-02-21 04:24:49,496 INFO L290 TraceCheckUtils]: 11: Hoare triple {86248#true} assume !(0 == ~T1_E~0); {86248#true} is VALID [2022-02-21 04:24:49,496 INFO L290 TraceCheckUtils]: 12: Hoare triple {86248#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {86248#true} is VALID [2022-02-21 04:24:49,497 INFO L290 TraceCheckUtils]: 13: Hoare triple {86248#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {86248#true} is VALID [2022-02-21 04:24:49,497 INFO L290 TraceCheckUtils]: 14: Hoare triple {86248#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {86248#true} is VALID [2022-02-21 04:24:49,497 INFO L290 TraceCheckUtils]: 15: Hoare triple {86248#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,497 INFO L290 TraceCheckUtils]: 16: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,498 INFO L290 TraceCheckUtils]: 17: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,498 INFO L290 TraceCheckUtils]: 18: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,498 INFO L290 TraceCheckUtils]: 19: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,499 INFO L290 TraceCheckUtils]: 20: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,499 INFO L290 TraceCheckUtils]: 21: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,499 INFO L290 TraceCheckUtils]: 22: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,500 INFO L290 TraceCheckUtils]: 23: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,500 INFO L290 TraceCheckUtils]: 24: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,500 INFO L290 TraceCheckUtils]: 25: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,501 INFO L290 TraceCheckUtils]: 26: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,501 INFO L290 TraceCheckUtils]: 27: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,501 INFO L290 TraceCheckUtils]: 28: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,502 INFO L290 TraceCheckUtils]: 29: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,502 INFO L290 TraceCheckUtils]: 30: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,502 INFO L290 TraceCheckUtils]: 31: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,503 INFO L290 TraceCheckUtils]: 32: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,503 INFO L290 TraceCheckUtils]: 33: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,503 INFO L290 TraceCheckUtils]: 34: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,504 INFO L290 TraceCheckUtils]: 35: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,504 INFO L290 TraceCheckUtils]: 36: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,504 INFO L290 TraceCheckUtils]: 37: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,505 INFO L290 TraceCheckUtils]: 38: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,505 INFO L290 TraceCheckUtils]: 39: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,505 INFO L290 TraceCheckUtils]: 40: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,506 INFO L290 TraceCheckUtils]: 41: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,506 INFO L290 TraceCheckUtils]: 42: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,506 INFO L290 TraceCheckUtils]: 43: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,507 INFO L290 TraceCheckUtils]: 44: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,507 INFO L290 TraceCheckUtils]: 45: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,507 INFO L290 TraceCheckUtils]: 46: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,508 INFO L290 TraceCheckUtils]: 47: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,508 INFO L290 TraceCheckUtils]: 48: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,508 INFO L290 TraceCheckUtils]: 49: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,509 INFO L290 TraceCheckUtils]: 50: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,509 INFO L290 TraceCheckUtils]: 51: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,509 INFO L290 TraceCheckUtils]: 52: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,510 INFO L290 TraceCheckUtils]: 53: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,510 INFO L290 TraceCheckUtils]: 54: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,510 INFO L290 TraceCheckUtils]: 55: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,511 INFO L290 TraceCheckUtils]: 56: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,511 INFO L290 TraceCheckUtils]: 57: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,511 INFO L290 TraceCheckUtils]: 58: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,511 INFO L290 TraceCheckUtils]: 59: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,512 INFO L290 TraceCheckUtils]: 60: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,512 INFO L290 TraceCheckUtils]: 61: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,512 INFO L290 TraceCheckUtils]: 62: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,513 INFO L290 TraceCheckUtils]: 63: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,513 INFO L290 TraceCheckUtils]: 64: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,513 INFO L290 TraceCheckUtils]: 65: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,514 INFO L290 TraceCheckUtils]: 66: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,514 INFO L290 TraceCheckUtils]: 67: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,514 INFO L290 TraceCheckUtils]: 68: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,515 INFO L290 TraceCheckUtils]: 69: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,515 INFO L290 TraceCheckUtils]: 70: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,515 INFO L290 TraceCheckUtils]: 71: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,516 INFO L290 TraceCheckUtils]: 72: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,516 INFO L290 TraceCheckUtils]: 73: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,516 INFO L290 TraceCheckUtils]: 74: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,517 INFO L290 TraceCheckUtils]: 75: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,517 INFO L290 TraceCheckUtils]: 76: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,517 INFO L290 TraceCheckUtils]: 77: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,518 INFO L290 TraceCheckUtils]: 78: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,518 INFO L290 TraceCheckUtils]: 79: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,518 INFO L290 TraceCheckUtils]: 80: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t7_pc~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,519 INFO L290 TraceCheckUtils]: 81: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,519 INFO L290 TraceCheckUtils]: 82: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,519 INFO L290 TraceCheckUtils]: 83: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,520 INFO L290 TraceCheckUtils]: 84: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,520 INFO L290 TraceCheckUtils]: 85: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,520 INFO L290 TraceCheckUtils]: 86: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,521 INFO L290 TraceCheckUtils]: 87: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,521 INFO L290 TraceCheckUtils]: 88: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,521 INFO L290 TraceCheckUtils]: 89: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,522 INFO L290 TraceCheckUtils]: 90: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,522 INFO L290 TraceCheckUtils]: 91: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,522 INFO L290 TraceCheckUtils]: 92: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,523 INFO L290 TraceCheckUtils]: 93: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,523 INFO L290 TraceCheckUtils]: 94: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,523 INFO L290 TraceCheckUtils]: 95: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,524 INFO L290 TraceCheckUtils]: 96: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,524 INFO L290 TraceCheckUtils]: 97: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,524 INFO L290 TraceCheckUtils]: 98: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,525 INFO L290 TraceCheckUtils]: 99: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,525 INFO L290 TraceCheckUtils]: 100: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,525 INFO L290 TraceCheckUtils]: 101: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,526 INFO L290 TraceCheckUtils]: 102: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,526 INFO L290 TraceCheckUtils]: 103: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,526 INFO L290 TraceCheckUtils]: 104: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,526 INFO L290 TraceCheckUtils]: 105: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,527 INFO L290 TraceCheckUtils]: 106: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,527 INFO L290 TraceCheckUtils]: 107: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,527 INFO L290 TraceCheckUtils]: 108: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,528 INFO L290 TraceCheckUtils]: 109: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,528 INFO L290 TraceCheckUtils]: 110: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,528 INFO L290 TraceCheckUtils]: 111: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,529 INFO L290 TraceCheckUtils]: 112: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,529 INFO L290 TraceCheckUtils]: 113: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,529 INFO L290 TraceCheckUtils]: 114: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,530 INFO L290 TraceCheckUtils]: 115: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,530 INFO L290 TraceCheckUtils]: 116: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,530 INFO L290 TraceCheckUtils]: 117: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,531 INFO L290 TraceCheckUtils]: 118: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,531 INFO L290 TraceCheckUtils]: 119: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,531 INFO L290 TraceCheckUtils]: 120: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,532 INFO L290 TraceCheckUtils]: 121: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,532 INFO L290 TraceCheckUtils]: 122: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,532 INFO L290 TraceCheckUtils]: 123: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,533 INFO L290 TraceCheckUtils]: 124: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,533 INFO L290 TraceCheckUtils]: 125: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,533 INFO L290 TraceCheckUtils]: 126: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {86250#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:49,534 INFO L290 TraceCheckUtils]: 127: Hoare triple {86250#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {86249#false} is VALID [2022-02-21 04:24:49,534 INFO L290 TraceCheckUtils]: 128: Hoare triple {86249#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,534 INFO L290 TraceCheckUtils]: 129: Hoare triple {86249#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,534 INFO L290 TraceCheckUtils]: 130: Hoare triple {86249#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,534 INFO L290 TraceCheckUtils]: 131: Hoare triple {86249#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,534 INFO L290 TraceCheckUtils]: 132: Hoare triple {86249#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,534 INFO L290 TraceCheckUtils]: 133: Hoare triple {86249#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,534 INFO L290 TraceCheckUtils]: 134: Hoare triple {86249#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,534 INFO L290 TraceCheckUtils]: 135: Hoare triple {86249#false} assume !(1 == ~T13_E~0); {86249#false} is VALID [2022-02-21 04:24:49,535 INFO L290 TraceCheckUtils]: 136: Hoare triple {86249#false} assume 1 == ~E_1~0;~E_1~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,535 INFO L290 TraceCheckUtils]: 137: Hoare triple {86249#false} assume 1 == ~E_2~0;~E_2~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,535 INFO L290 TraceCheckUtils]: 138: Hoare triple {86249#false} assume 1 == ~E_3~0;~E_3~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,535 INFO L290 TraceCheckUtils]: 139: Hoare triple {86249#false} assume 1 == ~E_4~0;~E_4~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,535 INFO L290 TraceCheckUtils]: 140: Hoare triple {86249#false} assume 1 == ~E_5~0;~E_5~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,535 INFO L290 TraceCheckUtils]: 141: Hoare triple {86249#false} assume 1 == ~E_6~0;~E_6~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,535 INFO L290 TraceCheckUtils]: 142: Hoare triple {86249#false} assume 1 == ~E_7~0;~E_7~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,535 INFO L290 TraceCheckUtils]: 143: Hoare triple {86249#false} assume !(1 == ~E_8~0); {86249#false} is VALID [2022-02-21 04:24:49,535 INFO L290 TraceCheckUtils]: 144: Hoare triple {86249#false} assume 1 == ~E_9~0;~E_9~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,535 INFO L290 TraceCheckUtils]: 145: Hoare triple {86249#false} assume 1 == ~E_10~0;~E_10~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,535 INFO L290 TraceCheckUtils]: 146: Hoare triple {86249#false} assume 1 == ~E_11~0;~E_11~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,536 INFO L290 TraceCheckUtils]: 147: Hoare triple {86249#false} assume 1 == ~E_12~0;~E_12~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,536 INFO L290 TraceCheckUtils]: 148: Hoare triple {86249#false} assume 1 == ~E_13~0;~E_13~0 := 2; {86249#false} is VALID [2022-02-21 04:24:49,536 INFO L290 TraceCheckUtils]: 149: Hoare triple {86249#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {86249#false} is VALID [2022-02-21 04:24:49,536 INFO L290 TraceCheckUtils]: 150: Hoare triple {86249#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {86249#false} is VALID [2022-02-21 04:24:49,536 INFO L290 TraceCheckUtils]: 151: Hoare triple {86249#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {86249#false} is VALID [2022-02-21 04:24:49,536 INFO L290 TraceCheckUtils]: 152: Hoare triple {86249#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {86249#false} is VALID [2022-02-21 04:24:49,536 INFO L290 TraceCheckUtils]: 153: Hoare triple {86249#false} assume !(0 == start_simulation_~tmp~3#1); {86249#false} is VALID [2022-02-21 04:24:49,536 INFO L290 TraceCheckUtils]: 154: Hoare triple {86249#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {86249#false} is VALID [2022-02-21 04:24:49,536 INFO L290 TraceCheckUtils]: 155: Hoare triple {86249#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {86249#false} is VALID [2022-02-21 04:24:49,536 INFO L290 TraceCheckUtils]: 156: Hoare triple {86249#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {86249#false} is VALID [2022-02-21 04:24:49,537 INFO L290 TraceCheckUtils]: 157: Hoare triple {86249#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {86249#false} is VALID [2022-02-21 04:24:49,537 INFO L290 TraceCheckUtils]: 158: Hoare triple {86249#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {86249#false} is VALID [2022-02-21 04:24:49,537 INFO L290 TraceCheckUtils]: 159: Hoare triple {86249#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {86249#false} is VALID [2022-02-21 04:24:49,537 INFO L290 TraceCheckUtils]: 160: Hoare triple {86249#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {86249#false} is VALID [2022-02-21 04:24:49,537 INFO L290 TraceCheckUtils]: 161: Hoare triple {86249#false} assume !(0 != start_simulation_~tmp___0~1#1); {86249#false} is VALID [2022-02-21 04:24:49,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:49,538 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:49,538 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685607461] [2022-02-21 04:24:49,538 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685607461] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:49,538 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:49,538 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:49,538 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [868690487] [2022-02-21 04:24:49,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:49,539 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:49,539 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:49,539 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:49,539 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:49,539 INFO L87 Difference]: Start difference. First operand 1914 states and 2825 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:50,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:50,854 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2022-02-21 04:24:50,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:50,854 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:50,946 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:50,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:51,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:51,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-02-21 04:24:51,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:51,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:51,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:51,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:51,103 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-02-21 04:24:51,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:51,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:51,117 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:51,118 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2824 transitions. Second operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,119 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2824 transitions. Second operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,120 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. Second operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:51,193 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2022-02-21 04:24:51,193 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:51,195 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:51,195 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:51,196 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2824 transitions. [2022-02-21 04:24:51,197 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2824 transitions. [2022-02-21 04:24:51,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:51,272 INFO L93 Difference]: Finished difference Result 1914 states and 2824 transitions. [2022-02-21 04:24:51,272 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:51,273 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:51,274 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:51,274 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:51,274 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:51,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.4754440961337514) internal successors, (2824), 1913 states have internal predecessors, (2824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:51,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2824 transitions. [2022-02-21 04:24:51,350 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-02-21 04:24:51,350 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2824 transitions. [2022-02-21 04:24:51,350 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:24:51,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2824 transitions. [2022-02-21 04:24:51,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:51,353 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:51,353 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:51,355 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:51,355 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:51,355 INFO L791 eck$LassoCheckResult]: Stem: 89026#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 89027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 88846#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88562#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 88563#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 89739#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89740#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88698#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88699#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89153#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 88988#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 88989#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 88765#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 88766#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 89164#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 89341#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 89495#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 89532#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 88776#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88777#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 89952#L1258-2 assume !(0 == ~T1_E~0); 89071#L1263-1 assume !(0 == ~T2_E~0); 89072#L1268-1 assume !(0 == ~T3_E~0); 89375#L1273-1 assume !(0 == ~T4_E~0); 89934#L1278-1 assume !(0 == ~T5_E~0); 89795#L1283-1 assume !(0 == ~T6_E~0); 89796#L1288-1 assume !(0 == ~T7_E~0); 90032#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 90020#L1298-1 assume !(0 == ~T9_E~0); 89946#L1303-1 assume !(0 == ~T10_E~0); 88591#L1308-1 assume !(0 == ~T11_E~0); 88533#L1313-1 assume !(0 == ~T12_E~0); 88534#L1318-1 assume !(0 == ~T13_E~0); 88540#L1323-1 assume !(0 == ~E_1~0); 88541#L1328-1 assume !(0 == ~E_2~0); 88708#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 89667#L1338-1 assume !(0 == ~E_4~0); 89668#L1343-1 assume !(0 == ~E_5~0); 89769#L1348-1 assume !(0 == ~E_6~0); 90055#L1353-1 assume !(0 == ~E_7~0); 89394#L1358-1 assume !(0 == ~E_8~0); 89395#L1363-1 assume !(0 == ~E_9~0); 89685#L1368-1 assume !(0 == ~E_10~0); 88370#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 88371#L1378-1 assume !(0 == ~E_12~0); 88657#L1383-1 assume !(0 == ~E_13~0); 88658#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89401#L607 assume 1 == ~m_pc~0; 89402#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 88728#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89767#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 89321#L1560 assume !(0 != activate_threads_~tmp~1#1); 89322#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88553#L626 assume !(1 == ~t1_pc~0); 88554#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88822#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88823#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88992#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 88453#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88454#L645 assume 1 == ~t2_pc~0; 88570#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 88527#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89204#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 89205#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 89297#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 89298#L664 assume 1 == ~t3_pc~0; 90054#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 88294#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88295#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 88953#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 88954#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89962#L683 assume !(1 == ~t4_pc~0); 89517#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 89469#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89470#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89504#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89628#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89247#L702 assume 1 == ~t5_pc~0; 89248#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 89173#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89623#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89921#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 89862#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88342#L721 assume !(1 == ~t6_pc~0); 88316#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 88317#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88480#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 88962#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 88963#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 89564#L740 assume 1 == ~t7_pc~0; 88391#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 88204#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 88205#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 88194#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 88195#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 88898#L759 assume !(1 == ~t8_pc~0); 88899#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 88928#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89621#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 89622#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 89753#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 90031#L778 assume 1 == ~t9_pc~0; 89918#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 88369#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 88309#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 88238#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 88239#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 88566#L797 assume !(1 == ~t10_pc~0); 88567#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 88685#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 89819#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 89069#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 89070#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 89359#L816 assume 1 == ~t11_pc~0; 88274#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 88275#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 89030#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 88969#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 88970#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 89494#L835 assume 1 == ~t12_pc~0; 89372#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 88438#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 88460#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 88601#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 89126#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 89127#L854 assume !(1 == ~t13_pc~0); 88767#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 88768#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 88818#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 88478#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 88479#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89858#L1401 assume !(1 == ~M_E~0); 88957#L1401-2 assume !(1 == ~T1_E~0); 88958#L1406-1 assume !(1 == ~T2_E~0); 89553#L1411-1 assume !(1 == ~T3_E~0); 89554#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89220#L1421-1 assume !(1 == ~T5_E~0); 88763#L1426-1 assume !(1 == ~T6_E~0); 88764#L1431-1 assume !(1 == ~T7_E~0); 88312#L1436-1 assume !(1 == ~T8_E~0); 88313#L1441-1 assume !(1 == ~T9_E~0); 89060#L1446-1 assume !(1 == ~T10_E~0); 89061#L1451-1 assume !(1 == ~T11_E~0); 89766#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 89420#L1461-1 assume !(1 == ~T13_E~0); 88981#L1466-1 assume !(1 == ~E_1~0); 88982#L1471-1 assume !(1 == ~E_2~0); 89751#L1476-1 assume !(1 == ~E_3~0); 89752#L1481-1 assume !(1 == ~E_4~0); 89900#L1486-1 assume !(1 == ~E_5~0); 88606#L1491-1 assume !(1 == ~E_6~0); 88246#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 88247#L1501-1 assume !(1 == ~E_8~0); 89058#L1506-1 assume !(1 == ~E_9~0); 89059#L1511-1 assume !(1 == ~E_10~0); 89015#L1516-1 assume !(1 == ~E_11~0); 88190#L1521-1 assume !(1 == ~E_12~0); 88191#L1526-1 assume !(1 == ~E_13~0); 88245#L1531-1 assume { :end_inline_reset_delta_events } true; 88788#L1892-2 [2022-02-21 04:24:51,356 INFO L793 eck$LassoCheckResult]: Loop: 88788#L1892-2 assume !false; 89811#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 90009#L1233 assume !false; 89992#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89324#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 89304#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89462#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 88288#L1046 assume !(0 != eval_~tmp~0#1); 88290#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88324#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 89496#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 90053#L1258-5 assume !(0 == ~T1_E~0); 88466#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88467#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 90045#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 90051#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 90052#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88690#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88691#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 89808#L1298-3 assume !(0 == ~T9_E~0); 89809#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 89968#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 89807#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 89308#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 88468#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 88469#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 89892#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88611#L1338-3 assume !(0 == ~E_4~0); 88612#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 89724#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 89897#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 89898#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 89264#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 88824#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 88825#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 89581#L1378-3 assume !(0 == ~E_12~0); 89582#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 89763#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89764#L607-42 assume 1 == ~m_pc~0; 89377#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 89105#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 89106#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88838#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88839#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89360#L626-42 assume 1 == ~t1_pc~0; 88922#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 88923#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 89227#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 89228#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88502#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88503#L645-42 assume !(1 == ~t2_pc~0); 89702#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 89703#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 89868#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 88709#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88216#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88217#L664-42 assume !(1 == ~t3_pc~0); 88743#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 88744#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89995#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 89530#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89531#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89696#L683-42 assume 1 == ~t4_pc~0; 90061#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 89405#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89537#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 89957#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89958#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 89802#L702-42 assume !(1 == ~t5_pc~0); 88914#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 88915#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89211#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 89884#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88232#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88233#L721-42 assume !(1 == ~t6_pc~0); 88387#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 88406#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88870#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 90037#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 89042#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 88888#L740-42 assume !(1 == ~t7_pc~0); 88625#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 88626#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89167#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 89022#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 89023#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89296#L759-42 assume 1 == ~t8_pc~0; 89145#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 89077#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89078#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 89156#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 89157#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89252#L778-42 assume 1 == ~t9_pc~0; 89089#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 89091#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89501#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 89406#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 89407#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 89464#L797-42 assume 1 == ~t10_pc~0; 88631#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 88632#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 89633#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 89942#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 89502#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 89503#L816-42 assume 1 == ~t11_pc~0; 88180#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 88181#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 88723#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 88724#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 88803#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 88804#L835-42 assume 1 == ~t12_pc~0; 89208#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 89101#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 88778#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 88779#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 89861#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 89645#L854-42 assume !(1 == ~t13_pc~0); 88721#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 88722#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 88332#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 88333#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 88979#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88980#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 89758#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88569#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88433#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88434#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89033#L1421-3 assume !(1 == ~T5_E~0); 89034#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 88609#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 88610#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 88196#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 88197#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 89786#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 89117#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 88770#L1461-3 assume !(1 == ~T13_E~0); 88771#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 90048#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 88710#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 88711#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89111#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88738#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 88739#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 89151#L1501-3 assume !(1 == ~E_8~0); 89152#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 89578#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 89568#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 89569#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 89268#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 89269#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89663#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 88545#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89438#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 89079#L1911 assume !(0 == start_simulation_~tmp~3#1); 89080#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 89602#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 88669#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 89540#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 88374#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88375#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88604#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 88605#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 88788#L1892-2 [2022-02-21 04:24:51,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:51,356 INFO L85 PathProgramCache]: Analyzing trace with hash 855086876, now seen corresponding path program 1 times [2022-02-21 04:24:51,357 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:51,357 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723805868] [2022-02-21 04:24:51,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:51,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:51,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:51,387 INFO L290 TraceCheckUtils]: 0: Hoare triple {93910#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {93910#true} is VALID [2022-02-21 04:24:51,387 INFO L290 TraceCheckUtils]: 1: Hoare triple {93910#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,387 INFO L290 TraceCheckUtils]: 2: Hoare triple {93912#(= ~t13_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,388 INFO L290 TraceCheckUtils]: 3: Hoare triple {93912#(= ~t13_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,388 INFO L290 TraceCheckUtils]: 4: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,388 INFO L290 TraceCheckUtils]: 5: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,389 INFO L290 TraceCheckUtils]: 6: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,389 INFO L290 TraceCheckUtils]: 7: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,389 INFO L290 TraceCheckUtils]: 8: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,390 INFO L290 TraceCheckUtils]: 9: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,390 INFO L290 TraceCheckUtils]: 10: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,390 INFO L290 TraceCheckUtils]: 11: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,390 INFO L290 TraceCheckUtils]: 12: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,391 INFO L290 TraceCheckUtils]: 13: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,391 INFO L290 TraceCheckUtils]: 14: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,391 INFO L290 TraceCheckUtils]: 15: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,392 INFO L290 TraceCheckUtils]: 16: Hoare triple {93912#(= ~t13_i~0 1)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {93912#(= ~t13_i~0 1)} is VALID [2022-02-21 04:24:51,392 INFO L290 TraceCheckUtils]: 17: Hoare triple {93912#(= ~t13_i~0 1)} assume !(1 == ~t13_i~0);~t13_st~0 := 2; {93911#false} is VALID [2022-02-21 04:24:51,392 INFO L290 TraceCheckUtils]: 18: Hoare triple {93911#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {93911#false} is VALID [2022-02-21 04:24:51,392 INFO L290 TraceCheckUtils]: 19: Hoare triple {93911#false} assume 0 == ~M_E~0;~M_E~0 := 1; {93911#false} is VALID [2022-02-21 04:24:51,392 INFO L290 TraceCheckUtils]: 20: Hoare triple {93911#false} assume !(0 == ~T1_E~0); {93911#false} is VALID [2022-02-21 04:24:51,392 INFO L290 TraceCheckUtils]: 21: Hoare triple {93911#false} assume !(0 == ~T2_E~0); {93911#false} is VALID [2022-02-21 04:24:51,392 INFO L290 TraceCheckUtils]: 22: Hoare triple {93911#false} assume !(0 == ~T3_E~0); {93911#false} is VALID [2022-02-21 04:24:51,392 INFO L290 TraceCheckUtils]: 23: Hoare triple {93911#false} assume !(0 == ~T4_E~0); {93911#false} is VALID [2022-02-21 04:24:51,392 INFO L290 TraceCheckUtils]: 24: Hoare triple {93911#false} assume !(0 == ~T5_E~0); {93911#false} is VALID [2022-02-21 04:24:51,392 INFO L290 TraceCheckUtils]: 25: Hoare triple {93911#false} assume !(0 == ~T6_E~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 26: Hoare triple {93911#false} assume !(0 == ~T7_E~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 27: Hoare triple {93911#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 28: Hoare triple {93911#false} assume !(0 == ~T9_E~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 29: Hoare triple {93911#false} assume !(0 == ~T10_E~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 30: Hoare triple {93911#false} assume !(0 == ~T11_E~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 31: Hoare triple {93911#false} assume !(0 == ~T12_E~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 32: Hoare triple {93911#false} assume !(0 == ~T13_E~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 33: Hoare triple {93911#false} assume !(0 == ~E_1~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 34: Hoare triple {93911#false} assume !(0 == ~E_2~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 35: Hoare triple {93911#false} assume 0 == ~E_3~0;~E_3~0 := 1; {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 36: Hoare triple {93911#false} assume !(0 == ~E_4~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 37: Hoare triple {93911#false} assume !(0 == ~E_5~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 38: Hoare triple {93911#false} assume !(0 == ~E_6~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 39: Hoare triple {93911#false} assume !(0 == ~E_7~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 40: Hoare triple {93911#false} assume !(0 == ~E_8~0); {93911#false} is VALID [2022-02-21 04:24:51,393 INFO L290 TraceCheckUtils]: 41: Hoare triple {93911#false} assume !(0 == ~E_9~0); {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 42: Hoare triple {93911#false} assume !(0 == ~E_10~0); {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 43: Hoare triple {93911#false} assume 0 == ~E_11~0;~E_11~0 := 1; {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 44: Hoare triple {93911#false} assume !(0 == ~E_12~0); {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 45: Hoare triple {93911#false} assume !(0 == ~E_13~0); {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 46: Hoare triple {93911#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 47: Hoare triple {93911#false} assume 1 == ~m_pc~0; {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 48: Hoare triple {93911#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 49: Hoare triple {93911#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 50: Hoare triple {93911#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 51: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp~1#1); {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 52: Hoare triple {93911#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 53: Hoare triple {93911#false} assume !(1 == ~t1_pc~0); {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 54: Hoare triple {93911#false} is_transmit1_triggered_~__retres1~1#1 := 0; {93911#false} is VALID [2022-02-21 04:24:51,394 INFO L290 TraceCheckUtils]: 55: Hoare triple {93911#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 56: Hoare triple {93911#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 57: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp___0~0#1); {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 58: Hoare triple {93911#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 59: Hoare triple {93911#false} assume 1 == ~t2_pc~0; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 60: Hoare triple {93911#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 61: Hoare triple {93911#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 62: Hoare triple {93911#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 63: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp___1~0#1); {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 64: Hoare triple {93911#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 65: Hoare triple {93911#false} assume 1 == ~t3_pc~0; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 66: Hoare triple {93911#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 67: Hoare triple {93911#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 68: Hoare triple {93911#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 69: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp___2~0#1); {93911#false} is VALID [2022-02-21 04:24:51,395 INFO L290 TraceCheckUtils]: 70: Hoare triple {93911#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 71: Hoare triple {93911#false} assume !(1 == ~t4_pc~0); {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 72: Hoare triple {93911#false} is_transmit4_triggered_~__retres1~4#1 := 0; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 73: Hoare triple {93911#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 74: Hoare triple {93911#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 75: Hoare triple {93911#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 76: Hoare triple {93911#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 77: Hoare triple {93911#false} assume 1 == ~t5_pc~0; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 78: Hoare triple {93911#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 79: Hoare triple {93911#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 80: Hoare triple {93911#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 81: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp___4~0#1); {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 82: Hoare triple {93911#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 83: Hoare triple {93911#false} assume !(1 == ~t6_pc~0); {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 84: Hoare triple {93911#false} is_transmit6_triggered_~__retres1~6#1 := 0; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 85: Hoare triple {93911#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {93911#false} is VALID [2022-02-21 04:24:51,396 INFO L290 TraceCheckUtils]: 86: Hoare triple {93911#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 87: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp___5~0#1); {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 88: Hoare triple {93911#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 89: Hoare triple {93911#false} assume 1 == ~t7_pc~0; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 90: Hoare triple {93911#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 91: Hoare triple {93911#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 92: Hoare triple {93911#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 93: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp___6~0#1); {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 94: Hoare triple {93911#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 95: Hoare triple {93911#false} assume !(1 == ~t8_pc~0); {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 96: Hoare triple {93911#false} is_transmit8_triggered_~__retres1~8#1 := 0; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 97: Hoare triple {93911#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 98: Hoare triple {93911#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 99: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp___7~0#1); {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 100: Hoare triple {93911#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 101: Hoare triple {93911#false} assume 1 == ~t9_pc~0; {93911#false} is VALID [2022-02-21 04:24:51,397 INFO L290 TraceCheckUtils]: 102: Hoare triple {93911#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 103: Hoare triple {93911#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 104: Hoare triple {93911#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 105: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp___8~0#1); {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 106: Hoare triple {93911#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 107: Hoare triple {93911#false} assume !(1 == ~t10_pc~0); {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 108: Hoare triple {93911#false} is_transmit10_triggered_~__retres1~10#1 := 0; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 109: Hoare triple {93911#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 110: Hoare triple {93911#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 111: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp___9~0#1); {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 112: Hoare triple {93911#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 113: Hoare triple {93911#false} assume 1 == ~t11_pc~0; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 114: Hoare triple {93911#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 115: Hoare triple {93911#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 116: Hoare triple {93911#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 117: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp___10~0#1); {93911#false} is VALID [2022-02-21 04:24:51,398 INFO L290 TraceCheckUtils]: 118: Hoare triple {93911#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 119: Hoare triple {93911#false} assume 1 == ~t12_pc~0; {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 120: Hoare triple {93911#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 121: Hoare triple {93911#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 122: Hoare triple {93911#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 123: Hoare triple {93911#false} assume !(0 != activate_threads_~tmp___11~0#1); {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 124: Hoare triple {93911#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 125: Hoare triple {93911#false} assume !(1 == ~t13_pc~0); {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 126: Hoare triple {93911#false} is_transmit13_triggered_~__retres1~13#1 := 0; {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 127: Hoare triple {93911#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 128: Hoare triple {93911#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 129: Hoare triple {93911#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {93911#false} is VALID [2022-02-21 04:24:51,399 INFO L290 TraceCheckUtils]: 130: Hoare triple {93911#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {93911#false} is VALID [2022-02-21 04:24:51,400 INFO L290 TraceCheckUtils]: 131: Hoare triple {93911#false} assume !(1 == ~M_E~0); {93911#false} is VALID [2022-02-21 04:24:51,400 INFO L290 TraceCheckUtils]: 132: Hoare triple {93911#false} assume !(1 == ~T1_E~0); {93911#false} is VALID [2022-02-21 04:24:51,400 INFO L290 TraceCheckUtils]: 133: Hoare triple {93911#false} assume !(1 == ~T2_E~0); {93911#false} is VALID [2022-02-21 04:24:51,400 INFO L290 TraceCheckUtils]: 134: Hoare triple {93911#false} assume !(1 == ~T3_E~0); {93911#false} is VALID [2022-02-21 04:24:51,400 INFO L290 TraceCheckUtils]: 135: Hoare triple {93911#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {93911#false} is VALID [2022-02-21 04:24:51,400 INFO L290 TraceCheckUtils]: 136: Hoare triple {93911#false} assume !(1 == ~T5_E~0); {93911#false} is VALID [2022-02-21 04:24:51,400 INFO L290 TraceCheckUtils]: 137: Hoare triple {93911#false} assume !(1 == ~T6_E~0); {93911#false} is VALID [2022-02-21 04:24:51,400 INFO L290 TraceCheckUtils]: 138: Hoare triple {93911#false} assume !(1 == ~T7_E~0); {93911#false} is VALID [2022-02-21 04:24:51,400 INFO L290 TraceCheckUtils]: 139: Hoare triple {93911#false} assume !(1 == ~T8_E~0); {93911#false} is VALID [2022-02-21 04:24:51,400 INFO L290 TraceCheckUtils]: 140: Hoare triple {93911#false} assume !(1 == ~T9_E~0); {93911#false} is VALID [2022-02-21 04:24:51,401 INFO L290 TraceCheckUtils]: 141: Hoare triple {93911#false} assume !(1 == ~T10_E~0); {93911#false} is VALID [2022-02-21 04:24:51,401 INFO L290 TraceCheckUtils]: 142: Hoare triple {93911#false} assume !(1 == ~T11_E~0); {93911#false} is VALID [2022-02-21 04:24:51,401 INFO L290 TraceCheckUtils]: 143: Hoare triple {93911#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {93911#false} is VALID [2022-02-21 04:24:51,401 INFO L290 TraceCheckUtils]: 144: Hoare triple {93911#false} assume !(1 == ~T13_E~0); {93911#false} is VALID [2022-02-21 04:24:51,401 INFO L290 TraceCheckUtils]: 145: Hoare triple {93911#false} assume !(1 == ~E_1~0); {93911#false} is VALID [2022-02-21 04:24:51,401 INFO L290 TraceCheckUtils]: 146: Hoare triple {93911#false} assume !(1 == ~E_2~0); {93911#false} is VALID [2022-02-21 04:24:51,401 INFO L290 TraceCheckUtils]: 147: Hoare triple {93911#false} assume !(1 == ~E_3~0); {93911#false} is VALID [2022-02-21 04:24:51,401 INFO L290 TraceCheckUtils]: 148: Hoare triple {93911#false} assume !(1 == ~E_4~0); {93911#false} is VALID [2022-02-21 04:24:51,401 INFO L290 TraceCheckUtils]: 149: Hoare triple {93911#false} assume !(1 == ~E_5~0); {93911#false} is VALID [2022-02-21 04:24:51,401 INFO L290 TraceCheckUtils]: 150: Hoare triple {93911#false} assume !(1 == ~E_6~0); {93911#false} is VALID [2022-02-21 04:24:51,402 INFO L290 TraceCheckUtils]: 151: Hoare triple {93911#false} assume 1 == ~E_7~0;~E_7~0 := 2; {93911#false} is VALID [2022-02-21 04:24:51,402 INFO L290 TraceCheckUtils]: 152: Hoare triple {93911#false} assume !(1 == ~E_8~0); {93911#false} is VALID [2022-02-21 04:24:51,402 INFO L290 TraceCheckUtils]: 153: Hoare triple {93911#false} assume !(1 == ~E_9~0); {93911#false} is VALID [2022-02-21 04:24:51,402 INFO L290 TraceCheckUtils]: 154: Hoare triple {93911#false} assume !(1 == ~E_10~0); {93911#false} is VALID [2022-02-21 04:24:51,402 INFO L290 TraceCheckUtils]: 155: Hoare triple {93911#false} assume !(1 == ~E_11~0); {93911#false} is VALID [2022-02-21 04:24:51,402 INFO L290 TraceCheckUtils]: 156: Hoare triple {93911#false} assume !(1 == ~E_12~0); {93911#false} is VALID [2022-02-21 04:24:51,402 INFO L290 TraceCheckUtils]: 157: Hoare triple {93911#false} assume !(1 == ~E_13~0); {93911#false} is VALID [2022-02-21 04:24:51,402 INFO L290 TraceCheckUtils]: 158: Hoare triple {93911#false} assume { :end_inline_reset_delta_events } true; {93911#false} is VALID [2022-02-21 04:24:51,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:51,403 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:51,403 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [723805868] [2022-02-21 04:24:51,403 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [723805868] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:51,403 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:51,403 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:51,403 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [363802627] [2022-02-21 04:24:51,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:51,404 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:51,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:51,405 INFO L85 PathProgramCache]: Analyzing trace with hash -1921140675, now seen corresponding path program 1 times [2022-02-21 04:24:51,405 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:51,405 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987243480] [2022-02-21 04:24:51,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:51,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:51,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:51,442 INFO L290 TraceCheckUtils]: 0: Hoare triple {93913#true} assume !false; {93913#true} is VALID [2022-02-21 04:24:51,443 INFO L290 TraceCheckUtils]: 1: Hoare triple {93913#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {93913#true} is VALID [2022-02-21 04:24:51,443 INFO L290 TraceCheckUtils]: 2: Hoare triple {93913#true} assume !false; {93913#true} is VALID [2022-02-21 04:24:51,443 INFO L290 TraceCheckUtils]: 3: Hoare triple {93913#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {93913#true} is VALID [2022-02-21 04:24:51,443 INFO L290 TraceCheckUtils]: 4: Hoare triple {93913#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {93913#true} is VALID [2022-02-21 04:24:51,443 INFO L290 TraceCheckUtils]: 5: Hoare triple {93913#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {93913#true} is VALID [2022-02-21 04:24:51,444 INFO L290 TraceCheckUtils]: 6: Hoare triple {93913#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {93913#true} is VALID [2022-02-21 04:24:51,444 INFO L290 TraceCheckUtils]: 7: Hoare triple {93913#true} assume !(0 != eval_~tmp~0#1); {93913#true} is VALID [2022-02-21 04:24:51,444 INFO L290 TraceCheckUtils]: 8: Hoare triple {93913#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {93913#true} is VALID [2022-02-21 04:24:51,444 INFO L290 TraceCheckUtils]: 9: Hoare triple {93913#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {93913#true} is VALID [2022-02-21 04:24:51,444 INFO L290 TraceCheckUtils]: 10: Hoare triple {93913#true} assume 0 == ~M_E~0;~M_E~0 := 1; {93913#true} is VALID [2022-02-21 04:24:51,444 INFO L290 TraceCheckUtils]: 11: Hoare triple {93913#true} assume !(0 == ~T1_E~0); {93913#true} is VALID [2022-02-21 04:24:51,444 INFO L290 TraceCheckUtils]: 12: Hoare triple {93913#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {93913#true} is VALID [2022-02-21 04:24:51,445 INFO L290 TraceCheckUtils]: 13: Hoare triple {93913#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {93913#true} is VALID [2022-02-21 04:24:51,445 INFO L290 TraceCheckUtils]: 14: Hoare triple {93913#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {93913#true} is VALID [2022-02-21 04:24:51,445 INFO L290 TraceCheckUtils]: 15: Hoare triple {93913#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,445 INFO L290 TraceCheckUtils]: 16: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,446 INFO L290 TraceCheckUtils]: 17: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,446 INFO L290 TraceCheckUtils]: 18: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,447 INFO L290 TraceCheckUtils]: 19: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,447 INFO L290 TraceCheckUtils]: 20: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,447 INFO L290 TraceCheckUtils]: 21: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,448 INFO L290 TraceCheckUtils]: 22: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,448 INFO L290 TraceCheckUtils]: 23: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,448 INFO L290 TraceCheckUtils]: 24: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,449 INFO L290 TraceCheckUtils]: 25: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,449 INFO L290 TraceCheckUtils]: 26: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,449 INFO L290 TraceCheckUtils]: 27: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,450 INFO L290 TraceCheckUtils]: 28: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,450 INFO L290 TraceCheckUtils]: 29: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,451 INFO L290 TraceCheckUtils]: 30: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,451 INFO L290 TraceCheckUtils]: 31: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,451 INFO L290 TraceCheckUtils]: 32: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,452 INFO L290 TraceCheckUtils]: 33: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,452 INFO L290 TraceCheckUtils]: 34: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,452 INFO L290 TraceCheckUtils]: 35: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,453 INFO L290 TraceCheckUtils]: 36: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,453 INFO L290 TraceCheckUtils]: 37: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,453 INFO L290 TraceCheckUtils]: 38: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~m_pc~0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,454 INFO L290 TraceCheckUtils]: 39: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,454 INFO L290 TraceCheckUtils]: 40: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,455 INFO L290 TraceCheckUtils]: 41: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,455 INFO L290 TraceCheckUtils]: 42: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,455 INFO L290 TraceCheckUtils]: 43: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,456 INFO L290 TraceCheckUtils]: 44: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,456 INFO L290 TraceCheckUtils]: 45: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,456 INFO L290 TraceCheckUtils]: 46: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,457 INFO L290 TraceCheckUtils]: 47: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,457 INFO L290 TraceCheckUtils]: 48: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,457 INFO L290 TraceCheckUtils]: 49: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,458 INFO L290 TraceCheckUtils]: 50: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,458 INFO L290 TraceCheckUtils]: 51: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,459 INFO L290 TraceCheckUtils]: 52: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,459 INFO L290 TraceCheckUtils]: 53: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,459 INFO L290 TraceCheckUtils]: 54: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,460 INFO L290 TraceCheckUtils]: 55: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,460 INFO L290 TraceCheckUtils]: 56: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,460 INFO L290 TraceCheckUtils]: 57: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,461 INFO L290 TraceCheckUtils]: 58: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,461 INFO L290 TraceCheckUtils]: 59: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,461 INFO L290 TraceCheckUtils]: 60: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,462 INFO L290 TraceCheckUtils]: 61: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,462 INFO L290 TraceCheckUtils]: 62: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,463 INFO L290 TraceCheckUtils]: 63: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,463 INFO L290 TraceCheckUtils]: 64: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,463 INFO L290 TraceCheckUtils]: 65: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,464 INFO L290 TraceCheckUtils]: 66: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,464 INFO L290 TraceCheckUtils]: 67: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,464 INFO L290 TraceCheckUtils]: 68: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,465 INFO L290 TraceCheckUtils]: 69: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,465 INFO L290 TraceCheckUtils]: 70: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,465 INFO L290 TraceCheckUtils]: 71: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,466 INFO L290 TraceCheckUtils]: 72: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,466 INFO L290 TraceCheckUtils]: 73: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 74: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 75: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,467 INFO L290 TraceCheckUtils]: 76: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 77: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 78: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,468 INFO L290 TraceCheckUtils]: 79: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,469 INFO L290 TraceCheckUtils]: 80: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t7_pc~0); {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,469 INFO L290 TraceCheckUtils]: 81: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 82: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 83: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,470 INFO L290 TraceCheckUtils]: 84: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,471 INFO L290 TraceCheckUtils]: 85: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,471 INFO L290 TraceCheckUtils]: 86: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,475 INFO L290 TraceCheckUtils]: 87: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,476 INFO L290 TraceCheckUtils]: 88: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,476 INFO L290 TraceCheckUtils]: 89: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,477 INFO L290 TraceCheckUtils]: 90: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,477 INFO L290 TraceCheckUtils]: 91: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 92: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t9_pc~0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 93: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,478 INFO L290 TraceCheckUtils]: 94: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,479 INFO L290 TraceCheckUtils]: 95: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,479 INFO L290 TraceCheckUtils]: 96: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,479 INFO L290 TraceCheckUtils]: 97: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,480 INFO L290 TraceCheckUtils]: 98: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,480 INFO L290 TraceCheckUtils]: 99: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,481 INFO L290 TraceCheckUtils]: 100: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,481 INFO L290 TraceCheckUtils]: 101: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,481 INFO L290 TraceCheckUtils]: 102: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,482 INFO L290 TraceCheckUtils]: 103: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,482 INFO L290 TraceCheckUtils]: 104: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,483 INFO L290 TraceCheckUtils]: 105: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,483 INFO L290 TraceCheckUtils]: 106: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,483 INFO L290 TraceCheckUtils]: 107: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,484 INFO L290 TraceCheckUtils]: 108: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,484 INFO L290 TraceCheckUtils]: 109: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,484 INFO L290 TraceCheckUtils]: 110: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,485 INFO L290 TraceCheckUtils]: 111: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,485 INFO L290 TraceCheckUtils]: 112: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,486 INFO L290 TraceCheckUtils]: 113: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,486 INFO L290 TraceCheckUtils]: 114: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,486 INFO L290 TraceCheckUtils]: 115: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,487 INFO L290 TraceCheckUtils]: 116: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,487 INFO L290 TraceCheckUtils]: 117: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,487 INFO L290 TraceCheckUtils]: 118: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,488 INFO L290 TraceCheckUtils]: 119: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,488 INFO L290 TraceCheckUtils]: 120: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,489 INFO L290 TraceCheckUtils]: 121: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,489 INFO L290 TraceCheckUtils]: 122: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,489 INFO L290 TraceCheckUtils]: 123: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,490 INFO L290 TraceCheckUtils]: 124: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,490 INFO L290 TraceCheckUtils]: 125: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,490 INFO L290 TraceCheckUtils]: 126: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {93915#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:51,491 INFO L290 TraceCheckUtils]: 127: Hoare triple {93915#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {93914#false} is VALID [2022-02-21 04:24:51,491 INFO L290 TraceCheckUtils]: 128: Hoare triple {93914#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,491 INFO L290 TraceCheckUtils]: 129: Hoare triple {93914#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,491 INFO L290 TraceCheckUtils]: 130: Hoare triple {93914#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,491 INFO L290 TraceCheckUtils]: 131: Hoare triple {93914#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,492 INFO L290 TraceCheckUtils]: 132: Hoare triple {93914#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,492 INFO L290 TraceCheckUtils]: 133: Hoare triple {93914#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,492 INFO L290 TraceCheckUtils]: 134: Hoare triple {93914#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,492 INFO L290 TraceCheckUtils]: 135: Hoare triple {93914#false} assume !(1 == ~T13_E~0); {93914#false} is VALID [2022-02-21 04:24:51,492 INFO L290 TraceCheckUtils]: 136: Hoare triple {93914#false} assume 1 == ~E_1~0;~E_1~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,492 INFO L290 TraceCheckUtils]: 137: Hoare triple {93914#false} assume 1 == ~E_2~0;~E_2~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,492 INFO L290 TraceCheckUtils]: 138: Hoare triple {93914#false} assume 1 == ~E_3~0;~E_3~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,492 INFO L290 TraceCheckUtils]: 139: Hoare triple {93914#false} assume 1 == ~E_4~0;~E_4~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,493 INFO L290 TraceCheckUtils]: 140: Hoare triple {93914#false} assume 1 == ~E_5~0;~E_5~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,493 INFO L290 TraceCheckUtils]: 141: Hoare triple {93914#false} assume 1 == ~E_6~0;~E_6~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,493 INFO L290 TraceCheckUtils]: 142: Hoare triple {93914#false} assume 1 == ~E_7~0;~E_7~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,493 INFO L290 TraceCheckUtils]: 143: Hoare triple {93914#false} assume !(1 == ~E_8~0); {93914#false} is VALID [2022-02-21 04:24:51,493 INFO L290 TraceCheckUtils]: 144: Hoare triple {93914#false} assume 1 == ~E_9~0;~E_9~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,493 INFO L290 TraceCheckUtils]: 145: Hoare triple {93914#false} assume 1 == ~E_10~0;~E_10~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,493 INFO L290 TraceCheckUtils]: 146: Hoare triple {93914#false} assume 1 == ~E_11~0;~E_11~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,494 INFO L290 TraceCheckUtils]: 147: Hoare triple {93914#false} assume 1 == ~E_12~0;~E_12~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,494 INFO L290 TraceCheckUtils]: 148: Hoare triple {93914#false} assume 1 == ~E_13~0;~E_13~0 := 2; {93914#false} is VALID [2022-02-21 04:24:51,494 INFO L290 TraceCheckUtils]: 149: Hoare triple {93914#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {93914#false} is VALID [2022-02-21 04:24:51,494 INFO L290 TraceCheckUtils]: 150: Hoare triple {93914#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {93914#false} is VALID [2022-02-21 04:24:51,494 INFO L290 TraceCheckUtils]: 151: Hoare triple {93914#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {93914#false} is VALID [2022-02-21 04:24:51,494 INFO L290 TraceCheckUtils]: 152: Hoare triple {93914#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {93914#false} is VALID [2022-02-21 04:24:51,494 INFO L290 TraceCheckUtils]: 153: Hoare triple {93914#false} assume !(0 == start_simulation_~tmp~3#1); {93914#false} is VALID [2022-02-21 04:24:51,495 INFO L290 TraceCheckUtils]: 154: Hoare triple {93914#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {93914#false} is VALID [2022-02-21 04:24:51,495 INFO L290 TraceCheckUtils]: 155: Hoare triple {93914#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {93914#false} is VALID [2022-02-21 04:24:51,495 INFO L290 TraceCheckUtils]: 156: Hoare triple {93914#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {93914#false} is VALID [2022-02-21 04:24:51,495 INFO L290 TraceCheckUtils]: 157: Hoare triple {93914#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {93914#false} is VALID [2022-02-21 04:24:51,495 INFO L290 TraceCheckUtils]: 158: Hoare triple {93914#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {93914#false} is VALID [2022-02-21 04:24:51,495 INFO L290 TraceCheckUtils]: 159: Hoare triple {93914#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {93914#false} is VALID [2022-02-21 04:24:51,495 INFO L290 TraceCheckUtils]: 160: Hoare triple {93914#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {93914#false} is VALID [2022-02-21 04:24:51,496 INFO L290 TraceCheckUtils]: 161: Hoare triple {93914#false} assume !(0 != start_simulation_~tmp___0~1#1); {93914#false} is VALID [2022-02-21 04:24:51,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:51,496 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:51,496 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987243480] [2022-02-21 04:24:51,497 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [987243480] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:51,497 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:51,497 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:51,497 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1592322727] [2022-02-21 04:24:51,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:51,498 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:51,498 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:51,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:51,499 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:51,499 INFO L87 Difference]: Start difference. First operand 1914 states and 2824 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:52,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:52,817 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2022-02-21 04:24:52,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:52,817 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:52,915 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:52,916 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:52,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:53,071 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-02-21 04:24:53,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1914 [2022-02-21 04:24:53,072 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1914 [2022-02-21 04:24:53,073 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:53,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:53,074 INFO L681 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-02-21 04:24:53,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:53,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1914 to 1914. [2022-02-21 04:24:53,090 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:53,092 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1914 states and 2823 transitions. Second operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:53,093 INFO L74 IsIncluded]: Start isIncluded. First operand 1914 states and 2823 transitions. Second operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:53,095 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. Second operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:53,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:53,183 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2022-02-21 04:24:53,183 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:53,184 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:53,184 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:53,186 INFO L74 IsIncluded]: Start isIncluded. First operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2823 transitions. [2022-02-21 04:24:53,187 INFO L87 Difference]: Start difference. First operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1914 states and 2823 transitions. [2022-02-21 04:24:53,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:53,262 INFO L93 Difference]: Finished difference Result 1914 states and 2823 transitions. [2022-02-21 04:24:53,262 INFO L276 IsEmpty]: Start isEmpty. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:53,264 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:53,264 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:53,264 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:53,264 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:53,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1914 states, 1914 states have (on average 1.474921630094044) internal successors, (2823), 1913 states have internal predecessors, (2823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:53,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1914 states to 1914 states and 2823 transitions. [2022-02-21 04:24:53,339 INFO L704 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-02-21 04:24:53,339 INFO L587 BuchiCegarLoop]: Abstraction has 1914 states and 2823 transitions. [2022-02-21 04:24:53,339 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:24:53,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1914 states and 2823 transitions. [2022-02-21 04:24:53,343 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1741 [2022-02-21 04:24:53,343 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:53,343 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:53,345 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:53,345 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:53,345 INFO L791 eck$LassoCheckResult]: Stem: 96691#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 96692#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 96511#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 96227#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 96228#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 97404#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97405#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96363#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96364#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96822#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96653#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96654#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96430#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96431#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 96829#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97006#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97160#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 97197#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 96443#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96444#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 97617#L1258-2 assume !(0 == ~T1_E~0); 96736#L1263-1 assume !(0 == ~T2_E~0); 96737#L1268-1 assume !(0 == ~T3_E~0); 97040#L1273-1 assume !(0 == ~T4_E~0); 97599#L1278-1 assume !(0 == ~T5_E~0); 97460#L1283-1 assume !(0 == ~T6_E~0); 97461#L1288-1 assume !(0 == ~T7_E~0); 97698#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 97685#L1298-1 assume !(0 == ~T9_E~0); 97611#L1303-1 assume !(0 == ~T10_E~0); 96256#L1308-1 assume !(0 == ~T11_E~0); 96198#L1313-1 assume !(0 == ~T12_E~0); 96199#L1318-1 assume !(0 == ~T13_E~0); 96207#L1323-1 assume !(0 == ~E_1~0); 96208#L1328-1 assume !(0 == ~E_2~0); 96373#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 97332#L1338-1 assume !(0 == ~E_4~0); 97333#L1343-1 assume !(0 == ~E_5~0); 97434#L1348-1 assume !(0 == ~E_6~0); 97720#L1353-1 assume !(0 == ~E_7~0); 97059#L1358-1 assume !(0 == ~E_8~0); 97060#L1363-1 assume !(0 == ~E_9~0); 97351#L1368-1 assume !(0 == ~E_10~0); 96035#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 96036#L1378-1 assume !(0 == ~E_12~0); 96324#L1383-1 assume !(0 == ~E_13~0); 96325#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97066#L607 assume 1 == ~m_pc~0; 97067#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 96393#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97432#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96986#L1560 assume !(0 != activate_threads_~tmp~1#1); 96987#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96218#L626 assume !(1 == ~t1_pc~0); 96219#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 96489#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96490#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96659#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 96121#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96122#L645 assume 1 == ~t2_pc~0; 96235#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 96192#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96872#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96873#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 96962#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96963#L664 assume 1 == ~t3_pc~0; 97719#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 95963#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95964#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96618#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 96619#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97627#L683 assume !(1 == ~t4_pc~0); 97182#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 97134#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97135#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97169#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 97293#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96916#L702 assume 1 == ~t5_pc~0; 96917#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 96839#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97288#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97587#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 97528#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96007#L721 assume !(1 == ~t6_pc~0); 95981#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 95982#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96145#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96627#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 96628#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 97229#L740 assume 1 == ~t7_pc~0; 96056#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95869#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95870#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 95859#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 95860#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96564#L759 assume !(1 == ~t8_pc~0); 96565#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 96593#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 97286#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97287#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 97418#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97696#L778 assume 1 == ~t9_pc~0; 97585#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 96034#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95974#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 95903#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 95904#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 96232#L797 assume !(1 == ~t10_pc~0); 96233#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 96350#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97484#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96734#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 96735#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97024#L816 assume 1 == ~t11_pc~0; 95939#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 95940#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96697#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 96634#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 96635#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97159#L835 assume 1 == ~t12_pc~0; 97037#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 96103#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 96125#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 96266#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 96791#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 96792#L854 assume !(1 == ~t13_pc~0); 96432#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 96433#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 96485#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 96143#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 96144#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97523#L1401 assume !(1 == ~M_E~0); 96622#L1401-2 assume !(1 == ~T1_E~0); 96623#L1406-1 assume !(1 == ~T2_E~0); 97218#L1411-1 assume !(1 == ~T3_E~0); 97219#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 96885#L1421-1 assume !(1 == ~T5_E~0); 96428#L1426-1 assume !(1 == ~T6_E~0); 96429#L1431-1 assume !(1 == ~T7_E~0); 95977#L1436-1 assume !(1 == ~T8_E~0); 95978#L1441-1 assume !(1 == ~T9_E~0); 96727#L1446-1 assume !(1 == ~T10_E~0); 96728#L1451-1 assume !(1 == ~T11_E~0); 97431#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 97085#L1461-1 assume !(1 == ~T13_E~0); 96646#L1466-1 assume !(1 == ~E_1~0); 96647#L1471-1 assume !(1 == ~E_2~0); 97416#L1476-1 assume !(1 == ~E_3~0); 97417#L1481-1 assume !(1 == ~E_4~0); 97565#L1486-1 assume !(1 == ~E_5~0); 96273#L1491-1 assume !(1 == ~E_6~0); 95911#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 95912#L1501-1 assume !(1 == ~E_8~0); 96723#L1506-1 assume !(1 == ~E_9~0); 96724#L1511-1 assume !(1 == ~E_10~0); 96680#L1516-1 assume !(1 == ~E_11~0); 95857#L1521-1 assume !(1 == ~E_12~0); 95858#L1526-1 assume !(1 == ~E_13~0); 95910#L1531-1 assume { :end_inline_reset_delta_events } true; 96453#L1892-2 [2022-02-21 04:24:53,350 INFO L793 eck$LassoCheckResult]: Loop: 96453#L1892-2 assume !false; 97476#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97674#L1233 assume !false; 97657#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 96989#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 96969#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 97127#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 95953#L1046 assume !(0 != eval_~tmp~0#1); 95955#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 95989#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 97161#L1258-3 assume 0 == ~M_E~0;~M_E~0 := 1; 97718#L1258-5 assume !(0 == ~T1_E~0); 96135#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 96136#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 97710#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 97716#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 97717#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 96357#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 96358#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 97473#L1298-3 assume !(0 == ~T9_E~0); 97474#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 97633#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 97472#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 96973#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 96131#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 96132#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 97557#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 96276#L1338-3 assume !(0 == ~E_4~0); 96277#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 97389#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 97562#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 97563#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 96929#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 96487#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 96488#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 97246#L1378-3 assume !(0 == ~E_12~0); 97247#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 97428#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97429#L607-42 assume !(1 == ~m_pc~0); 97043#L607-44 is_master_triggered_~__retres1~0#1 := 0; 96770#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96771#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96503#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 96504#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97025#L626-42 assume 1 == ~t1_pc~0; 96587#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 96588#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96892#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96893#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 96167#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96168#L645-42 assume !(1 == ~t2_pc~0); 97367#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 97368#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97533#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96374#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95881#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95882#L664-42 assume !(1 == ~t3_pc~0); 96408#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 96409#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97660#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 97195#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97196#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97361#L683-42 assume !(1 == ~t4_pc~0); 97069#L683-44 is_transmit4_triggered_~__retres1~4#1 := 0; 97070#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97202#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97622#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 97623#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97467#L702-42 assume !(1 == ~t5_pc~0); 96579#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 96580#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96876#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 97549#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 95897#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95898#L721-42 assume 1 == ~t6_pc~0; 96051#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 96071#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96535#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97702#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 96707#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96553#L740-42 assume !(1 == ~t7_pc~0); 96290#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 96291#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96832#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96687#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 96688#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96961#L759-42 assume !(1 == ~t8_pc~0); 96811#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 96742#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96743#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96820#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 96821#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96915#L778-42 assume !(1 == ~t9_pc~0); 96755#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 96756#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 97165#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 97071#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 97072#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97129#L797-42 assume 1 == ~t10_pc~0; 96296#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 96297#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97298#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 97607#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 97167#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97168#L816-42 assume 1 == ~t11_pc~0; 95845#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 95846#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 96388#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 96389#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 96468#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 96469#L835-42 assume 1 == ~t12_pc~0; 96871#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 96766#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 96441#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 96442#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 97526#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 97310#L854-42 assume !(1 == ~t13_pc~0); 96384#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 96385#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 95997#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 95998#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 96644#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96645#L1401-3 assume 1 == ~M_E~0;~M_E~0 := 2; 97423#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 96231#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 96098#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 96099#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 96698#L1421-3 assume !(1 == ~T5_E~0); 96699#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 96274#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 96275#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 95861#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 95862#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 97451#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 96782#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 96435#L1461-3 assume !(1 == ~T13_E~0); 96436#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 97713#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 96375#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 96376#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 96776#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 96403#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 96404#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 96816#L1501-3 assume !(1 == ~E_8~0); 96817#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 97243#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 97233#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 97234#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 96933#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 96934#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 97328#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 96210#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 97103#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 96744#L1911 assume !(0 == start_simulation_~tmp~3#1); 96745#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 97267#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 96334#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 97205#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 96039#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 96040#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 96269#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 96270#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 96453#L1892-2 [2022-02-21 04:24:53,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:53,350 INFO L85 PathProgramCache]: Analyzing trace with hash 1395516382, now seen corresponding path program 1 times [2022-02-21 04:24:53,351 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:53,351 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498712245] [2022-02-21 04:24:53,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:53,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:53,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:53,390 INFO L290 TraceCheckUtils]: 0: Hoare triple {101575#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,390 INFO L290 TraceCheckUtils]: 1: Hoare triple {101577#(<= 2 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,391 INFO L290 TraceCheckUtils]: 2: Hoare triple {101577#(<= 2 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,391 INFO L290 TraceCheckUtils]: 3: Hoare triple {101577#(<= 2 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,391 INFO L290 TraceCheckUtils]: 4: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,392 INFO L290 TraceCheckUtils]: 5: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,392 INFO L290 TraceCheckUtils]: 6: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,392 INFO L290 TraceCheckUtils]: 7: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,393 INFO L290 TraceCheckUtils]: 8: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,393 INFO L290 TraceCheckUtils]: 9: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,393 INFO L290 TraceCheckUtils]: 10: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,394 INFO L290 TraceCheckUtils]: 11: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,394 INFO L290 TraceCheckUtils]: 12: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,394 INFO L290 TraceCheckUtils]: 13: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,395 INFO L290 TraceCheckUtils]: 14: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,395 INFO L290 TraceCheckUtils]: 15: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,395 INFO L290 TraceCheckUtils]: 16: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,396 INFO L290 TraceCheckUtils]: 17: Hoare triple {101577#(<= 2 ~M_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,396 INFO L290 TraceCheckUtils]: 18: Hoare triple {101577#(<= 2 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {101577#(<= 2 ~M_E~0)} is VALID [2022-02-21 04:24:53,397 INFO L290 TraceCheckUtils]: 19: Hoare triple {101577#(<= 2 ~M_E~0)} assume 0 == ~M_E~0;~M_E~0 := 1; {101576#false} is VALID [2022-02-21 04:24:53,397 INFO L290 TraceCheckUtils]: 20: Hoare triple {101576#false} assume !(0 == ~T1_E~0); {101576#false} is VALID [2022-02-21 04:24:53,397 INFO L290 TraceCheckUtils]: 21: Hoare triple {101576#false} assume !(0 == ~T2_E~0); {101576#false} is VALID [2022-02-21 04:24:53,397 INFO L290 TraceCheckUtils]: 22: Hoare triple {101576#false} assume !(0 == ~T3_E~0); {101576#false} is VALID [2022-02-21 04:24:53,397 INFO L290 TraceCheckUtils]: 23: Hoare triple {101576#false} assume !(0 == ~T4_E~0); {101576#false} is VALID [2022-02-21 04:24:53,397 INFO L290 TraceCheckUtils]: 24: Hoare triple {101576#false} assume !(0 == ~T5_E~0); {101576#false} is VALID [2022-02-21 04:24:53,397 INFO L290 TraceCheckUtils]: 25: Hoare triple {101576#false} assume !(0 == ~T6_E~0); {101576#false} is VALID [2022-02-21 04:24:53,398 INFO L290 TraceCheckUtils]: 26: Hoare triple {101576#false} assume !(0 == ~T7_E~0); {101576#false} is VALID [2022-02-21 04:24:53,398 INFO L290 TraceCheckUtils]: 27: Hoare triple {101576#false} assume 0 == ~T8_E~0;~T8_E~0 := 1; {101576#false} is VALID [2022-02-21 04:24:53,398 INFO L290 TraceCheckUtils]: 28: Hoare triple {101576#false} assume !(0 == ~T9_E~0); {101576#false} is VALID [2022-02-21 04:24:53,398 INFO L290 TraceCheckUtils]: 29: Hoare triple {101576#false} assume !(0 == ~T10_E~0); {101576#false} is VALID [2022-02-21 04:24:53,398 INFO L290 TraceCheckUtils]: 30: Hoare triple {101576#false} assume !(0 == ~T11_E~0); {101576#false} is VALID [2022-02-21 04:24:53,398 INFO L290 TraceCheckUtils]: 31: Hoare triple {101576#false} assume !(0 == ~T12_E~0); {101576#false} is VALID [2022-02-21 04:24:53,398 INFO L290 TraceCheckUtils]: 32: Hoare triple {101576#false} assume !(0 == ~T13_E~0); {101576#false} is VALID [2022-02-21 04:24:53,398 INFO L290 TraceCheckUtils]: 33: Hoare triple {101576#false} assume !(0 == ~E_1~0); {101576#false} is VALID [2022-02-21 04:24:53,399 INFO L290 TraceCheckUtils]: 34: Hoare triple {101576#false} assume !(0 == ~E_2~0); {101576#false} is VALID [2022-02-21 04:24:53,399 INFO L290 TraceCheckUtils]: 35: Hoare triple {101576#false} assume 0 == ~E_3~0;~E_3~0 := 1; {101576#false} is VALID [2022-02-21 04:24:53,399 INFO L290 TraceCheckUtils]: 36: Hoare triple {101576#false} assume !(0 == ~E_4~0); {101576#false} is VALID [2022-02-21 04:24:53,399 INFO L290 TraceCheckUtils]: 37: Hoare triple {101576#false} assume !(0 == ~E_5~0); {101576#false} is VALID [2022-02-21 04:24:53,399 INFO L290 TraceCheckUtils]: 38: Hoare triple {101576#false} assume !(0 == ~E_6~0); {101576#false} is VALID [2022-02-21 04:24:53,399 INFO L290 TraceCheckUtils]: 39: Hoare triple {101576#false} assume !(0 == ~E_7~0); {101576#false} is VALID [2022-02-21 04:24:53,399 INFO L290 TraceCheckUtils]: 40: Hoare triple {101576#false} assume !(0 == ~E_8~0); {101576#false} is VALID [2022-02-21 04:24:53,399 INFO L290 TraceCheckUtils]: 41: Hoare triple {101576#false} assume !(0 == ~E_9~0); {101576#false} is VALID [2022-02-21 04:24:53,400 INFO L290 TraceCheckUtils]: 42: Hoare triple {101576#false} assume !(0 == ~E_10~0); {101576#false} is VALID [2022-02-21 04:24:53,400 INFO L290 TraceCheckUtils]: 43: Hoare triple {101576#false} assume 0 == ~E_11~0;~E_11~0 := 1; {101576#false} is VALID [2022-02-21 04:24:53,400 INFO L290 TraceCheckUtils]: 44: Hoare triple {101576#false} assume !(0 == ~E_12~0); {101576#false} is VALID [2022-02-21 04:24:53,400 INFO L290 TraceCheckUtils]: 45: Hoare triple {101576#false} assume !(0 == ~E_13~0); {101576#false} is VALID [2022-02-21 04:24:53,400 INFO L290 TraceCheckUtils]: 46: Hoare triple {101576#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {101576#false} is VALID [2022-02-21 04:24:53,400 INFO L290 TraceCheckUtils]: 47: Hoare triple {101576#false} assume 1 == ~m_pc~0; {101576#false} is VALID [2022-02-21 04:24:53,400 INFO L290 TraceCheckUtils]: 48: Hoare triple {101576#false} assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; {101576#false} is VALID [2022-02-21 04:24:53,401 INFO L290 TraceCheckUtils]: 49: Hoare triple {101576#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {101576#false} is VALID [2022-02-21 04:24:53,401 INFO L290 TraceCheckUtils]: 50: Hoare triple {101576#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {101576#false} is VALID [2022-02-21 04:24:53,401 INFO L290 TraceCheckUtils]: 51: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp~1#1); {101576#false} is VALID [2022-02-21 04:24:53,401 INFO L290 TraceCheckUtils]: 52: Hoare triple {101576#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {101576#false} is VALID [2022-02-21 04:24:53,401 INFO L290 TraceCheckUtils]: 53: Hoare triple {101576#false} assume !(1 == ~t1_pc~0); {101576#false} is VALID [2022-02-21 04:24:53,401 INFO L290 TraceCheckUtils]: 54: Hoare triple {101576#false} is_transmit1_triggered_~__retres1~1#1 := 0; {101576#false} is VALID [2022-02-21 04:24:53,401 INFO L290 TraceCheckUtils]: 55: Hoare triple {101576#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {101576#false} is VALID [2022-02-21 04:24:53,401 INFO L290 TraceCheckUtils]: 56: Hoare triple {101576#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {101576#false} is VALID [2022-02-21 04:24:53,402 INFO L290 TraceCheckUtils]: 57: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp___0~0#1); {101576#false} is VALID [2022-02-21 04:24:53,402 INFO L290 TraceCheckUtils]: 58: Hoare triple {101576#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {101576#false} is VALID [2022-02-21 04:24:53,402 INFO L290 TraceCheckUtils]: 59: Hoare triple {101576#false} assume 1 == ~t2_pc~0; {101576#false} is VALID [2022-02-21 04:24:53,402 INFO L290 TraceCheckUtils]: 60: Hoare triple {101576#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {101576#false} is VALID [2022-02-21 04:24:53,402 INFO L290 TraceCheckUtils]: 61: Hoare triple {101576#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {101576#false} is VALID [2022-02-21 04:24:53,402 INFO L290 TraceCheckUtils]: 62: Hoare triple {101576#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {101576#false} is VALID [2022-02-21 04:24:53,402 INFO L290 TraceCheckUtils]: 63: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp___1~0#1); {101576#false} is VALID [2022-02-21 04:24:53,402 INFO L290 TraceCheckUtils]: 64: Hoare triple {101576#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {101576#false} is VALID [2022-02-21 04:24:53,403 INFO L290 TraceCheckUtils]: 65: Hoare triple {101576#false} assume 1 == ~t3_pc~0; {101576#false} is VALID [2022-02-21 04:24:53,403 INFO L290 TraceCheckUtils]: 66: Hoare triple {101576#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {101576#false} is VALID [2022-02-21 04:24:53,403 INFO L290 TraceCheckUtils]: 67: Hoare triple {101576#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {101576#false} is VALID [2022-02-21 04:24:53,403 INFO L290 TraceCheckUtils]: 68: Hoare triple {101576#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {101576#false} is VALID [2022-02-21 04:24:53,403 INFO L290 TraceCheckUtils]: 69: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp___2~0#1); {101576#false} is VALID [2022-02-21 04:24:53,403 INFO L290 TraceCheckUtils]: 70: Hoare triple {101576#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {101576#false} is VALID [2022-02-21 04:24:53,403 INFO L290 TraceCheckUtils]: 71: Hoare triple {101576#false} assume !(1 == ~t4_pc~0); {101576#false} is VALID [2022-02-21 04:24:53,403 INFO L290 TraceCheckUtils]: 72: Hoare triple {101576#false} is_transmit4_triggered_~__retres1~4#1 := 0; {101576#false} is VALID [2022-02-21 04:24:53,404 INFO L290 TraceCheckUtils]: 73: Hoare triple {101576#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {101576#false} is VALID [2022-02-21 04:24:53,404 INFO L290 TraceCheckUtils]: 74: Hoare triple {101576#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {101576#false} is VALID [2022-02-21 04:24:53,404 INFO L290 TraceCheckUtils]: 75: Hoare triple {101576#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {101576#false} is VALID [2022-02-21 04:24:53,404 INFO L290 TraceCheckUtils]: 76: Hoare triple {101576#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {101576#false} is VALID [2022-02-21 04:24:53,404 INFO L290 TraceCheckUtils]: 77: Hoare triple {101576#false} assume 1 == ~t5_pc~0; {101576#false} is VALID [2022-02-21 04:24:53,404 INFO L290 TraceCheckUtils]: 78: Hoare triple {101576#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {101576#false} is VALID [2022-02-21 04:24:53,404 INFO L290 TraceCheckUtils]: 79: Hoare triple {101576#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {101576#false} is VALID [2022-02-21 04:24:53,404 INFO L290 TraceCheckUtils]: 80: Hoare triple {101576#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {101576#false} is VALID [2022-02-21 04:24:53,405 INFO L290 TraceCheckUtils]: 81: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp___4~0#1); {101576#false} is VALID [2022-02-21 04:24:53,405 INFO L290 TraceCheckUtils]: 82: Hoare triple {101576#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {101576#false} is VALID [2022-02-21 04:24:53,405 INFO L290 TraceCheckUtils]: 83: Hoare triple {101576#false} assume !(1 == ~t6_pc~0); {101576#false} is VALID [2022-02-21 04:24:53,405 INFO L290 TraceCheckUtils]: 84: Hoare triple {101576#false} is_transmit6_triggered_~__retres1~6#1 := 0; {101576#false} is VALID [2022-02-21 04:24:53,405 INFO L290 TraceCheckUtils]: 85: Hoare triple {101576#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {101576#false} is VALID [2022-02-21 04:24:53,405 INFO L290 TraceCheckUtils]: 86: Hoare triple {101576#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {101576#false} is VALID [2022-02-21 04:24:53,405 INFO L290 TraceCheckUtils]: 87: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp___5~0#1); {101576#false} is VALID [2022-02-21 04:24:53,405 INFO L290 TraceCheckUtils]: 88: Hoare triple {101576#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {101576#false} is VALID [2022-02-21 04:24:53,406 INFO L290 TraceCheckUtils]: 89: Hoare triple {101576#false} assume 1 == ~t7_pc~0; {101576#false} is VALID [2022-02-21 04:24:53,406 INFO L290 TraceCheckUtils]: 90: Hoare triple {101576#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {101576#false} is VALID [2022-02-21 04:24:53,406 INFO L290 TraceCheckUtils]: 91: Hoare triple {101576#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {101576#false} is VALID [2022-02-21 04:24:53,406 INFO L290 TraceCheckUtils]: 92: Hoare triple {101576#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {101576#false} is VALID [2022-02-21 04:24:53,406 INFO L290 TraceCheckUtils]: 93: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp___6~0#1); {101576#false} is VALID [2022-02-21 04:24:53,406 INFO L290 TraceCheckUtils]: 94: Hoare triple {101576#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {101576#false} is VALID [2022-02-21 04:24:53,412 INFO L290 TraceCheckUtils]: 95: Hoare triple {101576#false} assume !(1 == ~t8_pc~0); {101576#false} is VALID [2022-02-21 04:24:53,412 INFO L290 TraceCheckUtils]: 96: Hoare triple {101576#false} is_transmit8_triggered_~__retres1~8#1 := 0; {101576#false} is VALID [2022-02-21 04:24:53,412 INFO L290 TraceCheckUtils]: 97: Hoare triple {101576#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {101576#false} is VALID [2022-02-21 04:24:53,412 INFO L290 TraceCheckUtils]: 98: Hoare triple {101576#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {101576#false} is VALID [2022-02-21 04:24:53,412 INFO L290 TraceCheckUtils]: 99: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp___7~0#1); {101576#false} is VALID [2022-02-21 04:24:53,412 INFO L290 TraceCheckUtils]: 100: Hoare triple {101576#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {101576#false} is VALID [2022-02-21 04:24:53,412 INFO L290 TraceCheckUtils]: 101: Hoare triple {101576#false} assume 1 == ~t9_pc~0; {101576#false} is VALID [2022-02-21 04:24:53,413 INFO L290 TraceCheckUtils]: 102: Hoare triple {101576#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {101576#false} is VALID [2022-02-21 04:24:53,413 INFO L290 TraceCheckUtils]: 103: Hoare triple {101576#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {101576#false} is VALID [2022-02-21 04:24:53,413 INFO L290 TraceCheckUtils]: 104: Hoare triple {101576#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {101576#false} is VALID [2022-02-21 04:24:53,413 INFO L290 TraceCheckUtils]: 105: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp___8~0#1); {101576#false} is VALID [2022-02-21 04:24:53,413 INFO L290 TraceCheckUtils]: 106: Hoare triple {101576#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {101576#false} is VALID [2022-02-21 04:24:53,413 INFO L290 TraceCheckUtils]: 107: Hoare triple {101576#false} assume !(1 == ~t10_pc~0); {101576#false} is VALID [2022-02-21 04:24:53,413 INFO L290 TraceCheckUtils]: 108: Hoare triple {101576#false} is_transmit10_triggered_~__retres1~10#1 := 0; {101576#false} is VALID [2022-02-21 04:24:53,414 INFO L290 TraceCheckUtils]: 109: Hoare triple {101576#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {101576#false} is VALID [2022-02-21 04:24:53,414 INFO L290 TraceCheckUtils]: 110: Hoare triple {101576#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {101576#false} is VALID [2022-02-21 04:24:53,414 INFO L290 TraceCheckUtils]: 111: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp___9~0#1); {101576#false} is VALID [2022-02-21 04:24:53,414 INFO L290 TraceCheckUtils]: 112: Hoare triple {101576#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {101576#false} is VALID [2022-02-21 04:24:53,414 INFO L290 TraceCheckUtils]: 113: Hoare triple {101576#false} assume 1 == ~t11_pc~0; {101576#false} is VALID [2022-02-21 04:24:53,414 INFO L290 TraceCheckUtils]: 114: Hoare triple {101576#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {101576#false} is VALID [2022-02-21 04:24:53,414 INFO L290 TraceCheckUtils]: 115: Hoare triple {101576#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {101576#false} is VALID [2022-02-21 04:24:53,415 INFO L290 TraceCheckUtils]: 116: Hoare triple {101576#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {101576#false} is VALID [2022-02-21 04:24:53,415 INFO L290 TraceCheckUtils]: 117: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp___10~0#1); {101576#false} is VALID [2022-02-21 04:24:53,415 INFO L290 TraceCheckUtils]: 118: Hoare triple {101576#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {101576#false} is VALID [2022-02-21 04:24:53,415 INFO L290 TraceCheckUtils]: 119: Hoare triple {101576#false} assume 1 == ~t12_pc~0; {101576#false} is VALID [2022-02-21 04:24:53,415 INFO L290 TraceCheckUtils]: 120: Hoare triple {101576#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {101576#false} is VALID [2022-02-21 04:24:53,415 INFO L290 TraceCheckUtils]: 121: Hoare triple {101576#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {101576#false} is VALID [2022-02-21 04:24:53,415 INFO L290 TraceCheckUtils]: 122: Hoare triple {101576#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {101576#false} is VALID [2022-02-21 04:24:53,415 INFO L290 TraceCheckUtils]: 123: Hoare triple {101576#false} assume !(0 != activate_threads_~tmp___11~0#1); {101576#false} is VALID [2022-02-21 04:24:53,416 INFO L290 TraceCheckUtils]: 124: Hoare triple {101576#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {101576#false} is VALID [2022-02-21 04:24:53,416 INFO L290 TraceCheckUtils]: 125: Hoare triple {101576#false} assume !(1 == ~t13_pc~0); {101576#false} is VALID [2022-02-21 04:24:53,416 INFO L290 TraceCheckUtils]: 126: Hoare triple {101576#false} is_transmit13_triggered_~__retres1~13#1 := 0; {101576#false} is VALID [2022-02-21 04:24:53,416 INFO L290 TraceCheckUtils]: 127: Hoare triple {101576#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {101576#false} is VALID [2022-02-21 04:24:53,416 INFO L290 TraceCheckUtils]: 128: Hoare triple {101576#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {101576#false} is VALID [2022-02-21 04:24:53,416 INFO L290 TraceCheckUtils]: 129: Hoare triple {101576#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {101576#false} is VALID [2022-02-21 04:24:53,416 INFO L290 TraceCheckUtils]: 130: Hoare triple {101576#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {101576#false} is VALID [2022-02-21 04:24:53,417 INFO L290 TraceCheckUtils]: 131: Hoare triple {101576#false} assume !(1 == ~M_E~0); {101576#false} is VALID [2022-02-21 04:24:53,417 INFO L290 TraceCheckUtils]: 132: Hoare triple {101576#false} assume !(1 == ~T1_E~0); {101576#false} is VALID [2022-02-21 04:24:53,417 INFO L290 TraceCheckUtils]: 133: Hoare triple {101576#false} assume !(1 == ~T2_E~0); {101576#false} is VALID [2022-02-21 04:24:53,417 INFO L290 TraceCheckUtils]: 134: Hoare triple {101576#false} assume !(1 == ~T3_E~0); {101576#false} is VALID [2022-02-21 04:24:53,417 INFO L290 TraceCheckUtils]: 135: Hoare triple {101576#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {101576#false} is VALID [2022-02-21 04:24:53,417 INFO L290 TraceCheckUtils]: 136: Hoare triple {101576#false} assume !(1 == ~T5_E~0); {101576#false} is VALID [2022-02-21 04:24:53,417 INFO L290 TraceCheckUtils]: 137: Hoare triple {101576#false} assume !(1 == ~T6_E~0); {101576#false} is VALID [2022-02-21 04:24:53,418 INFO L290 TraceCheckUtils]: 138: Hoare triple {101576#false} assume !(1 == ~T7_E~0); {101576#false} is VALID [2022-02-21 04:24:53,418 INFO L290 TraceCheckUtils]: 139: Hoare triple {101576#false} assume !(1 == ~T8_E~0); {101576#false} is VALID [2022-02-21 04:24:53,418 INFO L290 TraceCheckUtils]: 140: Hoare triple {101576#false} assume !(1 == ~T9_E~0); {101576#false} is VALID [2022-02-21 04:24:53,418 INFO L290 TraceCheckUtils]: 141: Hoare triple {101576#false} assume !(1 == ~T10_E~0); {101576#false} is VALID [2022-02-21 04:24:53,418 INFO L290 TraceCheckUtils]: 142: Hoare triple {101576#false} assume !(1 == ~T11_E~0); {101576#false} is VALID [2022-02-21 04:24:53,418 INFO L290 TraceCheckUtils]: 143: Hoare triple {101576#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {101576#false} is VALID [2022-02-21 04:24:53,418 INFO L290 TraceCheckUtils]: 144: Hoare triple {101576#false} assume !(1 == ~T13_E~0); {101576#false} is VALID [2022-02-21 04:24:53,418 INFO L290 TraceCheckUtils]: 145: Hoare triple {101576#false} assume !(1 == ~E_1~0); {101576#false} is VALID [2022-02-21 04:24:53,419 INFO L290 TraceCheckUtils]: 146: Hoare triple {101576#false} assume !(1 == ~E_2~0); {101576#false} is VALID [2022-02-21 04:24:53,419 INFO L290 TraceCheckUtils]: 147: Hoare triple {101576#false} assume !(1 == ~E_3~0); {101576#false} is VALID [2022-02-21 04:24:53,419 INFO L290 TraceCheckUtils]: 148: Hoare triple {101576#false} assume !(1 == ~E_4~0); {101576#false} is VALID [2022-02-21 04:24:53,419 INFO L290 TraceCheckUtils]: 149: Hoare triple {101576#false} assume !(1 == ~E_5~0); {101576#false} is VALID [2022-02-21 04:24:53,419 INFO L290 TraceCheckUtils]: 150: Hoare triple {101576#false} assume !(1 == ~E_6~0); {101576#false} is VALID [2022-02-21 04:24:53,419 INFO L290 TraceCheckUtils]: 151: Hoare triple {101576#false} assume 1 == ~E_7~0;~E_7~0 := 2; {101576#false} is VALID [2022-02-21 04:24:53,419 INFO L290 TraceCheckUtils]: 152: Hoare triple {101576#false} assume !(1 == ~E_8~0); {101576#false} is VALID [2022-02-21 04:24:53,420 INFO L290 TraceCheckUtils]: 153: Hoare triple {101576#false} assume !(1 == ~E_9~0); {101576#false} is VALID [2022-02-21 04:24:53,420 INFO L290 TraceCheckUtils]: 154: Hoare triple {101576#false} assume !(1 == ~E_10~0); {101576#false} is VALID [2022-02-21 04:24:53,420 INFO L290 TraceCheckUtils]: 155: Hoare triple {101576#false} assume !(1 == ~E_11~0); {101576#false} is VALID [2022-02-21 04:24:53,420 INFO L290 TraceCheckUtils]: 156: Hoare triple {101576#false} assume !(1 == ~E_12~0); {101576#false} is VALID [2022-02-21 04:24:53,420 INFO L290 TraceCheckUtils]: 157: Hoare triple {101576#false} assume !(1 == ~E_13~0); {101576#false} is VALID [2022-02-21 04:24:53,420 INFO L290 TraceCheckUtils]: 158: Hoare triple {101576#false} assume { :end_inline_reset_delta_events } true; {101576#false} is VALID [2022-02-21 04:24:53,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:53,421 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:53,421 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498712245] [2022-02-21 04:24:53,421 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498712245] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:53,421 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:53,421 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:24:53,422 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1332506149] [2022-02-21 04:24:53,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:53,423 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:53,424 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:53,424 INFO L85 PathProgramCache]: Analyzing trace with hash -1535351462, now seen corresponding path program 2 times [2022-02-21 04:24:53,424 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:53,424 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136231579] [2022-02-21 04:24:53,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:53,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:53,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:53,457 INFO L290 TraceCheckUtils]: 0: Hoare triple {101578#true} assume !false; {101578#true} is VALID [2022-02-21 04:24:53,457 INFO L290 TraceCheckUtils]: 1: Hoare triple {101578#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {101578#true} is VALID [2022-02-21 04:24:53,457 INFO L290 TraceCheckUtils]: 2: Hoare triple {101578#true} assume !false; {101578#true} is VALID [2022-02-21 04:24:53,457 INFO L290 TraceCheckUtils]: 3: Hoare triple {101578#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {101578#true} is VALID [2022-02-21 04:24:53,457 INFO L290 TraceCheckUtils]: 4: Hoare triple {101578#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {101578#true} is VALID [2022-02-21 04:24:53,457 INFO L290 TraceCheckUtils]: 5: Hoare triple {101578#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {101578#true} is VALID [2022-02-21 04:24:53,457 INFO L290 TraceCheckUtils]: 6: Hoare triple {101578#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {101578#true} is VALID [2022-02-21 04:24:53,457 INFO L290 TraceCheckUtils]: 7: Hoare triple {101578#true} assume !(0 != eval_~tmp~0#1); {101578#true} is VALID [2022-02-21 04:24:53,458 INFO L290 TraceCheckUtils]: 8: Hoare triple {101578#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {101578#true} is VALID [2022-02-21 04:24:53,458 INFO L290 TraceCheckUtils]: 9: Hoare triple {101578#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {101578#true} is VALID [2022-02-21 04:24:53,458 INFO L290 TraceCheckUtils]: 10: Hoare triple {101578#true} assume 0 == ~M_E~0;~M_E~0 := 1; {101578#true} is VALID [2022-02-21 04:24:53,458 INFO L290 TraceCheckUtils]: 11: Hoare triple {101578#true} assume !(0 == ~T1_E~0); {101578#true} is VALID [2022-02-21 04:24:53,458 INFO L290 TraceCheckUtils]: 12: Hoare triple {101578#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {101578#true} is VALID [2022-02-21 04:24:53,458 INFO L290 TraceCheckUtils]: 13: Hoare triple {101578#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {101578#true} is VALID [2022-02-21 04:24:53,458 INFO L290 TraceCheckUtils]: 14: Hoare triple {101578#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {101578#true} is VALID [2022-02-21 04:24:53,458 INFO L290 TraceCheckUtils]: 15: Hoare triple {101578#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,459 INFO L290 TraceCheckUtils]: 16: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,459 INFO L290 TraceCheckUtils]: 17: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,459 INFO L290 TraceCheckUtils]: 18: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,460 INFO L290 TraceCheckUtils]: 19: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,460 INFO L290 TraceCheckUtils]: 20: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,460 INFO L290 TraceCheckUtils]: 21: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,461 INFO L290 TraceCheckUtils]: 22: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,461 INFO L290 TraceCheckUtils]: 23: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,461 INFO L290 TraceCheckUtils]: 24: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,462 INFO L290 TraceCheckUtils]: 25: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,462 INFO L290 TraceCheckUtils]: 26: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,462 INFO L290 TraceCheckUtils]: 27: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,463 INFO L290 TraceCheckUtils]: 28: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,463 INFO L290 TraceCheckUtils]: 29: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,463 INFO L290 TraceCheckUtils]: 30: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,464 INFO L290 TraceCheckUtils]: 31: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,464 INFO L290 TraceCheckUtils]: 32: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,464 INFO L290 TraceCheckUtils]: 33: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,465 INFO L290 TraceCheckUtils]: 34: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,465 INFO L290 TraceCheckUtils]: 35: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,465 INFO L290 TraceCheckUtils]: 36: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,466 INFO L290 TraceCheckUtils]: 37: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,466 INFO L290 TraceCheckUtils]: 38: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,466 INFO L290 TraceCheckUtils]: 39: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,467 INFO L290 TraceCheckUtils]: 40: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,467 INFO L290 TraceCheckUtils]: 41: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,467 INFO L290 TraceCheckUtils]: 42: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,468 INFO L290 TraceCheckUtils]: 43: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,468 INFO L290 TraceCheckUtils]: 44: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,468 INFO L290 TraceCheckUtils]: 45: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,469 INFO L290 TraceCheckUtils]: 46: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,469 INFO L290 TraceCheckUtils]: 47: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,469 INFO L290 TraceCheckUtils]: 48: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,470 INFO L290 TraceCheckUtils]: 49: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,470 INFO L290 TraceCheckUtils]: 50: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,470 INFO L290 TraceCheckUtils]: 51: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,470 INFO L290 TraceCheckUtils]: 52: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,471 INFO L290 TraceCheckUtils]: 53: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,471 INFO L290 TraceCheckUtils]: 54: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,471 INFO L290 TraceCheckUtils]: 55: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,472 INFO L290 TraceCheckUtils]: 56: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,472 INFO L290 TraceCheckUtils]: 57: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,472 INFO L290 TraceCheckUtils]: 58: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,473 INFO L290 TraceCheckUtils]: 59: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,473 INFO L290 TraceCheckUtils]: 60: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,473 INFO L290 TraceCheckUtils]: 61: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,474 INFO L290 TraceCheckUtils]: 62: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t4_pc~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,474 INFO L290 TraceCheckUtils]: 63: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,474 INFO L290 TraceCheckUtils]: 64: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,475 INFO L290 TraceCheckUtils]: 65: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,475 INFO L290 TraceCheckUtils]: 66: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,475 INFO L290 TraceCheckUtils]: 67: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,476 INFO L290 TraceCheckUtils]: 68: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,476 INFO L290 TraceCheckUtils]: 69: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,476 INFO L290 TraceCheckUtils]: 70: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,477 INFO L290 TraceCheckUtils]: 71: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,477 INFO L290 TraceCheckUtils]: 72: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,477 INFO L290 TraceCheckUtils]: 73: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,478 INFO L290 TraceCheckUtils]: 74: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,478 INFO L290 TraceCheckUtils]: 75: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,478 INFO L290 TraceCheckUtils]: 76: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,478 INFO L290 TraceCheckUtils]: 77: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,479 INFO L290 TraceCheckUtils]: 78: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,479 INFO L290 TraceCheckUtils]: 79: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,479 INFO L290 TraceCheckUtils]: 80: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t7_pc~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,480 INFO L290 TraceCheckUtils]: 81: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,480 INFO L290 TraceCheckUtils]: 82: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,480 INFO L290 TraceCheckUtils]: 83: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,481 INFO L290 TraceCheckUtils]: 84: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,481 INFO L290 TraceCheckUtils]: 85: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,481 INFO L290 TraceCheckUtils]: 86: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,482 INFO L290 TraceCheckUtils]: 87: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,482 INFO L290 TraceCheckUtils]: 88: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,482 INFO L290 TraceCheckUtils]: 89: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,483 INFO L290 TraceCheckUtils]: 90: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,483 INFO L290 TraceCheckUtils]: 91: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,483 INFO L290 TraceCheckUtils]: 92: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,484 INFO L290 TraceCheckUtils]: 93: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,484 INFO L290 TraceCheckUtils]: 94: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,484 INFO L290 TraceCheckUtils]: 95: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,485 INFO L290 TraceCheckUtils]: 96: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,485 INFO L290 TraceCheckUtils]: 97: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,485 INFO L290 TraceCheckUtils]: 98: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t10_pc~0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,486 INFO L290 TraceCheckUtils]: 99: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,486 INFO L290 TraceCheckUtils]: 100: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,486 INFO L290 TraceCheckUtils]: 101: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,486 INFO L290 TraceCheckUtils]: 102: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,487 INFO L290 TraceCheckUtils]: 103: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,487 INFO L290 TraceCheckUtils]: 104: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,487 INFO L290 TraceCheckUtils]: 105: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,488 INFO L290 TraceCheckUtils]: 106: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,488 INFO L290 TraceCheckUtils]: 107: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,488 INFO L290 TraceCheckUtils]: 108: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,489 INFO L290 TraceCheckUtils]: 109: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,489 INFO L290 TraceCheckUtils]: 110: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,489 INFO L290 TraceCheckUtils]: 111: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,490 INFO L290 TraceCheckUtils]: 112: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,490 INFO L290 TraceCheckUtils]: 113: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,490 INFO L290 TraceCheckUtils]: 114: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,491 INFO L290 TraceCheckUtils]: 115: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,491 INFO L290 TraceCheckUtils]: 116: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,491 INFO L290 TraceCheckUtils]: 117: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,492 INFO L290 TraceCheckUtils]: 118: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,492 INFO L290 TraceCheckUtils]: 119: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,492 INFO L290 TraceCheckUtils]: 120: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,493 INFO L290 TraceCheckUtils]: 121: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,493 INFO L290 TraceCheckUtils]: 122: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,493 INFO L290 TraceCheckUtils]: 123: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,494 INFO L290 TraceCheckUtils]: 124: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,494 INFO L290 TraceCheckUtils]: 125: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,494 INFO L290 TraceCheckUtils]: 126: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {101580#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:53,494 INFO L290 TraceCheckUtils]: 127: Hoare triple {101580#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {101579#false} is VALID [2022-02-21 04:24:53,495 INFO L290 TraceCheckUtils]: 128: Hoare triple {101579#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,495 INFO L290 TraceCheckUtils]: 129: Hoare triple {101579#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,495 INFO L290 TraceCheckUtils]: 130: Hoare triple {101579#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,495 INFO L290 TraceCheckUtils]: 131: Hoare triple {101579#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,495 INFO L290 TraceCheckUtils]: 132: Hoare triple {101579#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,495 INFO L290 TraceCheckUtils]: 133: Hoare triple {101579#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,495 INFO L290 TraceCheckUtils]: 134: Hoare triple {101579#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,495 INFO L290 TraceCheckUtils]: 135: Hoare triple {101579#false} assume !(1 == ~T13_E~0); {101579#false} is VALID [2022-02-21 04:24:53,495 INFO L290 TraceCheckUtils]: 136: Hoare triple {101579#false} assume 1 == ~E_1~0;~E_1~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,495 INFO L290 TraceCheckUtils]: 137: Hoare triple {101579#false} assume 1 == ~E_2~0;~E_2~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,496 INFO L290 TraceCheckUtils]: 138: Hoare triple {101579#false} assume 1 == ~E_3~0;~E_3~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,496 INFO L290 TraceCheckUtils]: 139: Hoare triple {101579#false} assume 1 == ~E_4~0;~E_4~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,496 INFO L290 TraceCheckUtils]: 140: Hoare triple {101579#false} assume 1 == ~E_5~0;~E_5~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,496 INFO L290 TraceCheckUtils]: 141: Hoare triple {101579#false} assume 1 == ~E_6~0;~E_6~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,496 INFO L290 TraceCheckUtils]: 142: Hoare triple {101579#false} assume 1 == ~E_7~0;~E_7~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,496 INFO L290 TraceCheckUtils]: 143: Hoare triple {101579#false} assume !(1 == ~E_8~0); {101579#false} is VALID [2022-02-21 04:24:53,496 INFO L290 TraceCheckUtils]: 144: Hoare triple {101579#false} assume 1 == ~E_9~0;~E_9~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,496 INFO L290 TraceCheckUtils]: 145: Hoare triple {101579#false} assume 1 == ~E_10~0;~E_10~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,496 INFO L290 TraceCheckUtils]: 146: Hoare triple {101579#false} assume 1 == ~E_11~0;~E_11~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,497 INFO L290 TraceCheckUtils]: 147: Hoare triple {101579#false} assume 1 == ~E_12~0;~E_12~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,497 INFO L290 TraceCheckUtils]: 148: Hoare triple {101579#false} assume 1 == ~E_13~0;~E_13~0 := 2; {101579#false} is VALID [2022-02-21 04:24:53,497 INFO L290 TraceCheckUtils]: 149: Hoare triple {101579#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {101579#false} is VALID [2022-02-21 04:24:53,497 INFO L290 TraceCheckUtils]: 150: Hoare triple {101579#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {101579#false} is VALID [2022-02-21 04:24:53,497 INFO L290 TraceCheckUtils]: 151: Hoare triple {101579#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {101579#false} is VALID [2022-02-21 04:24:53,497 INFO L290 TraceCheckUtils]: 152: Hoare triple {101579#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {101579#false} is VALID [2022-02-21 04:24:53,497 INFO L290 TraceCheckUtils]: 153: Hoare triple {101579#false} assume !(0 == start_simulation_~tmp~3#1); {101579#false} is VALID [2022-02-21 04:24:53,497 INFO L290 TraceCheckUtils]: 154: Hoare triple {101579#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {101579#false} is VALID [2022-02-21 04:24:53,497 INFO L290 TraceCheckUtils]: 155: Hoare triple {101579#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {101579#false} is VALID [2022-02-21 04:24:53,497 INFO L290 TraceCheckUtils]: 156: Hoare triple {101579#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {101579#false} is VALID [2022-02-21 04:24:53,497 INFO L290 TraceCheckUtils]: 157: Hoare triple {101579#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {101579#false} is VALID [2022-02-21 04:24:53,498 INFO L290 TraceCheckUtils]: 158: Hoare triple {101579#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {101579#false} is VALID [2022-02-21 04:24:53,498 INFO L290 TraceCheckUtils]: 159: Hoare triple {101579#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {101579#false} is VALID [2022-02-21 04:24:53,498 INFO L290 TraceCheckUtils]: 160: Hoare triple {101579#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {101579#false} is VALID [2022-02-21 04:24:53,498 INFO L290 TraceCheckUtils]: 161: Hoare triple {101579#false} assume !(0 != start_simulation_~tmp___0~1#1); {101579#false} is VALID [2022-02-21 04:24:53,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:53,498 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:53,499 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1136231579] [2022-02-21 04:24:53,499 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1136231579] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:53,499 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:53,499 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:53,499 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723193005] [2022-02-21 04:24:53,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:53,499 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:53,500 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:53,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:24:53,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:24:53,500 INFO L87 Difference]: Start difference. First operand 1914 states and 2823 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:56,144 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2022-02-21 04:24:56,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:24:56,145 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,241 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:24:56,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:56,531 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-02-21 04:24:56,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-02-21 04:24:56,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3555 [2022-02-21 04:24:56,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3555 [2022-02-21 04:24:56,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:56,802 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:24:56,802 INFO L681 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-02-21 04:24:56,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:56,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3555 to 3555. [2022-02-21 04:24:56,841 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:24:56,845 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3555 states and 5213 transitions. Second operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,849 INFO L74 IsIncluded]: Start isIncluded. First operand 3555 states and 5213 transitions. Second operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:56,853 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. Second operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:57,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:57,148 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2022-02-21 04:24:57,148 INFO L276 IsEmpty]: Start isEmpty. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:57,151 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:57,151 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:57,156 INFO L74 IsIncluded]: Start isIncluded. First operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3555 states and 5213 transitions. [2022-02-21 04:24:57,159 INFO L87 Difference]: Start difference. First operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3555 states and 5213 transitions. [2022-02-21 04:24:57,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:24:57,428 INFO L93 Difference]: Finished difference Result 3555 states and 5213 transitions. [2022-02-21 04:24:57,428 INFO L276 IsEmpty]: Start isEmpty. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:57,431 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:24:57,431 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:24:57,431 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:24:57,432 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:24:57,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3555 states, 3555 states have (on average 1.4663853727144867) internal successors, (5213), 3554 states have internal predecessors, (5213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:24:57,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3555 states to 3555 states and 5213 transitions. [2022-02-21 04:24:57,708 INFO L704 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-02-21 04:24:57,708 INFO L587 BuchiCegarLoop]: Abstraction has 3555 states and 5213 transitions. [2022-02-21 04:24:57,708 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:24:57,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3555 states and 5213 transitions. [2022-02-21 04:24:57,717 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3382 [2022-02-21 04:24:57,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:24:57,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:24:57,719 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:57,719 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:24:57,719 INFO L791 eck$LassoCheckResult]: Stem: 106001#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 106002#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 105820#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 105535#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105536#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 106719#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106720#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105672#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105673#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 106128#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105963#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 105964#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 105739#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 105740#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 106139#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 106320#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 106472#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 106509#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 105750#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105751#L1258 assume !(0 == ~M_E~0); 106956#L1258-2 assume !(0 == ~T1_E~0); 106046#L1263-1 assume !(0 == ~T2_E~0); 106047#L1268-1 assume !(0 == ~T3_E~0); 106354#L1273-1 assume !(0 == ~T4_E~0); 106935#L1278-1 assume !(0 == ~T5_E~0); 106777#L1283-1 assume !(0 == ~T6_E~0); 106778#L1288-1 assume !(0 == ~T7_E~0); 107059#L1293-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 107045#L1298-1 assume !(0 == ~T9_E~0); 106950#L1303-1 assume !(0 == ~T10_E~0); 105565#L1308-1 assume !(0 == ~T11_E~0); 105506#L1313-1 assume !(0 == ~T12_E~0); 105507#L1318-1 assume !(0 == ~T13_E~0); 105513#L1323-1 assume !(0 == ~E_1~0); 105514#L1328-1 assume !(0 == ~E_2~0); 105682#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 106646#L1338-1 assume !(0 == ~E_4~0); 106647#L1343-1 assume !(0 == ~E_5~0); 106750#L1348-1 assume !(0 == ~E_6~0); 107092#L1353-1 assume !(0 == ~E_7~0); 106373#L1358-1 assume !(0 == ~E_8~0); 106374#L1363-1 assume !(0 == ~E_9~0); 106665#L1368-1 assume !(0 == ~E_10~0); 105342#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 105343#L1378-1 assume !(0 == ~E_12~0); 105631#L1383-1 assume !(0 == ~E_13~0); 105632#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106379#L607 assume !(1 == ~m_pc~0); 105701#L607-2 is_master_triggered_~__retres1~0#1 := 0; 105702#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106748#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 106299#L1560 assume !(0 != activate_threads_~tmp~1#1); 106300#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105526#L626 assume !(1 == ~t1_pc~0); 105527#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105796#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 105797#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 105967#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 105425#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105426#L645 assume 1 == ~t2_pc~0; 105543#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 105500#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106179#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 106180#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 106274#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106275#L664 assume 1 == ~t3_pc~0; 107089#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 105265#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105266#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 105928#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 105929#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106967#L683 assume !(1 == ~t4_pc~0); 106494#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 106446#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106447#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 106481#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 106607#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106222#L702 assume 1 == ~t5_pc~0; 106223#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 106148#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106602#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 106920#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 106852#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 105314#L721 assume !(1 == ~t6_pc~0); 105287#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 105288#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 105452#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 105937#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 105938#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 106542#L740 assume 1 == ~t7_pc~0; 105363#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 105175#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 105176#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 105165#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 105166#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 105873#L759 assume !(1 == ~t8_pc~0); 105874#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 105903#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 106600#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 106601#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 106733#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 107058#L778 assume 1 == ~t9_pc~0; 106917#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 105341#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 105280#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 105209#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 105210#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 105539#L797 assume !(1 == ~t10_pc~0); 105540#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 105659#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 106805#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 106044#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 106045#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 106338#L816 assume 1 == ~t11_pc~0; 105245#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 105246#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 106005#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 105944#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 105945#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 106471#L835 assume 1 == ~t12_pc~0; 106351#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 105410#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 105432#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 105575#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 106101#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 106102#L854 assume !(1 == ~t13_pc~0); 105741#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 105742#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 105792#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 105450#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 105451#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106847#L1401 assume !(1 == ~M_E~0); 105932#L1401-2 assume !(1 == ~T1_E~0); 105933#L1406-1 assume !(1 == ~T2_E~0); 106531#L1411-1 assume !(1 == ~T3_E~0); 106532#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106195#L1421-1 assume !(1 == ~T5_E~0); 105737#L1426-1 assume !(1 == ~T6_E~0); 105738#L1431-1 assume !(1 == ~T7_E~0); 105283#L1436-1 assume !(1 == ~T8_E~0); 105284#L1441-1 assume !(1 == ~T9_E~0); 106035#L1446-1 assume !(1 == ~T10_E~0); 106036#L1451-1 assume !(1 == ~T11_E~0); 106747#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 106397#L1461-1 assume !(1 == ~T13_E~0); 105956#L1466-1 assume !(1 == ~E_1~0); 105957#L1471-1 assume !(1 == ~E_2~0); 106731#L1476-1 assume !(1 == ~E_3~0); 106732#L1481-1 assume !(1 == ~E_4~0); 106897#L1486-1 assume !(1 == ~E_5~0); 105580#L1491-1 assume !(1 == ~E_6~0); 105217#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 105218#L1501-1 assume !(1 == ~E_8~0); 106033#L1506-1 assume !(1 == ~E_9~0); 106034#L1511-1 assume !(1 == ~E_10~0); 105990#L1516-1 assume !(1 == ~E_11~0); 105161#L1521-1 assume !(1 == ~E_12~0); 105162#L1526-1 assume !(1 == ~E_13~0); 105216#L1531-1 assume { :end_inline_reset_delta_events } true; 105762#L1892-2 [2022-02-21 04:24:57,719 INFO L793 eck$LassoCheckResult]: Loop: 105762#L1892-2 assume !false; 107148#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 107030#L1233 assume !false; 107031#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 106302#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 106281#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 106439#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 105259#L1046 assume !(0 != eval_~tmp~0#1); 105261#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 108530#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 108529#L1258-3 assume !(0 == ~M_E~0); 108528#L1258-5 assume !(0 == ~T1_E~0); 108527#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 108526#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 108525#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 108524#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 108523#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 108522#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 108521#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 108520#L1298-3 assume !(0 == ~T9_E~0); 108519#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 108518#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 108517#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 108516#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 108515#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 108514#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 108232#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 108231#L1338-3 assume !(0 == ~E_4~0); 108203#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 108202#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 108200#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 108198#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 108195#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 108193#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 108191#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 108189#L1378-3 assume !(0 == ~E_12~0); 108187#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 108185#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108182#L607-42 assume !(1 == ~m_pc~0); 108179#L607-44 is_master_triggered_~__retres1~0#1 := 0; 108177#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108175#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 108173#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 108171#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108168#L626-42 assume 1 == ~t1_pc~0; 108165#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 108163#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108162#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 108161#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 108160#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108159#L645-42 assume !(1 == ~t2_pc~0); 108157#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 108156#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108155#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 108154#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 108153#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108152#L664-42 assume !(1 == ~t3_pc~0); 108151#L664-44 is_transmit3_triggered_~__retres1~3#1 := 0; 108149#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108148#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 108147#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 108146#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108145#L683-42 assume 1 == ~t4_pc~0; 108141#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 108138#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108135#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 108133#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 108131#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 108129#L702-42 assume !(1 == ~t5_pc~0); 108127#L702-44 is_transmit5_triggered_~__retres1~5#1 := 0; 108124#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108123#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 108122#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 108076#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 108075#L721-42 assume 1 == ~t6_pc~0; 108073#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 108070#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 108067#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 108065#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 108053#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 108050#L740-42 assume !(1 == ~t7_pc~0); 108048#L740-44 is_transmit7_triggered_~__retres1~7#1 := 0; 108045#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 108043#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 108041#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 108040#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 108039#L759-42 assume 1 == ~t8_pc~0; 108037#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 108036#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 106307#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 106131#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 106132#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 106227#L778-42 assume !(1 == ~t9_pc~0); 106065#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 106066#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 106478#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 106384#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 106385#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 108023#L797-42 assume !(1 == ~t10_pc~0); 108021#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 108018#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 108015#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 108014#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 108013#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 108012#L816-42 assume 1 == ~t11_pc~0; 108011#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 108009#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 108008#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 108006#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 108004#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 107673#L835-42 assume 1 == ~t12_pc~0; 107671#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 106855#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 105752#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 105753#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 106851#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 106624#L854-42 assume 1 == ~t13_pc~0; 106625#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 105696#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 105304#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 105305#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 105954#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105955#L1401-3 assume !(1 == ~M_E~0); 106738#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 105542#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 105405#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 105406#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106008#L1421-3 assume !(1 == ~T5_E~0); 106009#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 105583#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 105584#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 105167#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 105168#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 106768#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 106092#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 105744#L1461-3 assume !(1 == ~T13_E~0); 105745#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 107642#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 107641#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 107640#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 107639#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107638#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 107010#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 106126#L1501-3 assume !(1 == ~E_8~0); 106127#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 107636#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 107635#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 107634#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 107633#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 107632#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 107525#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 107518#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 107516#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 107514#L1911 assume !(0 == start_simulation_~tmp~3#1); 106888#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 106581#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 105643#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 106517#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 105346#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 105347#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 105578#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 105579#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 105762#L1892-2 [2022-02-21 04:24:57,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:57,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1486214853, now seen corresponding path program 1 times [2022-02-21 04:24:57,720 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:57,720 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1211492129] [2022-02-21 04:24:57,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:57,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:57,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:57,764 INFO L290 TraceCheckUtils]: 0: Hoare triple {115804#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,765 INFO L290 TraceCheckUtils]: 1: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,765 INFO L290 TraceCheckUtils]: 2: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,765 INFO L290 TraceCheckUtils]: 3: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,766 INFO L290 TraceCheckUtils]: 4: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,766 INFO L290 TraceCheckUtils]: 5: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,766 INFO L290 TraceCheckUtils]: 6: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,767 INFO L290 TraceCheckUtils]: 7: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,767 INFO L290 TraceCheckUtils]: 8: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,767 INFO L290 TraceCheckUtils]: 9: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,768 INFO L290 TraceCheckUtils]: 10: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,768 INFO L290 TraceCheckUtils]: 11: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,768 INFO L290 TraceCheckUtils]: 12: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,769 INFO L290 TraceCheckUtils]: 13: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,769 INFO L290 TraceCheckUtils]: 14: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,769 INFO L290 TraceCheckUtils]: 15: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,770 INFO L290 TraceCheckUtils]: 16: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,770 INFO L290 TraceCheckUtils]: 17: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,770 INFO L290 TraceCheckUtils]: 18: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,771 INFO L290 TraceCheckUtils]: 19: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume !(0 == ~M_E~0); {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,771 INFO L290 TraceCheckUtils]: 20: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume !(0 == ~T1_E~0); {115806#(= ~T2_E~0 ~T8_E~0)} is VALID [2022-02-21 04:24:57,771 INFO L290 TraceCheckUtils]: 21: Hoare triple {115806#(= ~T2_E~0 ~T8_E~0)} assume !(0 == ~T2_E~0); {115807#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:57,772 INFO L290 TraceCheckUtils]: 22: Hoare triple {115807#(not (= ~T8_E~0 0))} assume !(0 == ~T3_E~0); {115807#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:57,772 INFO L290 TraceCheckUtils]: 23: Hoare triple {115807#(not (= ~T8_E~0 0))} assume !(0 == ~T4_E~0); {115807#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:57,772 INFO L290 TraceCheckUtils]: 24: Hoare triple {115807#(not (= ~T8_E~0 0))} assume !(0 == ~T5_E~0); {115807#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:57,773 INFO L290 TraceCheckUtils]: 25: Hoare triple {115807#(not (= ~T8_E~0 0))} assume !(0 == ~T6_E~0); {115807#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:57,773 INFO L290 TraceCheckUtils]: 26: Hoare triple {115807#(not (= ~T8_E~0 0))} assume !(0 == ~T7_E~0); {115807#(not (= ~T8_E~0 0))} is VALID [2022-02-21 04:24:57,773 INFO L290 TraceCheckUtils]: 27: Hoare triple {115807#(not (= ~T8_E~0 0))} assume 0 == ~T8_E~0;~T8_E~0 := 1; {115805#false} is VALID [2022-02-21 04:24:57,774 INFO L290 TraceCheckUtils]: 28: Hoare triple {115805#false} assume !(0 == ~T9_E~0); {115805#false} is VALID [2022-02-21 04:24:57,774 INFO L290 TraceCheckUtils]: 29: Hoare triple {115805#false} assume !(0 == ~T10_E~0); {115805#false} is VALID [2022-02-21 04:24:57,774 INFO L290 TraceCheckUtils]: 30: Hoare triple {115805#false} assume !(0 == ~T11_E~0); {115805#false} is VALID [2022-02-21 04:24:57,774 INFO L290 TraceCheckUtils]: 31: Hoare triple {115805#false} assume !(0 == ~T12_E~0); {115805#false} is VALID [2022-02-21 04:24:57,774 INFO L290 TraceCheckUtils]: 32: Hoare triple {115805#false} assume !(0 == ~T13_E~0); {115805#false} is VALID [2022-02-21 04:24:57,774 INFO L290 TraceCheckUtils]: 33: Hoare triple {115805#false} assume !(0 == ~E_1~0); {115805#false} is VALID [2022-02-21 04:24:57,774 INFO L290 TraceCheckUtils]: 34: Hoare triple {115805#false} assume !(0 == ~E_2~0); {115805#false} is VALID [2022-02-21 04:24:57,775 INFO L290 TraceCheckUtils]: 35: Hoare triple {115805#false} assume 0 == ~E_3~0;~E_3~0 := 1; {115805#false} is VALID [2022-02-21 04:24:57,775 INFO L290 TraceCheckUtils]: 36: Hoare triple {115805#false} assume !(0 == ~E_4~0); {115805#false} is VALID [2022-02-21 04:24:57,775 INFO L290 TraceCheckUtils]: 37: Hoare triple {115805#false} assume !(0 == ~E_5~0); {115805#false} is VALID [2022-02-21 04:24:57,775 INFO L290 TraceCheckUtils]: 38: Hoare triple {115805#false} assume !(0 == ~E_6~0); {115805#false} is VALID [2022-02-21 04:24:57,775 INFO L290 TraceCheckUtils]: 39: Hoare triple {115805#false} assume !(0 == ~E_7~0); {115805#false} is VALID [2022-02-21 04:24:57,775 INFO L290 TraceCheckUtils]: 40: Hoare triple {115805#false} assume !(0 == ~E_8~0); {115805#false} is VALID [2022-02-21 04:24:57,775 INFO L290 TraceCheckUtils]: 41: Hoare triple {115805#false} assume !(0 == ~E_9~0); {115805#false} is VALID [2022-02-21 04:24:57,776 INFO L290 TraceCheckUtils]: 42: Hoare triple {115805#false} assume !(0 == ~E_10~0); {115805#false} is VALID [2022-02-21 04:24:57,776 INFO L290 TraceCheckUtils]: 43: Hoare triple {115805#false} assume 0 == ~E_11~0;~E_11~0 := 1; {115805#false} is VALID [2022-02-21 04:24:57,776 INFO L290 TraceCheckUtils]: 44: Hoare triple {115805#false} assume !(0 == ~E_12~0); {115805#false} is VALID [2022-02-21 04:24:57,776 INFO L290 TraceCheckUtils]: 45: Hoare triple {115805#false} assume !(0 == ~E_13~0); {115805#false} is VALID [2022-02-21 04:24:57,776 INFO L290 TraceCheckUtils]: 46: Hoare triple {115805#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {115805#false} is VALID [2022-02-21 04:24:57,776 INFO L290 TraceCheckUtils]: 47: Hoare triple {115805#false} assume !(1 == ~m_pc~0); {115805#false} is VALID [2022-02-21 04:24:57,776 INFO L290 TraceCheckUtils]: 48: Hoare triple {115805#false} is_master_triggered_~__retres1~0#1 := 0; {115805#false} is VALID [2022-02-21 04:24:57,776 INFO L290 TraceCheckUtils]: 49: Hoare triple {115805#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {115805#false} is VALID [2022-02-21 04:24:57,777 INFO L290 TraceCheckUtils]: 50: Hoare triple {115805#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {115805#false} is VALID [2022-02-21 04:24:57,777 INFO L290 TraceCheckUtils]: 51: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp~1#1); {115805#false} is VALID [2022-02-21 04:24:57,777 INFO L290 TraceCheckUtils]: 52: Hoare triple {115805#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {115805#false} is VALID [2022-02-21 04:24:57,777 INFO L290 TraceCheckUtils]: 53: Hoare triple {115805#false} assume !(1 == ~t1_pc~0); {115805#false} is VALID [2022-02-21 04:24:57,777 INFO L290 TraceCheckUtils]: 54: Hoare triple {115805#false} is_transmit1_triggered_~__retres1~1#1 := 0; {115805#false} is VALID [2022-02-21 04:24:57,777 INFO L290 TraceCheckUtils]: 55: Hoare triple {115805#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {115805#false} is VALID [2022-02-21 04:24:57,777 INFO L290 TraceCheckUtils]: 56: Hoare triple {115805#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {115805#false} is VALID [2022-02-21 04:24:57,777 INFO L290 TraceCheckUtils]: 57: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp___0~0#1); {115805#false} is VALID [2022-02-21 04:24:57,778 INFO L290 TraceCheckUtils]: 58: Hoare triple {115805#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {115805#false} is VALID [2022-02-21 04:24:57,778 INFO L290 TraceCheckUtils]: 59: Hoare triple {115805#false} assume 1 == ~t2_pc~0; {115805#false} is VALID [2022-02-21 04:24:57,778 INFO L290 TraceCheckUtils]: 60: Hoare triple {115805#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {115805#false} is VALID [2022-02-21 04:24:57,778 INFO L290 TraceCheckUtils]: 61: Hoare triple {115805#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {115805#false} is VALID [2022-02-21 04:24:57,778 INFO L290 TraceCheckUtils]: 62: Hoare triple {115805#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {115805#false} is VALID [2022-02-21 04:24:57,778 INFO L290 TraceCheckUtils]: 63: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp___1~0#1); {115805#false} is VALID [2022-02-21 04:24:57,778 INFO L290 TraceCheckUtils]: 64: Hoare triple {115805#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {115805#false} is VALID [2022-02-21 04:24:57,779 INFO L290 TraceCheckUtils]: 65: Hoare triple {115805#false} assume 1 == ~t3_pc~0; {115805#false} is VALID [2022-02-21 04:24:57,779 INFO L290 TraceCheckUtils]: 66: Hoare triple {115805#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {115805#false} is VALID [2022-02-21 04:24:57,779 INFO L290 TraceCheckUtils]: 67: Hoare triple {115805#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {115805#false} is VALID [2022-02-21 04:24:57,779 INFO L290 TraceCheckUtils]: 68: Hoare triple {115805#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {115805#false} is VALID [2022-02-21 04:24:57,779 INFO L290 TraceCheckUtils]: 69: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp___2~0#1); {115805#false} is VALID [2022-02-21 04:24:57,779 INFO L290 TraceCheckUtils]: 70: Hoare triple {115805#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {115805#false} is VALID [2022-02-21 04:24:57,779 INFO L290 TraceCheckUtils]: 71: Hoare triple {115805#false} assume !(1 == ~t4_pc~0); {115805#false} is VALID [2022-02-21 04:24:57,779 INFO L290 TraceCheckUtils]: 72: Hoare triple {115805#false} is_transmit4_triggered_~__retres1~4#1 := 0; {115805#false} is VALID [2022-02-21 04:24:57,780 INFO L290 TraceCheckUtils]: 73: Hoare triple {115805#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {115805#false} is VALID [2022-02-21 04:24:57,780 INFO L290 TraceCheckUtils]: 74: Hoare triple {115805#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {115805#false} is VALID [2022-02-21 04:24:57,780 INFO L290 TraceCheckUtils]: 75: Hoare triple {115805#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {115805#false} is VALID [2022-02-21 04:24:57,780 INFO L290 TraceCheckUtils]: 76: Hoare triple {115805#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {115805#false} is VALID [2022-02-21 04:24:57,780 INFO L290 TraceCheckUtils]: 77: Hoare triple {115805#false} assume 1 == ~t5_pc~0; {115805#false} is VALID [2022-02-21 04:24:57,780 INFO L290 TraceCheckUtils]: 78: Hoare triple {115805#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {115805#false} is VALID [2022-02-21 04:24:57,780 INFO L290 TraceCheckUtils]: 79: Hoare triple {115805#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {115805#false} is VALID [2022-02-21 04:24:57,781 INFO L290 TraceCheckUtils]: 80: Hoare triple {115805#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {115805#false} is VALID [2022-02-21 04:24:57,781 INFO L290 TraceCheckUtils]: 81: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp___4~0#1); {115805#false} is VALID [2022-02-21 04:24:57,781 INFO L290 TraceCheckUtils]: 82: Hoare triple {115805#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {115805#false} is VALID [2022-02-21 04:24:57,781 INFO L290 TraceCheckUtils]: 83: Hoare triple {115805#false} assume !(1 == ~t6_pc~0); {115805#false} is VALID [2022-02-21 04:24:57,781 INFO L290 TraceCheckUtils]: 84: Hoare triple {115805#false} is_transmit6_triggered_~__retres1~6#1 := 0; {115805#false} is VALID [2022-02-21 04:24:57,781 INFO L290 TraceCheckUtils]: 85: Hoare triple {115805#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {115805#false} is VALID [2022-02-21 04:24:57,781 INFO L290 TraceCheckUtils]: 86: Hoare triple {115805#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {115805#false} is VALID [2022-02-21 04:24:57,782 INFO L290 TraceCheckUtils]: 87: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp___5~0#1); {115805#false} is VALID [2022-02-21 04:24:57,782 INFO L290 TraceCheckUtils]: 88: Hoare triple {115805#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {115805#false} is VALID [2022-02-21 04:24:57,782 INFO L290 TraceCheckUtils]: 89: Hoare triple {115805#false} assume 1 == ~t7_pc~0; {115805#false} is VALID [2022-02-21 04:24:57,782 INFO L290 TraceCheckUtils]: 90: Hoare triple {115805#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {115805#false} is VALID [2022-02-21 04:24:57,782 INFO L290 TraceCheckUtils]: 91: Hoare triple {115805#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {115805#false} is VALID [2022-02-21 04:24:57,782 INFO L290 TraceCheckUtils]: 92: Hoare triple {115805#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {115805#false} is VALID [2022-02-21 04:24:57,782 INFO L290 TraceCheckUtils]: 93: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp___6~0#1); {115805#false} is VALID [2022-02-21 04:24:57,782 INFO L290 TraceCheckUtils]: 94: Hoare triple {115805#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {115805#false} is VALID [2022-02-21 04:24:57,783 INFO L290 TraceCheckUtils]: 95: Hoare triple {115805#false} assume !(1 == ~t8_pc~0); {115805#false} is VALID [2022-02-21 04:24:57,783 INFO L290 TraceCheckUtils]: 96: Hoare triple {115805#false} is_transmit8_triggered_~__retres1~8#1 := 0; {115805#false} is VALID [2022-02-21 04:24:57,783 INFO L290 TraceCheckUtils]: 97: Hoare triple {115805#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {115805#false} is VALID [2022-02-21 04:24:57,783 INFO L290 TraceCheckUtils]: 98: Hoare triple {115805#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {115805#false} is VALID [2022-02-21 04:24:57,783 INFO L290 TraceCheckUtils]: 99: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp___7~0#1); {115805#false} is VALID [2022-02-21 04:24:57,783 INFO L290 TraceCheckUtils]: 100: Hoare triple {115805#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {115805#false} is VALID [2022-02-21 04:24:57,783 INFO L290 TraceCheckUtils]: 101: Hoare triple {115805#false} assume 1 == ~t9_pc~0; {115805#false} is VALID [2022-02-21 04:24:57,784 INFO L290 TraceCheckUtils]: 102: Hoare triple {115805#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {115805#false} is VALID [2022-02-21 04:24:57,784 INFO L290 TraceCheckUtils]: 103: Hoare triple {115805#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {115805#false} is VALID [2022-02-21 04:24:57,784 INFO L290 TraceCheckUtils]: 104: Hoare triple {115805#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {115805#false} is VALID [2022-02-21 04:24:57,784 INFO L290 TraceCheckUtils]: 105: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp___8~0#1); {115805#false} is VALID [2022-02-21 04:24:57,784 INFO L290 TraceCheckUtils]: 106: Hoare triple {115805#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {115805#false} is VALID [2022-02-21 04:24:57,784 INFO L290 TraceCheckUtils]: 107: Hoare triple {115805#false} assume !(1 == ~t10_pc~0); {115805#false} is VALID [2022-02-21 04:24:57,784 INFO L290 TraceCheckUtils]: 108: Hoare triple {115805#false} is_transmit10_triggered_~__retres1~10#1 := 0; {115805#false} is VALID [2022-02-21 04:24:57,785 INFO L290 TraceCheckUtils]: 109: Hoare triple {115805#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {115805#false} is VALID [2022-02-21 04:24:57,785 INFO L290 TraceCheckUtils]: 110: Hoare triple {115805#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {115805#false} is VALID [2022-02-21 04:24:57,785 INFO L290 TraceCheckUtils]: 111: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp___9~0#1); {115805#false} is VALID [2022-02-21 04:24:57,785 INFO L290 TraceCheckUtils]: 112: Hoare triple {115805#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {115805#false} is VALID [2022-02-21 04:24:57,785 INFO L290 TraceCheckUtils]: 113: Hoare triple {115805#false} assume 1 == ~t11_pc~0; {115805#false} is VALID [2022-02-21 04:24:57,785 INFO L290 TraceCheckUtils]: 114: Hoare triple {115805#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {115805#false} is VALID [2022-02-21 04:24:57,785 INFO L290 TraceCheckUtils]: 115: Hoare triple {115805#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {115805#false} is VALID [2022-02-21 04:24:57,785 INFO L290 TraceCheckUtils]: 116: Hoare triple {115805#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {115805#false} is VALID [2022-02-21 04:24:57,786 INFO L290 TraceCheckUtils]: 117: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp___10~0#1); {115805#false} is VALID [2022-02-21 04:24:57,786 INFO L290 TraceCheckUtils]: 118: Hoare triple {115805#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {115805#false} is VALID [2022-02-21 04:24:57,786 INFO L290 TraceCheckUtils]: 119: Hoare triple {115805#false} assume 1 == ~t12_pc~0; {115805#false} is VALID [2022-02-21 04:24:57,786 INFO L290 TraceCheckUtils]: 120: Hoare triple {115805#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {115805#false} is VALID [2022-02-21 04:24:57,786 INFO L290 TraceCheckUtils]: 121: Hoare triple {115805#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {115805#false} is VALID [2022-02-21 04:24:57,786 INFO L290 TraceCheckUtils]: 122: Hoare triple {115805#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {115805#false} is VALID [2022-02-21 04:24:57,786 INFO L290 TraceCheckUtils]: 123: Hoare triple {115805#false} assume !(0 != activate_threads_~tmp___11~0#1); {115805#false} is VALID [2022-02-21 04:24:57,787 INFO L290 TraceCheckUtils]: 124: Hoare triple {115805#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {115805#false} is VALID [2022-02-21 04:24:57,787 INFO L290 TraceCheckUtils]: 125: Hoare triple {115805#false} assume !(1 == ~t13_pc~0); {115805#false} is VALID [2022-02-21 04:24:57,787 INFO L290 TraceCheckUtils]: 126: Hoare triple {115805#false} is_transmit13_triggered_~__retres1~13#1 := 0; {115805#false} is VALID [2022-02-21 04:24:57,787 INFO L290 TraceCheckUtils]: 127: Hoare triple {115805#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {115805#false} is VALID [2022-02-21 04:24:57,787 INFO L290 TraceCheckUtils]: 128: Hoare triple {115805#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {115805#false} is VALID [2022-02-21 04:24:57,787 INFO L290 TraceCheckUtils]: 129: Hoare triple {115805#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {115805#false} is VALID [2022-02-21 04:24:57,787 INFO L290 TraceCheckUtils]: 130: Hoare triple {115805#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {115805#false} is VALID [2022-02-21 04:24:57,787 INFO L290 TraceCheckUtils]: 131: Hoare triple {115805#false} assume !(1 == ~M_E~0); {115805#false} is VALID [2022-02-21 04:24:57,788 INFO L290 TraceCheckUtils]: 132: Hoare triple {115805#false} assume !(1 == ~T1_E~0); {115805#false} is VALID [2022-02-21 04:24:57,788 INFO L290 TraceCheckUtils]: 133: Hoare triple {115805#false} assume !(1 == ~T2_E~0); {115805#false} is VALID [2022-02-21 04:24:57,788 INFO L290 TraceCheckUtils]: 134: Hoare triple {115805#false} assume !(1 == ~T3_E~0); {115805#false} is VALID [2022-02-21 04:24:57,788 INFO L290 TraceCheckUtils]: 135: Hoare triple {115805#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {115805#false} is VALID [2022-02-21 04:24:57,788 INFO L290 TraceCheckUtils]: 136: Hoare triple {115805#false} assume !(1 == ~T5_E~0); {115805#false} is VALID [2022-02-21 04:24:57,788 INFO L290 TraceCheckUtils]: 137: Hoare triple {115805#false} assume !(1 == ~T6_E~0); {115805#false} is VALID [2022-02-21 04:24:57,788 INFO L290 TraceCheckUtils]: 138: Hoare triple {115805#false} assume !(1 == ~T7_E~0); {115805#false} is VALID [2022-02-21 04:24:57,789 INFO L290 TraceCheckUtils]: 139: Hoare triple {115805#false} assume !(1 == ~T8_E~0); {115805#false} is VALID [2022-02-21 04:24:57,789 INFO L290 TraceCheckUtils]: 140: Hoare triple {115805#false} assume !(1 == ~T9_E~0); {115805#false} is VALID [2022-02-21 04:24:57,789 INFO L290 TraceCheckUtils]: 141: Hoare triple {115805#false} assume !(1 == ~T10_E~0); {115805#false} is VALID [2022-02-21 04:24:57,789 INFO L290 TraceCheckUtils]: 142: Hoare triple {115805#false} assume !(1 == ~T11_E~0); {115805#false} is VALID [2022-02-21 04:24:57,789 INFO L290 TraceCheckUtils]: 143: Hoare triple {115805#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {115805#false} is VALID [2022-02-21 04:24:57,789 INFO L290 TraceCheckUtils]: 144: Hoare triple {115805#false} assume !(1 == ~T13_E~0); {115805#false} is VALID [2022-02-21 04:24:57,789 INFO L290 TraceCheckUtils]: 145: Hoare triple {115805#false} assume !(1 == ~E_1~0); {115805#false} is VALID [2022-02-21 04:24:57,789 INFO L290 TraceCheckUtils]: 146: Hoare triple {115805#false} assume !(1 == ~E_2~0); {115805#false} is VALID [2022-02-21 04:24:57,790 INFO L290 TraceCheckUtils]: 147: Hoare triple {115805#false} assume !(1 == ~E_3~0); {115805#false} is VALID [2022-02-21 04:24:57,790 INFO L290 TraceCheckUtils]: 148: Hoare triple {115805#false} assume !(1 == ~E_4~0); {115805#false} is VALID [2022-02-21 04:24:57,790 INFO L290 TraceCheckUtils]: 149: Hoare triple {115805#false} assume !(1 == ~E_5~0); {115805#false} is VALID [2022-02-21 04:24:57,790 INFO L290 TraceCheckUtils]: 150: Hoare triple {115805#false} assume !(1 == ~E_6~0); {115805#false} is VALID [2022-02-21 04:24:57,790 INFO L290 TraceCheckUtils]: 151: Hoare triple {115805#false} assume 1 == ~E_7~0;~E_7~0 := 2; {115805#false} is VALID [2022-02-21 04:24:57,790 INFO L290 TraceCheckUtils]: 152: Hoare triple {115805#false} assume !(1 == ~E_8~0); {115805#false} is VALID [2022-02-21 04:24:57,790 INFO L290 TraceCheckUtils]: 153: Hoare triple {115805#false} assume !(1 == ~E_9~0); {115805#false} is VALID [2022-02-21 04:24:57,791 INFO L290 TraceCheckUtils]: 154: Hoare triple {115805#false} assume !(1 == ~E_10~0); {115805#false} is VALID [2022-02-21 04:24:57,791 INFO L290 TraceCheckUtils]: 155: Hoare triple {115805#false} assume !(1 == ~E_11~0); {115805#false} is VALID [2022-02-21 04:24:57,791 INFO L290 TraceCheckUtils]: 156: Hoare triple {115805#false} assume !(1 == ~E_12~0); {115805#false} is VALID [2022-02-21 04:24:57,791 INFO L290 TraceCheckUtils]: 157: Hoare triple {115805#false} assume !(1 == ~E_13~0); {115805#false} is VALID [2022-02-21 04:24:57,791 INFO L290 TraceCheckUtils]: 158: Hoare triple {115805#false} assume { :end_inline_reset_delta_events } true; {115805#false} is VALID [2022-02-21 04:24:57,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:57,792 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:57,792 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1211492129] [2022-02-21 04:24:57,792 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1211492129] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:57,792 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:57,792 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:57,792 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1305076823] [2022-02-21 04:24:57,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:57,793 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:24:57,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:24:57,793 INFO L85 PathProgramCache]: Analyzing trace with hash 1924037592, now seen corresponding path program 1 times [2022-02-21 04:24:57,794 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:24:57,794 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079613908] [2022-02-21 04:24:57,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:24:57,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:24:57,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:24:57,831 INFO L290 TraceCheckUtils]: 0: Hoare triple {115808#true} assume !false; {115808#true} is VALID [2022-02-21 04:24:57,832 INFO L290 TraceCheckUtils]: 1: Hoare triple {115808#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {115808#true} is VALID [2022-02-21 04:24:57,832 INFO L290 TraceCheckUtils]: 2: Hoare triple {115808#true} assume !false; {115808#true} is VALID [2022-02-21 04:24:57,832 INFO L290 TraceCheckUtils]: 3: Hoare triple {115808#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {115808#true} is VALID [2022-02-21 04:24:57,832 INFO L290 TraceCheckUtils]: 4: Hoare triple {115808#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {115808#true} is VALID [2022-02-21 04:24:57,832 INFO L290 TraceCheckUtils]: 5: Hoare triple {115808#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {115808#true} is VALID [2022-02-21 04:24:57,832 INFO L290 TraceCheckUtils]: 6: Hoare triple {115808#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {115808#true} is VALID [2022-02-21 04:24:57,832 INFO L290 TraceCheckUtils]: 7: Hoare triple {115808#true} assume !(0 != eval_~tmp~0#1); {115808#true} is VALID [2022-02-21 04:24:57,833 INFO L290 TraceCheckUtils]: 8: Hoare triple {115808#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {115808#true} is VALID [2022-02-21 04:24:57,833 INFO L290 TraceCheckUtils]: 9: Hoare triple {115808#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {115808#true} is VALID [2022-02-21 04:24:57,833 INFO L290 TraceCheckUtils]: 10: Hoare triple {115808#true} assume !(0 == ~M_E~0); {115808#true} is VALID [2022-02-21 04:24:57,833 INFO L290 TraceCheckUtils]: 11: Hoare triple {115808#true} assume !(0 == ~T1_E~0); {115808#true} is VALID [2022-02-21 04:24:57,833 INFO L290 TraceCheckUtils]: 12: Hoare triple {115808#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {115808#true} is VALID [2022-02-21 04:24:57,833 INFO L290 TraceCheckUtils]: 13: Hoare triple {115808#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {115808#true} is VALID [2022-02-21 04:24:57,833 INFO L290 TraceCheckUtils]: 14: Hoare triple {115808#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {115808#true} is VALID [2022-02-21 04:24:57,834 INFO L290 TraceCheckUtils]: 15: Hoare triple {115808#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,834 INFO L290 TraceCheckUtils]: 16: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,835 INFO L290 TraceCheckUtils]: 17: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,835 INFO L290 TraceCheckUtils]: 18: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T8_E~0;~T8_E~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,835 INFO L290 TraceCheckUtils]: 19: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,836 INFO L290 TraceCheckUtils]: 20: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,836 INFO L290 TraceCheckUtils]: 21: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,837 INFO L290 TraceCheckUtils]: 22: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,837 INFO L290 TraceCheckUtils]: 23: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,837 INFO L290 TraceCheckUtils]: 24: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,838 INFO L290 TraceCheckUtils]: 25: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,838 INFO L290 TraceCheckUtils]: 26: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,838 INFO L290 TraceCheckUtils]: 27: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,839 INFO L290 TraceCheckUtils]: 28: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,839 INFO L290 TraceCheckUtils]: 29: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,840 INFO L290 TraceCheckUtils]: 30: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,840 INFO L290 TraceCheckUtils]: 31: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,840 INFO L290 TraceCheckUtils]: 32: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,841 INFO L290 TraceCheckUtils]: 33: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,841 INFO L290 TraceCheckUtils]: 34: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,841 INFO L290 TraceCheckUtils]: 35: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,842 INFO L290 TraceCheckUtils]: 36: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,842 INFO L290 TraceCheckUtils]: 37: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,842 INFO L290 TraceCheckUtils]: 38: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,843 INFO L290 TraceCheckUtils]: 39: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,843 INFO L290 TraceCheckUtils]: 40: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,844 INFO L290 TraceCheckUtils]: 41: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,844 INFO L290 TraceCheckUtils]: 42: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,844 INFO L290 TraceCheckUtils]: 43: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,845 INFO L290 TraceCheckUtils]: 44: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t1_pc~0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,845 INFO L290 TraceCheckUtils]: 45: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,845 INFO L290 TraceCheckUtils]: 46: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,846 INFO L290 TraceCheckUtils]: 47: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,846 INFO L290 TraceCheckUtils]: 48: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,847 INFO L290 TraceCheckUtils]: 49: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,847 INFO L290 TraceCheckUtils]: 50: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,847 INFO L290 TraceCheckUtils]: 51: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,848 INFO L290 TraceCheckUtils]: 52: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,848 INFO L290 TraceCheckUtils]: 53: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,848 INFO L290 TraceCheckUtils]: 54: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,849 INFO L290 TraceCheckUtils]: 55: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,849 INFO L290 TraceCheckUtils]: 56: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t3_pc~0); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,850 INFO L290 TraceCheckUtils]: 57: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,850 INFO L290 TraceCheckUtils]: 58: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,850 INFO L290 TraceCheckUtils]: 59: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,851 INFO L290 TraceCheckUtils]: 60: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,851 INFO L290 TraceCheckUtils]: 61: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,851 INFO L290 TraceCheckUtils]: 62: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,852 INFO L290 TraceCheckUtils]: 63: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,852 INFO L290 TraceCheckUtils]: 64: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,853 INFO L290 TraceCheckUtils]: 65: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,853 INFO L290 TraceCheckUtils]: 66: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,853 INFO L290 TraceCheckUtils]: 67: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,854 INFO L290 TraceCheckUtils]: 68: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t5_pc~0); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,854 INFO L290 TraceCheckUtils]: 69: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,855 INFO L290 TraceCheckUtils]: 70: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,855 INFO L290 TraceCheckUtils]: 71: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,855 INFO L290 TraceCheckUtils]: 72: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,856 INFO L290 TraceCheckUtils]: 73: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,856 INFO L290 TraceCheckUtils]: 74: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t6_pc~0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,856 INFO L290 TraceCheckUtils]: 75: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,857 INFO L290 TraceCheckUtils]: 76: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,857 INFO L290 TraceCheckUtils]: 77: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,858 INFO L290 TraceCheckUtils]: 78: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,858 INFO L290 TraceCheckUtils]: 79: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,858 INFO L290 TraceCheckUtils]: 80: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t7_pc~0); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,859 INFO L290 TraceCheckUtils]: 81: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,859 INFO L290 TraceCheckUtils]: 82: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,860 INFO L290 TraceCheckUtils]: 83: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,860 INFO L290 TraceCheckUtils]: 84: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,860 INFO L290 TraceCheckUtils]: 85: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,861 INFO L290 TraceCheckUtils]: 86: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t8_pc~0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,861 INFO L290 TraceCheckUtils]: 87: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,861 INFO L290 TraceCheckUtils]: 88: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,862 INFO L290 TraceCheckUtils]: 89: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,862 INFO L290 TraceCheckUtils]: 90: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,863 INFO L290 TraceCheckUtils]: 91: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,863 INFO L290 TraceCheckUtils]: 92: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,863 INFO L290 TraceCheckUtils]: 93: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,864 INFO L290 TraceCheckUtils]: 94: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,864 INFO L290 TraceCheckUtils]: 95: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,864 INFO L290 TraceCheckUtils]: 96: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,865 INFO L290 TraceCheckUtils]: 97: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,865 INFO L290 TraceCheckUtils]: 98: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,866 INFO L290 TraceCheckUtils]: 99: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,866 INFO L290 TraceCheckUtils]: 100: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,866 INFO L290 TraceCheckUtils]: 101: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,867 INFO L290 TraceCheckUtils]: 102: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,867 INFO L290 TraceCheckUtils]: 103: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,867 INFO L290 TraceCheckUtils]: 104: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t11_pc~0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,868 INFO L290 TraceCheckUtils]: 105: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,868 INFO L290 TraceCheckUtils]: 106: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,869 INFO L290 TraceCheckUtils]: 107: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,869 INFO L290 TraceCheckUtils]: 108: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,869 INFO L290 TraceCheckUtils]: 109: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,870 INFO L290 TraceCheckUtils]: 110: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,870 INFO L290 TraceCheckUtils]: 111: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,870 INFO L290 TraceCheckUtils]: 112: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,871 INFO L290 TraceCheckUtils]: 113: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,871 INFO L290 TraceCheckUtils]: 114: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,872 INFO L290 TraceCheckUtils]: 115: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,872 INFO L290 TraceCheckUtils]: 116: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t13_pc~0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,872 INFO L290 TraceCheckUtils]: 117: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,873 INFO L290 TraceCheckUtils]: 118: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,873 INFO L290 TraceCheckUtils]: 119: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,873 INFO L290 TraceCheckUtils]: 120: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,874 INFO L290 TraceCheckUtils]: 121: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,874 INFO L290 TraceCheckUtils]: 122: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~M_E~0); {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,875 INFO L290 TraceCheckUtils]: 123: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,875 INFO L290 TraceCheckUtils]: 124: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,875 INFO L290 TraceCheckUtils]: 125: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,876 INFO L290 TraceCheckUtils]: 126: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {115810#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:24:57,876 INFO L290 TraceCheckUtils]: 127: Hoare triple {115810#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {115809#false} is VALID [2022-02-21 04:24:57,876 INFO L290 TraceCheckUtils]: 128: Hoare triple {115809#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,876 INFO L290 TraceCheckUtils]: 129: Hoare triple {115809#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,876 INFO L290 TraceCheckUtils]: 130: Hoare triple {115809#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,877 INFO L290 TraceCheckUtils]: 131: Hoare triple {115809#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,877 INFO L290 TraceCheckUtils]: 132: Hoare triple {115809#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,877 INFO L290 TraceCheckUtils]: 133: Hoare triple {115809#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,877 INFO L290 TraceCheckUtils]: 134: Hoare triple {115809#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,877 INFO L290 TraceCheckUtils]: 135: Hoare triple {115809#false} assume !(1 == ~T13_E~0); {115809#false} is VALID [2022-02-21 04:24:57,877 INFO L290 TraceCheckUtils]: 136: Hoare triple {115809#false} assume 1 == ~E_1~0;~E_1~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,877 INFO L290 TraceCheckUtils]: 137: Hoare triple {115809#false} assume 1 == ~E_2~0;~E_2~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,878 INFO L290 TraceCheckUtils]: 138: Hoare triple {115809#false} assume 1 == ~E_3~0;~E_3~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,878 INFO L290 TraceCheckUtils]: 139: Hoare triple {115809#false} assume 1 == ~E_4~0;~E_4~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,878 INFO L290 TraceCheckUtils]: 140: Hoare triple {115809#false} assume 1 == ~E_5~0;~E_5~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,878 INFO L290 TraceCheckUtils]: 141: Hoare triple {115809#false} assume 1 == ~E_6~0;~E_6~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,878 INFO L290 TraceCheckUtils]: 142: Hoare triple {115809#false} assume 1 == ~E_7~0;~E_7~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,878 INFO L290 TraceCheckUtils]: 143: Hoare triple {115809#false} assume !(1 == ~E_8~0); {115809#false} is VALID [2022-02-21 04:24:57,878 INFO L290 TraceCheckUtils]: 144: Hoare triple {115809#false} assume 1 == ~E_9~0;~E_9~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,879 INFO L290 TraceCheckUtils]: 145: Hoare triple {115809#false} assume 1 == ~E_10~0;~E_10~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,879 INFO L290 TraceCheckUtils]: 146: Hoare triple {115809#false} assume 1 == ~E_11~0;~E_11~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,879 INFO L290 TraceCheckUtils]: 147: Hoare triple {115809#false} assume 1 == ~E_12~0;~E_12~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,879 INFO L290 TraceCheckUtils]: 148: Hoare triple {115809#false} assume 1 == ~E_13~0;~E_13~0 := 2; {115809#false} is VALID [2022-02-21 04:24:57,879 INFO L290 TraceCheckUtils]: 149: Hoare triple {115809#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {115809#false} is VALID [2022-02-21 04:24:57,879 INFO L290 TraceCheckUtils]: 150: Hoare triple {115809#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {115809#false} is VALID [2022-02-21 04:24:57,879 INFO L290 TraceCheckUtils]: 151: Hoare triple {115809#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {115809#false} is VALID [2022-02-21 04:24:57,879 INFO L290 TraceCheckUtils]: 152: Hoare triple {115809#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {115809#false} is VALID [2022-02-21 04:24:57,880 INFO L290 TraceCheckUtils]: 153: Hoare triple {115809#false} assume !(0 == start_simulation_~tmp~3#1); {115809#false} is VALID [2022-02-21 04:24:57,880 INFO L290 TraceCheckUtils]: 154: Hoare triple {115809#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {115809#false} is VALID [2022-02-21 04:24:57,880 INFO L290 TraceCheckUtils]: 155: Hoare triple {115809#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {115809#false} is VALID [2022-02-21 04:24:57,880 INFO L290 TraceCheckUtils]: 156: Hoare triple {115809#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {115809#false} is VALID [2022-02-21 04:24:57,880 INFO L290 TraceCheckUtils]: 157: Hoare triple {115809#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {115809#false} is VALID [2022-02-21 04:24:57,880 INFO L290 TraceCheckUtils]: 158: Hoare triple {115809#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {115809#false} is VALID [2022-02-21 04:24:57,880 INFO L290 TraceCheckUtils]: 159: Hoare triple {115809#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {115809#false} is VALID [2022-02-21 04:24:57,881 INFO L290 TraceCheckUtils]: 160: Hoare triple {115809#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {115809#false} is VALID [2022-02-21 04:24:57,881 INFO L290 TraceCheckUtils]: 161: Hoare triple {115809#false} assume !(0 != start_simulation_~tmp___0~1#1); {115809#false} is VALID [2022-02-21 04:24:57,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:24:57,881 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:24:57,882 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079613908] [2022-02-21 04:24:57,882 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079613908] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:24:57,882 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:24:57,882 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:24:57,882 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351621890] [2022-02-21 04:24:57,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:24:57,883 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:24:57,883 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:24:57,883 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:24:57,883 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:24:57,884 INFO L87 Difference]: Start difference. First operand 3555 states and 5213 transitions. cyclomatic complexity: 1659 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:02,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:02,648 INFO L93 Difference]: Finished difference Result 6962 states and 10199 transitions. [2022-02-21 04:25:02,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:25:02,648 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:02,740 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 159 edges. 159 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:25:02,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:03,798 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-02-21 04:25:04,964 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-02-21 04:25:04,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6962 [2022-02-21 04:25:04,968 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6962 [2022-02-21 04:25:04,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:04,973 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:25:04,973 INFO L681 BuchiCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-02-21 04:25:04,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:05,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6962 to 6962. [2022-02-21 04:25:05,093 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:25:05,102 INFO L82 GeneralOperation]: Start isEquivalent. First operand 6962 states and 10199 transitions. Second operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:05,111 INFO L74 IsIncluded]: Start isIncluded. First operand 6962 states and 10199 transitions. Second operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:05,120 INFO L87 Difference]: Start difference. First operand 6962 states and 10199 transitions. Second operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:06,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:06,210 INFO L93 Difference]: Finished difference Result 6962 states and 10199 transitions. [2022-02-21 04:25:06,210 INFO L276 IsEmpty]: Start isEmpty. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:06,217 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:06,217 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:06,223 INFO L74 IsIncluded]: Start isIncluded. First operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6962 states and 10199 transitions. [2022-02-21 04:25:06,228 INFO L87 Difference]: Start difference. First operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6962 states and 10199 transitions. [2022-02-21 04:25:07,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:25:07,259 INFO L93 Difference]: Finished difference Result 6962 states and 10199 transitions. [2022-02-21 04:25:07,259 INFO L276 IsEmpty]: Start isEmpty. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:07,265 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:25:07,265 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:25:07,265 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:25:07,265 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:25:07,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6962 states, 6962 states have (on average 1.4649525998276358) internal successors, (10199), 6961 states have internal predecessors, (10199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:25:08,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6962 states to 6962 states and 10199 transitions. [2022-02-21 04:25:08,373 INFO L704 BuchiCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-02-21 04:25:08,373 INFO L587 BuchiCegarLoop]: Abstraction has 6962 states and 10199 transitions. [2022-02-21 04:25:08,373 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:25:08,373 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6962 states and 10199 transitions. [2022-02-21 04:25:08,388 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6764 [2022-02-21 04:25:08,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:25:08,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:25:08,390 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:08,390 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:25:08,390 INFO L791 eck$LassoCheckResult]: Stem: 123647#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 123648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 123462#L1855 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 123173#L874 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 123174#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 124382#L881-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 124383#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 123311#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 123312#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 123779#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 123608#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 123609#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 123380#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 123381#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 123790#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 123973#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 124128#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 124166#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 123391#L946-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 123392#L1258 assume !(0 == ~M_E~0); 124606#L1258-2 assume !(0 == ~T1_E~0); 123692#L1263-1 assume !(0 == ~T2_E~0); 123693#L1268-1 assume !(0 == ~T3_E~0); 124009#L1273-1 assume !(0 == ~T4_E~0); 124587#L1278-1 assume !(0 == ~T5_E~0); 124441#L1283-1 assume !(0 == ~T6_E~0); 124442#L1288-1 assume !(0 == ~T7_E~0); 124697#L1293-1 assume !(0 == ~T8_E~0); 124685#L1298-1 assume !(0 == ~T9_E~0); 124600#L1303-1 assume !(0 == ~T10_E~0); 123203#L1308-1 assume !(0 == ~T11_E~0); 123144#L1313-1 assume !(0 == ~T12_E~0); 123145#L1318-1 assume !(0 == ~T13_E~0); 123151#L1323-1 assume !(0 == ~E_1~0); 123152#L1328-1 assume !(0 == ~E_2~0); 123321#L1333-1 assume 0 == ~E_3~0;~E_3~0 := 1; 124306#L1338-1 assume !(0 == ~E_4~0); 124307#L1343-1 assume !(0 == ~E_5~0); 124413#L1348-1 assume !(0 == ~E_6~0); 124726#L1353-1 assume !(0 == ~E_7~0); 124028#L1358-1 assume !(0 == ~E_8~0); 124029#L1363-1 assume !(0 == ~E_9~0); 124325#L1368-1 assume !(0 == ~E_10~0); 122981#L1373-1 assume 0 == ~E_11~0;~E_11~0 := 1; 122982#L1378-1 assume !(0 == ~E_12~0); 123270#L1383-1 assume !(0 == ~E_13~0); 123271#L1388-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124034#L607 assume !(1 == ~m_pc~0); 123340#L607-2 is_master_triggered_~__retres1~0#1 := 0; 123341#L618 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124411#L619 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 123953#L1560 assume !(0 != activate_threads_~tmp~1#1); 123954#L1560-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123164#L626 assume !(1 == ~t1_pc~0); 123165#L626-2 is_transmit1_triggered_~__retres1~1#1 := 0; 123438#L637 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 123439#L638 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123612#L1568 assume !(0 != activate_threads_~tmp___0~0#1); 123064#L1568-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123065#L645 assume 1 == ~t2_pc~0; 123182#L646 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 123138#L656 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 123831#L657 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123832#L1576 assume !(0 != activate_threads_~tmp___1~0#1); 123928#L1576-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123929#L664 assume 1 == ~t3_pc~0; 124722#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 122905#L675 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 122906#L676 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 123571#L1584 assume !(0 != activate_threads_~tmp___2~0#1); 123572#L1584-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 124616#L683 assume !(1 == ~t4_pc~0); 124151#L683-2 is_transmit4_triggered_~__retres1~4#1 := 0; 124102#L694 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 124103#L695 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 124138#L1592 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 124267#L1592-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 123877#L702 assume 1 == ~t5_pc~0; 123878#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 123800#L713 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 124262#L714 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 124574#L1600 assume !(0 != activate_threads_~tmp___4~0#1); 124511#L1600-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122953#L721 assume !(1 == ~t6_pc~0); 122928#L721-2 is_transmit6_triggered_~__retres1~6#1 := 0; 122929#L732 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 123091#L733 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 123580#L1608 assume !(0 != activate_threads_~tmp___5~0#1); 123581#L1608-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 124203#L740 assume 1 == ~t7_pc~0; 123002#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 122814#L751 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 122815#L752 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 122804#L1616 assume !(0 != activate_threads_~tmp___6~0#1); 122805#L1616-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 123516#L759 assume !(1 == ~t8_pc~0); 123517#L759-2 is_transmit8_triggered_~__retres1~8#1 := 0; 123546#L770 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 124260#L771 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 124261#L1624 assume !(0 != activate_threads_~tmp___7~0#1); 124396#L1624-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 124696#L778 assume 1 == ~t9_pc~0; 124571#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 122980#L789 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 122920#L790 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 122848#L1632 assume !(0 != activate_threads_~tmp___8~0#1); 122849#L1632-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 123177#L797 assume !(1 == ~t10_pc~0); 123178#L797-2 is_transmit10_triggered_~__retres1~10#1 := 0; 123298#L808 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 124466#L809 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 123690#L1640 assume !(0 != activate_threads_~tmp___9~0#1); 123691#L1640-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 123991#L816 assume 1 == ~t11_pc~0; 122885#L817 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 122886#L827 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 123651#L828 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 123589#L1648 assume !(0 != activate_threads_~tmp___10~0#1); 123590#L1648-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 124127#L835 assume 1 == ~t12_pc~0; 124005#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 123049#L846 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 123071#L847 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 123213#L1656 assume !(0 != activate_threads_~tmp___11~0#1); 123752#L1656-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 123753#L854 assume !(1 == ~t13_pc~0); 123382#L854-2 is_transmit13_triggered_~__retres1~13#1 := 0; 123383#L865 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 123434#L866 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 123089#L1664 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 123090#L1664-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124506#L1401 assume !(1 == ~M_E~0); 123575#L1401-2 assume !(1 == ~T1_E~0); 123576#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 124514#L1411-1 assume !(1 == ~T3_E~0); 125502#L1416-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 125501#L1421-1 assume !(1 == ~T5_E~0); 125500#L1426-1 assume !(1 == ~T6_E~0); 125499#L1431-1 assume !(1 == ~T7_E~0); 125498#L1436-1 assume !(1 == ~T8_E~0); 122924#L1441-1 assume !(1 == ~T9_E~0); 125497#L1446-1 assume !(1 == ~T10_E~0); 125496#L1451-1 assume !(1 == ~T11_E~0); 125495#L1456-1 assume 1 == ~T12_E~0;~T12_E~0 := 2; 125494#L1461-1 assume !(1 == ~T13_E~0); 125493#L1466-1 assume !(1 == ~E_1~0); 125492#L1471-1 assume !(1 == ~E_2~0); 125491#L1476-1 assume !(1 == ~E_3~0); 125490#L1481-1 assume !(1 == ~E_4~0); 125489#L1486-1 assume !(1 == ~E_5~0); 125488#L1491-1 assume !(1 == ~E_6~0); 125487#L1496-1 assume 1 == ~E_7~0;~E_7~0 := 2; 124066#L1501-1 assume !(1 == ~E_8~0); 123679#L1506-1 assume !(1 == ~E_9~0); 123680#L1511-1 assume !(1 == ~E_10~0); 123635#L1516-1 assume !(1 == ~E_11~0); 123636#L1521-1 assume !(1 == ~E_12~0); 122855#L1526-1 assume !(1 == ~E_13~0); 122856#L1531-1 assume { :end_inline_reset_delta_events } true; 124819#L1892-2 [2022-02-21 04:25:08,391 INFO L793 eck$LassoCheckResult]: Loop: 124819#L1892-2 assume !false; 124813#L1893 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 124812#L1233 assume !false; 124811#L1042 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 124796#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 124781#L1031 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 124779#L1032 eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 124776#L1046 assume !(0 != eval_~tmp~0#1); 124773#L1248 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 124771#L874-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 124769#L1258-3 assume !(0 == ~M_E~0); 124765#L1258-5 assume !(0 == ~T1_E~0); 124766#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 126675#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 126668#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 126661#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 126652#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 126643#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 126635#L1293-3 assume !(0 == ~T8_E~0); 126628#L1298-3 assume !(0 == ~T9_E~0); 126623#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 126558#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 126553#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 126548#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 126543#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 126539#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 126535#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 126531#L1338-3 assume !(0 == ~E_4~0); 126526#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 126523#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 126521#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 126519#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 126517#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 126514#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 126511#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 126509#L1378-3 assume !(0 == ~E_12~0); 126507#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 126504#L1388-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126500#L607-42 assume !(1 == ~m_pc~0); 126497#L607-44 is_master_triggered_~__retres1~0#1 := 0; 126495#L618-14 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126493#L619-14 activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 126491#L1560-42 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 126489#L1560-44 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126488#L626-42 assume !(1 == ~t1_pc~0); 126485#L626-44 is_transmit1_triggered_~__retres1~1#1 := 0; 126482#L637-14 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126480#L638-14 activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 126478#L1568-42 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 126476#L1568-44 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126474#L645-42 assume !(1 == ~t2_pc~0); 126469#L645-44 is_transmit2_triggered_~__retres1~2#1 := 0; 126467#L656-14 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126465#L657-14 activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 126463#L1576-42 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 126461#L1576-44 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126458#L664-42 assume 1 == ~t3_pc~0; 126455#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 126453#L675-14 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126451#L676-14 activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 126449#L1584-42 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 126447#L1584-44 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126446#L683-42 assume 1 == ~t4_pc~0; 126445#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 126418#L694-14 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126324#L695-14 activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126323#L1592-42 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126321#L1592-44 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126319#L702-42 assume 1 == ~t5_pc~0; 126315#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 126313#L713-14 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 126221#L714-14 activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 126220#L1600-42 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 126209#L1600-44 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 126201#L721-42 assume !(1 == ~t6_pc~0); 126193#L721-44 is_transmit6_triggered_~__retres1~6#1 := 0; 126190#L732-14 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 126184#L733-14 activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 126181#L1608-42 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 126177#L1608-44 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 126174#L740-42 assume 1 == ~t7_pc~0; 126169#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 126165#L751-14 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 126160#L752-14 activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 126156#L1616-42 assume !(0 != activate_threads_~tmp___6~0#1); 126150#L1616-44 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 126146#L759-42 assume !(1 == ~t8_pc~0); 126141#L759-44 is_transmit8_triggered_~__retres1~8#1 := 0; 126135#L770-14 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 126129#L771-14 activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 126124#L1624-42 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 126118#L1624-44 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 126113#L778-42 assume !(1 == ~t9_pc~0); 126107#L778-44 is_transmit9_triggered_~__retres1~9#1 := 0; 126103#L789-14 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 126092#L790-14 activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 126086#L1632-42 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 125620#L1632-44 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125618#L797-42 assume !(1 == ~t10_pc~0); 125616#L797-44 is_transmit10_triggered_~__retres1~10#1 := 0; 125613#L808-14 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 125611#L809-14 activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 125608#L1640-42 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 125606#L1640-44 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 125604#L816-42 assume !(1 == ~t11_pc~0); 125601#L816-44 is_transmit11_triggered_~__retres1~11#1 := 0; 125599#L827-14 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 125597#L828-14 activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 125594#L1648-42 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 125592#L1648-44 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 125590#L835-42 assume 1 == ~t12_pc~0; 125587#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 125585#L846-14 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 125583#L847-14 activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 125580#L1656-42 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 125578#L1656-44 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 125576#L854-42 assume !(1 == ~t13_pc~0); 125573#L854-44 is_transmit13_triggered_~__retres1~13#1 := 0; 125571#L865-14 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 125569#L866-14 activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 125566#L1664-42 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 125564#L1664-44 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 125562#L1401-3 assume !(1 == ~M_E~0); 125558#L1401-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 125556#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 125552#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 125549#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 125547#L1421-3 assume !(1 == ~T5_E~0); 125545#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 125543#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 125541#L1436-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 125538#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 125535#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 125533#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 125531#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 125529#L1461-3 assume !(1 == ~T13_E~0); 125527#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 125525#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 125522#L1476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 125520#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 125518#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 125516#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 125514#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 125510#L1501-3 assume !(1 == ~E_8~0); 125508#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 125507#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 125506#L1516-3 assume 1 == ~E_11~0;~E_11~0 := 2; 125505#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 125504#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 125503#L1531-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 125472#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 125466#L1031-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 125464#L1032-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 125463#L1911 assume !(0 == start_simulation_~tmp~3#1); 125461#L1911-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 125460#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 125437#L1031-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 125428#L1032-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 125421#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 124897#L1873 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 124892#L1874 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 124830#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 124819#L1892-2 [2022-02-21 04:25:08,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:08,392 INFO L85 PathProgramCache]: Analyzing trace with hash -1259435077, now seen corresponding path program 1 times [2022-02-21 04:25:08,392 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:08,392 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206585790] [2022-02-21 04:25:08,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:08,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:08,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:08,435 INFO L290 TraceCheckUtils]: 0: Hoare triple {143664#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,435 INFO L290 TraceCheckUtils]: 1: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,436 INFO L290 TraceCheckUtils]: 2: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,436 INFO L290 TraceCheckUtils]: 3: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,436 INFO L290 TraceCheckUtils]: 4: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,437 INFO L290 TraceCheckUtils]: 5: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,437 INFO L290 TraceCheckUtils]: 6: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,438 INFO L290 TraceCheckUtils]: 7: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,438 INFO L290 TraceCheckUtils]: 8: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,438 INFO L290 TraceCheckUtils]: 9: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,439 INFO L290 TraceCheckUtils]: 10: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,439 INFO L290 TraceCheckUtils]: 11: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,439 INFO L290 TraceCheckUtils]: 12: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t8_i~0;~t8_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,440 INFO L290 TraceCheckUtils]: 13: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t9_i~0;~t9_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,440 INFO L290 TraceCheckUtils]: 14: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t10_i~0;~t10_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,441 INFO L290 TraceCheckUtils]: 15: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t11_i~0;~t11_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,441 INFO L290 TraceCheckUtils]: 16: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t12_i~0;~t12_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,441 INFO L290 TraceCheckUtils]: 17: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume 1 == ~t13_i~0;~t13_st~0 := 0; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,442 INFO L290 TraceCheckUtils]: 18: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,442 INFO L290 TraceCheckUtils]: 19: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~M_E~0); {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,442 INFO L290 TraceCheckUtils]: 20: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T1_E~0); {143666#(= ~T2_E~0 ~E_3~0)} is VALID [2022-02-21 04:25:08,443 INFO L290 TraceCheckUtils]: 21: Hoare triple {143666#(= ~T2_E~0 ~E_3~0)} assume !(0 == ~T2_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,443 INFO L290 TraceCheckUtils]: 22: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~T3_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,443 INFO L290 TraceCheckUtils]: 23: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~T4_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,444 INFO L290 TraceCheckUtils]: 24: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~T5_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,444 INFO L290 TraceCheckUtils]: 25: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~T6_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,444 INFO L290 TraceCheckUtils]: 26: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~T7_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,445 INFO L290 TraceCheckUtils]: 27: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~T8_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,445 INFO L290 TraceCheckUtils]: 28: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~T9_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,445 INFO L290 TraceCheckUtils]: 29: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~T10_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,446 INFO L290 TraceCheckUtils]: 30: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~T11_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,446 INFO L290 TraceCheckUtils]: 31: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~T12_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,446 INFO L290 TraceCheckUtils]: 32: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~T13_E~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 33: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~E_1~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 34: Hoare triple {143667#(not (= ~E_3~0 0))} assume !(0 == ~E_2~0); {143667#(not (= ~E_3~0 0))} is VALID [2022-02-21 04:25:08,447 INFO L290 TraceCheckUtils]: 35: Hoare triple {143667#(not (= ~E_3~0 0))} assume 0 == ~E_3~0;~E_3~0 := 1; {143665#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 36: Hoare triple {143665#false} assume !(0 == ~E_4~0); {143665#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 37: Hoare triple {143665#false} assume !(0 == ~E_5~0); {143665#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 38: Hoare triple {143665#false} assume !(0 == ~E_6~0); {143665#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 39: Hoare triple {143665#false} assume !(0 == ~E_7~0); {143665#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 40: Hoare triple {143665#false} assume !(0 == ~E_8~0); {143665#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 41: Hoare triple {143665#false} assume !(0 == ~E_9~0); {143665#false} is VALID [2022-02-21 04:25:08,448 INFO L290 TraceCheckUtils]: 42: Hoare triple {143665#false} assume !(0 == ~E_10~0); {143665#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 43: Hoare triple {143665#false} assume 0 == ~E_11~0;~E_11~0 := 1; {143665#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 44: Hoare triple {143665#false} assume !(0 == ~E_12~0); {143665#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 45: Hoare triple {143665#false} assume !(0 == ~E_13~0); {143665#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 46: Hoare triple {143665#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {143665#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 47: Hoare triple {143665#false} assume !(1 == ~m_pc~0); {143665#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 48: Hoare triple {143665#false} is_master_triggered_~__retres1~0#1 := 0; {143665#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 49: Hoare triple {143665#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {143665#false} is VALID [2022-02-21 04:25:08,449 INFO L290 TraceCheckUtils]: 50: Hoare triple {143665#false} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {143665#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 51: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp~1#1); {143665#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 52: Hoare triple {143665#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {143665#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 53: Hoare triple {143665#false} assume !(1 == ~t1_pc~0); {143665#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 54: Hoare triple {143665#false} is_transmit1_triggered_~__retres1~1#1 := 0; {143665#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 55: Hoare triple {143665#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {143665#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 56: Hoare triple {143665#false} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {143665#false} is VALID [2022-02-21 04:25:08,450 INFO L290 TraceCheckUtils]: 57: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp___0~0#1); {143665#false} is VALID [2022-02-21 04:25:08,451 INFO L290 TraceCheckUtils]: 58: Hoare triple {143665#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {143665#false} is VALID [2022-02-21 04:25:08,451 INFO L290 TraceCheckUtils]: 59: Hoare triple {143665#false} assume 1 == ~t2_pc~0; {143665#false} is VALID [2022-02-21 04:25:08,451 INFO L290 TraceCheckUtils]: 60: Hoare triple {143665#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {143665#false} is VALID [2022-02-21 04:25:08,451 INFO L290 TraceCheckUtils]: 61: Hoare triple {143665#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {143665#false} is VALID [2022-02-21 04:25:08,451 INFO L290 TraceCheckUtils]: 62: Hoare triple {143665#false} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {143665#false} is VALID [2022-02-21 04:25:08,451 INFO L290 TraceCheckUtils]: 63: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp___1~0#1); {143665#false} is VALID [2022-02-21 04:25:08,451 INFO L290 TraceCheckUtils]: 64: Hoare triple {143665#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {143665#false} is VALID [2022-02-21 04:25:08,451 INFO L290 TraceCheckUtils]: 65: Hoare triple {143665#false} assume 1 == ~t3_pc~0; {143665#false} is VALID [2022-02-21 04:25:08,452 INFO L290 TraceCheckUtils]: 66: Hoare triple {143665#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {143665#false} is VALID [2022-02-21 04:25:08,452 INFO L290 TraceCheckUtils]: 67: Hoare triple {143665#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {143665#false} is VALID [2022-02-21 04:25:08,452 INFO L290 TraceCheckUtils]: 68: Hoare triple {143665#false} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {143665#false} is VALID [2022-02-21 04:25:08,452 INFO L290 TraceCheckUtils]: 69: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp___2~0#1); {143665#false} is VALID [2022-02-21 04:25:08,452 INFO L290 TraceCheckUtils]: 70: Hoare triple {143665#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {143665#false} is VALID [2022-02-21 04:25:08,452 INFO L290 TraceCheckUtils]: 71: Hoare triple {143665#false} assume !(1 == ~t4_pc~0); {143665#false} is VALID [2022-02-21 04:25:08,452 INFO L290 TraceCheckUtils]: 72: Hoare triple {143665#false} is_transmit4_triggered_~__retres1~4#1 := 0; {143665#false} is VALID [2022-02-21 04:25:08,453 INFO L290 TraceCheckUtils]: 73: Hoare triple {143665#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {143665#false} is VALID [2022-02-21 04:25:08,453 INFO L290 TraceCheckUtils]: 74: Hoare triple {143665#false} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {143665#false} is VALID [2022-02-21 04:25:08,453 INFO L290 TraceCheckUtils]: 75: Hoare triple {143665#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {143665#false} is VALID [2022-02-21 04:25:08,453 INFO L290 TraceCheckUtils]: 76: Hoare triple {143665#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {143665#false} is VALID [2022-02-21 04:25:08,453 INFO L290 TraceCheckUtils]: 77: Hoare triple {143665#false} assume 1 == ~t5_pc~0; {143665#false} is VALID [2022-02-21 04:25:08,453 INFO L290 TraceCheckUtils]: 78: Hoare triple {143665#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {143665#false} is VALID [2022-02-21 04:25:08,453 INFO L290 TraceCheckUtils]: 79: Hoare triple {143665#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {143665#false} is VALID [2022-02-21 04:25:08,453 INFO L290 TraceCheckUtils]: 80: Hoare triple {143665#false} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {143665#false} is VALID [2022-02-21 04:25:08,454 INFO L290 TraceCheckUtils]: 81: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp___4~0#1); {143665#false} is VALID [2022-02-21 04:25:08,454 INFO L290 TraceCheckUtils]: 82: Hoare triple {143665#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {143665#false} is VALID [2022-02-21 04:25:08,454 INFO L290 TraceCheckUtils]: 83: Hoare triple {143665#false} assume !(1 == ~t6_pc~0); {143665#false} is VALID [2022-02-21 04:25:08,454 INFO L290 TraceCheckUtils]: 84: Hoare triple {143665#false} is_transmit6_triggered_~__retres1~6#1 := 0; {143665#false} is VALID [2022-02-21 04:25:08,454 INFO L290 TraceCheckUtils]: 85: Hoare triple {143665#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {143665#false} is VALID [2022-02-21 04:25:08,454 INFO L290 TraceCheckUtils]: 86: Hoare triple {143665#false} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {143665#false} is VALID [2022-02-21 04:25:08,454 INFO L290 TraceCheckUtils]: 87: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp___5~0#1); {143665#false} is VALID [2022-02-21 04:25:08,455 INFO L290 TraceCheckUtils]: 88: Hoare triple {143665#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {143665#false} is VALID [2022-02-21 04:25:08,455 INFO L290 TraceCheckUtils]: 89: Hoare triple {143665#false} assume 1 == ~t7_pc~0; {143665#false} is VALID [2022-02-21 04:25:08,455 INFO L290 TraceCheckUtils]: 90: Hoare triple {143665#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {143665#false} is VALID [2022-02-21 04:25:08,455 INFO L290 TraceCheckUtils]: 91: Hoare triple {143665#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {143665#false} is VALID [2022-02-21 04:25:08,455 INFO L290 TraceCheckUtils]: 92: Hoare triple {143665#false} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {143665#false} is VALID [2022-02-21 04:25:08,455 INFO L290 TraceCheckUtils]: 93: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp___6~0#1); {143665#false} is VALID [2022-02-21 04:25:08,455 INFO L290 TraceCheckUtils]: 94: Hoare triple {143665#false} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {143665#false} is VALID [2022-02-21 04:25:08,455 INFO L290 TraceCheckUtils]: 95: Hoare triple {143665#false} assume !(1 == ~t8_pc~0); {143665#false} is VALID [2022-02-21 04:25:08,456 INFO L290 TraceCheckUtils]: 96: Hoare triple {143665#false} is_transmit8_triggered_~__retres1~8#1 := 0; {143665#false} is VALID [2022-02-21 04:25:08,456 INFO L290 TraceCheckUtils]: 97: Hoare triple {143665#false} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {143665#false} is VALID [2022-02-21 04:25:08,456 INFO L290 TraceCheckUtils]: 98: Hoare triple {143665#false} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {143665#false} is VALID [2022-02-21 04:25:08,456 INFO L290 TraceCheckUtils]: 99: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp___7~0#1); {143665#false} is VALID [2022-02-21 04:25:08,456 INFO L290 TraceCheckUtils]: 100: Hoare triple {143665#false} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {143665#false} is VALID [2022-02-21 04:25:08,456 INFO L290 TraceCheckUtils]: 101: Hoare triple {143665#false} assume 1 == ~t9_pc~0; {143665#false} is VALID [2022-02-21 04:25:08,456 INFO L290 TraceCheckUtils]: 102: Hoare triple {143665#false} assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; {143665#false} is VALID [2022-02-21 04:25:08,457 INFO L290 TraceCheckUtils]: 103: Hoare triple {143665#false} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {143665#false} is VALID [2022-02-21 04:25:08,457 INFO L290 TraceCheckUtils]: 104: Hoare triple {143665#false} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {143665#false} is VALID [2022-02-21 04:25:08,457 INFO L290 TraceCheckUtils]: 105: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp___8~0#1); {143665#false} is VALID [2022-02-21 04:25:08,457 INFO L290 TraceCheckUtils]: 106: Hoare triple {143665#false} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {143665#false} is VALID [2022-02-21 04:25:08,457 INFO L290 TraceCheckUtils]: 107: Hoare triple {143665#false} assume !(1 == ~t10_pc~0); {143665#false} is VALID [2022-02-21 04:25:08,457 INFO L290 TraceCheckUtils]: 108: Hoare triple {143665#false} is_transmit10_triggered_~__retres1~10#1 := 0; {143665#false} is VALID [2022-02-21 04:25:08,457 INFO L290 TraceCheckUtils]: 109: Hoare triple {143665#false} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {143665#false} is VALID [2022-02-21 04:25:08,457 INFO L290 TraceCheckUtils]: 110: Hoare triple {143665#false} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {143665#false} is VALID [2022-02-21 04:25:08,458 INFO L290 TraceCheckUtils]: 111: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp___9~0#1); {143665#false} is VALID [2022-02-21 04:25:08,458 INFO L290 TraceCheckUtils]: 112: Hoare triple {143665#false} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {143665#false} is VALID [2022-02-21 04:25:08,458 INFO L290 TraceCheckUtils]: 113: Hoare triple {143665#false} assume 1 == ~t11_pc~0; {143665#false} is VALID [2022-02-21 04:25:08,458 INFO L290 TraceCheckUtils]: 114: Hoare triple {143665#false} assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; {143665#false} is VALID [2022-02-21 04:25:08,458 INFO L290 TraceCheckUtils]: 115: Hoare triple {143665#false} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {143665#false} is VALID [2022-02-21 04:25:08,458 INFO L290 TraceCheckUtils]: 116: Hoare triple {143665#false} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {143665#false} is VALID [2022-02-21 04:25:08,458 INFO L290 TraceCheckUtils]: 117: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp___10~0#1); {143665#false} is VALID [2022-02-21 04:25:08,459 INFO L290 TraceCheckUtils]: 118: Hoare triple {143665#false} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {143665#false} is VALID [2022-02-21 04:25:08,459 INFO L290 TraceCheckUtils]: 119: Hoare triple {143665#false} assume 1 == ~t12_pc~0; {143665#false} is VALID [2022-02-21 04:25:08,459 INFO L290 TraceCheckUtils]: 120: Hoare triple {143665#false} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {143665#false} is VALID [2022-02-21 04:25:08,459 INFO L290 TraceCheckUtils]: 121: Hoare triple {143665#false} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {143665#false} is VALID [2022-02-21 04:25:08,459 INFO L290 TraceCheckUtils]: 122: Hoare triple {143665#false} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {143665#false} is VALID [2022-02-21 04:25:08,459 INFO L290 TraceCheckUtils]: 123: Hoare triple {143665#false} assume !(0 != activate_threads_~tmp___11~0#1); {143665#false} is VALID [2022-02-21 04:25:08,459 INFO L290 TraceCheckUtils]: 124: Hoare triple {143665#false} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {143665#false} is VALID [2022-02-21 04:25:08,460 INFO L290 TraceCheckUtils]: 125: Hoare triple {143665#false} assume !(1 == ~t13_pc~0); {143665#false} is VALID [2022-02-21 04:25:08,460 INFO L290 TraceCheckUtils]: 126: Hoare triple {143665#false} is_transmit13_triggered_~__retres1~13#1 := 0; {143665#false} is VALID [2022-02-21 04:25:08,460 INFO L290 TraceCheckUtils]: 127: Hoare triple {143665#false} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {143665#false} is VALID [2022-02-21 04:25:08,460 INFO L290 TraceCheckUtils]: 128: Hoare triple {143665#false} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {143665#false} is VALID [2022-02-21 04:25:08,460 INFO L290 TraceCheckUtils]: 129: Hoare triple {143665#false} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {143665#false} is VALID [2022-02-21 04:25:08,460 INFO L290 TraceCheckUtils]: 130: Hoare triple {143665#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {143665#false} is VALID [2022-02-21 04:25:08,460 INFO L290 TraceCheckUtils]: 131: Hoare triple {143665#false} assume !(1 == ~M_E~0); {143665#false} is VALID [2022-02-21 04:25:08,460 INFO L290 TraceCheckUtils]: 132: Hoare triple {143665#false} assume !(1 == ~T1_E~0); {143665#false} is VALID [2022-02-21 04:25:08,461 INFO L290 TraceCheckUtils]: 133: Hoare triple {143665#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {143665#false} is VALID [2022-02-21 04:25:08,461 INFO L290 TraceCheckUtils]: 134: Hoare triple {143665#false} assume !(1 == ~T3_E~0); {143665#false} is VALID [2022-02-21 04:25:08,461 INFO L290 TraceCheckUtils]: 135: Hoare triple {143665#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {143665#false} is VALID [2022-02-21 04:25:08,461 INFO L290 TraceCheckUtils]: 136: Hoare triple {143665#false} assume !(1 == ~T5_E~0); {143665#false} is VALID [2022-02-21 04:25:08,461 INFO L290 TraceCheckUtils]: 137: Hoare triple {143665#false} assume !(1 == ~T6_E~0); {143665#false} is VALID [2022-02-21 04:25:08,461 INFO L290 TraceCheckUtils]: 138: Hoare triple {143665#false} assume !(1 == ~T7_E~0); {143665#false} is VALID [2022-02-21 04:25:08,461 INFO L290 TraceCheckUtils]: 139: Hoare triple {143665#false} assume !(1 == ~T8_E~0); {143665#false} is VALID [2022-02-21 04:25:08,462 INFO L290 TraceCheckUtils]: 140: Hoare triple {143665#false} assume !(1 == ~T9_E~0); {143665#false} is VALID [2022-02-21 04:25:08,462 INFO L290 TraceCheckUtils]: 141: Hoare triple {143665#false} assume !(1 == ~T10_E~0); {143665#false} is VALID [2022-02-21 04:25:08,462 INFO L290 TraceCheckUtils]: 142: Hoare triple {143665#false} assume !(1 == ~T11_E~0); {143665#false} is VALID [2022-02-21 04:25:08,462 INFO L290 TraceCheckUtils]: 143: Hoare triple {143665#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {143665#false} is VALID [2022-02-21 04:25:08,462 INFO L290 TraceCheckUtils]: 144: Hoare triple {143665#false} assume !(1 == ~T13_E~0); {143665#false} is VALID [2022-02-21 04:25:08,462 INFO L290 TraceCheckUtils]: 145: Hoare triple {143665#false} assume !(1 == ~E_1~0); {143665#false} is VALID [2022-02-21 04:25:08,462 INFO L290 TraceCheckUtils]: 146: Hoare triple {143665#false} assume !(1 == ~E_2~0); {143665#false} is VALID [2022-02-21 04:25:08,462 INFO L290 TraceCheckUtils]: 147: Hoare triple {143665#false} assume !(1 == ~E_3~0); {143665#false} is VALID [2022-02-21 04:25:08,463 INFO L290 TraceCheckUtils]: 148: Hoare triple {143665#false} assume !(1 == ~E_4~0); {143665#false} is VALID [2022-02-21 04:25:08,463 INFO L290 TraceCheckUtils]: 149: Hoare triple {143665#false} assume !(1 == ~E_5~0); {143665#false} is VALID [2022-02-21 04:25:08,463 INFO L290 TraceCheckUtils]: 150: Hoare triple {143665#false} assume !(1 == ~E_6~0); {143665#false} is VALID [2022-02-21 04:25:08,463 INFO L290 TraceCheckUtils]: 151: Hoare triple {143665#false} assume 1 == ~E_7~0;~E_7~0 := 2; {143665#false} is VALID [2022-02-21 04:25:08,463 INFO L290 TraceCheckUtils]: 152: Hoare triple {143665#false} assume !(1 == ~E_8~0); {143665#false} is VALID [2022-02-21 04:25:08,463 INFO L290 TraceCheckUtils]: 153: Hoare triple {143665#false} assume !(1 == ~E_9~0); {143665#false} is VALID [2022-02-21 04:25:08,463 INFO L290 TraceCheckUtils]: 154: Hoare triple {143665#false} assume !(1 == ~E_10~0); {143665#false} is VALID [2022-02-21 04:25:08,464 INFO L290 TraceCheckUtils]: 155: Hoare triple {143665#false} assume !(1 == ~E_11~0); {143665#false} is VALID [2022-02-21 04:25:08,464 INFO L290 TraceCheckUtils]: 156: Hoare triple {143665#false} assume !(1 == ~E_12~0); {143665#false} is VALID [2022-02-21 04:25:08,464 INFO L290 TraceCheckUtils]: 157: Hoare triple {143665#false} assume !(1 == ~E_13~0); {143665#false} is VALID [2022-02-21 04:25:08,464 INFO L290 TraceCheckUtils]: 158: Hoare triple {143665#false} assume { :end_inline_reset_delta_events } true; {143665#false} is VALID [2022-02-21 04:25:08,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:08,465 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:08,465 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [206585790] [2022-02-21 04:25:08,465 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [206585790] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:08,465 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:08,465 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:08,465 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121296241] [2022-02-21 04:25:08,466 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:08,466 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:25:08,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:25:08,466 INFO L85 PathProgramCache]: Analyzing trace with hash 1607241172, now seen corresponding path program 1 times [2022-02-21 04:25:08,467 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:25:08,467 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100780818] [2022-02-21 04:25:08,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:25:08,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:25:08,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:25:08,501 INFO L290 TraceCheckUtils]: 0: Hoare triple {143668#true} assume !false; {143668#true} is VALID [2022-02-21 04:25:08,501 INFO L290 TraceCheckUtils]: 1: Hoare triple {143668#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {143668#true} is VALID [2022-02-21 04:25:08,501 INFO L290 TraceCheckUtils]: 2: Hoare triple {143668#true} assume !false; {143668#true} is VALID [2022-02-21 04:25:08,501 INFO L290 TraceCheckUtils]: 3: Hoare triple {143668#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {143668#true} is VALID [2022-02-21 04:25:08,502 INFO L290 TraceCheckUtils]: 4: Hoare triple {143668#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {143668#true} is VALID [2022-02-21 04:25:08,502 INFO L290 TraceCheckUtils]: 5: Hoare triple {143668#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {143668#true} is VALID [2022-02-21 04:25:08,502 INFO L290 TraceCheckUtils]: 6: Hoare triple {143668#true} eval_#t~ret4#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; {143668#true} is VALID [2022-02-21 04:25:08,502 INFO L290 TraceCheckUtils]: 7: Hoare triple {143668#true} assume !(0 != eval_~tmp~0#1); {143668#true} is VALID [2022-02-21 04:25:08,502 INFO L290 TraceCheckUtils]: 8: Hoare triple {143668#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {143668#true} is VALID [2022-02-21 04:25:08,502 INFO L290 TraceCheckUtils]: 9: Hoare triple {143668#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {143668#true} is VALID [2022-02-21 04:25:08,502 INFO L290 TraceCheckUtils]: 10: Hoare triple {143668#true} assume !(0 == ~M_E~0); {143668#true} is VALID [2022-02-21 04:25:08,503 INFO L290 TraceCheckUtils]: 11: Hoare triple {143668#true} assume !(0 == ~T1_E~0); {143668#true} is VALID [2022-02-21 04:25:08,503 INFO L290 TraceCheckUtils]: 12: Hoare triple {143668#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {143668#true} is VALID [2022-02-21 04:25:08,503 INFO L290 TraceCheckUtils]: 13: Hoare triple {143668#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {143668#true} is VALID [2022-02-21 04:25:08,503 INFO L290 TraceCheckUtils]: 14: Hoare triple {143668#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {143668#true} is VALID [2022-02-21 04:25:08,503 INFO L290 TraceCheckUtils]: 15: Hoare triple {143668#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,504 INFO L290 TraceCheckUtils]: 16: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,504 INFO L290 TraceCheckUtils]: 17: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,505 INFO L290 TraceCheckUtils]: 18: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T8_E~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,505 INFO L290 TraceCheckUtils]: 19: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~T9_E~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,505 INFO L290 TraceCheckUtils]: 20: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T10_E~0;~T10_E~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,506 INFO L290 TraceCheckUtils]: 21: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T11_E~0;~T11_E~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,506 INFO L290 TraceCheckUtils]: 22: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T12_E~0;~T12_E~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,506 INFO L290 TraceCheckUtils]: 23: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~T13_E~0;~T13_E~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,507 INFO L290 TraceCheckUtils]: 24: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,507 INFO L290 TraceCheckUtils]: 25: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,508 INFO L290 TraceCheckUtils]: 26: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,508 INFO L290 TraceCheckUtils]: 27: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_4~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,508 INFO L290 TraceCheckUtils]: 28: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,509 INFO L290 TraceCheckUtils]: 29: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,509 INFO L290 TraceCheckUtils]: 30: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,509 INFO L290 TraceCheckUtils]: 31: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_8~0;~E_8~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,510 INFO L290 TraceCheckUtils]: 32: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_9~0;~E_9~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,510 INFO L290 TraceCheckUtils]: 33: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_10~0;~E_10~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,511 INFO L290 TraceCheckUtils]: 34: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_11~0;~E_11~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,511 INFO L290 TraceCheckUtils]: 35: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 == ~E_12~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,511 INFO L290 TraceCheckUtils]: 36: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 == ~E_13~0;~E_13~0 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,512 INFO L290 TraceCheckUtils]: 37: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,512 INFO L290 TraceCheckUtils]: 38: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~m_pc~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,512 INFO L290 TraceCheckUtils]: 39: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,513 INFO L290 TraceCheckUtils]: 40: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,513 INFO L290 TraceCheckUtils]: 41: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret19#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,514 INFO L290 TraceCheckUtils]: 42: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,514 INFO L290 TraceCheckUtils]: 43: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,514 INFO L290 TraceCheckUtils]: 44: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t1_pc~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,515 INFO L290 TraceCheckUtils]: 45: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,515 INFO L290 TraceCheckUtils]: 46: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,515 INFO L290 TraceCheckUtils]: 47: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,516 INFO L290 TraceCheckUtils]: 48: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,516 INFO L290 TraceCheckUtils]: 49: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,517 INFO L290 TraceCheckUtils]: 50: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t2_pc~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,517 INFO L290 TraceCheckUtils]: 51: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,517 INFO L290 TraceCheckUtils]: 52: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,518 INFO L290 TraceCheckUtils]: 53: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,518 INFO L290 TraceCheckUtils]: 54: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,518 INFO L290 TraceCheckUtils]: 55: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,519 INFO L290 TraceCheckUtils]: 56: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t3_pc~0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,519 INFO L290 TraceCheckUtils]: 57: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,520 INFO L290 TraceCheckUtils]: 58: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,520 INFO L290 TraceCheckUtils]: 59: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,520 INFO L290 TraceCheckUtils]: 60: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,521 INFO L290 TraceCheckUtils]: 61: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,521 INFO L290 TraceCheckUtils]: 62: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t4_pc~0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,521 INFO L290 TraceCheckUtils]: 63: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,522 INFO L290 TraceCheckUtils]: 64: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,522 INFO L290 TraceCheckUtils]: 65: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,523 INFO L290 TraceCheckUtils]: 66: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,523 INFO L290 TraceCheckUtils]: 67: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,523 INFO L290 TraceCheckUtils]: 68: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t5_pc~0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,524 INFO L290 TraceCheckUtils]: 69: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,524 INFO L290 TraceCheckUtils]: 70: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,524 INFO L290 TraceCheckUtils]: 71: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,525 INFO L290 TraceCheckUtils]: 72: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,525 INFO L290 TraceCheckUtils]: 73: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,525 INFO L290 TraceCheckUtils]: 74: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t6_pc~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,526 INFO L290 TraceCheckUtils]: 75: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,526 INFO L290 TraceCheckUtils]: 76: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,526 INFO L290 TraceCheckUtils]: 77: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,527 INFO L290 TraceCheckUtils]: 78: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,527 INFO L290 TraceCheckUtils]: 79: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,527 INFO L290 TraceCheckUtils]: 80: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t7_pc~0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,528 INFO L290 TraceCheckUtils]: 81: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,528 INFO L290 TraceCheckUtils]: 82: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,528 INFO L290 TraceCheckUtils]: 83: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,529 INFO L290 TraceCheckUtils]: 84: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(0 != activate_threads_~tmp___6~0#1); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,529 INFO L290 TraceCheckUtils]: 85: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,529 INFO L290 TraceCheckUtils]: 86: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t8_pc~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,530 INFO L290 TraceCheckUtils]: 87: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_~__retres1~8#1 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,530 INFO L290 TraceCheckUtils]: 88: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,531 INFO L290 TraceCheckUtils]: 89: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,531 INFO L290 TraceCheckUtils]: 90: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,531 INFO L290 TraceCheckUtils]: 91: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,531 INFO L290 TraceCheckUtils]: 92: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t9_pc~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,532 INFO L290 TraceCheckUtils]: 93: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_~__retres1~9#1 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,532 INFO L290 TraceCheckUtils]: 94: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,532 INFO L290 TraceCheckUtils]: 95: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,533 INFO L290 TraceCheckUtils]: 96: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,533 INFO L290 TraceCheckUtils]: 97: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,533 INFO L290 TraceCheckUtils]: 98: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t10_pc~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,534 INFO L290 TraceCheckUtils]: 99: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_~__retres1~10#1 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,534 INFO L290 TraceCheckUtils]: 100: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,535 INFO L290 TraceCheckUtils]: 101: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,535 INFO L290 TraceCheckUtils]: 102: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,535 INFO L290 TraceCheckUtils]: 103: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,535 INFO L290 TraceCheckUtils]: 104: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t11_pc~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,536 INFO L290 TraceCheckUtils]: 105: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_~__retres1~11#1 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,536 INFO L290 TraceCheckUtils]: 106: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,536 INFO L290 TraceCheckUtils]: 107: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,537 INFO L290 TraceCheckUtils]: 108: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,537 INFO L290 TraceCheckUtils]: 109: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,537 INFO L290 TraceCheckUtils]: 110: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~t12_pc~0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,538 INFO L290 TraceCheckUtils]: 111: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,538 INFO L290 TraceCheckUtils]: 112: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,538 INFO L290 TraceCheckUtils]: 113: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,538 INFO L290 TraceCheckUtils]: 114: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,539 INFO L290 TraceCheckUtils]: 115: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,539 INFO L290 TraceCheckUtils]: 116: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~t13_pc~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,539 INFO L290 TraceCheckUtils]: 117: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_~__retres1~13#1 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,540 INFO L290 TraceCheckUtils]: 118: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,540 INFO L290 TraceCheckUtils]: 119: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,540 INFO L290 TraceCheckUtils]: 120: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,541 INFO L290 TraceCheckUtils]: 121: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,541 INFO L290 TraceCheckUtils]: 122: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~M_E~0); {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,541 INFO L290 TraceCheckUtils]: 123: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,541 INFO L290 TraceCheckUtils]: 124: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,542 INFO L290 TraceCheckUtils]: 125: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,542 INFO L290 TraceCheckUtils]: 126: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {143670#(= (+ (- 1) ~T5_E~0) 0)} is VALID [2022-02-21 04:25:08,542 INFO L290 TraceCheckUtils]: 127: Hoare triple {143670#(= (+ (- 1) ~T5_E~0) 0)} assume !(1 == ~T5_E~0); {143669#false} is VALID [2022-02-21 04:25:08,542 INFO L290 TraceCheckUtils]: 128: Hoare triple {143669#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,542 INFO L290 TraceCheckUtils]: 129: Hoare triple {143669#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,543 INFO L290 TraceCheckUtils]: 130: Hoare triple {143669#false} assume 1 == ~T8_E~0;~T8_E~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,543 INFO L290 TraceCheckUtils]: 131: Hoare triple {143669#false} assume 1 == ~T9_E~0;~T9_E~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,543 INFO L290 TraceCheckUtils]: 132: Hoare triple {143669#false} assume 1 == ~T10_E~0;~T10_E~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,543 INFO L290 TraceCheckUtils]: 133: Hoare triple {143669#false} assume 1 == ~T11_E~0;~T11_E~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,543 INFO L290 TraceCheckUtils]: 134: Hoare triple {143669#false} assume 1 == ~T12_E~0;~T12_E~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,543 INFO L290 TraceCheckUtils]: 135: Hoare triple {143669#false} assume !(1 == ~T13_E~0); {143669#false} is VALID [2022-02-21 04:25:08,543 INFO L290 TraceCheckUtils]: 136: Hoare triple {143669#false} assume 1 == ~E_1~0;~E_1~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,543 INFO L290 TraceCheckUtils]: 137: Hoare triple {143669#false} assume 1 == ~E_2~0;~E_2~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,543 INFO L290 TraceCheckUtils]: 138: Hoare triple {143669#false} assume 1 == ~E_3~0;~E_3~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,544 INFO L290 TraceCheckUtils]: 139: Hoare triple {143669#false} assume 1 == ~E_4~0;~E_4~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,544 INFO L290 TraceCheckUtils]: 140: Hoare triple {143669#false} assume 1 == ~E_5~0;~E_5~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,544 INFO L290 TraceCheckUtils]: 141: Hoare triple {143669#false} assume 1 == ~E_6~0;~E_6~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,544 INFO L290 TraceCheckUtils]: 142: Hoare triple {143669#false} assume 1 == ~E_7~0;~E_7~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,544 INFO L290 TraceCheckUtils]: 143: Hoare triple {143669#false} assume !(1 == ~E_8~0); {143669#false} is VALID [2022-02-21 04:25:08,544 INFO L290 TraceCheckUtils]: 144: Hoare triple {143669#false} assume 1 == ~E_9~0;~E_9~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,544 INFO L290 TraceCheckUtils]: 145: Hoare triple {143669#false} assume 1 == ~E_10~0;~E_10~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,545 INFO L290 TraceCheckUtils]: 146: Hoare triple {143669#false} assume 1 == ~E_11~0;~E_11~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,545 INFO L290 TraceCheckUtils]: 147: Hoare triple {143669#false} assume 1 == ~E_12~0;~E_12~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,545 INFO L290 TraceCheckUtils]: 148: Hoare triple {143669#false} assume 1 == ~E_13~0;~E_13~0 := 2; {143669#false} is VALID [2022-02-21 04:25:08,545 INFO L290 TraceCheckUtils]: 149: Hoare triple {143669#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {143669#false} is VALID [2022-02-21 04:25:08,545 INFO L290 TraceCheckUtils]: 150: Hoare triple {143669#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {143669#false} is VALID [2022-02-21 04:25:08,545 INFO L290 TraceCheckUtils]: 151: Hoare triple {143669#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {143669#false} is VALID [2022-02-21 04:25:08,545 INFO L290 TraceCheckUtils]: 152: Hoare triple {143669#false} start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; {143669#false} is VALID [2022-02-21 04:25:08,546 INFO L290 TraceCheckUtils]: 153: Hoare triple {143669#false} assume !(0 == start_simulation_~tmp~3#1); {143669#false} is VALID [2022-02-21 04:25:08,546 INFO L290 TraceCheckUtils]: 154: Hoare triple {143669#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; {143669#false} is VALID [2022-02-21 04:25:08,546 INFO L290 TraceCheckUtils]: 155: Hoare triple {143669#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; {143669#false} is VALID [2022-02-21 04:25:08,546 INFO L290 TraceCheckUtils]: 156: Hoare triple {143669#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; {143669#false} is VALID [2022-02-21 04:25:08,546 INFO L290 TraceCheckUtils]: 157: Hoare triple {143669#false} stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; {143669#false} is VALID [2022-02-21 04:25:08,546 INFO L290 TraceCheckUtils]: 158: Hoare triple {143669#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {143669#false} is VALID [2022-02-21 04:25:08,546 INFO L290 TraceCheckUtils]: 159: Hoare triple {143669#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {143669#false} is VALID [2022-02-21 04:25:08,547 INFO L290 TraceCheckUtils]: 160: Hoare triple {143669#false} start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; {143669#false} is VALID [2022-02-21 04:25:08,547 INFO L290 TraceCheckUtils]: 161: Hoare triple {143669#false} assume !(0 != start_simulation_~tmp___0~1#1); {143669#false} is VALID [2022-02-21 04:25:08,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:25:08,547 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:25:08,548 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100780818] [2022-02-21 04:25:08,548 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100780818] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:25:08,548 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:25:08,548 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:25:08,548 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [393607227] [2022-02-21 04:25:08,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:25:08,549 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:25:08,549 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:25:08,549 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:25:08,549 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:25:08,550 INFO L87 Difference]: Start difference. First operand 6962 states and 10199 transitions. cyclomatic complexity: 3239 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)